S: Maintained
T: git git://git.denx.de/u-boot-samsung.git
F: arch/arm/cpu/arm920t/s3c24x0/
-F: arch/arm/cpu/armv7/exynos/
-F: arch/arm/cpu/armv7/s5pc1xx/
+F: arch/arm/mach-exynos/
+F: arch/arm/mach-s5pc1xx/
F: arch/arm/cpu/armv7/s5p-common/
-F: arch/arm/include/asm/arch-exynos/
F: arch/arm/include/asm/arch-s3c24x0/
-F: arch/arm/include/asm/arch-s5pc1xx/
ARM STM SPEAR
M: Vipin Kumar <vipin.kumar@st.com>
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory.
+ CONFIG_SYS_FSL_HAS_DP_DDR
+ Defines the SoC has DP-DDR used for DPAA.
+
CONFIG_SYS_FSL_SEC_BE
Defines the SEC controller register space as Big Endian
Enables the driver for SPI controller on SuperH. Currently
only SH7757 is supported.
- CONFIG_SPI_X
-
- Enables extended (16-bit) SPI EEPROM addressing.
- (symmetrical to CONFIG_I2C_X)
-
CONFIG_SOFT_SPI
Enables a software (bit-bang) SPI driver rather than
bool "Support Versatile Express Juno Development Platform"
select ARM64
-config TARGET_LS2085A_EMU
- bool "Support ls2085a_emu"
+config TARGET_LS2080A_EMU
+ bool "Support ls2080a_emu"
select ARM64
select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS2080A_EMU platform
+ The LS2080A Development System (EMULATOR) is a pre silicon
+ development platform that supports the QorIQ LS2080A
+ Layerscape Architecture processor.
-config TARGET_LS2085A_SIMU
- bool "Support ls2085a_simu"
+config TARGET_LS2080A_SIMU
+ bool "Support ls2080a_simu"
select ARM64
select ARMV8_MULTIENTRY
+ help
+ Support for Freescale LS2080A_SIMU platform
+ The LS2080A Development System (QDS) is a pre silicon
+ development platform that supports the QorIQ LS2080A
+ Layerscape Architecture processor.
-config TARGET_LS2085AQDS
- bool "Support ls2085aqds"
+config TARGET_LS2080AQDS
+ bool "Support ls2080aqds"
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
- Support for Freescale LS2085AQDS platform
- The LS2085A Development System (QDS) is a high-performance
- development platform that supports the QorIQ LS2085A
+ Support for Freescale LS2080AQDS platform
+ The LS2080A Development System (QDS) is a high-performance
+ development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
-config TARGET_LS2085ARDB
- bool "Support ls2085ardb"
+config TARGET_LS2080ARDB
+ bool "Support ls2080ardb"
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
- Support for Freescale LS2085ARDB platform.
- The LS2085A Reference design board (RDB) is a high-performance
- development platform that supports the QorIQ LS2085A
+ Support for Freescale LS2080ARDB platform.
+ The LS2080A Reference design board (RDB) is a high-performance
+ development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
config TARGET_HIKEY
select CPU_V7
select SUPPORT_SPL
+config TARGET_LS1043AQDS
+ bool "Support ls1043aqds"
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
+ help
+ Support for Freescale LS1043AQDS platform.
+
config TARGET_LS1043ARDB
bool "Support ls1043ardb"
select ARM64
source "arch/arm/mach-rockchip/Kconfig"
-source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
+source "arch/arm/mach-s5pc1xx/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
source "board/creative/xfi3/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
-source "board/freescale/ls2085a/Kconfig"
-source "board/freescale/ls2085aqds/Kconfig"
-source "board/freescale/ls2085ardb/Kconfig"
+source "board/freescale/ls2080a/Kconfig"
+source "board/freescale/ls2080aqds/Kconfig"
+source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
+source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/mx23evk/Kconfig"
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
+machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_TEGRA) += tegra
obj-$(CONFIG_OMAP44XX) += omap4/
obj-$(CONFIG_OMAP54XX) += omap5/
obj-$(CONFIG_RMOBILE) += rmobile/
-obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_VF610) += vf610/
set_uart_mux_conf();
setup_clocks_for_console();
uart_soft_reset();
-#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
- /* TODO: This does not work, gd is not available yet */
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init();
- gd->have_console = 1;
-#endif
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
/* Enable RTC32K clock */
rtc32k_enable();
*/
}
}
+
+void arch_preboot_os(void)
+{
+ unsigned long ctrl;
+
+ /* Disable PL1 Physical Timer */
+ asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
+ ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+ asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
+}
int timer_init(void)
{
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
- unsigned long ctrl, val, freq;
+ unsigned long ctrl, freq;
+ unsigned long long val;
/* Enable System Counter */
writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
+++ /dev/null
-if ARCH_S5PC1XX
-
-choice
- prompt "S5PC1XX board select"
- optional
-
-config TARGET_S5P_GONI
- bool "S5P Goni board"
- select OF_CONTROL
-
-config TARGET_SMDKC100
- bool "Support smdkc100 board"
- select OF_CONTROL
-
-endchoice
-
-config SYS_SOC
- default "s5pc1xx"
-
-source "board/samsung/goni/Kconfig"
-source "board/samsung/smdkc100/Kconfig"
-
-endif
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cache.o
-obj-y += reset.o
-
-obj-y += clock.o
+++ /dev/null
-/*
- * Copyright (C) 2014 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Robert Baldyga <r.baldyga@samsung.com>
- *
- * based on arch/arm/cpu/armv7/omap3/cache.S
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- dcache_enable();
-}
-
-void disable_caches(void)
-{
- dcache_disable();
-}
-#endif
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-void v7_outer_cache_enable(void)
-{
- __asm(
- "push {r0, r1, r2, lr}\n\t"
- "mrc 15, 0, r3, cr1, cr0, 1\n\t"
- "orr r3, r3, #2\n\t"
- "mcr 15, 0, r3, cr1, cr0, 1\n\t"
- "pop {r1, r2, r3, pc}"
- );
-}
-
-void v7_outer_cache_disable(void)
-{
- __asm(
- "push {r0, r1, r2, lr}\n\t"
- "mrc 15, 0, r3, cr1, cr0, 1\n\t"
- "bic r3, r3, #2\n\t"
- "mcr 15, 0, r3, cr1, cr0, 1\n\t"
- "pop {r1, r2, r3, pc}"
- );
-}
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-
-#define CLK_M 0
-#define CLK_D 1
-#define CLK_P 2
-
-#ifndef CONFIG_SYS_CLK_FREQ_C100
-#define CONFIG_SYS_CLK_FREQ_C100 12000000
-#endif
-#ifndef CONFIG_SYS_CLK_FREQ_C110
-#define CONFIG_SYS_CLK_FREQ_C110 24000000
-#endif
-
-/* s5pc110: return pll clock frequency */
-static unsigned long s5pc100_get_pll_clk(int pllreg)
-{
- struct s5pc100_clock *clk =
- (struct s5pc100_clock *)samsung_get_base_clock();
- unsigned long r, m, p, s, mask, fout;
- unsigned int freq;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con);
- break;
- case MPLL:
- r = readl(&clk->mpll_con);
- break;
- case EPLL:
- r = readl(&clk->epll_con);
- break;
- case HPLL:
- r = readl(&clk->hpll_con);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- /*
- * APLL_CON: MIDV [25:16]
- * MPLL_CON: MIDV [23:16]
- * EPLL_CON: MIDV [23:16]
- * HPLL_CON: MIDV [23:16]
- */
- if (pllreg == APLL)
- mask = 0x3ff;
- else
- mask = 0x0ff;
-
- m = (r >> 16) & mask;
-
- /* PDIV [13:8] */
- p = (r >> 8) & 0x3f;
- /* SDIV [2:0] */
- s = r & 0x7;
-
- /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
- freq = CONFIG_SYS_CLK_FREQ_C100;
- fout = m * (freq / (p * (1 << s)));
-
- return fout;
-}
-
-/* s5pc100: return pll clock frequency */
-static unsigned long s5pc110_get_pll_clk(int pllreg)
-{
- struct s5pc110_clock *clk =
- (struct s5pc110_clock *)samsung_get_base_clock();
- unsigned long r, m, p, s, mask, fout;
- unsigned int freq;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con);
- break;
- case MPLL:
- r = readl(&clk->mpll_con);
- break;
- case EPLL:
- r = readl(&clk->epll_con);
- break;
- case VPLL:
- r = readl(&clk->vpll_con);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- /*
- * APLL_CON: MIDV [25:16]
- * MPLL_CON: MIDV [25:16]
- * EPLL_CON: MIDV [24:16]
- * VPLL_CON: MIDV [24:16]
- */
- if (pllreg == APLL || pllreg == MPLL)
- mask = 0x3ff;
- else
- mask = 0x1ff;
-
- m = (r >> 16) & mask;
-
- /* PDIV [13:8] */
- p = (r >> 8) & 0x3f;
- /* SDIV [2:0] */
- s = r & 0x7;
-
- freq = CONFIG_SYS_CLK_FREQ_C110;
- if (pllreg == APLL) {
- if (s < 1)
- s = 1;
- /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
- fout = m * (freq / (p * (1 << (s - 1))));
- } else
- /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
- fout = m * (freq / (p * (1 << s)));
-
- return fout;
-}
-
-/* s5pc110: return ARM clock frequency */
-static unsigned long s5pc110_get_arm_clk(void)
-{
- struct s5pc110_clock *clk =
- (struct s5pc110_clock *)samsung_get_base_clock();
- unsigned long div;
- unsigned long dout_apll, armclk;
- unsigned int apll_ratio;
-
- div = readl(&clk->div0);
-
- /* APLL_RATIO: [2:0] */
- apll_ratio = div & 0x7;
-
- dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
- armclk = dout_apll;
-
- return armclk;
-}
-
-/* s5pc100: return ARM clock frequency */
-static unsigned long s5pc100_get_arm_clk(void)
-{
- struct s5pc100_clock *clk =
- (struct s5pc100_clock *)samsung_get_base_clock();
- unsigned long div;
- unsigned long dout_apll, armclk;
- unsigned int apll_ratio, arm_ratio;
-
- div = readl(&clk->div0);
-
- /* ARM_RATIO: [6:4] */
- arm_ratio = (div >> 4) & 0x7;
- /* APLL_RATIO: [0] */
- apll_ratio = div & 0x1;
-
- dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
- armclk = dout_apll / (arm_ratio + 1);
-
- return armclk;
-}
-
-/* s5pc100: return HCLKD0 frequency */
-static unsigned long get_hclk(void)
-{
- struct s5pc100_clock *clk =
- (struct s5pc100_clock *)samsung_get_base_clock();
- unsigned long hclkd0;
- uint div, d0_bus_ratio;
-
- div = readl(&clk->div0);
- /* D0_BUS_RATIO: [10:8] */
- d0_bus_ratio = (div >> 8) & 0x7;
-
- hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
-
- return hclkd0;
-}
-
-/* s5pc100: return PCLKD1 frequency */
-static unsigned long get_pclkd1(void)
-{
- struct s5pc100_clock *clk =
- (struct s5pc100_clock *)samsung_get_base_clock();
- unsigned long d1_bus, pclkd1;
- uint div, d1_bus_ratio, pclkd1_ratio;
-
- div = readl(&clk->div0);
- /* D1_BUS_RATIO: [14:12] */
- d1_bus_ratio = (div >> 12) & 0x7;
- /* PCLKD1_RATIO: [18:16] */
- pclkd1_ratio = (div >> 16) & 0x7;
-
- /* ASYNC Mode */
- d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
- pclkd1 = d1_bus / (pclkd1_ratio + 1);
-
- return pclkd1;
-}
-
-/* s5pc110: return HCLKs frequency */
-static unsigned long get_hclk_sys(int dom)
-{
- struct s5pc110_clock *clk =
- (struct s5pc110_clock *)samsung_get_base_clock();
- unsigned long hclk;
- unsigned int div;
- unsigned int offset;
- unsigned int hclk_sys_ratio;
-
- if (dom == CLK_M)
- return get_hclk();
-
- div = readl(&clk->div0);
-
- /*
- * HCLK_MSYS_RATIO: [10:8]
- * HCLK_DSYS_RATIO: [19:16]
- * HCLK_PSYS_RATIO: [27:24]
- */
- offset = 8 + (dom << 0x3);
-
- hclk_sys_ratio = (div >> offset) & 0xf;
-
- hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
-
- return hclk;
-}
-
-/* s5pc110: return PCLKs frequency */
-static unsigned long get_pclk_sys(int dom)
-{
- struct s5pc110_clock *clk =
- (struct s5pc110_clock *)samsung_get_base_clock();
- unsigned long pclk;
- unsigned int div;
- unsigned int offset;
- unsigned int pclk_sys_ratio;
-
- div = readl(&clk->div0);
-
- /*
- * PCLK_MSYS_RATIO: [14:12]
- * PCLK_DSYS_RATIO: [22:20]
- * PCLK_PSYS_RATIO: [30:28]
- */
- offset = 12 + (dom << 0x3);
-
- pclk_sys_ratio = (div >> offset) & 0x7;
-
- pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
-
- return pclk;
-}
-
-/* s5pc110: return peripheral clock frequency */
-static unsigned long s5pc110_get_pclk(void)
-{
- return get_pclk_sys(CLK_P);
-}
-
-/* s5pc100: return peripheral clock frequency */
-static unsigned long s5pc100_get_pclk(void)
-{
- return get_pclkd1();
-}
-
-/* s5pc1xx: return uart clock frequency */
-static unsigned long s5pc1xx_get_uart_clk(int dev_index)
-{
- if (cpu_is_s5pc110())
- return s5pc110_get_pclk();
- else
- return s5pc100_get_pclk();
-}
-
-/* s5pc1xx: return pwm clock frequency */
-static unsigned long s5pc1xx_get_pwm_clk(void)
-{
- if (cpu_is_s5pc110())
- return s5pc110_get_pclk();
- else
- return s5pc100_get_pclk();
-}
-
-unsigned long get_pll_clk(int pllreg)
-{
- if (cpu_is_s5pc110())
- return s5pc110_get_pll_clk(pllreg);
- else
- return s5pc100_get_pll_clk(pllreg);
-}
-
-unsigned long get_arm_clk(void)
-{
- if (cpu_is_s5pc110())
- return s5pc110_get_arm_clk();
- else
- return s5pc100_get_arm_clk();
-}
-
-unsigned long get_pwm_clk(void)
-{
- return s5pc1xx_get_pwm_clk();
-}
-
-unsigned long get_uart_clk(int dev_index)
-{
- return s5pc1xx_get_uart_clk(dev_index);
-}
-
-void set_mmc_clk(int dev_index, unsigned int div)
-{
- /* Do NOTHING */
-}
+++ /dev/null
-/*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/cpu.h>
-#include <linux/linkage.h>
-
-#define S5PC100_SWRESET 0xE0200000
-#define S5PC110_SWRESET 0xE0102000
-
-ENTRY(reset_cpu)
- ldr r1, =S5PC100_PRO_ID
- ldr r2, [r1]
- ldr r4, =0x00010000
- and r4, r2, r4
- cmp r4, #0
- bne 110f
- /* S5PC100 */
- ldr r1, =S5PC100_SWRESET
- ldr r2, =0xC100
- b 200f
-110: /* S5PC110 */
- ldr r1, =S5PC110_SWRESET
- mov r2, #1
-200:
- str r2, [r1]
-_loop_forever:
- b _loop_forever
-ENDPROC(reset_cpu)
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
+obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o
obj-y += fel_utils.o
endif
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
clock_set_pll1(408000000);
- writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
-
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+ while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
+ ;
+
+ writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
puts("CPU: Allwinner A23 (SUN8I)\n");
#elif defined CONFIG_MACH_SUN8I_A33
puts("CPU: Allwinner A33 (SUN8I)\n");
+#elif defined CONFIG_MACH_SUN8I_H3
+ puts("CPU: Allwinner H3 (SUN8I)\n");
#elif defined CONFIG_MACH_SUN9I
puts("CPU: Allwinner A80 (SUN9I)\n");
#else
--- /dev/null
+/*
+ * sun8i H3 platform dram controller init
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <linux/kconfig.h>
+
+struct dram_para {
+ u32 read_delays;
+ u32 write_delays;
+ u16 page_size;
+ u8 bus_width;
+ u8 dual_rank;
+ u8 row_bits;
+};
+
+static inline int ns_to_t(int nanoseconds)
+{
+ const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
+
+ return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+
+static u32 bin_to_mgray(int val)
+{
+ static const u8 lookup_table[32] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
+ 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
+ 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
+ 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
+ };
+
+ return lookup_table[clamp(val, 0, 31)];
+}
+
+static int mgray_to_bin(u32 val)
+{
+ static const u8 lookup_table[32] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
+ 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
+ 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
+ 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
+ };
+
+ return lookup_table[val & 0x1f];
+}
+
+static void mctl_phy_init(u32 val)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ writel(val | PIR_INIT, &mctl_ctl->pir);
+ mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
+}
+
+static void mctl_dq_delay(u32 read, u32 write)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ int i, j;
+ u32 val;
+
+ for (i = 0; i < 4; i++) {
+ val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
+ DATX_IOCR_READ_DELAY((read >> (i * 4)) & 0xf);
+
+ for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
+ setbits_le32(&mctl_ctl->datx[i].iocr[j], val);
+ }
+
+ clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
+
+ for (i = 0; i < 4; i++) {
+ val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
+ DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
+
+ setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQS], val);
+ setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN], val);
+ }
+
+ setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
+
+ udelay(1);
+}
+
+static void mctl_set_master_priority(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ /* enable bandwidth limit windows and set windows size 1us */
+ writel(0x00010190, &mctl_com->bwcr);
+
+ /* set cpu high priority */
+ writel(0x00000001, &mctl_com->mapr);
+
+ writel(0x0200000d, &mctl_com->mcr[0][0]);
+ writel(0x00800100, &mctl_com->mcr[0][1]);
+ writel(0x06000009, &mctl_com->mcr[1][0]);
+ writel(0x01000400, &mctl_com->mcr[1][1]);
+ writel(0x0200000d, &mctl_com->mcr[2][0]);
+ writel(0x00600100, &mctl_com->mcr[2][1]);
+ writel(0x0100000d, &mctl_com->mcr[3][0]);
+ writel(0x00200080, &mctl_com->mcr[3][1]);
+ writel(0x07000009, &mctl_com->mcr[4][0]);
+ writel(0x01000640, &mctl_com->mcr[4][1]);
+ writel(0x0100000d, &mctl_com->mcr[5][0]);
+ writel(0x00200080, &mctl_com->mcr[5][1]);
+ writel(0x01000009, &mctl_com->mcr[6][0]);
+ writel(0x00400080, &mctl_com->mcr[6][1]);
+ writel(0x0100000d, &mctl_com->mcr[7][0]);
+ writel(0x00400080, &mctl_com->mcr[7][1]);
+ writel(0x0100000d, &mctl_com->mcr[8][0]);
+ writel(0x00400080, &mctl_com->mcr[8][1]);
+ writel(0x04000009, &mctl_com->mcr[9][0]);
+ writel(0x00400100, &mctl_com->mcr[9][1]);
+ writel(0x2000030d, &mctl_com->mcr[10][0]);
+ writel(0x04001800, &mctl_com->mcr[10][1]);
+ writel(0x04000009, &mctl_com->mcr[11][0]);
+ writel(0x00400120, &mctl_com->mcr[11][1]);
+}
+
+static void mctl_set_timing_params(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ u8 tccd = 2;
+ u8 tfaw = ns_to_t(50);
+ u8 trrd = max(ns_to_t(10), 4);
+ u8 trcd = ns_to_t(15);
+ u8 trc = ns_to_t(53);
+ u8 txp = max(ns_to_t(8), 3);
+ u8 twtr = max(ns_to_t(8), 4);
+ u8 trtp = max(ns_to_t(8), 4);
+ u8 twr = max(ns_to_t(15), 3);
+ u8 trp = ns_to_t(15);
+ u8 tras = ns_to_t(38);
+ u16 trefi = ns_to_t(7800) / 32;
+ u16 trfc = ns_to_t(350);
+
+ u8 tmrw = 0;
+ u8 tmrd = 4;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 4;
+ u8 trasmax = 24;
+
+ u8 tcl = 6; /* CL 12 */
+ u8 tcwl = 4; /* CWL 8 */
+ u8 t_rdata_en = 4;
+ u8 wr_latency = 2;
+
+ u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
+ u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
+ u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
+ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
+ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
+
+ /* set mode register */
+ writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
+ writel(0x40, &mctl_ctl->mr[1]);
+ writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
+ writel(0x0, &mctl_ctl->mr[3]);
+
+ /* set DRAM timing */
+ writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
+ DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
+ &mctl_ctl->dramtmg[0]);
+ writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
+ &mctl_ctl->dramtmg[1]);
+ writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
+ DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
+ &mctl_ctl->dramtmg[2]);
+ writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
+ &mctl_ctl->dramtmg[3]);
+ writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
+ DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
+ writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
+ DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
+ &mctl_ctl->dramtmg[5]);
+
+ /* set two rank timing */
+ clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
+ (0x66 << 8) | (0x10 << 0));
+
+ /* set PHY interface timing, write latency and read latency configure */
+ writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
+ (wr_latency << 0), &mctl_ctl->pitmg[0]);
+
+ /* set PHY timing, PTR0-2 use default */
+ writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
+ writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
+
+ /* set refresh timing */
+ writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
+}
+
+static void mctl_zq_calibration(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ int i;
+ u16 zq_val[6];
+ u8 val;
+
+ writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
+
+ for (i = 0; i < 6; i++) {
+ u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
+
+ writel((zq << 20) | (zq << 16) | (zq << 12) |
+ (zq << 8) | (zq << 4) | (zq << 0),
+ &mctl_ctl->zqcr);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
+ writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ val = readl(&mctl_ctl->zqdr[0]) >> 24;
+ zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
+ }
+
+ writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
+ writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
+ writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
+}
+
+static void mctl_set_cr(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
+ MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
+ (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
+ MCTL_CR_PAGE_SIZE(para->page_size) |
+ MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
+}
+
+static void mctl_sys_init(struct dram_para *para)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
+ clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
+ udelay(10);
+
+ clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
+ udelay(1000);
+
+ clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
+ clrsetbits_le32(&ccm->dram_clk_cfg,
+ CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK,
+ CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 |
+ CCM_DRAMCLK_CFG_UPD);
+ mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
+
+ setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
+ udelay(10);
+
+ writel(0xc00e, &mctl_ctl->clken);
+ udelay(500);
+}
+
+static int mctl_channel_init(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ unsigned int i;
+
+ mctl_set_cr(para);
+ mctl_set_timing_params(para);
+ mctl_set_master_priority();
+
+ /* setting VTC, default disable all VT */
+ clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
+ clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
+
+ /* increase DFI_PHY_UPD clock */
+ writel(PROTECT_MAGIC, &mctl_com->protect);
+ udelay(100);
+ clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
+ writel(0x0, &mctl_com->protect);
+ udelay(100);
+
+ /* set dramc odt */
+ for (i = 0; i < 4; i++)
+ clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) |
+ (0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
+ (0x3 << 14),
+ IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
+
+ /* AC PDR should always ON */
+ setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
+
+ /* set DQS auto gating PD mode */
+ setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
+
+ /* dx ddr_clk & hdr_clk dynamic mode */
+ clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
+
+ /* dphy & aphy phase select 270 degree */
+ clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
+ (0x1 << 10) | (0x2 << 8));
+
+ /* set half DQ */
+ if (para->bus_width != 32) {
+ writel(0x0, &mctl_ctl->datx[2].gcr);
+ writel(0x0, &mctl_ctl->datx[3].gcr);
+ }
+
+ /* data training configuration */
+ clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
+ (para->dual_rank ? 0x3 : 0x1) << 24);
+
+
+ if (para->read_delays || para->write_delays) {
+ mctl_dq_delay(para->read_delays, para->write_delays);
+ udelay(50);
+ }
+
+ mctl_zq_calibration(para);
+
+ mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST |
+ PIR_DRAMINIT | PIR_QSGATE);
+
+ /* detect ranks and bus width */
+ if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
+ /* only one rank */
+ if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) ||
+ ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) {
+ clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
+ para->dual_rank = 0;
+ }
+
+ /* only half DQ width */
+ if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) ||
+ ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) {
+ writel(0x0, &mctl_ctl->datx[2].gcr);
+ writel(0x0, &mctl_ctl->datx[3].gcr);
+ para->bus_width = 16;
+ }
+
+ mctl_set_cr(para);
+ udelay(20);
+
+ /* re-train */
+ mctl_phy_init(PIR_QSGATE);
+ if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
+ return 1;
+ }
+
+ /* check the dramc status */
+ mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
+
+ /* liuke added for refresh debug */
+ setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
+ udelay(10);
+ clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
+ udelay(10);
+
+ /* set PGCR3, CKE polarity */
+ writel(0x00aa0060, &mctl_ctl->pgcr[3]);
+
+ /* power down zq calibration module for power save */
+ setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
+
+ /* enable master access */
+ writel(0xffffffff, &mctl_com->maer);
+
+ return 0;
+}
+
+static void mctl_auto_detect_dram_size(struct dram_para *para)
+{
+ /* detect row address bits */
+ para->page_size = 512;
+ para->row_bits = 16;
+ mctl_set_cr(para);
+
+ for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
+ if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
+ break;
+
+ /* detect page size */
+ para->page_size = 8192;
+ mctl_set_cr(para);
+
+ for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
+ if (mctl_mem_matches(para->page_size))
+ break;
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ struct dram_para para = {
+ .read_delays = 0x00007979,
+ .write_delays = 0x6aaa0000,
+ .dual_rank = 0,
+ .bus_width = 32,
+ .row_bits = 15,
+ .page_size = 4096,
+ };
+
+ mctl_sys_init(¶);
+ if (mctl_channel_init(¶))
+ return 0;
+
+ if (para.dual_rank)
+ writel(0x00000303, &mctl_ctl->odtmap);
+ else
+ writel(0x00000201, &mctl_ctl->odtmap);
+ udelay(1);
+
+ /* odt delay */
+ writel(0x0c000400, &mctl_ctl->odtcfg);
+
+ /* clear credit value */
+ setbits_le32(&mctl_com->cccr, 1 << 31);
+ udelay(10);
+
+ mctl_auto_detect_dram_size(¶);
+ mctl_set_cr(¶);
+
+ return (1 << (para.row_bits + 3)) * para.page_size *
+ (para.dual_rank ? 2 : 1);
+}
#ifndef CONFIG_SYS_DCACHE_OFF
inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
- u64 memory_type, u64 share)
+ u64 memory_type, u64 attribute)
{
u64 value;
value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
- value |= share;
+ value |= attribute;
page_table[index] = value;
}
endif
endif
+ifneq ($(CONFIG_LS2080A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
+endif
+
ifneq ($(CONFIG_LS2085A),)
-obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
-else
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
+endif
+
ifneq ($(CONFIG_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
endif
-endif
Freescale LayerScape with Chassis Generation 3
This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
-for example LS2085A.
+for example LS2080A.
DDR Layout
============
nand write <rcw image in memory> 0 <size of rcw image>
To form the NAND image, build u-boot with NAND config, for example,
-ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
+ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
nand write <u-boot image in memory> 200000 <size of u-boot image>
| 0x81_0000_0000 | | 0x08_0080_0000 |
------------------ ------------------
... ...
+
+
+DPAA2 commands to manage Management Complex (MC)
+------------------------------------------------
+DPAA2 commands has been introduced to manage Management Complex
+(MC). These commands are used to start mc, aiop and apply DPL
+from u-boot command prompt.
+
+Please note Management complex Firmware(MC), DPL and DPC are no
+more deployed during u-boot boot-sequence.
+
+Commands:
+a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+c) fsl_mc start aiop <FW_addr> - Start AIOP
+
+How to use commands :-
+1. Command sequence for u-boot ethernet:
+ a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+ b) DPMAC net-devices are now available for use
+
+ Example-
+ Assumption: MC firmware, DPL and DPC dtb is already programmed
+ on NOR flash.
+
+ => fsl_mc start mc 580300000 580800000
+ => setenv ethact DPMAC1@xgmii
+ => ping $serverip
+
+2. Command sequence for Linux boot:
+ a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+ b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+ c) No DPMAC net-devices are available for use in u-boot
+ d) boot Linux
+
+ Example-
+ Assumption: MC firmware, DPL and DPC dtb is already programmed
+ on NOR flash.
+
+ => fsl_mc start mc 580300000 580800000
+ => setenv ethact DPMAC1@xgmii
+ => tftp a0000000 kernel.itb
+ => fsl_mc apply dpl 580700000
+ => bootm a0000000
+
+3. Command sequence for AIOP boot:
+ a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
+ b) fsl_mc start aiop <FW_addr> - Start AIOP
+ c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
+ d) No DPMAC net-devices are availabe for use in u-boot
+ Please note actual AIOP start will happen during DPL parsing of
+ Management complex
+
+ Example-
+ Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
+ programmed on NOR flash.
+
+ => fsl_mc start mc 580300000 580800000
+ => fsl_mc start aiop 0x580900000
+ => setenv ethact DPMAC1@xgmii
+ => fsl_mc apply dpl 580700000
+
+Errata A009635
+---------------
+If the core runs at higher than x3 speed of the platform, there is
+possiblity about sev instruction to getting missed by other cores.
+This is because of SoC Run Control block may not able to sample
+the EVENTI(Sev) signals.
+
+Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
+wake up A57 cores
+
+Errata workaround uses Env variable "a009635_interval_val". It uses decimal
+value.
+- Default value of env variable is platform clock (MHz)
+
+- User can modify default value by updating the env variable
+ setenv a009635_interval_val 600; saveenv;
+ It configure platform clock as 600 MHz
+
+- Env variable as 0 signifies no workaround
index,
block_addr,
list->memory_type,
- list->share);
+ list->attribute);
block_addr += block_size;
index++;
}
#ifdef CONFIG_SYS_DPAA_FMAN
printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
#endif
-#ifdef CONFIG_FSL_LSCH3
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
#endif
puts("\n");
{
#ifdef CONFIG_MP
int rv = 1;
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+ erratum_a009635();
+#endif
+
+#ifdef CONFIG_MP
rv = fsl_layerscape_wake_seconday_cores();
if (rv)
printf("Did not wake secondary cores\n");
/*
* The info below summarizes how streamID partitioning works
- * for ls2085a and how it is conveyed to the OS via the device tree.
+ * for ls2080a and how it is conveyed to the OS via the device tree.
*
* -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
* -all legacy devices get a unique ICID assigned and programmed in
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
+#ifdef CONFIG_FSL_MC_ENET
+int xfi_dpmac[XFI8 + 1];
+int sgmii_dpmac[SGMII16 + 1];
+#endif
+
int is_serdes_configured(enum srds_prtcl device)
{
int ret = 0;
wriop_init_dpmac(sd, 12, (int)lane_prtcl);
break;
default:
+ if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
+ wriop_init_dpmac(sd,
+ xfi_dpmac[lane_prtcl],
+ (int)lane_prtcl);
+
if (lane_prtcl >= SGMII1 &&
- lane_prtcl <= SGMII16)
- wriop_init_dpmac(sd, lane + 1,
+ lane_prtcl <= SGMII16)
+ wriop_init_dpmac(sd, sgmii_dpmac[
+ lane_prtcl],
(int)lane_prtcl);
break;
}
void fsl_serdes_init(void)
{
+#ifdef CONFIG_FSL_MC_ENET
+ int i , j;
+
+ for (i = XFI1, j = 1; i <= XFI8; i++, j++)
+ xfi_dpmac[i] = j;
+
+ for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
+ sgmii_dpmac[i] = j;
+#endif
+
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
#include <fsl_ifc.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include "cpu.h"
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
+#endif
#else
sys_info->freq_ddrbus = sysclk;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
sys_info->freq_ddrbus2 = sysclk;
+#endif
#endif
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
+#endif
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
/*
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
+#endif
#if defined(CONFIG_FSL_ESDHC)
gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif /* defined(CONFIG_FSL_ESDHC) */
* DDR controller 0 & 1 are on memory complex 0
* DDR controler 2 is on memory complext 1
*/
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num >= 2)
return gd->arch.mem2_clk;
+#endif
return gd->mem_clk;
}
--- /dev/null
+/*
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+
+struct serdes_config {
+ u8 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } },
+ {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+ SGMII1 } },
+ {0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+ SGMII1 } },
+ {0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+ SGMII1 } },
+ {0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+ SGMII1 } },
+ {0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+ SGMII1 } },
+ {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
+ {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
+#ifdef CONFIG_LS2080A
+ {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } },
+#endif
+#ifdef CONFIG_LS2085A
+ {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
+#endif
+ {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
+ {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
+ {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
+ QSGMII_B} },
+ {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+ {}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+ /* SerDes 2 */
+ {0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+ SGMII16 } },
+ {0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+ SGMII16 } },
+ {0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+ SGMII16 } },
+ {0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+ SGMII16 } },
+ {0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+ SGMII16 } },
+ {0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+ {0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+ {0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+ {0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+ {0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+ {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+ {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+ {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+ {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
+ SGMII16 } },
+ {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
+ PCIE4 } },
+ {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
+ SATA2 } },
+ {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
+ SATA2 } },
+ {}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+ serdes2_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
+++ /dev/null
-/*
- * Copyright 2014-2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/fsl_serdes.h>
-
-struct serdes_config {
- u8 protocol;
- u8 lanes[SRDS_MAX_LANES];
-};
-
-static struct serdes_config serdes1_cfg_tbl[] = {
- /* SerDes 1 */
- {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } },
- {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
- {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
- SGMII1 } },
- {0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
- SGMII1 } },
- {0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
- SGMII1 } },
- {0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
- SGMII1 } },
- {0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
- SGMII1 } },
- {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
- {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
- {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
- {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
- {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
- {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
- QSGMII_B} },
- {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
- {}
-};
-static struct serdes_config serdes2_cfg_tbl[] = {
- /* SerDes 2 */
- {0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
- SGMII16 } },
- {0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
- SGMII16 } },
- {0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
- SGMII16 } },
- {0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
- SGMII16 } },
- {0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
- SGMII16 } },
- {0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
- {0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
- {0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
- {0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
- {0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
- {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
- {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
- {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
- {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
- SGMII16 } },
- {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
- PCIE4 } },
- {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
- SATA2 } },
- {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
- SATA2 } },
- {}
-};
-
-static struct serdes_config *serdes_cfg_tbl[] = {
- serdes1_cfg_tbl,
- serdes2_cfg_tbl,
-};
-
-enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
-{
- struct serdes_config *ptr;
-
- if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
- return 0;
-
- ptr = serdes_cfg_tbl[serdes];
- while (ptr->protocol) {
- if (ptr->protocol == cfg)
- return ptr->lanes[lane];
- ptr++;
- }
-
- return 0;
-}
-
-int is_serdes_prtcl_valid(int serdes, u32 prtcl)
-{
- int i;
- struct serdes_config *ptr;
-
- if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
- return 0;
-
- ptr = serdes_cfg_tbl[serdes];
- while (ptr->protocol) {
- if (ptr->protocol == prtcl)
- break;
- ptr++;
- }
-
- if (!ptr->protocol)
- return 0;
-
- for (i = 0; i < SRDS_MAX_LANES; i++) {
- if (ptr->lanes[i] != NONE)
- return 1;
- }
-
- return 0;
-}
(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
asm volatile("dsb st");
smp_kick_all_cpus(); /* only those with entry addr set will run */
+ /*
+ * When the first release command runs, all cores are set to go. Those
+ * without a valid entry address will be trapped by "wfe". "sev" kicks
+ * them off to check the address again. When set, they continue to run.
+ */
+ asm volatile("sev");
return 0;
}
#include <asm/arch/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
+#include <asm/arch-fsl-layerscape/config.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
+
+static unsigned long get_internval_val_mhz(void)
+{
+ char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
+ /*
+ * interval is the number of platform cycles(MHz) between
+ * wake up events generated by EPU.
+ */
+ ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
+
+ if (interval)
+ interval_mhz = simple_strtoul(interval, NULL, 10);
+
+ return interval_mhz;
+}
+
+void erratum_a009635(void)
+{
+ u32 val;
+ unsigned long interval_mhz = get_internval_val_mhz();
+
+ if (!interval_mhz)
+ return;
+
+ val = in_le32(DCSR_CGACRE5);
+ writel(val | 0x00000200, DCSR_CGACRE5);
+
+ val = in_le32(EPU_EPCMPR5);
+ writel(interval_mhz, EPU_EPCMPR5);
+ val = in_le32(EPU_EPCCR5);
+ writel(val | 0x82820000, EPU_EPCCR5);
+ val = in_le32(EPU_EPSMCR5);
+ writel(val | 0x002f0000, EPU_EPSMCR5);
+ val = in_le32(EPU_EPECR5);
+ writel(val | 0x20000000, EPU_EPECR5);
+ val = in_le32(EPU_EPGCR);
+ writel(val | 0x80000000, EPU_EPGCR);
+}
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
+
static void erratum_a008751(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
- /* Set global data pointer */
- gd = &gdata;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
arch_cpu_init();
#endif
#ifdef CONFIG_FSL_IFC
#endif
board_early_init_f();
timer_init();
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
env_init();
#endif
get_clocks();
exynos5422-odroidxu3.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-firefly.dtb \
- rk3288-jerry.dtb
+ rk3288-jerry.dtb \
+ rk3036-sdk.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
ls1021a-twr.dtb
-dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
- fsl-ls2085a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+ fsl-ls2080a-rdb.dtb
+dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
+ fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun7i-a20-cubietruck.dtb \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
+ sun7i-a20-lamobo-r1.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-m5.dtb \
sun7i-a20-mk808c.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb
+dtb-$(CONFIG_MACH_SUN8I_H3) += \
+ sun8i-h3-orangepi-pc.dtb \
+ sun8i-h3-orangepi-plus.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
--- /dev/null
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1043a.dtsi"
+
+/ {
+ model = "LS1043A QDS Board";
+};
+
+&i2c0 {
+ status = "okay";
+ pca9547@77 {
+ compatible = "philips,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ /* IRQ10_B */
+ interrupts = <0 150 0x4>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220@41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ eeprom@56 {
+ compatible = "at24,24c512";
+ reg = <0x56>;
+ };
+
+ eeprom@57 {
+ compatible = "at24,24c512";
+ reg = <0x57>;
+ };
+
+ adt7461a@4c {
+ compatible = "adt7461a";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x2 0x0 0x0 0x7e800000 0x00010000
+ 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+ status = "okay";
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@2,0 {
+ compatible = "fsl,ifc-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ fpga: board-control@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ reg = <0x3 0x0 0x0000100>;
+ bank-width = <1>;
+ device-width = <1>;
+ ranges = <0 3 0 0x100>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "fsl-ls1043a.dtsi"
+
+/ {
+ model = "LS1043A RDB Board";
+
+ aliases {
+ spi1 = &dspi0;
+ };
+
+};
+
+&dspi0 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: n25q12a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <1000000>; /* input clock */
+ };
+
+};
+
+&i2c0 {
+ status = "okay";
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+ adt7461a@4c {
+ compatible = "adi,adt7461a";
+ reg = <0x4c>;
+ };
+ eeprom@56 {
+ compatible = "at24,24c512";
+ reg = <0x52>;
+ };
+
+ eeprom@57 {
+ compatible = "at24,24c512";
+ reg = <0x53>;
+ };
+
+ rtc@68 {
+ compatible = "pericom,pt7c4338";
+ reg = <0x68>;
+ };
+};
+
+&ifc {
+ status = "okay";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ /* NOR, NAND Flashes and FPGA on board */
+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+ 0x2 0x0 0x0 0x7e800000 0x00010000
+ 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+
+ nor@0,0 {
+ compatible = "cfi-flash";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@1,0 {
+ compatible = "fsl,ifc-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ cpld: board-control@2,0 {
+ compatible = "fsl,ls1043ardb-cpld";
+ reg = <0x2 0x0 0x0000100>;
+ };
+};
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright (C) 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+ compatible = "fsl,ls1043a";
+ interrupt-parent = <&gic>;
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ clocks = <&clockgen 1 0>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ clocks = <&clockgen 1 0>;
+ };
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ gic: interrupt-controller@1400000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+ <0x0 0x1402000 0 0x2000>, /* GICC */
+ <0x0 0x1404000 0 0x2000>, /* GICH */
+ <0x0 0x1406000 0 0x2000>; /* GICV */
+ interrupts = <1 9 0xf08>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clockgen: clocking@1ee1000 {
+ compatible = "fsl,ls1043a-clockgen";
+ reg = <0x0 0x1ee1000 0x0 0x1000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ dspi0: dspi@2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 64 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <6>;
+ big-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi@2110000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <0 65 0x4>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <6>;
+ big-endian;
+ status = "disabled";
+ };
+
+ ifc: ifc@1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x1530000 0x0 0x10000>;
+ interrupts = <0 43 0x4>;
+ };
+
+ i2c0: i2c@2180000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <0 56 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2190000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <0 57 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@21a0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21a0000 0x0 0x10000>;
+ interrupts = <0 58 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@21b0000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21b0000 0x0 0x10000>;
+ interrupts = <0 59 0x4>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ duart0: serial@21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0500 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart1: serial@21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x00 0x21c0600 0x0 0x100>;
+ interrupts = <0 54 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart2: serial@21d0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0500 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+
+ duart3: serial@21d0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21d0600 0x0 0x100>;
+ interrupts = <0 55 0x4>;
+ clocks = <&clockgen 4 0>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Freescale ls2080a QDS board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2080a.dtsi"
+
+/ {
+ model = "Freescale Layerscape 2080a QDS Board";
+ compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
+
+ aliases {
+ spi1 = &dspi;
+ };
+};
+
+&dspi {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <1>;
+ };
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <2>;
+ };
+};
--- /dev/null
+/*
+ * Freescale ls2080a RDB board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "fsl-ls2080a.dtsi"
+
+/ {
+ model = "Freescale Layerscape 2080a RDB Board";
+ compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
+
+ aliases {
+ spi1 = &dspi;
+ };
+};
+
+&dspi {
+ bus-num = <0>;
+ status = "okay";
+
+ dflash0: n25q512a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
--- /dev/null
+/*
+ * Freescale ls2080a SOC common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ compatible = "fsl,ls2080a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /*
+ * We expect the enable-method for cpu's to be "psci", but this
+ * is dependent on the SoC FW, which will fill this in.
+ *
+ * Currently supported enable-method is psci v0.2
+ */
+
+ /* We have 4 clusters having 2 Cortex-A57 cores each */
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x1>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ };
+
+ cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x200>;
+ };
+
+ cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x201>;
+ };
+
+ cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x300>;
+ };
+
+ cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x301>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x80000000>;
+ /* DRAM space - 1, size : 2 GB DRAM */
+ };
+
+ gic: interrupt-controller@6000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+ <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <1 9 0x4>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
+ <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
+ <1 11 0x8>, /* Virtual PPI, active-low */
+ <1 10 0x8>; /* Hypervisor PPI, active-low */
+ };
+
+ serial0: serial@21c0500 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0500 0x0 0x100>;
+ clock-frequency = <0>; /* Updated by bootloader */
+ interrupts = <0 32 0x1>; /* edge triggered */
+ };
+
+ serial1: serial@21c0600 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0600 0x0 0x100>;
+ clock-frequency = <0>; /* Updated by bootloader */
+ interrupts = <0 32 0x1>; /* edge triggered */
+ };
+
+ fsl_mc: fsl-mc@80c000000 {
+ compatible = "fsl,qoriq-mc";
+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+ };
+
+ dspi: dspi@2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 26 0x4>; /* Level high type */
+ num-cs = <6>;
+ };
+};
+++ /dev/null
-/*
- * Freescale ls2085a QDS board device tree source
- *
- * Copyright 2013-2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-
-#include "fsl-ls2085a.dtsi"
-
-/ {
- model = "Freescale Layerscape 2085a QDS Board";
- compatible = "fsl,ls2085a-qds", "fsl,ls2085a";
-
- aliases {
- spi1 = &dspi;
- };
-};
-
-&dspi {
- bus-num = <0>;
- status = "okay";
-
- dflash0: n25q128a {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-flash";
- spi-max-frequency = <3000000>;
- spi-cpol;
- spi-cpha;
- reg = <0>;
- };
- dflash1: sst25wf040b {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-flash";
- spi-max-frequency = <3000000>;
- spi-cpol;
- spi-cpha;
- reg = <1>;
- };
- dflash2: en25s64 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-flash";
- spi-max-frequency = <3000000>;
- spi-cpol;
- spi-cpha;
- reg = <2>;
- };
-};
+++ /dev/null
-/*
- * Freescale ls2085a RDB board device tree source
- *
- * Copyright 2013-2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/dts-v1/;
-
-#include "fsl-ls2085a.dtsi"
-
-/ {
- model = "Freescale Layerscape 2085a RDB Board";
- compatible = "fsl,ls2085a-rdb", "fsl,ls2085a";
-
- aliases {
- spi1 = &dspi;
- };
-};
-
-&dspi {
- bus-num = <0>;
- status = "okay";
-
- dflash0: n25q512a {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-flash";
- spi-max-frequency = <3000000>;
- spi-cpol;
- spi-cpha;
- reg = <0>;
- };
-};
+++ /dev/null
-/*
- * Freescale ls2085a SOC common device tree source
- *
- * Copyright 2013-2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/ {
- compatible = "fsl,ls2085a";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- /*
- * We expect the enable-method for cpu's to be "psci", but this
- * is dependent on the SoC FW, which will fill this in.
- *
- * Currently supported enable-method is psci v0.2
- */
-
- /* We have 4 clusters having 2 Cortex-A57 cores each */
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x0>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x1>;
- };
-
- cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x100>;
- };
-
- cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x101>;
- };
-
- cpu@200 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x200>;
- };
-
- cpu@201 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x201>;
- };
-
- cpu@300 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x300>;
- };
-
- cpu@301 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x301>;
- };
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x00000000 0x80000000 0 0x80000000>;
- /* DRAM space - 1, size : 2 GB DRAM */
- };
-
- gic: interrupt-controller@6000000 {
- compatible = "arm,gic-v3";
- reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
- <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = <1 9 0x4>;
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
- <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
- <1 11 0x8>, /* Virtual PPI, active-low */
- <1 10 0x8>; /* Hypervisor PPI, active-low */
- };
-
- serial0: serial@21c0500 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0500 0x0 0x100>;
- clock-frequency = <0>; /* Updated by bootloader */
- interrupts = <0 32 0x1>; /* edge triggered */
- };
-
- serial1: serial@21c0600 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0600 0x0 0x100>;
- clock-frequency = <0>; /* Updated by bootloader */
- interrupts = <0 32 0x1>; /* edge triggered */
- };
-
- fsl_mc: fsl-mc@80c000000 {
- compatible = "fsl,qoriq-mc";
- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
- };
-
- dspi: dspi@2100000 {
- compatible = "fsl,vf610-dspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2100000 0x0 0x10000>;
- interrupts = <0 26 0x4>; /* Level high type */
- num-cs = <6>;
- };
-};
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+ model = "SDK-RK3036";
+ compatible = "sdk,sdk-rk3036", "rockchip,rk3036";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ usb_control {
+ compatible = "rockchip,rk3036-usb-control";
+ host_drv_gpio = <&gpio2 23 GPIO_ACTIVE_LOW>;
+ otg_drv_gpio = <&gpio0 26 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+};
+
+&usb_host {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+
+ dr_mode = "host";
+};
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3036-cru.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "rockchip,rk3036";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ i2c1 = &i2c1;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ mmc0 = &emmc;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "rockchip,rk3036-smp";
+
+ cpu0: cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ operating-points = <
+ /* KHz uV */
+ 816000 1000000
+ >;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ resets = <&cru SRST_CORE0>;
+ };
+ cpu1: cpu@f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ resets = <&cru SRST_CORE1>;
+ };
+ };
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma: pdma@20078000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x20078000 0x4000>;
+ arm,pl330-broken-no-flushp;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ clocks = <&cru ACLK_DMAC2>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ arm,cpu-registers-not-fw-configured;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ cru: clock-controller@20000000 {
+ compatible = "rockchip,rk3036-cru";
+ reg = <0x20000000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&cru PLL_GPLL>;
+ assigned-clock-rates = <594000000>;
+ };
+
+ uart0: serial@20060000 {
+ compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
+ reg = <0x20060000 0x100>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ };
+
+ uart1: serial@20064000 {
+ compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
+ reg = <0x20064000 0x100>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ };
+
+ uart2: serial@20068000 {
+ compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
+ reg = <0x20068000 0x100>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_xfer>;
+ };
+
+ pwm0: pwm@20050000 {
+ compatible = "rockchip,rk2928-pwm";
+ reg = <0x20050000 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
+ pwm1: pwm@20050010 {
+ compatible = "rockchip,rk2928-pwm";
+ reg = <0x20050010 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
+ pwm2: pwm@20050020 {
+ compatible = "rockchip,rk2928-pwm";
+ reg = <0x20050020 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
+ pwm3: pwm@20050030 {
+ compatible = "rockchip,rk2928-pwm";
+ reg = <0x20050030 0x10>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ status = "disabled";
+ };
+
+ sram: sram@10080000 {
+ compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
+ reg = <0x10080000 0x2000>;
+ };
+
+ gic: interrupt-controller@10139000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x10139000 0x1000>,
+ <0x1013a000 0x1000>,
+ <0x1013c000 0x2000>,
+ <0x1013e000 0x2000>;
+ interrupts = <GIC_PPI 9 0xf04>;
+ };
+
+ grf: syscon@20008000 {
+ compatible = "rockchip,rk3036-grf", "syscon";
+ reg = <0x20008000 0x1000>;
+ };
+
+ usb_otg: usb@10180000 {
+ compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x10180000 0x40000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG0>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <275>;
+ g-tx-fifo-size = <256 128 128 64 64 32>;
+ g-use-dma;
+ status = "disabled";
+ };
+
+ usb_host: usb@101c0000 {
+ compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x101c0000 0x40000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG1>;
+ clock-names = "otg";
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ emmc: dwmmc@1021c000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ clock-frequency = <37500000>;
+ clock-freq-min-max = <400000 37500000>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ dmas = <&pdma 12>;
+ dma-names = "rx-tx";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1021c000 0x4000>;
+ broken-cd;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ disable-wp;
+ fifo-mode;
+ non-removable;
+ num-slots = <1>;
+ default-sample-phase = <158>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3036-pinctrl";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@2007c000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x2007c000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@20080000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20080000 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2@20084000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20084000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ emmc {
+ /*
+ * We run eMMC at max speed; bump up drive strength.
+ * We also have external pulls, so disable the internal ones.
+ */
+ emmc_clk: emmc-clk {
+ rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
+ <1 25 RK_FUNC_2 &pcfg_pull_none>,
+ <1 26 RK_FUNC_2 &pcfg_pull_none>,
+ <1 27 RK_FUNC_2 &pcfg_pull_none>;
+ /*
+ <1 28 RK_FUNC_2 &pcfg_pull_up>,
+ <1 29 RK_FUNC_2 &pcfg_pull_up>,
+ <1 30 RK_FUNC_2 &pcfg_pull_up>,
+ <1 31 RK_FUNC_2 &pcfg_pull_up>;
+ */
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
+ <0 17 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
+ <2 23 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ /* no rts / cts for uart1 */
+ };
+
+ uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
+ <1 19 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ /* no rts / cts for uart2 */
+ };
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+ rockchip,pins = <0 1 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins = <0 27 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
+ <0 3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+ };
+
+ i2c1: i2c@20056000 {
+ compatible = "rockchip,rk3288-i2c";
+ reg = <0x20056000 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ status = "disabled";
+ };
+};
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ clock-frequency = <24000000>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ clock-frequency = <24000000>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ drvsel = <3>;
+ smplsel = <0>;
};
sysmgr@ffd08000 {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ drvsel = <3>;
+ smplsel = <0>;
};
sysmgr@ffd08000 {
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
};
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
};
&gmac1 {
&mmc0 {
status = "okay";
+ u-boot,dm-pre-reloc;
};
&qspi {
--- /dev/null
+/*
+ * Copyright 2015 Jelle de Jong <jelledejong@powercraft.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Lamobo R1";
+ compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart3;
+ serial2 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_lamobo_r1>;
+
+ green {
+ label = "lamobo_r1:green:usr";
+ gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_power_pin_lamobo_r1>;
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+ };
+};
+
+&ahci_pwr_pin_a {
+ allwinner,pins = "PB3";
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+ operating-points = <
+ /* kHz uV */
+ 960000 1400000
+ 912000 1400000
+ 864000 1350000
+ 720000 1250000
+ 528000 1150000
+ 312000 1100000
+ 144000 1050000
+ >;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ phy-supply = <®_gmac_3v3>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_rx_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 {
+ allwinner,pins = "PH10";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ gmac_power_pin_lamobo_r1: gmac_power_pin@0 {
+ allwinner,pins = "PH23";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_lamobo_r1: led_pins@0 {
+ allwinner,pins = "PH24";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+#include "axp209.dtsi"
+
+®_ahci_5v {
+ gpio = <&pio 1 3 0>; /* PB3 */
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb0_vbus {
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_a>,
+ <&spi0_cs0_pins_a>,
+ <&spi0_cs1_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_b>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi PC";
+ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi Plus";
+ compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_usb3_vbus: usb3-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_vbus_pin_a>;
+ regulator-name = "usb3-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&pio {
+ usb3_vbus_pin_a: usb3_vbus_pin@0 {
+ allwinner,pins = "PG11";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+®_usb1_vbus {
+ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PG13";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb3_vbus-supply = <®_usb3_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ /* dummy clock until actually implemented */
+ pll5: pll5_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "pll5";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6", "pll6x2", "pll6d2";
+ };
+
+ pll8: clk@01c20044 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20044 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll8", "pll8x2";
+ };
+
+ cpu: cpu_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb1: ahb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ahb1-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+ clock-output-names = "ahb1";
+ };
+
+ ahb2: ahb2_clk@01c2005c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-h3-ahb2-clk";
+ reg = <0x01c2005c 0x4>;
+ clocks = <&ahb1>, <&pll6 2>;
+ clock-output-names = "ahb2";
+ };
+
+ apb1: apb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ clock-output-names = "apb1";
+ };
+
+ apb2: apb2_clk@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
+ clock-output-names = "apb2";
+ };
+
+ bus_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-h3-bus-gates-clk";
+ reg = <0x01c20060 0x14>;
+ clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
+ clock-names = "ahb1", "ahb2", "apb1", "apb2";
+ clock-indices = <5>, <6>, <8>,
+ <9>, <10>, <13>,
+ <14>, <17>, <18>,
+ <19>, <20>,
+ <21>, <23>,
+ <24>, <25>,
+ <26>, <27>,
+ <28>, <29>,
+ <30>, <31>, <32>,
+ <35>, <36>, <37>,
+ <40>, <41>, <43>,
+ <44>, <52>, <53>,
+ <54>, <64>,
+ <65>, <69>, <72>,
+ <76>, <77>, <78>,
+ <96>, <97>, <98>,
+ <112>, <113>,
+ <114>, <115>, <116>,
+ <128>, <135>;
+ clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0",
+ "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand",
+ "ahb1_sdram", "ahb2_gmac", "ahb1_ts",
+ "ahb1_hstimer", "ahb1_spi0",
+ "ahb1_spi1", "ahb1_otg",
+ "ahb1_otg_ehci0", "ahb1_ehic1",
+ "ahb1_ehic2", "ahb1_ehic3",
+ "ahb1_otg_ohci0", "ahb2_ohic1",
+ "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve",
+ "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint",
+ "ahb1_csi", "ahb1_tve", "ahb1_hdmi",
+ "ahb1_de", "ahb1_gpu", "ahb1_msgbox",
+ "ahb1_spinlock", "apb1_codec",
+ "apb1_spdif", "apb1_pio", "apb1_ths",
+ "apb1_i2s0", "apb1_i2s1", "apb1_i2s2",
+ "apb2_i2c0", "apb2_i2c1", "apb2_i2c2",
+ "apb2_uart0", "apb2_uart1",
+ "apb2_uart2", "apb2_uart3", "apb2_scr",
+ "ahb1_ephy", "ahb1_dbg";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+ };
+
+ usb_clk: clk@01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun8i-h3-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "usb_phy0", "usb_phy1",
+ "usb_phy2", "usb_phy3",
+ "usb_ohci0", "usb_ohci1",
+ "usb_ohci2", "usb_ohci3";
+ };
+
+ mbus_clk: clk@01c2015c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-mbus-clk";
+ reg = <0x01c2015c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5>;
+ clock-output-names = "mbus";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun8i-h3-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 6>;
+ resets = <&bus_rst 6>;
+ #dma-cells = <1>;
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&bus_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&bus_rst 8>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&bus_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&bus_rst 9>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&bus_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&bus_rst 10>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usbphy: phy@01c19400 {
+ compatible = "allwinner,sun8i-h3-usb-phy";
+ reg = <0x01c19400 0x2c>,
+ <0x01c1a800 0x4>,
+ <0x01c1b800 0x4>,
+ <0x01c1c800 0x4>,
+ <0x01c1d800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2",
+ "pmu3";
+ clocks = <&usb_clk 8>,
+ <&usb_clk 9>,
+ <&usb_clk 10>,
+ <&usb_clk 11>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb3_phy";
+ resets = <&usb_clk 0>,
+ <&usb_clk 1>,
+ <&usb_clk 2>,
+ <&usb_clk 3>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset",
+ "usb3_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci1: usb@01c1b000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 25>, <&bus_gates 29>;
+ resets = <&bus_rst 25>, <&bus_rst 29>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@01c1b400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1b400 0x100>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 29>, <&bus_gates 25>,
+ <&usb_clk 17>;
+ resets = <&bus_rst 29>, <&bus_rst 25>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb@01c1c000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 26>, <&bus_gates 30>;
+ resets = <&bus_rst 26>, <&bus_rst 30>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@01c1c400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 30>, <&bus_gates 26>,
+ <&usb_clk 18>;
+ resets = <&bus_rst 30>, <&bus_rst 26>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci3: usb@01c1d000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1d000 0x100>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 27>, <&bus_gates 31>;
+ resets = <&bus_rst 27>, <&bus_rst 31>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci3: usb@01c1d400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1d400 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 31>, <&bus_gates 27>,
+ <&usb_clk 19>;
+ resets = <&bus_rst 31>, <&bus_rst 27>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun8i-h3-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 69>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PA4", "PA5";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin: mmc0_cd_pin@0 {
+ allwinner,pins = "PF6";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc1_pins_a: mmc1@0 {
+ allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ bus_rst: reset@01c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun8i-h3-bus-reset";
+ reg = <0x01c202c0 0x1c>;
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ wdt0: watchdog@01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 112>;
+ resets = <&bus_rst 144>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 113>;
+ resets = <&bus_rst 145>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 114>;
+ resets = <&bus_rst 146>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 115>;
+ resets = <&bus_rst 147>;
+ dmas = <&dma 9>, <&dma 9>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ rtc: rtc@01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
-#if defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#ifdef CONFIG_LS2080A
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#endif
+#ifdef CONFIG_LS2085A
#define CONFIG_NUM_DDR_CONTROLLERS 3
+#define CONFIG_SYS_FSL_HAS_DP_DDR
+#endif
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
#define CONFIG_SYS_FSL_ESDHC_LE
#define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
#define CCI_MN_DVM_DOMAIN_CTL 0x200
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
+#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
+#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
+#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
+#define CCN_HN_F_SAM_NODEID_MASK 0x7f
+#define CCN_HN_F_SAM_NODEID_DDR0 0x4
+#define CCN_HN_F_SAM_NODEID_DDR1 0xe
+
#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+#define DCSR_CGACRE5 0x700070914ULL
+#define EPU_EPCMPR5 0x700060914ULL
+#define EPU_EPCCR5 0x700060814ULL
+#define EPU_EPSMCR5 0x700060228ULL
+#define EPU_EPECR5 0x700060314ULL
+#define EPU_EPCTR5 0x700060a14ULL
+#define EPU_EPGCR 0x700060000ULL
+
#define CONFIG_SYS_FSL_ERRATUM_A008336
#define CONFIG_SYS_FSL_ERRATUM_A008511
#define CONFIG_SYS_FSL_ERRATUM_A008514
#define CONFIG_SYS_FSL_ERRATUM_A008585
#define CONFIG_SYS_FSL_ERRATUM_A008751
+#define CONFIG_SYS_FSL_ERRATUM_A009635
#elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define _FSL_LAYERSCAPE_CPU_H
static struct cpu_type cpu_type_list[] = {
- CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+ CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
};
u64 phys_addr;
u64 size;
u64 memory_type;
- u64 share;
+ u64 attribute;
};
struct table_info {
static const struct sys_mmu_table early_mmu_table[] = {
#ifdef CONFIG_FSL_LSCH3
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
/* For IFC Region #1, only the first 4MB is cache-enabled */
CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+ CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
static const struct sys_mmu_table final_mmu_table[] = {
#ifdef CONFIG_FSL_LSCH3
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
- CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
- CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
- CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
/* For QBMAN portal, only the first 64MB is cache-enabled */
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
- MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
- CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
- CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
- CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#ifdef CONFIG_LS2085A
+ CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
- CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
#endif
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
- CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
- CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
- CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
- CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
- CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
- CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
- CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
- CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#endif
void append_mmu_masters(void *blob, const char *smmu_path,
const char *master_name, u32 *stream_ids, int count);
void fdt_fixup_smmu_pcie(void *blob);
+void fdt_fixup_board_enet(void *fdt);
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
#include <config.h>
-#if defined(CONFIG_LS2085A)
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
enum srds_prtcl {
NONE = 0,
PCIE1,
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
+/* LUT registers */
+#define PCIE_LUT_BASE 0x10000
+#define PCIE_LUT_LCTRL0 0x7F8
+#define PCIE_LUT_DBG 0x7FC
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
-#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
+#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
+/* LUT registers */
+#define PCIE_LUT_BASE 0x80000
+#define PCIE_LUT_LCTRL0 0x7F8
+#define PCIE_LUT_DBG 0x7FC
/* Device Configuration */
#define DCFG_BASE 0x01e00000
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
unsigned long freq_ddrbus;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
unsigned long freq_ddrbus2;
+#endif
unsigned long freq_localbus;
unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#ifndef __FSL_STREAM_ID_H
+#define __FSL_STREAM_ID_H
+
+/* Stream IDs on ls2080a devices are not hardwired and are
+ * programmed by sw. There are a limited number of stream IDs
+ * available, and the partitioning of them is scenario dependent.
+ * This header defines the partitioning between legacy, PCI,
+ * and DPAA2 devices.
+ *
+ * This partitiong can be customized in this file depending
+ * on the specific hardware config-- e.g. perhaps not all
+ * PEX controllers are in use.
+ *
+ * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for
+ * each of the different bus masters. The relationship between
+ * the AMQ registers and stream IDs is defined in the table below:
+ * AMQ bit streamID bit
+ * ---------------------------
+ * PL[18] 9
+ * BMT[17] 8
+ * VA[16] 7
+ * [15] -
+ * ICID[14:7] -
+ * ICID[6:0] 6-0
+ * ----------------------------
+ */
+
+#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
+#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
+
+#define FSL_INVALID_STREAM_ID 0
+
+#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
+
+/* legacy devices */
+#define FSL_USB1_STREAM_ID 1
+#define FSL_USB2_STREAM_ID 2
+#define FSL_SDMMC_STREAM_ID 3
+#define FSL_SATA1_STREAM_ID 4
+#define FSL_SATA2_STREAM_ID 5
+#define FSL_DMA_STREAM_ID 6
+
+/* PCI - programmed in PEXn_LUT by OS */
+/* 4 IDs per controller */
+#define FSL_PEX1_STREAM_ID_START 7
+#define FSL_PEX1_STREAM_ID_END 10
+#define FSL_PEX2_STREAM_ID_START 11
+#define FSL_PEX2_STREAM_ID_END 14
+#define FSL_PEX3_STREAM_ID_START 15
+#define FSL_PEX3_STREAM_ID_END 18
+#define FSL_PEX4_STREAM_ID_START 19
+#define FSL_PEX4_STREAM_ID_END 22
+
+/* DPAA2 - set in MC DPC and alloced by MC */
+#define FSL_DPAA2_STREAM_ID_START 23
+#define FSL_DPAA2_STREAM_ID_END 63
+
+#endif
+++ /dev/null
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- */
-#ifndef __FSL_STREAM_ID_H
-#define __FSL_STREAM_ID_H
-
-/* Stream IDs on ls2085a devices are not hardwired and are
- * programmed by sw. There are a limited number of stream IDs
- * available, and the partitioning of them is scenario dependent.
- * This header defines the partitioning between legacy, PCI,
- * and DPAA2 devices.
- *
- * This partitiong can be customized in this file depending
- * on the specific hardware config-- e.g. perhaps not all
- * PEX controllers are in use.
- *
- * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for
- * each of the different bus masters. The relationship between
- * the AMQ registers and stream IDs is defined in the table below:
- * AMQ bit streamID bit
- * ---------------------------
- * PL[18] 9
- * BMT[17] 8
- * VA[16] 7
- * [15] -
- * ICID[14:7] -
- * ICID[6:0] 6-0
- * ----------------------------
- */
-
-#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
-#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
-
-#define FSL_INVALID_STREAM_ID 0
-
-#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
-
-/* legacy devices */
-#define FSL_USB1_STREAM_ID 1
-#define FSL_USB2_STREAM_ID 2
-#define FSL_SDMMC_STREAM_ID 3
-#define FSL_SATA1_STREAM_ID 4
-#define FSL_SATA2_STREAM_ID 5
-#define FSL_DMA_STREAM_ID 6
-
-/* PCI - programmed in PEXn_LUT by OS */
-/* 4 IDs per controller */
-#define FSL_PEX1_STREAM_ID_START 7
-#define FSL_PEX1_STREAM_ID_END 10
-#define FSL_PEX2_STREAM_ID_START 11
-#define FSL_PEX2_STREAM_ID_END 14
-#define FSL_PEX3_STREAM_ID_START 15
-#define FSL_PEX3_STREAM_ID_END 18
-#define FSL_PEX4_STREAM_ID_START 19
-#define FSL_PEX4_STREAM_ID_END 22
-
-/* DPAA2 - set in MC DPC and alloced by MC */
-#define FSL_DPAA2_STREAM_ID_START 23
-#define FSL_DPAA2_STREAM_ID_END 63
-
-#endif
#define scfg_out32(a, v) out_be32(a, v)
#endif
+#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
+#define pex_lut_in32(a) in_le32(a)
+#define pex_lut_out32(a, v) out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
+#define pex_lut_in32(a) in_be32(a)
+#define pex_lut_out32(a, v) out_be32(a, v)
+#endif
+
struct cpu_type {
char name[15];
u32 soc_ver;
#endif
void cpu_name(char *name);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+void erratum_a009635(void);
+#endif
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
#endif
#if defined(CONFIG_SYS_NS16550_SERIAL)
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define RCWSR4_SRDS1_PRTCL_SHIFT 24
#define RCWSR4_SRDS1_PRTCL_MASK 0xff000000
-#define TIMER_COMP_VAL 0xffffffff
+#define TIMER_COMP_VAL 0xffffffffffffffffull
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
#define SYS_COUNTER_CTRL_ENABLE (1 << 24)
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK3036_H
+#define _ASM_ARCH_CRU_RK3036_H
+
+#include <common.h>
+
+#define OSC_HZ (24 * 1000 * 1000)
+
+#define APLL_HZ (600 * 1000000)
+#define GPLL_HZ (594 * 1000000)
+
+#define CORE_PERI_HZ 150000000
+#define CORE_ACLK_HZ 300000000
+
+#define CPU_ACLK_HZ 150000000
+#define CPU_HCLK_HZ 300000000
+#define CPU_PCLK_HZ 300000000
+
+#define PERI_ACLK_HZ 148500000
+#define PERI_HCLK_HZ 148500000
+#define PERI_PCLK_HZ 74250000
+
+struct rk3036_cru {
+ struct rk3036_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ } pll[4];
+ unsigned int cru_mode_con;
+ unsigned int cru_clksel_con[35];
+ unsigned int cru_clkgate_con[11];
+ unsigned int reserved;
+ unsigned int cru_glb_srst_fst_value;
+ unsigned int cru_glb_srst_snd_value;
+ unsigned int reserved1[2];
+ unsigned int cru_softrst_con[9];
+ unsigned int cru_misc_con;
+ unsigned int reserved2[2];
+ unsigned int cru_glb_cnt_th;
+ unsigned int cru_sdmmc_con[2];
+ unsigned int cru_sdio_con[2];
+ unsigned int cru_emmc_con[2];
+ unsigned int reserved3;
+ unsigned int cru_rst_st;
+ unsigned int reserved4[0x23];
+ unsigned int cru_pll_mask_con;
+};
+check_member(rk3036_cru, cru_pll_mask_con, 0x01f0);
+
+struct pll_div {
+ u32 refdiv;
+ u32 fbdiv;
+ u32 postdiv1;
+ u32 postdiv2;
+ u32 frac;
+};
+
+enum {
+ /* PLLCON0*/
+ PLL_POSTDIV1_MASK = 7,
+ PLL_POSTDIV1_SHIFT = 12,
+ PLL_FBDIV_MASK = 0xfff,
+ PLL_FBDIV_SHIFT = 0,
+
+ /* PLLCON1 */
+ PLL_DSMPD_MASK = 1,
+ PLL_DSMPD_SHIFT = 12,
+ PLL_LOCK_STATUS_MASK = 1,
+ PLL_LOCK_STATUS_SHIFT = 10,
+ PLL_POSTDIV2_MASK = 7,
+ PLL_POSTDIV2_SHIFT = 6,
+ PLL_REFDIV_MASK = 0x3f,
+ PLL_REFDIV_SHIFT = 0,
+ PLL_RST_SHIFT = 14,
+
+ /* CRU_MODE */
+ GPLL_MODE_MASK = 3,
+ GPLL_MODE_SHIFT = 12,
+ GPLL_MODE_SLOW = 0,
+ GPLL_MODE_NORM,
+ GPLL_MODE_DEEP,
+ DPLL_MODE_MASK = 1,
+ DPLL_MODE_SHIFT = 4,
+ DPLL_MODE_SLOW = 0,
+ DPLL_MODE_NORM,
+ APLL_MODE_MASK = 1,
+ APLL_MODE_SHIFT = 0,
+ APLL_MODE_SLOW = 0,
+ APLL_MODE_NORM,
+
+ /* CRU_CLK_SEL0_CON */
+ CPU_CLK_PLL_SEL_MASK = 3,
+ CPU_CLK_PLL_SEL_SHIFT = 14,
+ CPU_CLK_PLL_SEL_APLL = 0,
+ CPU_CLK_PLL_SEL_DPLL,
+ CPU_CLK_PLL_SEL_GPLL,
+ ACLK_CPU_DIV_MASK = 0x1f,
+ ACLK_CPU_DIV_SHIFT = 8,
+ CORE_CLK_PLL_SEL_MASK = 1,
+ CORE_CLK_PLL_SEL_SHIFT = 7,
+ CORE_CLK_PLL_SEL_APLL = 0,
+ CORE_CLK_PLL_SEL_GPLL,
+ CORE_DIV_CON_MASK = 0x1f,
+ CORE_DIV_CON_SHIFT = 0,
+
+ /* CRU_CLK_SEL1_CON */
+ CPU_PCLK_DIV_MASK = 7,
+ CPU_PCLK_DIV_SHIFT = 12,
+ CPU_HCLK_DIV_MASK = 3,
+ CPU_HCLK_DIV_SHIFT = 8,
+ CORE_ACLK_DIV_MASK = 7,
+ CORE_ACLK_DIV_SHIFT = 4,
+ CORE_PERI_DIV_MASK = 0xf,
+ CORE_PERI_DIV_SHIFT = 0,
+
+ /* CRU_CLKSEL10_CON */
+ PERI_PLL_SEL_MASK = 3,
+ PERI_PLL_SEL_SHIFT = 14,
+ PERI_PLL_APLL = 0,
+ PERI_PLL_DPLL,
+ PERI_PLL_GPLL,
+ PERI_PCLK_DIV_MASK = 3,
+ PERI_PCLK_DIV_SHIFT = 12,
+ PERI_HCLK_DIV_MASK = 3,
+ PERI_HCLK_DIV_SHIFT = 8,
+ PERI_ACLK_DIV_MASK = 0x1f,
+ PERI_ACLK_DIV_SHIFT = 0,
+
+ /* CRU_CLKSEL11_CON */
+ SDIO_DIV_MASK = 0x7f,
+ SDIO_DIV_SHIFT = 8,
+ MMC0_DIV_MASK = 0x7f,
+ MMC0_DIV_SHIFT = 0,
+
+ /* CRU_CLKSEL12_CON */
+ EMMC_PLL_MASK = 3,
+ EMMC_PLL_SHIFT = 12,
+ EMMC_SEL_APLL = 0,
+ EMMC_SEL_DPLL,
+ EMMC_SEL_GPLL,
+ EMMC_SEL_24M,
+ SDIO_PLL_MASK = 3,
+ SDIO_PLL_SHIFT = 10,
+ SDIO_SEL_APLL = 0,
+ SDIO_SEL_DPLL,
+ SDIO_SEL_GPLL,
+ SDIO_SEL_24M,
+ MMC0_PLL_MASK = 3,
+ MMC0_PLL_SHIFT = 8,
+ MMC0_SEL_APLL = 0,
+ MMC0_SEL_DPLL,
+ MMC0_SEL_GPLL,
+ MMC0_SEL_24M,
+ EMMC_DIV_MASK = 0x7f,
+ EMMC_DIV_SHIFT = 0,
+
+ /* CRU_SOFTRST5_CON */
+ DDRCTRL_PSRST_SHIFT = 11,
+ DDRCTRL_SRST_SHIFT = 10,
+ DDRPHY_PSRST_SHIFT = 9,
+ DDRPHY_SRST_SHIFT = 8,
+};
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_GRF_RK3036_H
+#define _ASM_ARCH_GRF_RK3036_H
+
+#include <common.h>
+
+struct rk3036_grf {
+ unsigned int reserved[0x2a];
+ unsigned int gpio0a_iomux;
+ unsigned int gpio0b_iomux;
+ unsigned int gpio0c_iomux;
+ unsigned int gpio0d_iomux;
+
+ unsigned int gpio1a_iomux;
+ unsigned int gpio1b_iomux;
+ unsigned int gpio1c_iomux;
+ unsigned int gpio1d_iomux;
+
+ unsigned int gpio2a_iomux;
+ unsigned int gpio2b_iomux;
+ unsigned int gpio2c_iomux;
+ unsigned int gpio2d_iomux;
+
+ unsigned int reserved2[0x0a];
+ unsigned int gpiods;
+ unsigned int reserved3[0x05];
+ unsigned int gpio0l_pull;
+ unsigned int gpio0h_pull;
+ unsigned int gpio1l_pull;
+ unsigned int gpio1h_pull;
+ unsigned int gpio2l_pull;
+ unsigned int gpio2h_pull;
+ unsigned int reserved4[4];
+ unsigned int soc_con0;
+ unsigned int soc_con1;
+ unsigned int soc_con2;
+ unsigned int soc_status0;
+ unsigned int reserved5;
+ unsigned int soc_con3;
+ unsigned int reserved6;
+ unsigned int dmac_con0;
+ unsigned int dmac_con1;
+ unsigned int dmac_con2;
+ unsigned int reserved7[5];
+ unsigned int uoc0_con5;
+ unsigned int reserved8[4];
+ unsigned int uoc1_con4;
+ unsigned int uoc1_con5;
+ unsigned int reserved9;
+ unsigned int ddrc_stat;
+ unsigned int uoc_con6;
+ unsigned int soc_status1;
+ unsigned int cpu_con0;
+ unsigned int cpu_con1;
+ unsigned int cpu_con2;
+ unsigned int cpu_con3;
+ unsigned int reserved10;
+ unsigned int reserved11;
+ unsigned int cpu_status0;
+ unsigned int cpu_status1;
+ unsigned int os_reg[8];
+ unsigned int reserved12[6];
+ unsigned int dll_con[4];
+ unsigned int dll_status[4];
+ unsigned int dfi_wrnum;
+ unsigned int dfi_rdnum;
+ unsigned int dfi_actnum;
+ unsigned int dfi_timerval;
+ unsigned int nfi_fifo[4];
+ unsigned int reserved13[0x10];
+ unsigned int usbphy0_con[8];
+ unsigned int usbphy1_con[8];
+ unsigned int reserved14[0x10];
+ unsigned int chip_tag;
+ unsigned int sdmmc_det_cnt;
+};
+check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
+
+/* GRF_GPIO0A_IOMUX */
+enum {
+ GPIO0A3_SHIFT = 6,
+ GPIO0A3_MASK = 1,
+ GPIO0A3_GPIO = 0,
+ GPIO0A3_I2C1_SDA,
+
+ GPIO0A2_SHIFT = 4,
+ GPIO0A2_MASK = 1,
+ GPIO0A2_GPIO = 0,
+ GPIO0A2_I2C1_SCL,
+
+ GPIO0A1_SHIFT = 2,
+ GPIO0A1_MASK = 3,
+ GPIO0A1_GPIO = 0,
+ GPIO0A1_I2C0_SDA,
+ GPIO0A1_PWM2,
+
+ GPIO0A0_SHIFT = 0,
+ GPIO0A0_MASK = 3,
+ GPIO0A0_GPIO = 0,
+ GPIO0A0_I2C0_SCL,
+ GPIO0A0_PWM1,
+
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+ GPIO0B6_SHIFT = 12,
+ GPIO0B6_MASK = 3,
+ GPIO0B6_GPIO = 0,
+ GPIO0B6_MMC1_D3,
+ GPIO0B6_I2S1_SCLK,
+
+ GPIO0B5_SHIFT = 10,
+ GPIO0B5_MASK = 3,
+ GPIO0B5_GPIO = 0,
+ GPIO0B5_MMC1_D2,
+ GPIO0B5_I2S1_SDI,
+
+ GPIO0B4_SHIFT = 8,
+ GPIO0B4_MASK = 3,
+ GPIO0B4_GPIO = 0,
+ GPIO0B4_MMC1_D1,
+ GPIO0B4_I2S1_LRCKTX,
+
+ GPIO0B3_SHIFT = 6,
+ GPIO0B3_MASK = 3,
+ GPIO0B3_GPIO = 0,
+ GPIO0B3_MMC1_D0,
+ GPIO0B3_I2S1_LRCKRX,
+
+ GPIO0B1_SHIFT = 2,
+ GPIO0B1_MASK = 3,
+ GPIO0B1_GPIO = 0,
+ GPIO0B1_MMC1_CLKOUT,
+ GPIO0B1_I2S1_MCLK,
+
+ GPIO0B0_SHIFT = 0,
+ GPIO0B0_MASK = 3,
+ GPIO0B0_GPIO = 0,
+ GPIO0B0_MMC1_CMD,
+ GPIO0B0_I2S1_SDO,
+};
+
+/* GRF_GPIO0C_IOMUX */
+enum {
+ GPIO0C4_SHIFT = 8,
+ GPIO0C4_MASK = 1,
+ GPIO0C4_GPIO = 0,
+ GPIO0C4_DRIVE_VBUS,
+
+ GPIO0C3_SHIFT = 6,
+ GPIO0C3_MASK = 1,
+ GPIO0C3_GPIO = 0,
+ GPIO0C3_UART0_CTSN,
+
+ GPIO0C2_SHIFT = 4,
+ GPIO0C2_MASK = 1,
+ GPIO0C2_GPIO = 0,
+ GPIO0C2_UART0_RTSN,
+
+ GPIO0C1_SHIFT = 2,
+ GPIO0C1_MASK = 1,
+ GPIO0C1_GPIO = 0,
+ GPIO0C1_UART0_SIN,
+
+
+ GPIO0C0_SHIFT = 0,
+ GPIO0C0_MASK = 1,
+ GPIO0C0_GPIO = 0,
+ GPIO0C0_UART0_SOUT,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+ GPIO0D4_SHIFT = 8,
+ GPIO0D4_MASK = 1,
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_SPDIF,
+
+ GPIO0D3_SHIFT = 6,
+ GPIO0D3_MASK = 1,
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_PWM3,
+
+ GPIO0D2_SHIFT = 4,
+ GPIO0D2_MASK = 1,
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_PWM0,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+ GPIO1A5_SHIFT = 10,
+ GPIO1A5_MASK = 1,
+ GPIO1A5_GPIO = 0,
+ GPIO1A5_I2S_SDI,
+
+ GPIO1A4_SHIFT = 8,
+ GPIO1A4_MASK = 1,
+ GPIO1A4_GPIO = 0,
+ GPIO1A4_I2S_SD0,
+
+ GPIO1A3_SHIFT = 6,
+ GPIO1A3_MASK = 1,
+ GPIO1A3_GPIO = 0,
+ GPIO1A3_I2S_LRCKTX,
+
+ GPIO1A2_SHIFT = 4,
+ GPIO1A2_MASK = 6,
+ GPIO1A2_GPIO = 0,
+ GPIO1A2_I2S_LRCKRX,
+ GPIO1A2_I2S_PWM1_0,
+
+ GPIO1A1_SHIFT = 2,
+ GPIO1A1_MASK = 1,
+ GPIO1A1_GPIO = 0,
+ GPIO1A1_I2S_SCLK,
+
+ GPIO1A0_SHIFT = 0,
+ GPIO1A0_MASK = 1,
+ GPIO1A0_GPIO = 0,
+ GPIO1A0_I2S_MCLK,
+
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = 1,
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_MMC0_CMD,
+
+ GPIO1B3_SHIFT = 6,
+ GPIO1B3_MASK = 1,
+ GPIO1B3_GPIO = 0,
+ GPIO1B3_HDMI_HPD,
+
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 1,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_HDMI_SCL,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 1,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_HDMI_SDA,
+
+ GPIO1B0_SHIFT = 0,
+ GPIO1B0_MASK = 1,
+ GPIO1B0_GPIO = 0,
+ GPIO1B0_HDMI_CEC,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C5_SHIFT = 10,
+ GPIO1C5_MASK = 3,
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_MMC0_D3,
+ GPIO1C5_JTAG_TMS,
+
+ GPIO1C4_SHIFT = 8,
+ GPIO1C4_MASK = 3,
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_MMC0_D2,
+ GPIO1C4_JTAG_TCK,
+
+ GPIO1C3_SHIFT = 6,
+ GPIO1C3_MASK = 3,
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_MMC0_D1,
+ GPIO1C3_UART2_SOUT,
+
+ GPIO1C2_SHIFT = 4,
+ GPIO1C2_MASK = 3,
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_MMC0_D0,
+ GPIO1C2_UART2_SIN,
+
+ GPIO1C1_SHIFT = 2,
+ GPIO1C1_MASK = 1,
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_MMC0_DETN,
+
+ GPIO1C0_SHIFT = 0,
+ GPIO1C0_MASK = 1,
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_MMC0_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+ GPIO1D7_SHIFT = 14,
+ GPIO1D7_MASK = 3,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_NAND_D7,
+ GPIO1D7_EMMC_D7,
+ GPIO1D7_SPI_CSN1,
+
+ GPIO1D6_SHIFT = 12,
+ GPIO1D6_MASK = 3,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_NAND_D6,
+ GPIO1D6_EMMC_D6,
+ GPIO1D6_SPI_CSN0,
+
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = 3,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_NAND_D5,
+ GPIO1D5_EMMC_D5,
+ GPIO1D5_SPI_TXD,
+
+ GPIO1D4_SHIFT = 8,
+ GPIO1D4_MASK = 3,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_NAND_D4,
+ GPIO1D4_EMMC_D4,
+ GPIO1D4_SPI_RXD,
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 3,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_NAND_D3,
+ GPIO1D3_EMMC_D3,
+ GPIO1D3_SFC_SIO3,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 3,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_NAND_D2,
+ GPIO1D2_EMMC_D2,
+ GPIO1D2_SFC_SIO2,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 3,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_NAND_D1,
+ GPIO1D1_EMMC_D1,
+ GPIO1D1_SFC_SIO1,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 3,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_NAND_D0,
+ GPIO1D0_EMMC_D0,
+ GPIO1D0_SFC_SIO0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+ GPIO2A7_SHIFT = 14,
+ GPIO2A7_MASK = 1,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_TESTCLK_OUT,
+
+ GPIO2A6_SHIFT = 12,
+ GPIO2A6_MASK = 1,
+ GPIO2A6_GPIO = 0,
+ GPIO2A6_NAND_CS0,
+
+ GPIO2A4_SHIFT = 8,
+ GPIO2A4_MASK = 3,
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_NAND_RDY,
+ GPIO2A4_EMMC_CMD,
+ GPIO2A3_SFC_CLK,
+
+ GPIO2A3_SHIFT = 6,
+ GPIO2A3_MASK = 3,
+ GPIO2A3_GPIO = 0,
+ GPIO2A3_NAND_RDN,
+ GPIO2A4_SFC_CSN1,
+
+ GPIO2A2_SHIFT = 4,
+ GPIO2A2_MASK = 3,
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_NAND_WRN,
+ GPIO2A4_SFC_CSN0,
+
+ GPIO2A1_SHIFT = 2,
+ GPIO2A1_MASK = 3,
+ GPIO2A1_GPIO = 0,
+ GPIO2A1_NAND_CLE,
+ GPIO2A1_EMMC_CLKOUT,
+
+ GPIO2A0_SHIFT = 0,
+ GPIO2A0_MASK = 3,
+ GPIO2A0_GPIO = 0,
+ GPIO2A0_NAND_ALE,
+ GPIO2A0_SPI_CLK,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+ GPIO2B7_SHIFT = 14,
+ GPIO2B7_MASK = 1,
+ GPIO2B7_GPIO = 0,
+ GPIO2B7_MAC_RXER,
+
+ GPIO2B6_SHIFT = 12,
+ GPIO2B6_MASK = 3,
+ GPIO2B6_GPIO = 0,
+ GPIO2B6_MAC_CLKOUT,
+ GPIO2B6_MAC_CLKIN,
+
+ GPIO2B5_SHIFT = 10,
+ GPIO2B5_MASK = 1,
+ GPIO2B5_GPIO = 0,
+ GPIO2B5_MAC_TXEN,
+
+ GPIO2B4_SHIFT = 8,
+ GPIO2B4_MASK = 1,
+ GPIO2B4_GPIO = 0,
+ GPIO2B4_MAC_MDIO,
+
+ GPIO2B2_SHIFT = 4,
+ GPIO2B2_MASK = 1,
+ GPIO2B2_GPIO = 0,
+ GPIO2B2_MAC_CRS,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+ GPIO2C7_SHIFT = 14,
+ GPIO2C7_MASK = 3,
+ GPIO2C7_GPIO = 0,
+ GPIO2C7_UART1_SOUT,
+ GPIO2C7_TESTCLK_OUT1,
+
+ GPIO2C6_SHIFT = 12,
+ GPIO2C6_MASK = 1,
+ GPIO2C6_GPIO = 0,
+ GPIO2C6_UART1_SIN,
+
+ GPIO2C5_SHIFT = 10,
+ GPIO2C5_MASK = 1,
+ GPIO2C5_GPIO = 0,
+ GPIO2C5_I2C2_SCL,
+
+ GPIO2C4_SHIFT = 8,
+ GPIO2C4_MASK = 1,
+ GPIO2C4_GPIO = 0,
+ GPIO2C4_I2C2_SDA,
+
+ GPIO2C3_SHIFT = 6,
+ GPIO2C3_MASK = 1,
+ GPIO2C3_GPIO = 0,
+ GPIO2C3_MAC_TXD0,
+
+ GPIO2C2_SHIFT = 4,
+ GPIO2C2_MASK = 1,
+ GPIO2C2_GPIO = 0,
+ GPIO2C2_MAC_TXD1,
+
+ GPIO2C1_SHIFT = 2,
+ GPIO2C1_MASK = 1,
+ GPIO2C1_GPIO = 0,
+ GPIO2C1_MAC_RXD0,
+
+ GPIO2C0_SHIFT = 0,
+ GPIO2C0_MASK = 1,
+ GPIO2C0_GPIO = 0,
+ GPIO2C0_MAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2D6_SHIFT = 12,
+ GPIO2D6_MASK = 1,
+ GPIO2D6_GPIO = 0,
+ GPIO2D6_I2S_SDO1,
+
+ GPIO2D5_SHIFT = 10,
+ GPIO2D5_MASK = 1,
+ GPIO2D5_GPIO = 0,
+ GPIO2D5_I2S_SDO2,
+
+ GPIO2D4_SHIFT = 8,
+ GPIO2D4_MASK = 1,
+ GPIO2D4_GPIO = 0,
+ GPIO2D4_I2S_SDO3,
+
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 1,
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_MAC_MDC,
+};
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_SDRAM_RK3036_H
+#define _ASM_ARCH_SDRAM_RK3036_H
+
+#include <common.h>
+
+struct rk3036_ddr_pctl {
+ u32 scfg;
+ u32 sctl;
+ u32 stat;
+ u32 intrstat;
+ u32 reserved0[12];
+ u32 mcmd;
+ u32 powctl;
+ u32 powstat;
+ u32 cmdtstat;
+ u32 cmdtstaten;
+ u32 reserved1[3];
+ u32 mrrcfg0;
+ u32 mrrstat0;
+ u32 mrrstat1;
+ u32 reserved2[4];
+ u32 mcfg1;
+ u32 mcfg;
+ u32 ppcfg;
+ u32 mstat;
+ u32 lpddr2zqcfg;
+ u32 reserved3;
+ u32 dtupdes;
+ u32 dtuna;
+ u32 dtune;
+ u32 dtuprd0;
+ u32 dtuprd1;
+ u32 dtuprd2;
+ u32 dtuprd3;
+ u32 dtuawdt;
+ u32 reserved4[3];
+ u32 togcnt1u;
+ u32 tinit;
+ u32 trsth;
+ u32 togcnt100n;
+ u32 trefi;
+ u32 tmrd;
+ u32 trfc;
+ u32 trp;
+ u32 trtw;
+ u32 tal;
+ u32 tcl;
+ u32 tcwl;
+ u32 tras;
+ u32 trc;
+ u32 trcd;
+ u32 trrd;
+ u32 trtp;
+ u32 twr;
+ u32 twtr;
+ u32 texsr;
+ u32 txp;
+ u32 txpdll;
+ u32 tzqcs;
+ u32 tzqcsi;
+ u32 tdqs;
+ u32 tcksre;
+ u32 tcksrx;
+ u32 tcke;
+ u32 tmod;
+ u32 trstl;
+ u32 tzqcl;
+ u32 tmrr;
+ u32 tckesr;
+ u32 reserved5[47];
+ u32 dtuwactl;
+ u32 dturactl;
+ u32 dtucfg;
+ u32 dtuectl;
+ u32 dtuwd0;
+ u32 dtuwd1;
+ u32 dtuwd2;
+ u32 dtuwd3;
+ u32 dtuwdm;
+ u32 dturd0;
+ u32 dturd1;
+ u32 dturd2;
+ u32 dturd3;
+ u32 dtulfsrwd;
+ u32 dtulfsrrd;
+ u32 dtueaf;
+ u32 dfitctrldelay;
+ u32 dfiodtcfg;
+ u32 dfiodtcfg1;
+ u32 dfiodtrankmap;
+ u32 dfitphywrdata;
+ u32 dfitphywrlat;
+ u32 reserved7[2];
+ u32 dfitrddataen;
+ u32 dfitphyrdlat;
+ u32 reserved8[2];
+ u32 dfitphyupdtype0;
+ u32 dfitphyupdtype1;
+ u32 dfitphyupdtype2;
+ u32 dfitphyupdtype3;
+ u32 dfitctrlupdmin;
+ u32 dfitctrlupdmax;
+ u32 dfitctrlupddly;
+ u32 reserved9;
+ u32 dfiupdcfg;
+ u32 dfitrefmski;
+ u32 dfitctrlupdi;
+ u32 reserved10[4];
+ u32 dfitrcfg0;
+ u32 dfitrstat0;
+ u32 dfitrwrlvlen;
+ u32 dfitrrdlvlen;
+ u32 dfitrrdlvlgateen;
+ u32 dfiststat0;
+ u32 dfistcfg0;
+ u32 dfistcfg1;
+ u32 reserved11;
+ u32 dfitdramclken;
+ u32 dfitdramclkdis;
+ u32 dfistcfg2;
+ u32 dfistparclr;
+ u32 dfistparlog;
+ u32 reserved12[3];
+ u32 dfilpcfg0;
+ u32 reserved13[3];
+ u32 dfitrwrlvlresp0;
+ u32 dfitrwrlvlresp1;
+ u32 dfitrwrlvlresp2;
+ u32 dfitrrdlvlresp0;
+ u32 dfitrrdlvlresp1;
+ u32 dfitrrdlvlresp2;
+ u32 dfitrwrlvldelay0;
+ u32 dfitrwrlvldelay1;
+ u32 dfitrwrlvldelay2;
+ u32 dfitrrdlvldelay0;
+ u32 dfitrrdlvldelay1;
+ u32 dfitrrdlvldelay2;
+ u32 dfitrrdlvlgatedelay0;
+ u32 dfitrrdlvlgatedelay1;
+ u32 dfitrrdlvlgatedelay2;
+ u32 dfitrcmd;
+ u32 reserved14[46];
+ u32 ipvr;
+ u32 iptr;
+};
+check_member(rk3036_ddr_pctl, iptr, 0x03fc);
+
+struct rk3036_ddr_phy {
+ u32 ddrphy_reg1;
+ u32 ddrphy_reg3;
+ u32 ddrphy_reg2;
+ u32 reserve[11];
+ u32 ddrphy_reg4a;
+ u32 ddrphy_reg4b;
+ u32 reserve1[5];
+ u32 ddrphy_reg16;
+ u32 reserve2;
+ u32 ddrphy_reg18;
+ u32 ddrphy_reg19;
+ u32 reserve3;
+ u32 ddrphy_reg21;
+ u32 reserve4;
+ u32 ddrphy_reg22;
+ u32 reserve5[3];
+ u32 ddrphy_reg25;
+ u32 ddrphy_reg26;
+ u32 ddrphy_reg27;
+ u32 ddrphy_reg28;
+ u32 reserve6[17];
+ u32 ddrphy_reg6;
+ u32 ddrphy_reg7;
+ u32 reserve7;
+ u32 ddrphy_reg8;
+ u32 ddrphy_reg0e4;
+ u32 reserve8[11];
+ u32 ddrphy_reg9;
+ u32 ddrphy_reg10;
+ u32 reserve9;
+ u32 ddrphy_reg11;
+ u32 ddrphy_reg124;
+ u32 reserve10[38];
+ u32 ddrphy_reg29;
+ u32 reserve11[40];
+ u32 ddrphy_reg264;
+ u32 reserve12[18];
+ u32 ddrphy_reg2a;
+ u32 reserve13[4];
+ u32 ddrphy_reg30;
+ u32 ddrphy_reg31;
+ u32 ddrphy_reg32;
+ u32 ddrphy_reg33;
+ u32 ddrphy_reg34;
+ u32 ddrphy_reg35;
+ u32 ddrphy_reg36;
+ u32 ddrphy_reg37;
+ u32 ddrphy_reg38;
+ u32 ddrphy_reg39;
+ u32 ddrphy_reg40;
+ u32 ddrphy_reg41;
+ u32 ddrphy_reg42;
+ u32 ddrphy_reg43;
+ u32 ddrphy_reg44;
+ u32 ddrphy_reg45;
+ u32 ddrphy_reg46;
+ u32 ddrphy_reg47;
+ u32 ddrphy_reg48;
+ u32 ddrphy_reg49;
+ u32 ddrphy_reg50;
+ u32 ddrphy_reg51;
+ u32 ddrphy_reg52;
+ u32 ddrphy_reg53;
+ u32 reserve14;
+ u32 ddrphy_reg54;
+ u32 ddrphy_reg55;
+ u32 ddrphy_reg56;
+ u32 ddrphy_reg57;
+ u32 ddrphy_reg58;
+ u32 ddrphy_reg59;
+ u32 ddrphy_reg5a;
+ u32 ddrphy_reg5b;
+ u32 ddrphy_reg5c;
+ u32 ddrphy_reg5d;
+ u32 ddrphy_reg5e;
+ u32 reserve15[28];
+ u32 ddrphy_reg5f;
+ u32 reserve16[6];
+ u32 ddrphy_reg60;
+ u32 ddrphy_reg61;
+ u32 ddrphy_reg62;
+};
+check_member(rk3036_ddr_phy, ddrphy_reg62, 0x03e8);
+
+struct rk3036_pctl_timing {
+ u32 togcnt1u;
+ u32 tinit;
+ u32 trsth;
+ u32 togcnt100n;
+ u32 trefi;
+ u32 tmrd;
+ u32 trfc;
+ u32 trp;
+ u32 trtw;
+ u32 tal;
+ u32 tcl;
+ u32 tcwl;
+ u32 tras;
+ u32 trc;
+ u32 trcd;
+ u32 trrd;
+ u32 trtp;
+ u32 twr;
+ u32 twtr;
+ u32 texsr;
+ u32 txp;
+ u32 txpdll;
+ u32 tzqcs;
+ u32 tzqcsi;
+ u32 tdqs;
+ u32 tcksre;
+ u32 tcksrx;
+ u32 tcke;
+ u32 tmod;
+ u32 trstl;
+ u32 tzqcl;
+ u32 tmrr;
+ u32 tckesr;
+ u32 tdpd;
+};
+
+struct rk3036_phy_timing {
+ u32 mr[4];
+ u32 bl;
+ u32 cl_al;
+};
+
+typedef union {
+ u32 noc_timing;
+ struct {
+ u32 acttoact:6;
+ u32 rdtomiss:6;
+ u32 wrtomiss:6;
+ u32 burstlen:3;
+ u32 rdtowr:5;
+ u32 wrtord:5;
+ u32 bwratio:1;
+ };
+} rk3036_noc_timing;
+
+struct rk3036_ddr_timing {
+ u32 freq;
+ struct rk3036_pctl_timing pctl_timing;
+ struct rk3036_phy_timing phy_timing;
+ rk3036_noc_timing noc_timing;
+};
+
+struct rk3036_service_sys {
+ u32 id_coreid;
+ u32 id_revisionid;
+ u32 ddrconf;
+ u32 ddrtiming;
+ u32 ddrmode;
+ u32 readlatency;
+};
+
+struct rk3036_ddr_config {
+ /*
+ * 000: lpddr
+ * 001: ddr
+ * 010: ddr2
+ * 011: ddr3
+ * 100: lpddr2-s2
+ * 101: lpddr2-s4
+ * 110: lpddr3
+ */
+ u32 ddr_type;
+ u32 rank;
+ u32 cs0_row;
+ u32 cs1_row;
+
+ /* 2: 4bank, 3: 8bank */
+ u32 bank;
+ u32 col;
+
+ /* bw(0: 8bit, 1: 16bit, 2: 32bit) */
+ u32 bw;
+};
+
+/* rk3036 sdram initial */
+void sdram_init(void);
+
+/* get ddr die config, implement in specific board */
+void get_ddr_config(struct rk3036_ddr_config *config);
+
+/* get ddr size on board */
+size_t sdram_size(void);
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_TIMER_H
+#define __ASM_ARCH_TIMER_H
+
+struct rk_timer {
+ unsigned int timer_load_count0;
+ unsigned int timer_load_count1;
+ unsigned int timer_curr_value0;
+ unsigned int timer_curr_value1;
+ unsigned int timer_ctrl_reg;
+ unsigned int timer_int_status;
+};
+
+void rockchip_timer_init(void);
+void rockchip_udelay(unsigned int usec);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_UART_H
+#define __ASM_ARCH_UART_H
+struct rk_uart {
+ unsigned int rbr; /* Receive buffer register. */
+ unsigned int ier; /* Interrupt enable register. */
+ unsigned int fcr; /* FIFO control register. */
+ unsigned int lcr; /* Line control register. */
+ unsigned int mcr; /* Modem control register. */
+ unsigned int lsr; /* Line status register. */
+ unsigned int msr; /* Modem status register. */
+ unsigned int scr;
+ unsigned int reserved1[(0x30 - 0x20) / 4];
+ unsigned int srbr[(0x70 - 0x30) / 4];
+ unsigned int far;
+ unsigned int tfr;
+ unsigned int rfw;
+ unsigned int usr;
+ unsigned int tfl;
+ unsigned int rfl;
+ unsigned int srr;
+ unsigned int srts;
+ unsigned int sbcr;
+ unsigned int sdmam;
+ unsigned int sfe;
+ unsigned int srt;
+ unsigned int stet;
+ unsigned int htx;
+ unsigned int dmasa;
+ unsigned int reserver2[(0xf4 - 0xac) / 4];
+ unsigned int cpr;
+ unsigned int ucv;
+ unsigned int ctr;
+};
+
+void rk_uart_init(void *base);
+void print_hex(unsigned int n);
+void print(char *s);
+#endif
+++ /dev/null
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_CLK_H_
-#define __ASM_ARM_ARCH_CLK_H_
-
-#define APLL 0
-#define MPLL 1
-#define EPLL 2
-#define HPLL 3
-#define VPLL 4
-
-unsigned long get_pll_clk(int pllreg);
-unsigned long get_arm_clk(void);
-unsigned long get_pwm_clk(void);
-unsigned long get_uart_clk(int dev_index);
-void set_mmc_clk(int dev_index, unsigned int div);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_CLOCK_H_
-#define __ASM_ARM_ARCH_CLOCK_H_
-
-#ifndef __ASSEMBLY__
-struct s5pc100_clock {
- unsigned int apll_lock;
- unsigned int mpll_lock;
- unsigned int epll_lock;
- unsigned int hpll_lock;
- unsigned char res1[0xf0];
- unsigned int apll_con;
- unsigned int mpll_con;
- unsigned int epll_con;
- unsigned int hpll_con;
- unsigned char res2[0xf0];
- unsigned int src0;
- unsigned int src1;
- unsigned int src2;
- unsigned int src3;
- unsigned char res3[0xf0];
- unsigned int div0;
- unsigned int div1;
- unsigned int div2;
- unsigned int div3;
- unsigned int div4;
- unsigned char res4[0x1ec];
- unsigned int gate_d00;
- unsigned int gate_d01;
- unsigned int gate_d02;
- unsigned char res5[0x54];
- unsigned int gate_sclk0;
- unsigned int gate_sclk1;
-};
-
-struct s5pc110_clock {
- unsigned int apll_lock;
- unsigned char res1[0x4];
- unsigned int mpll_lock;
- unsigned char res2[0x4];
- unsigned int epll_lock;
- unsigned char res3[0xc];
- unsigned int vpll_lock;
- unsigned char res4[0xdc];
- unsigned int apll_con;
- unsigned char res5[0x4];
- unsigned int mpll_con;
- unsigned char res6[0x4];
- unsigned int epll_con;
- unsigned char res7[0xc];
- unsigned int vpll_con;
- unsigned char res8[0xdc];
- unsigned int src0;
- unsigned int src1;
- unsigned int src2;
- unsigned int src3;
- unsigned char res9[0xf0];
- unsigned int div0;
- unsigned int div1;
- unsigned int div2;
- unsigned int div3;
- unsigned int div4;
- unsigned char res10[0x1ec];
- unsigned int gate_d00;
- unsigned int gate_d01;
- unsigned int gate_d02;
- unsigned char res11[0x54];
- unsigned int gate_sclk0;
- unsigned int gate_sclk1;
-};
-#endif
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _S5PC1XX_CPU_H
-#define _S5PC1XX_CPU_H
-
-#define S5P_CPU_NAME "S5P"
-#define S5PC1XX_ADDR_BASE 0xE0000000
-
-/* S5PC100 */
-#define S5PC100_PRO_ID 0xE0000000
-#define S5PC100_CLOCK_BASE 0xE0100000
-#define S5PC100_GPIO_BASE 0xE0300000
-#define S5PC100_VIC0_BASE 0xE4000000
-#define S5PC100_VIC1_BASE 0xE4100000
-#define S5PC100_VIC2_BASE 0xE4200000
-#define S5PC100_DMC_BASE 0xE6000000
-#define S5PC100_SROMC_BASE 0xE7000000
-#define S5PC100_ONENAND_BASE 0xE7100000
-#define S5PC100_PWMTIMER_BASE 0xEA000000
-#define S5PC100_WATCHDOG_BASE 0xEA200000
-#define S5PC100_UART_BASE 0xEC000000
-#define S5PC100_MMC_BASE 0xED800000
-
-/* S5PC110 */
-#define S5PC110_PRO_ID 0xE0000000
-#define S5PC110_CLOCK_BASE 0xE0100000
-#define S5PC110_GPIO_BASE 0xE0200000
-#define S5PC110_PWMTIMER_BASE 0xE2500000
-#define S5PC110_WATCHDOG_BASE 0xE2700000
-#define S5PC110_UART_BASE 0xE2900000
-#define S5PC110_SROMC_BASE 0xE8000000
-#define S5PC110_MMC_BASE 0xEB000000
-#define S5PC110_DMC0_BASE 0xF0000000
-#define S5PC110_DMC1_BASE 0xF1400000
-#define S5PC110_VIC0_BASE 0xF2000000
-#define S5PC110_VIC1_BASE 0xF2100000
-#define S5PC110_VIC2_BASE 0xF2200000
-#define S5PC110_VIC3_BASE 0xF2300000
-#define S5PC110_OTG_BASE 0xEC000000
-#define S5PC110_PHY_BASE 0xEC100000
-#define S5PC110_USB_PHY_CONTROL 0xE010E80C
-
-
-#ifndef __ASSEMBLY__
-#include <asm/io.h>
-/* CPU detection macros */
-extern unsigned int s5p_cpu_id;
-extern unsigned int s5p_cpu_rev;
-
-static inline int s5p_get_cpu_rev(void)
-{
- return s5p_cpu_rev;
-}
-
-static inline void s5p_set_cpu_id(void)
-{
- s5p_cpu_id = readl(S5PC100_PRO_ID);
- s5p_cpu_rev = s5p_cpu_id & 0x000000FF;
- s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
-}
-
-static inline char *s5p_get_cpu_name(void)
-{
- return S5P_CPU_NAME;
-}
-
-#define IS_SAMSUNG_TYPE(type, id) \
-static inline int cpu_is_##type(void) \
-{ \
- return s5p_cpu_id == id ? 1 : 0; \
-}
-
-IS_SAMSUNG_TYPE(s5pc100, 0xc100)
-IS_SAMSUNG_TYPE(s5pc110, 0xc110)
-
-#define SAMSUNG_BASE(device, base) \
-static inline unsigned int samsung_get_base_##device(void) \
-{ \
- if (cpu_is_s5pc100()) \
- return S5PC100_##base; \
- else if (cpu_is_s5pc110()) \
- return S5PC110_##base; \
- else \
- return 0; \
-}
-
-SAMSUNG_BASE(clock, CLOCK_BASE)
-SAMSUNG_BASE(gpio, GPIO_BASE)
-SAMSUNG_BASE(pro_id, PRO_ID)
-SAMSUNG_BASE(mmc, MMC_BASE)
-SAMSUNG_BASE(sromc, SROMC_BASE)
-SAMSUNG_BASE(timer, PWMTIMER_BASE)
-SAMSUNG_BASE(uart, UART_BASE)
-SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
-#endif
-
-#endif /* _S5PC1XX_CPU_H */
+++ /dev/null
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#ifndef __ASSEMBLY__
-struct s5p_gpio_bank {
- unsigned int con;
- unsigned int dat;
- unsigned int pull;
- unsigned int drv;
- unsigned int pdn_con;
- unsigned int pdn_pull;
- unsigned char res1[8];
-};
-
-/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
-enum s5pc100_gpio_pin {
- S5PC100_GPIO_A00,
- S5PC100_GPIO_A01,
- S5PC100_GPIO_A02,
- S5PC100_GPIO_A03,
- S5PC100_GPIO_A04,
- S5PC100_GPIO_A05,
- S5PC100_GPIO_A06,
- S5PC100_GPIO_A07,
- S5PC100_GPIO_A10,
- S5PC100_GPIO_A11,
- S5PC100_GPIO_A12,
- S5PC100_GPIO_A13,
- S5PC100_GPIO_A14,
- S5PC100_GPIO_A15,
- S5PC100_GPIO_A16,
- S5PC100_GPIO_A17,
- S5PC100_GPIO_B0,
- S5PC100_GPIO_B1,
- S5PC100_GPIO_B2,
- S5PC100_GPIO_B3,
- S5PC100_GPIO_B4,
- S5PC100_GPIO_B5,
- S5PC100_GPIO_B6,
- S5PC100_GPIO_B7,
- S5PC100_GPIO_C0,
- S5PC100_GPIO_C1,
- S5PC100_GPIO_C2,
- S5PC100_GPIO_C3,
- S5PC100_GPIO_C4,
- S5PC100_GPIO_C5,
- S5PC100_GPIO_C6,
- S5PC100_GPIO_C7,
- S5PC100_GPIO_D0,
- S5PC100_GPIO_D1,
- S5PC100_GPIO_D2,
- S5PC100_GPIO_D3,
- S5PC100_GPIO_D4,
- S5PC100_GPIO_D5,
- S5PC100_GPIO_D6,
- S5PC100_GPIO_D7,
- S5PC100_GPIO_E00,
- S5PC100_GPIO_E01,
- S5PC100_GPIO_E02,
- S5PC100_GPIO_E03,
- S5PC100_GPIO_E04,
- S5PC100_GPIO_E05,
- S5PC100_GPIO_E06,
- S5PC100_GPIO_E07,
- S5PC100_GPIO_E10,
- S5PC100_GPIO_E11,
- S5PC100_GPIO_E12,
- S5PC100_GPIO_E13,
- S5PC100_GPIO_E14,
- S5PC100_GPIO_E15,
- S5PC100_GPIO_E16,
- S5PC100_GPIO_E17,
- S5PC100_GPIO_F00,
- S5PC100_GPIO_F01,
- S5PC100_GPIO_F02,
- S5PC100_GPIO_F03,
- S5PC100_GPIO_F04,
- S5PC100_GPIO_F05,
- S5PC100_GPIO_F06,
- S5PC100_GPIO_F07,
- S5PC100_GPIO_F10,
- S5PC100_GPIO_F11,
- S5PC100_GPIO_F12,
- S5PC100_GPIO_F13,
- S5PC100_GPIO_F14,
- S5PC100_GPIO_F15,
- S5PC100_GPIO_F16,
- S5PC100_GPIO_F17,
- S5PC100_GPIO_F20,
- S5PC100_GPIO_F21,
- S5PC100_GPIO_F22,
- S5PC100_GPIO_F23,
- S5PC100_GPIO_F24,
- S5PC100_GPIO_F25,
- S5PC100_GPIO_F26,
- S5PC100_GPIO_F27,
- S5PC100_GPIO_F30,
- S5PC100_GPIO_F31,
- S5PC100_GPIO_F32,
- S5PC100_GPIO_F33,
- S5PC100_GPIO_F34,
- S5PC100_GPIO_F35,
- S5PC100_GPIO_F36,
- S5PC100_GPIO_F37,
- S5PC100_GPIO_G00,
- S5PC100_GPIO_G01,
- S5PC100_GPIO_G02,
- S5PC100_GPIO_G03,
- S5PC100_GPIO_G04,
- S5PC100_GPIO_G05,
- S5PC100_GPIO_G06,
- S5PC100_GPIO_G07,
- S5PC100_GPIO_G10,
- S5PC100_GPIO_G11,
- S5PC100_GPIO_G12,
- S5PC100_GPIO_G13,
- S5PC100_GPIO_G14,
- S5PC100_GPIO_G15,
- S5PC100_GPIO_G16,
- S5PC100_GPIO_G17,
- S5PC100_GPIO_G20,
- S5PC100_GPIO_G21,
- S5PC100_GPIO_G22,
- S5PC100_GPIO_G23,
- S5PC100_GPIO_G24,
- S5PC100_GPIO_G25,
- S5PC100_GPIO_G26,
- S5PC100_GPIO_G27,
- S5PC100_GPIO_G30,
- S5PC100_GPIO_G31,
- S5PC100_GPIO_G32,
- S5PC100_GPIO_G33,
- S5PC100_GPIO_G34,
- S5PC100_GPIO_G35,
- S5PC100_GPIO_G36,
- S5PC100_GPIO_G37,
- S5PC100_GPIO_I0,
- S5PC100_GPIO_I1,
- S5PC100_GPIO_I2,
- S5PC100_GPIO_I3,
- S5PC100_GPIO_I4,
- S5PC100_GPIO_I5,
- S5PC100_GPIO_I6,
- S5PC100_GPIO_I7,
- S5PC100_GPIO_J00,
- S5PC100_GPIO_J01,
- S5PC100_GPIO_J02,
- S5PC100_GPIO_J03,
- S5PC100_GPIO_J04,
- S5PC100_GPIO_J05,
- S5PC100_GPIO_J06,
- S5PC100_GPIO_J07,
- S5PC100_GPIO_J10,
- S5PC100_GPIO_J11,
- S5PC100_GPIO_J12,
- S5PC100_GPIO_J13,
- S5PC100_GPIO_J14,
- S5PC100_GPIO_J15,
- S5PC100_GPIO_J16,
- S5PC100_GPIO_J17,
- S5PC100_GPIO_J20,
- S5PC100_GPIO_J21,
- S5PC100_GPIO_J22,
- S5PC100_GPIO_J23,
- S5PC100_GPIO_J24,
- S5PC100_GPIO_J25,
- S5PC100_GPIO_J26,
- S5PC100_GPIO_J27,
- S5PC100_GPIO_J30,
- S5PC100_GPIO_J31,
- S5PC100_GPIO_J32,
- S5PC100_GPIO_J33,
- S5PC100_GPIO_J34,
- S5PC100_GPIO_J35,
- S5PC100_GPIO_J36,
- S5PC100_GPIO_J37,
- S5PC100_GPIO_J40,
- S5PC100_GPIO_J41,
- S5PC100_GPIO_J42,
- S5PC100_GPIO_J43,
- S5PC100_GPIO_J44,
- S5PC100_GPIO_J45,
- S5PC100_GPIO_J46,
- S5PC100_GPIO_J47,
- S5PC100_GPIO_K00,
- S5PC100_GPIO_K01,
- S5PC100_GPIO_K02,
- S5PC100_GPIO_K03,
- S5PC100_GPIO_K04,
- S5PC100_GPIO_K05,
- S5PC100_GPIO_K06,
- S5PC100_GPIO_K07,
- S5PC100_GPIO_K10,
- S5PC100_GPIO_K11,
- S5PC100_GPIO_K12,
- S5PC100_GPIO_K13,
- S5PC100_GPIO_K14,
- S5PC100_GPIO_K15,
- S5PC100_GPIO_K16,
- S5PC100_GPIO_K17,
- S5PC100_GPIO_K20,
- S5PC100_GPIO_K21,
- S5PC100_GPIO_K22,
- S5PC100_GPIO_K23,
- S5PC100_GPIO_K24,
- S5PC100_GPIO_K25,
- S5PC100_GPIO_K26,
- S5PC100_GPIO_K27,
- S5PC100_GPIO_K30,
- S5PC100_GPIO_K31,
- S5PC100_GPIO_K32,
- S5PC100_GPIO_K33,
- S5PC100_GPIO_K34,
- S5PC100_GPIO_K35,
- S5PC100_GPIO_K36,
- S5PC100_GPIO_K37,
- S5PC100_GPIO_L00,
- S5PC100_GPIO_L01,
- S5PC100_GPIO_L02,
- S5PC100_GPIO_L03,
- S5PC100_GPIO_L04,
- S5PC100_GPIO_L05,
- S5PC100_GPIO_L06,
- S5PC100_GPIO_L07,
- S5PC100_GPIO_L10,
- S5PC100_GPIO_L11,
- S5PC100_GPIO_L12,
- S5PC100_GPIO_L13,
- S5PC100_GPIO_L14,
- S5PC100_GPIO_L15,
- S5PC100_GPIO_L16,
- S5PC100_GPIO_L17,
- S5PC100_GPIO_L20,
- S5PC100_GPIO_L21,
- S5PC100_GPIO_L22,
- S5PC100_GPIO_L23,
- S5PC100_GPIO_L24,
- S5PC100_GPIO_L25,
- S5PC100_GPIO_L26,
- S5PC100_GPIO_L27,
- S5PC100_GPIO_L30,
- S5PC100_GPIO_L31,
- S5PC100_GPIO_L32,
- S5PC100_GPIO_L33,
- S5PC100_GPIO_L34,
- S5PC100_GPIO_L35,
- S5PC100_GPIO_L36,
- S5PC100_GPIO_L37,
- S5PC100_GPIO_L40,
- S5PC100_GPIO_L41,
- S5PC100_GPIO_L42,
- S5PC100_GPIO_L43,
- S5PC100_GPIO_L44,
- S5PC100_GPIO_L45,
- S5PC100_GPIO_L46,
- S5PC100_GPIO_L47,
- S5PC100_GPIO_H00,
- S5PC100_GPIO_H01,
- S5PC100_GPIO_H02,
- S5PC100_GPIO_H03,
- S5PC100_GPIO_H04,
- S5PC100_GPIO_H05,
- S5PC100_GPIO_H06,
- S5PC100_GPIO_H07,
- S5PC100_GPIO_H10,
- S5PC100_GPIO_H11,
- S5PC100_GPIO_H12,
- S5PC100_GPIO_H13,
- S5PC100_GPIO_H14,
- S5PC100_GPIO_H15,
- S5PC100_GPIO_H16,
- S5PC100_GPIO_H17,
- S5PC100_GPIO_H20,
- S5PC100_GPIO_H21,
- S5PC100_GPIO_H22,
- S5PC100_GPIO_H23,
- S5PC100_GPIO_H24,
- S5PC100_GPIO_H25,
- S5PC100_GPIO_H26,
- S5PC100_GPIO_H27,
- S5PC100_GPIO_H30,
- S5PC100_GPIO_H31,
- S5PC100_GPIO_H32,
- S5PC100_GPIO_H33,
- S5PC100_GPIO_H34,
- S5PC100_GPIO_H35,
- S5PC100_GPIO_H36,
- S5PC100_GPIO_H37,
-
- S5PC100_GPIO_MAX_PORT
-};
-
-enum s5pc110_gpio_pin {
- S5PC110_GPIO_A00,
- S5PC110_GPIO_A01,
- S5PC110_GPIO_A02,
- S5PC110_GPIO_A03,
- S5PC110_GPIO_A04,
- S5PC110_GPIO_A05,
- S5PC110_GPIO_A06,
- S5PC110_GPIO_A07,
- S5PC110_GPIO_A10,
- S5PC110_GPIO_A11,
- S5PC110_GPIO_A12,
- S5PC110_GPIO_A13,
- S5PC110_GPIO_A14,
- S5PC110_GPIO_A15,
- S5PC110_GPIO_A16,
- S5PC110_GPIO_A17,
- S5PC110_GPIO_B0,
- S5PC110_GPIO_B1,
- S5PC110_GPIO_B2,
- S5PC110_GPIO_B3,
- S5PC110_GPIO_B4,
- S5PC110_GPIO_B5,
- S5PC110_GPIO_B6,
- S5PC110_GPIO_B7,
- S5PC110_GPIO_C00,
- S5PC110_GPIO_C01,
- S5PC110_GPIO_C02,
- S5PC110_GPIO_C03,
- S5PC110_GPIO_C04,
- S5PC110_GPIO_C05,
- S5PC110_GPIO_C06,
- S5PC110_GPIO_C07,
- S5PC110_GPIO_C10,
- S5PC110_GPIO_C11,
- S5PC110_GPIO_C12,
- S5PC110_GPIO_C13,
- S5PC110_GPIO_C14,
- S5PC110_GPIO_C15,
- S5PC110_GPIO_C16,
- S5PC110_GPIO_C17,
- S5PC110_GPIO_D00,
- S5PC110_GPIO_D01,
- S5PC110_GPIO_D02,
- S5PC110_GPIO_D03,
- S5PC110_GPIO_D04,
- S5PC110_GPIO_D05,
- S5PC110_GPIO_D06,
- S5PC110_GPIO_D07,
- S5PC110_GPIO_D10,
- S5PC110_GPIO_D11,
- S5PC110_GPIO_D12,
- S5PC110_GPIO_D13,
- S5PC110_GPIO_D14,
- S5PC110_GPIO_D15,
- S5PC110_GPIO_D16,
- S5PC110_GPIO_D17,
- S5PC110_GPIO_E00,
- S5PC110_GPIO_E01,
- S5PC110_GPIO_E02,
- S5PC110_GPIO_E03,
- S5PC110_GPIO_E04,
- S5PC110_GPIO_E05,
- S5PC110_GPIO_E06,
- S5PC110_GPIO_E07,
- S5PC110_GPIO_E10,
- S5PC110_GPIO_E11,
- S5PC110_GPIO_E12,
- S5PC110_GPIO_E13,
- S5PC110_GPIO_E14,
- S5PC110_GPIO_E15,
- S5PC110_GPIO_E16,
- S5PC110_GPIO_E17,
- S5PC110_GPIO_F00,
- S5PC110_GPIO_F01,
- S5PC110_GPIO_F02,
- S5PC110_GPIO_F03,
- S5PC110_GPIO_F04,
- S5PC110_GPIO_F05,
- S5PC110_GPIO_F06,
- S5PC110_GPIO_F07,
- S5PC110_GPIO_F10,
- S5PC110_GPIO_F11,
- S5PC110_GPIO_F12,
- S5PC110_GPIO_F13,
- S5PC110_GPIO_F14,
- S5PC110_GPIO_F15,
- S5PC110_GPIO_F16,
- S5PC110_GPIO_F17,
- S5PC110_GPIO_F20,
- S5PC110_GPIO_F21,
- S5PC110_GPIO_F22,
- S5PC110_GPIO_F23,
- S5PC110_GPIO_F24,
- S5PC110_GPIO_F25,
- S5PC110_GPIO_F26,
- S5PC110_GPIO_F27,
- S5PC110_GPIO_F30,
- S5PC110_GPIO_F31,
- S5PC110_GPIO_F32,
- S5PC110_GPIO_F33,
- S5PC110_GPIO_F34,
- S5PC110_GPIO_F35,
- S5PC110_GPIO_F36,
- S5PC110_GPIO_F37,
- S5PC110_GPIO_G00,
- S5PC110_GPIO_G01,
- S5PC110_GPIO_G02,
- S5PC110_GPIO_G03,
- S5PC110_GPIO_G04,
- S5PC110_GPIO_G05,
- S5PC110_GPIO_G06,
- S5PC110_GPIO_G07,
- S5PC110_GPIO_G10,
- S5PC110_GPIO_G11,
- S5PC110_GPIO_G12,
- S5PC110_GPIO_G13,
- S5PC110_GPIO_G14,
- S5PC110_GPIO_G15,
- S5PC110_GPIO_G16,
- S5PC110_GPIO_G17,
- S5PC110_GPIO_G20,
- S5PC110_GPIO_G21,
- S5PC110_GPIO_G22,
- S5PC110_GPIO_G23,
- S5PC110_GPIO_G24,
- S5PC110_GPIO_G25,
- S5PC110_GPIO_G26,
- S5PC110_GPIO_G27,
- S5PC110_GPIO_G30,
- S5PC110_GPIO_G31,
- S5PC110_GPIO_G32,
- S5PC110_GPIO_G33,
- S5PC110_GPIO_G34,
- S5PC110_GPIO_G35,
- S5PC110_GPIO_G36,
- S5PC110_GPIO_G37,
- S5PC110_GPIO_I0,
- S5PC110_GPIO_I1,
- S5PC110_GPIO_I2,
- S5PC110_GPIO_I3,
- S5PC110_GPIO_I4,
- S5PC110_GPIO_I5,
- S5PC110_GPIO_I6,
- S5PC110_GPIO_I7,
- S5PC110_GPIO_J00,
- S5PC110_GPIO_J01,
- S5PC110_GPIO_J02,
- S5PC110_GPIO_J03,
- S5PC110_GPIO_J04,
- S5PC110_GPIO_J05,
- S5PC110_GPIO_J06,
- S5PC110_GPIO_J07,
- S5PC110_GPIO_J10,
- S5PC110_GPIO_J11,
- S5PC110_GPIO_J12,
- S5PC110_GPIO_J13,
- S5PC110_GPIO_J14,
- S5PC110_GPIO_J15,
- S5PC110_GPIO_J16,
- S5PC110_GPIO_J17,
- S5PC110_GPIO_J20,
- S5PC110_GPIO_J21,
- S5PC110_GPIO_J22,
- S5PC110_GPIO_J23,
- S5PC110_GPIO_J24,
- S5PC110_GPIO_J25,
- S5PC110_GPIO_J26,
- S5PC110_GPIO_J27,
- S5PC110_GPIO_J30,
- S5PC110_GPIO_J31,
- S5PC110_GPIO_J32,
- S5PC110_GPIO_J33,
- S5PC110_GPIO_J34,
- S5PC110_GPIO_J35,
- S5PC110_GPIO_J36,
- S5PC110_GPIO_J37,
- S5PC110_GPIO_J40,
- S5PC110_GPIO_J41,
- S5PC110_GPIO_J42,
- S5PC110_GPIO_J43,
- S5PC110_GPIO_J44,
- S5PC110_GPIO_J45,
- S5PC110_GPIO_J46,
- S5PC110_GPIO_J47,
- S5PC110_GPIO_MP010,
- S5PC110_GPIO_MP011,
- S5PC110_GPIO_MP012,
- S5PC110_GPIO_MP013,
- S5PC110_GPIO_MP014,
- S5PC110_GPIO_MP015,
- S5PC110_GPIO_MP016,
- S5PC110_GPIO_MP017,
- S5PC110_GPIO_MP020,
- S5PC110_GPIO_MP021,
- S5PC110_GPIO_MP022,
- S5PC110_GPIO_MP023,
- S5PC110_GPIO_MP024,
- S5PC110_GPIO_MP025,
- S5PC110_GPIO_MP026,
- S5PC110_GPIO_MP027,
- S5PC110_GPIO_MP030,
- S5PC110_GPIO_MP031,
- S5PC110_GPIO_MP032,
- S5PC110_GPIO_MP033,
- S5PC110_GPIO_MP034,
- S5PC110_GPIO_MP035,
- S5PC110_GPIO_MP036,
- S5PC110_GPIO_MP037,
- S5PC110_GPIO_MP040,
- S5PC110_GPIO_MP041,
- S5PC110_GPIO_MP042,
- S5PC110_GPIO_MP043,
- S5PC110_GPIO_MP044,
- S5PC110_GPIO_MP045,
- S5PC110_GPIO_MP046,
- S5PC110_GPIO_MP047,
- S5PC110_GPIO_MP050,
- S5PC110_GPIO_MP051,
- S5PC110_GPIO_MP052,
- S5PC110_GPIO_MP053,
- S5PC110_GPIO_MP054,
- S5PC110_GPIO_MP055,
- S5PC110_GPIO_MP056,
- S5PC110_GPIO_MP057,
- S5PC110_GPIO_MP060,
- S5PC110_GPIO_MP061,
- S5PC110_GPIO_MP062,
- S5PC110_GPIO_MP063,
- S5PC110_GPIO_MP064,
- S5PC110_GPIO_MP065,
- S5PC110_GPIO_MP066,
- S5PC110_GPIO_MP067,
- S5PC110_GPIO_MP070,
- S5PC110_GPIO_MP071,
- S5PC110_GPIO_MP072,
- S5PC110_GPIO_MP073,
- S5PC110_GPIO_MP074,
- S5PC110_GPIO_MP075,
- S5PC110_GPIO_MP076,
- S5PC110_GPIO_MP077,
- S5PC110_GPIO_MP100,
- S5PC110_GPIO_MP101,
- S5PC110_GPIO_MP102,
- S5PC110_GPIO_MP103,
- S5PC110_GPIO_MP104,
- S5PC110_GPIO_MP105,
- S5PC110_GPIO_MP106,
- S5PC110_GPIO_MP107,
- S5PC110_GPIO_MP110,
- S5PC110_GPIO_MP111,
- S5PC110_GPIO_MP112,
- S5PC110_GPIO_MP113,
- S5PC110_GPIO_MP114,
- S5PC110_GPIO_MP115,
- S5PC110_GPIO_MP116,
- S5PC110_GPIO_MP117,
- S5PC110_GPIO_MP120,
- S5PC110_GPIO_MP121,
- S5PC110_GPIO_MP122,
- S5PC110_GPIO_MP123,
- S5PC110_GPIO_MP124,
- S5PC110_GPIO_MP125,
- S5PC110_GPIO_MP126,
- S5PC110_GPIO_MP127,
- S5PC110_GPIO_MP130,
- S5PC110_GPIO_MP131,
- S5PC110_GPIO_MP132,
- S5PC110_GPIO_MP133,
- S5PC110_GPIO_MP134,
- S5PC110_GPIO_MP135,
- S5PC110_GPIO_MP136,
- S5PC110_GPIO_MP137,
- S5PC110_GPIO_MP140,
- S5PC110_GPIO_MP141,
- S5PC110_GPIO_MP142,
- S5PC110_GPIO_MP143,
- S5PC110_GPIO_MP144,
- S5PC110_GPIO_MP145,
- S5PC110_GPIO_MP146,
- S5PC110_GPIO_MP147,
- S5PC110_GPIO_MP150,
- S5PC110_GPIO_MP151,
- S5PC110_GPIO_MP152,
- S5PC110_GPIO_MP153,
- S5PC110_GPIO_MP154,
- S5PC110_GPIO_MP155,
- S5PC110_GPIO_MP156,
- S5PC110_GPIO_MP157,
- S5PC110_GPIO_MP160,
- S5PC110_GPIO_MP161,
- S5PC110_GPIO_MP162,
- S5PC110_GPIO_MP163,
- S5PC110_GPIO_MP164,
- S5PC110_GPIO_MP165,
- S5PC110_GPIO_MP166,
- S5PC110_GPIO_MP167,
- S5PC110_GPIO_MP170,
- S5PC110_GPIO_MP171,
- S5PC110_GPIO_MP172,
- S5PC110_GPIO_MP173,
- S5PC110_GPIO_MP174,
- S5PC110_GPIO_MP175,
- S5PC110_GPIO_MP176,
- S5PC110_GPIO_MP177,
- S5PC110_GPIO_MP180,
- S5PC110_GPIO_MP181,
- S5PC110_GPIO_MP182,
- S5PC110_GPIO_MP183,
- S5PC110_GPIO_MP184,
- S5PC110_GPIO_MP185,
- S5PC110_GPIO_MP186,
- S5PC110_GPIO_MP187,
- S5PC110_GPIO_MP200,
- S5PC110_GPIO_MP201,
- S5PC110_GPIO_MP202,
- S5PC110_GPIO_MP203,
- S5PC110_GPIO_MP204,
- S5PC110_GPIO_MP205,
- S5PC110_GPIO_MP206,
- S5PC110_GPIO_MP207,
- S5PC110_GPIO_MP210,
- S5PC110_GPIO_MP211,
- S5PC110_GPIO_MP212,
- S5PC110_GPIO_MP213,
- S5PC110_GPIO_MP214,
- S5PC110_GPIO_MP215,
- S5PC110_GPIO_MP216,
- S5PC110_GPIO_MP217,
- S5PC110_GPIO_MP220,
- S5PC110_GPIO_MP221,
- S5PC110_GPIO_MP222,
- S5PC110_GPIO_MP223,
- S5PC110_GPIO_MP224,
- S5PC110_GPIO_MP225,
- S5PC110_GPIO_MP226,
- S5PC110_GPIO_MP227,
- S5PC110_GPIO_MP230,
- S5PC110_GPIO_MP231,
- S5PC110_GPIO_MP232,
- S5PC110_GPIO_MP233,
- S5PC110_GPIO_MP234,
- S5PC110_GPIO_MP235,
- S5PC110_GPIO_MP236,
- S5PC110_GPIO_MP237,
- S5PC110_GPIO_MP240,
- S5PC110_GPIO_MP241,
- S5PC110_GPIO_MP242,
- S5PC110_GPIO_MP243,
- S5PC110_GPIO_MP244,
- S5PC110_GPIO_MP245,
- S5PC110_GPIO_MP246,
- S5PC110_GPIO_MP247,
- S5PC110_GPIO_MP250,
- S5PC110_GPIO_MP251,
- S5PC110_GPIO_MP252,
- S5PC110_GPIO_MP253,
- S5PC110_GPIO_MP254,
- S5PC110_GPIO_MP255,
- S5PC110_GPIO_MP256,
- S5PC110_GPIO_MP257,
- S5PC110_GPIO_MP260,
- S5PC110_GPIO_MP261,
- S5PC110_GPIO_MP262,
- S5PC110_GPIO_MP263,
- S5PC110_GPIO_MP264,
- S5PC110_GPIO_MP265,
- S5PC110_GPIO_MP266,
- S5PC110_GPIO_MP267,
- S5PC110_GPIO_MP270,
- S5PC110_GPIO_MP271,
- S5PC110_GPIO_MP272,
- S5PC110_GPIO_MP273,
- S5PC110_GPIO_MP274,
- S5PC110_GPIO_MP275,
- S5PC110_GPIO_MP276,
- S5PC110_GPIO_MP277,
- S5PC110_GPIO_MP280,
- S5PC110_GPIO_MP281,
- S5PC110_GPIO_MP282,
- S5PC110_GPIO_MP283,
- S5PC110_GPIO_MP284,
- S5PC110_GPIO_MP285,
- S5PC110_GPIO_MP286,
- S5PC110_GPIO_MP287,
- S5PC110_GPIO_H00,
- S5PC110_GPIO_H01,
- S5PC110_GPIO_H02,
- S5PC110_GPIO_H03,
- S5PC110_GPIO_H04,
- S5PC110_GPIO_H05,
- S5PC110_GPIO_H06,
- S5PC110_GPIO_H07,
- S5PC110_GPIO_H10,
- S5PC110_GPIO_H11,
- S5PC110_GPIO_H12,
- S5PC110_GPIO_H13,
- S5PC110_GPIO_H14,
- S5PC110_GPIO_H15,
- S5PC110_GPIO_H16,
- S5PC110_GPIO_H17,
- S5PC110_GPIO_H20,
- S5PC110_GPIO_H21,
- S5PC110_GPIO_H22,
- S5PC110_GPIO_H23,
- S5PC110_GPIO_H24,
- S5PC110_GPIO_H25,
- S5PC110_GPIO_H26,
- S5PC110_GPIO_H27,
- S5PC110_GPIO_H30,
- S5PC110_GPIO_H31,
- S5PC110_GPIO_H32,
- S5PC110_GPIO_H33,
- S5PC110_GPIO_H34,
- S5PC110_GPIO_H35,
- S5PC110_GPIO_H36,
- S5PC110_GPIO_H37,
-
- S5PC110_GPIO_MAX_PORT
-};
-
-struct gpio_info {
- unsigned int reg_addr; /* Address of register for this part */
- unsigned int max_gpio; /* Maximum GPIO in this part */
-};
-
-#define S5PC100_GPIO_NUM_PARTS 1
-static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = {
- { S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT },
-};
-
-#define S5PC110_GPIO_NUM_PARTS 1
-static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = {
- { S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT },
-};
-
-static inline struct gpio_info *get_gpio_data(void)
-{
- if (cpu_is_s5pc100())
- return s5pc100_gpio_data;
- else if (cpu_is_s5pc110())
- return s5pc110_gpio_data;
-
- return NULL;
-}
-
-static inline unsigned int get_bank_num(void)
-{
- if (cpu_is_s5pc100())
- return S5PC100_GPIO_NUM_PARTS;
- else if (cpu_is_s5pc110())
- return S5PC110_GPIO_NUM_PARTS;
-
- return 0;
-}
-
-/*
- * This structure helps mapping symbolic GPIO names into indices from
- * exynos5_gpio_pin/exynos5420_gpio_pin enums.
- *
- * By convention, symbolic GPIO name is defined as follows:
- *
- * g[p]<bank><set><bit>, where
- * p is optional
- * <bank> - a single character bank name, as defined by the SOC
- * <set> - a single digit set number
- * <bit> - bit number within the set (in 0..7 range).
- *
- * <set><bit> essentially form an octal number of the GPIO pin within the bank
- * space. On the 5420 architecture some banks' sets do not start not from zero
- * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
- * maintain flat number space withoout holes, those banks use offsets to be
- * deducted from the pin number.
- */
-struct gpio_name_num_table {
- char bank; /* bank name symbol */
- u8 bank_size; /* total number of pins in the bank */
- char bank_offset; /* offset of the first bank's pin */
- unsigned int base; /* index of the first bank's pin in the enum */
-};
-
-#define GPIO_PER_BANK 8
-#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
-static const struct gpio_name_num_table s5pc100_gpio_table[] = {
- GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0),
- GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0),
- GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0),
- GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0),
- GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0),
- GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0),
- GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0),
- GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0),
- GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0),
- GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0),
- GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0),
- GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0),
- { 0 }
-};
-
-static const struct gpio_name_num_table s5pc110_gpio_table[] = {
- GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0),
- GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0),
- GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0),
- GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0),
- GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0),
- GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0),
- GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0),
- GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0),
- GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0),
- GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0),
- { 0 }
-};
-
-/* functions */
-void gpio_cfg_pin(int gpio, int cfg);
-void gpio_set_pull(int gpio, int mode);
-void gpio_set_drv(int gpio, int mode);
-void gpio_set_rate(int gpio, int mode);
-int s5p_gpio_get_pin(unsigned gpio);
-
-/* GPIO pins per bank */
-#define GPIO_PER_BANK 8
-#endif
-
-/* Pin configurations */
-#define S5P_GPIO_INPUT 0x0
-#define S5P_GPIO_OUTPUT 0x1
-#define S5P_GPIO_IRQ 0xf
-#define S5P_GPIO_FUNC(x) (x)
-
-/* Pull mode */
-#define S5P_GPIO_PULL_NONE 0x0
-#define S5P_GPIO_PULL_DOWN 0x1
-#define S5P_GPIO_PULL_UP 0x2
-
-/* Drive Strength level */
-#define S5P_GPIO_DRV_1X 0x0
-#define S5P_GPIO_DRV_3X 0x1
-#define S5P_GPIO_DRV_2X 0x2
-#define S5P_GPIO_DRV_4X 0x3
-#define S5P_GPIO_DRV_FAST 0x0
-#define S5P_GPIO_DRV_SLOW 0x1
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MMC_H_
-#define __ASM_ARCH_MMC_H_
-
-#define S5P_MMC_DEV_OFFSET 0x100000
-
-#define SDHCI_CONTROL2 0x80
-#define SDHCI_CONTROL3 0x84
-#define SDHCI_CONTROL4 0x8C
-
-#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
-#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
-#define SDHCI_CTRL2_CDINVRXD3 (1 << 29)
-#define SDHCI_CTRL2_SLCARDOUT (1 << 28)
-
-#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
-#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
-#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
-
-#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
-#define SDHCI_CTRL2_LVLDAT_SHIFT (16)
-#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
-
-#define SDHCI_CTRL2_ENFBCLKTX (1 << 15)
-#define SDHCI_CTRL2_ENFBCLKRX (1 << 14)
-#define SDHCI_CTRL2_SDCDSEL (1 << 13)
-#define SDHCI_CTRL2_SDSIGPC (1 << 12)
-#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
-
-#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9)
-#define SDHCI_CTRL2_DFCNT_SHIFT (9)
-
-#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
-#define SDHCI_CTRL2_RWAITMODE (1 << 7)
-#define SDHCI_CTRL2_DISBUFRD (1 << 6)
-#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4)
-#define SDHCI_CTRL2_SELBASECLK_SHIFT (4)
-#define SDHCI_CTRL2_PWRSYNC (1 << 3)
-#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
-#define SDHCI_CTRL2_HWINITFIN (1 << 0)
-
-#define SDHCI_CTRL3_FCSEL3 (1 << 31)
-#define SDHCI_CTRL3_FCSEL2 (1 << 23)
-#define SDHCI_CTRL3_FCSEL1 (1 << 15)
-#define SDHCI_CTRL3_FCSEL0 (1 << 7)
-
-#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
-#define SDHCI_CTRL4_DRIVE_SHIFT (16)
-
-int s5p_sdhci_init(u32 regbase, int index, int bus_width);
-
-static inline int s5p_mmc_init(int index, int bus_width)
-{
- unsigned int base = samsung_get_base_mmc() +
- (S5P_MMC_DEV_OFFSET * index);
-
- return s5p_sdhci_init(base, index, bus_width);
-}
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Rajeshwari Shinde <rajeshwari.s@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PERIPH_H
-#define __ASM_ARM_ARCH_PERIPH_H
-
-/*
- * Peripherals required for pinmux configuration. List will
- * grow with support for more devices getting added.
- * Numbering based on interrupt table.
- *
- */
-enum periph_id {
- PERIPH_ID_UART0 = 51,
- PERIPH_ID_UART1,
- PERIPH_ID_UART2,
- PERIPH_ID_UART3,
- PERIPH_ID_I2C0 = 56,
- PERIPH_ID_I2C1,
- PERIPH_ID_I2C2,
- PERIPH_ID_I2C3,
- PERIPH_ID_I2C4,
- PERIPH_ID_I2C5,
- PERIPH_ID_I2C6,
- PERIPH_ID_I2C7,
- PERIPH_ID_SPI0 = 68,
- PERIPH_ID_SPI1,
- PERIPH_ID_SPI2,
- PERIPH_ID_SDMMC0 = 75,
- PERIPH_ID_SDMMC1,
- PERIPH_ID_SDMMC2,
- PERIPH_ID_SDMMC3,
- PERIPH_ID_I2C8 = 87,
- PERIPH_ID_I2C9,
- PERIPH_ID_I2S0 = 98,
- PERIPH_ID_I2S1 = 99,
-
- /* Since following peripherals do
- * not have shared peripheral interrupts (SPIs)
- * they are numbered arbitiraly after the maximum
- * SPIs Exynos has (128)
- */
- PERIPH_ID_SROMC = 128,
- PERIPH_ID_SPI3,
- PERIPH_ID_SPI4,
- PERIPH_ID_SDMMC4,
- PERIPH_ID_PWM0,
- PERIPH_ID_PWM1,
- PERIPH_ID_PWM2,
- PERIPH_ID_PWM3,
- PERIPH_ID_PWM4,
- PERIPH_ID_I2C10 = 203,
-
- PERIPH_ID_NONE = -1,
-};
-
-#endif /* __ASM_ARM_ARCH_PERIPH_H */
+++ /dev/null
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Abhilash Kesavan <a.kesavan@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PINMUX_H
-#define __ASM_ARM_ARCH_PINMUX_H
-
-#include "periph.h"
-
-/*
- * Flags for setting specific configarations of peripherals.
- * List will grow with support for more devices getting added.
- */
-enum {
- PINMUX_FLAG_NONE = 0x00000000,
-
- /* Flags for eMMC */
- PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
-
- /* Flags for SROM controller */
- PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
- PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
-};
-
-/**
- * Configures the pinmux for a particular peripheral.
- *
- * Each gpio can be configured in many different ways (4 bits on exynos)
- * such as "input", "output", "special function", "external interrupt"
- * etc. This function will configure the peripheral pinmux along with
- * pull-up/down and drive strength.
- *
- * @param peripheral peripheral to be configured
- * @param flags configure flags
- * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
- */
-int exynos_pinmux_config(int peripheral, int flags);
-
-/**
- * Decode the peripheral id using the interrpt numbers.
- *
- * @param blob Device tree blob
- * @param node FDT I2C node to find
- * @return peripheral id if ok, PERIPH_ID_NONE on error
- */
-int pinmux_decode_periph_id(const void *blob, int node);
-#endif
+++ /dev/null
-/*
- * Copyright (c) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_POWER_H_
-#define __ASM_ARM_ARCH_POWER_H_
-
-/*
- * Power control
- */
-#define S5PC100_OTHERS 0xE0108200
-#define S5PC100_RST_STAT 0xE0108300
-#define S5PC100_SLEEP_WAKEUP (1 << 3)
-#define S5PC100_WAKEUP_STAT 0xE0108304
-#define S5PC100_INFORM0 0xE0108400
-
-#define S5PC110_RST_STAT 0xE010A000
-#define S5PC110_SLEEP_WAKEUP (1 << 3)
-#define S5PC110_WAKEUP_STAT 0xE010C200
-#define S5PC110_OTHERS 0xE010E000
-#define S5PC110_USB_PHY_CON 0xE010E80C
-#define S5PC110_INFORM0 0xE010F000
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PWM_H_
-#define __ASM_ARM_ARCH_PWM_H_
-
-#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
-#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
-
-/* Divider MUX */
-#define MUX_DIV_1 0 /* 1/1 period */
-#define MUX_DIV_2 1 /* 1/2 period */
-#define MUX_DIV_4 2 /* 1/4 period */
-#define MUX_DIV_8 3 /* 1/8 period */
-#define MUX_DIV_16 4 /* 1/16 period */
-
-#define MUX_DIV_SHIFT(x) (x * 4)
-
-#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
-
-#define TCON_START(x) (1 << TCON_OFFSET(x))
-#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
-#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
-#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
-#define TCON4_AUTO_RELOAD (1 << 22)
-
-#ifndef __ASSEMBLY__
-struct s5p_timer {
- unsigned int tcfg0;
- unsigned int tcfg1;
- unsigned int tcon;
- unsigned int tcntb0;
- unsigned int tcmpb0;
- unsigned int tcnto0;
- unsigned int tcntb1;
- unsigned int tcmpb1;
- unsigned int tcnto1;
- unsigned int tcntb2;
- unsigned int tcmpb2;
- unsigned int tcnto2;
- unsigned int tcntb3;
- unsigned int res1;
- unsigned int tcnto3;
- unsigned int tcntb4;
- unsigned int tcnto4;
- unsigned int tintcstat;
-};
-#endif /* __ASSEMBLY__ */
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.naveen@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Note: This file contains the register description for Memory subsystem
- * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
- *
- * Only SROMC is defined as of now
- */
-
-#ifndef __ASM_ARCH_SROMC_H_
-#define __ASM_ARCH_SROMC_H_
-
-#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
-#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
- /* 1-> Byte base address*/
-#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
-#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
-
-#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
-#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
-#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
-#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
-#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
-#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
-#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
-
-#ifndef __ASSEMBLY__
-struct s5p_sromc {
- unsigned int bw;
- unsigned int bc[6];
-};
-#endif /* __ASSEMBLY__ */
-
-/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
-void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
-
-#endif /* __ASM_ARCH_SMC_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2009 Samsung Electrnoics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-u32 get_device_type(void);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_UART_H_
-#define __ASM_ARCH_UART_H_
-
-#ifndef __ASSEMBLY__
-/* baudrate rest value */
-union br_rest {
- unsigned short slot; /* udivslot */
- unsigned char value; /* ufracval */
-};
-
-struct s5p_uart {
- unsigned int ulcon;
- unsigned int ucon;
- unsigned int ufcon;
- unsigned int umcon;
- unsigned int utrstat;
- unsigned int uerstat;
- unsigned int ufstat;
- unsigned int umstat;
- unsigned char utxh;
- unsigned char res1[3];
- unsigned char urxh;
- unsigned char res2[3];
- unsigned int ubrdiv;
- union br_rest rest;
- unsigned char res3[0x3d0];
-};
-
-static inline int s5p_uart_divslot(void)
-{
- return 1;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2011 Samsung Electronics
- * Heungjun Kim <riverful.kim@samsung.com>
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_WATCHDOG_H_
-#define __ASM_ARM_ARCH_WATCHDOG_H_
-
-#define WTCON_RESET_OFFSET 0
-#define WTCON_INTEN_OFFSET 2
-#define WTCON_CLKSEL_OFFSET 3
-#define WTCON_EN_OFFSET 5
-#define WTCON_PRE_OFFSET 8
-
-#define WTCON_CLK_16 0x0
-#define WTCON_CLK_32 0x1
-#define WTCON_CLK_64 0x2
-#define WTCON_CLK_128 0x3
-
-#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET)
-#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET)
-#define WTCON_EN (0x1 << WTCON_EN_OFFSET)
-#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
-#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
-
-#ifndef __ASSEMBLY__
-struct s5p_watchdog {
- unsigned int wtcon;
- unsigned int wtdat;
- unsigned int wtcnt;
- unsigned int wtclrint;
-};
-
-/* functions */
-void wdt_stop(void);
-void wdt_start(unsigned int timeout);
-#endif /* __ASSEMBLY__ */
-
-#endif
#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
#define CCM_PLL6_CTRL_K_SHIFT 4
#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_LOCK (1 << 28)
#define CCM_MIPI_PLL_CTRL_M_SHIFT 0
#define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)
#define CCM_PLL11_CTRL_UPD (0x1 << 30)
#define CCM_PLL11_CTRL_EN (0x1 << 31)
-#define AHB1_ABP1_DIV_DEFAULT 0x00002020
+#if defined CONFIG_MACH_SUN8I_H3
+#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
+#else
+#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */
+#endif
#define AXI_GATE_OFFSET_DRAM 0
#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0)
#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
+#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20)
+#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20)
+#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20)
#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
#include <asm/arch/dram_sun8i_a23.h>
#elif defined(CONFIG_MACH_SUN8I_A33)
#include <asm/arch/dram_sun8i_a33.h>
+#elif defined(CONFIG_MACH_SUN8I_H3)
+#include <asm/arch/dram_sun8i_h3.h>
#else
#include <asm/arch/dram_sun4i.h>
#endif
--- /dev/null
+/*
+ * sun8i H3 platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_H3_H
+#define _SUNXI_DRAM_SUN8I_H3_H
+
+struct sunxi_mctl_com_reg {
+ u32 cr; /* 0x00 control register */
+ u8 res0[0xc]; /* 0x04 */
+ u32 mcr[16][2]; /* 0x10 */
+ u32 bwcr; /* 0x90 bandwidth control register */
+ u32 maer; /* 0x94 master enable register */
+ u32 mapr; /* 0x98 master priority register */
+ u32 mcgcr; /* 0x9c */
+ u32 cpu_bwcr; /* 0xa0 */
+ u32 gpu_bwcr; /* 0xa4 */
+ u32 ve_bwcr; /* 0xa8 */
+ u32 disp_bwcr; /* 0xac */
+ u32 other_bwcr; /* 0xb0 */
+ u32 total_bwcr; /* 0xb4 */
+ u8 res1[0x8]; /* 0xb8 */
+ u32 swonr; /* 0xc0 */
+ u32 swoffr; /* 0xc4 */
+ u8 res2[0x8]; /* 0xc8 */
+ u32 cccr; /* 0xd0 */
+ u8 res3[0x72c]; /* 0xd4 */
+ u32 protect; /* 0x800 */
+};
+
+#define MCTL_CR_BL8 (0x4 << 20)
+
+#define MCTL_CR_1T (0x1 << 19)
+#define MCTL_CR_2T (0x0 << 19)
+
+#define MCTL_CR_LPDDR3 (0x7 << 16)
+#define MCTL_CR_LPDDR2 (0x6 << 16)
+#define MCTL_CR_DDR3 (0x3 << 16)
+#define MCTL_CR_DDR2 (0x2 << 16)
+
+#define MCTL_CR_SEQUENTIAL (0x1 << 15)
+#define MCTL_CR_INTERLEAVED (0x0 << 15)
+
+#define MCTL_CR_32BIT (0x1 << 12)
+#define MCTL_CR_16BIT (0x0 << 12)
+#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT)
+
+#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
+#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4)
+#define MCTL_CR_EIGHT_BANKS (0x1 << 2)
+#define MCTL_CR_FOUR_BANKS (0x0 << 2)
+#define MCTL_CR_DUAL_RANK (0x1 << 0)
+#define MCTL_CR_SINGLE_RANK (0x0 << 0)
+
+#define PROTECT_MAGIC (0x94be6fa3)
+
+struct sunxi_mctl_ctl_reg {
+ u32 pir; /* 0x00 PHY initialization register */
+ u32 pwrctl; /* 0x04 */
+ u32 mrctrl; /* 0x08 */
+ u32 clken; /* 0x0c */
+ u32 pgsr[2]; /* 0x10 PHY general status registers */
+ u32 statr; /* 0x18 */
+ u8 res1[0x14]; /* 0x1c */
+ u32 mr[4]; /* 0x30 mode registers */
+ u32 pllgcr; /* 0x40 */
+ u32 ptr[5]; /* 0x44 PHY timing registers */
+ u32 dramtmg[9]; /* 0x58 DRAM timing registers */
+ u32 odtcfg; /* 0x7c */
+ u32 pitmg[2]; /* 0x80 PHY interface timing registers */
+ u8 res2[0x4]; /* 0x88 */
+ u32 rfshctl0; /* 0x8c */
+ u32 rfshtmg; /* 0x90 refresh timing */
+ u32 rfshctl1; /* 0x94 */
+ u32 pwrtmg; /* 0x98 */
+ u8 res3[0x20]; /* 0x9c */
+ u32 dqsgmr; /* 0xbc */
+ u32 dtcr; /* 0xc0 */
+ u32 dtar[4]; /* 0xc4 */
+ u32 dtdr[2]; /* 0xd4 */
+ u32 dtmr[2]; /* 0xdc */
+ u32 dtbmr; /* 0xe4 */
+ u32 catr[2]; /* 0xe8 */
+ u32 dtedr[2]; /* 0xf0 */
+ u8 res4[0x8]; /* 0xf8 */
+ u32 pgcr[4]; /* 0x100 PHY general configuration registers */
+ u32 iovcr[2]; /* 0x110 */
+ u32 dqsdr; /* 0x118 */
+ u32 dxccr; /* 0x11c */
+ u32 odtmap; /* 0x120 */
+ u32 zqctl[2]; /* 0x124 */
+ u8 res6[0x14]; /* 0x12c */
+ u32 zqcr; /* 0x140 ZQ control register */
+ u32 zqsr; /* 0x144 ZQ status register */
+ u32 zqdr[3]; /* 0x148 ZQ data registers */
+ u8 res7[0x6c]; /* 0x154 */
+ u32 sched; /* 0x1c0 */
+ u32 perfhpr[2]; /* 0x1c4 */
+ u32 perflpr[2]; /* 0x1cc */
+ u32 perfwr[2]; /* 0x1d4 */
+ u8 res8[0x2c]; /* 0x1dc */
+ u32 aciocr; /* 0x208 */
+ u8 res9[0xf4]; /* 0x20c */
+ struct { /* 0x300 DATX8 modules*/
+ u32 mdlr; /* 0x00 */
+ u32 lcdlr[3]; /* 0x04 */
+ u32 iocr[11]; /* 0x10 IO configuration register */
+ u32 bdlr6; /* 0x3c */
+ u32 gtr; /* 0x40 */
+ u32 gcr; /* 0x44 */
+ u32 gsr[3]; /* 0x48 */
+ u8 res0[0x2c]; /* 0x54 */
+ } datx[4];
+ u8 res10[0x388]; /* 0x500 */
+ u32 upd2; /* 0x888 */
+};
+
+#define PTR3_TDINIT1(x) ((x) << 20)
+#define PTR3_TDINIT0(x) ((x) << 0)
+
+#define PTR4_TDINIT3(x) ((x) << 20)
+#define PTR4_TDINIT2(x) ((x) << 0)
+
+#define DRAMTMG0_TWTP(x) ((x) << 24)
+#define DRAMTMG0_TFAW(x) ((x) << 16)
+#define DRAMTMG0_TRAS_MAX(x) ((x) << 8)
+#define DRAMTMG0_TRAS(x) ((x) << 0)
+
+#define DRAMTMG1_TXP(x) ((x) << 16)
+#define DRAMTMG1_TRTP(x) ((x) << 8)
+#define DRAMTMG1_TRC(x) ((x) << 0)
+
+#define DRAMTMG2_TCWL(x) ((x) << 24)
+#define DRAMTMG2_TCL(x) ((x) << 16)
+#define DRAMTMG2_TRD2WR(x) ((x) << 8)
+#define DRAMTMG2_TWR2RD(x) ((x) << 0)
+
+#define DRAMTMG3_TMRW(x) ((x) << 16)
+#define DRAMTMG3_TMRD(x) ((x) << 12)
+#define DRAMTMG3_TMOD(x) ((x) << 0)
+
+#define DRAMTMG4_TRCD(x) ((x) << 24)
+#define DRAMTMG4_TCCD(x) ((x) << 16)
+#define DRAMTMG4_TRRD(x) ((x) << 8)
+#define DRAMTMG4_TRP(x) ((x) << 0)
+
+#define DRAMTMG5_TCKSRX(x) ((x) << 24)
+#define DRAMTMG5_TCKSRE(x) ((x) << 16)
+#define DRAMTMG5_TCKESR(x) ((x) << 8)
+#define DRAMTMG5_TCKE(x) ((x) << 0)
+
+#define RFSHTMG_TREFI(x) ((x) << 16)
+#define RFSHTMG_TRFC(x) ((x) << 0)
+
+#define PIR_CLRSR (0x1 << 27) /* clear status registers */
+#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */
+#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */
+#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */
+#define PIR_PHYRST (0x1 << 6) /* PHY reset */
+#define PIR_DCAL (0x1 << 5) /* DDL calibration */
+#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */
+#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */
+#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */
+
+#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */
+
+#define ZQCR_PWRDOWN (0x1 << 31) /* ZQ power down */
+
+#define DATX_IOCR_DQ(x) (x) /* DQ0-7 IOCR index */
+#define DATX_IOCR_DM (8) /* DM IOCR index */
+#define DATX_IOCR_DQS (9) /* DQS IOCR index */
+#define DATX_IOCR_DQSN (10) /* DQSN IOCR index */
+
+#define DATX_IOCR_WRITE_DELAY(x) ((x) << 8)
+#define DATX_IOCR_READ_DELAY(x) ((x) << 0)
+
+#endif /* _SUNXI_DRAM_SUN8I_H3_H */
#define SUN7I_GPA_GMAC 5
#define SUN6I_GPA_SDC2 5
#define SUN6I_GPA_SDC3 4
+#define SUN8I_H3_GPA_UART0 2
#define SUN4I_GPB_TWI0 2
#define SUN4I_GPB_TWI1 2
void set_pgtable_section(u64 *page_table, u64 index,
u64 section, u64 memory_type,
- u64 share);
+ u64 attribute);
void set_pgtable_table(u64 *page_table, u64 index,
u64 *table_addr);
u32 omap_boot_mode;
u8 omap_ch_flags;
#endif
-#ifdef CONFIG_FSL_LSCH3
+#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
unsigned long mem2_clk;
#endif
};
select CPU_ARM926EJS
select SUPPORT_SPL
+config TARGET_SAMA5D2_XPLAINED
+ bool "SAMA5D2 Xplained board"
+ select CPU_V7
+
config TARGET_SAMA5D3_XPLAINED
bool "SAMA5D3 Xplained board"
select CPU_V7
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
-obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
+obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
obj-y += spl.o
endif
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o
obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o
obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o
obj-y += clock.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d2.h>
+
+char *get_cpu_name()
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_sama5d2()) {
+ switch (extension_id) {
+ case ARCH_EXID_SAMA5D21CU:
+ return "SAMA5D21";
+ case ARCH_EXID_SAMA5D22CU:
+ return "SAMA5D22-CU";
+ case ARCH_EXID_SAMA5D22CN:
+ return "SAMA5D22-CN";
+ case ARCH_EXID_SAMA5D23CU:
+ return "SAMA5D23-CU";
+ case ARCH_EXID_SAMA5D24CX:
+ return "SAMA5D24-CX";
+ case ARCH_EXID_SAMA5D24CU:
+ return "SAMA5D24-CU";
+ case ARCH_EXID_SAMA5D26CU:
+ return "SAMA5D26-CU";
+ case ARCH_EXID_SAMA5D27CU:
+ return "SAMA5D27-CU";
+ case ARCH_EXID_SAMA5D27CN:
+ return "SAMA5D27-CN";
+ case ARCH_EXID_SAMA5D28CU:
+ return "SAMA5D28-CU";
+ case ARCH_EXID_SAMA5D28CN:
+ return "SAMA5D28-CN";
+ }
+ }
+
+ return "Unknown CPU type";
+}
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+void at91_udp_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
+
+ at91_periph_clk_enable(ATMEL_ID_UDPHS);
+}
+#endif
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
-#include <asm/arch/sama5_matrix.h>
#include <asm/arch/sama5_sfr.h>
#include <asm/arch/sama5d4.h>
at91_periph_clk_enable(ATMEL_ID_UDPHS);
}
#endif
-
-#ifdef CONFIG_SPL_BUILD
-void matrix_init(void)
-{
- struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
- struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
- int i;
-
- /* Disable the write protect */
- writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
- writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-
- /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
- for (i = 4; i <= 10; i++) {
- writel(0x000f0f0f, &h64mx->ssr[i]);
- writel(0x0000ffff, &h64mx->sassr[i]);
- writel(0x0000000f, &h64mx->srtsr[i]);
- }
-
- /* CS3 */
- writel(0x00c0c0c0, &h32mx->ssr[3]);
- writel(0xff000000, &h32mx->sassr[3]);
- writel(0xff000000, &h32mx->srtsr[3]);
-
- /* NFC SRAM */
- writel(0x00010101, &h32mx->ssr[4]);
- writel(0x00000001, &h32mx->sassr[4]);
- writel(0x00000001, &h32mx->srtsr[4]);
-
- /* Configure Programmable Security peripherals on matrix 64 */
- writel(readl(&h64mx->spselr[0]) | 0x00080000, &h64mx->spselr[0]);
- writel(readl(&h64mx->spselr[1]) | 0x00180000, &h64mx->spselr[1]);
- writel(readl(&h64mx->spselr[2]) | 0x00000008, &h64mx->spselr[2]);
-
- /* Configure Programmable Security peripherals on matrix 32 */
- writel(readl(&h32mx->spselr[0]) | 0xFFC00000, &h32mx->spselr[0]);
- writel(readl(&h32mx->spselr[1]) | 0x60E3FFFF, &h32mx->spselr[1]);
-
- /* Enable the write protect */
- writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
- writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-}
-
-void redirect_int_from_saic_to_aic(void)
-{
- struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
- u32 key32;
-
- if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
- key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
- writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
- }
-}
-#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sama5_sfr.h>
+
+void redirect_int_from_saic_to_aic(void)
+{
+ struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+ u32 key32;
+
+ if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
+ key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
+ writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
+ }
+}
#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF)
#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8)
#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14)
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+ defined(CONFIG_SAMA5D4)
#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18)
#else
#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16)
#define AT91_PMC_MCKR_CSS_PLLB 0x00000003
#define AT91_PMC_MCKR_CSS_MASK 0x00000003
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+ defined(CONFIG_SAMA5D4) || \
defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
#define AT91_PMC_MCKR_PRES_1 0x00000000
#define AT91_PMC_MCKR_PRES_2 0x00000010
#else
#define AT91_PMC_MCKR_MDIV_1 0x00000000
#define AT91_PMC_MCKR_MDIV_2 0x00000100
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
- defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
#define AT91_PMC_MCKR_MDIV_3 0x00000300
-#endif
#define AT91_PMC_MCKR_MDIV_4 0x00000200
#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
#endif
--- /dev/null
+/*
+ * Copyright (C) 2015 Atmel Corporation.
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ATMEL_PIO4_H
+#define __ATMEL_PIO4_H
+
+#ifndef __ASSEMBLY__
+
+struct atmel_pio4_port {
+ u32 mskr; /* 0x00 PIO Mask Register */
+ u32 cfgr; /* 0x04 PIO Configuration Register */
+ u32 pdsr; /* 0x08 PIO Pin Data Status Register */
+ u32 locksr; /* 0x0C PIO Lock Status Register */
+ u32 sodr; /* 0x10 PIO Set Output Data Register */
+ u32 codr; /* 0x14 PIO Clear Output Data Register */
+ u32 odsr; /* 0x18 PIO Output Data Status Register */
+ u32 reserved0;
+ u32 ier; /* 0x20 PIO Interrupt Enable Register */
+ u32 idr; /* 0x24 PIO Interrupt Disable Register */
+ u32 imr; /* 0x28 PIO Interrupt Mask Register */
+ u32 isr; /* 0x2C PIO Interrupt Status Register */
+ u32 reserved1[3];
+ u32 iofr; /* 0x3C PIO I/O Freeze Register */
+};
+
+#endif
+
+#define AT91_PIO_PORTA 0x0
+#define AT91_PIO_PORTB 0x1
+#define AT91_PIO_PORTC 0x2
+#define AT91_PIO_PORTD 0x3
+
+int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup);
+int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value);
+int atmel_pio4_get_pio_input(u32 port, u32 pin);
+
+#endif
EP("ep5", 5, 1024, 3, 1, 1),
EP("ep6", 6, 1024, 3, 1, 1),
};
-#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
+#elif defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+ defined(CONFIG_SAMA5D4)
static struct usba_ep_data usba_udc_ep[] = {
EP("ep0", 0, 64, 1, 0, 0),
EP("ep1", 1, 1024, 3, 1, 0),
# include <asm/arch/at91sam9g45.h>
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
# include <asm/arch/at91sam9x5.h>
+#elif defined(CONFIG_SAMA5D2)
+# include <asm/arch/sama5d2.h>
#elif defined(CONFIG_SAMA5D3)
# include <asm/arch/sama5d3.h>
#elif defined(CONFIG_SAMA5D4)
#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
/* Bit field in AICREDIR */
-#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
#endif
--- /dev/null
+/*
+ * Chip-specific header file for the SAMA5D2 SoC
+ *
+ * Copyright (C) 2015 Atmel
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMA5D2_H
+#define __SAMA5D2_H
+
+/*
+ * definitions to be used in other places
+ */
+#define CONFIG_AT91FAMILY /* It's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* FIQ Interrupt ID */
+/* 1 */
+#define ATMEL_ID_ARM 2 /* Performance Monitor Unit */
+#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */
+#define ATMEL_ID_WDT 4 /* Watchdog Timer Interrupt */
+#define ATMEL_ID_GMAC 5 /* Ethernet MAC */
+#define ATMEL_ID_XDMAC0 6 /* DMA Controller 0 */
+#define ATMEL_ID_XDMAC1 7 /* DMA Controller 1 */
+#define ATMEL_ID_ICM 8 /* Integrity Check Monitor */
+#define ATMEL_ID_AES 9 /* Advanced Encryption Standard */
+#define ATMEL_ID_AESB 10 /* AES bridge */
+#define ATMEL_ID_TDES 11 /* Triple Data Encryption Standard */
+#define ATMEL_ID_SHA 12 /* SHA Signature */
+#define ATMEL_ID_MPDDRC 13 /* MPDDR Controller */
+#define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */
+#define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */
+#define ATMEL_ID_SECUMOD 16 /* Secure Module */
+#define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */
+#define ATMEL_ID_PIOA 18 /* Parallel I/O Controller A */
+#define ATMEL_ID_FLEXCOM0 19 /* FLEXCOM0 */
+#define ATMEL_ID_FLEXCOM1 20 /* FLEXCOM1 */
+#define ATMEL_ID_FLEXCOM2 21 /* FLEXCOM2 */
+#define ATMEL_ID_FLEXCOM3 22 /* FLEXCOM3 */
+#define ATMEL_ID_FLEXCOM4 23 /* FLEXCOM4 */
+#define ATMEL_ID_UART0 24 /* UART0 */
+#define ATMEL_ID_UART1 25 /* UART1 */
+#define ATMEL_ID_UART2 26 /* UART2 */
+#define ATMEL_ID_UART3 27 /* UART3 */
+#define ATMEL_ID_UART4 28 /* UART4 */
+#define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */
+#define ATMEL_ID_TWIHS1 30 /* Two-wire Interface 1 */
+#define ATMEL_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */
+#define ATMEL_ID_SDMMC1 32 /* Secure Data Memory Card Controller 1 */
+#define ATMEL_ID_SPI0 33 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 34 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */
+#define ATMEL_ID_TC1 36 /* Timer Counter 1 (ch.3,4,5) */
+/* 37 */
+#define ATMEL_ID_PWM 38 /* PWMController0 (ch. 0,1,2,3) */
+/* 39 */
+#define ATMEL_ID_ADC 40 /* Touch Screen ADC Controller */
+#define ATMEL_ID_UHPHS 41 /* USB Host High Speed */
+#define ATMEL_ID_UDPHS 42 /* USB Device High Speed */
+#define ATMEL_ID_SSC0 43 /* Serial Synchronous Controller 0 */
+#define ATMEL_ID_SSC1 44 /* Serial Synchronous Controller 1 */
+#define ATMEL_ID_LCDC 45 /* LCD Controller */
+#define ATMEL_ID_ISI 46 /* Image Sensor Controller, for A5D2, named after ISC */
+#define ATMEL_ID_TRNG 47 /* True Random Number Generator */
+#define ATMEL_ID_PDMIC 48 /* PDM Interface Controller */
+#define ATMEL_ID_AIC_IRQ 49 /* IRQ Interrupt ID */
+#define ATMEL_ID_SFC 50 /* Fuse Controller */
+#define ATMEL_ID_SECURAM 51 /* Secure RAM */
+#define ATMEL_ID_QSPI0 52 /* QSPI0 */
+#define ATMEL_ID_QSPI1 53 /* QSPI1 */
+#define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */
+#define ATMEL_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */
+#define ATMEL_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */
+#define ATMEL_ID_CAN1_INT0 57 /* MCAN 1 Interrupt0 */
+/* 58 */
+#define ATMEL_ID_CLASSD 59 /* Audio Class D Amplifier */
+#define ATMEL_ID_SFR 60 /* Special Function Register */
+#define ATMEL_ID_SAIC 61 /* Secured AIC */
+#define ATMEL_ID_AIC 62 /* Advanced Interrupt Controller */
+#define ATMEL_ID_L2CC 63 /* L2 Cache Controller */
+#define ATMEL_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */
+#define ATMEL_ID_CAN1_INT1 65 /* MCAN 1 Interrupt1 */
+#define ATMEL_ID_GMAC_Q1 66 /* GMAC Queue 1 Interrupt */
+#define ATMEL_ID_GMAC_Q2 67 /* GMAC Queue 2 Interrupt */
+#define ATMEL_ID_PIOB 68 /* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC 69 /* Parallel I/O Controller C */
+#define ATMEL_ID_PIOD 70 /* Parallel I/O Controller D */
+#define ATMEL_ID_SDMMC0_TIMER 71 /* Secure Data Memory Card Controller 0 (TIMER) */
+#define ATMEL_ID_SDMMC1_TIMER 72 /* Secure Data Memory Card Controller 1 (TIMER) */
+/* 73 */
+#define ATMEL_ID_SYS 74 /* System Controller Interrupt */
+#define ATMEL_ID_ACC 75 /* Analog Comparator */
+#define ATMEL_ID_RXLP 76 /* UART Low-Power */
+#define ATMEL_ID_SFRBU 77 /* Special Function Register BackUp */
+#define ATMEL_ID_CHIPID 78 /* Chip ID */
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_LCDC 0xf0000000
+#define ATMEL_BASE_XDMAC1 0xf0004000
+#define ATMEL_BASE_MPDDRC 0xf000c000
+#define ATMEL_BASE_XDMAC0 0xf0010000
+#define ATMEL_BASE_PMC 0xf0014000
+#define ATMEL_BASE_QSPI0 0xf0020000
+#define ATMEL_BASE_QSPI1 0xf0024000
+#define ATMEL_BASE_SPI0 0xf8000000
+#define ATMEL_BASE_GMAC 0xf8008000
+#define ATMEL_BASE_TC0 0xf800c000
+#define ATMEL_BASE_TC1 0xf8010000
+#define ATMEL_BASE_HSMC 0xf8014000
+#define ATMEL_BASE_UART0 0xf801c000
+#define ATMEL_BASE_UART1 0xf8020000
+#define ATMEL_BASE_UART2 0xf8024000
+#define ATMEL_BASE_TWI0 0xf8028000
+#define ATMEL_BASE_SYSC 0xf8048000
+#define ATMEL_BASE_SPI1 0xfc000000
+#define ATMEL_BASE_UART3 0xfc008000
+#define ATMEL_BASE_UART4 0xfc00c000
+#define ATMEL_BASE_TWI1 0xfc028000
+#define ATMEL_BASE_UDPHS 0xfc02c000
+
+#define ATMEL_BASE_PIOA 0xfc038000
+
+#define ATMEL_CHIPID_CIDR 0xfc069000
+#define ATMEL_CHIPID_EXID 0xfc069004
+
+/*
+ * Address Memory Space
+ */
+#define ATMEL_BASE_DDRCS 0x20000000
+#define ATMEL_BASE_QSPI0_AES_MEM 0x90000000
+#define ATMEL_BASE_QSPI1_AES_MEM 0x98000000
+#define ATMEL_BASE_SDMMC0 0xa0000000
+#define ATMEL_BASE_SDMMC1 0xb0000000
+#define ATMEL_BASE_QSPI0_MEM 0xd0000000
+#define ATMEL_BASE_QSPI1_MEM 0xd8000000
+
+/*
+ * Internal Memories
+ */
+#define ATMEL_BASE_UDPHS_FIFO 0x00300000 /* USB Device HS controller */
+#define ATMEL_BASE_OHCI 0x00400000 /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI 0x00500000 /* USB Host controller (EHCI) */
+
+/*
+ * SYSC Spawns
+ */
+#define ATMEL_BASE_RSTC ATMEL_BASE_SYSC
+#define ATMEL_BASE_SHDWC (ATMEL_BASE_SYSC + 0x10)
+#define ATMEL_BASE_PIT (ATMEL_BASE_SYSC + 0x30)
+#define ATMEL_BASE_WDT (ATMEL_BASE_SYSC + 0x40)
+#define ATMEL_BASE_SCKC (ATMEL_BASE_SYSC + 0x50)
+#define ATMEL_BASE_RTC (ATMEL_BASE_SYSC + 0xb0)
+
+/*
+ * Other misc definitions
+ */
+#define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70)
+#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500)
+
+#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40)
+#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40)
+#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40)
+
+#define ATMEL_PIO_PORTS 4
+#define CPU_HAS_PCR
+#define CPU_HAS_H32MXDIV
+
+/* SAMA5D2 series chip id definitions */
+#define ARCH_ID_SAMA5D2 0x8a5c08c0
+#define ARCH_EXID_SAMA5D21CU 0x0000005a
+#define ARCH_EXID_SAMA5D22CU 0x00000059
+#define ARCH_EXID_SAMA5D22CN 0x00000069
+#define ARCH_EXID_SAMA5D23CU 0x00000058
+#define ARCH_EXID_SAMA5D24CX 0x00000004
+#define ARCH_EXID_SAMA5D24CU 0x00000014
+#define ARCH_EXID_SAMA5D26CU 0x00000012
+#define ARCH_EXID_SAMA5D27CU 0x00000011
+#define ARCH_EXID_SAMA5D27CN 0x00000021
+#define ARCH_EXID_SAMA5D28CU 0x00000010
+#define ARCH_EXID_SAMA5D28CN 0x00000020
+
+#define cpu_is_sama5d2() (get_chip_id() == ARCH_ID_SAMA5D2)
+
+/* PIT Timer(PIT_PIIR) */
+#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
+
+/* No PMECC Galois table in ROM */
+#define NO_GALOIS_TABLE_IN_ROM
+
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
#define CPU_HAS_PCR
#define CPU_HAS_H32MXDIV
+/* MATRIX0(H64MX) slave id definitions */
+#define H64MX_SLAVE_AXIMX_BRIDGE 0 /* Bridge from H64MX to AXIMX */
+#define H64MX_SLAVE_PERIPH_BRIDGE 1 /* H64MX Peripheral Bridge */
+#define H64MX_SLAVE_VDEC 2 /* Video Decoder */
+#define H64MX_SLAVE_DDRC_PORT0 3 /* DDR2 Port0-AESOTF */
+#define H64MX_SLAVE_DDRC_PORT1 4 /* DDR2 Port1 */
+#define H64MX_SLAVE_DDRC_PORT2 5 /* DDR2 Port2 */
+#define H64MX_SLAVE_DDRC_PORT3 6 /* DDR2 Port3 */
+#define H64MX_SLAVE_DDRC_PORT4 7 /* DDR2 Port4 */
+#define H64MX_SLAVE_DDRC_PORT5 8 /* DDR2 Port5 */
+#define H64MX_SLAVE_DDRC_PORT6 9 /* DDR2 Port6 */
+#define H64MX_SLAVE_DDRC_PORT7 10 /* DDR2 Port7 */
+#define H64MX_SLAVE_SRAM 11 /* Internal SRAM 128K */
+#define H64MX_SLAVE_H32MX_BRIDGE 12 /* Bridge from H64MX to H32MX */
+
+/* MATRIX1(H32MX) slave id definitions */
+#define H32MX_SLAVE_H64MX_BRIDGE 0 /* Bridge from H32MX to H64MX */
+#define H32MX_SLAVE_PERIPH_BRIDGE0 1 /* H32MX Peripheral Bridge 0 */
+#define H32MX_SLAVE_PERIPH_BRIDGE1 2 /* H32MX Peripheral Bridge 1 */
+#define H32MX_SLAVE_EBI 3 /* External Bus Interface */
+#define H32MX_SLAVE_NFC_CMD 3 /* NFC command Register */
+#define H32MX_SLAVE_NFC_SRAM 4 /* NFC SRAM */
+#define H32MX_SLAVE_USB 5 /* USB Device & Host */
+#define H32MX_SLAVE_SMD 6 /* Soft Modem (SMD) */
+
+/* AICREDIR Unlock Key */
+#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
+
/* sama5d4 series chip id definitions */
#define ARCH_ID_SAMA5D4 0x8a5c07c0
#define ARCH_EXID_SAMA5D41 0x00000001
--- /dev/null
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sama5_matrix.h>
+
+void matrix_init(void)
+{
+ struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
+ struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
+ int i;
+
+ /* DDR port 1 ~ port 7 */
+ for (i = H64MX_SLAVE_DDRC_PORT1; i <= H64MX_SLAVE_DDRC_PORT7; i++) {
+ writel(0x000f0f0f, &h64mx->ssr[i]);
+ writel(0x0000ffff, &h64mx->sassr[i]);
+ writel(0x0000000f, &h64mx->srtsr[i]);
+ }
+
+ /* EBI CS3 (NANDFlash 128M) and NFC Command Registers(128M) */
+ writel(0x00c0c0c0, &h32mx->ssr[H32MX_SLAVE_EBI]);
+ writel(0xff000000, &h32mx->sassr[H32MX_SLAVE_EBI]);
+ writel(0xff000000, &h32mx->srtsr[H32MX_SLAVE_EBI]);
+
+ /* NFC SRAM */
+ writel(0x00010101, &h32mx->ssr[H32MX_SLAVE_NFC_SRAM]);
+ writel(0x00000001, &h32mx->sassr[H32MX_SLAVE_NFC_SRAM]);
+ writel(0x00000001, &h32mx->srtsr[H32MX_SLAVE_NFC_SRAM]);
+}
config TARGET_NAS220
bool "BlackArmor NAS220"
+config TARGET_NSA310S
+ bool "Zyxel NSA310S"
+
endchoice
config SYS_SOC
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
source "board/Seagate/nas220/Kconfig"
+source "board/zyxel/nsa310s/Kconfig"
endif
#define CONFIG_PHYLIB
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
+#define CONFIG_ARP_TIMEOUT 200
+#define CONFIG_NET_RETRY_COUNT 50
#endif /* CONFIG_CMD_NET */
/*
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs.
+config ROCKCHIP_RK3036
+ bool "Support Rockchip RK3036"
+ help
+ The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
+ including NEON and GPU, Mali-400 graphics, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+
+config ROCKCHIP_SPL_HDR
+ string "Header of rockchip's spl loader"
+ help
+ Rockchip's bootrom requires the spl loader to start with a 4-bytes
+ header. The content of this header depends on the chip type.
+
+config ROCKCHIP_MAX_SPL_SIZE
+ hex "Max size of rockchip's spl loader"
+ help
+ Different chip may have different sram size. And if we want to jump
+ back to the bootrom after spl, we may need to reserve some sram space
+ for the bootrom.
+ The max spl loader size should be sram size minus reserved
+ size(if needed)
+
config SYS_MALLOC_F
default y
-config SYS_MALLOC_F_LEN
- default 0x800
+config SPL_SYS_MALLOC_SIMPLE
+ default y
config SPL_DM
default y
config DM_GPIO
default y
-config ROCKCHIP_SERIAL
- default y
-
source "arch/arm/mach-rockchip/rk3288/Kconfig"
-
+source "arch/arm/mach-rockchip/rk3036/Kconfig"
endif
#
ifdef CONFIG_SPL_BUILD
-obj-y += board-spl.o
+obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
+obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
else
-obj-y += board.o
+obj-$(CONFIG_ROCKCHIP_RK3288) += board.o
endif
-obj-y += common.o
+obj-y += rk_timer.o
+obj-y += rk_early_print.o
+obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
+obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+++ /dev/null
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <led.h>
-#include <malloc.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/sdram.h>
-#include <dm/pinctrl.h>
-#include <dm/root.h>
-#include <dm/test.h>
-#include <dm/util.h>
-#include <power/regulator.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
- const void *blob = gd->fdt_blob;
- struct udevice *dev;
- const char *bootdev;
- int node;
- int ret;
-
- bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
- debug("Boot device %s\n", bootdev);
- if (!bootdev)
- goto fallback;
-
- node = fdt_path_offset(blob, bootdev);
- if (node < 0) {
- debug("node=%d\n", node);
- goto fallback;
- }
- ret = device_get_global_by_of_offset(node, &dev);
- if (ret) {
- debug("device at node %s/%d not found: %d\n", bootdev, node,
- ret);
- goto fallback;
- }
- debug("Found device %s\n", dev->name);
- switch (device_get_uclass_id(dev)) {
- case UCLASS_SPI_FLASH:
- return BOOT_DEVICE_SPI;
- case UCLASS_MMC:
- return BOOT_DEVICE_MMC1;
- default:
- debug("Booting from device uclass '%s' not supported\n",
- dev_get_uclass_name(dev));
- }
-
-fallback:
- return BOOT_DEVICE_MMC1;
-}
-
-u32 spl_boot_mode(void)
-{
- return MMCSD_MODE_RAW;
-}
-
-/* read L2 control register (L2CTLR) */
-static inline uint32_t read_l2ctlr(void)
-{
- uint32_t val = 0;
-
- asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
-
- return val;
-}
-
-/* write L2 control register (L2CTLR) */
-static inline void write_l2ctlr(uint32_t val)
-{
- /*
- * Note: L2CTLR can only be written when the L2 memory system
- * is idle, ie before the MMU is enabled.
- */
- asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
- isb();
-}
-
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
-struct rk3288_timer {
- u32 timer_load_count0;
- u32 timer_load_count1;
- u32 timer_curr_value0;
- u32 timer_curr_value1;
- u32 timer_ctrl_reg;
- u32 timer_int_status;
-};
-
-void init_timer(void)
-{
- struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE;
-
- writel(0xffffffff, &timer7_ptr->timer_load_count0);
- writel(0xffffffff, &timer7_ptr->timer_load_count1);
- writel(1, &timer7_ptr->timer_ctrl_reg);
-}
-
-static int configure_emmc(struct udevice *pinctrl)
-{
- struct gpio_desc desc;
- int ret;
-
- pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
-
- /*
- * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
- * use the EMMC_PWREN setting.
- */
- ret = dm_gpio_lookup_name("D9", &desc);
- if (ret) {
- debug("gpio ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_request(&desc, "emmc_pwren");
- if (ret) {
- debug("gpio_request ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
- if (ret) {
- debug("gpio dir ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_set_value(&desc, 1);
- if (ret) {
- debug("gpio value ret=%d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-void board_init_f(ulong dummy)
-{
- struct udevice *pinctrl;
- struct udevice *dev;
- int ret;
-
- /* Example code showing how to enable the debug UART on RK3288 */
-#ifdef EARLY_UART
-#include <asm/arch/grf_rk3288.h>
- /* Enable early UART on the RK3288 */
-#define GRF_BASE 0xff770000
- struct rk3288_grf * const grf = (void *)GRF_BASE;
-
- rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
- GPIO7C6_MASK << GPIO7C6_SHIFT,
- GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
- GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
- /*
- * Debug UART can be used from here if required:
- *
- * debug_uart_init();
- * printch('a');
- * printhex8(0x1234);
- * printascii("string");
- */
- debug_uart_init();
-#endif
-
- ret = spl_init();
- if (ret) {
- debug("spl_init() failed: %d\n", ret);
- hang();
- }
-
- init_timer();
- configure_l2ctlr();
-
- ret = uclass_get_device(UCLASS_CLK, 0, &dev);
- if (ret) {
- debug("CLK init failed: %d\n", ret);
- return;
- }
-
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("Pinctrl init failed: %d\n", ret);
- return;
- }
-
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- debug("DRAM init failed: %d\n", ret);
- return;
- }
-
- /*
- * Now that DRAM is initialized setup base pointer for simple malloc
- * into RAM.
- */
- gd->malloc_base = CONFIG_SPL_STACK_R_ADDR;
- gd->malloc_ptr = 0;
-}
-
-static int setup_led(void)
-{
-#ifdef CONFIG_SPL_LED
- struct udevice *dev;
- char *led_name;
- int ret;
-
- led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
- if (!led_name)
- return 0;
- ret = led_get_by_label(led_name, &dev);
- if (ret) {
- debug("%s: get=%d\n", __func__, ret);
- return ret;
- }
- ret = led_set_on(dev, 1);
- if (ret)
- return ret;
-#endif
-
- return 0;
-}
-
-void spl_board_init(void)
-{
- struct udevice *pinctrl;
- int ret;
-
- ret = setup_led();
-
- if (ret) {
- debug("LED ret=%d\n", ret);
- hang();
- }
-
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
- ret = configure_emmc(pinctrl);
- if (ret) {
- debug("%s: Failed to set up eMMC\n", __func__);
- goto err;
- }
-
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- goto err;
- }
-
- preloader_console_init();
- return;
-err:
- printf("spl_board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
-}
#include <common.h>
#include <dm.h>
#include <ram.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/grf_rk3036.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sdram_rk3036.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GRF_BASE 0x20008000
+static struct rk3036_grf * const grf = (void *)GRF_BASE;
+
+#define DEBUG_UART_BASE 0x20068000
+
+extern void back_to_bootrom(void);
+
+void board_init_f(ulong dummy)
+{
+#ifdef EARLY_DEBUG
+ /*
+ * NOTE: sd card and debug uart use same iomux in rk3036,
+ * so if you enable uart,
+ * you can not boot from sdcard
+ */
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C3_MASK << GPIO1C3_SHIFT |
+ GPIO1C2_MASK << GPIO1C2_SHIFT,
+ GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
+ GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
+ rk_uart_init((void *)DEBUG_UART_BASE);
+#endif
+ rockchip_timer_init();
+ sdram_init();
+
+ /* return to maskrom */
+ back_to_bootrom();
+}
+
+/* Place Holders */
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+ /*
+ * Function attribute is no-return
+ * This Function never executes
+ */
+ while (1)
+ ;
+}
--- /dev/null
+if ROCKCHIP_RK3036
+
+config TARGET_EVB_RK3036
+ bool "EVB_RK3036"
+
+config SYS_SOC
+ default "rockchip"
+
+config SYS_MALLOC_F_LEN
+ default 0x400
+
+config ROCKCHIP_SPL_HDR
+ default "RK30"
+
+config ROCKCHIP_MAX_SPL_SIZE
+ default 0x1000
+
+config ROCKCHIP_COMMON
+ bool "Support rk common fuction"
+
+source "board/evb_rk3036/evb_rk3036/Kconfig"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2015 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y += reset_rk3036.o
+obj-y += syscon_rk3036.o
+endif
+
+obj-y += sdram_rk3036.o
+obj-y += save_boot_param.o
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3036.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+int rk3036_reset_request(struct udevice *dev, enum reset_t type)
+{
+ struct rk3036_cru *cru = rockchip_get_cru();
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+ switch (type) {
+ case RESET_WARM:
+ writel(0xeca8, &cru->cru_glb_srst_snd_value);
+ break;
+ case RESET_COLD:
+ writel(0xfdb9, &cru->cru_glb_srst_fst_value);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct reset_ops rk3036_reset = {
+ .request = rk3036_reset_request,
+};
+
+U_BOOT_DRIVER(reset_rk3036) = {
+ .name = "rk3036_reset",
+ .id = UCLASS_RESET,
+ .ops = &rk3036_reset,
+};
--- /dev/null
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/linkage.h>
+
+.globl SAVE_SP_ADDR
+SAVE_SP_ADDR:
+ .word 0
+
+/*
+ * void save_boot_params
+ *
+ * Save sp, lr, r1~r12
+ */
+ENTRY(save_boot_params)
+ push {r1-r12, lr}
+ ldr r0, =SAVE_SP_ADDR
+ str sp, [r0]
+ b save_boot_params_ret @ back to my caller
+ENDPROC(save_boot_params)
+
+
+.globl back_to_bootrom
+ENTRY(back_to_bootrom)
+ ldr r0, =SAVE_SP_ADDR
+ ldr sp, [r0]
+ mov r0, #0
+ pop {r1-r12, pc}
+ENDPROC(back_to_bootrom)
--- /dev/null
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/arch/cru_rk3036.h>
+#include <asm/arch/grf_rk3036.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sdram_rk3036.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/uart.h>
+
+/*
+ * we can not fit the code to access the device tree in SPL
+ * (due to 4K SRAM size limits), so these are hard-coded
+ */
+#define CRU_BASE 0x20000000
+#define GRF_BASE 0x20008000
+#define DDR_PHY_BASE 0x2000a000
+#define DDR_PCTL_BASE 0x20004000
+#define CPU_AXI_BUS_BASE 0x10128000
+
+struct rk3036_sdram_priv {
+ struct rk3036_cru *cru;
+ struct rk3036_grf *grf;
+ struct rk3036_ddr_phy *phy;
+ struct rk3036_ddr_pctl *pctl;
+ struct rk3036_service_sys *axi_bus;
+
+ /* ddr die config */
+ struct rk3036_ddr_config ddr_config;
+};
+
+/* use integer mode, 396MHz dpll setting
+ * refdiv, fbdiv, postdiv1, postdiv2
+ */
+const struct pll_div dpll_init_cfg = {1, 66, 4, 1};
+
+/* 396Mhz ddr timing */
+const struct rk3036_ddr_timing ddr_timing = {0x18c,
+ {0x18c, 0xc8, 0x1f4, 0x27, 0x4e,
+ 0x4, 0x8b, 0x06, 0x03, 0x0, 0x06, 0x05, 0x0f, 0x15, 0x06, 0x04, 0x04,
+ 0x06, 0x04, 0x200, 0x03, 0x0a, 0x40, 0x2710, 0x01, 0x05, 0x05, 0x03,
+ 0x0c, 0x28, 0x100, 0x0, 0x04, 0x0},
+ {{0x420, 0x42, 0x0, 0x0}, 0x01, 0x60},
+ {0x24717315} };
+
+/*
+ * [7:6] bank(n:n bit bank)
+ * [5:4] row(13+n)
+ * [3] cs(0:1 cs, 1:2 cs)
+ * [2:1] bank(n:n bit bank)
+ * [0] col(10+n)
+ */
+const char ddr_cfg_2_rbc[] = {
+ ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 1),
+ ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 0),
+ ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 0),
+ ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 0),
+ ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 1),
+ ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 1),
+ ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 1),
+ ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 0),
+ ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 1),
+ ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 0),
+ ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 1),
+ ((1 << 6) | (2 << 4) | (0 << 3) | (2 << 1) | 0),
+ ((3 << 6) | (2 << 4) | (0 << 3) | (0 << 1) | 1),
+ ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 0),
+};
+
+/* DDRPHY REG */
+enum {
+ /* DDRPHY_REG1 */
+ SOFT_RESET_MASK = 3,
+ SOFT_RESET_SHIFT = 2,
+
+ /* DDRPHY_REG2 */
+ MEMORY_SELECT_DDR3 = 0 << 6,
+ DQS_SQU_CAL_NORMAL_MODE = 0 << 1,
+ DQS_SQU_CAL_START = 1 << 0,
+ DQS_SQU_NO_CAL = 0 << 0,
+
+ /* DDRPHY_REG2A */
+ CMD_DLL_BYPASS = 1 << 4,
+ CMD_DLL_BYPASS_DISABLE = 0 << 4,
+ HIGH_8BIT_DLL_BYPASS = 1 << 3,
+ HIGH_8BIT_DLL_BYPASS_DISABLE = 0 << 3,
+ LOW_8BIT_DLL_BYPASS = 1 << 2,
+ LOW_8BIT_DLL_BYPASS_DISABLE = 0 << 2,
+
+ /* DDRPHY_REG19 */
+ CMD_FEEDBACK_ENABLE = 1 << 5,
+ CMD_SLAVE_DLL_INVERSE_MODE = 1 << 4,
+ CMD_SLAVE_DLL_NO_INVERSE_MODE = 0 << 4,
+ CMD_SLAVE_DLL_ENALBE = 1 << 3,
+ CMD_TX_SLAVE_DLL_DELAY_MASK = 7,
+ CMD_TX_SLAVE_DLL_DELAY_SHIFT = 0,
+
+ /* DDRPHY_REG6 */
+ LEFT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4,
+ LEFT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4,
+ LEFT_CHN_TX_DQ_DLL_ENABLE = 1 << 3,
+ LEFT_CHN_TX_DQ_DLL_DELAY_MASK = 7,
+ LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0,
+
+ /* DDRPHY_REG8 */
+ LEFT_CHN_RX_DQS_DELAY_TAP_MASK = 3,
+ LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0,
+
+ /* DDRPHY_REG9 */
+ RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4,
+ RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4,
+ RIGHT_CHN_TX_DQ_DLL_ENABLE = 1 << 3,
+ RIGHT_CHN_TX_DQ_DLL_DELAY_MASK = 7,
+ RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0,
+
+ /* DDRPHY_REG11 */
+ RIGHT_CHN_RX_DQS_DELAY_TAP_MASK = 3,
+ RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0,
+
+ /* DDRPHY_REG62 */
+ CAL_DONE_MASK = 3,
+ HIGH_8BIT_CAL_DONE = 1 << 1,
+ LOW_8BIT_CAL_DONE = 1 << 0,
+};
+
+/* PTCL */
+enum {
+ /* PCTL_DFISTCFG0 */
+ DFI_INIT_START = 1 << 0,
+ DFI_DATA_BYTE_DISABLE_EN = 1 << 2,
+
+ /* PCTL_DFISTCFG1 */
+ DFI_DRAM_CLK_SR_EN = 1 << 0,
+ DFI_DRAM_CLK_DPD_EN = 1 << 1,
+
+ /* PCTL_DFISTCFG2 */
+ DFI_PARITY_INTR_EN = 1 << 0,
+ DFI_PARITY_EN = 1 << 1,
+
+ /* PCTL_DFILPCFG0 */
+ TLP_RESP_TIME_SHIFT = 16,
+ LP_SR_EN = 1 << 8,
+ LP_PD_EN = 1 << 0,
+
+ /* PCTL_DFIODTCFG */
+ RANK0_ODT_WRITE_SEL = 1 << 3,
+ RANK1_ODT_WRITE_SEL = 1 << 11,
+
+ /* PCTL_DFIODTCFG1 */
+ ODT_LEN_BL8_W_SHIFT = 16,
+
+ /* PCTL_MCFG */
+ TFAW_CFG_MASK = 3,
+ TFAW_CFG_SHIFT = 18,
+ PD_EXIT_SLOW_MODE = 0 << 17,
+ PD_ACTIVE_POWER_DOWN = 1 << 16,
+ PD_IDLE_MASK = 0xff,
+ PD_IDLE_SHIFT = 8,
+ MEM_BL4 = 0 << 0,
+ MEM_BL8 = 1 << 0,
+
+ /* PCTL_MCFG1 */
+ HW_EXIT_IDLE_EN_MASK = 1,
+ HW_EXIT_IDLE_EN_SHIFT = 31,
+ SR_IDLE_MASK = 0x1ff,
+ SR_IDLE_SHIFT = 0,
+
+ /* PCTL_SCFG */
+ HW_LOW_POWER_EN = 1 << 0,
+
+ /* PCTL_POWCTL */
+ POWER_UP_START = 1 << 0,
+
+ /* PCTL_POWSTAT */
+ POWER_UP_DONE = 1 << 0,
+
+ /* PCTL_MCMD */
+ START_CMD = 1 << 31,
+ BANK_ADDR_MASK = 7,
+ BANK_ADDR_SHIFT = 17,
+ CMD_ADDR_MASK = 0x1fff,
+ CMD_ADDR_SHIFT = 4,
+ DESELECT_CMD = 0,
+ PREA_CMD,
+ REF_CMD,
+ MRS_CMD,
+ ZQCS_CMD,
+ ZQCL_CMD,
+ RSTL_CMD,
+ MRR_CMD = 8,
+
+ /* PCTL_STAT */
+ INIT_MEM = 0,
+ CONFIG,
+ CONFIG_REQ,
+ ACCESS,
+ ACCESS_REQ,
+ LOW_POWER,
+ LOW_POWER_ENTRY_REQ,
+ LOW_POWER_EXIT_REQ,
+ PCTL_STAT_MASK = 7,
+
+ /* PCTL_SCTL */
+ INIT_STATE = 0,
+ CFG_STATE = 1,
+ GO_STATE = 2,
+ SLEEP_STATE = 3,
+ WAKEUP_STATE = 4,
+};
+
+/* GRF_SOC_CON2 */
+#define MSCH4_MAINDDR3 (1 << 7)
+#define PHY_DRV_ODT_SET(n) ((n << 4) | n)
+#define DDR3_DLL_RESET (1 << 8)
+
+/* CK pull up/down driver strength control */
+enum {
+ PHY_RON_DISABLE = 0,
+ PHY_RON_309OHM = 1,
+ PHY_RON_155OHM,
+ PHY_RON_103OHM = 3,
+ PHY_RON_63OHM = 5,
+ PHY_RON_45OHM = 7,
+ PHY_RON_77OHM,
+ PHY_RON_62OHM,
+ PHY_RON_52OHM,
+ PHY_RON_44OHM,
+ PHY_RON_39OHM,
+ PHY_RON_34OHM,
+ PHY_RON_31OHM,
+ PHY_RON_28OHM,
+};
+
+/* DQ pull up/down control */
+enum {
+ PHY_RTT_DISABLE = 0,
+ PHY_RTT_861OHM = 1,
+ PHY_RTT_431OHM,
+ PHY_RTT_287OHM,
+ PHY_RTT_216OHM,
+ PHY_RTT_172OHM,
+ PHY_RTT_145OHM,
+ PHY_RTT_124OHM,
+ PHY_RTT_215OHM,
+ PHY_RTT_144OHM = 0xa,
+ PHY_RTT_123OHM,
+ PHY_RTT_108OHM,
+ PHY_RTT_96OHM,
+ PHY_RTT_86OHM,
+ PHY_RTT_78OHM,
+};
+
+/* DQS squelch DLL delay */
+enum {
+ DQS_DLL_NO_DELAY = 0,
+ DQS_DLL_22P5_DELAY,
+ DQS_DLL_45_DELAY,
+ DQS_DLL_67P5_DELAY,
+ DQS_DLL_90_DELAY,
+ DQS_DLL_112P5_DELAY,
+ DQS_DLL_135_DELAY,
+ DQS_DLL_157P5_DELAY,
+};
+
+/* GRF_OS_REG1 */
+enum {
+ /*
+ * 000: lpddr
+ * 001: ddr
+ * 010: ddr2
+ * 011: ddr3
+ * 100: lpddr2-s2
+ * 101: lpddr2-s4
+ * 110: lpddr3
+ */
+ DDR_TYPE_MASK = 7,
+ DDR_TYPE_SHIFT = 13,
+
+ /* 0: 1 chn, 1: 2 chn */
+ DDR_CHN_CNT_SHIFT = 12,
+
+ /* 0: 1 rank, 1: 2 rank */
+ DDR_RANK_CNT_MASK = 1,
+ DDR_RANK_CNT_SHIFT = 11,
+
+ /*
+ * 00: 9col
+ * 01: 10col
+ * 10: 11col
+ * 11: 12col
+ */
+ DDR_COL_MASK = 3,
+ DDR_COL_SHIFT = 9,
+
+ /* 0: 8 bank, 1: 4 bank*/
+ DDR_BANK_MASK = 1,
+ DDR_BANK_SHIFT = 8,
+
+ /*
+ * 00: 13 row
+ * 01: 14 row
+ * 10: 15 row
+ * 11: 16 row
+ */
+ DDR_CS0_ROW_MASK = 3,
+ DDR_CS0_ROW_SHIFT = 6,
+ DDR_CS1_ROW_MASK = 3,
+ DDR_CS1_ROW_SHIFT = 4,
+
+ /*
+ * 00: 32 bit
+ * 01: 16 bit
+ * 10: 8 bit
+ * rk3036 only support 16bit
+ */
+ DDR_BW_MASK = 3,
+ DDR_BW_SHIFT = 2,
+ DDR_DIE_BW_MASK = 3,
+ DDR_DIE_BW_SHIFT = 0,
+};
+
+static void rkdclk_init(struct rk3036_sdram_priv *priv)
+{
+ struct rk3036_pll *pll = &priv->cru->pll[1];
+
+ /* pll enter slow-mode */
+ rk_clrsetreg(&priv->cru->cru_mode_con,
+ DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+ DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
+
+ /* use integer mode */
+ rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+
+ rk_clrsetreg(&pll->con0,
+ PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
+ (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) |
+ dpll_init_cfg.fbdiv);
+ rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
+ PLL_REFDIV_MASK << PLL_REFDIV_SHIFT,
+ (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
+ dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
+
+ /* waiting for pll lock */
+ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
+ rockchip_udelay(1);
+
+ /* PLL enter normal-mode */
+ rk_clrsetreg(&priv->cru->cru_mode_con,
+ DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+ DPLL_MODE_NORM << DPLL_MODE_SHIFT);
+}
+
+static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
+{
+ int i;
+
+ for (i = 0; i < n / sizeof(u32); i++) {
+ writel(*src, dest);
+ src++;
+ dest++;
+ }
+}
+
+void phy_pctrl_reset(struct rk3036_sdram_priv *priv)
+{
+ struct rk3036_ddr_phy *ddr_phy = priv->phy;
+
+ rk_clrsetreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
+ 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT |
+ 1 << DDRPHY_SRST_SHIFT,
+ 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
+ 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
+
+ rockchip_udelay(10);
+
+ rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
+ 1 << DDRPHY_SRST_SHIFT);
+ rockchip_udelay(10);
+
+ rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
+ 1 << DDRCTRL_SRST_SHIFT);
+ rockchip_udelay(10);
+
+ clrsetbits_le32(&ddr_phy->ddrphy_reg1,
+ SOFT_RESET_MASK << SOFT_RESET_SHIFT,
+ 0 << SOFT_RESET_SHIFT);
+ rockchip_udelay(10);
+ clrsetbits_le32(&ddr_phy->ddrphy_reg1,
+ SOFT_RESET_MASK << SOFT_RESET_SHIFT,
+ 3 << SOFT_RESET_SHIFT);
+
+ rockchip_udelay(1);
+}
+
+void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq)
+{
+ struct rk3036_ddr_phy *ddr_phy = priv->phy;
+
+ if (freq < ddr_timing.freq) {
+ writel(CMD_DLL_BYPASS | HIGH_8BIT_DLL_BYPASS |
+ LOW_8BIT_DLL_BYPASS, &ddr_phy->ddrphy_reg2a);
+
+ writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_90 |
+ LEFT_CHN_TX_DQ_DLL_ENABLE |
+ (0 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) <<
+ LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg6);
+
+ writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 |
+ RIGHT_CHN_TX_DQ_DLL_ENABLE |
+ (0 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) <<
+ RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT,
+ &ddr_phy->ddrphy_reg9);
+ } else {
+ writel(CMD_DLL_BYPASS_DISABLE | HIGH_8BIT_DLL_BYPASS_DISABLE |
+ LOW_8BIT_DLL_BYPASS_DISABLE, &ddr_phy->ddrphy_reg2a);
+
+ writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_0 |
+ LEFT_CHN_TX_DQ_DLL_ENABLE |
+ (4 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) <<
+ LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT,
+ &ddr_phy->ddrphy_reg6);
+
+ writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 |
+ RIGHT_CHN_TX_DQ_DLL_ENABLE |
+ (4 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) <<
+ RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT,
+ &ddr_phy->ddrphy_reg9);
+ }
+
+ writel(CMD_SLAVE_DLL_NO_INVERSE_MODE | CMD_SLAVE_DLL_ENALBE |
+ (0 & CMD_TX_SLAVE_DLL_DELAY_MASK) <<
+ CMD_TX_SLAVE_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg19);
+
+ /* 45 degree delay */
+ writel((DQS_DLL_45_DELAY & LEFT_CHN_RX_DQS_DELAY_TAP_MASK) <<
+ LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg8);
+ writel((DQS_DLL_45_DELAY & RIGHT_CHN_RX_DQS_DELAY_TAP_MASK) <<
+ RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg11);
+}
+
+static void send_command(struct rk3036_ddr_pctl *pctl,
+ u32 rank, u32 cmd, u32 arg)
+{
+ writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
+ rockchip_udelay(1);
+ while (readl(&pctl->mcmd) & START_CMD)
+ ;
+}
+
+static void memory_init(struct rk3036_sdram_priv *priv)
+{
+ struct rk3036_ddr_pctl *pctl = priv->pctl;
+
+ send_command(pctl, 3, DESELECT_CMD, 0);
+ rockchip_udelay(1);
+ send_command(pctl, 3, PREA_CMD, 0);
+ send_command(pctl, 3, MRS_CMD,
+ (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
+ (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) <<
+ CMD_ADDR_SHIFT);
+
+ send_command(pctl, 3, MRS_CMD,
+ (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
+ (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) <<
+ CMD_ADDR_SHIFT);
+
+ send_command(pctl, 3, MRS_CMD,
+ (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
+ (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) <<
+ CMD_ADDR_SHIFT);
+
+ send_command(pctl, 3, MRS_CMD,
+ (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
+ (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) <<
+ CMD_ADDR_SHIFT | DDR3_DLL_RESET);
+
+ send_command(pctl, 3, ZQCL_CMD, 0);
+}
+
+static void data_training(struct rk3036_sdram_priv *priv)
+{
+ struct rk3036_ddr_phy *ddr_phy = priv->phy;
+ struct rk3036_ddr_pctl *pctl = priv->pctl;
+ u32 value;
+
+ /* disable auto refresh */
+ value = readl(&pctl->trefi),
+ writel(0, &pctl->trefi);
+
+ clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
+ DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START);
+
+ rockchip_udelay(1);
+ while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) !=
+ (HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) {
+ ;
+ }
+
+ clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
+ DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_NO_CAL);
+
+ /*
+ * since data training will take about 20us, so send some auto
+ * refresh(about 7.8us) to complement the lost time
+ */
+ send_command(pctl, 3, REF_CMD, 0);
+ send_command(pctl, 3, REF_CMD, 0);
+ send_command(pctl, 3, REF_CMD, 0);
+
+ writel(value, &pctl->trefi);
+}
+
+static void move_to_config_state(struct rk3036_sdram_priv *priv)
+{
+ unsigned int state;
+ struct rk3036_ddr_pctl *pctl = priv->pctl;
+
+ while (1) {
+ state = readl(&pctl->stat) & PCTL_STAT_MASK;
+ switch (state) {
+ case LOW_POWER:
+ writel(WAKEUP_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MASK)
+ != ACCESS)
+ ;
+ /*
+ * If at low power state, need wakeup first, and then
+ * enter the config, so fallthrough
+ */
+ case ACCESS:
+ /* fallthrough */
+ case INIT_MEM:
+ writel(CFG_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
+ ;
+ break;
+ case CONFIG:
+ return;
+ default:
+ break;
+ }
+ }
+}
+
+static void move_to_access_state(struct rk3036_sdram_priv *priv)
+{
+ unsigned int state;
+ struct rk3036_ddr_pctl *pctl = priv->pctl;
+
+ while (1) {
+ state = readl(&pctl->stat) & PCTL_STAT_MASK;
+ switch (state) {
+ case LOW_POWER:
+ writel(WAKEUP_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
+ ;
+ break;
+ case INIT_MEM:
+ writel(CFG_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
+ ;
+ /* fallthrough */
+ case CONFIG:
+ writel(GO_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
+ ;
+ break;
+ case ACCESS:
+ return;
+ default:
+ break;
+ }
+ }
+}
+
+static void pctl_cfg(struct rk3036_sdram_priv *priv)
+{
+ struct rk3036_ddr_pctl *pctl = priv->pctl;
+ u32 burst_len;
+ u32 reg;
+
+ writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
+ writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1);
+ writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
+ writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
+ &pctl->dfilpcfg0);
+
+ writel(1, &pctl->dfitphyupdtype0);
+ writel(0x0d, &pctl->dfitphyrdlat);
+
+ /* cs0 and cs1 write odt enable */
+ writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
+ &pctl->dfiodtcfg);
+
+ /* odt write length */
+ writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
+
+ /* phyupd and ctrlupd disabled */
+ writel(0, &pctl->dfiupdcfg);
+
+ if ((ddr_timing.noc_timing.burstlen << 1) == 4)
+ burst_len = MEM_BL4;
+ else
+ burst_len = MEM_BL8;
+
+ copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u,
+ sizeof(struct rk3036_pctl_timing));
+ reg = readl(&pctl->tcl);
+ writel(reg - 3, &pctl->dfitrddataen);
+ reg = readl(&pctl->tcwl);
+ writel(reg - 1, &pctl->dfitphywrlat);
+
+ writel(burst_len | (1 & TFAW_CFG_MASK) << TFAW_CFG_SHIFT |
+ PD_EXIT_SLOW_MODE | PD_ACTIVE_POWER_DOWN |
+ (0 & PD_IDLE_MASK) << PD_IDLE_SHIFT,
+ &pctl->mcfg);
+
+ writel(RK_SETBITS(MSCH4_MAINDDR3), &priv->grf->soc_con2);
+ setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
+}
+
+static void phy_cfg(struct rk3036_sdram_priv *priv)
+{
+ struct rk3036_ddr_phy *ddr_phy = priv->phy;
+ struct rk3036_service_sys *axi_bus = priv->axi_bus;
+
+ writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming);
+ writel(0x3f, &axi_bus->readlatency);
+
+ writel(MEMORY_SELECT_DDR3 | DQS_SQU_CAL_NORMAL_MODE,
+ &ddr_phy->ddrphy_reg2);
+
+ clrsetbits_le32(&ddr_phy->ddrphy_reg3, 1, ddr_timing.phy_timing.bl);
+ writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a);
+ writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg16);
+ writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg22);
+ writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg25);
+ writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg26);
+ writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg27);
+ writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg28);
+}
+
+void dram_cfg_rbc(struct rk3036_sdram_priv *priv)
+{
+ char noc_config;
+ int i = 0;
+ struct rk3036_ddr_config config = priv->ddr_config;
+ struct rk3036_service_sys *axi_bus = priv->axi_bus;
+
+ move_to_config_state(priv);
+
+ /* 2bit in BIT1, 2 */
+ if (config.rank == 2) {
+ noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 |
+ 1 << 3 | (config.col - 10);
+ if (noc_config == ddr_cfg_2_rbc[9]) {
+ i = 9;
+ goto finish;
+ } else if (noc_config == ddr_cfg_2_rbc[10]) {
+ i = 10;
+ goto finish;
+ }
+ }
+
+ noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 |
+ (config.col - 10);
+
+ for (i = 0; i < sizeof(ddr_cfg_2_rbc); i++) {
+ if (noc_config == ddr_cfg_2_rbc[i])
+ goto finish;
+ }
+
+ /* bank: 1 bit in BIT6,7, 1bit in BIT1, 2 */
+ noc_config = 1 << 6 | (config.cs0_row - 13) << 4 |
+ 2 << 1 | (config.col - 10);
+ if (noc_config == ddr_cfg_2_rbc[11]) {
+ i = 11;
+ goto finish;
+ }
+
+ /* bank: 2bit in BIT6,7 */
+ noc_config = (config.bank << 6) | (config.cs0_row - 13) << 4 |
+ (config.col - 10);
+
+ if (noc_config == ddr_cfg_2_rbc[0])
+ i = 0;
+ else if (noc_config == ddr_cfg_2_rbc[12])
+ i = 12;
+ else if (noc_config == ddr_cfg_2_rbc[13])
+ i = 13;
+finish:
+ writel(i, &axi_bus->ddrconf);
+ move_to_access_state(priv);
+}
+
+static void sdram_all_config(struct rk3036_sdram_priv *priv)
+{
+ u32 os_reg = 0;
+ struct rk3036_ddr_config config = priv->ddr_config;
+
+ os_reg = config.ddr_type << DDR_TYPE_SHIFT |
+ 0 << DDR_CHN_CNT_SHIFT |
+ (config.rank - 1) << DDR_RANK_CNT_SHIFT |
+ (config.col - 1) << DDR_COL_SHIFT |
+ (config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT |
+ (config.cs0_row - 13) << DDR_CS0_ROW_SHIFT |
+ (config.cs1_row - 13) << DDR_CS1_ROW_SHIFT |
+ 1 << DDR_BW_SHIFT | config.bw << DDR_DIE_BW_SHIFT;
+ writel(os_reg, &priv->grf->os_reg[1]);
+}
+
+size_t sdram_size(void)
+{
+ u32 size, os_reg, cs0_row, cs1_row, col, bank, rank;
+ struct rk3036_grf *grf = (void *)GRF_BASE;
+
+ os_reg = readl(&grf->os_reg[1]);
+
+ cs0_row = 13 + ((os_reg >> DDR_CS0_ROW_SHIFT) & DDR_CS0_ROW_MASK);
+ cs1_row = 13 + ((os_reg >> DDR_CS1_ROW_SHIFT) & DDR_CS1_ROW_MASK);
+ col = 9 + ((os_reg >> DDR_COL_SHIFT) & DDR_COL_MASK);
+ bank = 3 - ((os_reg >> DDR_BANK_SHIFT) & DDR_BANK_MASK);
+ rank = 1 + ((os_reg >> DDR_RANK_CNT_SHIFT) & DDR_RANK_CNT_MASK);
+
+ /* row + col + bank + bw(rk3036 only support 16bit, so fix in 1) */
+ size = 1 << (cs0_row + col + bank + 1);
+
+ if (rank > 1)
+ size += size >> (cs0_row - cs1_row);
+
+ return size;
+}
+
+void sdram_init(void)
+{
+ struct rk3036_sdram_priv sdram_priv;
+
+ sdram_priv.cru = (void *)CRU_BASE;
+ sdram_priv.grf = (void *)GRF_BASE;
+ sdram_priv.phy = (void *)DDR_PHY_BASE;
+ sdram_priv.pctl = (void *)DDR_PCTL_BASE;
+ sdram_priv.axi_bus = (void *)CPU_AXI_BUS_BASE;
+
+ get_ddr_config(&sdram_priv.ddr_config);
+ sdram_all_config(&sdram_priv);
+ rkdclk_init(&sdram_priv);
+ phy_pctrl_reset(&sdram_priv);
+ phy_dll_bypass_set(&sdram_priv, ddr_timing.freq);
+ pctl_cfg(&sdram_priv);
+ phy_cfg(&sdram_priv);
+ writel(POWER_UP_START, &sdram_priv.pctl->powctl);
+ while (!(readl(&sdram_priv.pctl->powstat) & POWER_UP_DONE))
+ ;
+ memory_init(&sdram_priv);
+ move_to_config_state(&sdram_priv);
+ data_training(&sdram_priv);
+ move_to_access_state(&sdram_priv);
+ dram_cfg_rbc(&sdram_priv);
+}
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3036_syscon_ids[] = {
+ { .compatible = "rockchip,rk3036-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3036) = {
+ .name = "rk3036_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3036_syscon_ids,
+};
--- /dev/null
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <led.h>
+#include <malloc.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/timer.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <dm/test.h>
+#include <dm/util.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+ const void *blob = gd->fdt_blob;
+ struct udevice *dev;
+ const char *bootdev;
+ int node;
+ int ret;
+
+ bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
+ debug("Boot device %s\n", bootdev);
+ if (!bootdev)
+ goto fallback;
+
+ node = fdt_path_offset(blob, bootdev);
+ if (node < 0) {
+ debug("node=%d\n", node);
+ goto fallback;
+ }
+ ret = device_get_global_by_of_offset(node, &dev);
+ if (ret) {
+ debug("device at node %s/%d not found: %d\n", bootdev, node,
+ ret);
+ goto fallback;
+ }
+ debug("Found device %s\n", dev->name);
+ switch (device_get_uclass_id(dev)) {
+ case UCLASS_SPI_FLASH:
+ return BOOT_DEVICE_SPI;
+ case UCLASS_MMC:
+ return BOOT_DEVICE_MMC1;
+ default:
+ debug("Booting from device uclass '%s' not supported\n",
+ dev_get_uclass_name(dev));
+ }
+
+fallback:
+ return BOOT_DEVICE_MMC1;
+}
+
+u32 spl_boot_mode(void)
+{
+ return MMCSD_MODE_RAW;
+}
+
+/* read L2 control register (L2CTLR) */
+static inline uint32_t read_l2ctlr(void)
+{
+ uint32_t val = 0;
+
+ asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
+
+ return val;
+}
+
+/* write L2 control register (L2CTLR) */
+static inline void write_l2ctlr(uint32_t val)
+{
+ /*
+ * Note: L2CTLR can only be written when the L2 memory system
+ * is idle, ie before the MMU is enabled.
+ */
+ asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
+ isb();
+}
+
+static void configure_l2ctlr(void)
+{
+ uint32_t l2ctlr;
+
+ l2ctlr = read_l2ctlr();
+ l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
+
+ /*
+ * Data RAM write latency: 2 cycles
+ * Data RAM read latency: 2 cycles
+ * Data RAM setup latency: 1 cycle
+ * Tag RAM write latency: 1 cycle
+ * Tag RAM read latency: 1 cycle
+ * Tag RAM setup latency: 1 cycle
+ */
+ l2ctlr |= (1 << 3 | 1 << 0);
+ write_l2ctlr(l2ctlr);
+}
+
+static int configure_emmc(struct udevice *pinctrl)
+{
+ struct gpio_desc desc;
+ int ret;
+
+ pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
+
+ /*
+ * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
+ * use the EMMC_PWREN setting.
+ */
+ ret = dm_gpio_lookup_name("D9", &desc);
+ if (ret) {
+ debug("gpio ret=%d\n", ret);
+ return ret;
+ }
+ ret = dm_gpio_request(&desc, "emmc_pwren");
+ if (ret) {
+ debug("gpio_request ret=%d\n", ret);
+ return ret;
+ }
+ ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+ if (ret) {
+ debug("gpio dir ret=%d\n", ret);
+ return ret;
+ }
+ ret = dm_gpio_set_value(&desc, 1);
+ if (ret) {
+ debug("gpio value ret=%d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *pinctrl;
+ struct udevice *dev;
+ int ret;
+
+ /* Example code showing how to enable the debug UART on RK3288 */
+#ifdef EARLY_UART
+#include <asm/arch/grf_rk3288.h>
+ /* Enable early UART on the RK3288 */
+#define GRF_BASE 0xff770000
+ struct rk3288_grf * const grf = (void *)GRF_BASE;
+
+ rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
+ GPIO7C6_MASK << GPIO7C6_SHIFT,
+ GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
+ GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+ debug_uart_init();
+#endif
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ rockchip_timer_init();
+ configure_l2ctlr();
+
+ ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (ret) {
+ debug("CLK init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret) {
+ debug("Pinctrl init failed: %d\n", ret);
+ return;
+ }
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return;
+ }
+}
+
+static int setup_led(void)
+{
+#ifdef CONFIG_SPL_LED
+ struct udevice *dev;
+ char *led_name;
+ int ret;
+
+ led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
+ if (!led_name)
+ return 0;
+ ret = led_get_by_label(led_name, &dev);
+ if (ret) {
+ debug("%s: get=%d\n", __func__, ret);
+ return ret;
+ }
+ ret = led_set_on(dev, 1);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
+
+void spl_board_init(void)
+{
+ struct udevice *pinctrl;
+ int ret;
+
+ ret = setup_led();
+
+ if (ret) {
+ debug("LED ret=%d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret) {
+ debug("%s: Cannot find pinctrl device\n", __func__);
+ goto err;
+ }
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+ if (ret) {
+ debug("%s: Failed to set up SD card\n", __func__);
+ goto err;
+ }
+ ret = configure_emmc(pinctrl);
+ if (ret) {
+ debug("%s: Failed to set up eMMC\n", __func__);
+ goto err;
+ }
+
+ /* Enable debug UART */
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
+ if (ret) {
+ debug("%s: Failed to set up console UART\n", __func__);
+ goto err;
+ }
+
+ preloader_console_init();
+ return;
+err:
+ printf("spl_board_init: Error %d\n", ret);
+
+ /* No way to report error here */
+ hang();
+}
WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
the keyboard and battery functions.
+config ROCKCHIP_SPL_HDR
+ default "RK32"
+
+config ROCKCHIP_MAX_SPL_SIZE
+ default 0x8000
+
config SYS_SOC
default "rockchip"
+config SYS_MALLOC_F_LEN
+ default 0x0800
+
source "board/google/chromebook_jerry/Kconfig"
source "board/firefly/firefly-rk3288/Kconfig"
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/uart.h>
+#include <common.h>
+
+static struct rk_uart *uart_ptr;
+
+static void uart_wrtie_byte(char byte)
+{
+ writel(byte, &uart_ptr->rbr);
+ while (!(readl(&uart_ptr->lsr) & 0x40))
+ ;
+}
+
+void print(char *s)
+{
+ while (*s) {
+ if (*s == '\n')
+ uart_wrtie_byte('\r');
+ uart_wrtie_byte(*s);
+ s++;
+ }
+}
+
+void print_hex(unsigned int n)
+{
+ int i;
+ int temp;
+
+ uart_wrtie_byte('0');
+ uart_wrtie_byte('x');
+
+ for (i = 8; i > 0; i--) {
+ temp = (n >> (i - 1) * 4) & 0x0f;
+ if (temp < 10)
+ uart_wrtie_byte((char)(temp + '0'));
+ else
+ uart_wrtie_byte((char)(temp - 10 + 'a'));
+ }
+ uart_wrtie_byte('\n');
+ uart_wrtie_byte('\r');
+}
+
+/*
+ * TODO: since rk3036 only 4K sram to use in SPL, for saving space,
+ * we implement uart driver this way, we should convert this to use
+ * ns16550 driver in future, which support DEBUG_UART in the standard way
+ */
+void rk_uart_init(void *base)
+{
+ uart_ptr = (struct rk_uart *)base;
+ writel(0x83, &uart_ptr->lcr);
+ writel(0x0d, &uart_ptr->rbr);
+ writel(0x03, &uart_ptr->lcr);
+
+ /* fifo enable, sfe is shadow register of FCR[0] */
+ writel(0x01, &uart_ptr->sfe);
+}
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/timer.h>
+#include <asm/io.h>
+#include <common.h>
+#include <linux/types.h>
+
+struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE;
+
+static uint64_t rockchip_get_ticks(void)
+{
+ uint64_t timebase_h, timebase_l;
+
+ timebase_l = readl(&timer_ptr->timer_curr_value0);
+ timebase_h = readl(&timer_ptr->timer_curr_value1);
+
+ return timebase_h << 32 | timebase_l;
+}
+
+static uint64_t usec_to_tick(unsigned int usec)
+{
+ uint64_t tick = usec;
+ tick *= CONFIG_SYS_TIMER_RATE / (1000 * 1000);
+ return tick;
+}
+
+void rockchip_udelay(unsigned int usec)
+{
+ uint64_t tmp;
+
+ /* get timestamp */
+ tmp = rockchip_get_ticks() + usec_to_tick(usec);
+
+ /* loop till event */
+ while (rockchip_get_ticks() < tmp+1)
+ ;
+}
+
+void rockchip_timer_init(void)
+{
+ writel(0xffffffff, &timer_ptr->timer_load_count0);
+ writel(0xffffffff, &timer_ptr->timer_load_count1);
+ writel(1, &timer_ptr->timer_ctrl_reg);
+}
--- /dev/null
+if ARCH_S5PC1XX
+
+choice
+ prompt "S5PC1XX board select"
+ optional
+
+config TARGET_S5P_GONI
+ bool "S5P Goni board"
+ select OF_CONTROL
+
+config TARGET_SMDKC100
+ bool "Support smdkc100 board"
+ select OF_CONTROL
+
+endchoice
+
+config SYS_SOC
+ default "s5pc1xx"
+
+source "board/samsung/goni/Kconfig"
+source "board/samsung/smdkc100/Kconfig"
+
+endif
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cache.o
+obj-y += reset.o
+
+obj-y += clock.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Robert Baldyga <r.baldyga@samsung.com>
+ *
+ * based on arch/arm/cpu/armv7/omap3/cache.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ dcache_enable();
+}
+
+void disable_caches(void)
+{
+ dcache_disable();
+}
+#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+void v7_outer_cache_enable(void)
+{
+ __asm(
+ "push {r0, r1, r2, lr}\n\t"
+ "mrc 15, 0, r3, cr1, cr0, 1\n\t"
+ "orr r3, r3, #2\n\t"
+ "mcr 15, 0, r3, cr1, cr0, 1\n\t"
+ "pop {r1, r2, r3, pc}"
+ );
+}
+
+void v7_outer_cache_disable(void)
+{
+ __asm(
+ "push {r0, r1, r2, lr}\n\t"
+ "mrc 15, 0, r3, cr1, cr0, 1\n\t"
+ "bic r3, r3, #2\n\t"
+ "mcr 15, 0, r3, cr1, cr0, 1\n\t"
+ "pop {r1, r2, r3, pc}"
+ );
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+
+#define CLK_M 0
+#define CLK_D 1
+#define CLK_P 2
+
+#ifndef CONFIG_SYS_CLK_FREQ_C100
+#define CONFIG_SYS_CLK_FREQ_C100 12000000
+#endif
+#ifndef CONFIG_SYS_CLK_FREQ_C110
+#define CONFIG_SYS_CLK_FREQ_C110 24000000
+#endif
+
+/* s5pc110: return pll clock frequency */
+static unsigned long s5pc100_get_pll_clk(int pllreg)
+{
+ struct s5pc100_clock *clk =
+ (struct s5pc100_clock *)samsung_get_base_clock();
+ unsigned long r, m, p, s, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con);
+ break;
+ case HPLL:
+ r = readl(&clk->hpll_con);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [23:16]
+ * EPLL_CON: MIDV [23:16]
+ * HPLL_CON: MIDV [23:16]
+ */
+ if (pllreg == APLL)
+ mask = 0x3ff;
+ else
+ mask = 0x0ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ freq = CONFIG_SYS_CLK_FREQ_C100;
+ fout = m * (freq / (p * (1 << s)));
+
+ return fout;
+}
+
+/* s5pc100: return pll clock frequency */
+static unsigned long s5pc110_get_pll_clk(int pllreg)
+{
+ struct s5pc110_clock *clk =
+ (struct s5pc110_clock *)samsung_get_base_clock();
+ unsigned long r, m, p, s, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [25:16]
+ * EPLL_CON: MIDV [24:16]
+ * VPLL_CON: MIDV [24:16]
+ */
+ if (pllreg == APLL || pllreg == MPLL)
+ mask = 0x3ff;
+ else
+ mask = 0x1ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ_C110;
+ if (pllreg == APLL) {
+ if (s < 1)
+ s = 1;
+ /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+ fout = m * (freq / (p * (1 << (s - 1))));
+ } else
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ fout = m * (freq / (p * (1 << s)));
+
+ return fout;
+}
+
+/* s5pc110: return ARM clock frequency */
+static unsigned long s5pc110_get_arm_clk(void)
+{
+ struct s5pc110_clock *clk =
+ (struct s5pc110_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long dout_apll, armclk;
+ unsigned int apll_ratio;
+
+ div = readl(&clk->div0);
+
+ /* APLL_RATIO: [2:0] */
+ apll_ratio = div & 0x7;
+
+ dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+ armclk = dout_apll;
+
+ return armclk;
+}
+
+/* s5pc100: return ARM clock frequency */
+static unsigned long s5pc100_get_arm_clk(void)
+{
+ struct s5pc100_clock *clk =
+ (struct s5pc100_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long dout_apll, armclk;
+ unsigned int apll_ratio, arm_ratio;
+
+ div = readl(&clk->div0);
+
+ /* ARM_RATIO: [6:4] */
+ arm_ratio = (div >> 4) & 0x7;
+ /* APLL_RATIO: [0] */
+ apll_ratio = div & 0x1;
+
+ dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+ armclk = dout_apll / (arm_ratio + 1);
+
+ return armclk;
+}
+
+/* s5pc100: return HCLKD0 frequency */
+static unsigned long get_hclk(void)
+{
+ struct s5pc100_clock *clk =
+ (struct s5pc100_clock *)samsung_get_base_clock();
+ unsigned long hclkd0;
+ uint div, d0_bus_ratio;
+
+ div = readl(&clk->div0);
+ /* D0_BUS_RATIO: [10:8] */
+ d0_bus_ratio = (div >> 8) & 0x7;
+
+ hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
+
+ return hclkd0;
+}
+
+/* s5pc100: return PCLKD1 frequency */
+static unsigned long get_pclkd1(void)
+{
+ struct s5pc100_clock *clk =
+ (struct s5pc100_clock *)samsung_get_base_clock();
+ unsigned long d1_bus, pclkd1;
+ uint div, d1_bus_ratio, pclkd1_ratio;
+
+ div = readl(&clk->div0);
+ /* D1_BUS_RATIO: [14:12] */
+ d1_bus_ratio = (div >> 12) & 0x7;
+ /* PCLKD1_RATIO: [18:16] */
+ pclkd1_ratio = (div >> 16) & 0x7;
+
+ /* ASYNC Mode */
+ d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
+ pclkd1 = d1_bus / (pclkd1_ratio + 1);
+
+ return pclkd1;
+}
+
+/* s5pc110: return HCLKs frequency */
+static unsigned long get_hclk_sys(int dom)
+{
+ struct s5pc110_clock *clk =
+ (struct s5pc110_clock *)samsung_get_base_clock();
+ unsigned long hclk;
+ unsigned int div;
+ unsigned int offset;
+ unsigned int hclk_sys_ratio;
+
+ if (dom == CLK_M)
+ return get_hclk();
+
+ div = readl(&clk->div0);
+
+ /*
+ * HCLK_MSYS_RATIO: [10:8]
+ * HCLK_DSYS_RATIO: [19:16]
+ * HCLK_PSYS_RATIO: [27:24]
+ */
+ offset = 8 + (dom << 0x3);
+
+ hclk_sys_ratio = (div >> offset) & 0xf;
+
+ hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
+
+ return hclk;
+}
+
+/* s5pc110: return PCLKs frequency */
+static unsigned long get_pclk_sys(int dom)
+{
+ struct s5pc110_clock *clk =
+ (struct s5pc110_clock *)samsung_get_base_clock();
+ unsigned long pclk;
+ unsigned int div;
+ unsigned int offset;
+ unsigned int pclk_sys_ratio;
+
+ div = readl(&clk->div0);
+
+ /*
+ * PCLK_MSYS_RATIO: [14:12]
+ * PCLK_DSYS_RATIO: [22:20]
+ * PCLK_PSYS_RATIO: [30:28]
+ */
+ offset = 12 + (dom << 0x3);
+
+ pclk_sys_ratio = (div >> offset) & 0x7;
+
+ pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
+
+ return pclk;
+}
+
+/* s5pc110: return peripheral clock frequency */
+static unsigned long s5pc110_get_pclk(void)
+{
+ return get_pclk_sys(CLK_P);
+}
+
+/* s5pc100: return peripheral clock frequency */
+static unsigned long s5pc100_get_pclk(void)
+{
+ return get_pclkd1();
+}
+
+/* s5pc1xx: return uart clock frequency */
+static unsigned long s5pc1xx_get_uart_clk(int dev_index)
+{
+ if (cpu_is_s5pc110())
+ return s5pc110_get_pclk();
+ else
+ return s5pc100_get_pclk();
+}
+
+/* s5pc1xx: return pwm clock frequency */
+static unsigned long s5pc1xx_get_pwm_clk(void)
+{
+ if (cpu_is_s5pc110())
+ return s5pc110_get_pclk();
+ else
+ return s5pc100_get_pclk();
+}
+
+unsigned long get_pll_clk(int pllreg)
+{
+ if (cpu_is_s5pc110())
+ return s5pc110_get_pll_clk(pllreg);
+ else
+ return s5pc100_get_pll_clk(pllreg);
+}
+
+unsigned long get_arm_clk(void)
+{
+ if (cpu_is_s5pc110())
+ return s5pc110_get_arm_clk();
+ else
+ return s5pc100_get_arm_clk();
+}
+
+unsigned long get_pwm_clk(void)
+{
+ return s5pc1xx_get_pwm_clk();
+}
+
+unsigned long get_uart_clk(int dev_index)
+{
+ return s5pc1xx_get_uart_clk(dev_index);
+}
+
+void set_mmc_clk(int dev_index, unsigned int div)
+{
+ /* Do NOTHING */
+}
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_CLK_H_
+#define __ASM_ARM_ARCH_CLK_H_
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define HPLL 3
+#define VPLL 4
+
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+void set_mmc_clk(int dev_index, unsigned int div);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_H_
+#define __ASM_ARM_ARCH_CLOCK_H_
+
+#ifndef __ASSEMBLY__
+struct s5pc100_clock {
+ unsigned int apll_lock;
+ unsigned int mpll_lock;
+ unsigned int epll_lock;
+ unsigned int hpll_lock;
+ unsigned char res1[0xf0];
+ unsigned int apll_con;
+ unsigned int mpll_con;
+ unsigned int epll_con;
+ unsigned int hpll_con;
+ unsigned char res2[0xf0];
+ unsigned int src0;
+ unsigned int src1;
+ unsigned int src2;
+ unsigned int src3;
+ unsigned char res3[0xf0];
+ unsigned int div0;
+ unsigned int div1;
+ unsigned int div2;
+ unsigned int div3;
+ unsigned int div4;
+ unsigned char res4[0x1ec];
+ unsigned int gate_d00;
+ unsigned int gate_d01;
+ unsigned int gate_d02;
+ unsigned char res5[0x54];
+ unsigned int gate_sclk0;
+ unsigned int gate_sclk1;
+};
+
+struct s5pc110_clock {
+ unsigned int apll_lock;
+ unsigned char res1[0x4];
+ unsigned int mpll_lock;
+ unsigned char res2[0x4];
+ unsigned int epll_lock;
+ unsigned char res3[0xc];
+ unsigned int vpll_lock;
+ unsigned char res4[0xdc];
+ unsigned int apll_con;
+ unsigned char res5[0x4];
+ unsigned int mpll_con;
+ unsigned char res6[0x4];
+ unsigned int epll_con;
+ unsigned char res7[0xc];
+ unsigned int vpll_con;
+ unsigned char res8[0xdc];
+ unsigned int src0;
+ unsigned int src1;
+ unsigned int src2;
+ unsigned int src3;
+ unsigned char res9[0xf0];
+ unsigned int div0;
+ unsigned int div1;
+ unsigned int div2;
+ unsigned int div3;
+ unsigned int div4;
+ unsigned char res10[0x1ec];
+ unsigned int gate_d00;
+ unsigned int gate_d01;
+ unsigned int gate_d02;
+ unsigned char res11[0x54];
+ unsigned int gate_sclk0;
+ unsigned int gate_sclk1;
+};
+#endif
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _S5PC1XX_CPU_H
+#define _S5PC1XX_CPU_H
+
+#define S5P_CPU_NAME "S5P"
+#define S5PC1XX_ADDR_BASE 0xE0000000
+
+/* S5PC100 */
+#define S5PC100_PRO_ID 0xE0000000
+#define S5PC100_CLOCK_BASE 0xE0100000
+#define S5PC100_GPIO_BASE 0xE0300000
+#define S5PC100_VIC0_BASE 0xE4000000
+#define S5PC100_VIC1_BASE 0xE4100000
+#define S5PC100_VIC2_BASE 0xE4200000
+#define S5PC100_DMC_BASE 0xE6000000
+#define S5PC100_SROMC_BASE 0xE7000000
+#define S5PC100_ONENAND_BASE 0xE7100000
+#define S5PC100_PWMTIMER_BASE 0xEA000000
+#define S5PC100_WATCHDOG_BASE 0xEA200000
+#define S5PC100_UART_BASE 0xEC000000
+#define S5PC100_MMC_BASE 0xED800000
+
+/* S5PC110 */
+#define S5PC110_PRO_ID 0xE0000000
+#define S5PC110_CLOCK_BASE 0xE0100000
+#define S5PC110_GPIO_BASE 0xE0200000
+#define S5PC110_PWMTIMER_BASE 0xE2500000
+#define S5PC110_WATCHDOG_BASE 0xE2700000
+#define S5PC110_UART_BASE 0xE2900000
+#define S5PC110_SROMC_BASE 0xE8000000
+#define S5PC110_MMC_BASE 0xEB000000
+#define S5PC110_DMC0_BASE 0xF0000000
+#define S5PC110_DMC1_BASE 0xF1400000
+#define S5PC110_VIC0_BASE 0xF2000000
+#define S5PC110_VIC1_BASE 0xF2100000
+#define S5PC110_VIC2_BASE 0xF2200000
+#define S5PC110_VIC3_BASE 0xF2300000
+#define S5PC110_OTG_BASE 0xEC000000
+#define S5PC110_PHY_BASE 0xEC100000
+#define S5PC110_USB_PHY_CONTROL 0xE010E80C
+
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+/* CPU detection macros */
+extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+ return s5p_cpu_rev;
+}
+
+static inline void s5p_set_cpu_id(void)
+{
+ s5p_cpu_id = readl(S5PC100_PRO_ID);
+ s5p_cpu_rev = s5p_cpu_id & 0x000000FF;
+ s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
+}
+
+static inline char *s5p_get_cpu_name(void)
+{
+ return S5P_CPU_NAME;
+}
+
+#define IS_SAMSUNG_TYPE(type, id) \
+static inline int cpu_is_##type(void) \
+{ \
+ return s5p_cpu_id == id ? 1 : 0; \
+}
+
+IS_SAMSUNG_TYPE(s5pc100, 0xc100)
+IS_SAMSUNG_TYPE(s5pc110, 0xc110)
+
+#define SAMSUNG_BASE(device, base) \
+static inline unsigned int samsung_get_base_##device(void) \
+{ \
+ if (cpu_is_s5pc100()) \
+ return S5PC100_##base; \
+ else if (cpu_is_s5pc110()) \
+ return S5PC110_##base; \
+ else \
+ return 0; \
+}
+
+SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(gpio, GPIO_BASE)
+SAMSUNG_BASE(pro_id, PRO_ID)
+SAMSUNG_BASE(mmc, MMC_BASE)
+SAMSUNG_BASE(sromc, SROMC_BASE)
+SAMSUNG_BASE(timer, PWMTIMER_BASE)
+SAMSUNG_BASE(uart, UART_BASE)
+SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
+#endif
+
+#endif /* _S5PC1XX_CPU_H */
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#ifndef __ASSEMBLY__
+struct s5p_gpio_bank {
+ unsigned int con;
+ unsigned int dat;
+ unsigned int pull;
+ unsigned int drv;
+ unsigned int pdn_con;
+ unsigned int pdn_pull;
+ unsigned char res1[8];
+};
+
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum s5pc100_gpio_pin {
+ S5PC100_GPIO_A00,
+ S5PC100_GPIO_A01,
+ S5PC100_GPIO_A02,
+ S5PC100_GPIO_A03,
+ S5PC100_GPIO_A04,
+ S5PC100_GPIO_A05,
+ S5PC100_GPIO_A06,
+ S5PC100_GPIO_A07,
+ S5PC100_GPIO_A10,
+ S5PC100_GPIO_A11,
+ S5PC100_GPIO_A12,
+ S5PC100_GPIO_A13,
+ S5PC100_GPIO_A14,
+ S5PC100_GPIO_A15,
+ S5PC100_GPIO_A16,
+ S5PC100_GPIO_A17,
+ S5PC100_GPIO_B0,
+ S5PC100_GPIO_B1,
+ S5PC100_GPIO_B2,
+ S5PC100_GPIO_B3,
+ S5PC100_GPIO_B4,
+ S5PC100_GPIO_B5,
+ S5PC100_GPIO_B6,
+ S5PC100_GPIO_B7,
+ S5PC100_GPIO_C0,
+ S5PC100_GPIO_C1,
+ S5PC100_GPIO_C2,
+ S5PC100_GPIO_C3,
+ S5PC100_GPIO_C4,
+ S5PC100_GPIO_C5,
+ S5PC100_GPIO_C6,
+ S5PC100_GPIO_C7,
+ S5PC100_GPIO_D0,
+ S5PC100_GPIO_D1,
+ S5PC100_GPIO_D2,
+ S5PC100_GPIO_D3,
+ S5PC100_GPIO_D4,
+ S5PC100_GPIO_D5,
+ S5PC100_GPIO_D6,
+ S5PC100_GPIO_D7,
+ S5PC100_GPIO_E00,
+ S5PC100_GPIO_E01,
+ S5PC100_GPIO_E02,
+ S5PC100_GPIO_E03,
+ S5PC100_GPIO_E04,
+ S5PC100_GPIO_E05,
+ S5PC100_GPIO_E06,
+ S5PC100_GPIO_E07,
+ S5PC100_GPIO_E10,
+ S5PC100_GPIO_E11,
+ S5PC100_GPIO_E12,
+ S5PC100_GPIO_E13,
+ S5PC100_GPIO_E14,
+ S5PC100_GPIO_E15,
+ S5PC100_GPIO_E16,
+ S5PC100_GPIO_E17,
+ S5PC100_GPIO_F00,
+ S5PC100_GPIO_F01,
+ S5PC100_GPIO_F02,
+ S5PC100_GPIO_F03,
+ S5PC100_GPIO_F04,
+ S5PC100_GPIO_F05,
+ S5PC100_GPIO_F06,
+ S5PC100_GPIO_F07,
+ S5PC100_GPIO_F10,
+ S5PC100_GPIO_F11,
+ S5PC100_GPIO_F12,
+ S5PC100_GPIO_F13,
+ S5PC100_GPIO_F14,
+ S5PC100_GPIO_F15,
+ S5PC100_GPIO_F16,
+ S5PC100_GPIO_F17,
+ S5PC100_GPIO_F20,
+ S5PC100_GPIO_F21,
+ S5PC100_GPIO_F22,
+ S5PC100_GPIO_F23,
+ S5PC100_GPIO_F24,
+ S5PC100_GPIO_F25,
+ S5PC100_GPIO_F26,
+ S5PC100_GPIO_F27,
+ S5PC100_GPIO_F30,
+ S5PC100_GPIO_F31,
+ S5PC100_GPIO_F32,
+ S5PC100_GPIO_F33,
+ S5PC100_GPIO_F34,
+ S5PC100_GPIO_F35,
+ S5PC100_GPIO_F36,
+ S5PC100_GPIO_F37,
+ S5PC100_GPIO_G00,
+ S5PC100_GPIO_G01,
+ S5PC100_GPIO_G02,
+ S5PC100_GPIO_G03,
+ S5PC100_GPIO_G04,
+ S5PC100_GPIO_G05,
+ S5PC100_GPIO_G06,
+ S5PC100_GPIO_G07,
+ S5PC100_GPIO_G10,
+ S5PC100_GPIO_G11,
+ S5PC100_GPIO_G12,
+ S5PC100_GPIO_G13,
+ S5PC100_GPIO_G14,
+ S5PC100_GPIO_G15,
+ S5PC100_GPIO_G16,
+ S5PC100_GPIO_G17,
+ S5PC100_GPIO_G20,
+ S5PC100_GPIO_G21,
+ S5PC100_GPIO_G22,
+ S5PC100_GPIO_G23,
+ S5PC100_GPIO_G24,
+ S5PC100_GPIO_G25,
+ S5PC100_GPIO_G26,
+ S5PC100_GPIO_G27,
+ S5PC100_GPIO_G30,
+ S5PC100_GPIO_G31,
+ S5PC100_GPIO_G32,
+ S5PC100_GPIO_G33,
+ S5PC100_GPIO_G34,
+ S5PC100_GPIO_G35,
+ S5PC100_GPIO_G36,
+ S5PC100_GPIO_G37,
+ S5PC100_GPIO_I0,
+ S5PC100_GPIO_I1,
+ S5PC100_GPIO_I2,
+ S5PC100_GPIO_I3,
+ S5PC100_GPIO_I4,
+ S5PC100_GPIO_I5,
+ S5PC100_GPIO_I6,
+ S5PC100_GPIO_I7,
+ S5PC100_GPIO_J00,
+ S5PC100_GPIO_J01,
+ S5PC100_GPIO_J02,
+ S5PC100_GPIO_J03,
+ S5PC100_GPIO_J04,
+ S5PC100_GPIO_J05,
+ S5PC100_GPIO_J06,
+ S5PC100_GPIO_J07,
+ S5PC100_GPIO_J10,
+ S5PC100_GPIO_J11,
+ S5PC100_GPIO_J12,
+ S5PC100_GPIO_J13,
+ S5PC100_GPIO_J14,
+ S5PC100_GPIO_J15,
+ S5PC100_GPIO_J16,
+ S5PC100_GPIO_J17,
+ S5PC100_GPIO_J20,
+ S5PC100_GPIO_J21,
+ S5PC100_GPIO_J22,
+ S5PC100_GPIO_J23,
+ S5PC100_GPIO_J24,
+ S5PC100_GPIO_J25,
+ S5PC100_GPIO_J26,
+ S5PC100_GPIO_J27,
+ S5PC100_GPIO_J30,
+ S5PC100_GPIO_J31,
+ S5PC100_GPIO_J32,
+ S5PC100_GPIO_J33,
+ S5PC100_GPIO_J34,
+ S5PC100_GPIO_J35,
+ S5PC100_GPIO_J36,
+ S5PC100_GPIO_J37,
+ S5PC100_GPIO_J40,
+ S5PC100_GPIO_J41,
+ S5PC100_GPIO_J42,
+ S5PC100_GPIO_J43,
+ S5PC100_GPIO_J44,
+ S5PC100_GPIO_J45,
+ S5PC100_GPIO_J46,
+ S5PC100_GPIO_J47,
+ S5PC100_GPIO_K00,
+ S5PC100_GPIO_K01,
+ S5PC100_GPIO_K02,
+ S5PC100_GPIO_K03,
+ S5PC100_GPIO_K04,
+ S5PC100_GPIO_K05,
+ S5PC100_GPIO_K06,
+ S5PC100_GPIO_K07,
+ S5PC100_GPIO_K10,
+ S5PC100_GPIO_K11,
+ S5PC100_GPIO_K12,
+ S5PC100_GPIO_K13,
+ S5PC100_GPIO_K14,
+ S5PC100_GPIO_K15,
+ S5PC100_GPIO_K16,
+ S5PC100_GPIO_K17,
+ S5PC100_GPIO_K20,
+ S5PC100_GPIO_K21,
+ S5PC100_GPIO_K22,
+ S5PC100_GPIO_K23,
+ S5PC100_GPIO_K24,
+ S5PC100_GPIO_K25,
+ S5PC100_GPIO_K26,
+ S5PC100_GPIO_K27,
+ S5PC100_GPIO_K30,
+ S5PC100_GPIO_K31,
+ S5PC100_GPIO_K32,
+ S5PC100_GPIO_K33,
+ S5PC100_GPIO_K34,
+ S5PC100_GPIO_K35,
+ S5PC100_GPIO_K36,
+ S5PC100_GPIO_K37,
+ S5PC100_GPIO_L00,
+ S5PC100_GPIO_L01,
+ S5PC100_GPIO_L02,
+ S5PC100_GPIO_L03,
+ S5PC100_GPIO_L04,
+ S5PC100_GPIO_L05,
+ S5PC100_GPIO_L06,
+ S5PC100_GPIO_L07,
+ S5PC100_GPIO_L10,
+ S5PC100_GPIO_L11,
+ S5PC100_GPIO_L12,
+ S5PC100_GPIO_L13,
+ S5PC100_GPIO_L14,
+ S5PC100_GPIO_L15,
+ S5PC100_GPIO_L16,
+ S5PC100_GPIO_L17,
+ S5PC100_GPIO_L20,
+ S5PC100_GPIO_L21,
+ S5PC100_GPIO_L22,
+ S5PC100_GPIO_L23,
+ S5PC100_GPIO_L24,
+ S5PC100_GPIO_L25,
+ S5PC100_GPIO_L26,
+ S5PC100_GPIO_L27,
+ S5PC100_GPIO_L30,
+ S5PC100_GPIO_L31,
+ S5PC100_GPIO_L32,
+ S5PC100_GPIO_L33,
+ S5PC100_GPIO_L34,
+ S5PC100_GPIO_L35,
+ S5PC100_GPIO_L36,
+ S5PC100_GPIO_L37,
+ S5PC100_GPIO_L40,
+ S5PC100_GPIO_L41,
+ S5PC100_GPIO_L42,
+ S5PC100_GPIO_L43,
+ S5PC100_GPIO_L44,
+ S5PC100_GPIO_L45,
+ S5PC100_GPIO_L46,
+ S5PC100_GPIO_L47,
+ S5PC100_GPIO_H00,
+ S5PC100_GPIO_H01,
+ S5PC100_GPIO_H02,
+ S5PC100_GPIO_H03,
+ S5PC100_GPIO_H04,
+ S5PC100_GPIO_H05,
+ S5PC100_GPIO_H06,
+ S5PC100_GPIO_H07,
+ S5PC100_GPIO_H10,
+ S5PC100_GPIO_H11,
+ S5PC100_GPIO_H12,
+ S5PC100_GPIO_H13,
+ S5PC100_GPIO_H14,
+ S5PC100_GPIO_H15,
+ S5PC100_GPIO_H16,
+ S5PC100_GPIO_H17,
+ S5PC100_GPIO_H20,
+ S5PC100_GPIO_H21,
+ S5PC100_GPIO_H22,
+ S5PC100_GPIO_H23,
+ S5PC100_GPIO_H24,
+ S5PC100_GPIO_H25,
+ S5PC100_GPIO_H26,
+ S5PC100_GPIO_H27,
+ S5PC100_GPIO_H30,
+ S5PC100_GPIO_H31,
+ S5PC100_GPIO_H32,
+ S5PC100_GPIO_H33,
+ S5PC100_GPIO_H34,
+ S5PC100_GPIO_H35,
+ S5PC100_GPIO_H36,
+ S5PC100_GPIO_H37,
+
+ S5PC100_GPIO_MAX_PORT
+};
+
+enum s5pc110_gpio_pin {
+ S5PC110_GPIO_A00,
+ S5PC110_GPIO_A01,
+ S5PC110_GPIO_A02,
+ S5PC110_GPIO_A03,
+ S5PC110_GPIO_A04,
+ S5PC110_GPIO_A05,
+ S5PC110_GPIO_A06,
+ S5PC110_GPIO_A07,
+ S5PC110_GPIO_A10,
+ S5PC110_GPIO_A11,
+ S5PC110_GPIO_A12,
+ S5PC110_GPIO_A13,
+ S5PC110_GPIO_A14,
+ S5PC110_GPIO_A15,
+ S5PC110_GPIO_A16,
+ S5PC110_GPIO_A17,
+ S5PC110_GPIO_B0,
+ S5PC110_GPIO_B1,
+ S5PC110_GPIO_B2,
+ S5PC110_GPIO_B3,
+ S5PC110_GPIO_B4,
+ S5PC110_GPIO_B5,
+ S5PC110_GPIO_B6,
+ S5PC110_GPIO_B7,
+ S5PC110_GPIO_C00,
+ S5PC110_GPIO_C01,
+ S5PC110_GPIO_C02,
+ S5PC110_GPIO_C03,
+ S5PC110_GPIO_C04,
+ S5PC110_GPIO_C05,
+ S5PC110_GPIO_C06,
+ S5PC110_GPIO_C07,
+ S5PC110_GPIO_C10,
+ S5PC110_GPIO_C11,
+ S5PC110_GPIO_C12,
+ S5PC110_GPIO_C13,
+ S5PC110_GPIO_C14,
+ S5PC110_GPIO_C15,
+ S5PC110_GPIO_C16,
+ S5PC110_GPIO_C17,
+ S5PC110_GPIO_D00,
+ S5PC110_GPIO_D01,
+ S5PC110_GPIO_D02,
+ S5PC110_GPIO_D03,
+ S5PC110_GPIO_D04,
+ S5PC110_GPIO_D05,
+ S5PC110_GPIO_D06,
+ S5PC110_GPIO_D07,
+ S5PC110_GPIO_D10,
+ S5PC110_GPIO_D11,
+ S5PC110_GPIO_D12,
+ S5PC110_GPIO_D13,
+ S5PC110_GPIO_D14,
+ S5PC110_GPIO_D15,
+ S5PC110_GPIO_D16,
+ S5PC110_GPIO_D17,
+ S5PC110_GPIO_E00,
+ S5PC110_GPIO_E01,
+ S5PC110_GPIO_E02,
+ S5PC110_GPIO_E03,
+ S5PC110_GPIO_E04,
+ S5PC110_GPIO_E05,
+ S5PC110_GPIO_E06,
+ S5PC110_GPIO_E07,
+ S5PC110_GPIO_E10,
+ S5PC110_GPIO_E11,
+ S5PC110_GPIO_E12,
+ S5PC110_GPIO_E13,
+ S5PC110_GPIO_E14,
+ S5PC110_GPIO_E15,
+ S5PC110_GPIO_E16,
+ S5PC110_GPIO_E17,
+ S5PC110_GPIO_F00,
+ S5PC110_GPIO_F01,
+ S5PC110_GPIO_F02,
+ S5PC110_GPIO_F03,
+ S5PC110_GPIO_F04,
+ S5PC110_GPIO_F05,
+ S5PC110_GPIO_F06,
+ S5PC110_GPIO_F07,
+ S5PC110_GPIO_F10,
+ S5PC110_GPIO_F11,
+ S5PC110_GPIO_F12,
+ S5PC110_GPIO_F13,
+ S5PC110_GPIO_F14,
+ S5PC110_GPIO_F15,
+ S5PC110_GPIO_F16,
+ S5PC110_GPIO_F17,
+ S5PC110_GPIO_F20,
+ S5PC110_GPIO_F21,
+ S5PC110_GPIO_F22,
+ S5PC110_GPIO_F23,
+ S5PC110_GPIO_F24,
+ S5PC110_GPIO_F25,
+ S5PC110_GPIO_F26,
+ S5PC110_GPIO_F27,
+ S5PC110_GPIO_F30,
+ S5PC110_GPIO_F31,
+ S5PC110_GPIO_F32,
+ S5PC110_GPIO_F33,
+ S5PC110_GPIO_F34,
+ S5PC110_GPIO_F35,
+ S5PC110_GPIO_F36,
+ S5PC110_GPIO_F37,
+ S5PC110_GPIO_G00,
+ S5PC110_GPIO_G01,
+ S5PC110_GPIO_G02,
+ S5PC110_GPIO_G03,
+ S5PC110_GPIO_G04,
+ S5PC110_GPIO_G05,
+ S5PC110_GPIO_G06,
+ S5PC110_GPIO_G07,
+ S5PC110_GPIO_G10,
+ S5PC110_GPIO_G11,
+ S5PC110_GPIO_G12,
+ S5PC110_GPIO_G13,
+ S5PC110_GPIO_G14,
+ S5PC110_GPIO_G15,
+ S5PC110_GPIO_G16,
+ S5PC110_GPIO_G17,
+ S5PC110_GPIO_G20,
+ S5PC110_GPIO_G21,
+ S5PC110_GPIO_G22,
+ S5PC110_GPIO_G23,
+ S5PC110_GPIO_G24,
+ S5PC110_GPIO_G25,
+ S5PC110_GPIO_G26,
+ S5PC110_GPIO_G27,
+ S5PC110_GPIO_G30,
+ S5PC110_GPIO_G31,
+ S5PC110_GPIO_G32,
+ S5PC110_GPIO_G33,
+ S5PC110_GPIO_G34,
+ S5PC110_GPIO_G35,
+ S5PC110_GPIO_G36,
+ S5PC110_GPIO_G37,
+ S5PC110_GPIO_I0,
+ S5PC110_GPIO_I1,
+ S5PC110_GPIO_I2,
+ S5PC110_GPIO_I3,
+ S5PC110_GPIO_I4,
+ S5PC110_GPIO_I5,
+ S5PC110_GPIO_I6,
+ S5PC110_GPIO_I7,
+ S5PC110_GPIO_J00,
+ S5PC110_GPIO_J01,
+ S5PC110_GPIO_J02,
+ S5PC110_GPIO_J03,
+ S5PC110_GPIO_J04,
+ S5PC110_GPIO_J05,
+ S5PC110_GPIO_J06,
+ S5PC110_GPIO_J07,
+ S5PC110_GPIO_J10,
+ S5PC110_GPIO_J11,
+ S5PC110_GPIO_J12,
+ S5PC110_GPIO_J13,
+ S5PC110_GPIO_J14,
+ S5PC110_GPIO_J15,
+ S5PC110_GPIO_J16,
+ S5PC110_GPIO_J17,
+ S5PC110_GPIO_J20,
+ S5PC110_GPIO_J21,
+ S5PC110_GPIO_J22,
+ S5PC110_GPIO_J23,
+ S5PC110_GPIO_J24,
+ S5PC110_GPIO_J25,
+ S5PC110_GPIO_J26,
+ S5PC110_GPIO_J27,
+ S5PC110_GPIO_J30,
+ S5PC110_GPIO_J31,
+ S5PC110_GPIO_J32,
+ S5PC110_GPIO_J33,
+ S5PC110_GPIO_J34,
+ S5PC110_GPIO_J35,
+ S5PC110_GPIO_J36,
+ S5PC110_GPIO_J37,
+ S5PC110_GPIO_J40,
+ S5PC110_GPIO_J41,
+ S5PC110_GPIO_J42,
+ S5PC110_GPIO_J43,
+ S5PC110_GPIO_J44,
+ S5PC110_GPIO_J45,
+ S5PC110_GPIO_J46,
+ S5PC110_GPIO_J47,
+ S5PC110_GPIO_MP010,
+ S5PC110_GPIO_MP011,
+ S5PC110_GPIO_MP012,
+ S5PC110_GPIO_MP013,
+ S5PC110_GPIO_MP014,
+ S5PC110_GPIO_MP015,
+ S5PC110_GPIO_MP016,
+ S5PC110_GPIO_MP017,
+ S5PC110_GPIO_MP020,
+ S5PC110_GPIO_MP021,
+ S5PC110_GPIO_MP022,
+ S5PC110_GPIO_MP023,
+ S5PC110_GPIO_MP024,
+ S5PC110_GPIO_MP025,
+ S5PC110_GPIO_MP026,
+ S5PC110_GPIO_MP027,
+ S5PC110_GPIO_MP030,
+ S5PC110_GPIO_MP031,
+ S5PC110_GPIO_MP032,
+ S5PC110_GPIO_MP033,
+ S5PC110_GPIO_MP034,
+ S5PC110_GPIO_MP035,
+ S5PC110_GPIO_MP036,
+ S5PC110_GPIO_MP037,
+ S5PC110_GPIO_MP040,
+ S5PC110_GPIO_MP041,
+ S5PC110_GPIO_MP042,
+ S5PC110_GPIO_MP043,
+ S5PC110_GPIO_MP044,
+ S5PC110_GPIO_MP045,
+ S5PC110_GPIO_MP046,
+ S5PC110_GPIO_MP047,
+ S5PC110_GPIO_MP050,
+ S5PC110_GPIO_MP051,
+ S5PC110_GPIO_MP052,
+ S5PC110_GPIO_MP053,
+ S5PC110_GPIO_MP054,
+ S5PC110_GPIO_MP055,
+ S5PC110_GPIO_MP056,
+ S5PC110_GPIO_MP057,
+ S5PC110_GPIO_MP060,
+ S5PC110_GPIO_MP061,
+ S5PC110_GPIO_MP062,
+ S5PC110_GPIO_MP063,
+ S5PC110_GPIO_MP064,
+ S5PC110_GPIO_MP065,
+ S5PC110_GPIO_MP066,
+ S5PC110_GPIO_MP067,
+ S5PC110_GPIO_MP070,
+ S5PC110_GPIO_MP071,
+ S5PC110_GPIO_MP072,
+ S5PC110_GPIO_MP073,
+ S5PC110_GPIO_MP074,
+ S5PC110_GPIO_MP075,
+ S5PC110_GPIO_MP076,
+ S5PC110_GPIO_MP077,
+ S5PC110_GPIO_MP100,
+ S5PC110_GPIO_MP101,
+ S5PC110_GPIO_MP102,
+ S5PC110_GPIO_MP103,
+ S5PC110_GPIO_MP104,
+ S5PC110_GPIO_MP105,
+ S5PC110_GPIO_MP106,
+ S5PC110_GPIO_MP107,
+ S5PC110_GPIO_MP110,
+ S5PC110_GPIO_MP111,
+ S5PC110_GPIO_MP112,
+ S5PC110_GPIO_MP113,
+ S5PC110_GPIO_MP114,
+ S5PC110_GPIO_MP115,
+ S5PC110_GPIO_MP116,
+ S5PC110_GPIO_MP117,
+ S5PC110_GPIO_MP120,
+ S5PC110_GPIO_MP121,
+ S5PC110_GPIO_MP122,
+ S5PC110_GPIO_MP123,
+ S5PC110_GPIO_MP124,
+ S5PC110_GPIO_MP125,
+ S5PC110_GPIO_MP126,
+ S5PC110_GPIO_MP127,
+ S5PC110_GPIO_MP130,
+ S5PC110_GPIO_MP131,
+ S5PC110_GPIO_MP132,
+ S5PC110_GPIO_MP133,
+ S5PC110_GPIO_MP134,
+ S5PC110_GPIO_MP135,
+ S5PC110_GPIO_MP136,
+ S5PC110_GPIO_MP137,
+ S5PC110_GPIO_MP140,
+ S5PC110_GPIO_MP141,
+ S5PC110_GPIO_MP142,
+ S5PC110_GPIO_MP143,
+ S5PC110_GPIO_MP144,
+ S5PC110_GPIO_MP145,
+ S5PC110_GPIO_MP146,
+ S5PC110_GPIO_MP147,
+ S5PC110_GPIO_MP150,
+ S5PC110_GPIO_MP151,
+ S5PC110_GPIO_MP152,
+ S5PC110_GPIO_MP153,
+ S5PC110_GPIO_MP154,
+ S5PC110_GPIO_MP155,
+ S5PC110_GPIO_MP156,
+ S5PC110_GPIO_MP157,
+ S5PC110_GPIO_MP160,
+ S5PC110_GPIO_MP161,
+ S5PC110_GPIO_MP162,
+ S5PC110_GPIO_MP163,
+ S5PC110_GPIO_MP164,
+ S5PC110_GPIO_MP165,
+ S5PC110_GPIO_MP166,
+ S5PC110_GPIO_MP167,
+ S5PC110_GPIO_MP170,
+ S5PC110_GPIO_MP171,
+ S5PC110_GPIO_MP172,
+ S5PC110_GPIO_MP173,
+ S5PC110_GPIO_MP174,
+ S5PC110_GPIO_MP175,
+ S5PC110_GPIO_MP176,
+ S5PC110_GPIO_MP177,
+ S5PC110_GPIO_MP180,
+ S5PC110_GPIO_MP181,
+ S5PC110_GPIO_MP182,
+ S5PC110_GPIO_MP183,
+ S5PC110_GPIO_MP184,
+ S5PC110_GPIO_MP185,
+ S5PC110_GPIO_MP186,
+ S5PC110_GPIO_MP187,
+ S5PC110_GPIO_MP200,
+ S5PC110_GPIO_MP201,
+ S5PC110_GPIO_MP202,
+ S5PC110_GPIO_MP203,
+ S5PC110_GPIO_MP204,
+ S5PC110_GPIO_MP205,
+ S5PC110_GPIO_MP206,
+ S5PC110_GPIO_MP207,
+ S5PC110_GPIO_MP210,
+ S5PC110_GPIO_MP211,
+ S5PC110_GPIO_MP212,
+ S5PC110_GPIO_MP213,
+ S5PC110_GPIO_MP214,
+ S5PC110_GPIO_MP215,
+ S5PC110_GPIO_MP216,
+ S5PC110_GPIO_MP217,
+ S5PC110_GPIO_MP220,
+ S5PC110_GPIO_MP221,
+ S5PC110_GPIO_MP222,
+ S5PC110_GPIO_MP223,
+ S5PC110_GPIO_MP224,
+ S5PC110_GPIO_MP225,
+ S5PC110_GPIO_MP226,
+ S5PC110_GPIO_MP227,
+ S5PC110_GPIO_MP230,
+ S5PC110_GPIO_MP231,
+ S5PC110_GPIO_MP232,
+ S5PC110_GPIO_MP233,
+ S5PC110_GPIO_MP234,
+ S5PC110_GPIO_MP235,
+ S5PC110_GPIO_MP236,
+ S5PC110_GPIO_MP237,
+ S5PC110_GPIO_MP240,
+ S5PC110_GPIO_MP241,
+ S5PC110_GPIO_MP242,
+ S5PC110_GPIO_MP243,
+ S5PC110_GPIO_MP244,
+ S5PC110_GPIO_MP245,
+ S5PC110_GPIO_MP246,
+ S5PC110_GPIO_MP247,
+ S5PC110_GPIO_MP250,
+ S5PC110_GPIO_MP251,
+ S5PC110_GPIO_MP252,
+ S5PC110_GPIO_MP253,
+ S5PC110_GPIO_MP254,
+ S5PC110_GPIO_MP255,
+ S5PC110_GPIO_MP256,
+ S5PC110_GPIO_MP257,
+ S5PC110_GPIO_MP260,
+ S5PC110_GPIO_MP261,
+ S5PC110_GPIO_MP262,
+ S5PC110_GPIO_MP263,
+ S5PC110_GPIO_MP264,
+ S5PC110_GPIO_MP265,
+ S5PC110_GPIO_MP266,
+ S5PC110_GPIO_MP267,
+ S5PC110_GPIO_MP270,
+ S5PC110_GPIO_MP271,
+ S5PC110_GPIO_MP272,
+ S5PC110_GPIO_MP273,
+ S5PC110_GPIO_MP274,
+ S5PC110_GPIO_MP275,
+ S5PC110_GPIO_MP276,
+ S5PC110_GPIO_MP277,
+ S5PC110_GPIO_MP280,
+ S5PC110_GPIO_MP281,
+ S5PC110_GPIO_MP282,
+ S5PC110_GPIO_MP283,
+ S5PC110_GPIO_MP284,
+ S5PC110_GPIO_MP285,
+ S5PC110_GPIO_MP286,
+ S5PC110_GPIO_MP287,
+ S5PC110_GPIO_H00,
+ S5PC110_GPIO_H01,
+ S5PC110_GPIO_H02,
+ S5PC110_GPIO_H03,
+ S5PC110_GPIO_H04,
+ S5PC110_GPIO_H05,
+ S5PC110_GPIO_H06,
+ S5PC110_GPIO_H07,
+ S5PC110_GPIO_H10,
+ S5PC110_GPIO_H11,
+ S5PC110_GPIO_H12,
+ S5PC110_GPIO_H13,
+ S5PC110_GPIO_H14,
+ S5PC110_GPIO_H15,
+ S5PC110_GPIO_H16,
+ S5PC110_GPIO_H17,
+ S5PC110_GPIO_H20,
+ S5PC110_GPIO_H21,
+ S5PC110_GPIO_H22,
+ S5PC110_GPIO_H23,
+ S5PC110_GPIO_H24,
+ S5PC110_GPIO_H25,
+ S5PC110_GPIO_H26,
+ S5PC110_GPIO_H27,
+ S5PC110_GPIO_H30,
+ S5PC110_GPIO_H31,
+ S5PC110_GPIO_H32,
+ S5PC110_GPIO_H33,
+ S5PC110_GPIO_H34,
+ S5PC110_GPIO_H35,
+ S5PC110_GPIO_H36,
+ S5PC110_GPIO_H37,
+
+ S5PC110_GPIO_MAX_PORT
+};
+
+struct gpio_info {
+ unsigned int reg_addr; /* Address of register for this part */
+ unsigned int max_gpio; /* Maximum GPIO in this part */
+};
+
+#define S5PC100_GPIO_NUM_PARTS 1
+static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = {
+ { S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT },
+};
+
+#define S5PC110_GPIO_NUM_PARTS 1
+static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = {
+ { S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT },
+};
+
+static inline struct gpio_info *get_gpio_data(void)
+{
+ if (cpu_is_s5pc100())
+ return s5pc100_gpio_data;
+ else if (cpu_is_s5pc110())
+ return s5pc110_gpio_data;
+
+ return NULL;
+}
+
+static inline unsigned int get_bank_num(void)
+{
+ if (cpu_is_s5pc100())
+ return S5PC100_GPIO_NUM_PARTS;
+ else if (cpu_is_s5pc110())
+ return S5PC110_GPIO_NUM_PARTS;
+
+ return 0;
+}
+
+/*
+ * This structure helps mapping symbolic GPIO names into indices from
+ * exynos5_gpio_pin/exynos5420_gpio_pin enums.
+ *
+ * By convention, symbolic GPIO name is defined as follows:
+ *
+ * g[p]<bank><set><bit>, where
+ * p is optional
+ * <bank> - a single character bank name, as defined by the SOC
+ * <set> - a single digit set number
+ * <bit> - bit number within the set (in 0..7 range).
+ *
+ * <set><bit> essentially form an octal number of the GPIO pin within the bank
+ * space. On the 5420 architecture some banks' sets do not start not from zero
+ * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
+ * maintain flat number space withoout holes, those banks use offsets to be
+ * deducted from the pin number.
+ */
+struct gpio_name_num_table {
+ char bank; /* bank name symbol */
+ u8 bank_size; /* total number of pins in the bank */
+ char bank_offset; /* offset of the first bank's pin */
+ unsigned int base; /* index of the first bank's pin in the enum */
+};
+
+#define GPIO_PER_BANK 8
+#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
+static const struct gpio_name_num_table s5pc100_gpio_table[] = {
+ GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0),
+ GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0),
+ GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0),
+ GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0),
+ GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0),
+ GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0),
+ GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0),
+ GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0),
+ GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0),
+ GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0),
+ GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0),
+ GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0),
+ { 0 }
+};
+
+static const struct gpio_name_num_table s5pc110_gpio_table[] = {
+ GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0),
+ GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0),
+ GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0),
+ GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0),
+ GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0),
+ GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0),
+ GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0),
+ GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0),
+ GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0),
+ GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0),
+ { 0 }
+};
+
+/* functions */
+void gpio_cfg_pin(int gpio, int cfg);
+void gpio_set_pull(int gpio, int mode);
+void gpio_set_drv(int gpio, int mode);
+void gpio_set_rate(int gpio, int mode);
+int s5p_gpio_get_pin(unsigned gpio);
+
+/* GPIO pins per bank */
+#define GPIO_PER_BANK 8
+#endif
+
+/* Pin configurations */
+#define S5P_GPIO_INPUT 0x0
+#define S5P_GPIO_OUTPUT 0x1
+#define S5P_GPIO_IRQ 0xf
+#define S5P_GPIO_FUNC(x) (x)
+
+/* Pull mode */
+#define S5P_GPIO_PULL_NONE 0x0
+#define S5P_GPIO_PULL_DOWN 0x1
+#define S5P_GPIO_PULL_UP 0x2
+
+/* Drive Strength level */
+#define S5P_GPIO_DRV_1X 0x0
+#define S5P_GPIO_DRV_3X 0x1
+#define S5P_GPIO_DRV_2X 0x2
+#define S5P_GPIO_DRV_4X 0x3
+#define S5P_GPIO_DRV_FAST 0x0
+#define S5P_GPIO_DRV_SLOW 0x1
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MMC_H_
+#define __ASM_ARCH_MMC_H_
+
+#define S5P_MMC_DEV_OFFSET 0x100000
+
+#define SDHCI_CONTROL2 0x80
+#define SDHCI_CONTROL3 0x84
+#define SDHCI_CONTROL4 0x8C
+
+#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
+#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
+#define SDHCI_CTRL2_CDINVRXD3 (1 << 29)
+#define SDHCI_CTRL2_SLCARDOUT (1 << 28)
+
+#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
+#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
+#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
+
+#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
+#define SDHCI_CTRL2_LVLDAT_SHIFT (16)
+#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
+
+#define SDHCI_CTRL2_ENFBCLKTX (1 << 15)
+#define SDHCI_CTRL2_ENFBCLKRX (1 << 14)
+#define SDHCI_CTRL2_SDCDSEL (1 << 13)
+#define SDHCI_CTRL2_SDSIGPC (1 << 12)
+#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
+
+#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9)
+#define SDHCI_CTRL2_DFCNT_SHIFT (9)
+
+#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
+#define SDHCI_CTRL2_RWAITMODE (1 << 7)
+#define SDHCI_CTRL2_DISBUFRD (1 << 6)
+#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4)
+#define SDHCI_CTRL2_SELBASECLK_SHIFT (4)
+#define SDHCI_CTRL2_PWRSYNC (1 << 3)
+#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
+#define SDHCI_CTRL2_HWINITFIN (1 << 0)
+
+#define SDHCI_CTRL3_FCSEL3 (1 << 31)
+#define SDHCI_CTRL3_FCSEL2 (1 << 23)
+#define SDHCI_CTRL3_FCSEL1 (1 << 15)
+#define SDHCI_CTRL3_FCSEL0 (1 << 7)
+
+#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
+#define SDHCI_CTRL4_DRIVE_SHIFT (16)
+
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
+
+static inline int s5p_mmc_init(int index, int bus_width)
+{
+ unsigned int base = samsung_get_base_mmc() +
+ (S5P_MMC_DEV_OFFSET * index);
+
+ return s5p_sdhci_init(base, index, bus_width);
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals required for pinmux configuration. List will
+ * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
+ *
+ */
+enum periph_id {
+ PERIPH_ID_UART0 = 51,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_I2C0 = 56,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+ PERIPH_ID_SPI0 = 68,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_SDMMC0 = 75,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_I2C8 = 87,
+ PERIPH_ID_I2C9,
+ PERIPH_ID_I2S0 = 98,
+ PERIPH_ID_I2S1 = 99,
+
+ /* Since following peripherals do
+ * not have shared peripheral interrupts (SPIs)
+ * they are numbered arbitiraly after the maximum
+ * SPIs Exynos has (128)
+ */
+ PERIPH_ID_SROMC = 128,
+ PERIPH_ID_SPI3,
+ PERIPH_ID_SPI4,
+ PERIPH_ID_SDMMC4,
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
+ PERIPH_ID_I2C10 = 203,
+
+ PERIPH_ID_NONE = -1,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Abhilash Kesavan <a.kesavan@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PINMUX_H
+#define __ASM_ARM_ARCH_PINMUX_H
+
+#include "periph.h"
+
+/*
+ * Flags for setting specific configarations of peripherals.
+ * List will grow with support for more devices getting added.
+ */
+enum {
+ PINMUX_FLAG_NONE = 0x00000000,
+
+ /* Flags for eMMC */
+ PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
+
+ /* Flags for SROM controller */
+ PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
+ PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
+};
+
+/**
+ * Configures the pinmux for a particular peripheral.
+ *
+ * Each gpio can be configured in many different ways (4 bits on exynos)
+ * such as "input", "output", "special function", "external interrupt"
+ * etc. This function will configure the peripheral pinmux along with
+ * pull-up/down and drive strength.
+ *
+ * @param peripheral peripheral to be configured
+ * @param flags configure flags
+ * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
+ */
+int exynos_pinmux_config(int peripheral, int flags);
+
+/**
+ * Decode the peripheral id using the interrpt numbers.
+ *
+ * @param blob Device tree blob
+ * @param node FDT I2C node to find
+ * @return peripheral id if ok, PERIPH_ID_NONE on error
+ */
+int pinmux_decode_periph_id(const void *blob, int node);
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_POWER_H_
+#define __ASM_ARM_ARCH_POWER_H_
+
+/*
+ * Power control
+ */
+#define S5PC100_OTHERS 0xE0108200
+#define S5PC100_RST_STAT 0xE0108300
+#define S5PC100_SLEEP_WAKEUP (1 << 3)
+#define S5PC100_WAKEUP_STAT 0xE0108304
+#define S5PC100_INFORM0 0xE0108400
+
+#define S5PC110_RST_STAT 0xE010A000
+#define S5PC110_SLEEP_WAKEUP (1 << 3)
+#define S5PC110_WAKEUP_STAT 0xE010C200
+#define S5PC110_OTHERS 0xE010E000
+#define S5PC110_USB_PHY_CON 0xE010E80C
+#define S5PC110_INFORM0 0xE010F000
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PWM_H_
+#define __ASM_ARM_ARCH_PWM_H_
+
+#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
+#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
+
+/* Divider MUX */
+#define MUX_DIV_1 0 /* 1/1 period */
+#define MUX_DIV_2 1 /* 1/2 period */
+#define MUX_DIV_4 2 /* 1/4 period */
+#define MUX_DIV_8 3 /* 1/8 period */
+#define MUX_DIV_16 4 /* 1/16 period */
+
+#define MUX_DIV_SHIFT(x) (x * 4)
+
+#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
+
+#define TCON_START(x) (1 << TCON_OFFSET(x))
+#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
+#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
+#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
+#define TCON4_AUTO_RELOAD (1 << 22)
+
+#ifndef __ASSEMBLY__
+struct s5p_timer {
+ unsigned int tcfg0;
+ unsigned int tcfg1;
+ unsigned int tcon;
+ unsigned int tcntb0;
+ unsigned int tcmpb0;
+ unsigned int tcnto0;
+ unsigned int tcntb1;
+ unsigned int tcmpb1;
+ unsigned int tcnto1;
+ unsigned int tcntb2;
+ unsigned int tcmpb2;
+ unsigned int tcnto2;
+ unsigned int tcntb3;
+ unsigned int res1;
+ unsigned int tcnto3;
+ unsigned int tcntb4;
+ unsigned int tcnto4;
+ unsigned int tintcstat;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Note: This file contains the register description for Memory subsystem
+ * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ *
+ * Only SROMC is defined as of now
+ */
+
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
+
+#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0))
+#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
+ /* 1-> Byte base address*/
+#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2))
+#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3))
+
+#define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
+#define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
+#define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
+#define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
+#define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
+#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
+#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5p_sromc {
+ unsigned int bw;
+ unsigned int bc[6];
+};
+#endif /* __ASSEMBLY__ */
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+
+#endif /* __ASM_ARCH_SMC_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electrnoics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_device_type(void);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_UART_H_
+#define __ASM_ARCH_UART_H_
+
+#ifndef __ASSEMBLY__
+/* baudrate rest value */
+union br_rest {
+ unsigned short slot; /* udivslot */
+ unsigned char value; /* ufracval */
+};
+
+struct s5p_uart {
+ unsigned int ulcon;
+ unsigned int ucon;
+ unsigned int ufcon;
+ unsigned int umcon;
+ unsigned int utrstat;
+ unsigned int uerstat;
+ unsigned int ufstat;
+ unsigned int umstat;
+ unsigned char utxh;
+ unsigned char res1[3];
+ unsigned char urxh;
+ unsigned char res2[3];
+ unsigned int ubrdiv;
+ union br_rest rest;
+ unsigned char res3[0x3d0];
+};
+
+static inline int s5p_uart_divslot(void)
+{
+ return 1;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_WATCHDOG_H_
+#define __ASM_ARM_ARCH_WATCHDOG_H_
+
+#define WTCON_RESET_OFFSET 0
+#define WTCON_INTEN_OFFSET 2
+#define WTCON_CLKSEL_OFFSET 3
+#define WTCON_EN_OFFSET 5
+#define WTCON_PRE_OFFSET 8
+
+#define WTCON_CLK_16 0x0
+#define WTCON_CLK_32 0x1
+#define WTCON_CLK_64 0x2
+#define WTCON_CLK_128 0x3
+
+#define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET)
+#define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET)
+#define WTCON_EN (0x1 << WTCON_EN_OFFSET)
+#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
+#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct s5p_watchdog {
+ unsigned int wtcon;
+ unsigned int wtdat;
+ unsigned int wtcnt;
+ unsigned int wtclrint;
+};
+
+/* functions */
+void wdt_stop(void);
+void wdt_start(unsigned int timeout);
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2009 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/cpu.h>
+#include <linux/linkage.h>
+
+#define S5PC100_SWRESET 0xE0200000
+#define S5PC110_SWRESET 0xE0102000
+
+ENTRY(reset_cpu)
+ ldr r1, =S5PC100_PRO_ID
+ ldr r2, [r1]
+ ldr r4, =0x00010000
+ and r4, r2, r4
+ cmp r4, #0
+ bne 110f
+ /* S5PC100 */
+ ldr r1, =S5PC100_SWRESET
+ ldr r2, =0xC100
+ b 200f
+110: /* S5PC110 */
+ ldr r1, =S5PC110_SWRESET
+ mov r2, #1
+200:
+ str r2, [r1]
+_loop_forever:
+ b _loop_forever
+ENDPROC(reset_cpu)
bool "DENX MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_EBV_SOCRATES
+ bool "EBV SoCrates (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+ default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
endif
--- /dev/null
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
+#define _SOCFPGA_A10_BASE_HARDWARE_H_
+
+#define SOCFPGA_EMAC0_ADDRESS 0xff800000
+#define SOCFPGA_EMAC1_ADDRESS 0xff802000
+#define SOCFPGA_EMAC2_ADDRESS 0xff804000
+#define SOCFPGA_SDMMC_ADDRESS 0xff808000
+#define SOCFPGA_QSPIREGS_ADDRESS 0xff809000
+#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000
+#define SOCFPGA_UART1_ADDRESS 0xffc02100
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xffcfa000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400
+#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xffd03000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd00200
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd06000
+#define SOCFPGA_PINMUX_SHARED_3V_IO_ADDRESS 0xffd07000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd07200
+#define SOCFPGA_PINMUX_DEDICATED_IO_CFG_ADDRESS 0xffd07300
+#define SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS 0xffd07400
+#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
+#define SOCFPGA_MPUSCU_ADDRESS 0xffffc000
+#define SOCFPGA_MPUL2_ADDRESS 0xfffff000
+#define SOCFPGA_I2C0_ADDRESS 0xffc02200
+#define SOCFPGA_I2C1_ADDRESS 0xffc02300
+
+#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#define SOCFPGA_SDR_ADDRESS 0xffcfb000
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400
+#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
+#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300
+#define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400
+
+#endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_STM_ADDRESS 0xfc000000
+#define SOCFPGA_DAP_ADDRESS 0xff000000
+#define SOCFPGA_EMAC0_ADDRESS 0xff700000
+#define SOCFPGA_EMAC1_ADDRESS 0xff702000
+#define SOCFPGA_SDMMC_ADDRESS 0xff704000
+#define SOCFPGA_QSPI_ADDRESS 0xff705000
+#define SOCFPGA_GPIO0_ADDRESS 0xff708000
+#define SOCFPGA_GPIO1_ADDRESS 0xff709000
+#define SOCFPGA_GPIO2_ADDRESS 0xff70a000
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_USB0_ADDRESS 0xffb00000
+#define SOCFPGA_USB1_ADDRESS 0xffb40000
+#define SOCFPGA_CAN0_ADDRESS 0xffc00000
+#define SOCFPGA_CAN1_ADDRESS 0xffc01000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_I2C0_ADDRESS 0xffc04000
+#define SOCFPGA_I2C1_ADDRESS 0xffc05000
+#define SOCFPGA_I2C2_ADDRESS 0xffc06000
+#define SOCFPGA_I2C3_ADDRESS 0xffc07000
+#define SOCFPGA_SDR_ADDRESS 0xffc20000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
+#define SOCFPGA_L4WD1_ADDRESS 0xffd03000
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
+#define SOCFPGA_SPIS0_ADDRESS 0xffe02000
+#define SOCFPGA_SPIS1_ADDRESS 0xffe03000
+#define SOCFPGA_SPIM0_ADDRESS 0xfff00000
+#define SOCFPGA_SPIM1_ADDRESS 0xfff01000
+#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
+#define SOCFPGA_ROM_ADDRESS 0xfffd0000
+#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000
+#define SOCFPGA_MPUL2_ADDRESS 0xfffef000
+#define SOCFPGA_OCRAM_ADDRESS 0xffff0000
+#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000
+#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000
+#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000
+#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000
+#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000
+#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000
+#define SOCFPGA_NANDDATA_ADDRESS 0xff900000
+#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000
+#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000
+#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000
+#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000
+#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000
+#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000
+#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */
u32 per2_mod_reset;
u32 brg_mod_reset;
u32 misc_mod_reset;
+ u32 padding2[12];
u32 tstscratch;
};
+++ /dev/null
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SOCFPGA_BASE_ADDRS_H_
-#define _SOCFPGA_BASE_ADDRS_H_
-
-#define SOCFPGA_STM_ADDRESS 0xfc000000
-#define SOCFPGA_DAP_ADDRESS 0xff000000
-#define SOCFPGA_EMAC0_ADDRESS 0xff700000
-#define SOCFPGA_EMAC1_ADDRESS 0xff702000
-#define SOCFPGA_SDMMC_ADDRESS 0xff704000
-#define SOCFPGA_QSPI_ADDRESS 0xff705000
-#define SOCFPGA_GPIO0_ADDRESS 0xff708000
-#define SOCFPGA_GPIO1_ADDRESS 0xff709000
-#define SOCFPGA_GPIO2_ADDRESS 0xff70a000
-#define SOCFPGA_L3REGS_ADDRESS 0xff800000
-#define SOCFPGA_USB0_ADDRESS 0xffb00000
-#define SOCFPGA_USB1_ADDRESS 0xffb40000
-#define SOCFPGA_CAN0_ADDRESS 0xffc00000
-#define SOCFPGA_CAN1_ADDRESS 0xffc01000
-#define SOCFPGA_UART0_ADDRESS 0xffc02000
-#define SOCFPGA_UART1_ADDRESS 0xffc03000
-#define SOCFPGA_I2C0_ADDRESS 0xffc04000
-#define SOCFPGA_I2C1_ADDRESS 0xffc05000
-#define SOCFPGA_I2C2_ADDRESS 0xffc06000
-#define SOCFPGA_I2C3_ADDRESS 0xffc07000
-#define SOCFPGA_SDR_ADDRESS 0xffc20000
-#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
-#define SOCFPGA_L4WD1_ADDRESS 0xffd03000
-#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
-#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
-#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
-#define SOCFPGA_SPIS0_ADDRESS 0xffe02000
-#define SOCFPGA_SPIS1_ADDRESS 0xffe03000
-#define SOCFPGA_SPIM0_ADDRESS 0xfff00000
-#define SOCFPGA_SPIM1_ADDRESS 0xfff01000
-#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
-#define SOCFPGA_ROM_ADDRESS 0xfffd0000
-#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000
-#define SOCFPGA_MPUL2_ADDRESS 0xfffef000
-#define SOCFPGA_OCRAM_ADDRESS 0xffff0000
-#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000
-#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000
-#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000
-#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000
-#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000
-#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000
-#define SOCFPGA_NANDDATA_ADDRESS 0xff900000
-#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000
-#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000
-#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000
-#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000
-#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000
-#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
-#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000
-#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000
-#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000
-
-#endif /* _SOCFPGA_BASE_ADDRS_H_ */
if TEGRA
-config TEGRA_ARMV7_COMMON
- bool "Tegra 32-bit"
- select SUPPORT_SPL
- select SPL
- select OF_CONTROL
- select CPU_V7
+config TEGRA_COMMON
+ bool "Tegra common options"
select DM
- select DM_SPI_FLASH
- select DM_SERIAL
- select DM_I2C
- select DM_SPI
select DM_GPIO
+ select DM_I2C
select DM_KEYBOARD
+ select DM_PCI
+ select DM_PCI_COMPAT
+ select DM_SERIAL
+ select DM_SPI
+ select DM_SPI_FLASH
+ select OF_CONTROL
+
+config TEGRA_ARMV7_COMMON
+ bool "Tegra 32-bit common options"
+ select CPU_V7
+ select SPL
+ select SUPPORT_SPL
+ select TEGRA_COMMON
+
+config TEGRA_ARMV8_COMMON
+ bool "Tegra 64-bit common options"
+ select ARM64
+ select TEGRA_COMMON
choice
prompt "Tegra SoC select"
config TEGRA210
bool "Tegra210 family"
- select OF_CONTROL
- select ARM64
- select DM
- select DM_SPI_FLASH
- select DM_SERIAL
- select DM_I2C
- select DM_SPI
- select DM_GPIO
+ select TEGRA_ARMV8_COMMON
endchoice
*/
#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
setup_uarts(uart_ids);
}
+#if CONFIG_IS_ENABLED(DM_SERIAL) && !CONFIG_IS_ENABLED(OF_CONTROL)
+static struct ns16550_platdata ns16550_com1_pdata = {
+ .base = CONFIG_SYS_NS16550_COM1,
+ .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK,
+};
+
+U_BOOT_DEVICE(ns16550_com1) = {
+ "ns16550_serial", &ns16550_com1_pdata
+};
+#endif
+
#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
+#ifdef CONFIG_PCI
+ gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
+#endif
+
#ifdef CONFIG_PHYS_64BIT
if (gd->ram_size > SZ_2G) {
gd->bd->bi_dram[1].start = 0x100000000;
chosen {
bootargs = "debug console=ttyS0,115200";
- stdout-path = &uart_0;
+ stdout-path = &a_16550_uart_0;
};
};
source "board/gdsys/dlvision/Kconfig"
source "board/gdsys/gdppc440etx/Kconfig"
source "board/gdsys/intip/Kconfig"
-source "board/lwmon5/Kconfig"
+source "board/liebherr/lwmon5/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
..no_pllset:
#endif /* CONFIG_BUBINGA */
-#ifdef CONFIG_TAIHU
- mfdcr r4, CPC0_BOOT
- andi. r5, r4, CPC0_BOOT_SEP@l
- bne strap_1 /* serial eeprom present */
- addis r5,0,CPLD_REG0_ADDR@h
- ori r5,r5,CPLD_REG0_ADDR@l
- andi. r5, r5, 0x10
- bne _pci_66mhz
-#endif /* CONFIG_TAIHU */
-
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
ori r3,r3,PLLMR0_DEFAULT@l /* */
addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
ori r4,r4,PLLMR1_DEFAULT@l /* */
-#ifdef CONFIG_TAIHU
- b 1f
-_pci_66mhz:
- addis r3,0,PLLMR0_DEFAULT_PCI66@h
- ori r3,r3,PLLMR0_DEFAULT_PCI66@l
- addis r4,0,PLLMR1_DEFAULT_PCI66@h
- ori r4,r4,PLLMR1_DEFAULT_PCI66@l
- b 1f
-strap_1:
- mfdcr r3, CPC0_PLLMR0
- mfdcr r4, CPC0_PLLMR1
-#endif /* CONFIG_TAIHU */
-
1:
b pll_write /* Write the CPC0_PLLMR with new value */
/* All PPC boards must swap IDE bytes */
#define CONFIG_IDE_SWAP_IO
+#if defined(CONFIG_DM_SERIAL)
+/*
+ * TODO: Convert this to a clock driver exists that can give us the UART
+ * clock here.
+ */
+#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#endif
+
#endif /* _ASM_CONFIG_H_ */
timer {
compatible = "sandbox,timer";
+ clock-frequency = <1000000>;
};
tpm {
depends on X86_RESET_VECTOR
default 0xfffff800
+config DM_PCI_COMPAT
+ default y # Until we finish moving over to the new API
+
config BOARD_ROMSIZE_KB_512
bool
config BOARD_ROMSIZE_KB_1024
the memory used by this initialisation process. Typically 4KB is
enough space.
-config TSC_CALIBRATION_BYPASS
- bool "Bypass Time-Stamp Counter (TSC) calibration"
- default n
- help
- By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
- running frequency via Model-Specific Register (MSR) and Programmable
- Interval Timer (PIT). If the calibration does not work on your board,
- select this option and provide a hardcoded TSC running frequency with
- CONFIG_TSC_FREQ_IN_MHZ below.
-
- Normally this option should be turned on in a simulation environment
- like qemu.
-
-config TSC_FREQ_IN_MHZ
- int "Time-Stamp Counter (TSC) running frequency in MHz"
- depends on TSC_CALIBRATION_BYPASS
- default 1000
- help
- The running frequency in MHz of Time-Stamp Counter (TSC).
-
config HAVE_VGA_BIOS
bool "Add a VGA BIOS image"
help
int ret;
post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- timer_set_base(rdtsc());
-#endif
ret = x86_cpu_init_f();
if (ret)
void timestamp_init(void)
{
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- uint64_t base_time;
-#endif
-
- ts_table = lib_sysinfo.tstamp_table;
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- /*
- * If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
- * of base_time in coreboot's timestamp table as our timer base,
- * otherwise TSC counter value will be used.
- *
- * Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
- * the value of base_time in the timestamp table is still zero, so
- * we must exclude this case too (this is currently seen on booting
- * coreboot in qemu)
- */
- if (ts_table && ts_table->base_time)
- base_time = ts_table->base_time;
- else
- base_time = rdtsc();
- timer_set_base(base_time);
-#endif
timestamp_add_now(TS_U_BOOT_INITTED);
}
void show_boot_progress(int val)
{
-#if MIN_PORT80_KCLOCKS_DELAY
- /*
- * Scale the time counter reading to avoid using 64 bit arithmetics.
- * Can't use get_timer() here becuase it could be not yet
- * initialized or even implemented.
- */
- if (!gd->arch.tsc_prev) {
- gd->arch.tsc_base_kclocks = rdtsc() / 1000;
- gd->arch.tsc_prev = 0;
- } else {
- uint32_t now;
-
- do {
- now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
- } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
- gd->arch.tsc_prev = now;
- }
-#endif
outb(val, POST_PORT);
}
int arch_cpu_init(void)
{
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- timer_set_base(rdtsc());
-#endif
-
return 0;
}
int arch_cpu_init(void)
{
post_code(POST_CPU_INIT);
- timer_set_base(rdtsc());
return x86_cpu_init_f();
}
config QEMU
bool
- select TSC_CALIBRATION_BYPASS
if QEMU
int ret;
post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- timer_set_base(rdtsc());
-#endif
ret = x86_cpu_init_f();
if (ret)
config INTEL_QUARK
bool
select HAVE_RMU
- select TSC_CALIBRATION_BYPASS
if INTEL_QUARK
Space in bytes in eSRAM used as Cache-As-ARM (CAR).
Note this size must not exceed eSRAM's total size.
-config TSC_FREQ_IN_MHZ
- int
- default 400
-
endif
int ret;
post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- timer_set_base(rdtsc());
-#endif
ret = x86_cpu_init_f();
if (ret)
int ret;
post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- timer_set_base(rdtsc());
-#endif
ret = x86_cpu_init_f();
if (ret)
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
/ {
model = "Intel Bayley Bay";
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
/ {
model = "Advantech SOM-6896";
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
/ {
model = "Google Link";
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
/ {
model = "Google Panther";
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
/ {
model = "Intel Crown Bay";
/dts-v1/;
/include/ "skeleton.dtsi"
+/include/ "tsc_timer.dtsi"
/ {
model = "EFI";
stdout-path = &serial;
};
+ tsc-timer {
+ clock-frequency = <1000000000>;
+ };
+
serial: serial {
compatible = "efi,uart";
};
/include/ "skeleton.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
/ {
model = "Intel Galileo";
stdout-path = &pciuart0;
};
+ tsc-timer {
+ clock-frequency = <400000000>;
+ };
+
mrc {
compatible = "intel,quark-mrc";
flags = <MRC_FLAG_SCRAMBLE_EN>;
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
/ {
model = "Intel Minnowboard Max";
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
/ {
model = "QEMU x86 (I440FX)";
};
};
+ tsc-timer {
+ clock-frequency = <1000000000>;
+ };
+
pci {
compatible = "pci-x86";
#address-cells = <3>;
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
/ {
model = "QEMU x86 (Q35)";
};
};
+ tsc-timer {
+ clock-frequency = <1000000000>;
+ };
+
pci {
compatible = "pci-x86";
#address-cells = <3>;
/ {
serial: serial {
- compatible = "x86-uart";
+ compatible = "ns16550";
reg = <0x3f8 8>;
reg-shift = <0>;
clock-frequency = <1843200>;
--- /dev/null
+/ {
+ tsc-timer {
+ compatible = "x86,tsc-timer";
+ u-boot,dm-pre-reloc;
+ };
+};
uint8_t x86_mask;
uint32_t x86_device;
uint64_t tsc_base; /* Initial value returned by rdtsc() */
- uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */
- uint32_t tsc_prev; /* For show_boot_progress() */
- uint32_t tsc_mhz; /* TSC frequency in MHz */
void *new_fdt; /* Relocated FDT */
uint32_t bist; /* Built-in self test value */
enum pei_boot_mode_t pei_boot_mode;
obj-y += string.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
obj-y += tables.o
-obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o
obj-$(CONFIG_CMD_ZBOOT) += zimage.o
obj-$(CONFIG_HAVE_FSP) += fsp/
+++ /dev/null
-/*
- * Copyright (c) 2012 The Chromium OS Authors.
- *
- * TSC calibration codes are adapted from Linux kernel
- * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/i8254.h>
-#include <asm/ibmpc.h>
-#include <asm/msr.h>
-#include <asm/u-boot-x86.h>
-
-/* CPU reference clock frequency: in KHz */
-#define FREQ_83 83200
-#define FREQ_100 99840
-#define FREQ_133 133200
-#define FREQ_166 166400
-
-#define MAX_NUM_FREQS 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * According to Intel 64 and IA-32 System Programming Guide,
- * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
- * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
- * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
- * so we need manually differentiate SoC families. This is what the
- * field msr_plat does.
- */
-struct freq_desc {
- u8 x86_family; /* CPU family */
- u8 x86_model; /* model */
- /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
- u8 msr_plat;
- u32 freqs[MAX_NUM_FREQS];
-};
-
-static struct freq_desc freq_desc_tables[] = {
- /* PNW */
- { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
- /* CLV+ */
- { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
- /* TNG */
- { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
- /* VLV2 */
- { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
- /* Ivybridge */
- { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
- /* ANN */
- { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
-};
-
-static int match_cpu(u8 family, u8 model)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
- if ((family == freq_desc_tables[i].x86_family) &&
- (model == freq_desc_tables[i].x86_model))
- return i;
- }
-
- return -1;
-}
-
-/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
-#define id_to_freq(cpu_index, freq_id) \
- (freq_desc_tables[cpu_index].freqs[freq_id])
-
-/*
- * Do MSR calibration only for known/supported CPUs.
- *
- * Returns the calibration value or 0 if MSR calibration failed.
- */
-static unsigned long __maybe_unused try_msr_calibrate_tsc(void)
-{
- u32 lo, hi, ratio, freq_id, freq;
- unsigned long res;
- int cpu_index;
-
- cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
- if (cpu_index < 0)
- return 0;
-
- if (freq_desc_tables[cpu_index].msr_plat) {
- rdmsr(MSR_PLATFORM_INFO, lo, hi);
- ratio = (lo >> 8) & 0x1f;
- } else {
- rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
- ratio = (hi >> 8) & 0x1f;
- }
- debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
-
- if (!ratio)
- goto fail;
-
- if (freq_desc_tables[cpu_index].msr_plat == 2) {
- /* TODO: Figure out how best to deal with this */
- freq = FREQ_100;
- debug("Using frequency: %u KHz\n", freq);
- } else {
- /* Get FSB FREQ ID */
- rdmsr(MSR_FSB_FREQ, lo, hi);
- freq_id = lo & 0x7;
- freq = id_to_freq(cpu_index, freq_id);
- debug("Resolved frequency ID: %u, frequency: %u KHz\n",
- freq_id, freq);
- }
- if (!freq)
- goto fail;
-
- /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
- res = freq * ratio / 1000;
- debug("TSC runs at %lu MHz\n", res);
-
- return res;
-
-fail:
- debug("Fast TSC calibration using MSR failed\n");
- return 0;
-}
-
-/*
- * This reads the current MSB of the PIT counter, and
- * checks if we are running on sufficiently fast and
- * non-virtualized hardware.
- *
- * Our expectations are:
- *
- * - the PIT is running at roughly 1.19MHz
- *
- * - each IO is going to take about 1us on real hardware,
- * but we allow it to be much faster (by a factor of 10) or
- * _slightly_ slower (ie we allow up to a 2us read+counter
- * update - anything else implies a unacceptably slow CPU
- * or PIT for the fast calibration to work.
- *
- * - with 256 PIT ticks to read the value, we have 214us to
- * see the same MSB (and overhead like doing a single TSC
- * read per MSB value etc).
- *
- * - We're doing 2 reads per loop (LSB, MSB), and we expect
- * them each to take about a microsecond on real hardware.
- * So we expect a count value of around 100. But we'll be
- * generous, and accept anything over 50.
- *
- * - if the PIT is stuck, and we see *many* more reads, we
- * return early (and the next caller of pit_expect_msb()
- * then consider it a failure when they don't see the
- * next expected value).
- *
- * These expectations mean that we know that we have seen the
- * transition from one expected value to another with a fairly
- * high accuracy, and we didn't miss any events. We can thus
- * use the TSC value at the transitions to calculate a pretty
- * good value for the TSC frequencty.
- */
-static inline int pit_verify_msb(unsigned char val)
-{
- /* Ignore LSB */
- inb(0x42);
- return inb(0x42) == val;
-}
-
-static inline int pit_expect_msb(unsigned char val, u64 *tscp,
- unsigned long *deltap)
-{
- int count;
- u64 tsc = 0, prev_tsc = 0;
-
- for (count = 0; count < 50000; count++) {
- if (!pit_verify_msb(val))
- break;
- prev_tsc = tsc;
- tsc = rdtsc();
- }
- *deltap = rdtsc() - prev_tsc;
- *tscp = tsc;
-
- /*
- * We require _some_ success, but the quality control
- * will be based on the error terms on the TSC values.
- */
- return count > 5;
-}
-
-/*
- * How many MSB values do we want to see? We aim for
- * a maximum error rate of 500ppm (in practice the
- * real error is much smaller), but refuse to spend
- * more than 50ms on it.
- */
-#define MAX_QUICK_PIT_MS 50
-#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
-
-static unsigned long __maybe_unused quick_pit_calibrate(void)
-{
- int i;
- u64 tsc, delta;
- unsigned long d1, d2;
-
- /* Set the Gate high, disable speaker */
- outb((inb(0x61) & ~0x02) | 0x01, 0x61);
-
- /*
- * Counter 2, mode 0 (one-shot), binary count
- *
- * NOTE! Mode 2 decrements by two (and then the
- * output is flipped each time, giving the same
- * final output frequency as a decrement-by-one),
- * so mode 0 is much better when looking at the
- * individual counts.
- */
- outb(0xb0, 0x43);
-
- /* Start at 0xffff */
- outb(0xff, 0x42);
- outb(0xff, 0x42);
-
- /*
- * The PIT starts counting at the next edge, so we
- * need to delay for a microsecond. The easiest way
- * to do that is to just read back the 16-bit counter
- * once from the PIT.
- */
- pit_verify_msb(0);
-
- if (pit_expect_msb(0xff, &tsc, &d1)) {
- for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
- if (!pit_expect_msb(0xff-i, &delta, &d2))
- break;
-
- /*
- * Iterate until the error is less than 500 ppm
- */
- delta -= tsc;
- if (d1+d2 >= delta >> 11)
- continue;
-
- /*
- * Check the PIT one more time to verify that
- * all TSC reads were stable wrt the PIT.
- *
- * This also guarantees serialization of the
- * last cycle read ('d2') in pit_expect_msb.
- */
- if (!pit_verify_msb(0xfe - i))
- break;
- goto success;
- }
- }
- debug("Fast TSC calibration failed\n");
- return 0;
-
-success:
- /*
- * Ok, if we get here, then we've seen the
- * MSB of the PIT decrement 'i' times, and the
- * error has shrunk to less than 500 ppm.
- *
- * As a result, we can depend on there not being
- * any odd delays anywhere, and the TSC reads are
- * reliable (within the error).
- *
- * kHz = ticks / time-in-seconds / 1000;
- * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
- * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
- */
- delta *= PIT_TICK_RATE;
- delta /= (i*256*1000);
- debug("Fast TSC calibration using PIT\n");
- return delta / 1000;
-}
-
-void timer_set_base(u64 base)
-{
- gd->arch.tsc_base = base;
-}
-
-/*
- * Get the number of CPU time counter ticks since it was read first time after
- * restart. This yields a free running counter guaranteed to take almost 6
- * years to wrap around even at 100GHz clock rate.
- */
-u64 __attribute__((no_instrument_function)) get_ticks(void)
-{
- u64 now_tick = rdtsc();
-
- /* We assume that 0 means the base hasn't been set yet */
- if (!gd->arch.tsc_base)
- panic("No tick base available");
- return now_tick - gd->arch.tsc_base;
-}
-
-/* Get the speed of the TSC timer in MHz */
-unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
-{
- unsigned long fast_calibrate;
-
- if (gd->arch.tsc_mhz)
- return gd->arch.tsc_mhz;
-
-#ifdef CONFIG_TSC_CALIBRATION_BYPASS
- fast_calibrate = CONFIG_TSC_FREQ_IN_MHZ;
-#else
- fast_calibrate = try_msr_calibrate_tsc();
- if (!fast_calibrate) {
-
- fast_calibrate = quick_pit_calibrate();
- if (!fast_calibrate)
- panic("TSC frequency is ZERO");
- }
-#endif
-
- gd->arch.tsc_mhz = fast_calibrate;
- return fast_calibrate;
-}
-
-unsigned long get_tbclk(void)
-{
- return get_tbclk_mhz() * 1000 * 1000;
-}
-
-static ulong get_ms_timer(void)
-{
- return (get_ticks() * 1000) / get_tbclk();
-}
-
-ulong get_timer(ulong base)
-{
- return get_ms_timer() - base;
-}
-
-ulong __attribute__((no_instrument_function)) timer_get_us(void)
-{
- return get_ticks() / get_tbclk_mhz();
-}
-
-ulong timer_get_boot_us(void)
-{
- return timer_get_us();
-}
-
-void __udelay(unsigned long usec)
-{
- u64 now = get_ticks();
- u64 stop;
-
- stop = now + usec * get_tbclk_mhz();
-
- while ((int64_t)(stop - get_ticks()) > 0)
-#if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
- /*
- * Add a 'pause' instruction on qemu target,
- * to give other VCPUs a chance to run.
- */
- asm volatile("pause");
-#else
- ;
-#endif
-}
-
-int timer_init(void)
-{
-#ifdef CONFIG_I8254_TIMER
- /* Set up the i8254 timer if required */
- i8254_init();
-#endif
-
- return 0;
-}
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := vexpress64.o pcie.o
+obj-y := vexpress64.o
+obj-$(CONFIG_TARGET_VEXPRESS64_JUNO) += pcie.o
writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
- printf("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
+ debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,
((u64)1) << window_size, trsl_param);
}
void vexpress64_pcie_init(void)
{
-#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
xr3pci_init();
-#endif
}
.platdata = &serial_platdata,
};
+/* This function gets replaced by platforms supporting PCIe.
+ * The replacement function, eg. on Juno, initialises the PCIe bus.
+ */
+__weak void vexpress64_pcie_init(void)
+{
+}
+
int board_init(void)
{
vexpress64_pcie_init();
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#ifdef PHYS_SDRAM_2
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
}
/*
--- /dev/null
+if TARGET_SAMA5D2_XPLAINED
+
+config SYS_BOARD
+ default "sama5d2_xplained"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d2_xplained"
+
+endif
--- /dev/null
+SAMA5D2 XPLAINED BOARD
+M: Wenyou Yang <wenyou.yang@atmel.com>
+S: Maintained
+F: board/atmel/sama5d2_xplained/
+F: include/configs/sama5d2_xplained.h
+F: configs/sama5d2_xplained_mmc_defconfig
+F: configs/sama5d2_xplained_spiflash_defconfig
--- /dev/null
+#
+# Copyright (C) 2015 Atmel Corporation
+# Wenyou Yang <wenyou.yang@atmel.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sama5d2_xplained.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_hlcdc.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5d2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+}
+
+static void board_spi0_hw_init(void)
+{
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
+
+ atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+
+ at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+
+static void board_usb_hw_init(void)
+{
+ atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
+}
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 480,
+ .vl_row = 272,
+ .vl_clk = 9000000,
+ .vl_bpix = LCD_BPP,
+ .vl_tft = 1,
+ .vl_hsync_len = 41,
+ .vl_left_margin = 2,
+ .vl_right_margin = 2,
+ .vl_vsync_len = 11,
+ .vl_upper_margin = 2,
+ .vl_lower_margin = 2,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+/* No power up/down pin for the LCD pannel */
+void lcd_enable(void) { /* Empty! */ }
+void lcd_disable(void) { /* Empty! */ }
+
+unsigned int has_lcdc(void)
+{
+ return 1;
+}
+
+static void board_lcd_hw_init(void)
+{
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */
+
+ /* LCDDAT0 */
+ /* LCDDAT1 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */
+
+ /* LCDDAT8 */
+ /* LCDDAT9 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */
+
+ /* LCDD16 */
+ /* LCDD17 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */
+
+ at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+ ulong dram_size;
+ int i;
+ char temp[32];
+
+ lcd_printf("%s\n", U_BOOT_VERSION);
+ lcd_printf("2015 ATMEL Corp\n");
+ lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+
+ lcd_printf("%ld MB SDRAM\n", dram_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+static void board_gmac_hw_init(void)
+{
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */
+
+ at91_periph_clk_enable(ATMEL_ID_GMAC);
+}
+
+static void board_sdhci0_hw_init(void)
+{
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SDMMC0_CK */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SDMMC0_CMD */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SDMMC0_DAT0 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* SDMMC0_DAT1 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* SDMMC0_DAT2 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* SDMMC0_DAT3 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0); /* SDMMC0_DAT4 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0); /* SDMMC0_DAT5 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0); /* SDMMC0_DAT6 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0); /* SDMMC0_DAT7 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */
+
+ at91_periph_clk_enable(ATMEL_ID_SDMMC0);
+ at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
+ GCK_CSS_PLLA_CLK, 1);
+}
+
+static void board_sdhci1_hw_init(void)
+{
+ atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0); /* SDMMC1_DAT0 */
+ atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0); /* SDMMC1_DAT1 */
+ atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0); /* SDMMC1_DAT2 */
+ atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0); /* SDMMC1_DAT3 */
+ atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0); /* SDMMC1_CK */
+ atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0); /* SDMMC1_RSTN */
+ atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0); /* SDMMC1_CMD */
+ atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0); /* SDMMC1_CD */
+
+ at91_periph_clk_enable(ATMEL_ID_SDMMC1);
+ at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
+ GCK_CSS_PLLA_CLK, 1);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_ATMEL_SDHCI0
+ atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0);
+#endif
+#ifdef CONFIG_ATMEL_SDHCI1
+ atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1);
+#endif
+
+ return 0;
+}
+
+static void board_uart1_hw_init(void)
+{
+ atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */
+ atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
+
+ at91_periph_clk_enable(ATMEL_ID_UART1);
+}
+
+int board_early_init_f(void)
+{
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+ board_uart1_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+ board_spi0_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SDHCI
+#ifdef CONFIG_ATMEL_SDHCI0
+ board_sdhci0_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SDHCI1
+ board_sdhci1_hw_init();
+#endif
+#endif
+#ifdef CONFIG_MACB
+ board_gmac_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ board_lcd_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+ board_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+ at91_udp_hw_init();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+ usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+ usb_eth_initialize(bis);
+#endif
+#endif
+
+ return rc;
+}
int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom)
{
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
unsigned int bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE);
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
-#endif
if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) {
warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC,
int ret;
unsigned char *p;
int i;
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- unsigned int bus;
-#endif
memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE);
print_buffer(0, &eeprom, 1, sizeof(eeprom), 16);
#endif
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
+ eeprom_init(CONFIG_SYS_EEPROM_BUS_NUM);
- /* do page write to the eeprom */
- for (i = 0, p = (unsigned char *)&eeprom;
- i < sizeof(eeprom);
- i += 32, p += 32) {
- ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
- p, min(sizeof(eeprom) - i, 32));
- if (ret)
- break;
- udelay(5000); /* 5ms write cycle timing */
- }
+ ret = eeprom_write(devaddr, 0, (unsigned char *)&eeprom,
+ TRICORDER_EEPROM_SIZE);
+ if (ret)
+ printf("Tricorder: Could not write EEPROM content!\n");
- ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify,
+ ret = eeprom_read(devaddr, 0, (unsigned char *)&eeprom_verify,
TRICORDER_EEPROM_SIZE);
+ if (ret)
+ printf("Tricorder: Could not read EEPROM content!\n");
if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) {
printf("Tricorder: Could not verify EEPROM content!\n");
ret = 1;
}
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- i2c_set_bus_num(bus);
-#endif
return ret;
}
{
if (argc == 3) {
ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
- eeprom_init();
+
if (strcmp(argv[1], "read") == 0) {
int rcode;
char *version = argv[4];
char *serial = argv[5];
char *interface = NULL;
- eeprom_init();
if (argc == 7)
interface = argv[6];
--- /dev/null
+SOCRATES BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/ebv/socrates/
+F: include/configs/socfpga_socrates.h
+F: configs/socfpga_socrates_defconfig
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga.o
--- /dev/null
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00004824,
+ 0x01209000,
+ 0x82400000,
+ 0x00018004,
+ 0x00000000,
+ 0x00004000,
+ 0x00002412,
+ 0x00904800,
+ 0x41200000,
+ 0x80000002,
+ 0x00000904,
+ 0x00002000,
+ 0x00001209,
+ 0x00482400,
+ 0x20900000,
+ 0x40000001,
+ 0x00000482,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x00009048,
+ 0x02412000,
+ 0x048000C0,
+ 0x00000009,
+ 0x00002412,
+ 0x00008000,
+ 0x00004824,
+ 0x01209000,
+ 0x82400000,
+ 0x00000004,
+ 0x00001209,
+ 0x00004000,
+ 0x00002412,
+ 0x00904800,
+ 0x41200000,
+ 0x80000002,
+ 0x00000904,
+ 0x00002000,
+ 0x06001209,
+ 0x00482400,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x80001000,
+ 0x00000904,
+ 0x00241200,
+ 0x90480000,
+ 0x20003000,
+ 0x00000241,
+ 0x00000800,
+ 0x00000000,
+ 0x00000000,
+ 0x48240000,
+ 0x90000000,
+ 0x00000120,
+ 0x00000400,
+ 0x00000000,
+ 0x00090480,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x90000200,
+ 0x00600120,
+ 0x00000000,
+ 0x12090000,
+ 0x24000600,
+ 0x00000048,
+ 0x48000100,
+ 0x00300090,
+ 0xC0024120,
+ 0x09048000,
+ 0x12000300,
+ 0x000C0024,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x30009048,
+ 0x00000000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x0C002412,
+ 0x00008000,
+ 0x18004824,
+ 0x00000000,
+ 0x82400000,
+ 0x00018004,
+ 0x06001209,
+ 0x00004000,
+ 0x20002412,
+ 0x00904800,
+ 0x00000030,
+ 0x80000000,
+ 0x03000904,
+ 0x00002000,
+ 0x10001209,
+ 0x00482400,
+ 0x20900000,
+ 0x40010001,
+ 0x00000482,
+ 0x80001000,
+ 0x00000904,
+ 0x00000000,
+ 0x90480000,
+ 0x20008000,
+ 0x00C00241,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x0CC20D80,
+ 0x0C3000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680A28,
+ 0x45034030,
+ 0x12481A01,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A01450,
+ 0x280D0000,
+ 0x30C0680A,
+ 0x02490340,
+ 0xD000001A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000FF0,
+ 0x4810C000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x24086001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680A28,
+ 0x49034030,
+ 0x12481A02,
+ 0x80A280D0,
+ 0x34030C06,
+ 0x01A00040,
+ 0x280D0002,
+ 0x30C0680A,
+ 0x02490340,
+ 0xD00A281A,
+ 0x0680A280,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xF228A3D5,
+ 0xF6D1451E,
+ 0x0342E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x05140680,
+ 0xD949247A,
+ 0x1EF228A3,
+ 0x88F6D145,
+ 0x000352E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x86120800,
+ 0x00600240,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xF3CF23D5,
+ 0xF4D1451E,
+ 0x034A9248,
+ 0x821A038E,
+ 0x0000D000,
+ 0x00000680,
+ 0xD949247A,
+ 0x1EF3CF23,
+ 0x88F4D145,
+ 0x000352E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x18864000,
+ 0x49247A06,
+ 0xF228A3D9,
+ 0xF4D1451E,
+ 0x034A9248,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD949247A,
+ 0x1EF228A3,
+ 0x88F4D145,
+ 0x000352E3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x08864000,
+ 0x49247A02,
+ 0xF3CF23D9,
+ 0xF4D1451E,
+ 0x0342E388,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD949247A,
+ 0x1EF3CF23,
+ 0x88F4DE79,
+ 0x000342A2,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x40002000,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00020000,
+ 0x08000000,
+ 0x00000000,
+ 0x00000020,
+ 0x00008000,
+ 0x20001000,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00010000,
+ 0x04000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00004000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00041419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x20000000,
+ 0x00000000,
+ 0xE0000080,
+ 0x0000001F,
+ 0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 1, /* GENERALIO3 */
+ 1, /* GENERALIO4 */
+ 0, /* GENERALIO5 */
+ 0, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 3, /* GENERALIO9 */
+ 3, /* GENERALIO10 */
+ 3, /* GENERALIO11 */
+ 3, /* GENERALIO12 */
+ 2, /* GENERALIO13 */
+ 2, /* GENERALIO14 */
+ 1, /* GENERALIO15 */
+ 1, /* GENERALIO16 */
+ 1, /* GENERALIO17 */
+ 1, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define RW_MGR_GUARANTEED_READ 0x4C
+#define RW_MGR_GUARANTEED_READ_CONT 0x54
+#define RW_MGR_GUARANTEED_WRITE 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x7B
+#define RW_MGR_IDLE_LOOP2 0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0 0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_MRS1 0x03
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_MRS3 0x05
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_READ_B2B 0x59
+#define RW_MGR_READ_B2B_WAIT1 0x61
+#define RW_MGR_READ_B2B_WAIT2 0x6B
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_SGLE_READ 0x7D
+#define RW_MGR_ZQCL 0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 7
+#define CALIB_VFIFO_OFFSET 5
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 375
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 82
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL 82
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+ 0x20700000,
+ 0x20780000,
+ 0x10080221,
+ 0x10080320,
+ 0x10090044,
+ 0x100a0008,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080241,
+ 0x100802c0,
+ 0x100a0024,
+ 0x10090010,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
+
+#include <micrel.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/*
+ * PHY configuration
+ */
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret;
+ /*
+ * These skew settings for the KSZ9021 ethernet phy is required for ethernet
+ * to work reliably on most flavors of cyclone5 boards.
+ */
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+ if (ret)
+ return ret;
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+struct s3c_plat_otg_data socfpga_otg_data = {
+ .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
+ .usb_gusbcfg = 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return s3c_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ return 1;
+}
+#endif
--- /dev/null
+if TARGET_EVB_RK3036
+
+config SYS_BOARD
+ default "evb_rk3036"
+
+config SYS_VENDOR
+ default "evb_rk3036"
+
+config SYS_CONFIG_NAME
+ default "evb_rk3036"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
--- /dev/null
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evb_rk3036.o
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/uart.h>
+#include <asm/arch/sdram_rk3036.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void get_ddr_config(struct rk3036_ddr_config *config)
+{
+ /* K4B4G1646Q config */
+ config->ddr_type = 3;
+ config->rank = 2;
+ config->cs0_row = 15;
+ config->cs1_row = 15;
+
+ /* 8bank */
+ config->bank = 3;
+ config->col = 10;
+
+ /* 16bit bw */
+ config->bw = 1;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = sdram_size();
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
#include <common.h>
#include <command.h>
#include <i2c.h>
+#include <asm/io.h>
+#ifdef CONFIG_LS1043A
+#include <asm/arch/immap_lsch2.h>
+#else
#include <asm/immap_85xx.h>
+#endif
#include "vid.h"
DECLARE_GLOBAL_DATA_PTR;
* SoC before converting into an IR VID value
*/
vdd += board_vdd_drop_compensation();
+#ifdef CONFIG_LS1043A
+ vid = DIV_ROUND_UP(vdd - 265, 5);
+#else
vid = DIV_ROUND_UP(vdd - 245, 5);
+#endif
ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
1, (void *)&vid, sizeof(vid));
int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
+#ifdef CONFIG_LS1043A
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#else
ccsr_gur_t __iomem *gur =
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
u32 fusesr;
u8 vid;
int vdd_target, vdd_current, vdd_last;
* | T | | | | |
* ------------------------------------------------------
*/
+#ifdef CONFIG_LS1043A
+ vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
+ }
+#else
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_VID_MASK;
}
+#endif
vdd_target = vdd[vid];
/* check override variable for overriding VDD */
--- /dev/null
+if TARGET_LS1043AQDS
+
+config SYS_BOARD
+ default "ls1043aqds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls1043aqds"
+
+endif
--- /dev/null
+LS1043AQDS BOARD
+M: Mingkai Hu <Mingkai.Hu@freescale.com>
+S: Maintained
+F: board/freescale/ls1043aqds/
+F: include/configs/ls1043aqds.h
+F: configs/ls1043aqds_defconfig
+F: configs/ls1043aqds_nor_ddr3_defconfig
+F: configs/ls1043aqds_nand_defconfig
+F: configs/ls1043aqds_sdcard_ifc_defconfig
--- /dev/null
+#
+# Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ddr.o
+obj-y += eth.o
+obj-y += ls1043aqds.o
--- /dev/null
+Overview
+--------
+The LS1043A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1043A
+LayerScape Architecture processor. The LS1043AQDS provides SW development
+platform for the Freescale LS1043A processor series, with a complete
+debugging environment.
+
+LS1043A SoC Overview
+--------------------
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+ support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+ the following functions:
+ - Packet parsing, classification, and distribution (FMan)
+ - Queue management for scheduling, packet sequencing, and congestion
+ management (QMan)
+ - Hardware buffer management for buffer allocation and de-allocation (BMan)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+ - Up to 1 x XFI supporting 10G interface
+ - Up to 1 x QSGMII
+ - Up to 4 x SGMII supporting 1000Mbps
+ - Up to 2 x SGMII supporting 2500Mbps
+ - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+ - Three PCIe 2.0 controllers, one supporting x4 operation
+ - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+ - Three high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Serial peripheral interface (SPI) controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+ LS1043AQDS board Overview
+ -----------------------
+ - SERDES Connections, 4 lanes supporting:
+ - PCI Express - 3.0
+ - SGMII, SGMII 2.5
+ - QSGMII
+ - SATA 3.0
+ - XFI
+ - DDR Controller
+ - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
+ -IFC/Local Bus
+ - One in-socket 128 MB NOR flash 16-bit data bus
+ - One 512 MB NAND flash with ECC support
+ - PromJet Port
+ - FPGA connection
+ - USB 3.0
+ - Three high speed USB 3.0 ports
+ - First USB 3.0 port configured as Host with Type-A connector
+ - The other two USB 3.0 ports configured as OTG with micro-AB connector
+ - SDHC port connects directly to an adapter card slot, featuring:
+ - Optional clock feedback paths, and optional high-speed voltage translation assistance
+ - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC
+ - eMMC memory devices
+ - DSPI: Onboard support for three SPI flash memory devices
+ - 4 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - Two 4-pin serial ports at up to 115.2 Kbit/s
+ - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address End Address Description Size
+0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
+0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
+0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
+0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
+0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
+0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
+0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
+0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
+
+Booting Options
+---------------
+a) Promjet Boot
+b) NOR boot
+c) NAND boot
+d) SD boot
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 3) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->cpo_override = pbsp->cpo_override;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for %lu MT/s\n",
+ ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+ /* force DDR bus width to 32 bits */
+ popts->data_bus_width = 1;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ popts->bstopre = 0; /* enable auto precharge */
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
+ popts->cswl_override = DDR_CSWL_CS0;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ return fsl_ddr_sdram_size();
+#else
+ puts("Initializing DDR....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+#endif
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+ fsl_dp_ddr_restore();
+#endif
+
+ return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo_override;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+#ifdef CONFIG_SYS_FSL_DDR4
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,},
+ {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
+ {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+ {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+ {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+#else
+#error DDR type not defined
+#endif
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+#endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <fsl_dtsec.h>
+#include <malloc.h>
+#include <asm/arch/fsl_serdes.h>
+
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "ls1043aqds_qixis.h"
+
+#define EMI_NONE 0xFF
+#define EMI1_RGMII1 0
+#define EMI1_RGMII2 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 3
+#define EMI1_SLOT3 4
+#define EMI1_SLOT4 5
+#define EMI2 6
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+ "LS1043AQDS_MDIO_RGMII1",
+ "LS1043AQDS_MDIO_RGMII2",
+ "LS1043AQDS_MDIO_SLOT1",
+ "LS1043AQDS_MDIO_SLOT2",
+ "LS1043AQDS_MDIO_SLOT3",
+ "LS1043AQDS_MDIO_SLOT4",
+ "NULL",
+};
+
+/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
+static u8 lane_to_slot[] = {1, 2, 3, 4};
+
+static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name;
+
+ if (muxval > EMI2)
+ return NULL;
+
+ name = ls1043aqds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+struct ls1043aqds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void ls1043aqds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+
+ if (muxval < 7) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct ls1043aqds_mdio *priv = bus->priv;
+
+ ls1043aqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct ls1043aqds_mdio *priv = bus->priv;
+
+ ls1043aqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad,
+ regnum, value);
+}
+
+static int ls1043aqds_mdio_reset(struct mii_dev *bus)
+{
+ struct ls1043aqds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct ls1043aqds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate ls1043aqds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate ls1043aqds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = ls1043aqds_mdio_read;
+ bus->write = ls1043aqds_mdio_write;
+ bus->reset = ls1043aqds_mdio_reset;
+ sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ struct fixed_link f_link;
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ if (port == FM1_DTSEC9) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_riser_s1_p1");
+ } else if (port == FM1_DTSEC2) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_riser_s2_p1");
+ } else if (port == FM1_DTSEC5) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_riser_s3_p1");
+ } else if (port == FM1_DTSEC6) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_riser_s4_p1");
+ }
+ } else if (fm_info_get_enet_if(port) ==
+ PHY_INTERFACE_MODE_SGMII_2500) {
+ /* 2.5G SGMII interface */
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 1000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for 2.5G SGMII */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+ fdt_setprop_string(fdt, offset, "phy-connection-type",
+ "sgmii-2500");
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
+ switch (mdio_mux[port]) {
+ case EMI1_SLOT1:
+ switch (port) {
+ case FM1_DTSEC1:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s1_p1");
+ break;
+ case FM1_DTSEC2:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s1_p2");
+ break;
+ case FM1_DTSEC5:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s1_p3");
+ break;
+ case FM1_DTSEC6:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s1_p4");
+ break;
+ default:
+ break;
+ }
+ break;
+ case EMI1_SLOT2:
+ switch (port) {
+ case FM1_DTSEC1:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s2_p1");
+ break;
+ case FM1_DTSEC2:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s2_p2");
+ break;
+ case FM1_DTSEC5:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s2_p3");
+ break;
+ case FM1_DTSEC6:
+ fdt_set_phy_handle(fdt, compat, addr,
+ "qsgmii_s2_p4");
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ fdt_delprop(fdt, offset, "phy-connection-type");
+ fdt_setprop_string(fdt, offset, "phy-connection-type",
+ "qsgmii");
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
+ port == FM1_10GEC1) {
+ /* XFI interface */
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for XFI */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+ fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int i;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
+ switch (mdio_mux[i]) {
+ case EMI1_SLOT1:
+ fdt_status_okay_by_alias(fdt, "emi1_slot1");
+ break;
+ case EMI1_SLOT2:
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ break;
+ case EMI1_SLOT3:
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ break;
+ case EMI1_SLOT4:
+ fdt_status_okay_by_alias(fdt, "emi1_slot4");
+ break;
+ default:
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_XGMII:
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ int i, idx, lane, slot, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+ ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+ ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+ switch (srds_s1) {
+ case 0x2555:
+ /* 2.5G SGMII on lane A, MAC 9 */
+ fm_info_set_phy_address(FM1_DTSEC9, 9);
+ break;
+ case 0x4555:
+ case 0x4558:
+ /* QSGMII on lane A, MAC 1/2/5/6 */
+ fm_info_set_phy_address(FM1_DTSEC1,
+ QSGMII_CARD_PORT1_PHY_ADDR_S1);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ QSGMII_CARD_PORT2_PHY_ADDR_S1);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ QSGMII_CARD_PORT3_PHY_ADDR_S1);
+ fm_info_set_phy_address(FM1_DTSEC6,
+ QSGMII_CARD_PORT4_PHY_ADDR_S1);
+ break;
+ case 0x1355:
+ /* SGMII on lane B, MAC 2*/
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x2355:
+ /* 2.5G SGMII on lane A, MAC 9 */
+ fm_info_set_phy_address(FM1_DTSEC9, 9);
+ /* SGMII on lane B, MAC 2*/
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x3335:
+ /* SGMII on lane C, MAC 5 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+ case 0x3355:
+ case 0x3358:
+ /* SGMII on lane B, MAC 2 */
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ case 0x3555:
+ case 0x3558:
+ /* SGMII on lane A, MAC 9 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x1455:
+ /* QSGMII on lane B, MAC 1/2/5/6 */
+ fm_info_set_phy_address(FM1_DTSEC1,
+ QSGMII_CARD_PORT1_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ QSGMII_CARD_PORT2_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ QSGMII_CARD_PORT3_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC6,
+ QSGMII_CARD_PORT4_PHY_ADDR_S2);
+ break;
+ case 0x2455:
+ /* 2.5G SGMII on lane A, MAC 9 */
+ fm_info_set_phy_address(FM1_DTSEC9, 9);
+ /* QSGMII on lane B, MAC 1/2/5/6 */
+ fm_info_set_phy_address(FM1_DTSEC1,
+ QSGMII_CARD_PORT1_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ QSGMII_CARD_PORT2_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ QSGMII_CARD_PORT3_PHY_ADDR_S2);
+ fm_info_set_phy_address(FM1_DTSEC6,
+ QSGMII_CARD_PORT4_PHY_ADDR_S2);
+ break;
+ case 0x2255:
+ /* 2.5G SGMII on lane A, MAC 9 */
+ fm_info_set_phy_address(FM1_DTSEC9, 9);
+ /* 2.5G SGMII on lane B, MAC 2 */
+ fm_info_set_phy_address(FM1_DTSEC2, 2);
+ break;
+ case 0x3333:
+ /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
+ fm_info_set_phy_address(FM1_DTSEC9,
+ SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6,
+ SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ default:
+ printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
+ srds_s1);
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_QSGMII:
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_2500_FM1_DTSEC1 + idx);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ QSGMII_FM1_A);
+ }
+
+ if (lane < 0)
+ break;
+
+ slot = lane_to_slot[lane];
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 4:
+ mdio_mux[i] = EMI1_SLOT4;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC3)
+ mdio_mux[i] = EMI1_RGMII1;
+ else if (i == FM1_DTSEC4)
+ mdio_mux[i] = EMI1_RGMII2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <spl.h>
+
+#include "../common/qixis.h"
+#include "ls1043aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ MUX_TYPE_GPIO,
+};
+
+/* LS1043AQDS serdes mux */
+#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
+#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
+#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
+#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
+#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
+#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
+#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
+#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
+
+int checkboard(void)
+{
+ char buf[64];
+#ifndef CONFIG_SD_BOOT
+ u8 sw;
+#endif
+
+ puts("Board: LS1043AQDS, boot from ");
+
+#ifdef CONFIG_SD_BOOT
+ puts("SD\n");
+#else
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("PromJet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else if (sw == 0x15)
+ printf("IFCCard\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
+ QIXIS_READ(id), QIXIS_READ(arch));
+
+ printf("FPGA: v%d (%s), build %d\n",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+
+ return 0;
+}
+
+bool if_board_diff_clk(void)
+{
+ u8 diff_conf = QIXIS_READ(brdcfg[11]);
+
+ return diff_conf & 0x40;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0f) {
+ case QIXIS_SYSCLK_64:
+ return 64000000;
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ if (if_board_diff_clk())
+ return get_board_sys_clk();
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+
+ return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /*
+ * When resuming from deep sleep, the I2C channel may not be
+ * in the default channel. So, switch to the default channel
+ * before accessing DDR SPD.
+ */
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ gd->ram_size = initdram(0);
+
+ return 0;
+}
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return select_i2c_ch_pca9547(channel);
+}
+
+void board_retimer_init(void)
+{
+ u8 reg;
+
+ /* Retimer is connected to I2C1_CH7_CH5 */
+ reg = I2C_MUX_CH7;
+ i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
+ reg = I2C_MUX_CH5;
+ i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
+
+ /* Access to Control/Shared register */
+ reg = 0x0;
+ i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+
+ /* Read device revision and ID */
+ i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
+ debug("Retimer version id = 0x%x\n", reg);
+
+ /* Enable Broadcast. All writes target all channel register sets */
+ reg = 0x0c;
+ i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+
+ /* Reset Channel Registers */
+ i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+ reg |= 0x4;
+ i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+
+ /* Enable override divider select and Enable Override Output Mux */
+ i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
+ reg |= 0x24;
+ i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
+
+ /* Select VCO Divider to full rate (000) */
+ i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
+ reg &= 0x8f;
+ i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
+
+ /* Selects active PFD MUX Input as Re-timed Data (001) */
+ i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
+ reg &= 0x3f;
+ reg |= 0x20;
+ i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
+
+ /* Set data rate as 10.3125 Gbps */
+ reg = 0x0;
+ i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
+ reg = 0xb2;
+ i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
+ reg = 0x90;
+ i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
+ reg = 0xb3;
+ i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
+ reg = 0xcd;
+ i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch2_early_init_f();
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+/* determine if it is a warm boot */
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+ return 1;
+
+ return 0;
+}
+#endif
+
+int config_board_mux(int ctrl_type)
+{
+ u8 reg14;
+
+ reg14 = QIXIS_READ(brdcfg[14]);
+
+ switch (ctrl_type) {
+ case MUX_TYPE_GPIO:
+ reg14 = (reg14 & (~0x30)) | 0x20;
+ break;
+ default:
+ puts("Unsupported mux interface type\n");
+ return -1;
+ }
+
+ QIXIS_WRITE(brdcfg[14], reg14);
+
+ return 0;
+}
+
+int config_serdes_mux(void)
+{
+ return 0;
+}
+
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ if (hwconfig("gpio"))
+ config_board_mux(MUX_TYPE_GPIO);
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+ CONFIG_SYS_CCI400_ADDR;
+
+ /* Set CCI-400 control override register to enable barrier
+ * transaction */
+ out_le32(&cci->ctrl_ord,
+ CCI400_CTRLORD_EN_BARRIER);
+
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ board_retimer_init();
+
+#ifdef CONFIG_SYS_FSL_SERDES
+ config_serdes_mux();
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+ return 0;
+}
+#endif
+
+u8 flash_read8(void *addr)
+{
+ return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+ u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+ __raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+ u16 val = __raw_readw(addr);
+
+ return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
--- /dev/null
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#flush PBI data
+096100c0 000fffff
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xe0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+#define QIXIS_SYSCLK_64 0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100 0x0
+#define QIXIS_SDCLK1_125 0x1
+#define QIXIS_SDCLK1_165 0x2
+#define QIXIS_SDCLK1_100_SP 0x3
+
+#endif
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0810000f 0c000000 00000000 00000000
+14550002 80004012 e0106000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
--- /dev/null
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable IFC; disable QSPI
+0810000f 0c000000 00000000 00000000
+14550002 80004012 60040000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
int board_early_init_f(void)
{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ u32 usb_pwrfault;
+
fsl_lsch2_early_init_f();
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+ out_be32(&scfg->rcwpmuxcr0, 0x3333);
+ out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+ usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (SCFG_USBPWRFAULT_DEDICATED <<
+ SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (SCFG_USBPWRFAULT_SHARED <<
+ SCFG_USBPWRFAULT_USB1_SHIFT);
+ out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+
return 0;
}
--- /dev/null
+if TARGET_LS2080A_EMU
+
+config SYS_BOARD
+ default "ls2080a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls2080a_emu"
+
+endif
+
+if TARGET_LS2080A_SIMU
+
+config SYS_BOARD
+ default "ls2080a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls2080a_simu"
+
+endif
--- /dev/null
+LS2080A BOARD
+M: York Sun <yorksun@freescale.com>
+S: Maintained
+F: board/freescale/ls2080a/
+F: include/configs/ls2080a_emu.h
+F: configs/ls2080a_emu_defconfig
+F: include/configs/ls2080a_simu.h
+F: configs/ls2080a_simu_defconfig
+F: configs/ls2085a_emu_defconfig
+F: configs/ls2085a_simu_defconfig
--- /dev/null
+#
+# Copyright 2014-15 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls2080a.o
+obj-y += ddr.o
--- /dev/null
+Freescale ls2080a_emu
+
+This is a emulator target with limited peripherals.
+
+Memory map from core's view
+
+0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
+0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
+
+Other addresses are either reserved, or not used directly by u-boot.
+This list should be updated when more addresses are used.
+
+Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
+-------------------------------------------------------------------
+One needs to use appropriate bootargs to boot Linux flavors which do
+not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
+below:
+
+=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
+ earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
+ hugepages=16 mem=2048M'
+
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 3) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[ctrl_num];
+ else
+ pbsp = udimms[ctrl_num];
+
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for data rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+ if (ctrl_num == CONFIG_DP_DDR_CTRL) {
+ /* force DDR bus width to 32 bits */
+ popts->data_bus_width = 1;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ popts->bstopre = 0; /* enable auto precharge */
+ }
+#endif
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 2,
+ .rank_density = 1073741824u,
+ .capacity = 2147483648,
+ .primary_sdram_width = 64,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 937,
+ .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
+ .taa_ps = 13090,
+ .twr_ps = 15000,
+ .trcd_ps = 13090,
+ .trrd_ps = 5000,
+ .trp_ps = 13090,
+ .tras_ps = 33000,
+ .trc_ps = 46090,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 25000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if (((controller_number == 0) && (dimm_number == 0)) ||
+ ((controller_number == 1) && (dimm_number == 0))) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+#endif
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing DDR....");
+
+ puts("using SPD\n");
+ dram_size = fsl_ddr_sdram();
+
+ return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+ phys_size_t dp_ddr_size;
+#endif
+
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ } else {
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ }
+
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+ /* initialize DP-DDR here */
+ puts("DP-DDR: ");
+ /*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+ dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+ CONFIG_DP_DDR_CTRL,
+ CONFIG_DP_DDR_NUM_CTRLS,
+ CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
+ NULL, NULL, NULL);
+ if (dp_ddr_size) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->bd->bi_dram[2].size = dp_ddr_size;
+ } else {
+ puts("Not detected");
+ }
+#endif
+}
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 2140, 0, 4, 4, 0x0, 0x0},
+ {1, 2140, 0, 4, 4, 0x0, 0x0},
+ {}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters udimm2[] = {
+ /*
+ * memory controller 2
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 2140, 0, 4, 4, 0x0, 0x0},
+ {1, 2140, 0, 4, 4, 0x0, 0x0},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {4, 2140, 0, 5, 4, 0x0, 0x0},
+ {2, 2140, 0, 5, 4, 0x0, 0x0},
+ {1, 2140, 0, 4, 4, 0x0, 0x0},
+ {}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters rdimm2[] = {
+ /*
+ * memory controller 2
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {4, 2140, 0, 5, 4, 0x0, 0x0},
+ {2, 2140, 0, 5, 4, 0x0, 0x0},
+ {1, 2140, 0, 4, 4, 0x0, 0x0},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+ udimm0,
+ udimm2,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+ rdimm0,
+ rdimm2,
+};
+
+
+#endif
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <fsl_debug_server.h>
+#include <fsl-mc/fsl_mc.h>
+#include <environment.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ init_final_memctl_regs();
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+ print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+ if (gd->bd->bi_dram[2].size) {
+ puts("\nDP-DDR ");
+ print_size(gd->bd->bi_dram[2].size, "");
+ print_ddr_info(CONFIG_DP_DDR_CTRL);
+ }
+#endif
+}
+
+int dram_init(void)
+{
+ gd->ram_size = initdram(0);
+
+ return 0;
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+#ifdef CONFIG_FSL_DEBUG_SERVER
+ debug_server_init();
+#endif
+
+ return 0;
+}
+#endif
+
+unsigned long get_dram_size_to_hide(void)
+{
+ unsigned long dram_to_hide = 0;
+
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+ dram_to_hide += debug_server_get_dram_block_size();
+#endif
+
+/* Carve the MC private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_MC_ENET
+ dram_to_hide += mc_get_dram_block_size();
+#endif
+
+ return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int error = 0;
+
+#ifdef CONFIG_SMC91111
+ error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+ error = cpu_eth_init(bis);
+#endif
+ return error;
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/fsl-mc");
+
+ /*
+ * TODO: Remove this when backward compatibility
+ * with old DT node (fsl,dprc@0) is no longer needed.
+ */
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+
+ if (offset < 0) {
+ printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+ __func__, offset);
+ return;
+ }
+
+ if (get_mc_boot_status() == 0)
+ fdt_status_okay(fdt, offset);
+ else
+ fdt_status_fail(fdt, offset);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ ft_cpu_setup(blob, bd);
+
+ /* fixup DT for the two GPP DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
+
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fixup_board_enet(blob);
+ fsl_mc_ldpaa_exit(bd);
+#endif
+
+ return 0;
+}
+#endif
--- /dev/null
+
+if TARGET_LS2080AQDS
+
+config SYS_BOARD
+ default "ls2080aqds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls2080aqds"
+
+endif
--- /dev/null
+LS2080A BOARD
+M: Prabhakar Kushwaha <prabhakar@freescale.com>
+S: Maintained
+F: board/freescale/ls2080aqds/
+F: board/freescale/ls2080a/ls2080aqds.c
+F: include/configs/ls2080aqds.h
+F: configs/ls2080aqds_defconfig
+F: configs/ls2080aqds_nand_defconfig
+F: configs/ls2085aqds_defconfig
+F: configs/ls2085aqds_nand_defconfig
--- /dev/null
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls2080aqds.o
+obj-y += ddr.o
+obj-y += eth.o
--- /dev/null
+Overview
+--------
+The LS2080A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
+Layerscape Architecture processor. The LS2080AQDS provides validation and
+SW development platform for the Freescale LS2080A processor series, with
+a complete debugging environment.
+
+LS2080A SoC Overview
+------------------
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2080A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+ the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+ - Packet parsing, classification, and distribution (WRIOP)
+ - Queue and Hardware buffer management for scheduling, packet sequencing, and
+ congestion management, buffer allocation and de-allocation (QBMan)
+ - Cryptography acceleration (SEC) at up to 10 Gbps
+ - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+ - Decompression/compression acceleration (DCE) at up to 20 Gbps
+ - Accelerated I/O processing (AIOP) at up to 20 Gbps
+ - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+ - Up to eight 10 Gbps Ethernet MACs
+ - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 3.0) controllers
+ - Two high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Serial peripheral interface (SPI) controller
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+ capabilities
+
+ LS2080AQDS board Overview
+ -----------------------
+ - SERDES Connections, 16 lanes supporting:
+ - PCI Express - 3.0
+ - SGMII, SGMII 2.5
+ - QSGMII
+ - SATA 3.0
+ - XAUI
+ - XFI
+ - DDR Controller
+ - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
+ chip-selects and two DIMM connectors. Support is up to 2133MT/s.
+ - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
+ and two DIMM connectors. Support is up to 1600MT/s.
+ -IFC/Local Bus
+ - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
+ - One in-socket 128 MB NOR flash 16-bit data bus
+ - One 512 MB NAND flash with ECC support
+ - IFC Test Port
+ - PromJet Port
+ - FPGA connection
+ - USB 3.0
+ - Two high speed USB 3.0 ports
+ - First USB 3.0 port configured as Host with Type-A connector
+ - Second USB 3.0 port configured as OTG with micro-AB connector
+ - SDHC: PCIe x1 Right Angle connector for supporting following cards
+ - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only
+ - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only
+ - 4-bit eMMC Card Rev 4.4 (1.8V only)
+ - 8-bit eMMC Card Rev 4.5 (1.8V only)
+ - SD Card Rev 2.0 and Rev 3.0
+ - DSPI: 3 high-speed flash Memory for storage
+ - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+ - 8 MB high-speed flash Memory (up to 104 MHz)
+ - 512 MB low-speed flash Memory (up to 40 MHz)
+ - QSPI: via NAND/QSPI Card
+ - 4 I2C controllers
+ - Two SATA onboard connectors
+ - UART
+ - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
+ - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
+0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
+
+Other addresses are either reserved, or not used directly by u-boot.
+This list should be updated when more addresses are used.
+
+IFC region map from core's view
+-------------------------------
+During boot i.e. IFC Region #1:-
+ 0x30000000 - 0x37ffffff : 128MB : NOR flash
+ 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
+ 0x3C000000 - 0x40000000 : 64MB : FPGA etc
+
+After relocate to DDR i.e. IFC Region #2:-
+ 0x5_1000_0000..0x5_1fff_ffff Memory Hole
+ 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
+ 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
+ 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
+ 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
+
+Booting Options
+---------------
+a) Promjet Boot
+b) NOR boot
+c) NAND boot
+d) SD boot
+e) QSPI boot
+
+Environment Variables
+---------------------
+- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
+ the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+
+- mcmemsize: MC DRAM block size. If this variable is not defined
+ the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+
+Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
+-------------------------------------------------------------------
+One needs to use appropriate bootargs to boot Linux flavors which do
+not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
+below:
+
+=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
+ earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
+ hugepages=16 mem=2048M'
+
+
+X-QSGMII-16PORT riser card
+----------------------------
+The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
+interfaces implemented in PCIe form factor board.
+It supports followings
+ - Card can operate with up to 4 QSGMII lane simultaneously
+ - Card can operate with up to 8 SGMII lane simultaneously
+
+Supported card configuration
+ - CSEL : ON ON ON ON
+ - MSEL1 : ON ON ON ON OFF OFF OFF OFF
+ - MSEL2 : OFF OFF OFF OFF ON ON ON ON
+
+To enable this card: modify hwconfig to add "xqsgmii" variable.
+
+Supported PHY addresses during SGMII:
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+
+Mapping DPMACx to PHY during SGMII
+DPMAC1 -> PHY1-P0
+DPMAC2 -> PHY2-P0
+DPMAC3 -> PHY3-P0
+DPMAC4 -> PHY4-P0
+DPMAC5 -> PHY3-P2
+DPMAC6 -> PHY1-P2
+DPMAC7 -> PHY4-P1
+DPMAC8 -> PHY2-P2
+DPMAC9 -> PHY1-P0
+DPMAC10 -> PHY2-P0
+DPMAC11 -> PHY3-P0
+DPMAC12 -> PHY4-P0
+DPMAC13 -> PHY3-P2
+DPMAC14 -> PHY1-P2
+DPMAC15 -> PHY4-P1
+DPMAC16 -> PHY2-P2
+
+
+Supported PHY address during QSGMII
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
+
+Mapping DPMACx to PHY during QSGMII
+DPMAC1 -> PHY1-P3
+DPMAC2 -> PHY1-P2
+DPMAC3 -> PHY1-P1
+DPMAC4 -> PHY1-P0
+DPMAC5 -> PHY2-P3
+DPMAC6 -> PHY2-P2
+DPMAC7 -> PHY2-P1
+DPMAC8 -> PHY2-P0
+DPMAC9 -> PHY3-P0
+DPMAC10 -> PHY3-P1
+DPMAC11 -> PHY3-P2
+DPMAC12 -> PHY3-P3
+DPMAC13 -> PHY4-P0
+DPMAC14 -> PHY4-P1
+DPMAC15 -> PHY4-P2
+DPMAC16 -> PHY4-P3
+
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+ u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+ int slot;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+
+ for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
+ if (pdimm[slot].n_ranks)
+ break;
+ }
+
+ if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[ctrl_num];
+ else
+ pbsp = udimms[ctrl_num];
+
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm[slot].n_ranks &&
+ (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for data rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+ if (ctrl_num == CONFIG_DP_DDR_CTRL) {
+ /* force DDR bus width to 32 bits */
+ popts->data_bus_width = 1;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ popts->bstopre = 0; /* enable auto precharge */
+ /*
+ * Layout optimization results byte mapping
+ * Byte 0 -> Byte ECC
+ * Byte 1 -> Byte 3
+ * Byte 2 -> Byte 2
+ * Byte 3 -> Byte 1
+ * Byte ECC -> Byte 0
+ */
+ dq_mapping_0 = pdimm[slot].dq_mapping[0];
+ dq_mapping_2 = pdimm[slot].dq_mapping[2];
+ dq_mapping_3 = pdimm[slot].dq_mapping[3];
+ pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
+ pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
+ pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
+ pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
+ pdimm[slot].dq_mapping[6] = dq_mapping_2;
+ pdimm[slot].dq_mapping[7] = dq_mapping_3;
+ pdimm[slot].dq_mapping[8] = dq_mapping_0;
+ pdimm[slot].dq_mapping[9] = 0;
+ pdimm[slot].dq_mapping[10] = 0;
+ pdimm[slot].dq_mapping[11] = 0;
+ pdimm[slot].dq_mapping[12] = 0;
+ pdimm[slot].dq_mapping[13] = 0;
+ pdimm[slot].dq_mapping[14] = 0;
+ pdimm[slot].dq_mapping[15] = 0;
+ pdimm[slot].dq_mapping[16] = 0;
+ pdimm[slot].dq_mapping[17] = 0;
+ }
+#endif
+ /* To work at higher than 1333MT/s */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0x0; /* 32 clocks */
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ if (ddr_freq < 2350) {
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+ DDR_CDR2_VREF_RANGE_2;
+ } else {
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
+ DDR_CDR2_VREF_RANGE_2;
+ }
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ return fsl_ddr_sdram_size();
+#else
+ puts("Initializing DDR....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+#endif
+
+ return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+ phys_size_t dp_ddr_size;
+#endif
+
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ } else {
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ }
+
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+ /* initialize DP-DDR here */
+ puts("DP-DDR: ");
+ /*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+ dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+ CONFIG_DP_DDR_CTRL,
+ CONFIG_DP_DDR_NUM_CTRLS,
+ CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
+ NULL, NULL, NULL);
+ if (dp_ddr_size) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->bd->bi_dram[2].size = dp_ddr_size;
+ } else {
+ puts("Not detected");
+ }
+#endif
+}
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2300, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters udimm2[] = {
+ /*
+ * memory controller 2
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters rdimm2[] = {
+ /*
+ * memory controller 2
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
+ {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+ udimm0,
+ udimm2,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+ rdimm0,
+ rdimm2,
+};
+
+
+#endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <hwconfig.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+#include "../common/qixis.h"
+
+#include "ls2080aqds_qixis.h"
+
+
+#ifdef CONFIG_FSL_MC_ENET
+ /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
+ * Bank 1 -> Lanes A, B, C, D, E, F, G, H
+ * Bank 2 -> Lanes A,B, C, D, E, F, G, H
+ */
+
+ /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
+ * means that the mapping must be determined dynamically, or that the lane
+ * maps to something other than a board slot.
+ */
+
+static u8 lane_to_slot_fsm1[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u8 lane_to_slot_fsm2[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
+ * housed.
+ */
+
+static int xqsgii_riser_phy_addr[] = {
+ XQSGMII_CARD_PHY1_PORT0_ADDR,
+ XQSGMII_CARD_PHY2_PORT0_ADDR,
+ XQSGMII_CARD_PHY3_PORT0_ADDR,
+ XQSGMII_CARD_PHY4_PORT0_ADDR,
+ XQSGMII_CARD_PHY3_PORT2_ADDR,
+ XQSGMII_CARD_PHY1_PORT2_ADDR,
+ XQSGMII_CARD_PHY4_PORT2_ADDR,
+ XQSGMII_CARD_PHY2_PORT2_ADDR,
+};
+
+static int sgmii_riser_phy_addr[] = {
+ SGMII_CARD_PORT1_PHY_ADDR,
+ SGMII_CARD_PORT2_PHY_ADDR,
+ SGMII_CARD_PORT3_PHY_ADDR,
+ SGMII_CARD_PORT4_PHY_ADDR,
+};
+
+/* Slot2 does not have EMI connections */
+#define EMI_NONE 0xFFFFFFFF
+#define EMI1_SLOT1 0
+#define EMI1_SLOT2 1
+#define EMI1_SLOT3 2
+#define EMI1_SLOT4 3
+#define EMI1_SLOT5 4
+#define EMI1_SLOT6 5
+#define EMI2 6
+#define SFP_TX 0
+
+static const char * const mdio_names[] = {
+ "LS2080A_QDS_MDIO0",
+ "LS2080A_QDS_MDIO1",
+ "LS2080A_QDS_MDIO2",
+ "LS2080A_QDS_MDIO3",
+ "LS2080A_QDS_MDIO4",
+ "LS2080A_QDS_MDIO5",
+ DEFAULT_WRIOP_MDIO2_NAME,
+};
+
+struct ls2080a_qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void sgmii_configure_repeater(int serdes_port)
+{
+ struct mii_dev *bus;
+ uint8_t a = 0xf;
+ int i, j, ret;
+ int dpmac_id = 0, dpmac, mii_bus = 0;
+ unsigned short value;
+ char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
+ uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
+
+ uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+
+ int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
+
+ /* Set I2c to Slot 1 */
+ i2c_write(0x77, 0, 0, &a, 1);
+
+ for (dpmac = 0; dpmac < 8; dpmac++) {
+ /* Check the PHY status */
+ switch (serdes_port) {
+ case 1:
+ mii_bus = 0;
+ dpmac_id = dpmac + 1;
+ break;
+ case 2:
+ mii_bus = 1;
+ dpmac_id = dpmac + 9;
+ a = 0xb;
+ i2c_write(0x76, 0, 0, &a, 1);
+ break;
+ }
+
+ ret = miiphy_set_current_dev(dev[mii_bus]);
+ if (ret > 0)
+ goto error;
+
+ bus = mdio_get_current_dev();
+ debug("Reading from bus %s\n", bus->name);
+
+ ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
+ 3);
+ if (ret > 0)
+ goto error;
+
+ mdelay(10);
+ ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
+ &value);
+ if (ret > 0)
+ goto error;
+
+ mdelay(10);
+
+ if ((value & 0xfff) == 0x40f) {
+ printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
+ continue;
+ }
+
+ for (i = 0; i < 4; i++) {
+ for (j = 0; j < 4; j++) {
+ a = 0x18;
+ i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
+ a = 0x38;
+ i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
+ a = 0x4;
+ i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
+
+ i2c_write(i2c_addr[dpmac], 0xf, 1,
+ &ch_a_eq[i], 1);
+ i2c_write(i2c_addr[dpmac], 0x11, 1,
+ &ch_a_ctl2[j], 1);
+
+ i2c_write(i2c_addr[dpmac], 0x16, 1,
+ &ch_b_eq[i], 1);
+ i2c_write(i2c_addr[dpmac], 0x18, 1,
+ &ch_b_ctl2[j], 1);
+
+ a = 0x14;
+ i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
+ a = 0xb5;
+ i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
+ a = 0x20;
+ i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
+ mdelay(100);
+ ret = miiphy_read(dev[mii_bus],
+ riser_phy_addr[dpmac],
+ 0x11, &value);
+ if (ret > 0)
+ goto error;
+
+ mdelay(1);
+ ret = miiphy_read(dev[mii_bus],
+ riser_phy_addr[dpmac],
+ 0x11, &value);
+ if (ret > 0)
+ goto error;
+ mdelay(10);
+
+ if ((value & 0xfff) == 0x40f) {
+ printf("DPMAC %d :PHY is configured ",
+ dpmac_id);
+ printf("after setting repeater 0x%x\n",
+ value);
+ i = 5;
+ j = 5;
+ } else
+ printf("DPMAC %d :PHY is failed to ",
+ dpmac_id);
+ printf("configure the repeater 0x%x\n",
+ value);
+ }
+ }
+ }
+error:
+ if (ret)
+ printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
+ return;
+}
+
+static void qsgmii_configure_repeater(int dpmac)
+{
+ uint8_t a = 0xf;
+ int i, j;
+ int i2c_phy_addr = 0;
+ int phy_addr = 0;
+ int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
+
+ uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+ uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
+ uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
+
+ const char *dev = "LS2080A_QDS_MDIO0";
+ int ret = 0;
+ unsigned short value;
+
+ /* Set I2c to Slot 1 */
+ i2c_write(0x77, 0, 0, &a, 1);
+
+ switch (dpmac) {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ i2c_phy_addr = i2c_addr[0];
+ phy_addr = 0;
+ break;
+
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ i2c_phy_addr = i2c_addr[1];
+ phy_addr = 4;
+ break;
+
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ i2c_phy_addr = i2c_addr[2];
+ phy_addr = 8;
+ break;
+
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ i2c_phy_addr = i2c_addr[3];
+ phy_addr = 0xc;
+ break;
+ }
+
+ /* Check the PHY status */
+ ret = miiphy_set_current_dev(dev);
+ ret = miiphy_write(dev, phy_addr, 0x1f, 3);
+ mdelay(10);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ mdelay(10);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ mdelay(10);
+ if ((value & 0xf) == 0xf) {
+ printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
+ return;
+ }
+
+ for (i = 0; i < 4; i++) {
+ for (j = 0; j < 4; j++) {
+ a = 0x18;
+ i2c_write(i2c_phy_addr, 6, 1, &a, 1);
+ a = 0x38;
+ i2c_write(i2c_phy_addr, 4, 1, &a, 1);
+ a = 0x4;
+ i2c_write(i2c_phy_addr, 8, 1, &a, 1);
+
+ i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
+ i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
+
+ i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
+ i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
+
+ a = 0x14;
+ i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
+ a = 0xb5;
+ i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
+ a = 0x20;
+ i2c_write(i2c_phy_addr, 4, 1, &a, 1);
+ mdelay(100);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ if (ret > 0)
+ goto error;
+ mdelay(1);
+ ret = miiphy_read(dev, phy_addr, 0x11, &value);
+ if (ret > 0)
+ goto error;
+ mdelay(10);
+ if ((value & 0xf) == 0xf) {
+ printf("DPMAC %d :PHY is ..... Configured\n",
+ dpmac);
+ return;
+ }
+ }
+ }
+error:
+ printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
+ return;
+}
+
+static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+static void ls2080a_qds_enable_SFP_TX(u8 muxval)
+{
+ u8 brdcfg9;
+
+ brdcfg9 = QIXIS_READ(brdcfg[9]);
+ brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
+ brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
+ QIXIS_WRITE(brdcfg[9], brdcfg9);
+}
+
+static void ls2080a_qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+
+ if (muxval <= 5) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
+ int devad, int regnum)
+{
+ struct ls2080a_qds_mdio *priv = bus->priv;
+
+ ls2080a_qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct ls2080a_qds_mdio *priv = bus->priv;
+
+ ls2080a_qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
+{
+ struct ls2080a_qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct ls2080a_qds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate ls2080a_qds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate ls2080a_qds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = ls2080a_qds_mdio_read;
+ bus->write = ls2080a_qds_mdio_write;
+ bus->reset = ls2080a_qds_mdio_reset;
+ sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+
+ return mdio_register(bus);
+}
+
+/*
+ * Initialize the dpmac_info array.
+ *
+ */
+static void initialize_dpmac_to_slot(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+ >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+ int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
+ >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+ char *env_hwconfig;
+ env_hwconfig = getenv("hwconfig");
+
+ switch (serdes1_prtcl) {
+ case 0x07:
+ case 0x09:
+ case 0x33:
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ lane_to_slot_fsm1[0] = EMI1_SLOT1;
+ lane_to_slot_fsm1[1] = EMI1_SLOT1;
+ lane_to_slot_fsm1[2] = EMI1_SLOT1;
+ lane_to_slot_fsm1[3] = EMI1_SLOT1;
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm1[4] = EMI1_SLOT1;
+ lane_to_slot_fsm1[5] = EMI1_SLOT1;
+ lane_to_slot_fsm1[6] = EMI1_SLOT1;
+ lane_to_slot_fsm1[7] = EMI1_SLOT1;
+ } else {
+ lane_to_slot_fsm1[4] = EMI1_SLOT2;
+ lane_to_slot_fsm1[5] = EMI1_SLOT2;
+ lane_to_slot_fsm1[6] = EMI1_SLOT2;
+ lane_to_slot_fsm1[7] = EMI1_SLOT2;
+ }
+ break;
+
+ case 0x2A:
+ printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ default:
+ printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+ __func__, serdes1_prtcl);
+ break;
+ }
+
+ switch (serdes2_prtcl) {
+ case 0x07:
+ case 0x08:
+ case 0x09:
+ case 0x49:
+ printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+ serdes2_prtcl);
+ lane_to_slot_fsm2[0] = EMI1_SLOT4;
+ lane_to_slot_fsm2[1] = EMI1_SLOT4;
+ lane_to_slot_fsm2[2] = EMI1_SLOT4;
+ lane_to_slot_fsm2[3] = EMI1_SLOT4;
+
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ lane_to_slot_fsm2[4] = EMI1_SLOT4;
+ lane_to_slot_fsm2[5] = EMI1_SLOT4;
+ lane_to_slot_fsm2[6] = EMI1_SLOT4;
+ lane_to_slot_fsm2[7] = EMI1_SLOT4;
+ } else {
+ /* No MDIO physical connection */
+ lane_to_slot_fsm2[4] = EMI1_SLOT6;
+ lane_to_slot_fsm2[5] = EMI1_SLOT6;
+ lane_to_slot_fsm2[6] = EMI1_SLOT6;
+ lane_to_slot_fsm2[7] = EMI1_SLOT6;
+ }
+ break;
+ default:
+ printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
+ __func__ , serdes2_prtcl);
+ break;
+ }
+}
+
+void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
+{
+ int lane, slot;
+ struct mii_dev *bus;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+ >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+ int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
+ >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+ int *riser_phy_addr;
+ char *env_hwconfig = getenv("hwconfig");
+
+ if (hwconfig_f("xqsgmii", env_hwconfig))
+ riser_phy_addr = &xqsgii_riser_phy_addr[0];
+ else
+ riser_phy_addr = &sgmii_riser_phy_addr[0];
+
+ if (dpmac_id > WRIOP1_DPMAC9)
+ goto serdes2;
+
+ switch (serdes1_prtcl) {
+ case 0x07:
+
+ lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id);
+ slot = lane_to_slot_fsm1[lane];
+
+ switch (++slot) {
+ case 1:
+ /* Slot housing a SGMII riser card? */
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 1]);
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
+ bus = mii_dev_for_muxval(EMI1_SLOT1);
+ wriop_set_mdio(dpmac_id, bus);
+ dpmac_info[dpmac_id].phydev = phy_connect(
+ dpmac_info[dpmac_id].bus,
+ dpmac_info[dpmac_id].phy_addr,
+ NULL,
+ dpmac_info[dpmac_id].enet_if);
+ phy_config(dpmac_info[dpmac_id].phydev);
+ break;
+ case 2:
+ /* Slot housing a SGMII riser card? */
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 1]);
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
+ bus = mii_dev_for_muxval(EMI1_SLOT2);
+ wriop_set_mdio(dpmac_id, bus);
+ dpmac_info[dpmac_id].phydev = phy_connect(
+ dpmac_info[dpmac_id].bus,
+ dpmac_info[dpmac_id].phy_addr,
+ NULL,
+ dpmac_info[dpmac_id].enet_if);
+ phy_config(dpmac_info[dpmac_id].phydev);
+ break;
+ case 3:
+ break;
+ case 4:
+ break;
+ case 5:
+ break;
+ case 6:
+ break;
+ }
+ break;
+ default:
+ printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+ __func__ , serdes1_prtcl);
+ break;
+ }
+
+serdes2:
+ switch (serdes2_prtcl) {
+ case 0x07:
+ case 0x08:
+ case 0x49:
+ lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
+ (dpmac_id - 9));
+ slot = lane_to_slot_fsm2[lane];
+
+ switch (++slot) {
+ case 1:
+ break;
+ case 3:
+ break;
+ case 4:
+ /* Slot housing a SGMII riser card? */
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 9]);
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
+ bus = mii_dev_for_muxval(EMI1_SLOT4);
+ wriop_set_mdio(dpmac_id, bus);
+ dpmac_info[dpmac_id].phydev = phy_connect(
+ dpmac_info[dpmac_id].bus,
+ dpmac_info[dpmac_id].phy_addr,
+ NULL,
+ dpmac_info[dpmac_id].enet_if);
+ phy_config(dpmac_info[dpmac_id].phydev);
+ break;
+ case 5:
+ break;
+ case 6:
+ /* Slot housing a SGMII riser card? */
+ wriop_set_phy_address(dpmac_id,
+ riser_phy_addr[dpmac_id - 13]);
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
+ bus = mii_dev_for_muxval(EMI1_SLOT6);
+ wriop_set_mdio(dpmac_id, bus);
+ break;
+ }
+ break;
+ default:
+ printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
+ __func__, serdes2_prtcl);
+ break;
+ }
+}
+
+void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
+{
+ int lane = 0, slot;
+ struct mii_dev *bus;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+ >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ switch (serdes1_prtcl) {
+ case 0x33:
+ switch (dpmac_id) {
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
+ break;
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
+ break;
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
+ break;
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
+ break;
+ }
+
+ slot = lane_to_slot_fsm1[lane];
+
+ switch (++slot) {
+ case 1:
+ /* Slot housing a QSGMII riser card? */
+ wriop_set_phy_address(dpmac_id, dpmac_id - 1);
+ dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
+ bus = mii_dev_for_muxval(EMI1_SLOT1);
+ wriop_set_mdio(dpmac_id, bus);
+ dpmac_info[dpmac_id].phydev = phy_connect(
+ dpmac_info[dpmac_id].bus,
+ dpmac_info[dpmac_id].phy_addr,
+ NULL,
+ dpmac_info[dpmac_id].enet_if);
+
+ phy_config(dpmac_info[dpmac_id].phydev);
+ break;
+ case 3:
+ break;
+ case 4:
+ break;
+ case 5:
+ break;
+ case 6:
+ break;
+ }
+ break;
+ default:
+ printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ }
+
+ qsgmii_configure_repeater(dpmac_id);
+}
+
+void ls2080a_handle_phy_interface_xsgmii(int i)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+ >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ switch (serdes1_prtcl) {
+ case 0x2A:
+ /*
+ * XFI does not need a PHY to work, but to avoid U-boot use
+ * default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to XFI
+ * MAC, and should not use a real XAUI PHY address, since
+ * MDIO can access it successfully, and then MDIO thinks
+ * the XAUI card is used for the XFI MAC, which will cause
+ * error.
+ */
+ wriop_set_phy_address(i, i + 4);
+ ls2080a_qds_enable_SFP_TX(SFP_TX);
+
+ break;
+ default:
+ printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ }
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int error;
+#ifdef CONFIG_FSL_MC_ENET
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
+ >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+ int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
+ >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+ struct memac_mdio_info *memac_mdio0_info;
+ struct memac_mdio_info *memac_mdio1_info;
+ unsigned int i;
+ char *env_hwconfig;
+
+ env_hwconfig = getenv("hwconfig");
+
+ initialize_dpmac_to_slot();
+
+ memac_mdio0_info = (struct memac_mdio_info *)malloc(
+ sizeof(struct memac_mdio_info));
+ memac_mdio0_info->regs =
+ (struct memac_mdio_controller *)
+ CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
+
+ /* Register the real MDIO1 bus */
+ fm_memac_mdio_init(bis, memac_mdio0_info);
+
+ memac_mdio1_info = (struct memac_mdio_info *)malloc(
+ sizeof(struct memac_mdio_info));
+ memac_mdio1_info->regs =
+ (struct memac_mdio_controller *)
+ CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
+
+ /* Register the real MDIO2 bus */
+ fm_memac_mdio_init(bis, memac_mdio1_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
+
+ ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
+
+ for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+ switch (wriop_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_QSGMII:
+ ls2080a_handle_phy_interface_qsgmii(i);
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ ls2080a_handle_phy_interface_sgmii(i);
+ break;
+ case PHY_INTERFACE_MODE_XGMII:
+ ls2080a_handle_phy_interface_xsgmii(i);
+ break;
+ default:
+ break;
+
+ if (i == 16)
+ i = NUM_WRIOP_PORTS;
+ }
+ }
+
+ error = cpu_eth_init(bis);
+
+ if (hwconfig_f("xqsgmii", env_hwconfig)) {
+ if (serdes1_prtcl == 0x7)
+ sgmii_configure_repeater(1);
+ if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
+ serdes2_prtcl == 0x49)
+ sgmii_configure_repeater(2);
+ }
+#endif
+ error = pci_eth_init(bis);
+ return error;
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+
+#endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <fsl_debug_server.h>
+#include <fsl-mc/fsl_mc.h>
+#include <environment.h>
+#include <i2c.h>
+#include <rtc.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+
+#include "../common/qixis.h"
+#include "ls2080aqds_qixis.h"
+
+#define PIN_MUX_SEL_SDHC 0x00
+#define PIN_MUX_SEL_DSPI 0x0a
+
+#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ MUX_TYPE_SDHC,
+ MUX_TYPE_DSPI,
+};
+
+unsigned long long get_qixis_addr(void)
+{
+ unsigned long long addr;
+
+ if (gd->flags & GD_FLG_RELOC)
+ addr = QIXIS_BASE_PHYS;
+ else
+ addr = QIXIS_BASE_PHYS_EARLY;
+
+ /*
+ * IFC address under 256MB is mapped to 0x30000000, any address above
+ * is mapped to 0x5_10000000 up to 4GB.
+ */
+ addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
+
+ return addr;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+ static const char *const freq[] = {"100", "125", "156.25",
+ "100 separate SSCG"};
+ int clock;
+
+ cpu_name(buf);
+ printf("Board: %s-QDS, ", buf);
+
+ sw = QIXIS_READ(arch);
+ printf("Board Arch: V%d, ", sw >> 4);
+ printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+ memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("PromJet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else if (sw == 0x15)
+ printf("IFCCard\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ /*
+ * Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts("SERDES1 Reference : ");
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = (sw >> 6) & 3;
+ printf("Clock1 = %sMHz ", freq[clock]);
+ clock = (sw >> 4) & 3;
+ printf("Clock2 = %sMHz", freq[clock]);
+
+ puts("\nSERDES2 Reference : ");
+ clock = (sw >> 2) & 3;
+ printf("Clock1 = %sMHz ", freq[clock]);
+ clock = (sw >> 0) & 3;
+ printf("Clock2 = %sMHz\n", freq[clock]);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int config_board_mux(int ctrl_type)
+{
+ u8 reg5;
+
+ reg5 = QIXIS_READ(brdcfg[5]);
+
+ switch (ctrl_type) {
+ case MUX_TYPE_SDHC:
+ reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
+ break;
+ case MUX_TYPE_DSPI:
+ reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
+ break;
+ default:
+ printf("Wrong mux interface type\n");
+ return -1;
+ }
+
+ QIXIS_WRITE(brdcfg[5], reg5);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ char *env_hwconfig;
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+ u32 val;
+
+ init_final_memctl_regs();
+
+ val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+ env_hwconfig = getenv("hwconfig");
+
+ if (hwconfig_f("dspi", env_hwconfig) &&
+ DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
+ config_board_mux(MUX_TYPE_DSPI);
+ else
+ config_board_mux(MUX_TYPE_SDHC);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ rtc_enable_32khz_output();
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+ print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+ if (gd->bd->bi_dram[2].size) {
+ puts("\nDP-DDR ");
+ print_size(gd->bd->bi_dram[2].size, "");
+ print_ddr_info(CONFIG_DP_DDR_CTRL);
+ }
+#endif
+}
+
+int dram_init(void)
+{
+ gd->ram_size = initdram(0);
+
+ return 0;
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+#ifdef CONFIG_FSL_DEBUG_SERVER
+ debug_server_init();
+#endif
+
+ return 0;
+}
+#endif
+
+unsigned long get_dram_size_to_hide(void)
+{
+ unsigned long dram_to_hide = 0;
+
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+ dram_to_hide += debug_server_get_dram_block_size();
+#endif
+
+/* Carve the MC private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_MC_ENET
+ dram_to_hide += mc_get_dram_block_size();
+#endif
+
+ return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/fsl-mc");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+
+ if (offset < 0) {
+ printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+ __func__, offset);
+ return;
+ }
+
+ if (get_mc_boot_status() == 0)
+ fdt_status_okay(fdt, offset);
+ else
+ fdt_status_fail(fdt, offset);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int err;
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ ft_cpu_setup(blob, bd);
+
+ /* fixup DT for the two GPP DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
+
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fixup_board_enet(blob);
+ err = fsl_mc_ldpaa_exit(bd);
+ if (err)
+ return err;
+#endif
+
+ return 0;
+}
+#endif
+
+void qixis_dump_switch(void)
+{
+ int i, nr_of_cfgsw;
+
+ QIXIS_WRITE(cms[0], 0x00);
+ nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+ puts("DIP switch settings dump:\n");
+ for (i = 1; i <= nr_of_cfgsw; i++) {
+ QIXIS_WRITE(cms[0], i);
+ printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+ }
+}
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS2_QDS_QIXIS_H__
+#define __LS2_QDS_QIXIS_H__
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+#define BRDCFG9_SFPTX_MASK 0x10
+#define BRDCFG9_SFPTX_SHIFT 4
+#endif /*__LS2_QDS_QIXIS_H__*/
--- /dev/null
+
+if TARGET_LS2080ARDB
+
+config SYS_BOARD
+ default "ls2080ardb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "ls2080ardb"
+
+endif
--- /dev/null
+LS2080A BOARD
+M: Prabhakar Kushwaha <prabhakar@freescale.com>
+S: Maintained
+F: board/freescale/ls2080ardb/
+F: board/freescale/ls2080a/ls2080ardb.c
+F: include/configs/ls2080ardb.h
+F: configs/ls2080ardb_defconfig
+F: configs/ls2080ardb_nand_defconfig
+F: configs/ls2085ardb_defconfig
+F: configs/ls2085ardb_nand_defconfig
--- /dev/null
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls2080ardb.o eth_ls2080rdb.o
+obj-y += ddr.o
--- /dev/null
+Overview
+--------
+The LS2080A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
+Layerscape Architecture processor.
+
+LS2080A SoC Overview
+------------------
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2080A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+ the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+ - Packet parsing, classification, and distribution (WRIOP)
+ - Queue and Hardware buffer management for scheduling, packet sequencing, and
+ congestion management, buffer allocation and de-allocation (QBMan)
+ - Cryptography acceleration (SEC) at up to 10 Gbps
+ - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+ - Decompression/compression acceleration (DCE) at up to 20 Gbps
+ - Accelerated I/O processing (AIOP) at up to 20 Gbps
+ - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+ - Up to eight 10 Gbps Ethernet MACs
+ - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 3.0) controllers
+ - Two high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Serial peripheral interface (SPI) controller
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+ capabilities
+
+ LS2080ARDB board Overview
+ -----------------------
+ - SERDES Connections, 16 lanes supporting:
+ - PCI Express - 3.0
+ - SATA 3.0
+ - XFI
+ - DDR Controller
+ - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
+ chip-selects and two DIMM connectors. Support is up to 2133MT/s.
+ - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
+ and two DIMM connectors. Support is up to 1600MT/s.
+ -IFC/Local Bus
+ - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
+ - 128 MB NOR flash 16-bit data bus
+ - One 2 GB NAND flash with ECC support
+ - CPLD connection
+ - USB 3.0
+ - Two high speed USB 3.0 ports
+ - First USB 3.0 port configured as Host with Type-A connector
+ - Second USB 3.0 port configured as OTG with micro-AB connector
+ - SDHC adapter
+ - SD Card Rev 2.0 and Rev 3.0
+ - DSPI
+ - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+ - 4 I2C controllers
+ - Two SATA onboard connectors
+ - UART
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
+0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
+
+Other addresses are either reserved, or not used directly by u-boot.
+This list should be updated when more addresses are used.
+
+IFC region map from core's view
+-------------------------------
+During boot i.e. IFC Region #1:-
+ 0x30000000 - 0x37ffffff : 128MB : NOR flash
+ 0x3C000000 - 0x40000000 : 64MB : CPLD
+
+After relocate to DDR i.e. IFC Region #2:-
+ 0x5_1000_0000..0x5_1fff_ffff Memory Hole
+ 0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB)
+ 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
+ 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
+ 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
+
+Booting Options
+---------------
+a) NOR boot
+b) NAND boot
+
+Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
+-------------------------------------------------------------------
+One needs to use appropriate bootargs to boot Linux flavors which do
+not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
+below:
+
+=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
+ earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
+ hugepages=16 mem=2048M'
+
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+ u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+ int slot;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+
+ for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
+ if (pdimm[slot].n_ranks)
+ break;
+ }
+
+ if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[ctrl_num];
+ else
+ pbsp = udimms[ctrl_num];
+
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm[slot].n_ranks &&
+ (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for data rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+ if (ctrl_num == CONFIG_DP_DDR_CTRL) {
+ /* force DDR bus width to 32 bits */
+ popts->data_bus_width = 1;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ popts->bstopre = 0; /* enable auto precharge */
+ /*
+ * Layout optimization results byte mapping
+ * Byte 0 -> Byte ECC
+ * Byte 1 -> Byte 3
+ * Byte 2 -> Byte 2
+ * Byte 3 -> Byte 1
+ * Byte ECC -> Byte 0
+ */
+ dq_mapping_0 = pdimm[slot].dq_mapping[0];
+ dq_mapping_2 = pdimm[slot].dq_mapping[2];
+ dq_mapping_3 = pdimm[slot].dq_mapping[3];
+ pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
+ pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
+ pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
+ pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
+ pdimm[slot].dq_mapping[6] = dq_mapping_2;
+ pdimm[slot].dq_mapping[7] = dq_mapping_3;
+ pdimm[slot].dq_mapping[8] = dq_mapping_0;
+ pdimm[slot].dq_mapping[9] = 0;
+ pdimm[slot].dq_mapping[10] = 0;
+ pdimm[slot].dq_mapping[11] = 0;
+ pdimm[slot].dq_mapping[12] = 0;
+ pdimm[slot].dq_mapping[13] = 0;
+ pdimm[slot].dq_mapping[14] = 0;
+ pdimm[slot].dq_mapping[15] = 0;
+ pdimm[slot].dq_mapping[16] = 0;
+ pdimm[slot].dq_mapping[17] = 0;
+ }
+#endif
+ /* To work at higher than 1333MT/s */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0x0; /* 32 clocks */
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ if (ddr_freq < 2350) {
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+ DDR_CDR2_VREF_RANGE_2;
+ } else {
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
+ DDR_CDR2_VREF_RANGE_2;
+ }
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ return fsl_ddr_sdram_size();
+#else
+ puts("Initializing DDR....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+#endif
+
+ return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+ phys_size_t dp_ddr_size;
+#endif
+
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ } else {
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ }
+
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+ /* initialize DP-DDR here */
+ puts("DP-DDR: ");
+ /*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+ dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+ CONFIG_DP_DDR_CTRL,
+ CONFIG_DP_DDR_NUM_CTRLS,
+ CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
+ NULL, NULL, NULL);
+ if (dp_ddr_size) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->bd->bi_dram[2].size = dp_ddr_size;
+ } else {
+ puts("Not detected");
+ }
+#endif
+}
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
+ {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
+ {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
+ {}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters udimm2[] = {
+ /*
+ * memory controller 2
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
+ {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
+ {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters rdimm2[] = {
+ /*
+ * memory controller 2
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
+ {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
+ {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+ udimm0,
+ udimm2,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+ rdimm0,
+ rdimm2,
+};
+
+
+#endif
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int load_firmware_cortina(struct phy_device *phy_dev)
+{
+ if (phy_dev->drv->config)
+ return phy_dev->drv->config(phy_dev);
+
+ return 0;
+}
+
+void load_phy_firmware(void)
+{
+ int i;
+ u8 phy_addr;
+ struct phy_device *phy_dev;
+ struct mii_dev *dev;
+ phy_interface_t interface;
+
+ /*Initialize and upload firmware for all the PHYs*/
+ for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
+ interface = wriop_get_enet_if(i);
+ if (interface == PHY_INTERFACE_MODE_XGMII) {
+ dev = wriop_get_mdio(i);
+ phy_addr = wriop_get_phy_address(i);
+ phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
+ interface);
+ if (!phy_dev) {
+ printf("No phydev for phyaddr %d\n", phy_addr);
+ continue;
+ }
+
+ /*Flash firmware for All CS4340 PHYS */
+ if (phy_dev->phy_id == PHY_UID_CS4340)
+ load_firmware_cortina(phy_dev);
+ }
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ int i, interface;
+ struct memac_mdio_info mdio_info;
+ struct mii_dev *dev;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1;
+ struct memac_mdio_controller *reg;
+
+ srds_s1 = in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ mdio_info.regs = reg;
+ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+ /* Register the EMI 1 */
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ mdio_info.regs = reg;
+ mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+ /* Register the EMI 2 */
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ switch (srds_s1) {
+ case 0x2A:
+ wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
+ wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
+ wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+ wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
+ wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
+ wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
+
+ break;
+ default:
+ printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
+ srds_s1);
+ break;
+ }
+
+ for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
+ interface = wriop_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ wriop_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
+ switch (wriop_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+ wriop_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Load CORTINA CS4340 PHY firmware */
+ load_phy_firmware();
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+#ifdef CONFIG_PHY_AQUANTIA
+ /*
+ * Export functions to be used by AQ firmware
+ * upload application
+ */
+ gd->jt->strcpy = strcpy;
+ gd->jt->mdelay = mdelay;
+ gd->jt->mdio_get_current_dev = mdio_get_current_dev;
+ gd->jt->phy_find_by_mask = phy_find_by_mask;
+ gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
+ gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
+#endif
+ return pci_eth_init(bis);
+}
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <hwconfig.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <fsl_debug_server.h>
+#include <fsl-mc/fsl_mc.h>
+#include <environment.h>
+#include <i2c.h>
+#include <asm/arch/soc.h>
+
+#include "../common/qixis.h"
+#include "ls2080ardb_qixis.h"
+
+#define PIN_MUX_SEL_SDHC 0x00
+#define PIN_MUX_SEL_DSPI 0x0a
+
+#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ MUX_TYPE_SDHC,
+ MUX_TYPE_DSPI,
+};
+
+unsigned long long get_qixis_addr(void)
+{
+ unsigned long long addr;
+
+ if (gd->flags & GD_FLG_RELOC)
+ addr = QIXIS_BASE_PHYS;
+ else
+ addr = QIXIS_BASE_PHYS_EARLY;
+
+ /*
+ * IFC address under 256MB is mapped to 0x30000000, any address above
+ * is mapped to 0x5_10000000 up to 4GB.
+ */
+ addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
+
+ return addr;
+}
+
+int checkboard(void)
+{
+ u8 sw;
+ char buf[15];
+
+ cpu_name(buf);
+ printf("Board: %s-RDB, ", buf);
+
+ sw = QIXIS_READ(arch);
+ printf("Board Arch: V%d, ", sw >> 4);
+ printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+ printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+
+ puts("SERDES1 Reference : ");
+ printf("Clock1 = 156.25MHz ");
+ printf("Clock2 = 156.25MHz");
+
+ puts("\nSERDES2 Reference : ");
+ printf("Clock1 = 100MHz ");
+ printf("Clock2 = 100MHz\n");
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int config_board_mux(int ctrl_type)
+{
+ u8 reg5;
+
+ reg5 = QIXIS_READ(brdcfg[5]);
+
+ switch (ctrl_type) {
+ case MUX_TYPE_SDHC:
+ reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
+ break;
+ case MUX_TYPE_DSPI:
+ reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
+ break;
+ default:
+ printf("Wrong mux interface type\n");
+ return -1;
+ }
+
+ QIXIS_WRITE(brdcfg[5], reg5);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ char *env_hwconfig;
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+ u32 val;
+
+ init_final_memctl_regs();
+
+ val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+ env_hwconfig = getenv("hwconfig");
+
+ if (hwconfig_f("dspi", env_hwconfig) &&
+ DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
+ config_board_mux(MUX_TYPE_DSPI);
+ else
+ config_board_mux(MUX_TYPE_SDHC);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+ QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ if (hwconfig("sdhc"))
+ config_board_mux(MUX_TYPE_SDHC);
+
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+ print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+ if (gd->bd->bi_dram[2].size) {
+ puts("\nDP-DDR ");
+ print_size(gd->bd->bi_dram[2].size, "");
+ print_ddr_info(CONFIG_DP_DDR_CTRL);
+ }
+#endif
+}
+
+int dram_init(void)
+{
+ gd->ram_size = initdram(0);
+
+ return 0;
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+#ifdef CONFIG_FSL_DEBUG_SERVER
+ debug_server_init();
+#endif
+
+ return 0;
+}
+#endif
+
+unsigned long get_dram_size_to_hide(void)
+{
+ unsigned long dram_to_hide = 0;
+
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+ dram_to_hide += debug_server_get_dram_block_size();
+#endif
+
+/* Carve the MC private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_MC_ENET
+ dram_to_hide += mc_get_dram_block_size();
+#endif
+
+ return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/fsl-mc");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+
+ if (offset < 0) {
+ printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+ __func__, offset);
+ return;
+ }
+
+ if (get_mc_boot_status() == 0)
+ fdt_status_okay(fdt, offset);
+ else
+ fdt_status_fail(fdt, offset);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int err;
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ ft_cpu_setup(blob, bd);
+
+ /* fixup DT for the two GPP DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
+
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fixup_board_enet(blob);
+ err = fsl_mc_ldpaa_exit(bd);
+ if (err)
+ return err;
+#endif
+
+ return 0;
+}
+#endif
+
+void qixis_dump_switch(void)
+{
+ int i, nr_of_cfgsw;
+
+ QIXIS_WRITE(cms[0], 0x00);
+ nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+ puts("DIP switch settings dump:\n");
+ for (i = 1; i <= nr_of_cfgsw; i++) {
+ QIXIS_WRITE(cms[0], i);
+ printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+ }
+}
+
+/*
+ * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
+ * Both slots has 0x54, resulting 2nd slot unusable.
+ */
+void update_spd_address(unsigned int ctrl_num,
+ unsigned int slot,
+ unsigned int *addr)
+{
+ u8 sw;
+
+ sw = QIXIS_READ(arch);
+ if ((sw & 0xf) < 0x3) {
+ if (ctrl_num == 1 && slot == 0)
+ *addr = SPD_EEPROM_ADDRESS4;
+ else if (ctrl_num == 1 && slot == 1)
+ *addr = SPD_EEPROM_ADDRESS3;
+ }
+}
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS2_RDB_QIXIS_H__
+#define __LS2_RDB_QIXIS_H__
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+
+#endif /*__LS2_RDB_QIXIS_H__*/
+++ /dev/null
-if TARGET_LS2085A_EMU
-
-config SYS_BOARD
- default "ls2085a"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls2085a_emu"
-
-endif
-
-if TARGET_LS2085A_SIMU
-
-config SYS_BOARD
- default "ls2085a"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls2085a_simu"
-
-endif
+++ /dev/null
-LS2085A BOARD
-M: York Sun <yorksun@freescale.com>
-S: Maintained
-F: board/freescale/ls2085a/
-F: include/configs/ls2085a_emu.h
-F: configs/ls2085a_emu_defconfig
-F: include/configs/ls2085a_simu.h
-F: configs/ls2085a_simu_defconfig
+++ /dev/null
-#
-# Copyright 2014 Freescale Semiconductor
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ls2085a.o
-obj-y += ddr.o
+++ /dev/null
-Freescale ls2085a_emu
-
-This is a emulator target with limited peripherals.
-
-Memory map from core's view
-
-0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
-0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
-0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
-0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
-0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
-0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
-0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
-
-Other addresses are either reserved, or not used directly by u-boot.
-This list should be updated when more addresses are used.
-
-Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
--------------------------------------------------------------------
-One needs to use appropriate bootargs to boot Linux flavors which do
-not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
-below:
-
-=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
- earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
- hugepages=16 mem=2048M'
-
+++ /dev/null
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 3) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /*
- * we use identical timing for all slots. If needed, change the code
- * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
- */
- if (popts->registered_dimm_en)
- pbsp = rdimms[ctrl_num];
- else
- pbsp = udimms[ctrl_num];
-
-
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for data rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- if (ctrl_num == CONFIG_DP_DDR_CTRL) {
- /* force DDR bus width to 32 bits */
- popts->data_bus_width = 1;
- popts->otf_burst_chop_en = 0;
- popts->burst_length = DDR_BL8;
- popts->bstopre = 0; /* enable auto precharge */
- }
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 1;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
-#ifdef CONFIG_SYS_FSL_DDR4
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
- DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
-#else
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-#endif
-}
-
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 2,
- .rank_density = 1073741824u,
- .capacity = 2147483648,
- .primary_sdram_width = 64,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 14,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 937,
- .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
- .taa_ps = 13090,
- .twr_ps = 15000,
- .trcd_ps = 13090,
- .trrd_ps = 5000,
- .trp_ps = 13090,
- .tras_ps = 33000,
- .trc_ps = 46090,
- .trfc_ps = 160000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 25000,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "Fixed DDR on board";
-
- if (((controller_number == 0) && (dimm_number == 0)) ||
- ((controller_number == 1) && (dimm_number == 0))) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-#endif
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size;
-
- puts("Initializing DDR....");
-
- puts("using SPD\n");
- dram_size = fsl_ddr_sdram();
-
- return dram_size;
-}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- phys_size_t dp_ddr_size;
-#endif
-
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
- }
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
- CONFIG_DP_DDR_CTRL,
- CONFIG_DP_DDR_NUM_CTRLS,
- CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
- NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
- }
-#endif
-}
+++ /dev/null
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 2140, 0, 4, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-/* DP-DDR DIMM */
-static const struct board_specific_parameters udimm2[] = {
- /*
- * memory controller 2
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 2140, 0, 4, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {4, 2140, 0, 5, 4, 0x0, 0x0},
- {2, 2140, 0, 5, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-/* DP-DDR DIMM */
-static const struct board_specific_parameters rdimm2[] = {
- /*
- * memory controller 2
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {4, 2140, 0, 5, 4, 0x0, 0x0},
- {2, 2140, 0, 5, 4, 0x0, 0x0},
- {1, 2140, 0, 4, 4, 0x0, 0x0},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
- udimm0,
- udimm2,
-};
-
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
- rdimm0,
- rdimm2,
-};
-
-
-#endif
+++ /dev/null
-/*
- * Copyright 2014 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <netdev.h>
-#include <fsl_ifc.h>
-#include <fsl_ddr.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <libfdt.h>
-#include <fsl_debug_server.h>
-#include <fsl-mc/fsl_mc.h>
-#include <environment.h>
-#include <asm/arch/soc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- init_final_memctl_regs();
-
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- fsl_lsch3_early_init_f();
- return 0;
-}
-
-void detail_board_ddr_info(void)
-{
- puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
- print_ddr_info(0);
- if (gd->bd->bi_dram[2].size) {
- puts("\nDP-DDR ");
- print_size(gd->bd->bi_dram[2].size, "");
- print_ddr_info(CONFIG_DP_DDR_CTRL);
- }
-}
-
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
-#ifdef CONFIG_FSL_DEBUG_SERVER
- debug_server_init();
-#endif
-
- return 0;
-}
-#endif
-
-unsigned long get_dram_size_to_hide(void)
-{
- unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
- dram_to_hide += debug_server_get_dram_block_size();
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
- dram_to_hide += mc_get_dram_block_size();
-#endif
-
- return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
-}
-
-int board_eth_init(bd_t *bis)
-{
- int error = 0;
-
-#ifdef CONFIG_SMC91111
- error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-
-#ifdef CONFIG_FSL_MC_ENET
- error = cpu_eth_init(bis);
-#endif
- return error;
-}
-
-#ifdef CONFIG_FSL_MC_ENET
-void fdt_fixup_board_enet(void *fdt)
-{
- int offset;
-
- offset = fdt_path_offset(fdt, "/fsl-mc");
-
- /*
- * TODO: Remove this when backward compatibility
- * with old DT node (fsl,dprc@0) is no longer needed.
- */
- if (offset < 0)
- offset = fdt_path_offset(fdt, "/fsl,dprc@0");
-
- if (offset < 0) {
- printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
- __func__, offset);
- return;
- }
-
- if (get_mc_boot_status() == 0)
- fdt_status_okay(fdt, offset);
- else
- fdt_status_fail(fdt, offset);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
-
- ft_cpu_setup(blob, bd);
-
- /* fixup DT for the two GPP DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
-
- fdt_fixup_memory_banks(blob, base, size, 2);
-
-#ifdef CONFIG_FSL_MC_ENET
- fdt_fixup_board_enet(blob);
- fsl_mc_ldpaa_exit(bd);
-#endif
-
- return 0;
-}
-#endif
+++ /dev/null
-
-if TARGET_LS2085AQDS
-
-config SYS_BOARD
- default "ls2085aqds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls2085aqds"
-
-endif
+++ /dev/null
-LS2085A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
-S: Maintained
-F: board/freescale/ls2085aqds/
-F: board/freescale/ls2085a/ls2085aqds.c
-F: include/configs/ls2085aqds.h
-F: configs/ls2085aqds_defconfig
-F: configs/ls2085aqds_nand_defconfig
+++ /dev/null
-#
-# Copyright 2015 Freescale Semiconductor
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ls2085aqds.o
-obj-y += ddr.o
-obj-y += eth.o
+++ /dev/null
-Overview
---------
-The LS2085A Development System (QDS) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
-Layerscape Architecture processor. The LS2085AQDS provides validation and
-SW development platform for the Freescale LS2085A processor series, with
-a complete debugging environment.
-
-LS2085A SoC Overview
-------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2085A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
- the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
- - Packet parsing, classification, and distribution (WRIOP)
- - Queue and Hardware buffer management for scheduling, packet sequencing, and
- congestion management, buffer allocation and de-allocation (QBMan)
- - Cryptography acceleration (SEC) at up to 10 Gbps
- - RegEx pattern matching acceleration (PME) at up to 10 Gbps
- - Decompression/compression acceleration (DCE) at up to 20 Gbps
- - Accelerated I/O processing (AIOP) at up to 20 Gbps
- - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
- - Up to eight 10 Gbps Ethernet MACs
- - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
- - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
- - Two serial ATA (SATA 3.0) controllers
- - Two high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Serial peripheral interface (SPI) controller
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
- capabilities
-
- LS2085AQDS board Overview
- -----------------------
- - SERDES Connections, 16 lanes supporting:
- - PCI Express - 3.0
- - SGMII, SGMII 2.5
- - QSGMII
- - SATA 3.0
- - XAUI
- - XFI
- - DDR Controller
- - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
- chip-selects and two DIMM connectors. Support is up to 2133MT/s.
- - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
- and two DIMM connectors. Support is up to 1600MT/s.
- -IFC/Local Bus
- - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
- - One in-socket 128 MB NOR flash 16-bit data bus
- - One 512 MB NAND flash with ECC support
- - IFC Test Port
- - PromJet Port
- - FPGA connection
- - USB 3.0
- - Two high speed USB 3.0 ports
- - First USB 3.0 port configured as Host with Type-A connector
- - Second USB 3.0 port configured as OTG with micro-AB connector
- - SDHC: PCIe x1 Right Angle connector for supporting following cards
- - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only
- - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only
- - 4-bit eMMC Card Rev 4.4 (1.8V only)
- - 8-bit eMMC Card Rev 4.5 (1.8V only)
- - SD Card Rev 2.0 and Rev 3.0
- - DSPI: 3 high-speed flash Memory for storage
- - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
- - 8 MB high-speed flash Memory (up to 104 MHz)
- - 512 MB low-speed flash Memory (up to 40 MHz)
- - QSPI: via NAND/QSPI Card
- - 4 I2C controllers
- - Two SATA onboard connectors
- - UART
- - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
- - Two DB9 D-Type connectors supporting one Serial port each
- - ARM JTAG support
-
-Memory map from core's view
-----------------------------
-0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
-0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
-0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
-0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
-0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
-0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
-0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
-
-Other addresses are either reserved, or not used directly by u-boot.
-This list should be updated when more addresses are used.
-
-IFC region map from core's view
--------------------------------
-During boot i.e. IFC Region #1:-
- 0x30000000 - 0x37ffffff : 128MB : NOR flash
- 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
- 0x3C000000 - 0x40000000 : 64MB : FPGA etc
-
-After relocate to DDR i.e. IFC Region #2:-
- 0x5_1000_0000..0x5_1fff_ffff Memory Hole
- 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
- 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
- 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
- 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
-
-Booting Options
----------------
-a) Promjet Boot
-b) NOR boot
-c) NAND boot
-d) SD boot
-e) QSPI boot
-
-Environment Variables
----------------------
-- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
- the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
-
-- mcmemsize: MC DRAM block size. If this variable is not defined
- the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
-
-Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
--------------------------------------------------------------------
-One needs to use appropriate bootargs to boot Linux flavors which do
-not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
-below:
-
-=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
- earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
- hugepages=16 mem=2048M'
-
-
-X-QSGMII-16PORT riser card
-----------------------------
-The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
-interfaces implemented in PCIe form factor board.
-It supports followings
- - Card can operate with up to 4 QSGMII lane simultaneously
- - Card can operate with up to 8 SGMII lane simultaneously
-
-Supported card configuration
- - CSEL : ON ON ON ON
- - MSEL1 : ON ON ON ON OFF OFF OFF OFF
- - MSEL2 : OFF OFF OFF OFF ON ON ON ON
-
-To enable this card: modify hwconfig to add "xqsgmii" variable.
-
-Supported PHY addresses during SGMII:
-#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
-#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
-#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
-#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
-#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
-#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
-#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
-#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
-
-Mapping DPMACx to PHY during QSGMII
-DPMAC1 -> PHY1-P0
-DPMAC2 -> PHY2-P0
-DPMAC3 -> PHY3-P0
-DPMAC4 -> PHY4-P0
-DPMAC5 -> PHY3-P2
-DPMAC6 -> PHY1-P2
-DPMAC7 -> PHY4-P1
-DPMAC8 -> PHY2-P2
-DPMAC9 -> PHY1-P0
-DPMAC10 -> PHY2-P0
-DPMAC11 -> PHY3-P0
-DPMAC12 -> PHY4-P0
-DPMAC13 -> PHY3-P2
-DPMAC14 -> PHY1-P2
-DPMAC15 -> PHY4-P1
-DPMAC16 -> PHY2-P2
-
-
-Supported PHY address during QSGMII
-#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
-#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
-#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
-#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
-#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
-#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
-#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
-#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
-#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
-#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
-#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
-#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
-#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
-#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
-#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
-#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
-
-Mapping DPMACx to PHY during QSGMII
-DPMAC1 -> PHY1-P3
-DPMAC2 -> PHY1-P2
-DPMAC3 -> PHY1-P1
-DPMAC4 -> PHY1-P0
-DPMAC5 -> PHY2-P3
-DPMAC6 -> PHY2-P2
-DPMAC7 -> PHY2-P1
-DPMAC8 -> PHY2-P0
-DPMAC9 -> PHY3-P0
-DPMAC10 -> PHY3-P1
-DPMAC11 -> PHY3-P2
-DPMAC12 -> PHY3-P3
-DPMAC13 -> PHY4-P0
-DPMAC14 -> PHY4-P1
-DPMAC15 -> PHY4-P2
-DPMAC16 -> PHY4-P3
-
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
- int slot;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
-
- for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
- if (pdimm[slot].n_ranks)
- break;
- }
-
- if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
- return;
-
- /*
- * we use identical timing for all slots. If needed, change the code
- * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
- */
- if (popts->registered_dimm_en)
- pbsp = rdimms[ctrl_num];
- else
- pbsp = udimms[ctrl_num];
-
-
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm[slot].n_ranks &&
- (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for data rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- if (ctrl_num == CONFIG_DP_DDR_CTRL) {
- /* force DDR bus width to 32 bits */
- popts->data_bus_width = 1;
- popts->otf_burst_chop_en = 0;
- popts->burst_length = DDR_BL8;
- popts->bstopre = 0; /* enable auto precharge */
- /*
- * Layout optimization results byte mapping
- * Byte 0 -> Byte ECC
- * Byte 1 -> Byte 3
- * Byte 2 -> Byte 2
- * Byte 3 -> Byte 1
- * Byte ECC -> Byte 0
- */
- dq_mapping_0 = pdimm[slot].dq_mapping[0];
- dq_mapping_2 = pdimm[slot].dq_mapping[2];
- dq_mapping_3 = pdimm[slot].dq_mapping[3];
- pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
- pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
- pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
- pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
- pdimm[slot].dq_mapping[6] = dq_mapping_2;
- pdimm[slot].dq_mapping[7] = dq_mapping_3;
- pdimm[slot].dq_mapping[8] = dq_mapping_0;
- pdimm[slot].dq_mapping[9] = 0;
- pdimm[slot].dq_mapping[10] = 0;
- pdimm[slot].dq_mapping[11] = 0;
- pdimm[slot].dq_mapping[12] = 0;
- pdimm[slot].dq_mapping[13] = 0;
- pdimm[slot].dq_mapping[14] = 0;
- pdimm[slot].dq_mapping[15] = 0;
- pdimm[slot].dq_mapping[16] = 0;
- pdimm[slot].dq_mapping[17] = 0;
- }
- /* To work at higher than 1333MT/s */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0x0; /* 32 clocks */
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- if (ddr_freq < 2350) {
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
- DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
- DDR_CDR2_VREF_RANGE_2;
- } else {
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
- DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
- DDR_CDR2_VREF_RANGE_2;
- }
-}
-
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- return fsl_ddr_sdram_size();
-#else
- puts("Initializing DDR....using SPD\n");
-
- dram_size = fsl_ddr_sdram();
-#endif
-
- return dram_size;
-}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- phys_size_t dp_ddr_size;
-#endif
-
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
- }
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
- CONFIG_DP_DDR_CTRL,
- CONFIG_DP_DDR_NUM_CTRLS,
- CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
- NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
- }
-#endif
-}
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2300, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
- {}
-};
-
-/* DP-DDR DIMM */
-static const struct board_specific_parameters udimm2[] = {
- /*
- * memory controller 2
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
- {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
- {}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
- {}
-};
-
-/* DP-DDR DIMM */
-static const struct board_specific_parameters rdimm2[] = {
- /*
- * memory controller 2
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
- udimm0,
- udimm2,
-};
-
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
- rdimm0,
- rdimm2,
-};
-
-
-#endif
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/fsl_serdes.h>
-#include <hwconfig.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <fsl-mc/ldpaa_wriop.h>
-
-#include "../common/qixis.h"
-
-#include "ls2085aqds_qixis.h"
-
-
-#ifdef CONFIG_FSL_MC_ENET
- /* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks.
- * Bank 1 -> Lanes A, B, C, D, E, F, G, H
- * Bank 2 -> Lanes A,B, C, D, E, F, G, H
- */
-
- /* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here
- * means that the mapping must be determined dynamically, or that the lane
- * maps to something other than a board slot.
- */
-
-static u8 lane_to_slot_fsm1[] = {
- 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-static u8 lane_to_slot_fsm2[] = {
- 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
- * housed.
- */
-
-static int xqsgii_riser_phy_addr[] = {
- XQSGMII_CARD_PHY1_PORT0_ADDR,
- XQSGMII_CARD_PHY2_PORT0_ADDR,
- XQSGMII_CARD_PHY3_PORT0_ADDR,
- XQSGMII_CARD_PHY4_PORT0_ADDR,
- XQSGMII_CARD_PHY3_PORT2_ADDR,
- XQSGMII_CARD_PHY1_PORT2_ADDR,
- XQSGMII_CARD_PHY4_PORT2_ADDR,
- XQSGMII_CARD_PHY2_PORT2_ADDR,
-};
-
-static int sgmii_riser_phy_addr[] = {
- SGMII_CARD_PORT1_PHY_ADDR,
- SGMII_CARD_PORT2_PHY_ADDR,
- SGMII_CARD_PORT3_PHY_ADDR,
- SGMII_CARD_PORT4_PHY_ADDR,
-};
-
-/* Slot2 does not have EMI connections */
-#define EMI_NONE 0xFFFFFFFF
-#define EMI1_SLOT1 0
-#define EMI1_SLOT2 1
-#define EMI1_SLOT3 2
-#define EMI1_SLOT4 3
-#define EMI1_SLOT5 4
-#define EMI1_SLOT6 5
-#define EMI2 6
-#define SFP_TX 0
-
-static const char * const mdio_names[] = {
- "LS2085A_QDS_MDIO0",
- "LS2085A_QDS_MDIO1",
- "LS2085A_QDS_MDIO2",
- "LS2085A_QDS_MDIO3",
- "LS2085A_QDS_MDIO4",
- "LS2085A_QDS_MDIO5",
- DEFAULT_WRIOP_MDIO2_NAME,
-};
-
-struct ls2085a_qds_mdio {
- u8 muxval;
- struct mii_dev *realbus;
-};
-
-static void sgmii_configure_repeater(int serdes_port)
-{
- struct mii_dev *bus;
- uint8_t a = 0xf;
- int i, j, ret;
- int dpmac_id = 0, dpmac, mii_bus = 0;
- unsigned short value;
- char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"};
- uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
-
- uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
- uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
-
- int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
-
- /* Set I2c to Slot 1 */
- i2c_write(0x77, 0, 0, &a, 1);
-
- for (dpmac = 0; dpmac < 8; dpmac++) {
- /* Check the PHY status */
- switch (serdes_port) {
- case 1:
- mii_bus = 0;
- dpmac_id = dpmac + 1;
- break;
- case 2:
- mii_bus = 1;
- dpmac_id = dpmac + 9;
- a = 0xb;
- i2c_write(0x76, 0, 0, &a, 1);
- break;
- }
-
- ret = miiphy_set_current_dev(dev[mii_bus]);
- if (ret > 0)
- goto error;
-
- bus = mdio_get_current_dev();
- debug("Reading from bus %s\n", bus->name);
-
- ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
- 3);
- if (ret > 0)
- goto error;
-
- mdelay(10);
- ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
- &value);
- if (ret > 0)
- goto error;
-
- mdelay(10);
-
- if ((value & 0xfff) == 0x40f) {
- printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
- continue;
- }
-
- for (i = 0; i < 4; i++) {
- for (j = 0; j < 4; j++) {
- a = 0x18;
- i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
- a = 0x38;
- i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
- a = 0x4;
- i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
-
- i2c_write(i2c_addr[dpmac], 0xf, 1,
- &ch_a_eq[i], 1);
- i2c_write(i2c_addr[dpmac], 0x11, 1,
- &ch_a_ctl2[j], 1);
-
- i2c_write(i2c_addr[dpmac], 0x16, 1,
- &ch_b_eq[i], 1);
- i2c_write(i2c_addr[dpmac], 0x18, 1,
- &ch_b_ctl2[j], 1);
-
- a = 0x14;
- i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
- a = 0xb5;
- i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
- a = 0x20;
- i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
- mdelay(100);
- ret = miiphy_read(dev[mii_bus],
- riser_phy_addr[dpmac],
- 0x11, &value);
- if (ret > 0)
- goto error;
-
- mdelay(1);
- ret = miiphy_read(dev[mii_bus],
- riser_phy_addr[dpmac],
- 0x11, &value);
- if (ret > 0)
- goto error;
- mdelay(10);
-
- if ((value & 0xfff) == 0x40f) {
- printf("DPMAC %d :PHY is configured ",
- dpmac_id);
- printf("after setting repeater 0x%x\n",
- value);
- i = 5;
- j = 5;
- } else
- printf("DPMAC %d :PHY is failed to ",
- dpmac_id);
- printf("configure the repeater 0x%x\n",
- value);
- }
- }
- }
-error:
- if (ret)
- printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
- return;
-}
-
-static void qsgmii_configure_repeater(int dpmac)
-{
- uint8_t a = 0xf;
- int i, j;
- int i2c_phy_addr = 0;
- int phy_addr = 0;
- int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
-
- uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
- uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
- uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
-
- const char *dev = "LS2085A_QDS_MDIO0";
- int ret = 0;
- unsigned short value;
-
- /* Set I2c to Slot 1 */
- i2c_write(0x77, 0, 0, &a, 1);
-
- switch (dpmac) {
- case 1:
- case 2:
- case 3:
- case 4:
- i2c_phy_addr = i2c_addr[0];
- phy_addr = 0;
- break;
-
- case 5:
- case 6:
- case 7:
- case 8:
- i2c_phy_addr = i2c_addr[1];
- phy_addr = 4;
- break;
-
- case 9:
- case 10:
- case 11:
- case 12:
- i2c_phy_addr = i2c_addr[2];
- phy_addr = 8;
- break;
-
- case 13:
- case 14:
- case 15:
- case 16:
- i2c_phy_addr = i2c_addr[3];
- phy_addr = 0xc;
- break;
- }
-
- /* Check the PHY status */
- ret = miiphy_set_current_dev(dev);
- ret = miiphy_write(dev, phy_addr, 0x1f, 3);
- mdelay(10);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- mdelay(10);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- mdelay(10);
- if ((value & 0xf) == 0xf) {
- printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
- return;
- }
-
- for (i = 0; i < 4; i++) {
- for (j = 0; j < 4; j++) {
- a = 0x18;
- i2c_write(i2c_phy_addr, 6, 1, &a, 1);
- a = 0x38;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
- a = 0x4;
- i2c_write(i2c_phy_addr, 8, 1, &a, 1);
-
- i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
-
- i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
- i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
-
- a = 0x14;
- i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
- a = 0xb5;
- i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
- a = 0x20;
- i2c_write(i2c_phy_addr, 4, 1, &a, 1);
- mdelay(100);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- if (ret > 0)
- goto error;
- mdelay(1);
- ret = miiphy_read(dev, phy_addr, 0x11, &value);
- if (ret > 0)
- goto error;
- mdelay(10);
- if ((value & 0xf) == 0xf) {
- printf("DPMAC %d :PHY is ..... Configured\n",
- dpmac);
- return;
- }
- }
- }
-error:
- printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
- return;
-}
-
-static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
-{
- return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u8 muxval)
-{
- struct mii_dev *bus;
- const char *name = ls2085a_qds_mdio_name_for_muxval(muxval);
-
- if (!name) {
- printf("No bus for muxval %x\n", muxval);
- return NULL;
- }
-
- bus = miiphy_get_dev_by_name(name);
-
- if (!bus) {
- printf("No bus by name %s\n", name);
- return NULL;
- }
-
- return bus;
-}
-
-static void ls2085a_qds_enable_SFP_TX(u8 muxval)
-{
- u8 brdcfg9;
-
- brdcfg9 = QIXIS_READ(brdcfg[9]);
- brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
- brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
- QIXIS_WRITE(brdcfg[9], brdcfg9);
-}
-
-static void ls2085a_qds_mux_mdio(u8 muxval)
-{
- u8 brdcfg4;
-
- if (muxval <= 5) {
- brdcfg4 = QIXIS_READ(brdcfg[4]);
- brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
- brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
- QIXIS_WRITE(brdcfg[4], brdcfg4);
- }
-}
-
-static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr,
- int devad, int regnum)
-{
- struct ls2085a_qds_mdio *priv = bus->priv;
-
- ls2085a_qds_mux_mdio(priv->muxval);
-
- return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
- int regnum, u16 value)
-{
- struct ls2085a_qds_mdio *priv = bus->priv;
-
- ls2085a_qds_mux_mdio(priv->muxval);
-
- return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int ls2085a_qds_mdio_reset(struct mii_dev *bus)
-{
- struct ls2085a_qds_mdio *priv = bus->priv;
-
- return priv->realbus->reset(priv->realbus);
-}
-
-static int ls2085a_qds_mdio_init(char *realbusname, u8 muxval)
-{
- struct ls2085a_qds_mdio *pmdio;
- struct mii_dev *bus = mdio_alloc();
-
- if (!bus) {
- printf("Failed to allocate ls2085a_qds MDIO bus\n");
- return -1;
- }
-
- pmdio = malloc(sizeof(*pmdio));
- if (!pmdio) {
- printf("Failed to allocate ls2085a_qds private data\n");
- free(bus);
- return -1;
- }
-
- bus->read = ls2085a_qds_mdio_read;
- bus->write = ls2085a_qds_mdio_write;
- bus->reset = ls2085a_qds_mdio_reset;
- sprintf(bus->name, ls2085a_qds_mdio_name_for_muxval(muxval));
-
- pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
- if (!pmdio->realbus) {
- printf("No bus with name %s\n", realbusname);
- free(bus);
- free(pmdio);
- return -1;
- }
-
- pmdio->muxval = muxval;
- bus->priv = pmdio;
-
- return mdio_register(bus);
-}
-
-/*
- * Initialize the dpmac_info array.
- *
- */
-static void initialize_dpmac_to_slot(void)
-{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
- int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
-
- char *env_hwconfig;
- env_hwconfig = getenv("hwconfig");
-
- switch (serdes1_prtcl) {
- case 0x07:
- case 0x09:
- case 0x33:
- printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- lane_to_slot_fsm1[0] = EMI1_SLOT1;
- lane_to_slot_fsm1[1] = EMI1_SLOT1;
- lane_to_slot_fsm1[2] = EMI1_SLOT1;
- lane_to_slot_fsm1[3] = EMI1_SLOT1;
- if (hwconfig_f("xqsgmii", env_hwconfig)) {
- lane_to_slot_fsm1[4] = EMI1_SLOT1;
- lane_to_slot_fsm1[5] = EMI1_SLOT1;
- lane_to_slot_fsm1[6] = EMI1_SLOT1;
- lane_to_slot_fsm1[7] = EMI1_SLOT1;
- } else {
- lane_to_slot_fsm1[4] = EMI1_SLOT2;
- lane_to_slot_fsm1[5] = EMI1_SLOT2;
- lane_to_slot_fsm1[6] = EMI1_SLOT2;
- lane_to_slot_fsm1[7] = EMI1_SLOT2;
- }
- break;
-
- case 0x2A:
- printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- default:
- printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
-
- switch (serdes2_prtcl) {
- case 0x07:
- case 0x08:
- case 0x09:
- case 0x49:
- printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
- lane_to_slot_fsm2[0] = EMI1_SLOT4;
- lane_to_slot_fsm2[1] = EMI1_SLOT4;
- lane_to_slot_fsm2[2] = EMI1_SLOT4;
- lane_to_slot_fsm2[3] = EMI1_SLOT4;
-
- if (hwconfig_f("xqsgmii", env_hwconfig)) {
- lane_to_slot_fsm2[4] = EMI1_SLOT4;
- lane_to_slot_fsm2[5] = EMI1_SLOT4;
- lane_to_slot_fsm2[6] = EMI1_SLOT4;
- lane_to_slot_fsm2[7] = EMI1_SLOT4;
- } else {
- /* No MDIO physical connection */
- lane_to_slot_fsm2[4] = EMI1_SLOT6;
- lane_to_slot_fsm2[5] = EMI1_SLOT6;
- lane_to_slot_fsm2[6] = EMI1_SLOT6;
- lane_to_slot_fsm2[7] = EMI1_SLOT6;
- }
- break;
- default:
- printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
- break;
- }
-}
-
-void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
-{
- int lane, slot;
- struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
- int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
-
- int *riser_phy_addr;
- char *env_hwconfig = getenv("hwconfig");
-
- if (hwconfig_f("xqsgmii", env_hwconfig))
- riser_phy_addr = &xqsgii_riser_phy_addr[0];
- else
- riser_phy_addr = &sgmii_riser_phy_addr[0];
-
- if (dpmac_id > WRIOP1_DPMAC9)
- goto serdes2;
-
- switch (serdes1_prtcl) {
- case 0x07:
-
- lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id);
- slot = lane_to_slot_fsm1[lane];
-
- switch (++slot) {
- case 1:
- /* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id,
- riser_phy_addr[dpmac_id - 1]);
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
- bus = mii_dev_for_muxval(EMI1_SLOT1);
- wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
- phy_config(dpmac_info[dpmac_id].phydev);
- break;
- case 2:
- /* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id,
- riser_phy_addr[dpmac_id - 1]);
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
- bus = mii_dev_for_muxval(EMI1_SLOT2);
- wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
- phy_config(dpmac_info[dpmac_id].phydev);
- break;
- case 3:
- break;
- case 4:
- break;
- case 5:
- break;
- case 6:
- break;
- }
- break;
- default:
- printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
-
-serdes2:
- switch (serdes2_prtcl) {
- case 0x07:
- case 0x08:
- case 0x49:
- lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
- (dpmac_id - 9));
- slot = lane_to_slot_fsm2[lane];
-
- switch (++slot) {
- case 1:
- break;
- case 3:
- break;
- case 4:
- /* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id,
- riser_phy_addr[dpmac_id - 9]);
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
- bus = mii_dev_for_muxval(EMI1_SLOT4);
- wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
- phy_config(dpmac_info[dpmac_id].phydev);
- break;
- case 5:
- break;
- case 6:
- /* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id,
- riser_phy_addr[dpmac_id - 13]);
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
- bus = mii_dev_for_muxval(EMI1_SLOT6);
- wriop_set_mdio(dpmac_id, bus);
- break;
- }
- break;
- default:
- printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
- serdes2_prtcl);
- break;
- }
-}
-
-void ls2085a_handle_phy_interface_qsgmii(int dpmac_id)
-{
- int lane = 0, slot;
- struct mii_dev *bus;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
- int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
-
- switch (serdes1_prtcl) {
- case 0x33:
- switch (dpmac_id) {
- case 1:
- case 2:
- case 3:
- case 4:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
- break;
- case 5:
- case 6:
- case 7:
- case 8:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
- break;
- case 9:
- case 10:
- case 11:
- case 12:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
- break;
- case 13:
- case 14:
- case 15:
- case 16:
- lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
- break;
- }
-
- slot = lane_to_slot_fsm1[lane];
-
- switch (++slot) {
- case 1:
- /* Slot housing a QSGMII riser card? */
- wriop_set_phy_address(dpmac_id, dpmac_id - 1);
- dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
- bus = mii_dev_for_muxval(EMI1_SLOT1);
- wriop_set_mdio(dpmac_id, bus);
- dpmac_info[dpmac_id].phydev = phy_connect(
- dpmac_info[dpmac_id].bus,
- dpmac_info[dpmac_id].phy_addr,
- NULL,
- dpmac_info[dpmac_id].enet_if);
-
- phy_config(dpmac_info[dpmac_id].phydev);
- break;
- case 3:
- break;
- case 4:
- break;
- case 5:
- break;
- case 6:
- break;
- }
- break;
- default:
- printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
-
- qsgmii_configure_repeater(dpmac_id);
-}
-
-void ls2085a_handle_phy_interface_xsgmii(int i)
-{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
- int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
-
- switch (serdes1_prtcl) {
- case 0x2A:
- /*
- * XFI does not need a PHY to work, but to avoid U-boot use
- * default PHY address which is zero to a MAC when it found
- * a MAC has no PHY address, we give a PHY address to XFI
- * MAC, and should not use a real XAUI PHY address, since
- * MDIO can access it successfully, and then MDIO thinks
- * the XAUI card is used for the XFI MAC, which will cause
- * error.
- */
- wriop_set_phy_address(i, i + 4);
- ls2085a_qds_enable_SFP_TX(SFP_TX);
-
- break;
- default:
- printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
- serdes1_prtcl);
- break;
- }
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- int error;
-#ifdef CONFIG_FSL_MC_ENET
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
- int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
- >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
-
- struct memac_mdio_info *memac_mdio0_info;
- struct memac_mdio_info *memac_mdio1_info;
- unsigned int i;
- char *env_hwconfig;
-
- env_hwconfig = getenv("hwconfig");
-
- initialize_dpmac_to_slot();
-
- memac_mdio0_info = (struct memac_mdio_info *)malloc(
- sizeof(struct memac_mdio_info));
- memac_mdio0_info->regs =
- (struct memac_mdio_controller *)
- CONFIG_SYS_FSL_WRIOP1_MDIO1;
- memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
-
- /* Register the real MDIO1 bus */
- fm_memac_mdio_init(bis, memac_mdio0_info);
-
- memac_mdio1_info = (struct memac_mdio_info *)malloc(
- sizeof(struct memac_mdio_info));
- memac_mdio1_info->regs =
- (struct memac_mdio_controller *)
- CONFIG_SYS_FSL_WRIOP1_MDIO2;
- memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
-
- /* Register the real MDIO2 bus */
- fm_memac_mdio_init(bis, memac_mdio1_info);
-
- /* Register the muxing front-ends to the MDIO buses */
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
-
- ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
-
- for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
- switch (wriop_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_QSGMII:
- ls2085a_handle_phy_interface_qsgmii(i);
- break;
- case PHY_INTERFACE_MODE_SGMII:
- ls2085a_handle_phy_interface_sgmii(i);
- break;
- case PHY_INTERFACE_MODE_XGMII:
- ls2085a_handle_phy_interface_xsgmii(i);
- break;
- default:
- break;
-
- if (i == 16)
- i = NUM_WRIOP_PORTS;
- }
- }
-
- error = cpu_eth_init(bis);
-
- if (hwconfig_f("xqsgmii", env_hwconfig)) {
- if (serdes1_prtcl == 0x7)
- sgmii_configure_repeater(1);
- if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
- serdes2_prtcl == 0x49)
- sgmii_configure_repeater(2);
- }
-#endif
- error = pci_eth_init(bis);
- return error;
-}
-
-#ifdef CONFIG_FSL_MC_ENET
-
-#endif
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <netdev.h>
-#include <fsl_ifc.h>
-#include <fsl_ddr.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <libfdt.h>
-#include <fsl_debug_server.h>
-#include <fsl-mc/fsl_mc.h>
-#include <environment.h>
-#include <i2c.h>
-#include <rtc.h>
-#include <asm/arch/soc.h>
-#include <hwconfig.h>
-
-#include "../common/qixis.h"
-#include "ls2085aqds_qixis.h"
-
-#define PIN_MUX_SEL_SDHC 0x00
-#define PIN_MUX_SEL_DSPI 0x0a
-
-#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-enum {
- MUX_TYPE_SDHC,
- MUX_TYPE_DSPI,
-};
-
-unsigned long long get_qixis_addr(void)
-{
- unsigned long long addr;
-
- if (gd->flags & GD_FLG_RELOC)
- addr = QIXIS_BASE_PHYS;
- else
- addr = QIXIS_BASE_PHYS_EARLY;
-
- /*
- * IFC address under 256MB is mapped to 0x30000000, any address above
- * is mapped to 0x5_10000000 up to 4GB.
- */
- addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
-
- return addr;
-}
-
-int checkboard(void)
-{
- char buf[64];
- u8 sw;
- static const char *const freq[] = {"100", "125", "156.25",
- "100 separate SSCG"};
- int clock;
-
- cpu_name(buf);
- printf("Board: %s-QDS, ", buf);
-
- sw = QIXIS_READ(arch);
- printf("Board Arch: V%d, ", sw >> 4);
- printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
-
- memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
-
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw == 0x8)
- puts("PromJet\n");
- else if (sw == 0x9)
- puts("NAND\n");
- else if (sw == 0x15)
- printf("IFCCard\n");
- else
- printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
- printf("FPGA: v%d (%s), build %d",
- (int)QIXIS_READ(scver), qixis_read_tag(buf),
- (int)qixis_read_minor());
- /* the timestamp string contains "\n" at the end */
- printf(" on %s", qixis_read_time(buf));
-
- /*
- * Display the actual SERDES reference clocks as configured by the
- * dip switches on the board. Note that the SWx registers could
- * technically be set to force the reference clocks to match the
- * values that the SERDES expects (or vice versa). For now, however,
- * we just display both values and hope the user notices when they
- * don't match.
- */
- puts("SERDES1 Reference : ");
- sw = QIXIS_READ(brdcfg[2]);
- clock = (sw >> 6) & 3;
- printf("Clock1 = %sMHz ", freq[clock]);
- clock = (sw >> 4) & 3;
- printf("Clock2 = %sMHz", freq[clock]);
-
- puts("\nSERDES2 Reference : ");
- clock = (sw >> 2) & 3;
- printf("Clock1 = %sMHz ", freq[clock]);
- clock = (sw >> 0) & 3;
- printf("Clock2 = %sMHz\n", freq[clock]);
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch ((ddrclk_conf & 0x30) >> 4) {
- case QIXIS_DDRCLK_100:
- return 100000000;
- case QIXIS_DDRCLK_125:
- return 125000000;
- case QIXIS_DDRCLK_133:
- return 133333333;
- }
- return 66666666;
-}
-
-int select_i2c_ch_pca9547(u8 ch)
-{
- int ret;
-
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
-int config_board_mux(int ctrl_type)
-{
- u8 reg5;
-
- reg5 = QIXIS_READ(brdcfg[5]);
-
- switch (ctrl_type) {
- case MUX_TYPE_SDHC:
- reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
- break;
- case MUX_TYPE_DSPI:
- reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
- break;
- default:
- printf("Wrong mux interface type\n");
- return -1;
- }
-
- QIXIS_WRITE(brdcfg[5], reg5);
-
- return 0;
-}
-
-int board_init(void)
-{
- char *env_hwconfig;
- u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
- u32 val;
-
- init_final_memctl_regs();
-
- val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
-
- env_hwconfig = getenv("hwconfig");
-
- if (hwconfig_f("dspi", env_hwconfig) &&
- DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
- config_board_mux(MUX_TYPE_DSPI);
- else
- config_board_mux(MUX_TYPE_SDHC);
-
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- rtc_enable_32khz_output();
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- fsl_lsch3_early_init_f();
- return 0;
-}
-
-void detail_board_ddr_info(void)
-{
- puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
- print_ddr_info(0);
- if (gd->bd->bi_dram[2].size) {
- puts("\nDP-DDR ");
- print_size(gd->bd->bi_dram[2].size, "");
- print_ddr_info(CONFIG_DP_DDR_CTRL);
- }
-}
-
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
-#ifdef CONFIG_FSL_DEBUG_SERVER
- debug_server_init();
-#endif
-
- return 0;
-}
-#endif
-
-unsigned long get_dram_size_to_hide(void)
-{
- unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
- dram_to_hide += debug_server_get_dram_block_size();
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
- dram_to_hide += mc_get_dram_block_size();
-#endif
-
- return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
-}
-
-#ifdef CONFIG_FSL_MC_ENET
-void fdt_fixup_board_enet(void *fdt)
-{
- int offset;
-
- offset = fdt_path_offset(fdt, "/fsl-mc");
-
- if (offset < 0)
- offset = fdt_path_offset(fdt, "/fsl,dprc@0");
-
- if (offset < 0) {
- printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
- __func__, offset);
- return;
- }
-
- if (get_mc_boot_status() == 0)
- fdt_status_okay(fdt, offset);
- else
- fdt_status_fail(fdt, offset);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
-
- ft_cpu_setup(blob, bd);
-
- /* fixup DT for the two GPP DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
-
- fdt_fixup_memory_banks(blob, base, size, 2);
-
-#ifdef CONFIG_FSL_MC_ENET
- fdt_fixup_board_enet(blob);
- fsl_mc_ldpaa_exit(bd);
-#endif
-
- return 0;
-}
-#endif
-
-void qixis_dump_switch(void)
-{
- int i, nr_of_cfgsw;
-
- QIXIS_WRITE(cms[0], 0x00);
- nr_of_cfgsw = QIXIS_READ(cms[1]);
-
- puts("DIP switch settings dump:\n");
- for (i = 1; i <= nr_of_cfgsw; i++) {
- QIXIS_WRITE(cms[0], i);
- printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
- }
-}
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __LS2_QDS_QIXIS_H__
-#define __LS2_QDS_QIXIS_H__
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66 0x0
-#define QIXIS_SYSCLK_83 0x1
-#define QIXIS_SYSCLK_100 0x2
-#define QIXIS_SYSCLK_125 0x3
-#define QIXIS_SYSCLK_133 0x4
-#define QIXIS_SYSCLK_150 0x5
-#define QIXIS_SYSCLK_160 0x6
-#define QIXIS_SYSCLK_166 0x7
-
-/* DDRCLK */
-#define QIXIS_DDRCLK_66 0x0
-#define QIXIS_DDRCLK_100 0x1
-#define QIXIS_DDRCLK_125 0x2
-#define QIXIS_DDRCLK_133 0x3
-
-#define BRDCFG4_EMISEL_MASK 0xE0
-#define BRDCFG4_EMISEL_SHIFT 5
-#define BRDCFG9_SFPTX_MASK 0x10
-#define BRDCFG9_SFPTX_SHIFT 4
-#endif /*__LS2_QDS_QIXIS_H__*/
+++ /dev/null
-
-if TARGET_LS2085ARDB
-
-config SYS_BOARD
- default "ls2085ardb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls2085ardb"
-
-endif
+++ /dev/null
-LS2085A BOARD
-M: Prabhakar Kushwaha <prabhakar@freescale.com>
-S: Maintained
-F: board/freescale/ls2085ardb/
-F: board/freescale/ls2085a/ls2085ardb.c
-F: include/configs/ls2085ardb.h
-F: configs/ls2085ardb_defconfig
-F: configs/ls2085ardb_nand_defconfig
+++ /dev/null
-#
-# Copyright 2015 Freescale Semiconductor
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ls2085ardb.o eth_ls2085rdb.o
-obj-y += ddr.o
+++ /dev/null
-Overview
---------
-The LS2085A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
-Layerscape Architecture processor.
-
-LS2085A SoC Overview
-------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2085A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
- the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
- - Packet parsing, classification, and distribution (WRIOP)
- - Queue and Hardware buffer management for scheduling, packet sequencing, and
- congestion management, buffer allocation and de-allocation (QBMan)
- - Cryptography acceleration (SEC) at up to 10 Gbps
- - RegEx pattern matching acceleration (PME) at up to 10 Gbps
- - Decompression/compression acceleration (DCE) at up to 20 Gbps
- - Accelerated I/O processing (AIOP) at up to 20 Gbps
- - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
- - Up to eight 10 Gbps Ethernet MACs
- - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
- - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
- - Two serial ATA (SATA 3.0) controllers
- - Two high-speed USB 3.0 controllers with integrated PHY
- - Enhanced secure digital host controller (eSDXC/eMMC)
- - Serial peripheral interface (SPI) controller
- - Quad Serial Peripheral Interface (QSPI) Controller
- - Four I2C controllers
- - Two DUARTs
- - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
- capabilities
-
- LS2085ARDB board Overview
- -----------------------
- - SERDES Connections, 16 lanes supporting:
- - PCI Express - 3.0
- - SATA 3.0
- - XFI
- - DDR Controller
- - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
- chip-selects and two DIMM connectors. Support is up to 2133MT/s.
- - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
- and two DIMM connectors. Support is up to 1600MT/s.
- -IFC/Local Bus
- - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
- - 128 MB NOR flash 16-bit data bus
- - One 2 GB NAND flash with ECC support
- - CPLD connection
- - USB 3.0
- - Two high speed USB 3.0 ports
- - First USB 3.0 port configured as Host with Type-A connector
- - Second USB 3.0 port configured as OTG with micro-AB connector
- - SDHC adapter
- - SD Card Rev 2.0 and Rev 3.0
- - DSPI
- - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)
- - 4 I2C controllers
- - Two SATA onboard connectors
- - UART
- - ARM JTAG support
-
-Memory map from core's view
-----------------------------
-0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
-0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
-0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
-0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
-0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
-0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
-0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
-
-Other addresses are either reserved, or not used directly by u-boot.
-This list should be updated when more addresses are used.
-
-IFC region map from core's view
--------------------------------
-During boot i.e. IFC Region #1:-
- 0x30000000 - 0x37ffffff : 128MB : NOR flash
- 0x3C000000 - 0x40000000 : 64MB : CPLD
-
-After relocate to DDR i.e. IFC Region #2:-
- 0x5_1000_0000..0x5_1fff_ffff Memory Hole
- 0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB)
- 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
- 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
- 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
-
-Booting Options
----------------
-a) NOR boot
-b) NAND boot
-
-Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
--------------------------------------------------------------------
-One needs to use appropriate bootargs to boot Linux flavors which do
-not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
-below:
-
-=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
- earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
- hugepages=16 mem=2048M'
-
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
- int slot;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
-
- for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
- if (pdimm[slot].n_ranks)
- break;
- }
-
- if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
- return;
-
- /*
- * we use identical timing for all slots. If needed, change the code
- * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
- */
- if (popts->registered_dimm_en)
- pbsp = rdimms[ctrl_num];
- else
- pbsp = udimms[ctrl_num];
-
-
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm[slot].n_ranks &&
- (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for data rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- if (ctrl_num == CONFIG_DP_DDR_CTRL) {
- /* force DDR bus width to 32 bits */
- popts->data_bus_width = 1;
- popts->otf_burst_chop_en = 0;
- popts->burst_length = DDR_BL8;
- popts->bstopre = 0; /* enable auto precharge */
- /*
- * Layout optimization results byte mapping
- * Byte 0 -> Byte ECC
- * Byte 1 -> Byte 3
- * Byte 2 -> Byte 2
- * Byte 3 -> Byte 1
- * Byte ECC -> Byte 0
- */
- dq_mapping_0 = pdimm[slot].dq_mapping[0];
- dq_mapping_2 = pdimm[slot].dq_mapping[2];
- dq_mapping_3 = pdimm[slot].dq_mapping[3];
- pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
- pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
- pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
- pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
- pdimm[slot].dq_mapping[6] = dq_mapping_2;
- pdimm[slot].dq_mapping[7] = dq_mapping_3;
- pdimm[slot].dq_mapping[8] = dq_mapping_0;
- pdimm[slot].dq_mapping[9] = 0;
- pdimm[slot].dq_mapping[10] = 0;
- pdimm[slot].dq_mapping[11] = 0;
- pdimm[slot].dq_mapping[12] = 0;
- pdimm[slot].dq_mapping[13] = 0;
- pdimm[slot].dq_mapping[14] = 0;
- pdimm[slot].dq_mapping[15] = 0;
- pdimm[slot].dq_mapping[16] = 0;
- pdimm[slot].dq_mapping[17] = 0;
- }
- /* To work at higher than 1333MT/s */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0x0; /* 32 clocks */
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- if (ddr_freq < 2350) {
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
- DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
- DDR_CDR2_VREF_RANGE_2;
- } else {
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
- DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
- DDR_CDR2_VREF_RANGE_2;
- }
-}
-
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size;
-
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
- return fsl_ddr_sdram_size();
-#else
- puts("Initializing DDR....using SPD\n");
-
- dram_size = fsl_ddr_sdram();
-#endif
-
- return dram_size;
-}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- phys_size_t dp_ddr_size;
-#endif
-
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
- gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
- gd->bd->bi_dram[1].size = gd->ram_size -
- CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
- } else {
- gd->bd->bi_dram[0].size = gd->ram_size;
- }
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
- /* initialize DP-DDR here */
- puts("DP-DDR: ");
- /*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
- dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
- CONFIG_DP_DDR_CTRL,
- CONFIG_DP_DDR_NUM_CTRLS,
- CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
- NULL, NULL, NULL);
- if (dp_ddr_size) {
- gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
- gd->bd->bi_dram[2].size = dp_ddr_size;
- } else {
- puts("Not detected");
- }
-#endif
-}
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,},
- {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,},
- {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,},
- {}
-};
-
-/* DP-DDR DIMM */
-static const struct board_specific_parameters udimm2[] = {
- /*
- * memory controller 2
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,},
- {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
- {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,},
- {}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
- {}
-};
-
-/* DP-DDR DIMM */
-static const struct board_specific_parameters rdimm2[] = {
- /*
- * memory controller 2
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
- {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
- {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,},
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
- udimm0,
- udimm2,
-};
-
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
- rdimm0,
- rdimm2,
-};
-
-
-#endif
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fm_eth.h>
-#include <asm/io.h>
-#include <exports.h>
-#include <asm/arch/fsl_serdes.h>
-#include <fsl-mc/ldpaa_wriop.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int load_firmware_cortina(struct phy_device *phy_dev)
-{
- if (phy_dev->drv->config)
- return phy_dev->drv->config(phy_dev);
-
- return 0;
-}
-
-void load_phy_firmware(void)
-{
- int i;
- u8 phy_addr;
- struct phy_device *phy_dev;
- struct mii_dev *dev;
- phy_interface_t interface;
-
- /*Initialize and upload firmware for all the PHYs*/
- for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
- interface = wriop_get_enet_if(i);
- if (interface == PHY_INTERFACE_MODE_XGMII) {
- dev = wriop_get_mdio(i);
- phy_addr = wriop_get_phy_address(i);
- phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
- interface);
- if (!phy_dev) {
- printf("No phydev for phyaddr %d\n", phy_addr);
- continue;
- }
-
- /*Flash firmware for All CS4340 PHYS */
- if (phy_dev->phy_id == PHY_UID_CS4340)
- load_firmware_cortina(phy_dev);
- }
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_FSL_MC_ENET)
- int i, interface;
- struct memac_mdio_info mdio_info;
- struct mii_dev *dev;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- u32 srds_s1;
- struct memac_mdio_controller *reg;
-
- srds_s1 = in_le32(&gur->rcwsr[28]) &
- FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
-
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
- mdio_info.regs = reg;
- mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
-
- /* Register the EMI 1 */
- fm_memac_mdio_init(bis, &mdio_info);
-
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
- mdio_info.regs = reg;
- mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
-
- /* Register the EMI 2 */
- fm_memac_mdio_init(bis, &mdio_info);
-
- switch (srds_s1) {
- case 0x2A:
- wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
- wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
- wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
- wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
- wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
- wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
-
- break;
- default:
- printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
- srds_s1);
- break;
- }
-
- for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
- interface = wriop_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
- wriop_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
- switch (wriop_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
- wriop_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- /* Load CORTINA CS4340 PHY firmware */
- load_phy_firmware();
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
-#ifdef CONFIG_PHY_AQUANTIA
- /*
- * Export functions to be used by AQ firmware
- * upload application
- */
- gd->jt->strcpy = strcpy;
- gd->jt->mdelay = mdelay;
- gd->jt->mdio_get_current_dev = mdio_get_current_dev;
- gd->jt->phy_find_by_mask = phy_find_by_mask;
- gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
- gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
-#endif
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <netdev.h>
-#include <fsl_ifc.h>
-#include <fsl_ddr.h>
-#include <asm/io.h>
-#include <hwconfig.h>
-#include <fdt_support.h>
-#include <libfdt.h>
-#include <fsl_debug_server.h>
-#include <fsl-mc/fsl_mc.h>
-#include <environment.h>
-#include <i2c.h>
-#include <asm/arch/soc.h>
-
-#include "../common/qixis.h"
-#include "ls2085ardb_qixis.h"
-
-#define PIN_MUX_SEL_SDHC 0x00
-#define PIN_MUX_SEL_DSPI 0x0a
-
-#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
-DECLARE_GLOBAL_DATA_PTR;
-
-enum {
- MUX_TYPE_SDHC,
- MUX_TYPE_DSPI,
-};
-
-unsigned long long get_qixis_addr(void)
-{
- unsigned long long addr;
-
- if (gd->flags & GD_FLG_RELOC)
- addr = QIXIS_BASE_PHYS;
- else
- addr = QIXIS_BASE_PHYS_EARLY;
-
- /*
- * IFC address under 256MB is mapped to 0x30000000, any address above
- * is mapped to 0x5_10000000 up to 4GB.
- */
- addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
-
- return addr;
-}
-
-int checkboard(void)
-{
- u8 sw;
- char buf[15];
-
- cpu_name(buf);
- printf("Board: %s-RDB, ", buf);
-
- sw = QIXIS_READ(arch);
- printf("Board Arch: V%d, ", sw >> 4);
- printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
-
- sw = QIXIS_READ(brdcfg[0]);
- sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- printf("vBank: %d\n", sw);
- else if (sw == 0x9)
- puts("NAND\n");
- else
- printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
-
- printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
-
- puts("SERDES1 Reference : ");
- printf("Clock1 = 156.25MHz ");
- printf("Clock2 = 156.25MHz");
-
- puts("\nSERDES2 Reference : ");
- printf("Clock1 = 100MHz ");
- printf("Clock2 = 100MHz\n");
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
-
- switch (sysclk_conf & 0x0F) {
- case QIXIS_SYSCLK_83:
- return 83333333;
- case QIXIS_SYSCLK_100:
- return 100000000;
- case QIXIS_SYSCLK_125:
- return 125000000;
- case QIXIS_SYSCLK_133:
- return 133333333;
- case QIXIS_SYSCLK_150:
- return 150000000;
- case QIXIS_SYSCLK_160:
- return 160000000;
- case QIXIS_SYSCLK_166:
- return 166666666;
- }
- return 66666666;
-}
-
-int select_i2c_ch_pca9547(u8 ch)
-{
- int ret;
-
- ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
- if (ret) {
- puts("PCA: failed to select proper channel\n");
- return ret;
- }
-
- return 0;
-}
-
-int config_board_mux(int ctrl_type)
-{
- u8 reg5;
-
- reg5 = QIXIS_READ(brdcfg[5]);
-
- switch (ctrl_type) {
- case MUX_TYPE_SDHC:
- reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
- break;
- case MUX_TYPE_DSPI:
- reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
- break;
- default:
- printf("Wrong mux interface type\n");
- return -1;
- }
-
- QIXIS_WRITE(brdcfg[5], reg5);
-
- return 0;
-}
-
-int board_init(void)
-{
- char *env_hwconfig;
- u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
- u32 val;
-
- init_final_memctl_regs();
-
- val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
-
- env_hwconfig = getenv("hwconfig");
-
- if (hwconfig_f("dspi", env_hwconfig) &&
- DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
- config_board_mux(MUX_TYPE_DSPI);
- else
- config_board_mux(MUX_TYPE_SDHC);
-
-#ifdef CONFIG_ENV_IS_NOWHERE
- gd->env_addr = (ulong)&default_environment[0];
-#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-
- QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- fsl_lsch3_early_init_f();
- return 0;
-}
-
-int misc_init_r(void)
-{
- if (hwconfig("sdhc"))
- config_board_mux(MUX_TYPE_SDHC);
-
- return 0;
-}
-
-void detail_board_ddr_info(void)
-{
- puts("\nDDR ");
- print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
- print_ddr_info(0);
- if (gd->bd->bi_dram[2].size) {
- puts("\nDP-DDR ");
- print_size(gd->bd->bi_dram[2].size, "");
- print_ddr_info(CONFIG_DP_DDR_CTRL);
- }
-}
-
-int dram_init(void)
-{
- gd->ram_size = initdram(0);
-
- return 0;
-}
-
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
-#ifdef CONFIG_FSL_DEBUG_SERVER
- debug_server_init();
-#endif
-
- return 0;
-}
-#endif
-
-unsigned long get_dram_size_to_hide(void)
-{
- unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
- dram_to_hide += debug_server_get_dram_block_size();
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
- dram_to_hide += mc_get_dram_block_size();
-#endif
-
- return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
-}
-
-#ifdef CONFIG_FSL_MC_ENET
-void fdt_fixup_board_enet(void *fdt)
-{
- int offset;
-
- offset = fdt_path_offset(fdt, "/fsl-mc");
-
- if (offset < 0)
- offset = fdt_path_offset(fdt, "/fsl,dprc@0");
-
- if (offset < 0) {
- printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
- __func__, offset);
- return;
- }
-
- if (get_mc_boot_status() == 0)
- fdt_status_okay(fdt, offset);
- else
- fdt_status_fail(fdt, offset);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
-
- ft_cpu_setup(blob, bd);
-
- /* fixup DT for the two GPP DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
-
- fdt_fixup_memory_banks(blob, base, size, 2);
-
-#ifdef CONFIG_FSL_MC_ENET
- fdt_fixup_board_enet(blob);
- fsl_mc_ldpaa_exit(bd);
-#endif
-
- return 0;
-}
-#endif
-
-void qixis_dump_switch(void)
-{
- int i, nr_of_cfgsw;
-
- QIXIS_WRITE(cms[0], 0x00);
- nr_of_cfgsw = QIXIS_READ(cms[1]);
-
- puts("DIP switch settings dump:\n");
- for (i = 1; i <= nr_of_cfgsw; i++) {
- QIXIS_WRITE(cms[0], i);
- printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
- }
-}
-
-/*
- * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
- * Both slots has 0x54, resulting 2nd slot unusable.
- */
-void update_spd_address(unsigned int ctrl_num,
- unsigned int slot,
- unsigned int *addr)
-{
- u8 sw;
-
- sw = QIXIS_READ(arch);
- if ((sw & 0xf) < 0x3) {
- if (ctrl_num == 1 && slot == 0)
- *addr = SPD_EEPROM_ADDRESS4;
- else if (ctrl_num == 1 && slot == 1)
- *addr = SPD_EEPROM_ADDRESS3;
- }
-}
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __LS2_RDB_QIXIS_H__
-#define __LS2_RDB_QIXIS_H__
-
-/* SYSCLK */
-#define QIXIS_SYSCLK_66 0x0
-#define QIXIS_SYSCLK_83 0x1
-#define QIXIS_SYSCLK_100 0x2
-#define QIXIS_SYSCLK_125 0x3
-#define QIXIS_SYSCLK_133 0x4
-#define QIXIS_SYSCLK_150 0x5
-#define QIXIS_SYSCLK_160 0x6
-#define QIXIS_SYSCLK_166 0x7
-
-#endif /*__LS2_RDB_QIXIS_H__*/
};
U_BOOT_DEVICE(igep_uart) = {
- "serial_omap",
+ "ns16550_serial",
&igep_serial
};
};
U_BOOT_DEVICE(sniper_serial) = {
- .name = "serial_omap",
+ .name = "ns16550_serial",
.platdata = &serial_omap_platdata
};
--- /dev/null
+if TARGET_LWMON5
+
+config SYS_BOARD
+ default "lwmon5"
+
+config SYS_VENDOR
+ default "liebherr"
+
+config SYS_CONFIG_NAME
+ default "lwmon5"
+
+config DISPLAY_BOARDINFO
+ bool
+ default y
+
+endif
--- /dev/null
+LWMON5 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/liebherr/lwmon5/
+F: include/configs/lwmon5.h
+F: configs/lwmon5_defconfig
--- /dev/null
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = lwmon5.o kbd.o sdram.o
+extra-y += init.o
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# lwmon5 (440EPx)
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
+
+ /* TLB-entry for the FPGA Chip select 2 */
+ tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
+
+ /* TLB-entry for the FPGA Chip select 3 */
+ tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
+
+ /* TLB-entry for the LIME Controller */
+ tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I)
+
+ /*TLB-entry PCI registers*/
+ tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG)
+
+ /* TLB-entry for peripherals */
+ tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+ tlbtab_end
--- /dev/null
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2001, 2002
+ * DENX Software Engineering
+ * Wolfgang Denk, wd@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <i2c.h>
+#include <command.h>
+#include <console.h>
+#include <post.h>
+#include <serial.h>
+#include <malloc.h>
+
+#include <linux/types.h>
+#include <linux/string.h> /* for strdup */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void kbd_init (void);
+static int compare_magic (uchar *kbd_data, uchar *str);
+
+/*--------------------- Local macros and constants --------------------*/
+#define _NOT_USED_ 0xFFFFFFFF
+
+/*------------------------- dspic io expander -----------------------*/
+#define DSPIC_PON_STATUS_REG 0x80A
+#define DSPIC_PON_INV_STATUS_REG 0x80C
+#define DSPIC_PON_KEY_REG 0x810
+/*------------------------- Keyboard controller -----------------------*/
+/* command codes */
+#define KEYBD_CMD_READ_KEYS 0x01
+#define KEYBD_CMD_READ_VERSION 0x02
+#define KEYBD_CMD_READ_STATUS 0x03
+#define KEYBD_CMD_RESET_ERRORS 0x10
+
+/* status codes */
+#define KEYBD_STATUS_MASK 0x3F
+#define KEYBD_STATUS_H_RESET 0x20
+#define KEYBD_STATUS_BROWNOUT 0x10
+#define KEYBD_STATUS_WD_RESET 0x08
+#define KEYBD_STATUS_OVERLOAD 0x04
+#define KEYBD_STATUS_ILLEGAL_WR 0x02
+#define KEYBD_STATUS_ILLEGAL_RD 0x01
+
+/* Number of bytes returned from Keyboard Controller */
+#define KEYBD_VERSIONLEN 2 /* version information */
+
+/*
+ * This is different from the "old" lwmon dsPIC kbd controller
+ * implementation. Now the controller still answers with 9 bytes,
+ * but the last 3 bytes are always "0x06 0x07 0x08". So we just
+ * set the length to compare to 6 instead of 9.
+ */
+#define KEYBD_DATALEN 6 /* normal key scan data */
+
+/* maximum number of "magic" key codes that can be assigned */
+
+static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
+static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
+
+static uchar *key_match (uchar *);
+
+#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */
+
+/***********************************************************************
+F* Function: int board_postclk_init (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: int
+P* - 0 is always returned.
+ *
+Z* Intention: This function is the board_postclk_init() method implementation
+Z* for the lwmon board.
+ *
+ ***********************************************************************/
+int board_postclk_init (void)
+{
+ kbd_init();
+
+ return (0);
+}
+
+static void kbd_init (void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ uchar tmp_data[KEYBD_DATALEN];
+ uchar val, errcd;
+ int i;
+
+ i2c_set_bus_num(0);
+
+ gd->arch.kbd_status = 0;
+
+ /* Forced by PIC. Delays <= 175us loose */
+ udelay(1000);
+
+ /* Read initial keyboard error code */
+ val = KEYBD_CMD_READ_STATUS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, &errcd, 1);
+ /* clear unused bits */
+ errcd &= KEYBD_STATUS_MASK;
+ /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
+ errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
+ if (errcd) {
+ gd->arch.kbd_status |= errcd << 8;
+ }
+ /* Reset error code and verify */
+ val = KEYBD_CMD_RESET_ERRORS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ udelay(1000); /* delay NEEDED by keyboard PIC !!! */
+
+ val = KEYBD_CMD_READ_STATUS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, &val, 1);
+
+ val &= KEYBD_STATUS_MASK; /* clear unused bits */
+ if (val) { /* permanent error, report it */
+ gd->arch.kbd_status |= val;
+ return;
+ }
+
+ /*
+ * Read current keyboard state.
+ *
+ * After the error reset it may take some time before the
+ * keyboard PIC picks up a valid keyboard scan - the total
+ * scan time is approx. 1.6 ms (information by Martin Rajek,
+ * 28 Sep 2002). We read a couple of times for the keyboard
+ * to stabilize, using a big enough delay.
+ * 10 times should be enough. If the data is still changing,
+ * we use what we get :-(
+ */
+
+ memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */
+ for (i=0; i<10; ++i) {
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
+ /* consistent state, done */
+ break;
+ }
+ /* remeber last state, delay, and retry */
+ memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
+ udelay (5000);
+ }
+}
+
+
+/* Read a register from the dsPIC. */
+int _dspic_read(ushort reg, ushort *data)
+{
+ uchar buf[sizeof(*data)];
+ int rval;
+
+ if (i2c_read(dspic_addr, reg, 2, buf, 2))
+ return -1;
+
+ rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
+ *data = (buf[0] << 8) | buf[1];
+
+ return rval;
+}
+
+
+/***********************************************************************
+F* Function: int misc_init_r (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: int
+P* - 0 is always returned, even in the case of a keyboard
+P* error.
+ *
+Z* Intention: This function is the misc_init_r() method implementation
+Z* for the lwmon board.
+Z* The keyboard controller is initialized and the result
+Z* of a read copied to the environment variable "keybd".
+Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for
+Z* this key, and if found display to the LCD will be enabled.
+Z* The keys in "keybd" are checked against the magic
+Z* keycommands defined in the environment.
+Z* See also key_match().
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int misc_init_r_kbd (void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ uchar kbd_init_status = gd->arch.kbd_status >> 8;
+ uchar kbd_status = gd->arch.kbd_status;
+ uchar val;
+ ushort data, inv_data;
+ char *str;
+ int i;
+
+ if (kbd_init_status) {
+ printf ("KEYBD: Error %02X\n", kbd_init_status);
+ }
+ if (kbd_status) { /* permanent error, report it */
+ printf ("*** Keyboard error code %02X ***\n", kbd_status);
+ sprintf (keybd_env, "%02X", kbd_status);
+ setenv ("keybd", keybd_env);
+ return 0;
+ }
+
+ /*
+ * Now we know that we have a working keyboard, so disable
+ * all output to the LCD except when a key press is detected.
+ */
+
+ if ((console_assign (stdout, "serial") < 0) ||
+ (console_assign (stderr, "serial") < 0)) {
+ printf ("Can't assign serial port as output device\n");
+ }
+
+ /* Read Version */
+ val = KEYBD_CMD_READ_VERSION;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
+ printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
+
+ /* Read current keyboard state */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ /* read out start key from bse01 received via can */
+ _dspic_read(DSPIC_PON_STATUS_REG, &data);
+ /* check highbyte from status register */
+ if (data > 0xFF) {
+ _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
+
+ /* check inverse data */
+ if ((data+inv_data) == 0xFFFF) {
+ /* don't overwrite local key */
+ if (kbd_data[1] == 0) {
+ /* read key value */
+ _dspic_read(DSPIC_PON_KEY_REG, &data);
+ str = (char *)&data;
+ /* swap bytes */
+ kbd_data[1] = str[1];
+ kbd_data[2] = str[0];
+ printf("CAN received startkey: 0x%X\n", data);
+ }
+ }
+ }
+
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ }
+
+ setenv ("keybd", keybd_env);
+
+ str = strdup ((char *)key_match (kbd_data)); /* decode keys */
+#ifdef KEYBD_SET_DEBUGMODE
+ if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
+ if ((console_assign (stdout, "lcd") < 0) ||
+ (console_assign (stderr, "lcd") < 0)) {
+ printf ("Can't assign LCD display as output device\n");
+ }
+ }
+#endif /* KEYBD_SET_DEBUGMODE */
+#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
+ setenv ("preboot", str); /* set or delete definition */
+#endif /* CONFIG_PREBOOT */
+ if (str != NULL) {
+ free (str);
+ }
+ return (0);
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+static int compare_magic (uchar *kbd_data, uchar *str)
+{
+ uchar compare[KEYBD_DATALEN-1];
+ char *nxt;
+ int i;
+
+ /* Don't include modifier byte */
+ memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
+
+ for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
+ uchar c;
+ int k;
+
+ c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
+
+ if (str == (uchar *)nxt) { /* invalid character */
+ break;
+ }
+
+ /*
+ * Check if this key matches the input.
+ * Set matches to zero, so they match only once
+ * and we can find duplicates or extra keys
+ */
+ for (k = 0; k < sizeof(compare); ++k) {
+ if (compare[k] == '\0') /* only non-zero entries */
+ continue;
+ if (c == compare[k]) { /* found matching key */
+ compare[k] = '\0';
+ break;
+ }
+ }
+ if (k == sizeof(compare)) {
+ return -1; /* unmatched key */
+ }
+ }
+
+ /*
+ * A full match leaves no keys in the `compare' array,
+ */
+ for (i = 0; i < sizeof(compare); ++i) {
+ if (compare[i])
+ {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/***********************************************************************
+F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z*
+ *
+P* Parameters: uchar *kbd_data
+P* - The keys to match against our magic definitions
+P*
+P* Returnvalue: uchar *
+P* - != NULL: Pointer to the corresponding command(s)
+P* NULL: No magic is about to happen
+ *
+Z* Intention: Check if pressed key(s) match magic sequence,
+Z* and return the command string associated with that key(s).
+Z*
+Z* If no key press was decoded, NULL is returned.
+Z*
+Z* Note: the first character of the argument will be
+Z* overwritten with the "magic charcter code" of the
+Z* decoded key(s), or '\0'.
+Z*
+Z* Note: the string points to static environment data
+Z* and must be saved before you call any function that
+Z* modifies the environment.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+static uchar *key_match (uchar *kbd_data)
+{
+ char magic[sizeof (kbd_magic_prefix) + 1];
+ uchar *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can pe appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
+ sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+ debug ("### Check magic \"%s\"\n", magic);
+ if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
+ char cmd_name[sizeof (kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+
+ cmd = getenv (cmd_name);
+ debug ("### Set PREBOOT to $(%s): \"%s\"\n",
+ cmd_name, cmd ? cmd : "<<NULL>>");
+ *kbd_data = *suffix;
+ return ((uchar *)cmd);
+ }
+ }
+ debug ("### Delete PREBOOT\n");
+ *kbd_data = '\0';
+ return (NULL);
+}
+#endif /* CONFIG_PREBOOT */
+
+/***********************************************************************
+F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag,
+F* int argc, char * const argv[]) P*A*Z*
+ *
+P* Parameters: cmd_tbl_t *cmdtp
+P* - Pointer to our command table entry
+P* int flag
+P* - If the CMD_FLAG_REPEAT bit is set, then this call is
+P* a repetition
+P* int argc
+P* - Argument count
+P* char * const argv[]
+P* - Array of the actual arguments
+P*
+P* Returnvalue: int
+P* - 0 is always returned.
+ *
+Z* Intention: Implement the "kbd" command.
+Z* The keyboard status is read. The result is printed on
+Z* the console and written into the "keybd" environment
+Z* variable.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ uchar val;
+ int i;
+
+#if 0 /* Done in kbd_init */
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+ /* Read keys */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ puts ("Keys:");
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ printf (" %02x", kbd_data[i]);
+ }
+ putc ('\n');
+ setenv ("keybd", keybd_env);
+ return 0;
+}
+
+U_BOOT_CMD(
+ kbd, 1, 1, do_kbd,
+ "read keyboard status",
+ ""
+);
+
+/*----------------------------- Utilities -----------------------------*/
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ uchar val;
+
+ /* Read keys */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2007-2013
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/ppc440.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/io.h>
+#include <post.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
+
+ulong flash_get_size(ulong base, int banknum);
+int misc_init_r_kbd(void);
+
+int board_early_init_f(void)
+{
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 reg;
+
+ /* PLB Write pipelining disabled. Denali Core workaround */
+ mtdcr(PLB4A0_ACR, 0xDE000000);
+ mtdcr(PLB4A1_ACR, 0xDE000000);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
+ mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
+ mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
+ mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
+ mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ /* Trace Pins are disabled. SDR0_PFC0 Register */
+ mtsdr(SDR0_PFC0, 0x0);
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ /* SMII via ZMII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_6;
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_6;
+
+ /* enable SPI (SCP) */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
+
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ mtsdr(SDR0_PFC4, 0x80000000);
+
+ /* PCI arbiter disabled */
+ /* PCI Host Configuration disbaled */
+ mfsdr(SDR0_PCI0, reg);
+ reg = 0;
+ mtsdr(SDR0_PCI0, 0x00000000 | reg);
+
+ gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
+
+#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
+ /* enable the LSB transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
+ /* enable the CAN transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
+
+ reg = 0; /* reuse as counter */
+ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+ in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
+ & ~CONFIG_SYS_DSPIC_TEST_MASK);
+ while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
+ udelay(1000);
+ }
+ if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
+ /* set "boot error" flag */
+ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+ in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
+ CONFIG_SYS_DSPIC_TEST_MASK);
+ }
+#endif
+
+ /*
+ * Reset PHY's:
+ * The PHY's need a 2nd reset pulse, since the MDIO address is latched
+ * upon reset, and with the first reset upon powerup, the addresses are
+ * not latched reliable, since the IRQ line is multiplexed with an
+ * MDIO address. A 2nd reset at this time will make sure, that the
+ * correct address is latched.
+ */
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
+ udelay(1000);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
+ udelay(1000);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
+
+ return 0;
+}
+
+/*
+ * Override weak default with board specific version
+ */
+phys_addr_t cfi_flash_bank_addr(int bank)
+{
+ return lwmon5_cfi_flash_bank_addr[bank];
+}
+
+/*
+ * Override the weak default mapping function with a board specific one
+ */
+u32 flash_get_bank_size(int cs, int idx)
+{
+ return flash_info[idx].size;
+}
+
+int board_early_init_r(void)
+{
+ u32 val0, val1;
+
+ /*
+ * lwmon5 is manufactured in 2 different board versions:
+ * The lwmon5a board has 64MiB NOR flash instead of the
+ * 128MiB of the original lwmon5. Unfortunately the CFI driver
+ * will report 2 banks of 64MiB even for the smaller flash
+ * chip, since the bank is mirrored. To fix this, we bring
+ * one bank into CFI query mode and read its response. This
+ * enables us to detect the real number of flash devices/
+ * banks which will be used later on by the common CFI driver.
+ */
+
+ /* Put bank 0 into CFI command mode and read */
+ out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
+ val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
+ val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
+
+ /* Reset flash again out of query mode */
+ out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
+
+ /* When not identical, we have 2 different flash devices/banks */
+ if (val0 != val1)
+ return 0;
+
+ /*
+ * Now we're sure that we're running on a LWMON5a board with
+ * only 64MiB NOR flash in one bank:
+ *
+ * Set flash base address and bank count for CFI driver probing.
+ */
+ cfi_flash_num_flash_banks = 1;
+ lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u32 pbcr;
+ int size_val = 0;
+ u32 reg;
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1, sdr0_srst;
+
+ /*
+ * FLASH stuff...
+ */
+
+ /* Re-do sizing to get full correct info */
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ mfebc(PB0CR, pbcr);
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtebc(PB0CR, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /* Monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
+ &flash_info[cfi_flash_num_flash_banks - 1]);
+
+ /* Env protection ON by default */
+ flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[cfi_flash_num_flash_banks - 1]);
+
+ /*
+ * USB suff...
+ */
+
+ /* Reset USB */
+ /* Reset of USB2PHY0 must be active at least 10 us */
+ mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
+ udelay(2000);
+
+ mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
+ SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
+ SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
+ udelay(2000);
+
+ /* Errata CHIP_6 */
+
+ /* 1. Set internal PHY configuration */
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+
+ /*
+ * An 8-bit/60MHz interface is the only possible alternative
+ * when connecting the Device to the PHY
+ */
+ usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /* 2. De-assert internal PHY reset */
+ mfsdr(SDR0_SRST1, sdr0_srst);
+ sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
+ mtsdr(SDR0_SRST1, sdr0_srst);
+
+ /* 3. Wait for more than 1 ms */
+ udelay(2000);
+
+ /* 4. De-assert USB 2.0 Host main reset */
+ mfsdr(SDR0_SRST0, sdr0_srst);
+ sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
+ mtsdr(SDR0_SRST0, sdr0_srst);
+ udelay(1000);
+
+ /* 5. De-assert reset of OPB2 cores */
+ mfsdr(SDR0_SRST1, sdr0_srst);
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
+ mtsdr(SDR0_SRST1, sdr0_srst);
+ udelay(1000);
+
+ /* 6. Set EHCI Configure FLAG */
+
+ /* 7. Reassert internal PHY reset: */
+ mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
+ udelay(1000);
+
+ /*
+ * Clear resets
+ */
+ mtsdr(SDR0_SRST1, 0x00000000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy) Device(ext phy)\n");
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+ mtdcr(PLB4A0_ACR, reg);
+
+ /*
+ * Init matrix keyboard
+ */
+ misc_init_r_kbd();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: %s", __stringify(CONFIG_HOSTNAME));
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+void hw_watchdog_reset(void)
+{
+ int val;
+#if defined(CONFIG_WD_MAX_RATE)
+ unsigned long long ct = get_ticks();
+
+ /*
+ * Don't allow watch-dog triggering more frequently than
+ * the predefined value CONFIG_WD_MAX_RATE [ticks].
+ */
+ if (ct >= gd->arch.wdt_last) {
+ if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
+ return;
+ } else {
+ /* Time base counter had been reset */
+ if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
+ CONFIG_WD_MAX_RATE)
+ return;
+ }
+ gd->arch.wdt_last = get_ticks();
+#endif
+
+ /*
+ * Toggle watchdog output
+ */
+ val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
+ gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
+}
+
+int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ if ((strcmp(argv[1], "on") == 0))
+ gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
+ else if ((strcmp(argv[1], "off") == 0))
+ gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
+ else
+ return cmd_usage(cmdtp);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ eepromwp, 2, 0, do_eeprom_wp,
+ "eeprom write protect off/on",
+ "<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
+);
+
+#if defined(CONFIG_VIDEO)
+#include <video_fb.h>
+#include <mb862xx.h>
+
+extern GraphicDevice mb862xx;
+
+static const gdc_regs init_regs [] = {
+ { 0x0100, 0x00000f00 },
+ { 0x0020, 0x801401df },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x00000000 },
+ { 0x002c, 0x00000000 },
+ { 0x0110, 0x00000000 },
+ { 0x0114, 0x00000000 },
+ { 0x0118, 0x01df0280 },
+ { 0x0004, 0x031f0000 },
+ { 0x0008, 0x027f027f },
+ { 0x000c, 0x015f028f },
+ { 0x0010, 0x020c0000 },
+ { 0x0014, 0x01df01ea },
+ { 0x0018, 0x00000000 },
+ { 0x001c, 0x01e00280 },
+ { 0x0100, 0x80010f00 },
+ { 0x0, 0x0 }
+};
+
+const gdc_regs *board_get_regs(void)
+{
+ return init_regs;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init(void)
+{
+ /*
+ * Reset Lime controller
+ */
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
+ udelay(500);
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
+
+ mb862xx.winSizeX = 640;
+ mb862xx.winSizeY = 480;
+ mb862xx.gdfBytesPP = 2;
+ mb862xx.gdfIndex = GDF_15BIT_555RGB;
+
+ return CONFIG_SYS_LIME_BASE_0;
+}
+
+#define DEFAULT_BRIGHTNESS 0x64
+
+static void board_backlight_brightness(int brightness)
+{
+ if (brightness > 0) {
+ /* pwm duty, lamp on */
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
+ } else {
+ /* lamp off */
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
+ }
+}
+
+void board_backlight_switch(int flag)
+{
+ char * param;
+ int rc;
+
+ if (flag) {
+ param = getenv("brightness");
+ rc = param ? simple_strtol(param, NULL, 10) : -1;
+ if (rc < 0)
+ rc = DEFAULT_BRIGHTNESS;
+ } else {
+ rc = 0;
+ }
+ board_backlight_brightness(rc);
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str(int line_number, char *info)
+{
+ if (line_number == 1)
+ strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
+ else
+ info [0] = '\0';
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+#endif /* CONFIG_VIDEO */
+
+void board_reset(void)
+{
+ gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * lwmon5 specific implementation of spl_start_uboot()
+ *
+ * RETURN
+ * 0 if booting into OS is selected (default)
+ * 1 if booting into U-Boot is selected
+ */
+int spl_start_uboot(void)
+{
+ char s[8];
+
+ env_init();
+ getenv_f("boot_os", s, sizeof(s));
+ if ((s != NULL) && (strcmp(s, "yes") == 0))
+ return 0;
+
+ return 1;
+}
+
+/*
+ * This function is called from the SPL U-Boot version for
+ * early init stuff, that needs to be done for OS (e.g. Linux)
+ * booting. Doing it later in the real U-Boot would not work
+ * in case that the SPL U-Boot boots Linux directly.
+ */
+void spl_board_init(void)
+{
+ const gdc_regs *regs = board_get_regs();
+
+ /*
+ * Setup PFC registers, mainly for ethernet support
+ * later on in Linux
+ */
+ board_early_init_f();
+
+ /* enable the LSB transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
+
+ /*
+ * Clear resets
+ */
+ mtsdr(SDR0_SRST1, 0x00000000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ /*
+ * Reset Lime controller
+ */
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
+ udelay(500);
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
+
+ out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
+ udelay(300);
+ out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
+
+ while (regs->index) {
+ out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
+ regs->index, regs->value);
+ regs++;
+ }
+
+ board_backlight_brightness(DEFAULT_BRIGHTNESS);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2007-2013
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/ppc440.h>
+#include <watchdog.h>
+
+/*
+ * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
+ * region. Right now the cache should still be disabled in U-Boot because of the
+ * EMAC driver, that need it's buffer descriptor to be located in non cached
+ * memory.
+ *
+ * If at some time this restriction doesn't apply anymore, just define
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
+ * everything correctly.
+ */
+#ifdef CONFIG_4xx_DCACHE
+#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
+#else
+#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
+#endif
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes
+ *-----------------------------------------------------------------------------*/
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+extern void dcbz_area(u32 start_address, u32 num_bytes);
+
+static u32 is_ecc_enabled(void)
+{
+ u32 val;
+
+ mfsdram(DDR0_22, val);
+ val &= DDR0_22_CTRL_RAW_MASK;
+ if (val)
+ return 1;
+ else
+ return 0;
+}
+
+void board_add_ram_info(int use_default)
+{
+ PPC4xx_SYS_INFO board_cfg;
+ u32 val;
+
+ if (is_ecc_enabled())
+ puts(" (ECC");
+ else
+ puts(" (ECC not");
+
+ get_sys_info(&board_cfg);
+ printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
+
+ mfsdram(DDR0_03, val);
+ val = DDR0_03_CASLAT_DECODE(val);
+ printf(", CL%d)", val);
+}
+
+#ifdef CONFIG_DDR_ECC
+static void wait_ddr_idle(void)
+{
+ /*
+ * Controller idle status cannot be determined for Denali
+ * DDR2 code. Just return here.
+ */
+}
+
+static void program_ecc(u32 start_address,
+ u32 num_bytes,
+ u32 tlb_word2_i_value)
+{
+ u32 val;
+ u32 current_addr = start_address;
+ u32 size;
+ int bytes_remaining;
+
+ sync();
+ wait_ddr_idle();
+
+ /*
+ * Because of 440EPx errata CHIP 11, we don't touch the last 256
+ * bytes of SDRAM.
+ */
+ bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
+
+ /*
+ * We have to write the ECC bytes by zeroing and flushing in smaller
+ * steps, since the whole 256MByte takes too long for the external
+ * watchdog.
+ */
+ while (bytes_remaining > 0) {
+ size = min((64 << 20), bytes_remaining);
+
+ /* Write zero's to SDRAM */
+ dcbz_area(current_addr, size);
+
+ /* Write modified dcache lines back to memory */
+ clean_dcache_range(current_addr, current_addr + size);
+
+ current_addr += 64 << 20;
+ bytes_remaining -= 64 << 20;
+ WATCHDOG_RESET();
+ }
+
+ sync();
+ wait_ddr_idle();
+
+ /* Clear error status */
+ mfsdram(DDR0_00, val);
+ mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
+
+ /* Set 'int_mask' parameter to functionnal value */
+ mfsdram(DDR0_01, val);
+ mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
+
+ sync();
+ wait_ddr_idle();
+}
+#endif
+
+/*************************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+phys_size_t initdram (int board_type)
+{
+ /* CL=4 */
+ mtsdram(DDR0_02, 0x00000000);
+
+ mtsdram(DDR0_00, 0x0000190A);
+ mtsdram(DDR0_01, 0x01000000);
+ mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
+
+ mtsdram(DDR0_04, 0x0B030300);
+ mtsdram(DDR0_05, 0x02020308);
+ mtsdram(DDR0_06, 0x0003C812);
+ mtsdram(DDR0_07, 0x00090100);
+ mtsdram(DDR0_08, 0x03c80001);
+ mtsdram(DDR0_09, 0x00011D5F);
+ mtsdram(DDR0_10, 0x00000100);
+ mtsdram(DDR0_11, 0x000CC800);
+ mtsdram(DDR0_12, 0x00000003);
+ mtsdram(DDR0_14, 0x00000000);
+ mtsdram(DDR0_17, 0x1e000000);
+ mtsdram(DDR0_18, 0x1e1e1e1e);
+ mtsdram(DDR0_19, 0x1e1e1e1e);
+ mtsdram(DDR0_20, 0x0B0B0B0B);
+ mtsdram(DDR0_21, 0x0B0B0B0B);
+#ifdef CONFIG_DDR_ECC
+ mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
+#else
+ mtsdram(DDR0_22, 0x00267F0B);
+#endif
+
+ mtsdram(DDR0_23, 0x01000000);
+ mtsdram(DDR0_24, 0x01010001);
+
+ mtsdram(DDR0_26, 0x2D93028A);
+ mtsdram(DDR0_27, 0x0784682B);
+
+ mtsdram(DDR0_28, 0x00000080);
+ mtsdram(DDR0_31, 0x00000000);
+ mtsdram(DDR0_42, 0x01000008);
+
+ mtsdram(DDR0_43, 0x050A0200);
+ mtsdram(DDR0_44, 0x00000005);
+ mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+
+ denali_wait_for_dlllock();
+
+#if defined(CONFIG_DDR_DATA_EYE)
+ /* -----------------------------------------------------------+
+ * Perform data eye search if requested.
+ * ----------------------------------------------------------*/
+ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
+ TLB_WORD2_I_ENABLE);
+ denali_core_search_data_eye();
+ remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
+#endif
+
+ /*
+ * Program tlb entries for this size (dynamic)
+ */
+ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
+ MY_TLB_WORD2_I_ENABLE);
+
+#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_4xx_DCACHE)
+ /*
+ * If ECC is enabled, initialize the parity bits.
+ */
+ program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+#else /* CONFIG_4xx_DCACHE */
+ /*
+ * Setup 2nd TLB with same physical address but different virtual address
+ * with cache enabled. This is done for fast ECC generation.
+ */
+ program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+
+ /*
+ * If ECC is enabled, initialize the parity bits.
+ */
+ program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+
+ /*
+ * Now after initialization (auto-calibration and ECC generation)
+ * remove the TLB entries with caches enabled and program again with
+ * desired cache functionality
+ */
+ remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
+#endif /* CONFIG_4xx_DCACHE */
+#endif /* CONFIG_DDR_ECC */
+
+ /*
+ * Clear possible errors resulting from data-eye-search.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ return (CONFIG_SYS_MBYTES_SDRAM << 20);
+}
};
U_BOOT_DEVICE(omap3logic_uart) = {
- "serial_omap",
+ "ns16550_serial",
&omap3logic_serial
};
};
U_BOOT_DEVICE(zoom1_uart) = {
- "serial_omap",
+ "ns16550_serial",
&zoom1_serial
};
+++ /dev/null
-if TARGET_LWMON5
-
-config SYS_BOARD
- default "lwmon5"
-
-config SYS_CONFIG_NAME
- default "lwmon5"
-
-config DISPLAY_BOARDINFO
- bool
- default y
-
-endif
+++ /dev/null
-LWMON5 BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: board/lwmon5/
-F: include/configs/lwmon5.h
-F: configs/lwmon5_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = lwmon5.o kbd.o sdram.o
-extra-y += init.o
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# lwmon5 (440EPx)
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
-
- /*
- * TLB entries for SDRAM are not needed on this platform.
- * They are dynamically generated in the SPD DDR(2) detection
- * routine.
- */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-#endif
-
- /* TLB-entry for PCI Memory */
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
-
- /* TLB-entry for the FPGA Chip select 2 */
- tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
-
- /* TLB-entry for the FPGA Chip select 3 */
- tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
-
- /* TLB-entry for the LIME Controller */
- tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
-
- /* TLB-entry for Internal Registers & OCM */
- tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I)
-
- /*TLB-entry PCI registers*/
- tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG)
-
- /* TLB-entry for peripherals */
- tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
- tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2001, 2002
- * DENX Software Engineering
- * Wolfgang Denk, wd@denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <i2c.h>
-#include <command.h>
-#include <console.h>
-#include <post.h>
-#include <serial.h>
-#include <malloc.h>
-
-#include <linux/types.h>
-#include <linux/string.h> /* for strdup */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void kbd_init (void);
-static int compare_magic (uchar *kbd_data, uchar *str);
-
-/*--------------------- Local macros and constants --------------------*/
-#define _NOT_USED_ 0xFFFFFFFF
-
-/*------------------------- dspic io expander -----------------------*/
-#define DSPIC_PON_STATUS_REG 0x80A
-#define DSPIC_PON_INV_STATUS_REG 0x80C
-#define DSPIC_PON_KEY_REG 0x810
-/*------------------------- Keyboard controller -----------------------*/
-/* command codes */
-#define KEYBD_CMD_READ_KEYS 0x01
-#define KEYBD_CMD_READ_VERSION 0x02
-#define KEYBD_CMD_READ_STATUS 0x03
-#define KEYBD_CMD_RESET_ERRORS 0x10
-
-/* status codes */
-#define KEYBD_STATUS_MASK 0x3F
-#define KEYBD_STATUS_H_RESET 0x20
-#define KEYBD_STATUS_BROWNOUT 0x10
-#define KEYBD_STATUS_WD_RESET 0x08
-#define KEYBD_STATUS_OVERLOAD 0x04
-#define KEYBD_STATUS_ILLEGAL_WR 0x02
-#define KEYBD_STATUS_ILLEGAL_RD 0x01
-
-/* Number of bytes returned from Keyboard Controller */
-#define KEYBD_VERSIONLEN 2 /* version information */
-
-/*
- * This is different from the "old" lwmon dsPIC kbd controller
- * implementation. Now the controller still answers with 9 bytes,
- * but the last 3 bytes are always "0x06 0x07 0x08". So we just
- * set the length to compare to 6 instead of 9.
- */
-#define KEYBD_DATALEN 6 /* normal key scan data */
-
-/* maximum number of "magic" key codes that can be assigned */
-
-static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
-static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
-
-static uchar *key_match (uchar *);
-
-#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */
-
-/***********************************************************************
-F* Function: int board_postclk_init (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: int
-P* - 0 is always returned.
- *
-Z* Intention: This function is the board_postclk_init() method implementation
-Z* for the lwmon board.
- *
- ***********************************************************************/
-int board_postclk_init (void)
-{
- kbd_init();
-
- return (0);
-}
-
-static void kbd_init (void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- uchar tmp_data[KEYBD_DATALEN];
- uchar val, errcd;
- int i;
-
- i2c_set_bus_num(0);
-
- gd->arch.kbd_status = 0;
-
- /* Forced by PIC. Delays <= 175us loose */
- udelay(1000);
-
- /* Read initial keyboard error code */
- val = KEYBD_CMD_READ_STATUS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, &errcd, 1);
- /* clear unused bits */
- errcd &= KEYBD_STATUS_MASK;
- /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
- errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
- if (errcd) {
- gd->arch.kbd_status |= errcd << 8;
- }
- /* Reset error code and verify */
- val = KEYBD_CMD_RESET_ERRORS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- udelay(1000); /* delay NEEDED by keyboard PIC !!! */
-
- val = KEYBD_CMD_READ_STATUS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, &val, 1);
-
- val &= KEYBD_STATUS_MASK; /* clear unused bits */
- if (val) { /* permanent error, report it */
- gd->arch.kbd_status |= val;
- return;
- }
-
- /*
- * Read current keyboard state.
- *
- * After the error reset it may take some time before the
- * keyboard PIC picks up a valid keyboard scan - the total
- * scan time is approx. 1.6 ms (information by Martin Rajek,
- * 28 Sep 2002). We read a couple of times for the keyboard
- * to stabilize, using a big enough delay.
- * 10 times should be enough. If the data is still changing,
- * we use what we get :-(
- */
-
- memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */
- for (i=0; i<10; ++i) {
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
- /* consistent state, done */
- break;
- }
- /* remeber last state, delay, and retry */
- memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
- udelay (5000);
- }
-}
-
-
-/* Read a register from the dsPIC. */
-int _dspic_read(ushort reg, ushort *data)
-{
- uchar buf[sizeof(*data)];
- int rval;
-
- if (i2c_read(dspic_addr, reg, 2, buf, 2))
- return -1;
-
- rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
- *data = (buf[0] << 8) | buf[1];
-
- return rval;
-}
-
-
-/***********************************************************************
-F* Function: int misc_init_r (void) P*A*Z*
- *
-P* Parameters: none
-P*
-P* Returnvalue: int
-P* - 0 is always returned, even in the case of a keyboard
-P* error.
- *
-Z* Intention: This function is the misc_init_r() method implementation
-Z* for the lwmon board.
-Z* The keyboard controller is initialized and the result
-Z* of a read copied to the environment variable "keybd".
-Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for
-Z* this key, and if found display to the LCD will be enabled.
-Z* The keys in "keybd" are checked against the magic
-Z* keycommands defined in the environment.
-Z* See also key_match().
- *
-D* Design: wd@denx.de
-C* Coding: wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int misc_init_r_kbd (void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- uchar kbd_init_status = gd->arch.kbd_status >> 8;
- uchar kbd_status = gd->arch.kbd_status;
- uchar val;
- ushort data, inv_data;
- char *str;
- int i;
-
- if (kbd_init_status) {
- printf ("KEYBD: Error %02X\n", kbd_init_status);
- }
- if (kbd_status) { /* permanent error, report it */
- printf ("*** Keyboard error code %02X ***\n", kbd_status);
- sprintf (keybd_env, "%02X", kbd_status);
- setenv ("keybd", keybd_env);
- return 0;
- }
-
- /*
- * Now we know that we have a working keyboard, so disable
- * all output to the LCD except when a key press is detected.
- */
-
- if ((console_assign (stdout, "serial") < 0) ||
- (console_assign (stderr, "serial") < 0)) {
- printf ("Can't assign serial port as output device\n");
- }
-
- /* Read Version */
- val = KEYBD_CMD_READ_VERSION;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
- printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
-
- /* Read current keyboard state */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- /* read out start key from bse01 received via can */
- _dspic_read(DSPIC_PON_STATUS_REG, &data);
- /* check highbyte from status register */
- if (data > 0xFF) {
- _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
-
- /* check inverse data */
- if ((data+inv_data) == 0xFFFF) {
- /* don't overwrite local key */
- if (kbd_data[1] == 0) {
- /* read key value */
- _dspic_read(DSPIC_PON_KEY_REG, &data);
- str = (char *)&data;
- /* swap bytes */
- kbd_data[1] = str[1];
- kbd_data[2] = str[0];
- printf("CAN received startkey: 0x%X\n", data);
- }
- }
- }
-
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- }
-
- setenv ("keybd", keybd_env);
-
- str = strdup ((char *)key_match (kbd_data)); /* decode keys */
-#ifdef KEYBD_SET_DEBUGMODE
- if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
- if ((console_assign (stdout, "lcd") < 0) ||
- (console_assign (stderr, "lcd") < 0)) {
- printf ("Can't assign LCD display as output device\n");
- }
- }
-#endif /* KEYBD_SET_DEBUGMODE */
-#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
- setenv ("preboot", str); /* set or delete definition */
-#endif /* CONFIG_PREBOOT */
- if (str != NULL) {
- free (str);
- }
- return (0);
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
- uchar compare[KEYBD_DATALEN-1];
- char *nxt;
- int i;
-
- /* Don't include modifier byte */
- memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
-
- for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
- uchar c;
- int k;
-
- c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
- if (str == (uchar *)nxt) { /* invalid character */
- break;
- }
-
- /*
- * Check if this key matches the input.
- * Set matches to zero, so they match only once
- * and we can find duplicates or extra keys
- */
- for (k = 0; k < sizeof(compare); ++k) {
- if (compare[k] == '\0') /* only non-zero entries */
- continue;
- if (c == compare[k]) { /* found matching key */
- compare[k] = '\0';
- break;
- }
- }
- if (k == sizeof(compare)) {
- return -1; /* unmatched key */
- }
- }
-
- /*
- * A full match leaves no keys in the `compare' array,
- */
- for (i = 0; i < sizeof(compare); ++i) {
- if (compare[i])
- {
- return -1;
- }
- }
-
- return 0;
-}
-
-/***********************************************************************
-F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z*
- *
-P* Parameters: uchar *kbd_data
-P* - The keys to match against our magic definitions
-P*
-P* Returnvalue: uchar *
-P* - != NULL: Pointer to the corresponding command(s)
-P* NULL: No magic is about to happen
- *
-Z* Intention: Check if pressed key(s) match magic sequence,
-Z* and return the command string associated with that key(s).
-Z*
-Z* If no key press was decoded, NULL is returned.
-Z*
-Z* Note: the first character of the argument will be
-Z* overwritten with the "magic charcter code" of the
-Z* decoded key(s), or '\0'.
-Z*
-Z* Note: the string points to static environment data
-Z* and must be saved before you call any function that
-Z* modifies the environment.
- *
-D* Design: wd@denx.de
-C* Coding: wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-static uchar *key_match (uchar *kbd_data)
-{
- char magic[sizeof (kbd_magic_prefix) + 1];
- uchar *suffix;
- char *kbd_magic_keys;
-
- /*
- * The following string defines the characters that can pe appended
- * to "key_magic" to form the names of environment variables that
- * hold "magic" key codes, i. e. such key codes that can cause
- * pre-boot actions. If the string is empty (""), then only
- * "key_magic" is checked (old behaviour); the string "125" causes
- * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
- */
- if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
- kbd_magic_keys = "";
-
- /* loop over all magic keys;
- * use '\0' suffix in case of empty string
- */
- for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
- sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
- debug ("### Check magic \"%s\"\n", magic);
- if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
- char cmd_name[sizeof (kbd_command_prefix) + 1];
- char *cmd;
-
- sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
- cmd = getenv (cmd_name);
- debug ("### Set PREBOOT to $(%s): \"%s\"\n",
- cmd_name, cmd ? cmd : "<<NULL>>");
- *kbd_data = *suffix;
- return ((uchar *)cmd);
- }
- }
- debug ("### Delete PREBOOT\n");
- *kbd_data = '\0';
- return (NULL);
-}
-#endif /* CONFIG_PREBOOT */
-
-/***********************************************************************
-F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag,
-F* int argc, char * const argv[]) P*A*Z*
- *
-P* Parameters: cmd_tbl_t *cmdtp
-P* - Pointer to our command table entry
-P* int flag
-P* - If the CMD_FLAG_REPEAT bit is set, then this call is
-P* a repetition
-P* int argc
-P* - Argument count
-P* char * const argv[]
-P* - Array of the actual arguments
-P*
-P* Returnvalue: int
-P* - 0 is always returned.
- *
-Z* Intention: Implement the "kbd" command.
-Z* The keyboard status is read. The result is printed on
-Z* the console and written into the "keybd" environment
-Z* variable.
- *
-D* Design: wd@denx.de
-C* Coding: wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uchar kbd_data[KEYBD_DATALEN];
- char keybd_env[2 * KEYBD_DATALEN + 1];
- uchar val;
- int i;
-
-#if 0 /* Done in kbd_init */
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
- /* Read keys */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- puts ("Keys:");
- for (i = 0; i < KEYBD_DATALEN; ++i) {
- sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
- printf (" %02x", kbd_data[i]);
- }
- putc ('\n');
- setenv ("keybd", keybd_env);
- return 0;
-}
-
-U_BOOT_CMD(
- kbd, 1, 1, do_kbd,
- "read keyboard status",
- ""
-);
-
-/*----------------------------- Utilities -----------------------------*/
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- uchar kbd_data[KEYBD_DATALEN];
- uchar val;
-
- /* Read keys */
- val = KEYBD_CMD_READ_KEYS;
- i2c_write (kbd_addr, 0, 0, &val, 1);
- i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
- return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/ppc440.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <post.h>
-#include <flash.h>
-#include <mtd/cfi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
-
-ulong flash_get_size(ulong base, int banknum);
-int misc_init_r_kbd(void);
-
-int board_early_init_f(void)
-{
- u32 sdr0_pfc1, sdr0_pfc2;
- u32 reg;
-
- /* PLB Write pipelining disabled. Denali Core workaround */
- mtdcr(PLB4A0_ACR, 0xDE000000);
- mtdcr(PLB4A1_ACR, 0xDE000000);
-
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
- mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
- mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
- mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
- mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- /* Trace Pins are disabled. SDR0_PFC0 Register */
- mtsdr(SDR0_PFC0, 0x0);
-
- /* select Ethernet pins */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- /* SMII via ZMII */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
- SDR0_PFC1_SELECT_CONFIG_6;
- mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
- SDR0_PFC2_SELECT_CONFIG_6;
-
- /* enable SPI (SCP) */
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
-
- mtsdr(SDR0_PFC2, sdr0_pfc2);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- mtsdr(SDR0_PFC4, 0x80000000);
-
- /* PCI arbiter disabled */
- /* PCI Host Configuration disbaled */
- mfsdr(SDR0_PCI0, reg);
- reg = 0;
- mtsdr(SDR0_PCI0, 0x00000000 | reg);
-
- gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
- /* enable the LSB transmitter */
- gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
- /* enable the CAN transmitter */
- gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
-
- reg = 0; /* reuse as counter */
- out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
- in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
- & ~CONFIG_SYS_DSPIC_TEST_MASK);
- while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
- udelay(1000);
- }
- if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
- /* set "boot error" flag */
- out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
- in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
- CONFIG_SYS_DSPIC_TEST_MASK);
- }
-#endif
-
- /*
- * Reset PHY's:
- * The PHY's need a 2nd reset pulse, since the MDIO address is latched
- * upon reset, and with the first reset upon powerup, the addresses are
- * not latched reliable, since the IRQ line is multiplexed with an
- * MDIO address. A 2nd reset at this time will make sure, that the
- * correct address is latched.
- */
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
- udelay(1000);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
- udelay(1000);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
-
- return 0;
-}
-
-/*
- * Override weak default with board specific version
- */
-phys_addr_t cfi_flash_bank_addr(int bank)
-{
- return lwmon5_cfi_flash_bank_addr[bank];
-}
-
-/*
- * Override the weak default mapping function with a board specific one
- */
-u32 flash_get_bank_size(int cs, int idx)
-{
- return flash_info[idx].size;
-}
-
-int board_early_init_r(void)
-{
- u32 val0, val1;
-
- /*
- * lwmon5 is manufactured in 2 different board versions:
- * The lwmon5a board has 64MiB NOR flash instead of the
- * 128MiB of the original lwmon5. Unfortunately the CFI driver
- * will report 2 banks of 64MiB even for the smaller flash
- * chip, since the bank is mirrored. To fix this, we bring
- * one bank into CFI query mode and read its response. This
- * enables us to detect the real number of flash devices/
- * banks which will be used later on by the common CFI driver.
- */
-
- /* Put bank 0 into CFI command mode and read */
- out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
- val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
- val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
-
- /* Reset flash again out of query mode */
- out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
-
- /* When not identical, we have 2 different flash devices/banks */
- if (val0 != val1)
- return 0;
-
- /*
- * Now we're sure that we're running on a LWMON5a board with
- * only 64MiB NOR flash in one bank:
- *
- * Set flash base address and bank count for CFI driver probing.
- */
- cfi_flash_num_flash_banks = 1;
- lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- u32 pbcr;
- int size_val = 0;
- u32 reg;
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1, sdr0_srst;
-
- /*
- * FLASH stuff...
- */
-
- /* Re-do sizing to get full correct info */
-
- /* adjust flash start and offset */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- mfebc(PB0CR, pbcr);
- size_val = ffs(gd->bd->bi_flashsize) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtebc(PB0CR, pbcr);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, 0);
-
- /* Monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
- &flash_info[cfi_flash_num_flash_banks - 1]);
-
- /* Env protection ON by default */
- flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[cfi_flash_num_flash_banks - 1]);
-
- /*
- * USB suff...
- */
-
- /* Reset USB */
- /* Reset of USB2PHY0 must be active at least 10 us */
- mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
- udelay(2000);
-
- mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
- SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
- SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
- udelay(2000);
-
- /* Errata CHIP_6 */
-
- /* 1. Set internal PHY configuration */
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB0, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
- usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
-
- /*
- * An 8-bit/60MHz interface is the only possible alternative
- * when connecting the Device to the PHY
- */
- usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB0, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /* 2. De-assert internal PHY reset */
- mfsdr(SDR0_SRST1, sdr0_srst);
- sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
- mtsdr(SDR0_SRST1, sdr0_srst);
-
- /* 3. Wait for more than 1 ms */
- udelay(2000);
-
- /* 4. De-assert USB 2.0 Host main reset */
- mfsdr(SDR0_SRST0, sdr0_srst);
- sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
- mtsdr(SDR0_SRST0, sdr0_srst);
- udelay(1000);
-
- /* 5. De-assert reset of OPB2 cores */
- mfsdr(SDR0_SRST1, sdr0_srst);
- sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
- sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
- sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
- mtsdr(SDR0_SRST1, sdr0_srst);
- udelay(1000);
-
- /* 6. Set EHCI Configure FLAG */
-
- /* 7. Reassert internal PHY reset: */
- mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
- udelay(1000);
-
- /*
- * Clear resets
- */
- mtsdr(SDR0_SRST1, 0x00000000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Host(int phy) Device(ext phy)\n");
-
- /*
- * Clear PLB4A0_ACR[WRP]
- * This fix will make the MAL burst disabling patch for the Linux
- * EMAC driver obsolete.
- */
- reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
- mtdcr(PLB4A0_ACR, reg);
-
- /*
- * Init matrix keyboard
- */
- misc_init_r_kbd();
-
- return 0;
-}
-
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- printf("Board: %s", __stringify(CONFIG_HOSTNAME));
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-void hw_watchdog_reset(void)
-{
- int val;
-#if defined(CONFIG_WD_MAX_RATE)
- unsigned long long ct = get_ticks();
-
- /*
- * Don't allow watch-dog triggering more frequently than
- * the predefined value CONFIG_WD_MAX_RATE [ticks].
- */
- if (ct >= gd->arch.wdt_last) {
- if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
- return;
- } else {
- /* Time base counter had been reset */
- if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
- CONFIG_WD_MAX_RATE)
- return;
- }
- gd->arch.wdt_last = get_ticks();
-#endif
-
- /*
- * Toggle watchdog output
- */
- val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
- gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
-}
-
-int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc < 2)
- return cmd_usage(cmdtp);
-
- if ((strcmp(argv[1], "on") == 0))
- gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
- else if ((strcmp(argv[1], "off") == 0))
- gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
- else
- return cmd_usage(cmdtp);
-
- return 0;
-}
-
-U_BOOT_CMD(
- eepromwp, 2, 0, do_eeprom_wp,
- "eeprom write protect off/on",
- "<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
-);
-
-#if defined(CONFIG_VIDEO)
-#include <video_fb.h>
-#include <mb862xx.h>
-
-extern GraphicDevice mb862xx;
-
-static const gdc_regs init_regs [] = {
- { 0x0100, 0x00000f00 },
- { 0x0020, 0x801401df },
- { 0x0024, 0x00000000 },
- { 0x0028, 0x00000000 },
- { 0x002c, 0x00000000 },
- { 0x0110, 0x00000000 },
- { 0x0114, 0x00000000 },
- { 0x0118, 0x01df0280 },
- { 0x0004, 0x031f0000 },
- { 0x0008, 0x027f027f },
- { 0x000c, 0x015f028f },
- { 0x0010, 0x020c0000 },
- { 0x0014, 0x01df01ea },
- { 0x0018, 0x00000000 },
- { 0x001c, 0x01e00280 },
- { 0x0100, 0x80010f00 },
- { 0x0, 0x0 }
-};
-
-const gdc_regs *board_get_regs(void)
-{
- return init_regs;
-}
-
-/* Returns Lime base address */
-unsigned int board_video_init(void)
-{
- /*
- * Reset Lime controller
- */
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
- udelay(500);
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
- mb862xx.winSizeX = 640;
- mb862xx.winSizeY = 480;
- mb862xx.gdfBytesPP = 2;
- mb862xx.gdfIndex = GDF_15BIT_555RGB;
-
- return CONFIG_SYS_LIME_BASE_0;
-}
-
-#define DEFAULT_BRIGHTNESS 0x64
-
-static void board_backlight_brightness(int brightness)
-{
- if (brightness > 0) {
- /* pwm duty, lamp on */
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
- } else {
- /* lamp off */
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
- out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
- }
-}
-
-void board_backlight_switch(int flag)
-{
- char * param;
- int rc;
-
- if (flag) {
- param = getenv("brightness");
- rc = param ? simple_strtol(param, NULL, 10) : -1;
- if (rc < 0)
- rc = DEFAULT_BRIGHTNESS;
- } else {
- rc = 0;
- }
- board_backlight_brightness(rc);
-}
-
-#if defined(CONFIG_CONSOLE_EXTRA_INFO)
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str(int line_number, char *info)
-{
- if (line_number == 1)
- strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
- else
- info [0] = '\0';
-}
-#endif /* CONFIG_CONSOLE_EXTRA_INFO */
-#endif /* CONFIG_VIDEO */
-
-void board_reset(void)
-{
- gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * lwmon5 specific implementation of spl_start_uboot()
- *
- * RETURN
- * 0 if booting into OS is selected (default)
- * 1 if booting into U-Boot is selected
- */
-int spl_start_uboot(void)
-{
- char s[8];
-
- env_init();
- getenv_f("boot_os", s, sizeof(s));
- if ((s != NULL) && (strcmp(s, "yes") == 0))
- return 0;
-
- return 1;
-}
-
-/*
- * This function is called from the SPL U-Boot version for
- * early init stuff, that needs to be done for OS (e.g. Linux)
- * booting. Doing it later in the real U-Boot would not work
- * in case that the SPL U-Boot boots Linux directly.
- */
-void spl_board_init(void)
-{
- const gdc_regs *regs = board_get_regs();
-
- /*
- * Setup PFC registers, mainly for ethernet support
- * later on in Linux
- */
- board_early_init_f();
-
- /* enable the LSB transmitter */
- gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
-
- /*
- * Clear resets
- */
- mtsdr(SDR0_SRST1, 0x00000000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- /*
- * Reset Lime controller
- */
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
- udelay(500);
- gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
- out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
- udelay(300);
- out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
-
- while (regs->index) {
- out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
- regs->index, regs->value);
- regs++;
- }
-
- board_backlight_brightness(DEFAULT_BRIGHTNESS);
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/ppc440.h>
-#include <watchdog.h>
-
-/*
- * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
- * region. Right now the cache should still be disabled in U-Boot because of the
- * EMAC driver, that need it's buffer descriptor to be located in non cached
- * memory.
- *
- * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_4xx_DCACHE in the board config file and this code should setup
- * everything correctly.
- */
-#ifdef CONFIG_4xx_DCACHE
-#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
-#else
-#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Prototypes
- *-----------------------------------------------------------------------------*/
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-extern void dcbz_area(u32 start_address, u32 num_bytes);
-
-static u32 is_ecc_enabled(void)
-{
- u32 val;
-
- mfsdram(DDR0_22, val);
- val &= DDR0_22_CTRL_RAW_MASK;
- if (val)
- return 1;
- else
- return 0;
-}
-
-void board_add_ram_info(int use_default)
-{
- PPC4xx_SYS_INFO board_cfg;
- u32 val;
-
- if (is_ecc_enabled())
- puts(" (ECC");
- else
- puts(" (ECC not");
-
- get_sys_info(&board_cfg);
- printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
-
- mfsdram(DDR0_03, val);
- val = DDR0_03_CASLAT_DECODE(val);
- printf(", CL%d)", val);
-}
-
-#ifdef CONFIG_DDR_ECC
-static void wait_ddr_idle(void)
-{
- /*
- * Controller idle status cannot be determined for Denali
- * DDR2 code. Just return here.
- */
-}
-
-static void program_ecc(u32 start_address,
- u32 num_bytes,
- u32 tlb_word2_i_value)
-{
- u32 val;
- u32 current_addr = start_address;
- u32 size;
- int bytes_remaining;
-
- sync();
- wait_ddr_idle();
-
- /*
- * Because of 440EPx errata CHIP 11, we don't touch the last 256
- * bytes of SDRAM.
- */
- bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
-
- /*
- * We have to write the ECC bytes by zeroing and flushing in smaller
- * steps, since the whole 256MByte takes too long for the external
- * watchdog.
- */
- while (bytes_remaining > 0) {
- size = min((64 << 20), bytes_remaining);
-
- /* Write zero's to SDRAM */
- dcbz_area(current_addr, size);
-
- /* Write modified dcache lines back to memory */
- clean_dcache_range(current_addr, current_addr + size);
-
- current_addr += 64 << 20;
- bytes_remaining -= 64 << 20;
- WATCHDOG_RESET();
- }
-
- sync();
- wait_ddr_idle();
-
- /* Clear error status */
- mfsdram(DDR0_00, val);
- mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
-
- /* Set 'int_mask' parameter to functionnal value */
- mfsdram(DDR0_01, val);
- mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
-
- sync();
- wait_ddr_idle();
-}
-#endif
-
-/*************************************************************************
- *
- * initdram -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-phys_size_t initdram (int board_type)
-{
- /* CL=4 */
- mtsdram(DDR0_02, 0x00000000);
-
- mtsdram(DDR0_00, 0x0000190A);
- mtsdram(DDR0_01, 0x01000000);
- mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
-
- mtsdram(DDR0_04, 0x0B030300);
- mtsdram(DDR0_05, 0x02020308);
- mtsdram(DDR0_06, 0x0003C812);
- mtsdram(DDR0_07, 0x00090100);
- mtsdram(DDR0_08, 0x03c80001);
- mtsdram(DDR0_09, 0x00011D5F);
- mtsdram(DDR0_10, 0x00000100);
- mtsdram(DDR0_11, 0x000CC800);
- mtsdram(DDR0_12, 0x00000003);
- mtsdram(DDR0_14, 0x00000000);
- mtsdram(DDR0_17, 0x1e000000);
- mtsdram(DDR0_18, 0x1e1e1e1e);
- mtsdram(DDR0_19, 0x1e1e1e1e);
- mtsdram(DDR0_20, 0x0B0B0B0B);
- mtsdram(DDR0_21, 0x0B0B0B0B);
-#ifdef CONFIG_DDR_ECC
- mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
-#else
- mtsdram(DDR0_22, 0x00267F0B);
-#endif
-
- mtsdram(DDR0_23, 0x01000000);
- mtsdram(DDR0_24, 0x01010001);
-
- mtsdram(DDR0_26, 0x2D93028A);
- mtsdram(DDR0_27, 0x0784682B);
-
- mtsdram(DDR0_28, 0x00000080);
- mtsdram(DDR0_31, 0x00000000);
- mtsdram(DDR0_42, 0x01000008);
-
- mtsdram(DDR0_43, 0x050A0200);
- mtsdram(DDR0_44, 0x00000005);
- mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
-
- denali_wait_for_dlllock();
-
-#if defined(CONFIG_DDR_DATA_EYE)
- /* -----------------------------------------------------------+
- * Perform data eye search if requested.
- * ----------------------------------------------------------*/
- program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
- TLB_WORD2_I_ENABLE);
- denali_core_search_data_eye();
- remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif
-
- /*
- * Program tlb entries for this size (dynamic)
- */
- program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
- MY_TLB_WORD2_I_ENABLE);
-
-#if defined(CONFIG_DDR_ECC)
-#if defined(CONFIG_4xx_DCACHE)
- /*
- * If ECC is enabled, initialize the parity bits.
- */
- program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-#else /* CONFIG_4xx_DCACHE */
- /*
- * Setup 2nd TLB with same physical address but different virtual address
- * with cache enabled. This is done for fast ECC generation.
- */
- program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
- /*
- * If ECC is enabled, initialize the parity bits.
- */
- program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
- /*
- * Now after initialization (auto-calibration and ECC generation)
- * remove the TLB entries with caches enabled and program again with
- * desired cache functionality
- */
- remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif /* CONFIG_4xx_DCACHE */
-#endif /* CONFIG_DDR_ECC */
-
- /*
- * Clear possible errors resulting from data-eye-search.
- * If not done, then we could get an interrupt later on when
- * exceptions are enabled.
- */
- set_mcsr(get_mcsr());
-
- return (CONFIG_SYS_MBYTES_SDRAM << 20);
-}
};
U_BOOT_DEVICE(overo_uart) = {
- "serial_omap",
+ "ns16550_serial",
&overo_serial
};
};
U_BOOT_DEVICE(cairo_uart) = {
- "serial_omap",
+ "ns16550_serial",
&cairo_serial
};
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+config MACH_SUN8I_H3
+ bool "sun8i (Allwinner H3)"
+ select CPU_V7
+ select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
- default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
+ default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3
config DRAM_CLK
F: include/configs/sun8i.h
F: configs/ga10h_v1_1_defconfig
F: configs/gt90h_v4_defconfig
+F: configs/orangepi_pc_defconfig
+F: configs/orangepi_plus_defconfig
F: configs/q8_a23_tablet_800x480_defconfig
F: configs/q8_a33_tablet_800x480_defconfig
F: configs/q8_a33_tablet_1024x600_defconfig
S: Maintained
F: configs/iNet_86VS_defconfig
+LAMOBO-R1 BOARD
+M: Jelle de Jong <jelledejong@powercraft.nl>
+S: Maintained
+F: configs/Lamobo_R1_defconfig
+
LINKSPRITE-PCDUINO BOARD
M: Zoltan Herpai <wigyori@uid0.hu>
S: Maintained
{UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
{I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
{I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
- {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */
- {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */
- {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */
- {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */
+ {WAKEUP0, (M0 | PULL_UP)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP1, (M0)}, /* Wakeup1.Wakeup1 */
+ {WAKEUP2, (M0)}, /* Wakeup2.Wakeup2 */
+ {WAKEUP3, (M0 | PULL_UP)}, /* Wakeup3.Wakeup3 */
{ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
{RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
{RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */
};
U_BOOT_DEVICE(beagle_uart) = {
- "serial_omap",
+ "ns16550_serial",
&beagle_serial
};
{I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */
{I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */
{WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
- {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */
+ {WAKEUP2, (M14)}, /* Wakeup2.gpio1_2 */
};
#ifdef CONFIG_IODELAY_RECALIBRATION
};
U_BOOT_DEVICE(devkit8000_uart) = {
- "serial_omap",
+ "ns16550_serial",
&devkit8000_serial
};
--- /dev/null
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+if TARGET_NSA310S
+
+config SYS_BOARD
+ default "nsa310s"
+
+config SYS_VENDOR
+ default "zyxel"
+
+config SYS_CONFIG_NAME
+ default "nsa310s"
+
+endif
--- /dev/null
+NSA310S BOARD
+M: Gerald Kerma <dreagle@doukki.net>
+M: Tony Dinh <mibodhi@gmail.com>
+M: Luka Perkov <luka.perkov@sartura.hr>
+S: Maintained
+F: board/zyxel/nsa310s/
+F: include/configs/nsa310s.h
+F: configs/nsa310s_defconfig
--- /dev/null
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nsa310s.o
--- /dev/null
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer to doc/README.kwbimage for more details about how-to
+# configure and create kirkwood boot images.
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+DATA 0xFFD01400 0x43010c30
+DATA 0xFFD01404 0x39543000
+DATA 0xFFD01408 0x22125451
+DATA 0xFFD0140C 0x00000833
+DATA 0xFFD01410 0x0000000C
+DATA 0xFFD01414 0x00000000
+DATA 0xFFD01418 0x00000000
+DATA 0xFFD0141C 0x00000652
+DATA 0xFFD01420 0x00000004
+DATA 0xFFD01424 0x0000F17F
+DATA 0xFFD01428 0x00085520
+DATA 0xFFD0147c 0x00008552
+DATA 0xFFD01504 0x0FFFFFF1
+DATA 0xFFD01508 0x10000000
+DATA 0xFFD0150C 0x00000000
+DATA 0xFFD01514 0x00000000
+DATA 0xFFD0151C 0x00000000
+DATA 0xFFD01494 0x00010000
+DATA 0xFFD01498 0x00000000
+DATA 0xFFD0149C 0x0000E403
+DATA 0xFFD01480 0x00000001
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0x0 0x0
--- /dev/null
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/io.h>
+#include "nsa310s.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
+ NSA310S_OE_LOW, NSA310S_OE_HIGH);
+
+ /* (all LEDs & power off active high) */
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_GPIO,
+ MPP14_GPIO,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+ u16 reg;
+ u16 phyaddr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* read PHY dev address */
+ if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
+ printf("could not read PHY dev address\n");
+ return;
+ }
+
+ /* set RGMII delay */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
+ miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®);
+ reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
+ miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
+
+ /* reset PHY */
+ if (miiphy_reset(name, phyaddr))
+ return;
+
+ /*
+ * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
+ * and has an MCU attached to the LED[2] via tristate interrupt
+ */
+
+ /* switch to LED register page */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
+ /* read out LED polarity register */
+ miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®);
+ /* clear 4, set 5 - LED2 low, tri-state */
+ reg &= ~(MV88E1318_LED2_4);
+ reg |= (MV88E1318_LED2_5);
+ /* write back LED polarity register */
+ miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
+ /* jump back to page 0, per the PHY chip documenation. */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
+
+ /* set PHY back to auto-negotiation mode */
+ miiphy_write(name, phyaddr, 0x4, 0x1e1);
+ miiphy_write(name, phyaddr, 0x9, 0x300);
+ /* downshift */
+ miiphy_write(name, phyaddr, 0x10, 0x3860);
+ miiphy_write(name, phyaddr, 0x0, 0x9140);
+}
+#endif /* CONFIG_RESET_PHY_R */
--- /dev/null
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __NSA310S_H
+#define __NSA310S_H
+
+/* low GPIO's */
+#define HDD1_GREEN_LED (1 << 16)
+#define HDD1_RED_LED (1 << 13)
+#define USB_GREEN_LED (1 << 15)
+#define USB_POWER (1 << 21)
+#define SYS_GREEN_LED (1 << 28)
+#define SYS_ORANGE_LED (1 << 29)
+
+#define COPY_GREEN_LED (1 << 22)
+#define COPY_RED_LED (1 << 23)
+
+#define PIN_USB_GREEN_LED 15
+#define PIN_USB_POWER 21
+
+#define NSA310S_OE_LOW (~(0))
+#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
+
+/* high GPIO's */
+#define HDD2_GREEN_LED (1 << 2)
+#define HDD2_POWER (1 << 1)
+
+#define NSA310S_OE_HIGH (~(0))
+#define NSA310S_VAL_HIGH (HDD2_POWER)
+
+/* PHY related */
+#define MV88E1318_PGADR_REG 22
+#define MV88E1318_MAC_CTRL_PG 2
+#define MV88E1318_MAC_CTRL_REG 21
+#define MV88E1318_RGMII_TX_CTRL (1 << 4)
+#define MV88E1318_RGMII_RX_CTRL (1 << 5)
+#define MV88E1318_LED_PG 3
+#define MV88E1318_LED_POL_REG 17
+#define MV88E1318_LED2_4 (1 << 4)
+#define MV88E1318_LED2_5 (1 << 5)
+
+#endif /* __NSA310S_H */
{
/* tell others: relocation done */
gd->flags |= GD_FLG_RELOC | GD_FLG_FULL_MALLOC_INIT;
- bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
return 0;
}
}
#endif
+static int initr_bootstage(void)
+{
+ /* We cannot do this before initr_dm() */
+ bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
+
+ return 0;
+}
+
__weak int power_init_board(void)
{
return 0;
#ifdef CONFIG_DM
initr_dm,
#endif
+ initr_bootstage,
#if defined(CONFIG_ARM) || defined(CONFIG_NDS32)
board_init, /* Setup chipselects */
#endif
#include <command.h>
#include <i2c.h>
-extern void eeprom_init (void);
-extern int eeprom_read (unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt);
-extern int eeprom_write (unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt);
-#if defined(CONFIG_SYS_EEPROM_WREN)
-extern int eeprom_write_enable (unsigned dev_addr, int state);
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED 50000
#endif
-
-#if defined(CONFIG_SYS_EEPROM_X40430)
- /* Maximum number of times to poll for acknowledge after write */
-#define MAX_ACKNOWLEDGE_POLLS 10
+#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 0
#endif
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_EEPROM)
-static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- const char *const fmt =
- "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
-
-#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
- if (argc == 6) {
- ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
- ulong addr = simple_strtoul (argv[3], NULL, 16);
- ulong off = simple_strtoul (argv[4], NULL, 16);
- ulong cnt = simple_strtoul (argv[5], NULL, 16);
-#else
- if (argc == 5) {
- ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
- ulong addr = simple_strtoul (argv[2], NULL, 16);
- ulong off = simple_strtoul (argv[3], NULL, 16);
- ulong cnt = simple_strtoul (argv[4], NULL, 16);
-#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
-
-# if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
- eeprom_init ();
-# endif /* !CONFIG_SPI */
-
- if (strcmp (argv[1], "read") == 0) {
- int rcode;
-
- printf (fmt, dev_addr, argv[1], addr, off, cnt);
-
- rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);
-
- puts ("done\n");
- return rcode;
- } else if (strcmp (argv[1], "write") == 0) {
- int rcode;
-
- printf (fmt, dev_addr, argv[1], addr, off, cnt);
-
- rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
-
- puts ("done\n");
- return rcode;
- }
- }
-
- return CMD_RET_USAGE;
-}
+#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 8
#endif
-/*-----------------------------------------------------------------------
- *
+#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
+#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
+
+/*
* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
*
* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
* 0x00000nxx for EEPROM address selectors and page number at n.
*/
-
#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
-#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 || CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
+#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || \
+ (CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1) || \
+ (CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2)
#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
#endif
#endif
-int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+__weak int eeprom_write_enable(unsigned dev_addr, int state)
{
- unsigned end = offset + cnt;
- unsigned blk_off;
- int rcode = 0;
+ return 0;
+}
- /* Read data until done or would cross a page boundary.
- * We must write the address again when changing pages
- * because the next page may be in a different device.
- */
- while (offset < end) {
- unsigned alen, len;
-#if !defined(CONFIG_SYS_I2C_FRAM)
- unsigned maxlen;
+void eeprom_init(int bus)
+{
+ /* SPI EEPROM */
+#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
+ spi_init_f();
#endif
-#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
- uchar addr[2];
+ /* I2C EEPROM */
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+#if defined(CONFIG_SYS_I2C)
+ if (bus >= 0)
+ i2c_set_bus_num(bus);
+#endif
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+}
- blk_off = offset & 0xFF; /* block offset */
+static int eeprom_addr(unsigned dev_addr, unsigned offset, uchar *addr)
+{
+ unsigned blk_off;
+ int alen;
- addr[0] = offset >> 8; /* block number */
- addr[1] = blk_off; /* block offset */
- alen = 2;
+ blk_off = offset & 0xff; /* block offset */
+#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1
+ addr[0] = offset >> 8; /* block number */
+ addr[1] = blk_off; /* block offset */
+ alen = 2;
#else
- uchar addr[3];
-
- blk_off = offset & 0xFF; /* block offset */
-
- addr[0] = offset >> 16; /* block number */
- addr[1] = offset >> 8; /* upper address octet */
- addr[2] = blk_off; /* lower address octet */
- alen = 3;
-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
-
- addr[0] |= dev_addr; /* insert device address */
+ addr[0] = offset >> 16; /* block number */
+ addr[1] = offset >> 8; /* upper address octet */
+ addr[2] = blk_off; /* lower address octet */
+ alen = 3;
+#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN */
- len = end - offset;
+ addr[0] |= dev_addr; /* insert device address */
- /*
- * For a FRAM device there is no limit on the number of the
- * bytes that can be ccessed with the single read or write
- * operation.
- */
-#if !defined(CONFIG_SYS_I2C_FRAM)
- maxlen = 0x100 - blk_off;
- if (maxlen > I2C_RXTX_LEN)
- maxlen = I2C_RXTX_LEN;
- if (len > maxlen)
- len = maxlen;
-#endif
-
-#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
- spi_read (addr, alen, buffer, len);
-#else
-#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
- i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
-#endif
- if (i2c_read(addr[0], offset, alen - 1, buffer, len))
- rcode = 1;
-#endif
- buffer += len;
- offset += len;
- }
-
- return rcode;
+ return alen;
}
-/*-----------------------------------------------------------------------
- *
- * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
- * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
- *
- * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
- * 0x00000nxx for EEPROM address selectors and page number at n.
- */
-
-int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+static int eeprom_len(unsigned offset, unsigned end)
{
- unsigned end = offset + cnt;
- unsigned blk_off;
- int rcode = 0;
-
-#if defined(CONFIG_SYS_EEPROM_X40430)
- uchar contr_r_addr[2];
- uchar addr_void[2];
- uchar contr_reg[2];
- uchar ctrl_reg_v;
- int i;
-#endif
+ unsigned len = end - offset;
-#if defined(CONFIG_SYS_EEPROM_WREN)
- eeprom_write_enable (dev_addr,1);
-#endif
- /* Write data until done or would cross a write page boundary.
- * We must write the address again when changing pages
- * because the address counter only increments within a page.
+ /*
+ * For a FRAM device there is no limit on the number of the
+ * bytes that can be ccessed with the single read or write
+ * operation.
*/
-
- while (offset < end) {
- unsigned alen, len;
#if !defined(CONFIG_SYS_I2C_FRAM)
- unsigned maxlen;
-#endif
+ unsigned blk_off = offset & 0xff;
+ unsigned maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
-#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
- uchar addr[2];
+ if (maxlen > I2C_RXTX_LEN)
+ maxlen = I2C_RXTX_LEN;
- blk_off = offset & 0xFF; /* block offset */
-
- addr[0] = offset >> 8; /* block number */
- addr[1] = blk_off; /* block offset */
- alen = 2;
-#else
- uchar addr[3];
+ if (len > maxlen)
+ len = maxlen;
+#endif
- blk_off = offset & 0xFF; /* block offset */
+ return len;
+}
- addr[0] = offset >> 16; /* block number */
- addr[1] = offset >> 8; /* upper address octet */
- addr[2] = blk_off; /* lower address octet */
- alen = 3;
-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
+static int eeprom_rw_block(unsigned offset, uchar *addr, unsigned alen,
+ uchar *buffer, unsigned len, bool read)
+{
+ int ret = 0;
- addr[0] |= dev_addr; /* insert device address */
+ /* SPI */
+#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
+ if (read)
+ spi_read(addr, alen, buffer, len);
+ else
+ spi_write(addr, alen, buffer, len);
+#else /* I2C */
- len = end - offset;
+#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
+ i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+#endif
- /*
- * For a FRAM device there is no limit on the number of the
- * bytes that can be accessed with the single read or write
- * operation.
- */
-#if !defined(CONFIG_SYS_I2C_FRAM)
+ if (read)
+ ret = i2c_read(addr[0], offset, alen - 1, buffer, len);
+ else
+ ret = i2c_write(addr[0], offset, alen - 1, buffer, len);
-#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
+ if (ret)
+ ret = 1;
+#endif
+ return ret;
+}
-#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
-#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
+static int eeprom_rw(unsigned dev_addr, unsigned offset, uchar *buffer,
+ unsigned cnt, bool read)
+{
+ unsigned end = offset + cnt;
+ unsigned alen, len;
+ int rcode = 0;
+ uchar addr[3];
- maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
-#else
- maxlen = 0x100 - blk_off;
-#endif
- if (maxlen > I2C_RXTX_LEN)
- maxlen = I2C_RXTX_LEN;
+ while (offset < end) {
+ alen = eeprom_addr(dev_addr, offset, addr);
- if (len > maxlen)
- len = maxlen;
-#endif
+ len = eeprom_len(offset, end);
-#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
- spi_write (addr, alen, buffer, len);
-#else
-#if defined(CONFIG_SYS_EEPROM_X40430)
- /* Get the value of the control register.
- * Set current address (internal pointer in the x40430)
- * to 0x1ff.
- */
- contr_r_addr[0] = 9;
- contr_r_addr[1] = 0xff;
- addr_void[0] = 0;
- addr_void[1] = addr[1];
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
- contr_r_addr[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
- addr_void[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
-#endif
- contr_reg[0] = 0xff;
- if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
- rcode = 1;
- }
- ctrl_reg_v = contr_reg[0];
-
- /* Are any of the eeprom blocks write protected?
- */
- if (ctrl_reg_v & 0x18) {
- ctrl_reg_v &= ~0x18; /* reset block protect bits */
- ctrl_reg_v |= 0x02; /* set write enable latch */
- ctrl_reg_v &= ~0x04; /* clear RWEL */
-
- /* Set write enable latch.
- */
- contr_reg[0] = 0x02;
- if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
- rcode = 1;
- }
-
- /* Set register write enable latch.
- */
- contr_reg[0] = 0x06;
- if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
- rcode = 1;
- }
-
- /* Modify ctrl register.
- */
- contr_reg[0] = ctrl_reg_v;
- if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
- rcode = 1;
- }
-
- /* The write (above) is an operation on NV memory.
- * These can take some time (~5ms), and the device
- * will not respond to further I2C messages till
- * it's completed the write.
- * So poll device for an I2C acknowledge.
- * When we get one we know we can continue with other
- * operations.
- */
- contr_reg[0] = 0;
- for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
- if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
- break; /* got ack */
-#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
- udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
-#endif
- }
- if (i == MAX_ACKNOWLEDGE_POLLS) {
- puts ("EEPROM poll acknowledge failed\n");
- rcode = 1;
- }
- }
-
- /* Is the write enable latch on?.
- */
- else if (!(ctrl_reg_v & 0x02)) {
- /* Set write enable latch.
- */
- contr_reg[0] = 0x02;
- if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
- rcode = 1;
- }
- }
- /* Write is enabled ... now write eeprom value.
- */
-#endif
-#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
- i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
-#endif
- if (i2c_write(addr[0], offset, alen - 1, buffer, len))
- rcode = 1;
+ rcode = eeprom_rw_block(offset, addr, alen, buffer, len, read);
-#endif
buffer += len;
offset += len;
-#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
- udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
-#endif
+ if (!read)
+ udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
}
-#if defined(CONFIG_SYS_EEPROM_WREN)
- eeprom_write_enable (dev_addr,0);
-#endif
+
return rcode;
}
-#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
-int
-eeprom_probe (unsigned dev_addr, unsigned offset)
+int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
{
- unsigned char chip;
-
- /* Probe the chip address
+ /*
+ * Read data until done or would cross a page boundary.
+ * We must write the address again when changing pages
+ * because the next page may be in a different device.
*/
-#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
- chip = offset >> 8; /* block number */
-#else
- chip = offset >> 16; /* block number */
-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
+ return eeprom_rw(dev_addr, offset, buffer, cnt, 1);
+}
+
+int eeprom_write(unsigned dev_addr, unsigned offset,
+ uchar *buffer, unsigned cnt)
+{
+ int ret;
+
+ eeprom_write_enable(dev_addr, 1);
- chip |= dev_addr; /* insert device address */
+ /*
+ * Write data until done or would cross a write page boundary.
+ * We must write the address again when changing pages
+ * because the address counter only increments within a page.
+ */
+ ret = eeprom_rw(dev_addr, offset, buffer, cnt, 1);
- return (i2c_probe (chip));
+ eeprom_write_enable(dev_addr, 0);
+ return ret;
}
-#endif
-/*-----------------------------------------------------------------------
- * Set default values
- */
-#ifndef CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SPEED 50000
+static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const char *const fmt =
+ "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
+ char * const *args = &argv[2];
+ int rcode;
+ ulong dev_addr, addr, off, cnt;
+ int bus_addr;
+
+ switch (argc) {
+#ifdef CONFIG_SYS_DEF_EEPROM_ADDR
+ case 5:
+ bus_addr = -1;
+ dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
+ break;
#endif
+ case 6:
+ bus_addr = -1;
+ dev_addr = simple_strtoul(*args++, NULL, 16);
+ break;
+ case 7:
+ bus_addr = simple_strtoul(*args++, NULL, 16);
+ dev_addr = simple_strtoul(*args++, NULL, 16);
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
-void eeprom_init (void)
-{
+ addr = simple_strtoul(*args++, NULL, 16);
+ off = simple_strtoul(*args++, NULL, 16);
+ cnt = simple_strtoul(*args++, NULL, 16);
-#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
- spi_init_f ();
-#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-}
+ eeprom_init(bus_addr);
-/*-----------------------------------------------------------------------
- */
+ if (strcmp(argv[1], "read") == 0) {
+ printf(fmt, dev_addr, argv[1], addr, off, cnt);
+
+ rcode = eeprom_read(dev_addr, off, (uchar *)addr, cnt);
+
+ puts("done\n");
+ return rcode;
+ } else if (strcmp(argv[1], "write") == 0) {
+ printf(fmt, dev_addr, argv[1], addr, off, cnt);
-/***************************************************/
+ rcode = eeprom_write(dev_addr, off, (uchar *)addr, cnt);
-#if defined(CONFIG_CMD_EEPROM)
+ puts("done\n");
+ return rcode;
+ }
+
+ return CMD_RET_USAGE;
+}
-#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
U_BOOT_CMD(
- eeprom, 6, 1, do_eeprom,
+ eeprom, 7, 1, do_eeprom,
"EEPROM sub-system",
- "read devaddr addr off cnt\n"
- "eeprom write devaddr addr off cnt\n"
+ "read <bus> <devaddr> addr off cnt\n"
+ "eeprom write <bus> <devaddr> addr off cnt\n"
" - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
)
-#else /* One EEPROM */
-U_BOOT_CMD(
- eeprom, 5, 1, do_eeprom,
- "EEPROM sub-system",
- "read addr off cnt\n"
- "eeprom write addr off cnt\n"
- " - read/write `cnt' bytes at EEPROM offset `off'"
-)
-#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
-
-#endif
/*
* cmd_gpt.c -- GPT (GUID Partition Table) handling command
*
+ * Copyright (C) 2015
+ * Lukasz Majewski <l.majewski@majess.pl>
+ *
* Copyright (C) 2012 Samsung Electronics
* author: Lukasz Majewski <l.majewski@samsung.com>
* author: Piotr Wilczek <p.wilczek@samsung.com>
#include <exports.h>
#include <linux/ctype.h>
#include <div64.h>
+#include <memalign.h>
#ifndef CONFIG_PARTITION_UUIDS
#error CONFIG_PARTITION_UUIDS must be enabled for CONFIG_CMD_GPT to be enabled
return new;
}
+/**
+ * found_key(): Found key without value in parameter list (comma separated).
+ *
+ * @param str - pointer to string with key
+ * @param key - pointer to the key to search for
+ *
+ * @return - true on found key
+ */
+static bool found_key(const char *str, const char *key)
+{
+ char *k;
+ char *s, *strcopy;
+ bool result = false;
+
+ strcopy = strdup(str);
+ if (!strcopy)
+ return NULL;
+
+ s = strcopy;
+ while (s) {
+ k = strsep(&s, ",");
+ if (!k)
+ break;
+ if (strcmp(k, key) == 0) {
+ result = true;
+ break;
+ }
+ }
+
+ free(strcopy);
+
+ return result;
+}
+
/**
* set_gpt_info(): Fill partition information from string
* function allocates memory, remember to free!
parts[i].start = lldiv(start_ll, dev_desc->blksz);
free(val);
}
+
+ /* bootable */
+ if (found_key(tok, "bootable"))
+ parts[i].bootable = 1;
}
*parts_count = p_count;
u8 part_count = 0;
disk_partition_t *partitions = NULL;
- if (!str_part)
- return -1;
-
/* fill partitions */
ret = set_gpt_info(blk_dev_desc, str_part,
&str_disk_guid, &partitions, &part_count);
return ret;
}
+static int gpt_verify(block_dev_desc_t *blk_dev_desc, const char *str_part)
+{
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1,
+ blk_dev_desc->blksz);
+ disk_partition_t *partitions = NULL;
+ gpt_entry *gpt_pte = NULL;
+ char *str_disk_guid;
+ u8 part_count = 0;
+ int ret = 0;
+
+ /* fill partitions */
+ ret = set_gpt_info(blk_dev_desc, str_part,
+ &str_disk_guid, &partitions, &part_count);
+ if (ret) {
+ if (ret == -1) {
+ printf("No partition list provided - only basic check\n");
+ ret = gpt_verify_headers(blk_dev_desc, gpt_head,
+ &gpt_pte);
+ goto out;
+ }
+ if (ret == -2)
+ printf("Missing disk guid\n");
+ if ((ret == -3) || (ret == -4))
+ printf("Partition list incomplete\n");
+ return -1;
+ }
+
+ /* Check partition layout with provided pattern */
+ ret = gpt_verify_partitions(blk_dev_desc, partitions, part_count,
+ gpt_head, &gpt_pte);
+ free(str_disk_guid);
+ free(partitions);
+ out:
+ free(gpt_pte);
+ return ret;
+}
+
/**
* do_gpt(): Perform GPT operations
*
int ret = CMD_RET_SUCCESS;
int dev = 0;
char *ep;
- block_dev_desc_t *blk_dev_desc;
+ block_dev_desc_t *blk_dev_desc = NULL;
- if (argc < 5)
+ if (argc < 4 || argc > 5)
return CMD_RET_USAGE;
- /* command: 'write' */
- if ((strcmp(argv[1], "write") == 0) && (argc == 5)) {
- dev = (int)simple_strtoul(argv[3], &ep, 10);
- if (!ep || ep[0] != '\0') {
- printf("'%s' is not a number\n", argv[3]);
- return CMD_RET_USAGE;
- }
- blk_dev_desc = get_dev(argv[2], dev);
- if (!blk_dev_desc) {
- printf("%s: %s dev %d NOT available\n",
- __func__, argv[2], dev);
- return CMD_RET_FAILURE;
- }
-
- puts("Writing GPT: ");
+ dev = (int)simple_strtoul(argv[3], &ep, 10);
+ if (!ep || ep[0] != '\0') {
+ printf("'%s' is not a number\n", argv[3]);
+ return CMD_RET_USAGE;
+ }
+ blk_dev_desc = get_dev(argv[2], dev);
+ if (!blk_dev_desc) {
+ printf("%s: %s dev %d NOT available\n",
+ __func__, argv[2], dev);
+ return CMD_RET_FAILURE;
+ }
+ if ((strcmp(argv[1], "write") == 0) && (argc == 5)) {
+ printf("Writing GPT: ");
ret = gpt_default(blk_dev_desc, argv[4]);
- if (!ret) {
- puts("success!\n");
- return CMD_RET_SUCCESS;
- } else {
- puts("error!\n");
- return CMD_RET_FAILURE;
- }
+ } else if ((strcmp(argv[1], "verify") == 0)) {
+ ret = gpt_verify(blk_dev_desc, argv[4]);
+ printf("Verify GPT: ");
} else {
return CMD_RET_USAGE;
}
- return ret;
+
+ if (ret) {
+ printf("error!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("success!\n");
+ return CMD_RET_SUCCESS;
}
U_BOOT_CMD(gpt, CONFIG_SYS_MAXARGS, 1, do_gpt,
"GUID Partition Table",
"<command> <interface> <dev> <partitions_list>\n"
- " - GUID partition table restoration\n"
- " Restore GPT information on a device connected\n"
+ " - GUID partition table restoration and validity check\n"
+ " Restore or verify GPT information on a device connected\n"
" to interface\n"
+ " Example usage:\n"
+ " gpt write mmc 0 $partitions\n"
+ " gpt verify mmc 0 $partitions\n"
);
#include <cli.h>
#include <command.h>
#include <console.h>
+#include <dm.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
-/*
- * Follows routines for the output of infos about devices on PCI bus.
- */
+struct pci_reg_info {
+ const char *name;
+ enum pci_size_t size;
+ u8 offset;
+};
-void pci_header_show(pci_dev_t dev);
-void pci_header_show_brief(pci_dev_t dev);
+static int pci_byte_size(enum pci_size_t size)
+{
+ switch (size) {
+ case PCI_SIZE_8:
+ return 1;
+ case PCI_SIZE_16:
+ return 2;
+ case PCI_SIZE_32:
+ default:
+ return 4;
+ }
+}
-/*
- * Subroutine: pciinfo
- *
- * Description: Show information about devices on PCI bus.
- * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
- * the output will be more or less exhaustive.
- *
- * Inputs: bus_no the number of the bus to be scanned.
- *
- * Return: None
+static int pci_field_width(enum pci_size_t size)
+{
+ return pci_byte_size(size) * 2;
+}
+
+#ifdef CONFIG_DM_PCI
+static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
+{
+ for (; regs->name; regs++) {
+ unsigned long val;
+
+ dm_pci_read_config(dev, regs->offset, &val, regs->size);
+ printf(" %s =%*s%#.*lx\n", regs->name,
+ (int)(28 - strlen(regs->name)), "",
+ pci_field_width(regs->size), val);
+ }
+}
+#else
+static unsigned long pci_read_config(pci_dev_t dev, int offset,
+ enum pci_size_t size)
+{
+ u32 val32;
+ u16 val16;
+ u8 val8;
+
+ switch (size) {
+ case PCI_SIZE_8:
+ pci_read_config_byte(dev, offset, &val8);
+ return val8;
+ case PCI_SIZE_16:
+ pci_read_config_word(dev, offset, &val16);
+ return val16;
+ case PCI_SIZE_32:
+ default:
+ pci_read_config_dword(dev, offset, &val32);
+ return val32;
+ }
+}
+
+static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
+{
+ for (; regs->name; regs++) {
+ printf(" %s =%*s%#.*lx\n", regs->name,
+ (int)(28 - strlen(regs->name)), "",
+ pci_field_width(regs->size),
+ pci_read_config(dev, regs->offset, regs->size));
+ }
+}
+#endif
+
+static struct pci_reg_info regs_start[] = {
+ { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
+ { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
+ { "command register ID", PCI_SIZE_16, PCI_COMMAND },
+ { "status register", PCI_SIZE_16, PCI_STATUS },
+ { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
+ {},
+};
+
+static struct pci_reg_info regs_rest[] = {
+ { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
+ { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
+ { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
+ { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
+ { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
+ { "BIST", PCI_SIZE_8, PCI_BIST },
+ { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
+ {},
+};
+
+static struct pci_reg_info regs_normal[] = {
+ { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
+ { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
+ { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
+ { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
+ { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
+ { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
+ { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
+ { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
+ { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
+ { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
+ { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
+ { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
+ { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
+ {},
+};
+
+static struct pci_reg_info regs_bridge[] = {
+ { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
+ { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
+ { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
+ { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
+ { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
+ { "IO base", PCI_SIZE_8, PCI_IO_BASE },
+ { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
+ { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
+ { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
+ { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
+ { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
+ { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
+ { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
+ { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
+ { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
+ { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
+ { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
+ { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
+ { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
+ { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
+ {},
+};
+
+static struct pci_reg_info regs_cardbus[] = {
+ { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
+ { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
+ { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
+ { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
+ { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
+ { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
+ { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
+ { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
+ { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
+ { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
+ { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
+ { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
+ { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
+ { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
+ { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
+ { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
+ { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
+ { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
+ { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
+ { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
+ { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
+ { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
+ { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
+ { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
+ {},
+};
+
+/**
+ * pci_header_show() - Show the header of the specified PCI device.
*
+ * @dev: Bus+Device+Function number
*/
-void pciinfo(int BusNum, int ShortPCIListing)
+#ifdef CONFIG_DM_PCI
+void pci_header_show(struct udevice *dev)
+#else
+void pci_header_show(pci_dev_t dev)
+#endif
{
- struct pci_controller *hose = pci_bus_to_hose(BusNum);
- int Device;
- int Function;
- unsigned char HeaderType;
- unsigned short VendorID;
- pci_dev_t dev;
- int ret;
+#ifdef CONFIG_DM_PCI
+ unsigned long class, header_type;
- if (!hose)
- return;
+ dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
+ dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
+#else
+ u8 class, header_type;
+
+ pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
+ pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
+#endif
+ pci_show_regs(dev, regs_start);
+ printf(" class code = 0x%.2x (%s)\n", (int)class,
+ pci_class_str(class));
+ pci_show_regs(dev, regs_rest);
+
+ switch (header_type & 0x03) {
+ case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
+ pci_show_regs(dev, regs_normal);
+ break;
+ case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
+ pci_show_regs(dev, regs_bridge);
+ break;
+ case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
+ pci_show_regs(dev, regs_cardbus);
+ break;
+
+ default:
+ printf("unknown header\n");
+ break;
+ }
+}
- printf("Scanning PCI devices on bus %d\n", BusNum);
+void pciinfo_header(int busnum, bool short_listing)
+{
+ printf("Scanning PCI devices on bus %d\n", busnum);
- if (ShortPCIListing) {
+ if (short_listing) {
printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
printf("_____________________________________________________________\n");
}
+}
- for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
- HeaderType = 0;
- VendorID = 0;
- for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
- /*
- * If this is not a multi-function device, we skip the rest.
- */
- if (Function && !(HeaderType & 0x80))
- break;
-
- dev = PCI_BDF(BusNum, Device, Function);
-
- if (pci_skip_dev(hose, dev))
- continue;
+#ifdef CONFIG_DM_PCI
+/**
+ * pci_header_show_brief() - Show the short-form PCI device header
+ *
+ * Reads and prints the header of the specified PCI device in short form.
+ *
+ * @dev: PCI device to show
+ */
+static void pci_header_show_brief(struct udevice *dev)
+{
+ ulong vendor, device;
+ ulong class, subclass;
- ret = pci_read_config_word(dev, PCI_VENDOR_ID,
- &VendorID);
- if (ret)
- goto error;
- if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
- continue;
+ dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
+ dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
+ dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
+ dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
- if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
+ printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
+ vendor, device,
+ pci_class_str(class), subclass);
+}
- if (ShortPCIListing)
- {
- printf("%02x.%02x.%02x ", BusNum, Device, Function);
- pci_header_show_brief(dev);
- }
- else
- {
- printf("\nFound PCI device %02x.%02x.%02x:\n",
- BusNum, Device, Function);
- pci_header_show(dev);
- }
+static void pciinfo(struct udevice *bus, bool short_listing)
+{
+ struct udevice *dev;
+
+ pciinfo_header(bus->seq, short_listing);
+
+ for (device_find_first_child(bus, &dev);
+ dev;
+ device_find_next_child(&dev)) {
+ struct pci_child_platdata *pplat;
+
+ pplat = dev_get_parent_platdata(dev);
+ if (short_listing) {
+ printf("%02x.%02x.%02x ", bus->seq,
+ PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
+ pci_header_show_brief(dev);
+ } else {
+ printf("\nFound PCI device %02x.%02x.%02x:\n", bus->seq,
+ PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
+ pci_header_show(dev);
}
}
-
- return;
-error:
- printf("Cannot read bus configuration: %d\n", ret);
}
+#else
-/*
- * Subroutine: pci_header_show_brief
- *
- * Description: Reads and prints the header of the
- * specified PCI device in short form.
+/**
+ * pci_header_show_brief() - Show the short-form PCI device header
*
- * Inputs: dev Bus+Device+Function number
- *
- * Return: None
+ * Reads and prints the header of the specified PCI device in short form.
*
+ * @dev: Bus+Device+Function number
*/
void pci_header_show_brief(pci_dev_t dev)
{
pci_class_str(class), subclass);
}
-/*
- * Subroutine: PCI_Header_Show
+/**
+ * pciinfo() - Show a list of devices on the PCI bus
*
- * Description: Reads the header of the specified PCI device.
- *
- * Inputs: BusDevFunc Bus+Device+Function number
- *
- * Return: None
+ * Show information about devices on PCI bus. Depending on @short_pci_listing
+ * the output will be more or less exhaustive.
*
+ * @bus_num: The number of the bus to be scanned
+ * @short_pci_listing: true to use short form, showing only a brief header
+ * for each device
*/
-void pci_header_show(pci_dev_t dev)
+void pciinfo(int bus_num, int short_pci_listing)
{
- u8 _byte, header_type;
- u16 _word;
- u32 _dword;
-
-#define PRINT(msg, type, reg) \
- pci_read_config_##type(dev, reg, &_##type); \
- printf(msg, _##type)
-
-#define PRINT2(msg, type, reg, func) \
- pci_read_config_##type(dev, reg, &_##type); \
- printf(msg, _##type, func(_##type))
+ struct pci_controller *hose = pci_bus_to_hose(bus_num);
+ int device;
+ int function;
+ unsigned char header_type;
+ unsigned short vendor_id;
+ pci_dev_t dev;
+ int ret;
- pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
+ if (!hose)
+ return;
- PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
- PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
- PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
- PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
- PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
- PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
- pci_class_str);
- PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
- PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
- PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
- PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
- PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
- PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
- PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
+ pciinfo_header(bus_num, short_pci_listing);
- switch (header_type & 0x03) {
- case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
- PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
- PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
- PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
- PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
- PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
- PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
- PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
- PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
- PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
- PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
- PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
- PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
- PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
- break;
+ for (device = 0; device < PCI_MAX_PCI_DEVICES; device++) {
+ header_type = 0;
+ vendor_id = 0;
+ for (function = 0; function < PCI_MAX_PCI_FUNCTIONS;
+ function++) {
+ /*
+ * If this is not a multi-function device, we skip
+ * the rest.
+ */
+ if (function && !(header_type & 0x80))
+ break;
- case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
+ dev = PCI_BDF(bus_num, device, function);
- PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
- PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
- PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
- PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
- PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
- PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
- PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
- PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
- PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
- PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
- PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
- PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
- PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
- PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
- PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
- PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
- PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
- PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
- PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
- PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
- break;
+ if (pci_skip_dev(hose, dev))
+ continue;
- case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
+ ret = pci_read_config_word(dev, PCI_VENDOR_ID,
+ &vendor_id);
+ if (ret)
+ goto error;
+ if ((vendor_id == 0xFFFF) || (vendor_id == 0x0000))
+ continue;
- PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
- PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
- PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
- PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
- PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
- PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
- PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
- PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
- PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
- PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
- PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
- PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
- PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
- PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
- PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
- PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
- PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
- PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
- PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
- PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
- PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
- PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
- PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
- PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
- break;
+ if (!function) {
+ pci_read_config_byte(dev, PCI_HEADER_TYPE,
+ &header_type);
+ }
- default:
- printf("unknown header\n");
- break;
- }
+ if (short_pci_listing) {
+ printf("%02x.%02x.%02x ", bus_num, device,
+ function);
+ pci_header_show_brief(dev);
+ } else {
+ printf("\nFound PCI device %02x.%02x.%02x:\n",
+ bus_num, device, function);
+ pci_header_show(dev);
+ }
+ }
+ }
-#undef PRINT
-#undef PRINT2
+ return;
+error:
+ printf("Cannot read bus configuration: %d\n", ret);
}
+#endif
-/* Convert the "bus.device.function" identifier into a number.
+/**
+ * get_pci_dev() - Convert the "bus.device.function" identifier into a number
+ *
+ * @name: Device string in the form "bus.device.function" where each is in hex
+ * @return encoded pci_dev_t or -1 if the string was invalid
*/
-static pci_dev_t get_pci_dev(char* name)
+static pci_dev_t get_pci_dev(char *name)
{
char cnum[12];
int len, i, iold, n;
if (n == 0)
n = 1;
bdfs[n] = simple_strtoul(cnum, NULL, 16);
+
return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
}
-static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
+#ifdef CONFIG_DM_PCI
+static int pci_cfg_display(struct udevice *dev, ulong addr,
+ enum pci_size_t size, ulong length)
+#else
+static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
+ ulong length)
+#endif
{
#define DISP_LINE_LEN 16
ulong i, nbytes, linebytes;
+ int byte_size;
int rc = 0;
+ byte_size = pci_byte_size(size);
if (length == 0)
- length = 0x40 / size; /* Standard PCI configuration space */
+ length = 0x40 / byte_size; /* Standard PCI config space */
/* Print the lines.
* once, and all accesses are with the specified bus width.
*/
- nbytes = length * size;
+ nbytes = length * byte_size;
do {
- uint val4;
- ushort val2;
- u_char val1;
-
printf("%08lx:", addr);
- linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
- for (i=0; i<linebytes; i+= size) {
- if (size == 4) {
- pci_read_config_dword(bdf, addr, &val4);
- printf(" %08x", val4);
- } else if (size == 2) {
- pci_read_config_word(bdf, addr, &val2);
- printf(" %04x", val2);
- } else {
- pci_read_config_byte(bdf, addr, &val1);
- printf(" %02x", val1);
- }
- addr += size;
+ linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
+ for (i = 0; i < linebytes; i += byte_size) {
+ unsigned long val;
+
+#ifdef CONFIG_DM_PCI
+ dm_pci_read_config(dev, addr, &val, size);
+#else
+ val = pci_read_config(bdf, addr, size);
+#endif
+ printf(" %0*lx", pci_field_width(size), val);
+ addr += byte_size;
}
printf("\n");
nbytes -= linebytes;
return (rc);
}
+#ifndef CONFIG_DM_PCI
static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
{
if (size == 4) {
}
return 0;
}
+#endif
-static int
-pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
+#ifdef CONFIG_DM_PCI
+static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
+ ulong value, int incrflag)
+#else
+static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
+ int incrflag)
+#endif
{
ulong i;
int nbytes;
- uint val4;
- ushort val2;
- u_char val1;
+ ulong val;
/* Print the address, followed by value. Then accept input for
* the next value. A non-converted value exits.
*/
do {
printf("%08lx:", addr);
- if (size == 4) {
- pci_read_config_dword(bdf, addr, &val4);
- printf(" %08x", val4);
- }
- else if (size == 2) {
- pci_read_config_word(bdf, addr, &val2);
- printf(" %04x", val2);
- }
- else {
- pci_read_config_byte(bdf, addr, &val1);
- printf(" %02x", val1);
- }
+#ifdef CONFIG_DM_PCI
+ dm_pci_read_config(dev, addr, &val, size);
+#else
+ val = pci_read_config(bdf, addr, size);
+#endif
+ printf(" %0*lx", pci_field_width(size), val);
nbytes = cli_readline(" ? ");
if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
/* good enough to not time out
*/
bootretry_reset_cmd_timeout();
- pci_cfg_write (bdf, addr, size, i);
+#ifdef CONFIG_DM_PCI
+ dm_pci_write_config(dev, addr, i, size);
+#else
+ pci_cfg_write(bdf, addr, size, i);
+#endif
if (incrflag)
addr += size;
}
*/
static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong addr = 0, value = 0, size = 0;
+ ulong addr = 0, value = 0, cmd_size = 0;
+ enum pci_size_t size = PCI_SIZE_32;
+#ifdef CONFIG_DM_PCI
+ struct udevice *dev, *bus;
+#else
+ pci_dev_t dev;
+#endif
+ int busnum = 0;
pci_dev_t bdf = 0;
char cmd = 's';
+ int ret = 0;
if (argc > 1)
cmd = argv[1][0];
case 'm': /* modify */
case 'w': /* write */
/* Check for a size specification. */
- size = cmd_get_data_size(argv[1], 4);
+ cmd_size = cmd_get_data_size(argv[1], 4);
+ size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
if (argc > 3)
addr = simple_strtoul(argv[3], NULL, 16);
if (argc > 4)
#endif
default: /* scan bus */
value = 1; /* short listing */
- bdf = 0; /* bus number */
if (argc > 1) {
if (argv[argc-1][0] == 'l') {
value = 0;
argc--;
}
if (argc > 1)
- bdf = simple_strtoul(argv[1], NULL, 16);
+ busnum = simple_strtoul(argv[1], NULL, 16);
+ }
+#ifdef CONFIG_DM_PCI
+ ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
+ if (ret) {
+ printf("No such bus\n");
+ return CMD_RET_FAILURE;
}
- pciinfo(bdf, value);
+ pciinfo(bus, value);
+#else
+ pciinfo(busnum, value);
+#endif
return 0;
}
+#ifdef CONFIG_DM_PCI
+ ret = pci_bus_find_bdf(bdf, &dev);
+ if (ret) {
+ printf("No such device\n");
+ return CMD_RET_FAILURE;
+ }
+#else
+ dev = bdf;
+#endif
+
switch (argv[1][0]) {
case 'h': /* header */
- pci_header_show(bdf);
- return 0;
+ pci_header_show(dev);
+ break;
case 'd': /* display */
- return pci_cfg_display(bdf, addr, size, value);
+ return pci_cfg_display(dev, addr, size, value);
#ifdef CONFIG_CMD_PCI_ENUM
case 'e':
+# ifdef CONFIG_DM_PCI
+ printf("This command is not yet supported with driver model\n");
+# else
pci_init();
- return 0;
+# endif
+ break;
#endif
case 'n': /* next */
if (argc < 4)
goto usage;
- return pci_cfg_modify(bdf, addr, size, value, 0);
+ ret = pci_cfg_modify(dev, addr, size, value, 0);
+ break;
case 'm': /* modify */
if (argc < 4)
goto usage;
- return pci_cfg_modify(bdf, addr, size, value, 1);
+ ret = pci_cfg_modify(dev, addr, size, value, 1);
+ break;
case 'w': /* write */
if (argc < 5)
goto usage;
- return pci_cfg_write(bdf, addr, size, value);
+#ifdef CONFIG_DM_PCI
+ ret = dm_pci_write_config(dev, addr, value, size);
+#else
+ ret = pci_cfg_write(dev, addr, size, value);
+#endif
+ break;
+ default:
+ ret = CMD_RET_USAGE;
+ break;
}
- return 1;
+ return ret;
usage:
return CMD_RET_USAGE;
}
}
}
-int printf(const char *fmt, ...)
-{
- va_list args;
- uint i;
- char printbuffer[CONFIG_SYS_PBSIZE];
-
- va_start(args, fmt);
-
- /* For this to work, printbuffer must be larger than
- * anything we ever want to print.
- */
- i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
- va_end(args);
-
- /* Print the string */
- puts(printbuffer);
- return i;
-}
-
-int vprintf(const char *fmt, va_list args)
-{
- uint i;
- char printbuffer[CONFIG_SYS_PBSIZE];
-
-#if defined(CONFIG_PRE_CONSOLE_BUFFER) && !defined(CONFIG_SANDBOX)
- if (!gd->have_console)
- return 0;
-#endif
-
- /* For this to work, printbuffer must be larger than
- * anything we ever want to print.
- */
- i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
-
- /* Print the string */
- puts(printbuffer);
- return i;
-}
-
#ifdef CONFIG_CONSOLE_RECORD
int console_record_init(void)
{
uchar rdbuf[64], flags[2];
int i, crc_ok[2] = {0, 0};
- eeprom_init(); /* prepare for EEPROM read/write */
+ eeprom_init(-1); /* prepare for EEPROM read/write */
off_env[0] = CONFIG_ENV_OFFSET;
off_env[1] = CONFIG_ENV_OFFSET_REDUND;
ulong crc, len, new;
uchar rdbuf[64];
- eeprom_init(); /* prepare for EEPROM read/write */
+ eeprom_init(-1); /* prepare for EEPROM read/write */
/* read old CRC */
eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
CONFIG_ALTERA_QSPI=y
CONFIG_DM_ETH=y
CONFIG_ALTERA_TSE=y
-CONFIG_ALTERA_UART=y
+CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
CONFIG_ALTERA_TIMER=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_SUNXI_NO_PMIC=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-CONFIG_USB_MUSB_SUNXI=y
-CONFIG_USB_MUSB_GADGET=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_CMD_GPIO=y
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_GPIO=y
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_AXP_DCDC2_VOLT=1300
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_GADGET=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SPI_CS="PA0"
CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_USB0_VBUS_PIN="PH17"
+CONFIG_USB0_VBUS_DET="PH22"
+CONFIG_USB0_ID_DET="PH19"
CONFIG_VIDEO_VGA=y
CONFIG_GMAC_TX_DELAY=1
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB0_ID_DET="PH19"
-CONFIG_USB0_VBUS_DET="PH22"
-CONFIG_USB0_VBUS_PIN="PH17"
-CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB_MUSB_GADGET=y
# CONFIG_CMD_FLASH is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_FLASH is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_MMC0_CD_PIN="PH10"
+CONFIG_GMAC_TX_DELAY=4
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_TARGET_MIP405=y
CONFIG_SYS_EXTRA_OPTIONS="MIP405T"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_MIP405=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308RDB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8315ERDB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8323ERDB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349EMDS=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC837XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC837XEMDS=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC837XERDB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8540ADS=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8541CDS=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8541CDS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8544DS=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8548CDS=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8555CDS=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8555CDS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8568MDS=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="ATM"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8569MDS=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8572DS=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8610HPCD=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8641HPCN=y
CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8641HPCN=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
CONFIG_VIDEO_LCD_SSD2828_RESET="PA26"
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1022DS=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1023RDB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P4080DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P4080DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P4080DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_4xx=y
CONFIG_TARGET_PIP405=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_ALDO2_VOLT=1800
CONFIG_AXP_DLDO1_VOLT=3000
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T1040QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T1040QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T1040QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T208XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T208XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240RDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240RDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TQM834X=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_AUTOBOOT_STOP_STR="\x1b"
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_AUTOBOOT_STOP_STR="\x1b"
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_4xx=y
CONFIG_TARGET_VOM405=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_ACADIA=y
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_ADP_AG101P=y
CONFIG_SYS_PROMPT="NDS32 # "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DFU_TFTP=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
+CONFIG_SYS_NS16550=y
CONFIG_RSA=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_NFS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_PCI_TEGRA=y
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARCHES=y
CONFIG_DEFAULT_DEVICE_TREE="arches"
CONFIG_OF_CONTROL=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CLK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CLK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_BAMBOO=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+<<<<<<< HEAD
+CONFIG_SPI_FLASH_WINBOND=y
+=======
+CONFIG_PCI_TEGRA=y
+>>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_LIB_RAND=y
CONFIG_TARGET_BF527_EZKIT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_NET_TFTP_VARS is not set
CONFIG_SPI_FLASH=y
-CONFIG_NET_TFTP_VARS=n
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_LIB_RAND=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_BUBINGA=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NET is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_STOP_STR="\x0b"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+<<<<<<< HEAD
+CONFIG_SPI_FLASH_WINBOND=y
+=======
+CONFIG_PCI_TEGRA=y
+>>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ROCKCHIP_RK3288=y
CONFIG_TARGET_CHROMEBOOK_JERRY=y
CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry"
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_SPL_SYSCON=y
CONFIG_LED=y
CONFIG_SPL_LED=y
CONFIG_LED_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_NS16550=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_NS16550=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
CONFIG_DM=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_TPM=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
CONFIG_CMD_TPM=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TPM=y
CONFIG_DM=y
+CONFIG_SYS_NS16550=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TPM=y
CONFIG_DM=y
+CONFIG_SYS_NS16550=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
CONFIG_X86=y
CONFIG_VENDOR_COREBOOT=y
CONFIG_TARGET_COREBOOT=y
-CONFIG_TSC_CALIBRATION_BYPASS=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TPM_TEST=y
CONFIG_OF_CONTROL=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_PCH_GBE=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_4xx=y
CONFIG_TARGET_INTIP=y
CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_DLVISION=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DREAMPLUG=y
+CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
-CONFIG_CMD_SF=y
CONFIG_CMD_PING=y
-CONFIG_CMD_USB=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SPL=y
CONFIG_SYS_PROMPT="EDMiniV2> "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_VENDOR_EFI=y
CONFIG_DEFAULT_DEVICE_TREE="efi"
CONFIG_TARGET_EFI=y
-CONFIG_TSC_CALIBRATION_BYPASS=y
# CONFIG_CMD_BOOTM is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NET is not set
CONFIG_DEBUG_EFI_CONSOLE=y
CONFIG_DEBUG_UART_BASE=0
CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_ICH_SPI=y
# CONFIG_X86_SERIAL is not set
+CONFIG_TIMER=y
CONFIG_EFI=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ROCKCHIP_RK3036=y
+CONFIG_TARGET_EVB_RK3036=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CLK=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_RESET=y
+CONFIG_LED=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_ROCKCHIP_DWMMC=y
+CONFIG_ROCKCHIP_3036_PINCTRL=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_RAM=y
+CONFIG_DM_MMC=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
CONFIG_ROCKCHIP_RK3288=y
CONFIG_TARGET_FIREFLY_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_SPL_SYSCON=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_RESET=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_NS16550=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_GDPPC440ETX=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="glacier"
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_GURUPLUG=y
+CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_PING=y
-CONFIG_CMD_USB=y
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_KILAUEA=y
CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA"
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
-CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
-
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
+CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_IB62X0=y
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ib62x0 => "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_PING=y
-CONFIG_CMD_USB=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_ICON=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
CONFIG_AUTOBOOT_DELAY_STR="ids"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="INTIB"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_IO64=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_IOCON=y
+CONFIG_FIT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+<<<<<<< HEAD
+CONFIG_SPI_FLASH_WINBOND=y
+=======
+CONFIG_PCI_TEGRA=y
+>>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_KATMAI=y
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_KILAUEA=y
CONFIG_SYS_EXTRA_OPTIONS="KILAUEA"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC83xx=y
CONFIG_TARGET_KM8360=y
CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_KM8360=y
CONFIG_SYS_EXTRA_OPTIONS="KMETER1"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
-CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
+CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
+CONFIG_SYS_NS16550=y
-CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2"
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
+CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2"
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
+CONFIG_OF_CONTROL=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043AQDS=y
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_SYS_NS16550=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080A_EMU=y
+CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080A_SIMU=y
+CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A"
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080ARDB=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
-CONFIG_TARGET_LS2085A_EMU=y
-CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4"
+CONFIG_TARGET_LS2080A_EMU=y
+CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2085A"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
-CONFIG_TARGET_LS2085A_SIMU=y
-CONFIG_SYS_EXTRA_OPTIONS="SIMU"
+CONFIG_TARGET_LS2080A_SIMU=y
+CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2085A"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
-CONFIG_TARGET_LS2085AQDS=y
+CONFIG_TARGET_LS2080AQDS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-qds"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_ARM=y
-CONFIG_TARGET_LS2085AQDS=y
+CONFIG_TARGET_LS2080AQDS=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
-CONFIG_TARGET_LS2085ARDB=y
+CONFIG_TARGET_LS2080ARDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-rdb"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_ARM=y
-CONFIG_TARGET_LS2085ARDB=y
+CONFIG_TARGET_LS2080ARDB=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_LUAN=y
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_LWMON5=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_MAKALU=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_THERMAL=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_NS16550=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_SUNXI_NO_PMIC=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308_P1M=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_THERMAL=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_THERMAL=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_THERMAL=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_THERMAL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_NEO=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_TARGET_NSA310S=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_PROMPT="nsa310s => "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_USB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
+CONFIG_PCI_TEGRA=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65090=y
CONFIG_DM_REGULATOR=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_EXYNOS_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65090=y
CONFIG_DM_REGULATOR=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_EXYNOS_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="RAINIER"
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_REDWOOD=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_THERMAL=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_XPLAINED=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_XPLAINED=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
CONFIG_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
CONFIG_DEVRES=y
CONFIG_ADC=y
CONFIG_ADC_SANDBOX=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_TARGET_SBC8349=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_SBC8349=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,33"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,66"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC86xx=y
CONFIG_TARGET_SBC8641D=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA"
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_SHEEVAPLUG=y
+CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_PING=y
-CONFIG_CMD_USB=y
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_REGULATOR=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_DM_REGULATOR=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_EXYNOS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_BRIDGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM_I2C_COMPAT=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
+CONFIG_EXYNOS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_BRIDGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_PMIC_S5M8767=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_EXYNOS_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_CMD_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
-CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
+CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_TARGET_SOCRATES=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_PMIC_S5M8767=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_EXYNOS_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
-CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CADENCE_QSPI=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_WALNUT=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_T3CORP=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+<<<<<<< HEAD
+CONFIG_SPI_FLASH_WINBOND=y
+=======
+CONFIG_PCI_TEGRA=y
+>>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SFLASH=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="TUGE1"
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="TUXX1"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_VCT_PLATINUM=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_VCT_PREMIUM=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_VE8313=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_VME8349=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_WALNUT=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_4xx=y
CONFIG_TARGET_XPEDITE1000=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC86xx=y
CONFIG_TARGET_XPEDITE517X=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE520X=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE537X=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE550X=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_YOSEMITE=y
CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE"
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_YOSEMITE=y
CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE"
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_YUCCA=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_QSPI=y
memset(&gpt_e[i].attributes, 0,
sizeof(gpt_entry_attributes));
+ if (partitions[i].bootable)
+ gpt_e[i].attributes.fields.legacy_bios_bootable = 1;
+
/* partition name */
efiname_len = sizeof(gpt_e[i].partition_name)
/ sizeof(efi_char16_t);
return ret;
}
+static void gpt_convert_efi_name_to_char(char *s, efi_char16_t *es, int n)
+{
+ char *ess = (char *)es;
+ int i, j;
+
+ memset(s, '\0', n);
+
+ for (i = 0, j = 0; j < n; i += 2, j++) {
+ s[j] = ess[i];
+ if (!ess[i])
+ return;
+ }
+}
+
+int gpt_verify_headers(block_dev_desc_t *dev_desc, gpt_header *gpt_head,
+ gpt_entry **gpt_pte)
+{
+ /*
+ * This function validates AND
+ * fills in the GPT header and PTE
+ */
+ if (is_gpt_valid(dev_desc,
+ GPT_PRIMARY_PARTITION_TABLE_LBA,
+ gpt_head, gpt_pte) != 1) {
+ printf("%s: *** ERROR: Invalid GPT ***\n",
+ __func__);
+ return -1;
+ }
+ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
+ gpt_head, gpt_pte) != 1) {
+ printf("%s: *** ERROR: Invalid Backup GPT ***\n",
+ __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+int gpt_verify_partitions(block_dev_desc_t *dev_desc,
+ disk_partition_t *partitions, int parts,
+ gpt_header *gpt_head, gpt_entry **gpt_pte)
+{
+ char efi_str[PARTNAME_SZ + 1];
+ u64 gpt_part_size;
+ gpt_entry *gpt_e;
+ int ret, i;
+
+ ret = gpt_verify_headers(dev_desc, gpt_head, gpt_pte);
+ if (ret)
+ return ret;
+
+ gpt_e = *gpt_pte;
+
+ for (i = 0; i < parts; i++) {
+ if (i == gpt_head->num_partition_entries) {
+ error("More partitions than allowed!\n");
+ return -1;
+ }
+
+ /* Check if GPT and ENV partition names match */
+ gpt_convert_efi_name_to_char(efi_str, gpt_e[i].partition_name,
+ PARTNAME_SZ + 1);
+
+ debug("%s: part: %2d name - GPT: %16s, ENV: %16s ",
+ __func__, i, efi_str, partitions[i].name);
+
+ if (strncmp(efi_str, (char *)partitions[i].name,
+ sizeof(partitions->name))) {
+ error("Partition name: %s does not match %s!\n",
+ efi_str, (char *)partitions[i].name);
+ return -1;
+ }
+
+ /* Check if GPT and ENV sizes match */
+ gpt_part_size = le64_to_cpu(gpt_e[i].ending_lba) -
+ le64_to_cpu(gpt_e[i].starting_lba) + 1;
+ debug("size(LBA) - GPT: %8llu, ENV: %8llu ",
+ gpt_part_size, (u64) partitions[i].size);
+
+ if (le64_to_cpu(gpt_part_size) != partitions[i].size) {
+ error("Partition %s size: %llu does not match %llu!\n",
+ efi_str, gpt_part_size, (u64) partitions[i].size);
+ return -1;
+ }
+
+ /*
+ * Start address is optional - check only if provided
+ * in '$partition' variable
+ */
+ if (!partitions[i].start) {
+ debug("\n");
+ continue;
+ }
+
+ /* Check if GPT and ENV start LBAs match */
+ debug("start LBA - GPT: %8llu, ENV: %8llu\n",
+ le64_to_cpu(gpt_e[i].starting_lba),
+ (u64) partitions[i].start);
+
+ if (le64_to_cpu(gpt_e[i].starting_lba) != partitions[i].start) {
+ error("Partition %s start: %llu does not match %llu!\n",
+ efi_str, le64_to_cpu(gpt_e[i].starting_lba),
+ (u64) partitions[i].start);
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf)
{
gpt_header *gpt_h;
-Freescale ARM64 SoCs like LS2085A have ARM TrustZone components like
+Freescale ARM64 SoCs like LS2080A have ARM TrustZone components like
TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone
Address Space Controller).
privilege mode), but still some configurations of these peripherals
might be required while the bootloader is executing in EL3 privilege
mode. The following sections define how to turn on these features for
-LS2085A like SoCs.
+LS2080A like SoCs.
TZPC-BP147 (TrustZone Protection Controller)
============================================
Attribute flags:
Bit 0 - System partition
+ Bit 1 - Hide from EFI
+ Bit 2 - Legacy BIOS bootable
+ Bit 48-63 - Defined and used by the individual partition type
+ For Basic data partition :
Bit 60 - Read-only
Bit 62 - Hidden
Bit 63 - Not mount
The fields 'name' and 'size' are mandatory for every partition.
The field 'start' is optional.
+ If field 'size' of the last partition is 0, the partiton is extended
+ up to the end of the device.
+
The fields 'uuid' and 'uuid_disk' are optional if CONFIG_RANDOM_UUID is
enabled. A random uuid will be used if omitted or they point to an empty/
non-existent environment variable. The environment variable will be set to
the generated UUID.
+ The field 'bootable' is optional, it is used to mark the GPT partition
+ bootable (set attribute flags "Legacy BIOS bootable").
+ "name=u-boot,size=60MiB;name=boot,size=60Mib,bootable;name=rootfs,size=0"
+ It can be used to locate bootable disks with command
+ "part list <interface> <dev> -bootable <varname>",
+ please check out doc/README.distro for use.
+
2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT'
-2. From u-boot prompt type:
+3. From u-boot prompt type:
gpt write mmc 0 $partitions
+Checking (validating) GPT partitions in U-Boot:
+===============================================
+
+Procedure is the same as above. The only change is at point 3.
+
+At u-boot prompt one needs to write:
+ gpt verify mmc 0 [$partitions]
+
+where [$partitions] is an optional parameter.
+
+When it is not provided, only basic checks based on CRC32 calculation for GPT
+header and PTEs are performed.
+When provided, additionally partition data - name, size and starting
+offset (last two in LBA) - are compared with data defined in '$partitions'
+environment variable.
+
+After running this command, return code is set to 0 if no errors found in
+on non-volatile medium stored GPT.
+
+Following line can be used to assess if GPT verification has succeed:
+
+U-BOOT> gpt verify mmc 0 $partitions
+U-BOOT> if test $? = 0; then echo "GPT OK"; else echo "GPT ERR"; fi
+
+
Partition type GUID:
====================
- Radxa Rock 2 - also uses firefly-rk3288 configuration
- Haier Chromebook - use chromebook_jerry configuration
+one RK3036 board is support:
+
+ - EVB RK3036 - use evb-rk3036_defconfig configuration
+
For example:
CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all
Err: serial@ff690000
=>
+For evb_rk3036 board:
+ ./evb-rk3036/tools/mkimage -T rksd -d evb-rk3036/spl/u-boot-spl.bin out && \
+ cat evb-rk3036/u-boot-dtb.bin >> out && \
+ sudo dd if=out of=/dev/sdc seek=64
+
+Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, the
+ debug uart must be disabled
Booting from SPI
================
#
obj-$(CONFIG_CLK) += clk-uclass.o
+obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
--- /dev/null
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3036.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <dm/lists.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3036_clk_plat {
+ enum rk_clk_id clk_id;
+};
+
+struct rk3036_clk_priv {
+ struct rk3036_cru *cru;
+ ulong rate;
+};
+
+enum {
+ VCO_MAX_HZ = 2400U * 1000000,
+ VCO_MIN_HZ = 600 * 1000000,
+ OUTPUT_MAX_HZ = 2400U * 1000000,
+ OUTPUT_MIN_HZ = 24 * 1000000,
+};
+
+#define RATE_TO_DIV(input_rate, output_rate) \
+ ((input_rate) / (output_rate) - 1);
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
+ .refdiv = _refdiv,\
+ .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
+ .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
+ _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
+ OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
+ #hz "Hz cannot be hit with PLL "\
+ "divisors on line " __stringify(__LINE__));
+
+/* use interge mode*/
+static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
+
+static inline unsigned int log2(unsigned int value)
+{
+ return fls(value) - 1;
+}
+
+static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
+ const struct pll_div *div)
+{
+ int pll_id = rk_pll_id(clk_id);
+ struct rk3036_pll *pll = &cru->pll[pll_id];
+
+ /* All PLLs have same VCO and output frequency range restrictions. */
+ uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
+ uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
+
+ debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\
+ vco=%u Hz, output=%u Hz\n",
+ pll, div->fbdiv, div->refdiv, div->postdiv1,
+ div->postdiv2, vco_hz, output_hz);
+ assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
+ output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
+
+ /* use interger mode */
+ rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+
+ rk_clrsetreg(&pll->con0,
+ PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
+ (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
+ rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
+ PLL_REFDIV_MASK << PLL_REFDIV_SHIFT,
+ (div->postdiv2 << PLL_POSTDIV2_SHIFT |
+ div->refdiv << PLL_REFDIV_SHIFT));
+
+ /* waiting for pll lock */
+ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
+ udelay(1);
+
+ return 0;
+}
+
+static void rkclk_init(struct rk3036_cru *cru)
+{
+ u32 aclk_div;
+ u32 hclk_div;
+ u32 pclk_div;
+
+ /* pll enter slow-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK << GPLL_MODE_SHIFT |
+ APLL_MODE_MASK << APLL_MODE_SHIFT,
+ GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
+ APLL_MODE_SLOW << APLL_MODE_SHIFT);
+
+ /* init pll */
+ rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
+ rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
+
+ /*
+ * select apll as core clock pll source and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ * core hz : apll = 1:1
+ */
+ aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
+ assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
+
+ pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
+ assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
+
+ rk_clrsetreg(&cru->cru_clksel_con[0],
+ CORE_CLK_PLL_SEL_MASK << CORE_CLK_PLL_SEL_SHIFT |
+ CORE_DIV_CON_MASK << CORE_DIV_CON_SHIFT,
+ CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
+ 0 << CORE_DIV_CON_SHIFT);
+
+ rk_clrsetreg(&cru->cru_clksel_con[1],
+ CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT |
+ CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
+ aclk_div << CORE_ACLK_DIV_SHIFT |
+ pclk_div << CORE_PERI_DIV_SHIFT);
+
+ /*
+ * select apll as cpu clock pll source and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = APLL_HZ / CPU_ACLK_HZ - 1;
+ assert((aclk_div + 1) * CPU_ACLK_HZ == APLL_HZ && aclk_div < 0x1f);
+
+ pclk_div = APLL_HZ / CPU_PCLK_HZ - 1;
+ assert((pclk_div + 1) * CPU_PCLK_HZ == APLL_HZ && pclk_div < 0x7);
+
+ hclk_div = APLL_HZ / CPU_HCLK_HZ - 1;
+ assert((hclk_div + 1) * CPU_HCLK_HZ == APLL_HZ && hclk_div < 0x3);
+
+ rk_clrsetreg(&cru->cru_clksel_con[0],
+ CPU_CLK_PLL_SEL_MASK << CPU_CLK_PLL_SEL_SHIFT |
+ ACLK_CPU_DIV_MASK << ACLK_CPU_DIV_SHIFT,
+ CPU_CLK_PLL_SEL_APLL << CPU_CLK_PLL_SEL_SHIFT |
+ aclk_div << ACLK_CPU_DIV_SHIFT);
+
+ rk_clrsetreg(&cru->cru_clksel_con[1],
+ CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
+ CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
+ pclk_div << CPU_PCLK_DIV_SHIFT |
+ hclk_div << CPU_HCLK_DIV_SHIFT);
+
+ /*
+ * select gpll as peri clock pll source and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
+ assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+ hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
+ assert((1 << hclk_div) * PERI_HCLK_HZ ==
+ PERI_ACLK_HZ && (pclk_div < 0x4));
+
+ pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
+ assert((1 << pclk_div) * PERI_PCLK_HZ ==
+ PERI_ACLK_HZ && pclk_div < 0x8);
+
+ rk_clrsetreg(&cru->cru_clksel_con[10],
+ PERI_PLL_SEL_MASK << PERI_PLL_SEL_SHIFT |
+ PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
+ PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
+ PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
+ PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
+ pclk_div << PERI_PCLK_DIV_SHIFT |
+ hclk_div << PERI_HCLK_DIV_SHIFT |
+ aclk_div << PERI_ACLK_DIV_SHIFT);
+
+ /* PLL enter normal-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK << GPLL_MODE_SHIFT |
+ APLL_MODE_MASK << APLL_MODE_SHIFT,
+ GPLL_MODE_NORM << GPLL_MODE_SHIFT |
+ APLL_MODE_NORM << APLL_MODE_SHIFT);
+}
+
+/* Get pll rate by id */
+static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
+ enum rk_clk_id clk_id)
+{
+ uint32_t refdiv, fbdiv, postdiv1, postdiv2;
+ uint32_t con;
+ int pll_id = rk_pll_id(clk_id);
+ struct rk3036_pll *pll = &cru->pll[pll_id];
+ static u8 clk_shift[CLK_COUNT] = {
+ 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
+ GPLL_MODE_SHIFT, 0xff
+ };
+ static u8 clk_mask[CLK_COUNT] = {
+ 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
+ GPLL_MODE_MASK, 0xff
+ };
+ uint shift;
+ uint mask;
+
+ con = readl(&cru->cru_mode_con);
+ shift = clk_shift[clk_id];
+ mask = clk_mask[clk_id];
+
+ switch ((con >> shift) & mask) {
+ case GPLL_MODE_SLOW:
+ return OSC_HZ;
+ case GPLL_MODE_NORM:
+
+ /* normal mode */
+ con = readl(&pll->con0);
+ postdiv1 = (con >> PLL_POSTDIV1_SHIFT) & PLL_POSTDIV1_MASK;
+ fbdiv = (con >> PLL_FBDIV_SHIFT) & PLL_FBDIV_MASK;
+ con = readl(&pll->con1);
+ postdiv2 = (con >> PLL_POSTDIV2_SHIFT) & PLL_POSTDIV2_MASK;
+ refdiv = (con >> PLL_REFDIV_SHIFT) & PLL_REFDIV_MASK;
+ return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
+ case GPLL_MODE_DEEP:
+ default:
+ return 32768;
+ }
+}
+
+static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
+ enum periph_id periph)
+{
+ uint src_rate;
+ uint div, mux;
+ u32 con;
+
+ switch (periph) {
+ case PERIPH_ID_EMMC:
+ con = readl(&cru->cru_clksel_con[12]);
+ mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
+ div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
+ break;
+ case PERIPH_ID_SDCARD:
+ con = readl(&cru->cru_clksel_con[12]);
+ mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
+ div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
+ return DIV_TO_RATE(src_rate, div);
+}
+
+static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
+ enum periph_id periph, uint freq)
+{
+ int src_clk_div;
+ int mux;
+
+ debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
+
+ /* mmc clock auto divide 2 in internal */
+ src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
+
+ if (src_clk_div > 0x7f) {
+ src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
+ mux = EMMC_SEL_24M;
+ } else {
+ mux = EMMC_SEL_GPLL;
+ }
+
+ switch (periph) {
+ case PERIPH_ID_EMMC:
+ rk_clrsetreg(&cru->cru_clksel_con[12],
+ EMMC_PLL_MASK << EMMC_PLL_SHIFT |
+ EMMC_DIV_MASK << EMMC_DIV_SHIFT,
+ mux << EMMC_PLL_SHIFT |
+ (src_clk_div - 1) << EMMC_DIV_SHIFT);
+ break;
+ case PERIPH_ID_SDCARD:
+ rk_clrsetreg(&cru->cru_clksel_con[11],
+ MMC0_PLL_MASK << MMC0_PLL_SHIFT |
+ MMC0_DIV_MASK << MMC0_DIV_SHIFT,
+ mux << MMC0_PLL_SHIFT |
+ (src_clk_div - 1) << MMC0_DIV_SHIFT);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
+}
+
+static ulong rk3036_clk_get_rate(struct udevice *dev)
+{
+ struct rk3036_clk_plat *plat = dev_get_platdata(dev);
+ struct rk3036_clk_priv *priv = dev_get_priv(dev);
+
+ debug("%s\n", dev->name);
+ return rkclk_pll_get_rate(priv->cru, plat->clk_id);
+}
+
+static ulong rk3036_clk_set_rate(struct udevice *dev, ulong rate)
+{
+ debug("%s\n", dev->name);
+
+ return 0;
+}
+
+ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+{
+ struct rk3036_clk_priv *priv = dev_get_priv(dev);
+ ulong new_rate;
+
+ switch (periph) {
+ case PERIPH_ID_EMMC:
+ new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev),
+ periph, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return new_rate;
+}
+
+static struct clk_ops rk3036_clk_ops = {
+ .get_rate = rk3036_clk_get_rate,
+ .set_rate = rk3036_clk_set_rate,
+ .set_periph_rate = rk3036_set_periph_rate,
+};
+
+static int rk3036_clk_probe(struct udevice *dev)
+{
+ struct rk3036_clk_plat *plat = dev_get_platdata(dev);
+ struct rk3036_clk_priv *priv = dev_get_priv(dev);
+
+ if (plat->clk_id != CLK_OSC) {
+ struct rk3036_clk_priv *parent_priv = dev_get_priv(dev->parent);
+
+ priv->cru = parent_priv->cru;
+ return 0;
+ }
+ priv->cru = (struct rk3036_cru *)dev_get_addr(dev);
+ rkclk_init(priv->cru);
+
+ return 0;
+}
+
+static const char *const clk_name[] = {
+ "osc",
+ "apll",
+ "dpll",
+ "cpll",
+ "gpll",
+ "mpll",
+};
+
+static int rk3036_clk_bind(struct udevice *dev)
+{
+ struct rk3036_clk_plat *plat = dev_get_platdata(dev);
+ int pll, ret;
+
+ /* We only need to set up the root clock */
+ if (dev->of_offset == -1) {
+ plat->clk_id = CLK_OSC;
+ return 0;
+ }
+
+ /* Create devices for P main clocks */
+ for (pll = 1; pll < CLK_COUNT; pll++) {
+ struct udevice *child;
+ struct rk3036_clk_plat *cplat;
+
+ debug("%s %s\n", __func__, clk_name[pll]);
+ ret = device_bind_driver(dev, "clk_rk3036", clk_name[pll],
+ &child);
+ if (ret)
+ return ret;
+
+ cplat = dev_get_platdata(child);
+ cplat->clk_id = pll;
+ }
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(gd->dm_root, "rk3036_reset", "reset", &dev);
+ if (ret)
+ debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
+
+ return 0;
+}
+
+static const struct udevice_id rk3036_clk_ids[] = {
+ { .compatible = "rockchip,rk3036-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_rk3036) = {
+ .name = "clk_rk3036",
+ .id = UCLASS_CLK,
+ .of_match = rk3036_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
+ .platdata_auto_alloc_size = sizeof(struct rk3036_clk_plat),
+ .ops = &rk3036_clk_ops,
+ .bind = rk3036_clk_bind,
+ .probe = rk3036_clk_probe,
+};
support any bus type (I2C, SPI) but so far this only supports
direct memory access.
+config SPL_REGMAP
+ bool "Support register maps in SPL"
+ depends on DM
+ help
+ Hardware peripherals tend to have one or more sets of registers
+ which can be accessed to control the hardware. A register map
+ models this with a simple read/write interface. It can in principle
+ support any bus type (I2C, SPI) but so far this only supports
+ direct memory access.
+
config SYSCON
bool "Support system controllers"
depends on REGMAP
by this uclass, including accessing registers via regmap and
assigning a unique number to each.
+config SPL_SYSCON
+ bool "Support system controllers in SPL"
+ depends on REGMAP
+ help
+ Many SoCs have a number of system controllers which are dealt with
+ as a group by a single driver. Some common functionality is provided
+ by this uclass, including accessing registers via regmap and
+ assigning a unique number to each.
+
config DEVRES
bool "Managed device resources"
depends on DM
obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o
obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o
obj-$(CONFIG_DM) += dump.o
-obj-$(CONFIG_REGMAP) += regmap.o
-obj-$(CONFIG_SYSCON) += syscon-uclass.o
+obj-$(CONFIG_$(SPL_)REGMAP) += regmap.o
+obj-$(CONFIG_$(SPL_)SYSCON) += syscon-uclass.o
goto step2;
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
/* A008336 only applies to general DDR controllers */
if ((ctrl_num == 0) || (ctrl_num == 1))
#endif
ddr_out32(eddrtqcr1, 0x63b30002);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
/* A008514 only applies to DP-DDR controler */
if (ctrl_num == 2)
#endif
if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
puts("Running BIST test. This will take a while...");
cs0_config = ddr_in32(&ddr->cs0_config);
+ cs0_bnds = ddr_in32(&ddr->cs0_bnds);
+ cs1_bnds = ddr_in32(&ddr->cs1_bnds);
+ cs2_bnds = ddr_in32(&ddr->cs2_bnds);
+ cs3_bnds = ddr_in32(&ddr->cs3_bnds);
if (cs0_config & CTLR_INTLV_MASK) {
- cs0_bnds = ddr_in32(&cs0_bnds);
- cs1_bnds = ddr_in32(&cs1_bnds);
- cs2_bnds = ddr_in32(&cs2_bnds);
- cs3_bnds = ddr_in32(&cs3_bnds);
/* set bnds to non-interleaving */
- ddr_out32(&cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
- ddr_out32(&cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
- ddr_out32(&cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
- ddr_out32(&cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
+ ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
+ ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
+ ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
+ ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
}
ddr_out32(&ddr->mtp1, BIST_PATTERN1);
ddr_out32(&ddr->mtp2, BIST_PATTERN1);
if (cs0_config & CTLR_INTLV_MASK) {
/* restore bnds registers */
- ddr_out32(&cs0_bnds, cs0_bnds);
- ddr_out32(&cs1_bnds, cs1_bnds);
- ddr_out32(&cs2_bnds, cs2_bnds);
- ddr_out32(&cs3_bnds, cs3_bnds);
+ ddr_out32(&ddr->cs0_bnds, cs0_bnds);
+ ddr_out32(&ddr->cs1_bnds, cs1_bnds);
+ ddr_out32(&ddr->cs2_bnds, cs2_bnds);
+ ddr_out32(&ddr->cs3_bnds, cs3_bnds);
}
}
#endif
info.board_need_mem_reset = board_need_mem_reset;
info.board_mem_reset = board_assert_mem_reset;
info.board_mem_de_reset = board_deassert_mem_reset;
+ remove_unused_controllers(&info);
return __fsl_ddr_sdram(&info);
}
ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
}
#endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
+
+void remove_unused_controllers(fsl_ddr_info_t *info)
+{
+#ifdef CONFIG_FSL_LSCH3
+ int i;
+ u64 nodeid;
+ void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
+ bool ddr0_used = false;
+ bool ddr1_used = false;
+
+ for (i = 0; i < 8; i++) {
+ nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
+ if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
+ ddr0_used = true;
+ } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
+ ddr1_used = true;
+ } else {
+ printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
+ nodeid);
+ }
+ hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
+ }
+ if (!ddr0_used && !ddr1_used) {
+ printf("Invalid configuration in HN-F SAM control\n");
+ return;
+ }
+
+ if (!ddr0_used && info->first_ctrl == 0) {
+ info->first_ctrl = 1;
+ info->num_ctrls = 1;
+ debug("First DDR controller disabled\n");
+ return;
+ }
+
+ if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
+ info->num_ctrls = 1;
+ debug("Second DDR controller disabled\n");
+ }
+#endif
+}
help
Support for the Designware APB GPIO driver.
+config ATMEL_PIO4
+ bool "ATMEL PIO4 driver"
+ depends on DM
+ default n
+ help
+ Say yes here to support the Atmel PIO4 driver.
+ The PIO4 is new version of Atmel PIO controller, which manages
+ up to 128 fully programmable input/output lines. Each I/O line
+ may be dedicated as a general purpose I/O or be assigned to
+ a function of an embedded peripheral.
+
config LPC32XX_GPIO
bool "LPC32XX GPIO driver"
depends on DM
obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
+obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o
obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
obj-$(CONFIG_KONA_GPIO) += kona_gpio.o
--- /dev/null
+/*
+ * Atmel PIO4 device driver
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/hardware.h>
+#include <mach/gpio.h>
+#include <mach/atmel_pio4.h>
+
+#define ATMEL_PIO4_PINS_PER_BANK 32
+
+/*
+ * Register Field Definitions
+ */
+#define ATMEL_PIO4_CFGR_FUNC (0x7 << 0)
+#define ATMEL_PIO4_CFGR_FUNC_GPIO (0x0 << 0)
+#define ATMEL_PIO4_CFGR_FUNC_PERIPH_A (0x1 << 0)
+#define ATMEL_PIO4_CFGR_FUNC_PERIPH_B (0x2 << 0)
+#define ATMEL_PIO4_CFGR_FUNC_PERIPH_C (0x3 << 0)
+#define ATMEL_PIO4_CFGR_FUNC_PERIPH_D (0x4 << 0)
+#define ATMEL_PIO4_CFGR_FUNC_PERIPH_E (0x5 << 0)
+#define ATMEL_PIO4_CFGR_FUNC_PERIPH_F (0x6 << 0)
+#define ATMEL_PIO4_CFGR_FUNC_PERIPH_G (0x7 << 0)
+#define ATMEL_PIO4_CFGR_DIR (0x1 << 8)
+#define ATMEL_PIO4_CFGR_PUEN (0x1 << 9)
+#define ATMEL_PIO4_CFGR_PDEN (0x1 << 10)
+#define ATMEL_PIO4_CFGR_IFEN (0x1 << 12)
+#define ATMEL_PIO4_CFGR_IFSCEN (0x1 << 13)
+#define ATMEL_PIO4_CFGR_OPD (0x1 << 14)
+#define ATMEL_PIO4_CFGR_SCHMITT (0x1 << 15)
+#define ATMEL_PIO4_CFGR_DRVSTR (0x3 << 16)
+#define ATMEL_PIO4_CFGR_DRVSTR_LOW0 (0x0 << 16)
+#define ATMEL_PIO4_CFGR_DRVSTR_LOW1 (0x1 << 16)
+#define ATMEL_PIO4_CFGR_DRVSTR_MEDIUM (0x2 << 16)
+#define ATMEL_PIO4_CFGR_DRVSTR_HIGH (0x3 << 16)
+#define ATMEL_PIO4_CFGR_EVTSEL (0x7 << 24)
+#define ATMEL_PIO4_CFGR_EVTSEL_FALLING (0x0 << 24)
+#define ATMEL_PIO4_CFGR_EVTSEL_RISING (0x1 << 24)
+#define ATMEL_PIO4_CFGR_EVTSEL_BOTH (0x2 << 24)
+#define ATMEL_PIO4_CFGR_EVTSEL_LOW (0x3 << 24)
+#define ATMEL_PIO4_CFGR_EVTSEL_HIGH (0x4 << 24)
+#define ATMEL_PIO4_CFGR_PCFS (0x1 << 29)
+#define ATMEL_PIO4_CFGR_ICFS (0x1 << 30)
+
+static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
+{
+ struct atmel_pio4_port *base = NULL;
+
+ switch (port) {
+ case AT91_PIO_PORTA:
+ base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
+ break;
+ case AT91_PIO_PORTB:
+ base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
+ break;
+ case AT91_PIO_PORTC:
+ base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
+ break;
+ case AT91_PIO_PORTD:
+ base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
+ break;
+ default:
+ printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
+ port);
+ break;
+ }
+
+ return base;
+}
+
+static int atmel_pio4_config_io_func(u32 port, u32 pin,
+ u32 func, u32 use_pullup)
+{
+ struct atmel_pio4_port *port_base;
+ u32 reg, mask;
+
+ if (pin >= ATMEL_PIO4_PINS_PER_BANK)
+ return -ENODEV;
+
+ port_base = atmel_pio4_port_base(port);
+ if (!port_base)
+ return -ENODEV;
+
+ mask = 1 << pin;
+ reg = func;
+ reg |= use_pullup ? ATMEL_PIO4_CFGR_PUEN : 0;
+
+ writel(mask, &port_base->mskr);
+ writel(reg, &port_base->cfgr);
+
+ return 0;
+}
+
+int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup)
+{
+ return atmel_pio4_config_io_func(port, pin,
+ ATMEL_PIO4_CFGR_FUNC_GPIO,
+ use_pullup);
+}
+
+int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup)
+{
+ return atmel_pio4_config_io_func(port, pin,
+ ATMEL_PIO4_CFGR_FUNC_PERIPH_A,
+ use_pullup);
+}
+
+int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup)
+{
+ return atmel_pio4_config_io_func(port, pin,
+ ATMEL_PIO4_CFGR_FUNC_PERIPH_B,
+ use_pullup);
+}
+
+int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup)
+{
+ return atmel_pio4_config_io_func(port, pin,
+ ATMEL_PIO4_CFGR_FUNC_PERIPH_C,
+ use_pullup);
+}
+
+int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup)
+{
+ return atmel_pio4_config_io_func(port, pin,
+ ATMEL_PIO4_CFGR_FUNC_PERIPH_D,
+ use_pullup);
+}
+
+int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup)
+{
+ return atmel_pio4_config_io_func(port, pin,
+ ATMEL_PIO4_CFGR_FUNC_PERIPH_E,
+ use_pullup);
+}
+
+int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup)
+{
+ return atmel_pio4_config_io_func(port, pin,
+ ATMEL_PIO4_CFGR_FUNC_PERIPH_F,
+ use_pullup);
+}
+
+int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup)
+{
+ return atmel_pio4_config_io_func(port, pin,
+ ATMEL_PIO4_CFGR_FUNC_PERIPH_G,
+ use_pullup);
+}
+
+int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
+{
+ struct atmel_pio4_port *port_base;
+ u32 reg, mask;
+
+ if (pin >= ATMEL_PIO4_PINS_PER_BANK)
+ return -ENODEV;
+
+ port_base = atmel_pio4_port_base(port);
+ if (!port_base)
+ return -ENODEV;
+
+ mask = 0x01 << pin;
+ reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR;
+
+ writel(mask, &port_base->mskr);
+ writel(reg, &port_base->cfgr);
+
+ if (value)
+ writel(mask, &port_base->sodr);
+ else
+ writel(mask, &port_base->codr);
+
+ return 0;
+}
+
+int atmel_pio4_get_pio_input(u32 port, u32 pin)
+{
+ struct atmel_pio4_port *port_base;
+ u32 reg, mask;
+
+ if (pin >= ATMEL_PIO4_PINS_PER_BANK)
+ return -ENODEV;
+
+ port_base = atmel_pio4_port_base(port);
+ if (!port_base)
+ return -ENODEV;
+
+ mask = 0x01 << pin;
+ reg = ATMEL_PIO4_CFGR_FUNC_GPIO;
+
+ writel(mask, &port_base->mskr);
+ writel(reg, &port_base->cfgr);
+
+ return (readl(&port_base->pdsr) & mask) ? 1 : 0;
+}
+
+#ifdef CONFIG_DM_GPIO
+static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct at91_port_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
+ u32 mask = 0x01 << offset;
+ u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO;
+
+ writel(mask, &port_base->mskr);
+ writel(reg, &port_base->cfgr);
+
+ return 0;
+}
+
+static int atmel_pio4_direction_output(struct udevice *dev,
+ unsigned offset, int value)
+{
+ struct at91_port_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
+ u32 mask = 0x01 << offset;
+ u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR;
+
+ writel(mask, &port_base->mskr);
+ writel(reg, &port_base->cfgr);
+
+ if (value)
+ writel(mask, &port_base->sodr);
+ else
+ writel(mask, &port_base->codr);
+
+ return 0;
+}
+
+static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
+{
+ struct at91_port_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
+ u32 mask = 0x01 << offset;
+
+ return (readl(&port_base->pdsr) & mask) ? 1 : 0;
+}
+
+static int atmel_pio4_set_value(struct udevice *dev,
+ unsigned offset, int value)
+{
+ struct at91_port_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
+ u32 mask = 0x01 << offset;
+
+ if (value)
+ writel(mask, &port_base->sodr);
+ else
+ writel(mask, &port_base->codr);
+
+ return 0;
+}
+
+static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
+{
+ struct at91_port_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
+ u32 mask = 0x01 << offset;
+
+ writel(mask, &port_base->mskr);
+
+ return (readl(&port_base->cfgr) &
+ ATMEL_PIO4_CFGR_DIR) ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops atmel_pio4_ops = {
+ .direction_input = atmel_pio4_direction_input,
+ .direction_output = atmel_pio4_direction_output,
+ .get_value = atmel_pio4_get_value,
+ .set_value = atmel_pio4_set_value,
+ .get_function = atmel_pio4_get_function,
+};
+
+static int atmel_pio4_probe(struct udevice *dev)
+{
+ struct at91_port_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->bank_name = plat->bank_name;
+ uc_priv->gpio_count = ATMEL_PIO4_PINS_PER_BANK;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(gpio_atmel_pio4) = {
+ .name = "gpio_atmel_pio4",
+ .id = UCLASS_GPIO,
+ .ops = &atmel_pio4_ops,
+ .probe = atmel_pio4_probe,
+};
+#endif
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
-obj-y += muxes/
+obj-$(CONFIG_I2C_MUX) += muxes/
dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
}
+static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
+{
+ int ret = 0;
+ u32 timeout = 240000;
+ u32 mask, size, i, len = 0;
+ u32 *buf = NULL;
+ ulong start = get_timer(0);
+ u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
+ RX_WMARK_SHIFT) + 1) * 2;
+
+ size = data->blocksize * data->blocks / 4;
+ if (data->flags == MMC_DATA_READ)
+ buf = (unsigned int *)data->dest;
+ else
+ buf = (unsigned int *)data->src;
+
+ for (;;) {
+ mask = dwmci_readl(host, DWMCI_RINTSTS);
+ /* Error during data transfer. */
+ if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
+ debug("%s: DATA ERROR!\n", __func__);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (host->fifo_mode && size) {
+ if (data->flags == MMC_DATA_READ) {
+ if ((dwmci_readl(host, DWMCI_RINTSTS) &&
+ DWMCI_INTMSK_RXDR)) {
+ len = dwmci_readl(host, DWMCI_STATUS);
+ len = (len >> DWMCI_FIFO_SHIFT) &
+ DWMCI_FIFO_MASK;
+ for (i = 0; i < len; i++)
+ *buf++ =
+ dwmci_readl(host, DWMCI_DATA);
+ dwmci_writel(host, DWMCI_RINTSTS,
+ DWMCI_INTMSK_RXDR);
+ }
+ } else {
+ if ((dwmci_readl(host, DWMCI_RINTSTS) &&
+ DWMCI_INTMSK_TXDR)) {
+ len = dwmci_readl(host, DWMCI_STATUS);
+ len = fifo_depth - ((len >>
+ DWMCI_FIFO_SHIFT) &
+ DWMCI_FIFO_MASK);
+ for (i = 0; i < len; i++)
+ dwmci_writel(host, DWMCI_DATA,
+ *buf++);
+ dwmci_writel(host, DWMCI_RINTSTS,
+ DWMCI_INTMSK_TXDR);
+ }
+ }
+ size = size > len ? (size - len) : 0;
+ }
+
+ /* Data arrived correctly. */
+ if (mask & DWMCI_INTMSK_DTO) {
+ ret = 0;
+ break;
+ }
+
+ /* Check for timeout. */
+ if (get_timer(start) > timeout) {
+ debug("%s: Timeout waiting for data!\n",
+ __func__);
+ ret = TIMEOUT;
+ break;
+ }
+ }
+
+ dwmci_writel(host, DWMCI_RINTSTS, mask);
+
+ return ret;
+}
+
static int dwmci_set_transfer_mode(struct dwmci_host *host,
struct mmc_data *data)
{
dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
if (data) {
- if (data->flags == MMC_DATA_READ) {
- bounce_buffer_start(&bbstate, (void*)data->dest,
- data->blocksize *
- data->blocks, GEN_BB_WRITE);
+ if (host->fifo_mode) {
+ dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
+ dwmci_writel(host, DWMCI_BYTCNT,
+ data->blocksize * data->blocks);
+ dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
} else {
- bounce_buffer_start(&bbstate, (void*)data->src,
- data->blocksize *
- data->blocks, GEN_BB_READ);
+ if (data->flags == MMC_DATA_READ) {
+ bounce_buffer_start(&bbstate, (void*)data->dest,
+ data->blocksize *
+ data->blocks, GEN_BB_WRITE);
+ } else {
+ bounce_buffer_start(&bbstate, (void*)data->src,
+ data->blocksize *
+ data->blocks, GEN_BB_READ);
+ }
+ dwmci_prepare_data(host, data, cur_idmac,
+ bbstate.bounce_buffer);
}
- dwmci_prepare_data(host, data, cur_idmac,
- bbstate.bounce_buffer);
}
dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
}
if (data) {
- start = get_timer(0);
- timeout = 240000;
- for (;;) {
- mask = dwmci_readl(host, DWMCI_RINTSTS);
- /* Error during data transfer. */
- if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
- debug("%s: DATA ERROR!\n", __func__);
- ret = -EINVAL;
- break;
- }
-
- /* Data arrived correctly. */
- if (mask & DWMCI_INTMSK_DTO) {
- ret = 0;
- break;
- }
-
- /* Check for timeout. */
- if (get_timer(start) > timeout) {
- debug("%s: Timeout waiting for data!\n",
- __func__);
- ret = TIMEOUT;
- break;
- }
+ ret = dwmci_data_transfer(host, data);
+
+ /* only dma mode need it */
+ if (!host->fifo_mode) {
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ ctrl &= ~(DWMCI_DMA_EN);
+ dwmci_writel(host, DWMCI_CTRL, ctrl);
+ bounce_buffer_stop(&bbstate);
}
-
- dwmci_writel(host, DWMCI_RINTSTS, mask);
-
- ctrl = dwmci_readl(host, DWMCI_CTRL);
- ctrl &= ~(DWMCI_DMA_EN);
- dwmci_writel(host, DWMCI_CTRL, ctrl);
-
- bounce_buffer_stop(&bbstate);
}
udelay(100);
host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
host->priv = dev;
- /* TODO(sjg@chromium.org): Remove the need for this hack */
- host->dev_index = (ulong)host->ioaddr == 0xff0f0000 ? 0 : 1;
+ /* use non-removeable as sdcard and emmc as judgement */
+ if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
+ host->dev_index = 1;
return 0;
}
struct dwmci_host *host = &priv->host;
u32 minmax[2];
int ret;
+ int fifo_depth;
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (IS_ERR(priv->grf))
if (ret)
return ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
- "clock-freq-min-max", minmax, 2);
- if (!ret)
- ret = add_dwmci(host, minmax[1], minmax[0]);
+ if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ "clock-freq-min-max", minmax, 2))
+ return -EINVAL;
+
+ fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "fifo-depth", 0);
+ if (fifo_depth < 0)
+ return -EINVAL;
+
+ host->fifoth_val = MSIZE(0x2) |
+ RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
+
+ if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode"))
+ host->fifo_mode = true;
+
+ ret = add_dwmci(host, minmax[1], minmax[0]);
if (ret)
return ret;
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
-static void socfpga_dwmci_clksel(struct dwmci_host *host)
-{
+/* socfpga implmentation specific drver private data */
+struct dwmci_socfpga_priv_data {
unsigned int drvsel;
unsigned int smplsel;
+};
+
+static void socfpga_dwmci_clksel(struct dwmci_host *host)
+{
+ struct dwmci_socfpga_priv_data *priv = host->priv;
/* Disable SDMMC clock. */
clrbits_le32(&clock_manager_base->per_pll.en,
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
- /* Configures drv_sel and smpl_sel */
- drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
- smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
-
- debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
- writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
+ debug("%s: drvsel %d smplsel %d\n", __func__,
+ priv->drvsel, priv->smplsel);
+ writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
&system_manager_base->sdmmcgrp_ctrl);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
const unsigned long clk = cm_get_mmc_controller_clk_hz();
struct dwmci_host *host;
+ struct dwmci_socfpga_priv_data *priv;
fdt_addr_t reg_base;
int bus_width, fifo_depth;
if (!host)
return -ENOMEM;
+ /* Allocate the priv */
+ priv = calloc(1, sizeof(*priv));
+ if (!priv) {
+ free(host);
+ return -ENOMEM;
+ }
+
host->name = "SOCFPGA DWMMC";
host->ioaddr = (void *)reg_base;
host->buswidth = bus_width;
host->bus_hz = clk;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
+ priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3);
+ priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
+ host->priv = priv;
return add_dwmci(host, host->bus_hz, 400000);
}
dpmng.o \
dprc.o \
dpbp.o \
- dpni.o
+ dpni.o \
+ dpmac.o
obj-y += dpio/
return mc_send_command(mc_io, &cmd);
}
+int dpbp_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpbp_cfg *cfg,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ (void)(cfg); /* unused */
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE,
+ cmd_flags,
+ 0);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpbp_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
int dpbp_enable(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
return mc_send_command(mc_io, &cmd);
}
+int dpio_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpio_cfg *cfg,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_CREATE,
+ cmd_flags,
+ 0);
+ DPIO_CMD_CREATE(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpio_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPIO_CMDID_DESTROY,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
int dpio_enable(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token)
--- /dev/null
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dpmac.h>
+
+int dpmac_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int dpmac_id,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN,
+ cmd_flags,
+ 0);
+ DPMAC_CMD_OPEN(cmd, dpmac_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return err;
+}
+
+int dpmac_close(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpmac_cfg *cfg,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE,
+ cmd_flags,
+ 0);
+ DPMAC_CMD_CREATE(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpmac_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_get_attributes(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_attr *attr)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPMAC_RSP_GET_ATTRIBUTES(cmd, attr);
+
+ return 0;
+}
+
+int dpmac_mdio_read(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_mdio_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_READ,
+ cmd_flags,
+ token);
+ DPMAC_CMD_MDIO_READ(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPMAC_RSP_MDIO_READ(cmd, cfg->data);
+
+ return 0;
+}
+
+int dpmac_mdio_write(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_mdio_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_WRITE,
+ cmd_flags,
+ token);
+ DPMAC_CMD_MDIO_WRITE(cmd, cfg);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_link_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+ int err = 0;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ DPMAC_RSP_GET_LINK_CFG(cmd, cfg);
+
+ return 0;
+}
+
+int dpmac_set_link_state(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_link_state *link_state)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE,
+ cmd_flags,
+ token);
+ DPMAC_CMD_SET_LINK_STATE(cmd, link_state);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpmac_get_counter(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpmac_counter type,
+ uint64_t *counter)
+{
+ struct mc_command cmd = { 0 };
+ int err = 0;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER,
+ cmd_flags,
+ token);
+ DPMAC_CMD_GET_COUNTER(cmd, type);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ DPMAC_RSP_GET_COUNTER(cmd, *counter);
+
+ return 0;
+}
return mc_send_command(mc_io, &cmd);
}
+int dpni_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpni_cfg *cfg,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE,
+ cmd_flags,
+ 0);
+ DPNI_CMD_CREATE(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpni_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
int dpni_set_pools(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token,
return mc_send_command(mc_io, &cmd);
}
+int dprc_create_container(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dprc_cfg *cfg,
+ int *child_container_id,
+ uint64_t *child_portal_paddr)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ DPRC_CMD_CREATE_CONTAINER(cmd, cfg);
+
+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPRC_RSP_CREATE_CONTAINER(cmd, *child_container_id,
+ *child_portal_paddr);
+
+ return 0;
+}
+
+int dprc_destroy_container(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int child_container_id)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT,
+ cmd_flags,
+ token);
+ DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
int dprc_reset_container(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t token,
#include <fsl-mc/fsl_dpmng.h>
#include <fsl-mc/fsl_dprc.h>
#include <fsl-mc/fsl_dpio.h>
+#include <fsl-mc/fsl_dpni.h>
#include <fsl-mc/fsl_qbman_portal.h>
+#include <fsl-mc/ldpaa_wriop.h>
#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
DECLARE_GLOBAL_DATA_PTR;
-static int mc_boot_status;
-struct fsl_mc_io *dflt_mc_io = NULL;
+static int mc_boot_status = -1;
+static int mc_dpl_applied = -1;
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+static int mc_aiop_applied = -1;
+#endif
+struct fsl_mc_io *root_mc_io = NULL;
+struct fsl_mc_io *dflt_mc_io = NULL; /* child container */
+uint16_t root_dprc_handle = 0;
uint16_t dflt_dprc_handle = 0;
+int child_dprc_id;
struct fsl_dpbp_obj *dflt_dpbp = NULL;
struct fsl_dpio_obj *dflt_dpio = NULL;
-uint16_t dflt_dpio_handle = 0;
+struct fsl_dpni_obj *dflt_dpni = NULL;
#ifdef DEBUG
void dump_ram_words(const char *title, void *addr)
* Returns 0 on success and a negative errno on error.
* task fail.
**/
-int parse_mc_firmware_fit_image(const void **raw_image_addr,
+int parse_mc_firmware_fit_image(u64 mc_fw_addr,
+ const void **raw_image_addr,
size_t *raw_image_size)
{
int format;
size_t size;
const char *uname = "firmware";
- /* Check if the image is in NOR flash */
-#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR
- fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR;
-#else
-#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined"
-#endif
+ fit_hdr = (void *)mc_fw_addr;
/* Check if Image is in FIT format */
format = genimg_get_format(fit_hdr);
if (format != IMAGE_FORMAT_FIT) {
- printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n");
+ printf("fsl-mc: ERR: Bad firmware image (not a FIT image)\n");
return -EINVAL;
}
if (!fit_check_format(fit_hdr)) {
- printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n");
+ printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n");
return -EINVAL;
}
node_offset = fit_image_get_node(fit_hdr, uname);
if (node_offset < 0) {
- printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n");
+ printf("fsl-mc: ERR: Bad firmware image (missing subimage)\n");
return -ENOENT;
}
/* Verify MC firmware image */
if (!(fit_image_verify(fit_hdr, node_offset))) {
- printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n");
+ printf("fsl-mc: ERR: Bad firmware image (bad CRC)\n");
return -EINVAL;
}
return 0;
}
-static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size)
+static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr)
{
u64 mc_dpc_offset;
#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
/*
* Get address and size of the DPC blob stored in flash:
*/
-#ifdef CONFIG_SYS_LS_MC_DPC_IN_NOR
- dpc_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPC_ADDR;
-#else
-#error "No CONFIG_SYS_LS_MC_DPC_IN_xxx defined"
-#endif
+ dpc_fdt_hdr = (void *)mc_dpc_addr;
error = fdt_check_header(dpc_fdt_hdr);
if (error != 0) {
return 0;
}
-static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size)
+static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr)
{
u64 mc_dpl_offset;
#ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
/*
* Get address and size of the DPL blob stored in flash:
*/
-#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
- dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
-#else
-#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
-#endif
+ dpl_fdt_hdr = (void *)mc_dpl_addr;
error = fdt_check_header(dpl_fdt_hdr);
if (error != 0) {
return timeout_ms;
}
-#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
-static int load_mc_aiop_img(u64 mc_ram_addr, size_t mc_ram_size)
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+static int load_mc_aiop_img(u64 aiop_fw_addr)
{
+ u64 mc_ram_addr = mc_get_dram_addr();
+#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
void *aiop_img;
+#endif
/*
* Load the MC AIOP image in the MC private DRAM block:
*/
- aiop_img = (void *)CONFIG_SYS_LS_MC_AIOP_IMG_ADDR;
+#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
+ printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr +
+ CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+#else
+ aiop_img = (void *)aiop_fw_addr;
mc_copy_image("MC AIOP image",
(u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
+#endif
+ mc_aiop_applied = 0;
return 0;
}
#endif
+
static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
{
u32 reg_gsr;
return 0;
}
-int mc_init(void)
+int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
{
int error = 0;
int portal_id = 0;
struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
- u64 mc_ram_addr;
+ u64 mc_ram_addr = mc_get_dram_addr();
u32 reg_gsr;
u32 reg_mcfbalr;
#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
u8 mc_ram_num_256mb_blocks;
size_t mc_ram_size = mc_get_dram_block_size();
- /*
- * The MC private DRAM block was already carved at the end of DRAM
- * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
- */
- if (gd->bd->bi_dram[1].start) {
- mc_ram_addr =
- gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
- } else {
- mc_ram_addr =
- gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
- }
error = calculate_mc_private_ram_params(mc_ram_addr,
mc_ram_size,
#ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
#else
- error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size);
+ error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr,
+ &raw_image_size);
if (error != 0)
goto out;
/*
#endif
dump_ram_words("firmware", (void *)mc_ram_addr);
- error = load_mc_dpc(mc_ram_addr, mc_ram_size);
+ error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr);
if (error != 0)
goto out;
- error = load_mc_dpl(mc_ram_addr, mc_ram_size);
- if (error != 0)
- goto out;
-
-#ifdef CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
- error = load_mc_aiop_img(mc_ram_addr, mc_ram_size);
- if (error != 0)
- goto out;
-#endif
-
debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
dump_mc_ccsr_regs(mc_ccsr_regs);
* Initialize the global default MC portal
* And check that the MC firmware is responding portal commands:
*/
- dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
- if (!dflt_mc_io) {
+ root_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
+ if (!root_mc_io) {
printf(" No memory: malloc() failed\n");
return -ENOMEM;
}
- dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
+ root_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
- portal_id, dflt_mc_io->mmio_regs);
+ portal_id, root_mc_io->mmio_regs);
- error = mc_get_version(dflt_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info);
+ error = mc_get_version(root_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info);
if (error != 0) {
printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
error);
mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
reg_gsr & GSR_FS_MASK);
+out:
+ if (error != 0)
+ mc_boot_status = error;
+ else
+ mc_boot_status = 0;
+
+ return error;
+}
+
+int mc_apply_dpl(u64 mc_dpl_addr)
+{
+ struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
+ int error = 0;
+ u32 reg_gsr;
+ u64 mc_ram_addr = mc_get_dram_addr();
+ size_t mc_ram_size = mc_get_dram_block_size();
+
+ error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr);
+ if (error != 0)
+ return error;
+
/*
* Tell the MC to deploy the DPL:
*/
out_le32(&mc_ccsr_regs->reg_gsr, 0x0);
printf("fsl-mc: Deploying data path layout ... ");
error = wait_for_mc(false, ®_gsr);
- if (error != 0)
- goto out;
-out:
- if (error != 0)
- mc_boot_status = error;
- else
- mc_boot_status = 0;
+ if (!error)
+ mc_dpl_applied = 0;
return error;
}
return mc_boot_status;
}
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+int get_aiop_apply_status(void)
+{
+ return mc_aiop_applied;
+}
+#endif
+
+int get_dpl_apply_status(void)
+{
+ return mc_dpl_applied;
+}
+
+/**
+ * Return the MC address of private DRAM block.
+ */
+u64 mc_get_dram_addr(void)
+{
+ u64 mc_ram_addr;
+
+ /*
+ * The MC private DRAM block was already carved at the end of DRAM
+ * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
+ */
+ if (gd->bd->bi_dram[1].start) {
+ mc_ram_addr =
+ gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
+ } else {
+ mc_ram_addr =
+ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
+ }
+
+ return mc_ram_addr;
+}
+
/**
* Return the actual size of the MC private DRAM block.
*/
return dram_block_size;
}
-int dpio_init(struct dprc_obj_desc obj_desc)
+int fsl_mc_ldpaa_init(bd_t *bis)
+{
+ int i;
+
+ for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++)
+ if ((wriop_is_enabled_dpmac(i) == 1) &&
+ (wriop_get_phy_address(i) != -1))
+ ldpaa_eth_init(i, wriop_get_enet_if(i));
+ return 0;
+}
+
+static int dpio_init(void)
{
struct qbman_swp_desc p_des;
struct dpio_attr attr;
+ struct dpio_cfg dpio_cfg;
int err = 0;
dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj));
if (!dflt_dpio) {
- printf(" No memory: malloc() failed\n");
- return -ENOMEM;
+ printf("No memory: malloc() failed\n");
+ err = -ENOMEM;
+ goto err_malloc;
}
- dflt_dpio->dpio_id = obj_desc.id;
+ dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL;
+ dpio_cfg.num_priorities = 8;
- err = dpio_open(dflt_mc_io, MC_CMD_NO_FLAGS, obj_desc.id,
- &dflt_dpio_handle);
- if (err) {
- printf("dpio_open() failed\n");
- goto err_open;
+ err = dpio_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpio_cfg,
+ &dflt_dpio->dpio_handle);
+ if (err < 0) {
+ printf("dpio_create() failed: %d\n", err);
+ err = -ENODEV;
+ goto err_create;
}
+ memset(&attr, 0, sizeof(struct dpio_attr));
err = dpio_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpio_handle, &attr);
- if (err) {
- printf("dpio_get_attributes() failed %d\n", err);
+ dflt_dpio->dpio_handle, &attr);
+ if (err < 0) {
+ printf("dpio_get_attributes() failed: %d\n", err);
goto err_get_attr;
}
- err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle);
- if (err) {
+ dflt_dpio->dpio_id = attr.id;
+#ifdef DEBUG
+ printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id);
+#endif
+
+ err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+ if (err < 0) {
printf("dpio_enable() failed %d\n", err);
goto err_get_enable;
}
return 0;
err_get_swp_init:
+ dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
err_get_enable:
- dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle);
-err_get_attr:
- dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio_handle);
-err_open:
free(dflt_dpio);
+err_get_attr:
+ dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+ dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+err_create:
+err_malloc:
return err;
}
-int dpbp_init(struct dprc_obj_desc obj_desc)
+static int dpio_exit(void)
{
- dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
- if (!dflt_dpbp) {
+ int err;
+
+ err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+ if (err < 0) {
+ printf("dpio_disable() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpio_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
+ if (err < 0) {
+ printf("dpio_destroy() failed: %d\n", err);
+ goto err;
+ }
+
+#ifdef DEBUG
+ printf("Exit: DPIO id=0x%d\n", dflt_dpio->dpio_id);
+#endif
+
+ if (dflt_dpio)
+ free(dflt_dpio);
+
+ return 0;
+err:
+ return err;
+}
+
+static int dprc_init(void)
+{
+ int err, child_portal_id, container_id;
+ struct dprc_cfg cfg;
+ uint64_t mc_portal_offset;
+
+ /* Open root container */
+ err = dprc_get_container_id(root_mc_io, MC_CMD_NO_FLAGS, &container_id);
+ if (err < 0) {
+ printf("dprc_get_container_id(): Root failed: %d\n", err);
+ goto err_root_container_id;
+ }
+
+#ifdef DEBUG
+ printf("Root container id = %d\n", container_id);
+#endif
+ err = dprc_open(root_mc_io, MC_CMD_NO_FLAGS, container_id,
+ &root_dprc_handle);
+ if (err < 0) {
+ printf("dprc_open(): Root Container failed: %d\n", err);
+ goto err_root_open;
+ }
+
+ if (!root_dprc_handle) {
+ printf("dprc_open(): Root Container Handle is not valid\n");
+ goto err_root_open;
+ }
+
+ cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED |
+ DPRC_CFG_OPT_OBJ_CREATE_ALLOWED |
+ DPRC_CFG_OPT_ALLOC_ALLOWED;
+ cfg.icid = DPRC_GET_ICID_FROM_POOL;
+ cfg.portal_id = 250;
+ err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS,
+ root_dprc_handle,
+ &cfg,
+ &child_dprc_id,
+ &mc_portal_offset);
+ if (err < 0) {
+ printf("dprc_create_container() failed: %d\n", err);
+ goto err_create;
+ }
+
+ dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
+ if (!dflt_mc_io) {
+ err = -ENOMEM;
printf(" No memory: malloc() failed\n");
- return -ENOMEM;
+ goto err_malloc;
+ }
+
+ child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset);
+ dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(child_portal_id);
+#ifdef DEBUG
+ printf("MC portal of child DPRC container: %d, physical addr %p)\n",
+ child_dprc_id, dflt_mc_io->mmio_regs);
+#endif
+
+ err = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, child_dprc_id,
+ &dflt_dprc_handle);
+ if (err < 0) {
+ printf("dprc_open(): Child container failed: %d\n", err);
+ goto err_child_open;
+ }
+
+ if (!dflt_dprc_handle) {
+ printf("dprc_open(): Child container Handle is not valid\n");
+ goto err_child_open;
}
- dflt_dpbp->dpbp_attr.id = obj_desc.id;
return 0;
+err_child_open:
+ free(dflt_mc_io);
+err_malloc:
+ dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
+ root_dprc_handle, child_dprc_id);
+err_create:
+ dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
+err_root_open:
+err_root_container_id:
+ return err;
}
-int dprc_init_container_obj(struct dprc_obj_desc obj_desc, uint16_t dprc_handle)
+static int dprc_exit(void)
{
- int error = 0, state = 0;
- struct dprc_endpoint dpni_endpoint, dpmac_endpoint;
- if (!strcmp(obj_desc.type, "dpbp")) {
- if (!dflt_dpbp) {
- error = dpbp_init(obj_desc);
- if (error < 0)
- printf("dpbp_init failed\n");
- }
- } else if (!strcmp(obj_desc.type, "dpio")) {
- if (!dflt_dpio) {
- error = dpio_init(obj_desc);
- if (error < 0)
- printf("dpio_init failed\n");
- }
- } else if (!strcmp(obj_desc.type, "dpni")) {
- strcpy(dpni_endpoint.type, obj_desc.type);
- dpni_endpoint.id = obj_desc.id;
- error = dprc_get_connection(dflt_mc_io, MC_CMD_NO_FLAGS,
- dprc_handle, &dpni_endpoint,
- &dpmac_endpoint, &state);
- if (!strcmp(dpmac_endpoint.type, "dpmac"))
- error = ldpaa_eth_init(obj_desc);
- if (error < 0)
- printf("ldpaa_eth_init failed\n");
+ int err;
+
+ err = dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle);
+ if (err < 0) {
+ printf("dprc_close(): Child failed: %d\n", err);
+ goto err;
}
- return error;
+ err = dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
+ root_dprc_handle, child_dprc_id);
+ if (err < 0) {
+ printf("dprc_destroy_container() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
+ if (err < 0) {
+ printf("dprc_close(): Root failed: %d\n", err);
+ goto err;
+ }
+
+ if (dflt_mc_io)
+ free(dflt_mc_io);
+
+ if (root_mc_io)
+ free(root_mc_io);
+
+ return 0;
+
+err:
+ return err;
}
-int dprc_scan_container_obj(uint16_t dprc_handle, char *obj_type, int i)
+static int dpbp_init(void)
{
- int error = 0;
- struct dprc_obj_desc obj_desc;
+ int err;
+ struct dpbp_attr dpbp_attr;
+ struct dpbp_cfg dpbp_cfg;
- memset((void *)&obj_desc, 0x00, sizeof(struct dprc_obj_desc));
+ dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
+ if (!dflt_dpbp) {
+ printf("No memory: malloc() failed\n");
+ err = -ENOMEM;
+ goto err_malloc;
+ }
- error = dprc_get_obj(dflt_mc_io, MC_CMD_NO_FLAGS, dprc_handle,
- i, &obj_desc);
- if (error < 0) {
- printf("dprc_get_obj(i=%d) failed: %d\n",
- i, error);
- return error;
+ dpbp_cfg.options = 512;
+
+ err = dpbp_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpbp_cfg,
+ &dflt_dpbp->dpbp_handle);
+
+ if (err < 0) {
+ err = -ENODEV;
+ printf("dpbp_create() failed: %d\n", err);
+ goto err_create;
+ }
+
+ memset(&dpbp_attr, 0, sizeof(struct dpbp_attr));
+ err = dpbp_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpbp->dpbp_handle,
+ &dpbp_attr);
+ if (err < 0) {
+ printf("dpbp_get_attributes() failed: %d\n", err);
+ goto err_get_attr;
}
- if (!strcmp(obj_desc.type, obj_type)) {
- debug("Discovered object: type %s, id %d, req %s\n",
- obj_desc.type, obj_desc.id, obj_type);
+ dflt_dpbp->dpbp_attr.id = dpbp_attr.id;
+#ifdef DEBUG
+ printf("Init: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
+#endif
- error = dprc_init_container_obj(obj_desc, dprc_handle);
- if (error < 0) {
- printf("dprc_init_container_obj(i=%d) failed: %d\n",
- i, error);
- return error;
- }
+ err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
+ if (err < 0) {
+ printf("dpbp_close() failed: %d\n", err);
+ goto err_close;
}
- return error;
+ return 0;
+
+err_close:
+ free(dflt_dpbp);
+err_get_attr:
+ dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
+ dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
+err_create:
+err_malloc:
+ return err;
}
-int fsl_mc_ldpaa_init(bd_t *bis)
+static int dpbp_exit(void)
{
- int i, error = 0;
- int dprc_opened = 0, container_id;
- int num_child_objects = 0;
+ int err;
- error = mc_init();
- if (error < 0)
- goto error;
+ err = dpbp_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_attr.id,
+ &dflt_dpbp->dpbp_handle);
+ if (err < 0) {
+ printf("dpbp_open() failed: %d\n", err);
+ goto err;
+ }
- error = dprc_get_container_id(dflt_mc_io, MC_CMD_NO_FLAGS,
- &container_id);
- if (error < 0) {
- printf("dprc_get_container_id() failed: %d\n", error);
- goto error;
+ err = dpbp_destroy(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpbp->dpbp_handle);
+ if (err < 0) {
+ printf("dpbp_destroy() failed: %d\n", err);
+ goto err;
}
- debug("fsl-mc: Container id=0x%x\n", container_id);
+#ifdef DEBUG
+ printf("Exit: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id);
+#endif
+
+ if (dflt_dpbp)
+ free(dflt_dpbp);
+ return 0;
- error = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, container_id,
- &dflt_dprc_handle);
- if (error < 0) {
- printf("dprc_open() failed: %d\n", error);
- goto error;
+err:
+ return err;
+}
+
+static int dpni_init(void)
+{
+ int err;
+ struct dpni_attr dpni_attr;
+ struct dpni_cfg dpni_cfg;
+
+ dflt_dpni = (struct fsl_dpni_obj *)malloc(sizeof(struct fsl_dpni_obj));
+ if (!dflt_dpni) {
+ printf("No memory: malloc() failed\n");
+ err = -ENOMEM;
+ goto err_malloc;
}
- dprc_opened = true;
- error = dprc_get_obj_count(dflt_mc_io,
- MC_CMD_NO_FLAGS, dflt_dprc_handle,
- &num_child_objects);
- if (error < 0) {
- printf("dprc_get_obj_count() failed: %d\n", error);
- goto error;
+ memset(&dpni_cfg, 0, sizeof(dpni_cfg));
+ dpni_cfg.adv.options = DPNI_OPT_UNICAST_FILTER |
+ DPNI_OPT_MULTICAST_FILTER;
+
+ err = dpni_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpni_cfg,
+ &dflt_dpni->dpni_handle);
+
+ if (err < 0) {
+ err = -ENODEV;
+ printf("dpni_create() failed: %d\n", err);
+ goto err_create;
}
- debug("Total child in container %d = %d\n", container_id,
- num_child_objects);
- if (num_child_objects != 0) {
- /*
- * Discover objects currently in the DPRC container in the MC:
- */
- for (i = 0; i < num_child_objects; i++)
- error = dprc_scan_container_obj(dflt_dprc_handle,
- "dpbp", i);
+ memset(&dpni_attr, 0, sizeof(struct dpni_attr));
+ err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ &dpni_attr);
+ if (err < 0) {
+ printf("dpni_get_attributes() failed: %d\n", err);
+ goto err_get_attr;
+ }
- for (i = 0; i < num_child_objects; i++)
- error = dprc_scan_container_obj(dflt_dprc_handle,
- "dpio", i);
+ dflt_dpni->dpni_id = dpni_attr.id;
+#ifdef DEBUG
+ printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id);
+#endif
- for (i = 0; i < num_child_objects; i++)
- error = dprc_scan_container_obj(dflt_dprc_handle,
- "dpni", i);
+ err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+ if (err < 0) {
+ printf("dpni_close() failed: %d\n", err);
+ goto err_close;
}
-error:
- if (dprc_opened)
- dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle);
- return error;
+ return 0;
+
+err_close:
+ free(dflt_dpni);
+err_get_attr:
+ dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+ dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+err_create:
+err_malloc:
+ return err;
}
-void fsl_mc_ldpaa_exit(bd_t *bis)
+static int dpni_exit(void)
{
int err;
- if (get_mc_boot_status() == 0) {
- err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpio_handle);
- if (err < 0) {
- printf("dpio_disable() failed: %d\n", err);
- return;
- }
- err = dpio_reset(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpio_handle);
- if (err < 0) {
- printf("dpio_reset() failed: %d\n", err);
- return;
- }
- err = dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS,
- dflt_dpio_handle);
- if (err < 0) {
- printf("dpio_close() failed: %d\n", err);
- return;
- }
+ err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id,
+ &dflt_dpni->dpni_handle);
+ if (err < 0) {
+ printf("dpni_open() failed: %d\n", err);
+ goto err;
+ }
- free(dflt_dpio);
- free(dflt_dpbp);
+ err = dpni_destroy(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle);
+ if (err < 0) {
+ printf("dpni_destroy() failed: %d\n", err);
+ goto err;
}
- if (dflt_mc_io)
- free(dflt_mc_io);
+#ifdef DEBUG
+ printf("Exit: DPNI id=0x%d\n", dflt_dpni->dpni_id);
+#endif
+
+ if (dflt_dpni)
+ free(dflt_dpni);
+ return 0;
+
+err:
+ return err;
+}
+
+static int mc_init_object(void)
+{
+ int err = 0;
+
+ err = dprc_init();
+ if (err < 0) {
+ printf("dprc_init() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpbp_init();
+ if (err < 0) {
+ printf("dpbp_init() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpio_init();
+ if (err < 0) {
+ printf("dpio_init() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpni_init();
+ if (err < 0) {
+ printf("dpni_init() failed: %d\n", err);
+ goto err;
+ }
+
+ return 0;
+err:
+ return err;
}
+
+int fsl_mc_ldpaa_exit(bd_t *bd)
+{
+ int err = 0;
+
+ if (bd && get_mc_boot_status() == -1)
+ return 0;
+
+ if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) {
+ printf("ERROR: fsl-mc: DPL is not applied\n");
+ err = -ENODEV;
+ return err;
+ }
+
+ if (bd && !get_mc_boot_status() && !get_dpl_apply_status())
+ return err;
+
+ err = dpbp_exit();
+ if (err < 0) {
+ printf("dpni_exit() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpio_exit();
+ if (err < 0) {
+ printf("dpio_exit() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dpni_exit();
+ if (err < 0) {
+ printf("dpni_exit() failed: %d\n", err);
+ goto err;
+ }
+
+ err = dprc_exit();
+ if (err < 0) {
+ printf("dprc_exit() failed: %d\n", err);
+ goto err;
+ }
+
+ return 0;
+err:
+ return err;
+}
+
+static int do_fsl_mc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int err = 0;
+ if (argc < 3)
+ goto usage;
+
+ switch (argv[1][0]) {
+ case 's': {
+ char sub_cmd;
+ u64 mc_fw_addr, mc_dpc_addr;
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+ u64 aiop_fw_addr;
+#endif
+
+ sub_cmd = argv[2][0];
+ switch (sub_cmd) {
+ case 'm':
+ if (argc < 5)
+ goto usage;
+
+ if (get_mc_boot_status() == 0) {
+ printf("fsl-mc: MC is already booted");
+ printf("\n");
+ return err;
+ }
+ mc_fw_addr = simple_strtoull(argv[3], NULL, 16);
+ mc_dpc_addr = simple_strtoull(argv[4], NULL,
+ 16);
+
+ if (!mc_init(mc_fw_addr, mc_dpc_addr))
+ err = mc_init_object();
+ break;
+
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+ case 'a':
+ if (argc < 4)
+ goto usage;
+ if (get_aiop_apply_status() == 0) {
+ printf("fsl-mc: AIOP FW is already");
+ printf(" applied\n");
+ return err;
+ }
+
+ aiop_fw_addr = simple_strtoull(argv[3], NULL,
+ 16);
+
+ err = load_mc_aiop_img(aiop_fw_addr);
+ if (!err)
+ printf("fsl-mc: AIOP FW applied\n");
+ break;
+#endif
+ default:
+ printf("Invalid option: %s\n", argv[2]);
+ goto usage;
+
+ break;
+ }
+ }
+ break;
+
+ case 'a': {
+ u64 mc_dpl_addr;
+
+ if (argc < 4)
+ goto usage;
+
+ if (get_dpl_apply_status() == 0) {
+ printf("fsl-mc: DPL already applied\n");
+ return err;
+ }
+
+ mc_dpl_addr = simple_strtoull(argv[3], NULL,
+ 16);
+
+ if (get_mc_boot_status() != 0) {
+ printf("fsl-mc: Deploying data path layout ..");
+ printf("ERROR (MC is not booted)\n");
+ return -ENODEV;
+ }
+
+ if (!fsl_mc_ldpaa_exit(NULL))
+ err = mc_apply_dpl(mc_dpl_addr);
+ break;
+ }
+ default:
+ printf("Invalid option: %s\n", argv[1]);
+ goto usage;
+ break;
+ }
+ return err;
+ usage:
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ fsl_mc, CONFIG_SYS_MAXARGS, 1, do_fsl_mc,
+ "DPAA2 command to manage Management Complex (MC)",
+ "start mc [FW_addr] [DPC_addr] - Start Management Complex\n"
+ "fsl_mc apply DPL [DPL_addr] - Apply DPL file\n"
+ "fsl_mc start aiop [FW_addr] - Start AIOP\n"
+);
struct mc_command *cmd)
{
enum mc_cmd_status status;
- int timeout = 6000;
+ int timeout = 12000;
mc_write_command(mc_io->mmio_regs, cmd);
obj-y += ldpaa_wriop.o
obj-y += ldpaa_eth.o
-obj-$(CONFIG_LS2085A) += ls2085a.o
+obj-$(CONFIG_LS2080A) += ls2080a.o
+obj-$(CONFIG_LS2085A) += ls2080a.o
#include <hwconfig.h>
#include <phy.h>
#include <linux/compat.h>
+#include <fsl-mc/fsl_dpmac.h>
#include "ldpaa_eth.h"
return 0;
}
+#ifdef DEBUG
+static void ldpaa_eth_get_dpni_counter(void)
+{
+ int err = 0;
+ u64 value;
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_ING_FRAME,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_ING_FRAME failed\n");
+ return;
+ }
+ printf("DPNI_CNT_ING_FRAME=%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_ING_BYTE,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_ING_BYTE failed\n");
+ return;
+ }
+ printf("DPNI_CNT_ING_BYTE=%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_ING_FRAME_DROP ,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_ING_FRAME_DROP failed\n");
+ return;
+ }
+ printf("DPNI_CNT_ING_FRAME_DROP =%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_ING_FRAME_DISCARD,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_ING_FRAME_DISCARD failed\n");
+ return;
+ }
+ printf("DPNI_CNT_ING_FRAME_DISCARD=%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_EGR_FRAME,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_EGR_FRAME failed\n");
+ return;
+ }
+ printf("DPNI_CNT_EGR_FRAME=%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_EGR_BYTE ,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_EGR_BYTE failed\n");
+ return;
+ }
+ printf("DPNI_CNT_EGR_BYTE =%lld\n", value);
+
+ err = dpni_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle,
+ DPNI_CNT_EGR_FRAME_DISCARD ,
+ &value);
+ if (err < 0) {
+ printf("dpni_get_counter: DPNI_CNT_EGR_FRAME_DISCARD failed\n");
+ return;
+ }
+ printf("DPNI_CNT_EGR_FRAME_DISCARD =%lld\n", value);
+}
+#endif
+
static void ldpaa_eth_rx(struct ldpaa_eth_priv *priv,
const struct dpaa_fd *fd)
{
/* Read the frame annotation status word and check for errors */
fas = (struct ldpaa_fas *)
((uint8_t *)(fd_addr) +
- priv->buf_layout.private_data_size);
+ dflt_dpni->buf_layout.private_data_size);
status = le32_to_cpu(fas->status);
if (status & LDPAA_ETH_RX_ERR_MASK) {
printf("Rx frame error(s): 0x%08x\n",
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
struct dpni_queue_attr rx_queue_attr;
+ struct dpmac_link_state dpmac_link_state = { 0 };
+#ifdef DEBUG
+ struct dpni_link_state link_state;
+#endif
int err;
if (net_dev->state == ETH_STATE_ACTIVE)
return 0;
+ if (get_mc_boot_status() != 0) {
+ printf("ERROR (MC is not booted)\n");
+ return -ENODEV;
+ }
+
+ if (get_dpl_apply_status() == 0) {
+ printf("ERROR (DPL is deployed. No device available)\n");
+ return -ENODEV;
+ }
+ /* DPMAC initialization */
+ err = ldpaa_dpmac_setup(priv);
+ if (err < 0)
+ goto err_dpmac_setup;
+
+ /* DPMAC binding DPNI */
+ err = ldpaa_dpmac_bind(priv);
+ if (err)
+ goto err_dpamc_bind;
+
/* DPNI initialization */
err = ldpaa_dpni_setup(priv);
if (err < 0)
/* DPNI binding DPBP */
err = ldpaa_dpni_bind(priv);
if (err)
- goto err_bind;
+ goto err_dpni_bind;
err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, net_dev->enetaddr);
+ dflt_dpni->dpni_handle, net_dev->enetaddr);
if (err) {
printf("dpni_add_mac_addr() failed\n");
return err;
priv->phydev->duplex = DUPLEX_FULL;
#endif
- err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
+ err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
if (err < 0) {
printf("dpni_enable() failed\n");
return err;
}
+ dpmac_link_state.rate = SPEED_1000;
+ dpmac_link_state.options = DPMAC_LINK_OPT_AUTONEG;
+ dpmac_link_state.up = 1;
+ err = dpmac_set_link_state(dflt_mc_io, MC_CMD_NO_FLAGS,
+ priv->dpmac_handle, &dpmac_link_state);
+ if (err < 0) {
+ printf("dpmac_set_link_state() failed\n");
+ return err;
+ }
+
+#ifdef DEBUG
+ err = dpni_get_link_state(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle, &link_state);
+ if (err < 0) {
+ printf("dpni_get_link_state() failed\n");
+ return err;
+ }
+
+ printf("link status: %d - ", link_state.up);
+ link_state.up == 0 ? printf("down\n") :
+ link_state.up == 1 ? printf("up\n") : printf("error state\n");
+#endif
+
/* TODO: support multiple Rx flows */
- err = dpni_get_rx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle,
- 0, 0, &rx_queue_attr);
+ err = dpni_get_rx_flow(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle, 0, 0, &rx_queue_attr);
if (err) {
printf("dpni_get_rx_flow() failed\n");
goto err_rx_flow;
priv->rx_dflt_fqid = rx_queue_attr.fqid;
- err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle,
+ err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle,
&priv->tx_qdid);
if (err) {
printf("dpni_get_qdid() failed\n");
err_qdid:
err_rx_flow:
- dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
-err_bind:
+ dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+err_dpni_bind:
ldpaa_dpbp_free();
err_dpbp_setup:
- dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
+err_dpamc_bind:
+ dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
err_dpni_setup:
+err_dpmac_setup:
return err;
}
if ((net_dev->state == ETH_STATE_PASSIVE) ||
(net_dev->state == ETH_STATE_INIT))
return;
+
+#ifdef DEBUG
+ ldpaa_eth_get_dpni_counter();
+#endif
+
+ err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dprc_handle, &dpmac_endpoint);
+ if (err < 0)
+ printf("dprc_disconnect() failed dpmac_endpoint\n");
+
+ err = dpmac_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle);
+ if (err < 0)
+ printf("dpmac_destroy() failed\n");
+
/* Stop Tx and Rx traffic */
- err = dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
+ err = dpni_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
if (err < 0)
printf("dpni_disable() failed\n");
#endif
ldpaa_dpbp_free();
- dpni_reset(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
- dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
+ dpni_reset(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
+ dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
}
static void ldpaa_dpbp_drain_cnt(int count)
struct qbman_release_desc rd;
for (i = 0; i < 7; i++) {
- addr = memalign(L1_CACHE_BYTES, LDPAA_ETH_RX_BUFFER_SIZE);
+ addr = memalign(LDPAA_ETH_BUF_ALIGN, LDPAA_ETH_RX_BUFFER_SIZE);
if (!addr) {
printf("addr allocation failed\n");
goto err_alloc;
dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
}
+static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv)
+{
+ int err = 0;
+ struct dpmac_cfg dpmac_cfg;
+
+ dpmac_cfg.mac_id = priv->dpmac_id;
+ err = dpmac_create(dflt_mc_io, MC_CMD_NO_FLAGS, &dpmac_cfg,
+ &priv->dpmac_handle);
+ if (err)
+ printf("dpmac_create() failed\n");
+ return err;
+}
+
+static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv)
+{
+ int err = 0;
+ struct dprc_connection_cfg dprc_connection_cfg = {
+ /* If both rates are zero the connection */
+ /* will be configured in "best effort" mode. */
+ .committed_rate = 0,
+ .max_rate = 0
+ };
+
+#ifdef DEBUG
+ struct dprc_endpoint dbg_endpoint;
+ int state = 0;
+#endif
+
+ memset(&dpmac_endpoint, 0, sizeof(struct dprc_endpoint));
+ sprintf(dpmac_endpoint.type, "dpmac");
+ dpmac_endpoint.id = priv->dpmac_id;
+
+ memset(&dpni_endpoint, 0, sizeof(struct dprc_endpoint));
+ sprintf(dpni_endpoint.type, "dpni");
+ dpni_endpoint.id = dflt_dpni->dpni_id;
+
+ err = dprc_connect(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dprc_handle,
+ &dpmac_endpoint,
+ &dpni_endpoint,
+ &dprc_connection_cfg);
+ if (err)
+ printf("dprc_connect() failed\n");
+
+#ifdef DEBUG
+ err = dprc_get_connection(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dprc_handle, &dpni_endpoint,
+ &dbg_endpoint, &state);
+ printf("%s, DPMAC Type= %s\n", __func__, dbg_endpoint.type);
+ printf("%s, DPMAC ID= %d\n", __func__, dbg_endpoint.id);
+ printf("%s, DPMAC State= %d\n", __func__, state);
+
+ memset(&dbg_endpoint, 0, sizeof(struct dprc_endpoint));
+ err = dprc_get_connection(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dprc_handle, &dpmac_endpoint,
+ &dbg_endpoint, &state);
+ printf("%s, DPNI Type= %s\n", __func__, dbg_endpoint.type);
+ printf("%s, DPNI ID= %d\n", __func__, dbg_endpoint.id);
+ printf("%s, DPNI State= %d\n", __func__, state);
+#endif
+ return err;
+}
+
static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv)
{
int err;
/* and get a handle for the DPNI this interface is associate with */
- err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_id,
- &priv->dpni_handle);
+ err = dpni_open(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_id,
+ &dflt_dpni->dpni_handle);
if (err) {
printf("dpni_open() failed\n");
goto err_open;
}
err = dpni_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, &priv->dpni_attrs);
+ dflt_dpni->dpni_handle,
+ &dflt_dpni->dpni_attrs);
if (err) {
printf("dpni_get_attributes() failed (err=%d)\n", err);
goto err_get_attr;
}
/* Configure our buffers' layout */
- priv->buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
+ dflt_dpni->buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
- DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
- priv->buf_layout.pass_parser_result = true;
- priv->buf_layout.pass_frame_status = true;
- priv->buf_layout.private_data_size = LDPAA_ETH_SWA_SIZE;
+ DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE |
+ DPNI_BUF_LAYOUT_OPT_DATA_ALIGN;
+ dflt_dpni->buf_layout.pass_parser_result = true;
+ dflt_dpni->buf_layout.pass_frame_status = true;
+ dflt_dpni->buf_layout.private_data_size = LDPAA_ETH_SWA_SIZE;
+ /* HW erratum mandates data alignment in multiples of 256 */
+ dflt_dpni->buf_layout.data_align = LDPAA_ETH_BUF_ALIGN;
/* ...rx, ... */
err = dpni_set_rx_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, &priv->buf_layout);
+ dflt_dpni->dpni_handle,
+ &dflt_dpni->buf_layout);
if (err) {
printf("dpni_set_rx_buffer_layout() failed");
goto err_buf_layout;
}
/* ... tx, ... */
- priv->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PARSER_RESULT;
+ /* remove Rx-only options */
+ dflt_dpni->buf_layout.options &= ~(DPNI_BUF_LAYOUT_OPT_DATA_ALIGN |
+ DPNI_BUF_LAYOUT_OPT_PARSER_RESULT);
err = dpni_set_tx_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, &priv->buf_layout);
+ dflt_dpni->dpni_handle,
+ &dflt_dpni->buf_layout);
if (err) {
printf("dpni_set_tx_buffer_layout() failed");
goto err_buf_layout;
}
/* ... tx-confirm. */
- priv->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
+ dflt_dpni->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
err = dpni_set_tx_conf_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle,
- &priv->buf_layout);
+ dflt_dpni->dpni_handle,
+ &dflt_dpni->buf_layout);
if (err) {
printf("dpni_set_tx_conf_buffer_layout() failed");
goto err_buf_layout;
* required tx data offset.
*/
err = dpni_get_tx_data_offset(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, &priv->tx_data_offset);
+ dflt_dpni->dpni_handle,
+ &priv->tx_data_offset);
if (err) {
printf("dpni_get_tx_data_offset() failed\n");
goto err_data_offset;
err_data_offset:
err_buf_layout:
err_get_attr:
- dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle);
+ dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
err_open:
return err;
}
pools_params.num_dpbp = 1;
pools_params.pools[0].dpbp_id = (uint16_t)dflt_dpbp->dpbp_attr.id;
pools_params.pools[0].buffer_size = LDPAA_ETH_RX_BUFFER_SIZE;
- err = dpni_set_pools(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle,
- &pools_params);
+ err = dpni_set_pools(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle, &pools_params);
if (err) {
printf("dpni_set_pools() failed\n");
return err;
dflt_tx_flow.options = DPNI_TX_FLOW_OPT_ONLY_TX_ERROR;
dflt_tx_flow.conf_err_cfg.use_default_queue = 0;
dflt_tx_flow.conf_err_cfg.errors_only = 1;
- err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpni_handle,
- &priv->tx_flow_id, &dflt_tx_flow);
+ err = dpni_set_tx_flow(dflt_mc_io, MC_CMD_NO_FLAGS,
+ dflt_dpni->dpni_handle, &priv->tx_flow_id,
+ &dflt_tx_flow);
if (err) {
printf("dpni_set_tx_flow() failed\n");
return err;
return 0;
}
-static int ldpaa_eth_netdev_init(struct eth_device *net_dev)
+static int ldpaa_eth_netdev_init(struct eth_device *net_dev,
+ phy_interface_t enet_if)
{
int err;
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
- sprintf(net_dev->name, "DPNI%d", priv->dpni_id);
+ sprintf(net_dev->name, "DPMAC%d@%s", priv->dpmac_id,
+ phy_interface_strings[enet_if]);
net_dev->iobase = 0;
net_dev->init = ldpaa_eth_open;
return 0;
}
-int ldpaa_eth_init(struct dprc_obj_desc obj_desc)
+int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if)
{
struct eth_device *net_dev = NULL;
struct ldpaa_eth_priv *priv = NULL;
net_dev->priv = (void *)priv;
priv->net_dev = (struct eth_device *)net_dev;
- priv->dpni_id = obj_desc.id;
+ priv->dpmac_id = dpmac_id;
+ debug("%s dpmac_id=%d\n", __func__, dpmac_id);
- err = ldpaa_eth_netdev_init(net_dev);
+ err = ldpaa_eth_netdev_init(net_dev, enet_if);
if (err)
goto err_netdev_init;
#define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2)
#define LDPAA_ETH_RX_BUFFER_SIZE 2048
-/* Hardware requires alignment for ingress/egress buffer addresses
- * and ingress buffer lengths.
+/* Hardware requires alignment for buffer address and length: 256-byte
+ * for ingress, 64-byte for egress. Using 256 for both.
*/
-#define LDPAA_ETH_BUF_ALIGN 64
+#define LDPAA_ETH_BUF_ALIGN 256
/* So far we're only accomodating a skb backpointer in the frame's
* software annotation, but the hardware options are either 0 or 64.
struct ldpaa_eth_priv {
struct eth_device *net_dev;
- int dpni_id;
- uint16_t dpni_handle;
- struct dpni_attr dpni_attrs;
- /* Insofar as the MC is concerned, we're using one layout on all 3 types
- * of buffers (Rx, Tx, Tx-Conf).
- */
- struct dpni_buffer_layout buf_layout;
+ int dpmac_id;
+ uint16_t dpmac_handle;
+
uint16_t tx_data_offset;
uint32_t rx_dflt_fqid;
struct phy_device *phydev;
};
+struct dprc_endpoint dpmac_endpoint;
+struct dprc_endpoint dpni_endpoint;
+
extern struct fsl_mc_io *dflt_mc_io;
extern struct fsl_dpbp_obj *dflt_dpbp;
extern struct fsl_dpio_obj *dflt_dpio;
+extern struct fsl_dpni_obj *dflt_dpni;
+extern uint16_t dflt_dprc_handle;
static void ldpaa_dpbp_drain_cnt(int count);
static void ldpaa_dpbp_drain(void);
static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv);
static int ldpaa_dpbp_setup(void);
static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv);
+static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv);
+static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv);
#endif /* __LDPAA_H */
void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
{
phy_interface_t enet_if;
- int index = dpmac_id + sd * 8;
- dpmac_info[index].enabled = 0;
- dpmac_info[index].id = 0;
- dpmac_info[index].enet_if = PHY_INTERFACE_MODE_NONE;
+ dpmac_info[dpmac_id].enabled = 0;
+ dpmac_info[dpmac_id].id = 0;
+ dpmac_info[dpmac_id].phy_addr = -1;
+ dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NONE;
- enet_if = wriop_dpmac_enet_if(index, lane_prtcl);
+ enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl);
if (enet_if != PHY_INTERFACE_MODE_NONE) {
- dpmac_info[index].enabled = 1;
- dpmac_info[index].id = index;
- dpmac_info[index].enet_if = enet_if;
+ dpmac_info[dpmac_id].enabled = 1;
+ dpmac_info[dpmac_id].id = dpmac_id;
+ dpmac_info[dpmac_id].enet_if = enet_if;
}
}
wriop_dpmac_enable(dpmac_id);
}
+u8 wriop_is_enabled_dpmac(int dpmac_id)
+{
+ int i = wriop_dpmac_to_index(dpmac_id);
+
+ if (i == -1)
+ return -1;
+
+ return dpmac_info[i].enabled;
+}
+
+
void wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
{
int i = wriop_dpmac_to_index(dpmac_id);
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <phy.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+
+u32 dpmac_to_devdisr[] = {
+ [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
+ [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
+ [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
+ [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
+ [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
+ [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
+ [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
+ [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
+ [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
+ [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
+ [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
+ [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
+ [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
+ [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
+ [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
+ [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
+ [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
+ [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
+ [WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19,
+ [WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20,
+ [WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21,
+ [WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22,
+ [WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23,
+ [WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24,
+};
+
+static int is_device_disabled(int dpmac_id)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 devdisr2 = in_le32(&gur->devdisr2);
+
+ return dpmac_to_devdisr[dpmac_id] & devdisr2;
+}
+
+void wriop_dpmac_disable(int dpmac_id)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+void wriop_dpmac_enable(int dpmac_id)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
+{
+ enum srds_prtcl;
+
+ if (is_device_disabled(dpmac_id + 1))
+ return PHY_INTERFACE_MODE_NONE;
+
+ if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
+ return PHY_INTERFACE_MODE_SGMII;
+
+ if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2)
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
+ return PHY_INTERFACE_MODE_QSGMII;
+
+ return PHY_INTERFACE_MODE_NONE;
+}
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <phy.h>
-#include <fsl-mc/ldpaa_wriop.h>
-#include <asm/io.h>
-#include <asm/arch/fsl_serdes.h>
-
-u32 dpmac_to_devdisr[] = {
- [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
- [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
- [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
- [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
- [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
- [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
- [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
- [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
- [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
- [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
- [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
- [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
- [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
- [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
- [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
- [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
- [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
- [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
- [WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19,
- [WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20,
- [WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21,
- [WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22,
- [WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23,
- [WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24,
-};
-
-static int is_device_disabled(int dpmac_id)
-{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
- u32 devdisr2 = in_le32(&gur->devdisr2);
-
- return dpmac_to_devdisr[dpmac_id] & devdisr2;
-}
-
-void wriop_dpmac_disable(int dpmac_id)
-{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
-
- setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
-}
-
-void wriop_dpmac_enable(int dpmac_id)
-{
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
-
- clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
-}
-
-phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
-{
- enum srds_prtcl;
-
- if (is_device_disabled(dpmac_id + 1))
- return PHY_INTERFACE_MODE_NONE;
-
- if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
- return PHY_INTERFACE_MODE_SGMII;
-
- if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
- return PHY_INTERFACE_MODE_XGMII;
-
- if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2)
- return PHY_INTERFACE_MODE_XGMII;
-
- if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
- return PHY_INTERFACE_MODE_QSGMII;
-
- return PHY_INTERFACE_MODE_NONE;
-}
.startup = &aquantia_startup,
.shutdown = &gen10g_shutdown,
};
+
+struct phy_driver aqr405_driver = {
+ .name = "Aquantia AQR405",
+ .uid = 0x3a1b4b2,
+ .mask = 0xfffffff0,
+ .features = PHY_10G_FEATURES,
+ .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
+ MDIO_MMD_PHYXS | MDIO_MMD_AN |
+ MDIO_MMD_VEND1),
+ .config = &aquantia_config,
+ .startup = &aquantia_startup,
+ .shutdown = &gen10g_shutdown,
+};
+
int phy_aquantia_init(void)
{
phy_register(&aq1202_driver);
phy_register(&aq2104_driver);
phy_register(&aqr105_driver);
+ phy_register(&aqr405_driver);
return 0;
}
available PCI devices, allows scanning of PCI buses and provides
device configuration support.
+config DM_PCI_COMPAT
+ bool "Enable compatible functions for PCI"
+ depends on DM_PCI
+ help
+ Enable compatibility functions for PCI so that old code can be used
+ with CONFIG_DM_PCI enabled. This should be used as an interim
+ measure when porting a board to use driver model for PCI. Once the
+ board is fully supported, this option should be disabled.
+
config PCI_SANDBOX
bool "Sandbox PCI support"
depends on SANDBOX && DM_PCI
the device tree but the normal PCI scan technique is used to find
then.
+config PCI_TEGRA
+ bool "Tegra PCI support"
+ depends on TEGRA
+ help
+ Enable support for the PCIe controller found on some generations of
+ Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
+ 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
+ with a total of 5 lanes. Some boards require this for Ethernet
+ support to work (e.g. beaver, jetson-tk1).
+
endmenu
#
ifneq ($(CONFIG_DM_PCI),)
-obj-$(CONFIG_PCI) += pci-uclass.o pci_compat.o
+obj-$(CONFIG_PCI) += pci-uclass.o
+obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
obj-$(CONFIG_X86) += pci_x86.o
else
obj-$(CONFIG_PCI) += pci.o
endif
-obj-$(CONFIG_PCI) += pci_common.o pci_auto.o pci_rom.o
+obj-$(CONFIG_PCI) += pci_auto_common.o pci_auto_old.o pci_common.o pci_rom.o
obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
return dev_get_uclass_priv(bus);
}
+struct udevice *pci_get_controller(struct udevice *dev)
+{
+ while (device_is_on_pci_bus(dev))
+ dev = dev->parent;
+
+ return dev;
+}
+
pci_dev_t pci_get_bdf(struct udevice *dev)
{
struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
int parent_node, int node)
{
int pci_addr_cells, addr_cells, size_cells;
+ phys_addr_t base = 0, size;
int cells_per_record;
- phys_addr_t addr;
const u32 *prop;
int len;
int i;
int space_code;
u32 flags;
int type;
+ int pos;
if (len < cells_per_record)
break;
} else {
continue;
}
- debug(" - type=%d\n", type);
- pci_set_region(hose->regions + hose->region_count++, pci_addr,
- addr, size, type);
+ pos = -1;
+ for (i = 0; i < hose->region_count; i++) {
+ if (hose->regions[i].flags == type)
+ pos = i;
+ }
+ if (pos == -1)
+ pos = hose->region_count++;
+ debug(" - type=%d, pos=%d\n", type, pos);
+ pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
}
/* Add a region for our local memory */
- addr = gd->ram_size;
- if (gd->pci_ram_top && gd->pci_ram_top < addr)
- addr = gd->pci_ram_top;
- pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ size = gd->ram_size;
+#ifdef CONFIG_SYS_SDRAM_BASE
+ base = CONFIG_SYS_SDRAM_BASE;
+#endif
+ if (gd->pci_ram_top && gd->pci_ram_top < base + size)
+ size = gd->pci_ram_top - base;
+ pci_set_region(hose->regions + hose->region_count++, base, base,
+ size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
return 0;
}
return skip_to_next_device(bus, devp);
}
+ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
+{
+ switch (size) {
+ case PCI_SIZE_8:
+ return (value >> ((offset & 3) * 8)) & 0xff;
+ case PCI_SIZE_16:
+ return (value >> ((offset & 2) * 8)) & 0xffff;
+ default:
+ return value;
+ }
+}
+
+ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
+ enum pci_size_t size)
+{
+ uint off_mask;
+ uint val_mask, shift;
+ ulong ldata, mask;
+
+ switch (size) {
+ case PCI_SIZE_8:
+ off_mask = 3;
+ val_mask = 0xff;
+ break;
+ case PCI_SIZE_16:
+ off_mask = 2;
+ val_mask = 0xffff;
+ break;
+ default:
+ return value;
+ }
+ shift = (offset & off_mask) * 8;
+ ldata = (value & val_mask) << shift;
+ mask = val_mask << shift;
+ value = (old & ~mask) | ldata;
+
+ return value;
+}
+
+int pci_get_regions(struct udevice *dev, struct pci_region **iop,
+ struct pci_region **memp, struct pci_region **prefp)
+{
+ struct udevice *bus = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(bus);
+ int i;
+
+ *iop = NULL;
+ *memp = NULL;
+ *prefp = NULL;
+ for (i = 0; i < hose->region_count; i++) {
+ switch (hose->regions[i].flags) {
+ case PCI_REGION_IO:
+ if (!*iop || (*iop)->size < hose->regions[i].size)
+ *iop = hose->regions + i;
+ break;
+ case PCI_REGION_MEM:
+ if (!*memp || (*memp)->size < hose->regions[i].size)
+ *memp = hose->regions + i;
+ break;
+ case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
+ if (!*prefp || (*prefp)->size < hose->regions[i].size)
+ *prefp = hose->regions + i;
+ break;
+ }
+ }
+
+ return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
+}
+
UCLASS_DRIVER(pci) = {
.id = UCLASS_PCI,
.name = "pci",
+++ /dev/null
-/*
- * arch/powerpc/kernel/pci_auto.c
- *
- * PCI autoconfiguration library
- *
- * Author: Matt Porter <mporter@mvista.com>
- *
- * Copyright 2000 MontaVista Software Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <pci.h>
-
-/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
-#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
-#endif
-
-/*
- *
- */
-
-void pciauto_region_init(struct pci_region *res)
-{
- /*
- * Avoid allocating PCI resources from address 0 -- this is illegal
- * according to PCI 2.1 and moreover, this is known to cause Linux IDE
- * drivers to fail. Use a reasonable starting value of 0x1000 instead.
- */
- res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
-}
-
-void pciauto_region_align(struct pci_region *res, pci_size_t size)
-{
- res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
-}
-
-int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
- pci_addr_t *bar)
-{
- pci_addr_t addr;
-
- if (!res) {
- debug("No resource");
- goto error;
- }
-
- addr = ((res->bus_lower - 1) | (size - 1)) + 1;
-
- if (addr - res->bus_start + size > res->size) {
- debug("No room in resource");
- goto error;
- }
-
- res->bus_lower = addr + size;
-
- debug("address=0x%llx bus_lower=0x%llx", (unsigned long long)addr,
- (unsigned long long)res->bus_lower);
-
- *bar = addr;
- return 0;
-
- error:
- *bar = (pci_addr_t)-1;
- return -1;
-}
-
-/*
- *
- */
-
-void pciauto_setup_device(struct pci_controller *hose,
- pci_dev_t dev, int bars_num,
- struct pci_region *mem,
- struct pci_region *prefetch,
- struct pci_region *io)
-{
- u32 bar_response;
- pci_size_t bar_size;
- u16 cmdstat = 0;
- int bar, bar_nr = 0;
-#ifndef CONFIG_PCI_ENUM_ONLY
- u8 header_type;
- int rom_addr;
- pci_addr_t bar_value;
- struct pci_region *bar_res;
- int found_mem64 = 0;
-#endif
- u16 class;
-
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
- cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
-
- for (bar = PCI_BASE_ADDRESS_0;
- bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
- /* Tickle the BAR and get the response */
-#ifndef CONFIG_PCI_ENUM_ONLY
- pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
-#endif
- pci_hose_read_config_dword(hose, dev, bar, &bar_response);
-
- /* If BAR is not implemented go to the next BAR */
- if (!bar_response)
- continue;
-
-#ifndef CONFIG_PCI_ENUM_ONLY
- found_mem64 = 0;
-#endif
-
- /* Check the BAR type and set our address mask */
- if (bar_response & PCI_BASE_ADDRESS_SPACE) {
- bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
- & 0xffff) + 1;
-#ifndef CONFIG_PCI_ENUM_ONLY
- bar_res = io;
-#endif
-
- debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
- bar_nr, (unsigned long long)bar_size);
- } else {
- if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
- PCI_BASE_ADDRESS_MEM_TYPE_64) {
- u32 bar_response_upper;
- u64 bar64;
-
-#ifndef CONFIG_PCI_ENUM_ONLY
- pci_hose_write_config_dword(hose, dev, bar + 4,
- 0xffffffff);
-#endif
- pci_hose_read_config_dword(hose, dev, bar + 4,
- &bar_response_upper);
-
- bar64 = ((u64)bar_response_upper << 32) | bar_response;
-
- bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
-#ifndef CONFIG_PCI_ENUM_ONLY
- found_mem64 = 1;
-#endif
- } else {
- bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
- }
-#ifndef CONFIG_PCI_ENUM_ONLY
- if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
- bar_res = prefetch;
- else
- bar_res = mem;
-#endif
-
- debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
- bar_nr, bar_res == prefetch ? "Prf" : "Mem",
- (unsigned long long)bar_size);
- }
-
-#ifndef CONFIG_PCI_ENUM_ONLY
- if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
- /* Write it out and update our limit */
- pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
-
- if (found_mem64) {
- bar += 4;
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
-#else
- /*
- * If we are a 64-bit decoder then increment to the
- * upper 32 bits of the bar and force it to locate
- * in the lower 4GB of memory.
- */
- pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
-#endif
- }
-
- }
-#endif
- cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
- PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
-
- debug("\n");
-
- bar_nr++;
- }
-
-#ifndef CONFIG_PCI_ENUM_ONLY
- /* Configure the expansion ROM address */
- pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
- header_type &= 0x7f;
- if (header_type != PCI_HEADER_TYPE_CARDBUS) {
- rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
- PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
- pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
- pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
- if (bar_response) {
- bar_size = -(bar_response & ~1);
- debug("PCI Autoconfig: ROM, size=%#x, ",
- (unsigned int)bar_size);
- if (pciauto_region_allocate(mem, bar_size,
- &bar_value) == 0) {
- pci_hose_write_config_dword(hose, dev, rom_addr,
- bar_value);
- }
- cmdstat |= PCI_COMMAND_MEMORY;
- debug("\n");
- }
- }
-#endif
-
- /* PCI_COMMAND_IO must be set for VGA device */
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
- if (class == PCI_CLASS_DISPLAY_VGA)
- cmdstat |= PCI_COMMAND_IO;
-
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
- CONFIG_SYS_PCI_CACHE_LINE_SIZE);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-}
-
-void pciauto_prescan_setup_bridge(struct pci_controller *hose,
- pci_dev_t dev, int sub_bus)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
- u16 cmdstat, prefechable_64;
-
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-#endif
-
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
- pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
- &prefechable_64);
- prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
-
- /* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
- pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
- pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
-#else
- pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
- PCI_BUS(dev) - hose->first_busno);
- pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
- sub_bus - hose->first_busno);
-#endif
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
-
- if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
-
- /* Set up memory and I/O filter limits, assume 32-bit I/O space */
- pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
- (pci_mem->bus_lower & 0xfff00000) >> 16);
-
- cmdstat |= PCI_COMMAND_MEMORY;
- }
-
- if (pci_prefetch) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
-
- /* Set up memory and I/O filter limits, assume 32-bit I/O space */
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
- (pci_prefetch->bus_lower & 0xfff00000) >> 16);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_BASE_UPPER32,
- pci_prefetch->bus_lower >> 32);
-#else
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_BASE_UPPER32,
- 0x0);
-#endif
-
- cmdstat |= PCI_COMMAND_MEMORY;
- } else {
- /* We don't support prefetchable memory for now, so disable */
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
- pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
- pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
- }
- }
-
- if (pci_io) {
- /* Round I/O allocator to 4KB boundary */
- pciauto_region_align(pci_io, 0x1000);
-
- pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
- (pci_io->bus_lower & 0x0000f000) >> 8);
- pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
- (pci_io->bus_lower & 0xffff0000) >> 16);
-
- cmdstat |= PCI_COMMAND_IO;
- }
-
- /* Enable memory and I/O accesses, enable bus master */
- pci_hose_write_config_word(hose, dev, PCI_COMMAND,
- cmdstat | PCI_COMMAND_MASTER);
-}
-
-void pciauto_postscan_setup_bridge(struct pci_controller *hose,
- pci_dev_t dev, int sub_bus)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
-
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-#endif
-
- /* Configure bus number registers */
-#ifdef CONFIG_DM_PCI
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
-#else
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
- sub_bus - hose->first_busno);
-#endif
-
- if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
-
- pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
- (pci_mem->bus_lower - 1) >> 16);
- }
-
- if (pci_prefetch) {
- u16 prefechable_64;
-
- pci_hose_read_config_word(hose, dev,
- PCI_PREF_MEMORY_LIMIT,
- &prefechable_64);
- prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
-
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
-
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
- (pci_prefetch->bus_lower - 1) >> 16);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_LIMIT_UPPER32,
- (pci_prefetch->bus_lower - 1) >> 32);
-#else
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_LIMIT_UPPER32,
- 0x0);
-#endif
- }
-
- if (pci_io) {
- /* Round I/O allocator to 4KB boundary */
- pciauto_region_align(pci_io, 0x1000);
-
- pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
- ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
- pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
- ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
- }
-}
-
-/*
- *
- */
-
-void pciauto_config_init(struct pci_controller *hose)
-{
- int i;
-
- hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL;
-
- for (i = 0; i < hose->region_count; i++) {
- switch(hose->regions[i].flags) {
- case PCI_REGION_IO:
- if (!hose->pci_io ||
- hose->pci_io->size < hose->regions[i].size)
- hose->pci_io = hose->regions + i;
- break;
- case PCI_REGION_MEM:
- if (!hose->pci_mem ||
- hose->pci_mem->size < hose->regions[i].size)
- hose->pci_mem = hose->regions + i;
- break;
- case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
- if (!hose->pci_prefetch ||
- hose->pci_prefetch->size < hose->regions[i].size)
- hose->pci_prefetch = hose->regions + i;
- break;
- }
- }
-
-
- if (hose->pci_mem) {
- pciauto_region_init(hose->pci_mem);
-
- debug("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
- "\t\tPhysical Memory [%llx-%llxx]\n",
- (u64)hose->pci_mem->bus_start,
- (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
- (u64)hose->pci_mem->phys_start,
- (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
- }
-
- if (hose->pci_prefetch) {
- pciauto_region_init(hose->pci_prefetch);
-
- debug("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
- "\t\tPhysical Memory [%llx-%llx]\n",
- (u64)hose->pci_prefetch->bus_start,
- (u64)(hose->pci_prefetch->bus_start +
- hose->pci_prefetch->size - 1),
- (u64)hose->pci_prefetch->phys_start,
- (u64)(hose->pci_prefetch->phys_start +
- hose->pci_prefetch->size - 1));
- }
-
- if (hose->pci_io) {
- pciauto_region_init(hose->pci_io);
-
- debug("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
- "\t\tPhysical Memory: [%llx-%llx]\n",
- (u64)hose->pci_io->bus_start,
- (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
- (u64)hose->pci_io->phys_start,
- (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
-
- }
-}
-
-/*
- * HJF: Changed this to return int. I think this is required
- * to get the correct result when scanning bridges
- */
-int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
- unsigned int sub_bus = PCI_BUS(dev);
- unsigned short class;
- int n;
-
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
-
- pci_mem = ctlr_hose->pci_mem;
- pci_prefetch = ctlr_hose->pci_prefetch;
- pci_io = ctlr_hose->pci_io;
-#else
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-#endif
-
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
-
- switch (class) {
- case PCI_CLASS_BRIDGE_PCI:
- debug("PCI Autoconfig: Found P2P bridge, device %d\n",
- PCI_DEV(dev));
-
- pciauto_setup_device(hose, dev, 2, pci_mem,
- pci_prefetch, pci_io);
-
-#ifdef CONFIG_DM_PCI
- n = dm_pci_hose_probe_bus(hose, dev);
- if (n < 0)
- return n;
- sub_bus = (unsigned int)n;
-#else
- /* Passing in current_busno allows for sibling P2P bridges */
- hose->current_busno++;
- pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
- /*
- * need to figure out if this is a subordinate bridge on the bus
- * to be able to properly set the pri/sec/sub bridge registers.
- */
- n = pci_hose_scan_bus(hose, hose->current_busno);
-
- /* figure out the deepest we've gone for this leg */
- sub_bus = max((unsigned int)n, sub_bus);
- pciauto_postscan_setup_bridge(hose, dev, sub_bus);
-
- sub_bus = hose->current_busno;
-#endif
- break;
-
- case PCI_CLASS_BRIDGE_CARDBUS:
- /*
- * just do a minimal setup of the bridge,
- * let the OS take care of the rest
- */
- pciauto_setup_device(hose, dev, 0, pci_mem,
- pci_prefetch, pci_io);
-
- debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
- PCI_DEV(dev));
-
-#ifndef CONFIG_DM_PCI
- hose->current_busno++;
-#endif
- break;
-
-#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
- case PCI_CLASS_BRIDGE_OTHER:
- debug("PCI Autoconfig: Skipping bridge device %d\n",
- PCI_DEV(dev));
- break;
-#endif
-#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
- case PCI_CLASS_BRIDGE_OTHER:
- /*
- * The host/PCI bridge 1 seems broken in 8349 - it presents
- * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
- * device claiming resources io/mem/irq.. we only allow for
- * the PIMMR window to be allocated (BAR0 - 1MB size)
- */
- debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
- pciauto_setup_device(hose, dev, 0, hose->pci_mem,
- hose->pci_prefetch, hose->pci_io);
- break;
-#endif
-
- case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
- debug("PCI AutoConfig: Found PowerPC device\n");
-
- default:
- pciauto_setup_device(hose, dev, 6, pci_mem,
- pci_prefetch, pci_io);
- break;
- }
-
- return sub_bus;
-}
--- /dev/null
+/*
+ * PCI auto-configuration library
+ *
+ * Author: Matt Porter <mporter@mvista.com>
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ *
+ * Modifications for driver model:
+ * Copyright 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <pci.h>
+
+void pciauto_region_init(struct pci_region *res)
+{
+ /*
+ * Avoid allocating PCI resources from address 0 -- this is illegal
+ * according to PCI 2.1 and moreover, this is known to cause Linux IDE
+ * drivers to fail. Use a reasonable starting value of 0x1000 instead.
+ */
+ res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
+}
+
+void pciauto_region_align(struct pci_region *res, pci_size_t size)
+{
+ res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
+}
+
+int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
+ pci_addr_t *bar)
+{
+ pci_addr_t addr;
+
+ if (!res) {
+ debug("No resource");
+ goto error;
+ }
+
+ addr = ((res->bus_lower - 1) | (size - 1)) + 1;
+
+ if (addr - res->bus_start + size > res->size) {
+ debug("No room in resource");
+ goto error;
+ }
+
+ res->bus_lower = addr + size;
+
+ debug("address=0x%llx bus_lower=0x%llx", (unsigned long long)addr,
+ (unsigned long long)res->bus_lower);
+
+ *bar = addr;
+ return 0;
+
+ error:
+ *bar = (pci_addr_t)-1;
+ return -1;
+}
+
+void pciauto_config_init(struct pci_controller *hose)
+{
+ int i;
+
+ hose->pci_io = NULL;
+ hose->pci_mem = NULL;
+ hose->pci_prefetch = NULL;
+
+ for (i = 0; i < hose->region_count; i++) {
+ switch (hose->regions[i].flags) {
+ case PCI_REGION_IO:
+ if (!hose->pci_io ||
+ hose->pci_io->size < hose->regions[i].size)
+ hose->pci_io = hose->regions + i;
+ break;
+ case PCI_REGION_MEM:
+ if (!hose->pci_mem ||
+ hose->pci_mem->size < hose->regions[i].size)
+ hose->pci_mem = hose->regions + i;
+ break;
+ case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
+ if (!hose->pci_prefetch ||
+ hose->pci_prefetch->size < hose->regions[i].size)
+ hose->pci_prefetch = hose->regions + i;
+ break;
+ }
+ }
+
+
+ if (hose->pci_mem) {
+ pciauto_region_init(hose->pci_mem);
+
+ debug("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
+ "\t\tPhysical Memory [%llx-%llxx]\n",
+ (u64)hose->pci_mem->bus_start,
+ (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
+ (u64)hose->pci_mem->phys_start,
+ (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
+ }
+
+ if (hose->pci_prefetch) {
+ pciauto_region_init(hose->pci_prefetch);
+
+ debug("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
+ "\t\tPhysical Memory [%llx-%llx]\n",
+ (u64)hose->pci_prefetch->bus_start,
+ (u64)(hose->pci_prefetch->bus_start +
+ hose->pci_prefetch->size - 1),
+ (u64)hose->pci_prefetch->phys_start,
+ (u64)(hose->pci_prefetch->phys_start +
+ hose->pci_prefetch->size - 1));
+ }
+
+ if (hose->pci_io) {
+ pciauto_region_init(hose->pci_io);
+
+ debug("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
+ "\t\tPhysical Memory: [%llx-%llx]\n",
+ (u64)hose->pci_io->bus_start,
+ (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
+ (u64)hose->pci_io->phys_start,
+ (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
+ }
+}
--- /dev/null
+/*
+ * arch/powerpc/kernel/pci_auto.c
+ *
+ * PCI autoconfiguration library
+ *
+ * Author: Matt Porter <mporter@mvista.com>
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <pci.h>
+
+/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
+#endif
+
+/*
+ *
+ */
+
+void pciauto_setup_device(struct pci_controller *hose,
+ pci_dev_t dev, int bars_num,
+ struct pci_region *mem,
+ struct pci_region *prefetch,
+ struct pci_region *io)
+{
+ u32 bar_response;
+ pci_size_t bar_size;
+ u16 cmdstat = 0;
+ int bar, bar_nr = 0;
+#ifndef CONFIG_PCI_ENUM_ONLY
+ u8 header_type;
+ int rom_addr;
+ pci_addr_t bar_value;
+ struct pci_region *bar_res;
+ int found_mem64 = 0;
+#endif
+ u16 class;
+
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
+ cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
+
+ for (bar = PCI_BASE_ADDRESS_0;
+ bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
+ /* Tickle the BAR and get the response */
+#ifndef CONFIG_PCI_ENUM_ONLY
+ pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
+#endif
+ pci_hose_read_config_dword(hose, dev, bar, &bar_response);
+
+ /* If BAR is not implemented go to the next BAR */
+ if (!bar_response)
+ continue;
+
+#ifndef CONFIG_PCI_ENUM_ONLY
+ found_mem64 = 0;
+#endif
+
+ /* Check the BAR type and set our address mask */
+ if (bar_response & PCI_BASE_ADDRESS_SPACE) {
+ bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
+ & 0xffff) + 1;
+#ifndef CONFIG_PCI_ENUM_ONLY
+ bar_res = io;
+#endif
+
+ debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
+ bar_nr, (unsigned long long)bar_size);
+ } else {
+ if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
+ PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ u32 bar_response_upper;
+ u64 bar64;
+
+#ifndef CONFIG_PCI_ENUM_ONLY
+ pci_hose_write_config_dword(hose, dev, bar + 4,
+ 0xffffffff);
+#endif
+ pci_hose_read_config_dword(hose, dev, bar + 4,
+ &bar_response_upper);
+
+ bar64 = ((u64)bar_response_upper << 32) | bar_response;
+
+ bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+#ifndef CONFIG_PCI_ENUM_ONLY
+ found_mem64 = 1;
+#endif
+ } else {
+ bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
+ }
+#ifndef CONFIG_PCI_ENUM_ONLY
+ if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
+ bar_res = prefetch;
+ else
+ bar_res = mem;
+#endif
+
+ debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
+ bar_nr, bar_res == prefetch ? "Prf" : "Mem",
+ (unsigned long long)bar_size);
+ }
+
+#ifndef CONFIG_PCI_ENUM_ONLY
+ if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
+ /* Write it out and update our limit */
+ pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
+
+ if (found_mem64) {
+ bar += 4;
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
+#else
+ /*
+ * If we are a 64-bit decoder then increment to the
+ * upper 32 bits of the bar and force it to locate
+ * in the lower 4GB of memory.
+ */
+ pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
+#endif
+ }
+
+ }
+#endif
+ cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
+ PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
+
+ debug("\n");
+
+ bar_nr++;
+ }
+
+#ifndef CONFIG_PCI_ENUM_ONLY
+ /* Configure the expansion ROM address */
+ pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
+ if (header_type != PCI_HEADER_TYPE_CARDBUS) {
+ rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
+ PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
+ pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
+ pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
+ if (bar_response) {
+ bar_size = -(bar_response & ~1);
+ debug("PCI Autoconfig: ROM, size=%#x, ",
+ (unsigned int)bar_size);
+ if (pciauto_region_allocate(mem, bar_size,
+ &bar_value) == 0) {
+ pci_hose_write_config_dword(hose, dev, rom_addr,
+ bar_value);
+ }
+ cmdstat |= PCI_COMMAND_MEMORY;
+ debug("\n");
+ }
+ }
+#endif
+
+ /* PCI_COMMAND_IO must be set for VGA device */
+ pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
+ if (class == PCI_CLASS_DISPLAY_VGA)
+ cmdstat |= PCI_COMMAND_IO;
+
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
+ CONFIG_SYS_PCI_CACHE_LINE_SIZE);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+}
+
+void pciauto_prescan_setup_bridge(struct pci_controller *hose,
+ pci_dev_t dev, int sub_bus)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+ u16 cmdstat, prefechable_64;
+
+#ifdef CONFIG_DM_PCI
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+#else
+ pci_mem = hose->pci_mem;
+ pci_prefetch = hose->pci_prefetch;
+ pci_io = hose->pci_io;
+#endif
+
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
+ pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
+ &prefechable_64);
+ prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+ /* Configure bus number registers */
+#ifdef CONFIG_DM_PCI
+ pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
+ pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
+#else
+ pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
+ PCI_BUS(dev) - hose->first_busno);
+ pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
+ sub_bus - hose->first_busno);
+#endif
+ pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
+
+ if (pci_mem) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_mem, 0x100000);
+
+ /* Set up memory and I/O filter limits, assume 32-bit I/O space */
+ pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
+ (pci_mem->bus_lower & 0xfff00000) >> 16);
+
+ cmdstat |= PCI_COMMAND_MEMORY;
+ }
+
+ if (pci_prefetch) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_prefetch, 0x100000);
+
+ /* Set up memory and I/O filter limits, assume 32-bit I/O space */
+ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
+ (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_BASE_UPPER32,
+ pci_prefetch->bus_lower >> 32);
+#else
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_BASE_UPPER32,
+ 0x0);
+#endif
+
+ cmdstat |= PCI_COMMAND_MEMORY;
+ } else {
+ /* We don't support prefetchable memory for now, so disable */
+ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
+ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
+ pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
+ pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
+ }
+ }
+
+ if (pci_io) {
+ /* Round I/O allocator to 4KB boundary */
+ pciauto_region_align(pci_io, 0x1000);
+
+ pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
+ (pci_io->bus_lower & 0x0000f000) >> 8);
+ pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
+ (pci_io->bus_lower & 0xffff0000) >> 16);
+
+ cmdstat |= PCI_COMMAND_IO;
+ }
+
+ /* Enable memory and I/O accesses, enable bus master */
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND,
+ cmdstat | PCI_COMMAND_MASTER);
+}
+
+void pciauto_postscan_setup_bridge(struct pci_controller *hose,
+ pci_dev_t dev, int sub_bus)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+
+#ifdef CONFIG_DM_PCI
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+#else
+ pci_mem = hose->pci_mem;
+ pci_prefetch = hose->pci_prefetch;
+ pci_io = hose->pci_io;
+#endif
+
+ /* Configure bus number registers */
+#ifdef CONFIG_DM_PCI
+ pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
+#else
+ pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
+ sub_bus - hose->first_busno);
+#endif
+
+ if (pci_mem) {
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_mem, 0x100000);
+
+ pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
+ (pci_mem->bus_lower - 1) >> 16);
+ }
+
+ if (pci_prefetch) {
+ u16 prefechable_64;
+
+ pci_hose_read_config_word(hose, dev,
+ PCI_PREF_MEMORY_LIMIT,
+ &prefechable_64);
+ prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+
+ /* Round memory allocator to 1MB boundary */
+ pciauto_region_align(pci_prefetch, 0x100000);
+
+ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
+ (pci_prefetch->bus_lower - 1) >> 16);
+ if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_LIMIT_UPPER32,
+ (pci_prefetch->bus_lower - 1) >> 32);
+#else
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_LIMIT_UPPER32,
+ 0x0);
+#endif
+ }
+
+ if (pci_io) {
+ /* Round I/O allocator to 4KB boundary */
+ pciauto_region_align(pci_io, 0x1000);
+
+ pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
+ ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
+ pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
+ ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
+ }
+}
+
+
+/*
+ * HJF: Changed this to return int. I think this is required
+ * to get the correct result when scanning bridges
+ */
+int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
+{
+ struct pci_region *pci_mem;
+ struct pci_region *pci_prefetch;
+ struct pci_region *pci_io;
+ unsigned int sub_bus = PCI_BUS(dev);
+ unsigned short class;
+ int n;
+
+#ifdef CONFIG_DM_PCI
+ /* The root controller has the region information */
+ struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
+
+ pci_mem = ctlr_hose->pci_mem;
+ pci_prefetch = ctlr_hose->pci_prefetch;
+ pci_io = ctlr_hose->pci_io;
+#else
+ pci_mem = hose->pci_mem;
+ pci_prefetch = hose->pci_prefetch;
+ pci_io = hose->pci_io;
+#endif
+
+ pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
+
+ switch (class) {
+ case PCI_CLASS_BRIDGE_PCI:
+ debug("PCI Autoconfig: Found P2P bridge, device %d\n",
+ PCI_DEV(dev));
+
+ pciauto_setup_device(hose, dev, 2, pci_mem,
+ pci_prefetch, pci_io);
+
+#ifdef CONFIG_DM_PCI
+ n = dm_pci_hose_probe_bus(hose, dev);
+ if (n < 0)
+ return n;
+ sub_bus = (unsigned int)n;
+#else
+ /* Passing in current_busno allows for sibling P2P bridges */
+ hose->current_busno++;
+ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
+ /*
+ * need to figure out if this is a subordinate bridge on the bus
+ * to be able to properly set the pri/sec/sub bridge registers.
+ */
+ n = pci_hose_scan_bus(hose, hose->current_busno);
+
+ /* figure out the deepest we've gone for this leg */
+ sub_bus = max((unsigned int)n, sub_bus);
+ pciauto_postscan_setup_bridge(hose, dev, sub_bus);
+
+ sub_bus = hose->current_busno;
+#endif
+ break;
+
+ case PCI_CLASS_BRIDGE_CARDBUS:
+ /*
+ * just do a minimal setup of the bridge,
+ * let the OS take care of the rest
+ */
+ pciauto_setup_device(hose, dev, 0, pci_mem,
+ pci_prefetch, pci_io);
+
+ debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
+ PCI_DEV(dev));
+
+#ifndef CONFIG_DM_PCI
+ hose->current_busno++;
+#endif
+ break;
+
+#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
+ case PCI_CLASS_BRIDGE_OTHER:
+ debug("PCI Autoconfig: Skipping bridge device %d\n",
+ PCI_DEV(dev));
+ break;
+#endif
+#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
+ case PCI_CLASS_BRIDGE_OTHER:
+ /*
+ * The host/PCI bridge 1 seems broken in 8349 - it presents
+ * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
+ * device claiming resources io/mem/irq.. we only allow for
+ * the PIMMR window to be allocated (BAR0 - 1MB size)
+ */
+ debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
+ pciauto_setup_device(hose, dev, 0, hose->pci_mem,
+ hose->pci_prefetch, hose->pci_io);
+ break;
+#endif
+
+ case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
+ debug("PCI AutoConfig: Found PowerPC device\n");
+
+ default:
+ pciauto_setup_device(hose, dev, 6, pci_mem,
+ pci_prefetch, pci_io);
+ break;
+ }
+
+ return sub_bus;
+}
bus_addr = phys_addr - res->phys_start + res->bus_start;
if (bus_addr >= res->bus_start &&
- bus_addr < res->bus_start + res->size) {
+ (bus_addr - res->bus_start) < res->size) {
*ba = bus_addr;
return 0;
}
* SPDX-License-Identifier: GPL-2.0
*/
-#define DEBUG
#define pr_fmt(fmt) "tegra-pcie: " fmt
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
-struct tegra_pcie;
+enum tegra_pci_id {
+ TEGRA20_PCIE,
+ TEGRA30_PCIE,
+ TEGRA124_PCIE,
+ TEGRA210_PCIE,
+};
struct tegra_pcie_port {
struct tegra_pcie *pcie;
struct fdt_resource afi;
struct fdt_resource cs;
- struct fdt_resource prefetch;
- struct fdt_resource mem;
- struct fdt_resource io;
-
struct list_head ports;
unsigned long xbar;
struct tegra_xusb_phy *phy;
};
-static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose)
-{
- return container_of(hose, struct tegra_pcie, hose);
-}
-
static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
unsigned long offset)
{
return 0;
}
- return -1;
+ return -EFAULT;
}
-static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf,
- int where, u32 *value)
+static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
{
- struct tegra_pcie *pcie = to_tegra_pcie(hose);
- unsigned long address;
+ struct tegra_pcie *pcie = dev_get_priv(bus);
+ unsigned long address, value;
int err;
- err = tegra_pcie_conf_address(pcie, bdf, where, &address);
+ err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
if (err < 0) {
- *value = 0xffffffff;
- return 1;
+ value = 0xffffffff;
+ goto done;
}
- *value = readl(address);
+ value = readl(address);
/* fixup root port class */
if (PCI_BUS(bdf) == 0) {
- if (where == PCI_CLASS_REVISION) {
- *value &= ~0x00ff0000;
- *value |= PCI_CLASS_BRIDGE_PCI << 16;
+ if (offset == PCI_CLASS_REVISION) {
+ value &= ~0x00ff0000;
+ value |= PCI_CLASS_BRIDGE_PCI << 16;
}
}
+done:
+ *valuep = pci_conv_32_to_size(value, offset, size);
+
return 0;
}
-static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf,
- int where, u32 value)
+static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
{
- struct tegra_pcie *pcie = to_tegra_pcie(hose);
+ struct tegra_pcie *pcie = dev_get_priv(bus);
unsigned long address;
+ ulong old;
int err;
- err = tegra_pcie_conf_address(pcie, bdf, where, &address);
+ err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
if (err < 0)
- return 1;
+ return 0;
+ old = readl(address);
+ value = pci_conv_size_to_32(old, value, offset, size);
writel(value, address);
return 0;
}
static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
- unsigned long *xbar)
+ enum tegra_pci_id id, unsigned long *xbar)
{
- enum fdt_compat_id id = fdtdec_lookup(fdt, node);
-
switch (id) {
- case COMPAT_NVIDIA_TEGRA20_PCIE:
+ case TEGRA20_PCIE:
switch (lanes) {
case 0x00000004:
debug("single-mode configuration\n");
return 0;
}
break;
-
- case COMPAT_NVIDIA_TEGRA30_PCIE:
+ case TEGRA30_PCIE:
switch (lanes) {
case 0x00000204:
debug("4x1, 2x1 configuration\n");
return 0;
}
break;
-
- case COMPAT_NVIDIA_TEGRA124_PCIE:
- case COMPAT_NVIDIA_TEGRA210_PCIE:
+ case TEGRA124_PCIE:
+ case TEGRA210_PCIE:
switch (lanes) {
case 0x0000104:
debug("4x1, 1x1 configuration\n");
return 0;
}
break;
-
default:
break;
}
return -FDT_ERR_NOTFOUND;
}
-static int tegra_pcie_parse_dt_ranges(const void *fdt, int node,
- struct tegra_pcie *pcie)
-{
- int parent, na_parent, na_pcie, ns_pcie;
- const u32 *ptr, *end;
- int len;
-
- parent = fdt_parent_offset(fdt, node);
- if (parent < 0) {
- error("Can't find PCI parent node\n");
- return -FDT_ERR_NOTFOUND;
- }
-
- na_parent = fdt_address_cells(fdt, parent);
- if (na_parent < 1) {
- error("bad #address-cells for PCIE parent\n");
- return -FDT_ERR_NOTFOUND;
- }
-
- na_pcie = fdt_address_cells(fdt, node);
- if (na_pcie < 1) {
- error("bad #address-cells for PCIE\n");
- return -FDT_ERR_NOTFOUND;
- }
-
- ns_pcie = fdt_size_cells(fdt, node);
- if (ns_pcie < 1) {
- error("bad #size-cells for PCIE\n");
- return -FDT_ERR_NOTFOUND;
- }
-
- ptr = fdt_getprop(fdt, node, "ranges", &len);
- if (!ptr) {
- error("missing \"ranges\" property");
- return -FDT_ERR_NOTFOUND;
- }
-
- end = ptr + len / 4;
-
- while (ptr < end) {
- struct fdt_resource *res = NULL;
- u32 space = fdt32_to_cpu(*ptr);
-
- switch ((space >> 24) & 0x3) {
- case 0x01:
- res = &pcie->io;
- break;
-
- case 0x02: /* 32 bit */
- case 0x03: /* 64 bit */
- if (space & (1 << 30))
- res = &pcie->prefetch;
- else
- res = &pcie->mem;
-
- break;
- }
-
- if (res) {
- int start_low = na_pcie + (na_parent - 1);
- int size_low = na_pcie + na_parent + (ns_pcie - 1);
- res->start = fdt32_to_cpu(ptr[start_low]);
- res->end = res->start + fdt32_to_cpu(ptr[size_low]);
- }
-
- ptr += na_pcie + na_parent + ns_pcie;
- }
-
- debug("PCI regions:\n");
- debug(" I/O: %pa-%pa\n", &pcie->io.start, &pcie->io.end);
- debug(" non-prefetchable memory: %pa-%pa\n", &pcie->mem.start,
- &pcie->mem.end);
- debug(" prefetchable memory: %pa-%pa\n", &pcie->prefetch.start,
- &pcie->prefetch.end);
-
- return 0;
-}
-
static int tegra_pcie_parse_port_info(const void *fdt, int node,
unsigned int *index,
unsigned int *lanes)
return 0;
}
-static int tegra_pcie_parse_dt(const void *fdt, int node,
+int __weak tegra_pcie_board_init(void)
+{
+ return 0;
+}
+
+static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
struct tegra_pcie *pcie)
{
int err, subnode;
return err;
}
+ tegra_pcie_board_init();
+
pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
if (pcie->phy) {
err = tegra_xusb_phy_prepare(pcie->phy);
}
}
- err = tegra_pcie_parse_dt_ranges(fdt, node, pcie);
- if (err < 0) {
- error("failed to parse \"ranges\" property");
- return err;
- }
-
fdt_for_each_subnode(fdt, subnode, node) {
unsigned int index = 0, num_lanes = 0;
struct tegra_pcie_port *port;
port->pcie = pcie;
}
- err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar);
+ err = tegra_pcie_get_xbar_config(fdt, node, lanes, id, &pcie->xbar);
if (err < 0) {
error("invalid lane configuration");
return err;
return 0;
}
-int __weak tegra_pcie_board_init(void)
-{
- return 0;
-}
-
static int tegra_pcie_power_on(struct tegra_pcie *pcie)
{
const struct tegra_pcie_soc *soc = pcie->soc;
return 0;
}
-static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
+static int tegra_pcie_setup_translations(struct udevice *bus)
{
+ struct tegra_pcie *pcie = dev_get_priv(bus);
unsigned long fpci, axi, size;
+ struct pci_region *io, *mem, *pref;
+ int count;
/* BAR 0: type 1 extended configuration space */
fpci = 0xfe100000;
afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
afi_writel(pcie, fpci, AFI_FPCI_BAR0);
+ count = pci_get_regions(bus, &io, &mem, &pref);
+ if (count != 3)
+ return -EINVAL;
+
/* BAR 1: downstream I/O */
fpci = 0xfdfc0000;
- size = fdt_resource_size(&pcie->io);
- axi = pcie->io.start;
+ size = io->size;
+ axi = io->phys_start;
afi_writel(pcie, axi, AFI_AXI_BAR1_START);
afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
afi_writel(pcie, fpci, AFI_FPCI_BAR1);
/* BAR 2: prefetchable memory */
- fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
- size = fdt_resource_size(&pcie->prefetch);
- axi = pcie->prefetch.start;
+ fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
+ size = pref->size;
+ axi = pref->phys_start;
afi_writel(pcie, axi, AFI_AXI_BAR2_START);
afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
afi_writel(pcie, fpci, AFI_FPCI_BAR2);
/* BAR 3: non-prefetchable memory */
- fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
- size = fdt_resource_size(&pcie->mem);
- axi = pcie->mem.start;
+ fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
+ size = mem->size;
+ axi = mem->phys_start;
afi_writel(pcie, axi, AFI_AXI_BAR3_START);
afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
+
+ return 0;
}
static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
return 0;
}
-static const struct tegra_pcie_soc tegra20_pcie_soc = {
- .num_ports = 2,
- .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
- .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
- .has_pex_clkreq_en = false,
- .has_pex_bias_ctrl = false,
- .has_cml_clk = false,
- .has_gen2 = false,
- .force_pca_enable = false,
-};
-
-static const struct tegra_pcie_soc tegra30_pcie_soc = {
- .num_ports = 3,
- .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
- .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
- .has_pex_clkreq_en = true,
- .has_pex_bias_ctrl = true,
- .has_cml_clk = true,
- .has_gen2 = false,
- .force_pca_enable = false,
-};
-
-static const struct tegra_pcie_soc tegra124_pcie_soc = {
- .num_ports = 2,
- .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
- .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
- .has_pex_clkreq_en = true,
- .has_pex_bias_ctrl = true,
- .has_cml_clk = true,
- .has_gen2 = true,
- .force_pca_enable = false,
-};
-
-static const struct tegra_pcie_soc tegra210_pcie_soc = {
- .num_ports = 2,
- .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
- .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
- .has_pex_clkreq_en = true,
- .has_pex_bias_ctrl = true,
- .has_cml_clk = true,
- .has_gen2 = true,
- .force_pca_enable = true,
+static const struct tegra_pcie_soc pci_tegra_soc[] = {
+ [TEGRA20_PCIE] = {
+ .num_ports = 2,
+ .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
+ .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
+ .has_pex_clkreq_en = false,
+ .has_pex_bias_ctrl = false,
+ .has_cml_clk = false,
+ .has_gen2 = false,
+ },
+ [TEGRA30_PCIE] = {
+ .num_ports = 3,
+ .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
+ .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+ .has_pex_clkreq_en = true,
+ .has_pex_bias_ctrl = true,
+ .has_cml_clk = true,
+ .has_gen2 = false,
+ },
+ [TEGRA124_PCIE] = {
+ .num_ports = 2,
+ .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
+ .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+ .has_pex_clkreq_en = true,
+ .has_pex_bias_ctrl = true,
+ .has_cml_clk = true,
+ .has_gen2 = true,
+ },
+ [TEGRA210_PCIE] = {
+ .num_ports = 2,
+ .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
+ .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+ .has_pex_clkreq_en = true,
+ .has_pex_bias_ctrl = true,
+ .has_cml_clk = true,
+ .has_gen2 = true,
+ .force_pca_enable = true,
+ }
};
-static int process_nodes(const void *fdt, int nodes[], unsigned int count)
+static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
{
- unsigned int i;
- uint64_t dram_end;
- uint32_t pci_dram_size;
-
- /* Clip PCI-accessible DRAM to 32-bits */
- dram_end = ((uint64_t)NV_PA_SDRAM_BASE) + gd->ram_size;
- if (dram_end > 0x100000000)
- dram_end = 0x100000000;
- pci_dram_size = dram_end - NV_PA_SDRAM_BASE;
-
- for (i = 0; i < count; i++) {
- const struct tegra_pcie_soc *soc;
- struct tegra_pcie *pcie;
- enum fdt_compat_id id;
- int err;
-
- if (!fdtdec_get_is_enabled(fdt, nodes[i]))
- continue;
-
- id = fdtdec_lookup(fdt, nodes[i]);
- switch (id) {
- case COMPAT_NVIDIA_TEGRA20_PCIE:
- soc = &tegra20_pcie_soc;
- break;
-
- case COMPAT_NVIDIA_TEGRA30_PCIE:
- soc = &tegra30_pcie_soc;
- break;
-
- case COMPAT_NVIDIA_TEGRA124_PCIE:
- soc = &tegra124_pcie_soc;
- break;
-
- case COMPAT_NVIDIA_TEGRA210_PCIE:
- soc = &tegra210_pcie_soc;
- break;
-
- default:
- error("unsupported compatible: %s",
- fdtdec_get_compatible(id));
- continue;
- }
-
- pcie = malloc(sizeof(*pcie));
- if (!pcie) {
- error("failed to allocate controller");
- continue;
- }
-
- memset(pcie, 0, sizeof(*pcie));
- pcie->soc = soc;
-
- INIT_LIST_HEAD(&pcie->ports);
-
- err = tegra_pcie_parse_dt(fdt, nodes[i], pcie);
- if (err < 0) {
- free(pcie);
- continue;
- }
-
- err = tegra_pcie_power_on(pcie);
- if (err < 0) {
- error("failed to power on");
- continue;
- }
+ struct tegra_pcie *pcie = dev_get_priv(dev);
+ enum tegra_pci_id id;
- err = tegra_pcie_enable_controller(pcie);
- if (err < 0) {
- error("failed to enable controller");
- continue;
- }
-
- tegra_pcie_setup_translations(pcie);
-
- err = tegra_pcie_enable(pcie);
- if (err < 0) {
- error("failed to enable PCIe");
- continue;
- }
+ id = dev_get_driver_data(dev);
+ pcie->soc = &pci_tegra_soc[id];
- pcie->hose.first_busno = 0;
- pcie->hose.current_busno = 0;
- pcie->hose.last_busno = 0;
+ INIT_LIST_HEAD(&pcie->ports);
- pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE,
- NV_PA_SDRAM_BASE, pci_dram_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ if (tegra_pcie_parse_dt(gd->fdt_blob, dev->of_offset, id, pcie))
+ return -EINVAL;
- pci_set_region(&pcie->hose.regions[1], pcie->io.start,
- pcie->io.start, fdt_resource_size(&pcie->io),
- PCI_REGION_IO);
-
- pci_set_region(&pcie->hose.regions[2], pcie->mem.start,
- pcie->mem.start, fdt_resource_size(&pcie->mem),
- PCI_REGION_MEM);
-
- pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start,
- pcie->prefetch.start,
- fdt_resource_size(&pcie->prefetch),
- PCI_REGION_MEM | PCI_REGION_PREFETCH);
+ return 0;
+}
- pcie->hose.region_count = 4;
+static int pci_tegra_probe(struct udevice *dev)
+{
+ struct tegra_pcie *pcie = dev_get_priv(dev);
+ int err;
- pci_set_ops(&pcie->hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- tegra_pcie_read_conf,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- tegra_pcie_write_conf);
+ err = tegra_pcie_power_on(pcie);
+ if (err < 0) {
+ error("failed to power on");
+ return err;
+ }
- pci_register_hose(&pcie->hose);
+ err = tegra_pcie_enable_controller(pcie);
+ if (err < 0) {
+ error("failed to enable controller");
+ return err;
+ }
-#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Enumerating devices...\n");
- printf("---------------------------------------\n");
- printf(" Device ID Description\n");
- printf(" ------ -- -----------\n");
-#endif
+ err = tegra_pcie_setup_translations(dev);
+ if (err < 0) {
+ error("failed to decode ranges");
+ return err;
+ }
- pcie->hose.last_busno = pci_hose_scan(&pcie->hose);
+ err = tegra_pcie_enable(pcie);
+ if (err < 0) {
+ error("failed to enable PCIe");
+ return err;
}
return 0;
}
-void pci_init_board(void)
-{
- const void *fdt = gd->fdt_blob;
- int count, nodes[1];
+static const struct dm_pci_ops pci_tegra_ops = {
+ .read_config = pci_tegra_read_config,
+ .write_config = pci_tegra_write_config,
+};
- tegra_pcie_board_init();
+static const struct udevice_id pci_tegra_ids[] = {
+ { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
+ { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
+ { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
+ { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
+ { }
+};
- count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
- COMPAT_NVIDIA_TEGRA210_PCIE,
- nodes, ARRAY_SIZE(nodes));
- if (process_nodes(fdt, nodes, count))
- return;
-
- count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
- COMPAT_NVIDIA_TEGRA124_PCIE,
- nodes, ARRAY_SIZE(nodes));
- if (process_nodes(fdt, nodes, count))
- return;
-
- count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
- COMPAT_NVIDIA_TEGRA30_PCIE,
- nodes, ARRAY_SIZE(nodes));
- if (process_nodes(fdt, nodes, count))
- return;
-
- count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
- COMPAT_NVIDIA_TEGRA20_PCIE,
- nodes, ARRAY_SIZE(nodes));
- if (process_nodes(fdt, nodes, count))
- return;
-}
+U_BOOT_DRIVER(pci_tegra) = {
+ .name = "pci_tegra",
+ .id = UCLASS_PCI,
+ .of_match = pci_tegra_ids,
+ .ops = &pci_tegra_ops,
+ .ofdata_to_platdata = pci_tegra_ofdata_to_platdata,
+ .probe = pci_tegra_probe,
+ .priv_auto_alloc_size = sizeof(struct tegra_pcie),
+};
int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
#include <asm/io.h>
#include <errno.h>
#include <malloc.h>
-#ifdef CONFIG_FSL_LAYERSCAPE
+#ifndef CONFIG_LS102XA
#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
#endif
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
-/* LUT registers */
-#define PCIE_LUT_BASE 0x80000
-#define PCIE_LUT_LCTRL0 0x7F8
-#define PCIE_LUT_DBG 0x7FC
-
#define PCIE_DBI_RO_WR_EN 0x8bc
#define PCIE_LINK_CAP 0x7c
{
u32 state;
- state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
+ state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
LTSSM_STATE_MASK;
if (state < LTSSM_PCIE_L0) {
debug("....PCIe link error. LTSSM=0x%02x.\n", state);
for (pf = 0; pf < PCIE_PF_NUM; pf++) {
for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
+#ifndef CONFIG_LS102XA
writel(PCIE_LCTRL0_VAL(pf, vf),
pcie->dbi + PCIE_LUT_BASE +
PCIE_LUT_LCTRL0);
+#endif
ls_pcie_ep_setup_bars(pcie->dbi);
ls_pcie_ep_setup_atu(pcie, info);
}
}
/* Disable CFG2 */
+#ifndef CONFIG_LS102XA
writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
+#endif
} else {
ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
ls_pcie_ep_setup_atu(pcie, info);
}
#endif
-#ifdef CONFIG_LS2085A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
void pcie_set_available_streamids(void *blob, const char *pcie_path,
u32 *stream_ids, int count)
definitions and pin control functions for each available multiplex
function.
+config ROCKCHIP_3036_PINCTRL
+ bool "Rockchip rk3036 pin control driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is
+ controlled by a device tree node which contains both the GPIO
+ definitions and pin control functions for each available multiplex
+ function.
+
config PINCTRL_SANDBOX
bool "Sandbox pinctrl driver"
depends on SANDBOX
#
obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o
+obj-$(CONFIG_ROCKCHIP_3036_PINCTRL) += pinctrl_rk3036.o
--- /dev/null
+/*
+ * Pinctrl driver for Rockchip 3036 SoCs
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3036.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3036_pinctrl_priv {
+ struct rk3036_grf *grf;
+};
+
+static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id)
+{
+ switch (pwm_id) {
+ case PERIPH_ID_PWM0:
+ rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK << GPIO0D2_SHIFT,
+ GPIO0D2_PWM0 << GPIO0D2_SHIFT);
+ break;
+ case PERIPH_ID_PWM1:
+ rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK << GPIO0A0_SHIFT,
+ GPIO0A0_PWM1 << GPIO0A0_SHIFT);
+ break;
+ case PERIPH_ID_PWM2:
+ rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK << GPIO0A1_SHIFT,
+ GPIO0A1_PWM2 << GPIO0A1_SHIFT);
+ break;
+ case PERIPH_ID_PWM3:
+ rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK << GPIO0D3_SHIFT,
+ GPIO0D3_PWM3 << GPIO0D3_SHIFT);
+ break;
+ default:
+ debug("pwm id = %d iomux error!\n", pwm_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id)
+{
+ switch (i2c_id) {
+ case PERIPH_ID_I2C0:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GPIO0A1_MASK << GPIO0A1_SHIFT |
+ GPIO0A0_MASK << GPIO0A0_SHIFT,
+ GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
+ GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
+
+ break;
+ case PERIPH_ID_I2C1:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GPIO0A3_MASK << GPIO0A3_SHIFT |
+ GPIO0A2_MASK << GPIO0A2_SHIFT,
+ GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
+ GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
+ break;
+ case PERIPH_ID_I2C2:
+ rk_clrsetreg(&grf->gpio2c_iomux,
+ GPIO2C5_MASK << GPIO2C5_SHIFT |
+ GPIO2C4_MASK << GPIO2C4_SHIFT,
+ GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
+ GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
+
+ break;
+ }
+}
+
+static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs)
+{
+ switch (cs) {
+ case 0:
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D6_MASK << GPIO1D6_SHIFT,
+ GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT);
+ break;
+ case 1:
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D7_MASK << GPIO1D7_SHIFT,
+ GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT);
+ break;
+ }
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D5_MASK << GPIO1D5_SHIFT |
+ GPIO1D4_MASK << GPIO1D4_SHIFT,
+ GPIO1D5_SPI_TXD << GPIO1D5_SHIFT |
+ GPIO1D4_SPI_RXD << GPIO1D4_SHIFT);
+
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A0_MASK << GPIO2A0_SHIFT,
+ GPIO2A0_SPI_CLK << GPIO2A0_SHIFT);
+}
+
+static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id)
+{
+ switch (uart_id) {
+ case PERIPH_ID_UART0:
+ rk_clrsetreg(&grf->gpio0c_iomux,
+ GPIO0C3_MASK << GPIO0C3_SHIFT |
+ GPIO0C2_MASK << GPIO0C2_SHIFT |
+ GPIO0C1_MASK << GPIO0C1_SHIFT |
+ GPIO0C0_MASK << GPIO0C0_SHIFT,
+ GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT |
+ GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT |
+ GPIO0C1_UART0_SIN << GPIO0C1_SHIFT |
+ GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT);
+ break;
+ case PERIPH_ID_UART1:
+ rk_clrsetreg(&grf->gpio2c_iomux,
+ GPIO2C7_MASK << GPIO2C7_SHIFT |
+ GPIO2C6_MASK << GPIO2C6_SHIFT,
+ GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT |
+ GPIO2C6_UART1_SIN << GPIO2C6_SHIFT);
+ break;
+ case PERIPH_ID_UART2:
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C3_MASK << GPIO1C3_SHIFT |
+ GPIO1C2_MASK << GPIO1C2_SHIFT,
+ GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
+ GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
+ break;
+ }
+}
+
+static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id)
+{
+ switch (mmc_id) {
+ case PERIPH_ID_EMMC:
+ rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
+ GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
+ GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
+ GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
+ GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
+ GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
+ GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
+ GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
+ GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A4_MASK << GPIO2A4_SHIFT |
+ GPIO2A1_MASK << GPIO2A1_SHIFT,
+ GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT |
+ GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT);
+ break;
+ case PERIPH_ID_SDCARD:
+ rk_clrsetreg(&grf->gpio1c_iomux, 0xffff,
+ GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
+ GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
+ GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
+ GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
+ GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
+ GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
+ break;
+ }
+}
+
+static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+ struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
+
+ debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+ switch (func) {
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ pinctrl_rk3036_pwm_config(priv->grf, func);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ pinctrl_rk3036_i2c_config(priv->grf, func);
+ break;
+ case PERIPH_ID_SPI0:
+ pinctrl_rk3036_spi_config(priv->grf, flags);
+ break;
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ pinctrl_rk3036_uart_config(priv->grf, func);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ pinctrl_rk3036_sdmmc_config(priv->grf, func);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rk3036_pinctrl_get_periph_id(struct udevice *dev,
+ struct udevice *periph)
+{
+ u32 cell[3];
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ "interrupts", cell, ARRAY_SIZE(cell));
+ if (ret < 0)
+ return -EINVAL;
+
+ switch (cell[1]) {
+ case 14:
+ return PERIPH_ID_SDCARD;
+ case 16:
+ return PERIPH_ID_EMMC;
+ case 20:
+ return PERIPH_ID_UART0;
+ case 21:
+ return PERIPH_ID_UART1;
+ case 22:
+ return PERIPH_ID_UART2;
+ case 23:
+ return PERIPH_ID_SPI0;
+ case 24:
+ return PERIPH_ID_I2C0;
+ case 25:
+ return PERIPH_ID_I2C1;
+ case 26:
+ return PERIPH_ID_I2C2;
+ case 30:
+ return PERIPH_ID_PWM0;
+ }
+ return -ENOENT;
+}
+
+static int rk3036_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ int func;
+
+ func = rk3036_pinctrl_get_periph_id(dev, periph);
+ if (func < 0)
+ return func;
+ return rk3036_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops rk3036_pinctrl_ops = {
+ .set_state_simple = rk3036_pinctrl_set_state_simple,
+ .request = rk3036_pinctrl_request,
+ .get_periph_id = rk3036_pinctrl_get_periph_id,
+};
+
+static int rk3036_pinctrl_probe(struct udevice *dev)
+{
+ struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ debug("%s: grf=%p\n", __func__, priv->grf);
+ return 0;
+}
+
+static const struct udevice_id rk3036_pinctrl_ids[] = {
+ { .compatible = "rockchip,rk3036-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3036) = {
+ .name = "pinctrl_rk3036",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3036_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv),
+ .ops = &rk3036_pinctrl_ops,
+ .probe = rk3036_pinctrl_probe,
+};
prompt "Select Sunxi PMIC Variant"
depends on ARCH_SUNXI
default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
- default AXP221_POWER if MACH_SUN6I || MACH_SUN8I
+ default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
+ default SUNXI_NO_PMIC if MACH_SUN8I_H3
config SUNXI_NO_PMIC
boolean "board without a pmic"
config AXP221_POWER
boolean "axp221 / axp223 pmic support"
- depends on MACH_SUN6I || MACH_SUN8I
+ depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
---help---
Select this to enable support for the axp221/axp223 pmic found on most
A23 and A31 boards.
choice
prompt "Select which UART will provide the debug UART"
depends on DEBUG_UART
+ default DEBUG_UART_NS16550
config DEBUG_UART_ALTERA_JTAGUART
bool "Altera JTAG UART"
Select this to enable an UART for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
-config ROCKCHIP_SERIAL
- bool "Rockchip on-chip UART support"
- depends on ARCH_ROCKCHIP && DM_SERIAL
+config SYS_NS16550
+ bool "NS16550 UART or compatible"
help
- Select this to enable a debug UART for Rockchip devices. This uses
- the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in
- your board config header. The clock input is automatically set to
- use the oscillator (24MHz).
+ Support NS16550 UART or compatible. This can be enabled in the
+ device tree with the correct input clock frequency. If the input
+ clock frequency is not defined in the device tree, the macro
+ CONFIG_SYS_NS16550_CLK defined in a legacy board header file will
+ be used. It can be a constant or a function to get clock, eg,
+ get_serial_clock().
config SANDBOX_SERIAL
bool "Sandbox UART support"
If you have a UniPhier based board and want to use the on-chip
serial ports, say Y to this option. If unsure, say N.
-config X86_SERIAL
- bool "Support for 16550 serial port on x86 machines"
- depends on X86
- default y
- help
- Most x86 machines have a ns16550 UART or compatible. This can be
- enabled in the device tree with the correct input clock frequency
- provided (default 1843200). Enable this to obtain serial console
- output.
-
endmenu
ifdef CONFIG_DM_SERIAL
obj-y += serial-uclass.o
obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
-obj-$(CONFIG_PPC) += serial_ppc.o
else
obj-y += serial.o
obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
-obj-$(CONFIG_DW_SERIAL) += serial_dw.o
obj-$(CONFIG_EFI_APP) += serial_efi.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += mcfuart.o
obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
-obj-$(CONFIG_KEYSTONE_SERIAL) += serial_keystone.o
obj-$(CONFIG_SYS_NS16550) += ns16550.o
obj-$(CONFIG_S5P) += serial_s5p.o
obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
obj-$(CONFIG_MXS_AUART) += mxs_auart.o
-obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
-obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
-obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
-obj-$(CONFIG_X86_SERIAL) += serial_x86.o
obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
ifndef CONFIG_SPL_BUILD
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
-#include <mapmem.h>
#include <ns16550.h>
#include <serial.h>
#include <watchdog.h>
#ifdef CONFIG_DM_SERIAL
+#ifndef CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_CLK 0
+#endif
+
static inline void serial_out_shift(void *addr, int shift, int value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = map_sysmem(plat->base, 0) + offset;
+ addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
/*
* As far as we know it doesn't make sense to support selection of
* these options at run-time, so use the existing CONFIG options.
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = map_sysmem(plat->base, 0) + offset;
+ addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
return serial_in_shift(addr, plat->reg_shift);
}
plat->base = addr;
plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"reg-shift", 1);
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "clock-frequency",
+ CONFIG_SYS_NS16550_CLK);
+ if (!plat->clock) {
+ debug("ns16550 clock not defined\n");
+ return -EINVAL;
+ }
return 0;
}
.getc = ns16550_serial_getc,
.setbrg = ns16550_serial_setbrg,
};
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct udevice_id ns16550_serial_ids[] = {
+ { .compatible = "ns16550" },
+ { .compatible = "ns16550a" },
+ { .compatible = "nvidia,tegra20-uart" },
+ { .compatible = "rockchip,rk3036-uart" },
+ { .compatible = "snps,dw-apb-uart" },
+ { .compatible = "ti,omap2-uart" },
+ { .compatible = "ti,omap3-uart" },
+ { .compatible = "ti,omap4-uart" },
+ { .compatible = "ti,am3352-uart" },
+ { .compatible = "ti,am4372-uart" },
+ { .compatible = "ti,dra742-uart" },
+ {}
+};
+#endif
+
+U_BOOT_DRIVER(ns16550_serial) = {
+ .name = "ns16550_serial",
+ .id = UCLASS_SERIAL,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ .of_match = ns16550_serial_ids,
+ .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+#endif
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = ns16550_serial_probe,
+ .ops = &ns16550_serial_ops,
+};
#endif /* CONFIG_DM_SERIAL */
+++ /dev/null
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <serial.h>
-
-static const struct udevice_id dw_serial_ids[] = {
- { .compatible = "snps,dw-apb-uart" },
- { }
-};
-
-static int dw_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
- plat->clock = CONFIG_SYS_NS16550_CLK;
-
- return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
- .name = "serial_dw",
- .id = UCLASS_SERIAL,
- .of_match = dw_serial_ids,
- .ofdata_to_platdata = dw_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
-};
+++ /dev/null
-/*
- * Copyright (c) 2015 Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <ns16550.h>
-#include <serial.h>
-#include <asm/arch/clock.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct udevice_id keystone_serial_ids[] = {
- { .compatible = "ti,keystone-uart" },
- { .compatible = "ns16550a" },
- { }
-};
-
-static int keystone_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
- plat->clock = CONFIG_SYS_NS16550_CLK;
- return 0;
-}
-#endif
-
-U_BOOT_DRIVER(serial_keystone_ns16550) = {
- .name = "serial_keystone",
- .id = UCLASS_SERIAL,
-#if CONFIG_IS_ENABLED(OF_CONTROL)
- .of_match = of_match_ptr(keystone_serial_ids),
- .ofdata_to_platdata = of_match_ptr(keystone_serial_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
-#endif
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <ns16550.h>
-#include <serial.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct udevice_id omap_serial_ids[] = {
- { .compatible = "ti,omap2-uart" },
- { .compatible = "ti,omap3-uart" },
- { .compatible = "ti,omap4-uart" },
- { .compatible = "ti,am3352-uart" },
- { .compatible = "ti,am4372-uart" },
- { .compatible = "ti,dra742-uart" },
- { }
-};
-
-static int omap_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "clock-frequency", DEFAULT_CLK_SPEED);
- plat->reg_shift = 2;
-
- return 0;
-}
-#endif
-
-U_BOOT_DRIVER(serial_omap_ns16550) = {
- .name = "serial_omap",
- .id = UCLASS_SERIAL,
- .of_match = of_match_ptr(omap_serial_ids),
- .ofdata_to_platdata = of_match_ptr(omap_serial_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <serial.h>
-
-static const struct udevice_id ppc_serial_ids[] = {
- { .compatible = "ns16550" },
- { }
-};
-
-static int ppc_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
- plat->clock = get_serial_clock();
-
- return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
- .name = "serial_ppc",
- .id = UCLASS_SERIAL,
- .of_match = ppc_serial_ids,
- .ofdata_to_platdata = ppc_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (c) 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <serial.h>
-#include <asm/arch/clock.h>
-
-static const struct udevice_id rockchip_serial_ids[] = {
- { .compatible = "rockchip,rk3288-uart" },
- { }
-};
-
-static int rockchip_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
-
- /* Do all Rockchip parts use 24MHz? */
- plat->clock = 24 * 1000000;
-
- return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
- .name = "serial_rockchip",
- .id = UCLASS_SERIAL,
- .of_match = rockchip_serial_ids,
- .ofdata_to_platdata = rockchip_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <serial.h>
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct udevice_id tegra_serial_ids[] = {
- { .compatible = "nvidia,tegra20-uart" },
- { }
-};
-
-static int tegra_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
- plat->clock = V_NS16550_CLK;
-
- return 0;
-}
-#else
-struct ns16550_platdata tegra_serial = {
- .base = CONFIG_SYS_NS16550_COM1,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
-};
-
-U_BOOT_DEVICE(ns16550_serial) = {
- "serial_tegra20", &tegra_serial
-};
-#endif
-
-U_BOOT_DRIVER(serial_ns16550) = {
- .name = "serial_tegra20",
- .id = UCLASS_SERIAL,
-#if CONFIG_IS_ENABLED(OF_CONTROL)
- .of_match = tegra_serial_ids,
- .ofdata_to_platdata = tegra_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
-#endif
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <ns16550.h>
-#include <serial.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct udevice_id x86_serial_ids[] = {
- { .compatible = "x86-uart" },
- { }
-};
-
-static int x86_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
-
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "clock-frequency", 1843200);
-
- return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
- .name = "serial_x86",
- .id = UCLASS_SERIAL,
- .of_match = x86_serial_ids,
- .ofdata_to_platdata = x86_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
-};
menu "Timer Support"
config TIMER
- bool "Enable Driver Model for Timer drivers"
+ bool "Enable driver model for timer drivers"
depends on DM
help
- Enable driver model for Timer access. It uses the same API as
- lib/time.c. But now implemented by the uclass. The first timer
+ Enable driver model for timer access. It uses the same API as
+ lib/time.c, but now implemented by the uclass. The first timer
will be used. The timer is usually a 32 bits free-running up
counter. There may be no real tick, and no timer interrupt.
config ALTERA_TIMER
- bool "Altera Timer support"
+ bool "Altera timer support"
depends on TIMER
help
- Select this to enable an timer for Altera devices. Please find
+ Select this to enable a timer for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
config SANDBOX_TIMER
- bool "Sandbox Timer support"
+ bool "Sandbox timer support"
depends on SANDBOX && TIMER
help
Select this to enable an emulated timer for sandbox. It gets
time from host os.
+config X86_TSC_TIMER
+ bool "x86 Time-Stamp Counter (TSC) timer support"
+ depends on TIMER && X86
+ default y if X86
+ help
+ Select this to enable Time-Stamp Counter (TSC) timer for x86.
+
endmenu
obj-$(CONFIG_TIMER) += timer-uclass.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
+obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
struct altera_timer_platdata {
struct altera_timer_regs *regs;
- unsigned long clock_rate;
};
-static int altera_timer_get_count(struct udevice *dev, unsigned long *count)
+static int altera_timer_get_count(struct udevice *dev, u64 *count)
{
struct altera_timer_platdata *plat = dev->platdata;
struct altera_timer_regs *const regs = plat->regs;
/* Read timer value */
val = readl(®s->snapl) & 0xffff;
val |= (readl(®s->snaph) & 0xffff) << 16;
- *count = ~val;
+ *count = timer_conv_64(~val);
return 0;
}
static int altera_timer_probe(struct udevice *dev)
{
- struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct altera_timer_platdata *plat = dev->platdata;
struct altera_timer_regs *const regs = plat->regs;
- uc_priv->clock_rate = plat->clock_rate;
-
writel(0, ®s->status);
writel(0, ®s->control);
writel(ALTERA_TIMER_STOP, ®s->control);
plat->regs = map_physmem(dev_get_addr(dev),
sizeof(struct altera_timer_regs),
MAP_NOCACHE);
- plat->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "clock-frequency", 0);
return 0;
}
sandbox_timer_offset += offset;
}
-static int sandbox_timer_get_count(struct udevice *dev, unsigned long *count)
+static int sandbox_timer_get_count(struct udevice *dev, u64 *count)
{
*count = os_get_nsec() / 1000 + sandbox_timer_offset * 1000;
static int sandbox_timer_probe(struct udevice *dev)
{
- struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
- uc_priv->clock_rate = 1000000;
-
return 0;
}
#include <errno.h>
#include <timer.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
- * Implement a Timer uclass to work with lib/time.c. The timer is usually
- * a 32 bits free-running up counter. The get_rate() method is used to get
+ * Implement a timer uclass to work with lib/time.c. The timer is usually
+ * a 32/64 bits free-running up counter. The get_rate() method is used to get
* the input clock frequency of the timer. The get_count() method is used
- * get the current 32 bits count value. If the hardware is counting down,
+ * to get the current 64 bits count value. If the hardware is counting down,
* the value should be inversed inside the method. There may be no real
* tick, and no timer interrupt.
*/
-int timer_get_count(struct udevice *dev, unsigned long *count)
+int timer_get_count(struct udevice *dev, u64 *count)
{
const struct timer_ops *ops = device_get_ops(dev);
return uc_priv->clock_rate;
}
+static int timer_pre_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "clock-frequency", 0);
+
+ return 0;
+}
+
+u64 timer_conv_64(u32 count)
+{
+ /* increment tbh if tbl has rolled over */
+ if (count < gd->timebase_l)
+ gd->timebase_h++;
+ gd->timebase_l = count;
+ return ((u64)gd->timebase_h << 32) | gd->timebase_l;
+}
+
UCLASS_DRIVER(timer) = {
.id = UCLASS_TIMER,
.name = "timer",
+ .pre_probe = timer_pre_probe,
.per_device_auto_alloc_size = sizeof(struct timer_dev_priv),
};
--- /dev/null
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * TSC calibration codes are adapted from Linux kernel
+ * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <timer.h>
+#include <asm/io.h>
+#include <asm/i8254.h>
+#include <asm/ibmpc.h>
+#include <asm/msr.h>
+#include <asm/u-boot-x86.h>
+
+/* CPU reference clock frequency: in KHz */
+#define FREQ_83 83200
+#define FREQ_100 99840
+#define FREQ_133 133200
+#define FREQ_166 166400
+
+#define MAX_NUM_FREQS 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * According to Intel 64 and IA-32 System Programming Guide,
+ * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
+ * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
+ * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
+ * so we need manually differentiate SoC families. This is what the
+ * field msr_plat does.
+ */
+struct freq_desc {
+ u8 x86_family; /* CPU family */
+ u8 x86_model; /* model */
+ /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
+ u8 msr_plat;
+ u32 freqs[MAX_NUM_FREQS];
+};
+
+static struct freq_desc freq_desc_tables[] = {
+ /* PNW */
+ { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* CLV+ */
+ { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+ /* TNG */
+ { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
+ /* VLV2 */
+ { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
+ /* Ivybridge */
+ { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
+ /* ANN */
+ { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
+};
+
+static int match_cpu(u8 family, u8 model)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
+ if ((family == freq_desc_tables[i].x86_family) &&
+ (model == freq_desc_tables[i].x86_model))
+ return i;
+ }
+
+ return -1;
+}
+
+/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
+#define id_to_freq(cpu_index, freq_id) \
+ (freq_desc_tables[cpu_index].freqs[freq_id])
+
+/*
+ * Do MSR calibration only for known/supported CPUs.
+ *
+ * Returns the calibration value or 0 if MSR calibration failed.
+ */
+static unsigned long __maybe_unused try_msr_calibrate_tsc(void)
+{
+ u32 lo, hi, ratio, freq_id, freq;
+ unsigned long res;
+ int cpu_index;
+
+ cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
+ if (cpu_index < 0)
+ return 0;
+
+ if (freq_desc_tables[cpu_index].msr_plat) {
+ rdmsr(MSR_PLATFORM_INFO, lo, hi);
+ ratio = (lo >> 8) & 0x1f;
+ } else {
+ rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+ ratio = (hi >> 8) & 0x1f;
+ }
+ debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
+
+ if (!ratio)
+ goto fail;
+
+ if (freq_desc_tables[cpu_index].msr_plat == 2) {
+ /* TODO: Figure out how best to deal with this */
+ freq = FREQ_100;
+ debug("Using frequency: %u KHz\n", freq);
+ } else {
+ /* Get FSB FREQ ID */
+ rdmsr(MSR_FSB_FREQ, lo, hi);
+ freq_id = lo & 0x7;
+ freq = id_to_freq(cpu_index, freq_id);
+ debug("Resolved frequency ID: %u, frequency: %u KHz\n",
+ freq_id, freq);
+ }
+ if (!freq)
+ goto fail;
+
+ /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
+ res = freq * ratio / 1000;
+ debug("TSC runs at %lu MHz\n", res);
+
+ return res;
+
+fail:
+ debug("Fast TSC calibration using MSR failed\n");
+ return 0;
+}
+
+/*
+ * This reads the current MSB of the PIT counter, and
+ * checks if we are running on sufficiently fast and
+ * non-virtualized hardware.
+ *
+ * Our expectations are:
+ *
+ * - the PIT is running at roughly 1.19MHz
+ *
+ * - each IO is going to take about 1us on real hardware,
+ * but we allow it to be much faster (by a factor of 10) or
+ * _slightly_ slower (ie we allow up to a 2us read+counter
+ * update - anything else implies a unacceptably slow CPU
+ * or PIT for the fast calibration to work.
+ *
+ * - with 256 PIT ticks to read the value, we have 214us to
+ * see the same MSB (and overhead like doing a single TSC
+ * read per MSB value etc).
+ *
+ * - We're doing 2 reads per loop (LSB, MSB), and we expect
+ * them each to take about a microsecond on real hardware.
+ * So we expect a count value of around 100. But we'll be
+ * generous, and accept anything over 50.
+ *
+ * - if the PIT is stuck, and we see *many* more reads, we
+ * return early (and the next caller of pit_expect_msb()
+ * then consider it a failure when they don't see the
+ * next expected value).
+ *
+ * These expectations mean that we know that we have seen the
+ * transition from one expected value to another with a fairly
+ * high accuracy, and we didn't miss any events. We can thus
+ * use the TSC value at the transitions to calculate a pretty
+ * good value for the TSC frequencty.
+ */
+static inline int pit_verify_msb(unsigned char val)
+{
+ /* Ignore LSB */
+ inb(0x42);
+ return inb(0x42) == val;
+}
+
+static inline int pit_expect_msb(unsigned char val, u64 *tscp,
+ unsigned long *deltap)
+{
+ int count;
+ u64 tsc = 0, prev_tsc = 0;
+
+ for (count = 0; count < 50000; count++) {
+ if (!pit_verify_msb(val))
+ break;
+ prev_tsc = tsc;
+ tsc = rdtsc();
+ }
+ *deltap = rdtsc() - prev_tsc;
+ *tscp = tsc;
+
+ /*
+ * We require _some_ success, but the quality control
+ * will be based on the error terms on the TSC values.
+ */
+ return count > 5;
+}
+
+/*
+ * How many MSB values do we want to see? We aim for
+ * a maximum error rate of 500ppm (in practice the
+ * real error is much smaller), but refuse to spend
+ * more than 50ms on it.
+ */
+#define MAX_QUICK_PIT_MS 50
+#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
+
+static unsigned long __maybe_unused quick_pit_calibrate(void)
+{
+ int i;
+ u64 tsc, delta;
+ unsigned long d1, d2;
+
+ /* Set the Gate high, disable speaker */
+ outb((inb(0x61) & ~0x02) | 0x01, 0x61);
+
+ /*
+ * Counter 2, mode 0 (one-shot), binary count
+ *
+ * NOTE! Mode 2 decrements by two (and then the
+ * output is flipped each time, giving the same
+ * final output frequency as a decrement-by-one),
+ * so mode 0 is much better when looking at the
+ * individual counts.
+ */
+ outb(0xb0, 0x43);
+
+ /* Start at 0xffff */
+ outb(0xff, 0x42);
+ outb(0xff, 0x42);
+
+ /*
+ * The PIT starts counting at the next edge, so we
+ * need to delay for a microsecond. The easiest way
+ * to do that is to just read back the 16-bit counter
+ * once from the PIT.
+ */
+ pit_verify_msb(0);
+
+ if (pit_expect_msb(0xff, &tsc, &d1)) {
+ for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
+ if (!pit_expect_msb(0xff-i, &delta, &d2))
+ break;
+
+ /*
+ * Iterate until the error is less than 500 ppm
+ */
+ delta -= tsc;
+ if (d1+d2 >= delta >> 11)
+ continue;
+
+ /*
+ * Check the PIT one more time to verify that
+ * all TSC reads were stable wrt the PIT.
+ *
+ * This also guarantees serialization of the
+ * last cycle read ('d2') in pit_expect_msb.
+ */
+ if (!pit_verify_msb(0xfe - i))
+ break;
+ goto success;
+ }
+ }
+ debug("Fast TSC calibration failed\n");
+ return 0;
+
+success:
+ /*
+ * Ok, if we get here, then we've seen the
+ * MSB of the PIT decrement 'i' times, and the
+ * error has shrunk to less than 500 ppm.
+ *
+ * As a result, we can depend on there not being
+ * any odd delays anywhere, and the TSC reads are
+ * reliable (within the error).
+ *
+ * kHz = ticks / time-in-seconds / 1000;
+ * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
+ * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
+ */
+ delta *= PIT_TICK_RATE;
+ delta /= (i*256*1000);
+ debug("Fast TSC calibration using PIT\n");
+ return delta / 1000;
+}
+
+/* Get the speed of the TSC timer in MHz */
+unsigned notrace long get_tbclk_mhz(void)
+{
+ return get_tbclk() / 1000000;
+}
+
+static ulong get_ms_timer(void)
+{
+ return (get_ticks() * 1000) / get_tbclk();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_ms_timer() - base;
+}
+
+ulong notrace timer_get_us(void)
+{
+ return get_ticks() / get_tbclk_mhz();
+}
+
+ulong timer_get_boot_us(void)
+{
+ return timer_get_us();
+}
+
+void __udelay(unsigned long usec)
+{
+ u64 now = get_ticks();
+ u64 stop;
+
+ stop = now + usec * get_tbclk_mhz();
+
+ while ((int64_t)(stop - get_ticks()) > 0)
+#if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
+ /*
+ * Add a 'pause' instruction on qemu target,
+ * to give other VCPUs a chance to run.
+ */
+ asm volatile("pause");
+#else
+ ;
+#endif
+}
+
+int timer_init(void)
+{
+#ifdef CONFIG_I8254_TIMER
+ /* Set up the i8254 timer if required */
+ i8254_init();
+#endif
+
+ return 0;
+}
+
+static int tsc_timer_get_count(struct udevice *dev, u64 *count)
+{
+ u64 now_tick = rdtsc();
+
+ *count = now_tick - gd->arch.tsc_base;
+
+ return 0;
+}
+
+static int tsc_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ gd->arch.tsc_base = rdtsc();
+
+ /*
+ * If there is no clock frequency specified in the device tree,
+ * calibrate it by ourselves.
+ */
+ if (!uc_priv->clock_rate) {
+ unsigned long fast_calibrate;
+
+ fast_calibrate = try_msr_calibrate_tsc();
+ if (!fast_calibrate) {
+ fast_calibrate = quick_pit_calibrate();
+ if (!fast_calibrate)
+ panic("TSC frequency is ZERO");
+ }
+
+ uc_priv->clock_rate = fast_calibrate * 1000000;
+ }
+
+ return 0;
+}
+
+static const struct timer_ops tsc_timer_ops = {
+ .get_count = tsc_timer_get_count,
+};
+
+static const struct udevice_id tsc_timer_ids[] = {
+ { .compatible = "x86,tsc-timer", },
+ { }
+};
+
+U_BOOT_DRIVER(tsc_timer) = {
+ .name = "tsc_timer",
+ .id = UCLASS_TIMER,
+ .of_match = tsc_timer_ids,
+ .probe = tsc_timer_probe,
+ .ops = &tsc_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
}
+/******************************************************************************
+ * Needed for the DFU polling magic
+ ******************************************************************************/
+
+static u8 last_int_usb;
+
+bool dfu_usb_get_reset(void)
+{
+ return !!(last_int_usb & MUSB_INTR_RESET);
+}
+
/******************************************************************************
* MUSB Glue code
******************************************************************************/
/* read and flush interrupts */
musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
+ last_int_usb = musb->int_usb;
if (musb->int_usb)
musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
reg &= 0x0000FFFF;
__raw_writel(reg, DI_STP_REP(disp, 6));
__raw_writel(0, DI_STP_REP(disp, 7));
- __raw_writel(0, DI_STP_REP(disp, 9));
+ __raw_writel(0, DI_STP_REP9(disp));
/* Init template microcode */
if (disp) {
#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])
#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])
#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])
+#define DI_STP_REP9(di) (&DI_REG(di)->stp_rep9)
#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
#include "glue.h"
-/*
- * printf() and vprintf() are stolen from u-boot/common/console.c
- */
-int printf (const char *fmt, ...)
-{
- va_list args;
- uint i;
- char printbuffer[256];
-
- va_start (args, fmt);
-
- /* For this to work, printbuffer must be larger than
- * anything we ever want to print.
- */
- i = vsprintf (printbuffer, fmt, args);
- va_end (args);
-
- /* Print the string */
- ub_puts (printbuffer);
- return i;
-}
-
-int vprintf (const char *fmt, va_list args)
+void putc(const char c)
{
- uint i;
- char printbuffer[256];
-
- /* For this to work, printbuffer must be larger than
- * anything we ever want to print.
- */
- i = vsprintf (printbuffer, fmt, args);
-
- /* Print the string */
- ub_puts (printbuffer);
- return i;
+ ub_putc(c);
}
-void putc (const char c)
+void puts(const char *s)
{
- ub_putc(c);
+ ub_puts(s);
}
void __udelay(unsigned long usec)
if (status < 0)
return 0;
+ if (dirent.direntlen == 0) {
+ printf("Failed to iterate over directory %s\n", name);
+ return 0;
+ }
+
if (dirent.namelen != 0) {
char filename[dirent.namelen + 1];
struct ext2fs_node *fdiro;
void pci_init (void);
void pci_init_board(void);
-void pciinfo (int, int);
#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
int pci_pre_init (struct pci_controller *);
void fdc_hw_init (void);
/* $(BOARD)/eeprom.c */
-void eeprom_init (void);
-#ifndef CONFIG_SPI
-int eeprom_probe (unsigned dev_addr, unsigned offset);
-#endif
+void eeprom_init (int bus);
int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */
+#define CONFIG_SYS_NS16550_MEM32
/*
* Flash
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* I2C EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_CMD_I2C
-#define CONFIG_FSL_ESPI
/* eSPI - Enhanced SPI */
#ifdef CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
* used for SLIC
*/
/* eSPI - Enhanced SPI */
-#define CONFIG_FSL_ESPI /* SPI */
#ifdef CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* I2C EEPROM */
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_CMD_I2C
/* eSPI - Enhanced SPI */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_EON
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
# define CONFIG_SYS_DSPI_CS2
-# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
DSPI_CTAR_PCSSCK_1CLK | \
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
-# define CONFIG_SPI_FLASH_ATMEL
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
DSPI_CTAR_PCSSCK_1CLK | \
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
-# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
DSPI_CTAR_PCSSCK_1CLK | \
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x13
#ifdef CONFIG_CMD_SPI
-# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
DSPI_CTAR_PCSSCK_1CLK | \
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#ifdef CONFIG_MPC8XXX_SPI
#define CONFIG_CMD_SPI
#define CONFIG_USE_SPIFLASH
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#endif
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
#if defined(CONFIG_SPI_FLASH)
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#endif
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
*/
#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
/* eSPI - Enhanced SPI */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
#endif
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_BAR
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
#if defined(CONFIG_T1024RDB)
-#define CONFIG_SPI_FLASH_STMICRO
#elif defined(CONFIG_T1023RDB)
-#define CONFIG_SPI_FLASH_SPANSION
#endif
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_BAR
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
* eSPI - Enhanced SPI
*/
#ifdef CONFIG_SPI_FLASH
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
#endif
#define CONFIG_CMD_SF
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
* eSPI - Enhanced SPI
*/
#ifdef CONFIG_SPI_FLASH
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */
/* I2C RTC */
#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SST 1
-#define CONFIG_SPI_FLASH_STMICRO 1
-#define CONFIG_SPI_FLASH_WINBOND 1
#define CONFIG_CMD_SF 1
#define CONFIG_CMD_SPI 1
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
#define CONFIG_BAUDRATE 38400
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
#define CONFIG_SYS_NS16550_REG_SIZE -4
/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_QUAD
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* PMIC support */
#define CONFIG_POWER_TPS65217
/* SPI flash. */
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_SPEED 24000000
/* Network. */
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#include <asm/arch/omap.h>
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK 48000000
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#else
-#define CONFIG_OMAP_SERIAL
#endif
/* I2C Configuration */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* Power */
#define CONFIG_POWER
/* SPI */
#undef CONFIG_OMAP3_SPI
-#define CONFIG_TI_QSPI
-#define CONFIG_SPI_FLASH_MACRONIX
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_TI_SPI_MMAP
/*
* UART
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
/* PCI host support */
#define CONFIG_PCI
-#define CONFIG_PCI_TEGRA
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PCI_ENUM
/* PCI networking support */
#define CONFIG_E1000_NO_NVM
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_MTD
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/* DataFlash */
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_3
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
/* DataFlash */
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_SYS_ICACHE_LINESZ 32
#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_SYS_ICACHE_LINESZ 32
* UART configuration
*/
#define CONFIG_DW_SERIAL
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK 33333333
#define CONFIG_SYS_NS16550_MEM32
/*
* EEPROM configuration
*/
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
/* SPI flash. */
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_SPEED 24000000
/* Network. */
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
/* Serial Info */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
/* Post pad 3 bytes after each reg addr */
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_ENV_OVERWRITE
/* Serial Info */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_MMC_ENV_PART 2
/* SPI */
-#define CONFIG_TEGRA20_SLINK
#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
/* PCI host support */
#define CONFIG_PCI
-#define CONFIG_PCI_TEGRA
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PCI_ENUM
/* PCI networking support */
#define CONFIG_RTL8169
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
/*
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_HZ 30000000
-#define CONFIG_SPI_FLASH_EON
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_SST
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SPI_FLASH_ATMEL
/*
* SPI Settings
*/
#ifdef CONFIG_SPI_FLASH_ALL
-# define CONFIG_SPI_FLASH_ATMEL
-# define CONFIG_SPI_FLASH_EON
-# define CONFIG_SPI_FLASH_MACRONIX
-# define CONFIG_SPI_FLASH_SPANSION
-# define CONFIG_SPI_FLASH_SST
-# define CONFIG_SPI_FLASH_STMICRO
-# define CONFIG_SPI_FLASH_WINBOND
#endif
/*
/* SPI FLASH */
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
/* For the M25P64 SCK Should be Kept < 15Mhz */
#define CONFIG_ENV_SPI_MAX_HZ 15000000
#define CONFIG_SF_DEFAULT_SPEED 15000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
* FLASH organization and environment definitions
#define CONFIG_ENV_SPI_MAX_HZ 15000000
#define CONFIG_SF_DEFAULT_SPEED 15000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
* Interactive command settings
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#include <asm/arch/omap.h>
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_MMC_ENV_PART 2
/* SPI */
-#define CONFIG_TEGRA20_SLINK
#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
/* PCI host support */
#define CONFIG_PCI
-#define CONFIG_PCI_TEGRA
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PCI_ENUM
/* PCI networking support */
#define CONFIG_RTL8169
#include <configs/rk3288_common.h>
+#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#include <asm/arch/omap.h>
/* Serial support */
-#define CONFIG_OMAP_SERIAL
#define CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_NS16550_COM1 0x44e09000
/* SPI Flash support */
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_EON
-#define CONFIG_SPI_FLASH_GIGADEVICE
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_TI_SPI_MMAP
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SF_DEFAULT_SPEED 48000000
#ifdef CONFIG_OF_CONTROL
#define CONFIG_DM_SPI
#define CONFIG_CMD_SPI
-#define CONFIG_FSL_DSPI
#endif
#endif /* __CONFIG_H */
* Serial Port
*/
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_MMC
#define CONFIG_SDHCI
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
/*
* General PCI
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-#define CONFIG_SPI_FLASH_STMICRO
/*
* SDIO/MMC Card Configuration
/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-#define CONFIG_SPI_FLASH_STMICRO
/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
/* SPI */
#undef CONFIG_OMAP3_SPI
-#define CONFIG_TI_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_TI_SPI_MMAP
#ifdef CONFIG_CMD_SF
#define CONFIG_HARD_SPI 1
#define CONFIG_KIRKWOOD_SPI 1
-#define CONFIG_SPI_FLASH_MACRONIX 1
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#undef CONFIG_CMD_IMLS
-#undef CONFIG_SYS_NS16550
#undef CONFIG_X86_SERIAL
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
/* 512kB DataFlash at NPCS0 */
#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
#define CONFIG_HAS_DATAFLASH
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_ATMEL_DATAFLASH_SPI
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
#define DATAFLASH_TCSS (0x1a << 16)
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rk3036_common.h>
+
+#endif
/* SPI */
#ifdef CONFIG_SPI_FLASH
-#define CONFIG_EXYNOS_SPI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 50000000
#endif
#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+/* SPL @ 32k for ~36k
+ * ENV @ 96k
+ * u-boot @ 128K
+ */
+#define CONFIG_ENV_OFFSET (96 * 1024)
+
#endif
* Serial Port
*/
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
/* SH Ether */
#define CONFIG_SH_ETHER
/* Flash Support */
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_ATMEL
/*
* mv-common.h should be defined after CMD configs since it used them
#define CONFIG_MXC_SPI
#define CONFIG_SPI_FLASH_MTD
#define CONFIG_SPI_FLASH_BAR
- #define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
/* GPIO 3-19 (21248) */
* Serial Port
*/
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
/*
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_SYS_MMC_ENV_PART 2
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
/* PCI host support */
#define CONFIG_PCI
-#define CONFIG_PCI_TEGRA
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PCI_ENUM
/* PCI networking support */
#define CONFIG_RTL8169
#define IIC0_BOOTPROM_ADDR 0x50
#define IIC0_ALT_BOOTPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0x50)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_KM_COMMON_ETH_INIT
/* EEprom support 24C08, 24C16, 24C64 */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#define CONFIG_SYS_I2C_SOFT_SPEED 100000
/* EEprom support 24C128, 24C256 valid for environment eeprom */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_SPI_FLASH_STMICRO
/* SPI bus claim MPP configuration */
#define CONFIG_SYS_KW_SPI_MPP 0x0
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
/* SH Ether */
#define CONFIG_SH_ETHER
/* SPI */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SYS_NO_FLASH
/* SH Ether */
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* SPI */
#ifdef CONFIG_QSPI_BOOT
/* QSPI */
-#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE 0x40000000
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SPI_FLASH_SPANSION
/* DSPI */
-#define CONFIG_FSL_DSPI
/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
- "fdt_high=0xcfffffff\0" \
- "initrd_high=0xcfffffff\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
- "fdt_high=0xcfffffff\0" \
- "initrd_high=0xcfffffff\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#endif
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
-#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE 0x40000000
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SPI_FLASH_STMICRO
/* DSPI */
-#define CONFIG_FSL_DSPI
-#define CONFIG_SPI_FLASH_ATMEL
#endif
/* DM SPI */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_H__
+#define __LS1043AQDS_H__
+
+#include "ls1043a_common.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x60100000
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_DDR_SPD
+#define SPD_EEPROM_ADDRESS 0x51
+#define CONFIG_SYS_SPD_BUS_NUM 0
+
+#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
+#endif
+
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_SYS_HAS_SERDES
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHYLIB_10G
+#define RGMII_PHY1_ADDR 0x1
+#define RGMII_PHY2_ADDR 0x2
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+/* PHY address on QSGMII riser card on slot 1 */
+#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
+#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
+#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
+#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
+/* PHY address on QSGMII riser card on slot 2 */
+#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
+#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
+#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
+#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
+#endif
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
+#endif
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
+
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NOR_TRHZ_80)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1a) | \
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0xe) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+
+#define CONFIG_SYS_NAND_BASE 0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_NAND \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x7) | \
+ FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0xe) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
+ FTIM2_NAND_TREH(0xa) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
+#endif
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE 0x7fb00000
+#define QIXIS_BASE_PHYS QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_LBMAP_SWITCH 6
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_RST_CTL_RESET 0x44
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+
+#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
+#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+ CSPR_PORT_SIZE_8 | \
+ CSPR_MSEL_GPCM | \
+ CSPR_V)
+#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NOR_NOR_MODE_AVD_NOR | \
+ CSOR_NOR_TRHZ_80)
+
+/*
+ * QIXIS Timing parameters for IFC GPCM
+ */
+#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
+ FTIM0_GPCM_TEADC(0x20) | \
+ FTIM0_GPCM_TEAHC(0x10))
+#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
+ FTIM2_GPCM_TCH(0x8) | \
+ FTIM2_GPCM_TWP(0xf0))
+#define CONFIG_SYS_FPGA_FTIM3 0x0
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI 0x77
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR 0x18
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_CH7301 0xC
+#define I2C_MUX_CH5 0xD
+#define I2C_MUX_CH7 0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+
+#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_INA220
+/* The lowest and highest voltage allowed for LS1043AQDS */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (30 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET (1024 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x20000
+#endif
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_MII
+#define CONFIG_CMDLINE_TAG
+
+#endif /* __LS1043AQDS_H__ */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+/* DSPI */
+#define CONFIG_FSL_DSPI
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_BUS 1
+#define CONFIG_SF_DEFAULT_CS 0
+#endif
+
/*
* Environment
*/
#define CONFIG_ETHPRIME "FM1@DTSEC3"
#endif
+/* USB */
+#define CONFIG_HAS_FSL_XHCI_USB
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#endif
+
#endif /* __LS1043ARDB_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS2_COMMON_H
+#define __LS2_COMMON_H
+
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH3
+#define CONFIG_MP
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+
+/* Errata fixes */
+#define CONFIG_ARM_ERRATA_828024
+#define CONFIG_ARM_ERRATA_826974
+
+#include <asm/arch/ls2080a_stream_id.h>
+#include <asm/arch/config.h>
+#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
+#define CONFIG_SYS_HAS_SERDES
+#endif
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+
+/* We need architecture specific misc initializations */
+#define CONFIG_ARCH_MISC_INIT
+
+/* Link Definitions */
+#ifdef CONFIG_SPL
+#define CONFIG_SYS_TEXT_BASE 0x80400000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x30100000
+#endif
+
+#ifdef CONFIG_EMU
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#ifndef CONFIG_SPL
+#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#endif
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
+#define CONFIG_SYS_DDR_RAW_TIMING
+#endif
+
+#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
+
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
+/*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+#define CONFIG_SYS_DP_DDR_BASE_PHY 0
+#define CONFIG_DP_DDR_CTRL 2
+#define CONFIG_DP_DDR_NUM_CTRLS 1
+#endif
+
+/* Generic Timer Definitions */
+/*
+ * This is not an accurate number. It is used in start.S. The frequency
+ * will be udpated later when get_bus_freq(0) is available.
+ */
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* IFC */
+#define CONFIG_FSL_IFC
+
+/*
+ * During booting, IFC is mapped at the region of 0x30000000.
+ * But this region is limited to 256MB. To accommodate NOR, promjet
+ * and FPGA. This region is divided as below:
+ * 0x30000000 - 0x37ffffff : 128MB : NOR flash
+ * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
+ * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
+ *
+ * To accommodate bigger NOR flash and other devices, we will map IFC
+ * chip selects to as below:
+ * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
+ * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
+ * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
+ * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
+ * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
+ *
+ * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
+ * CONFIG_SYS_FLASH_BASE has the final address (core view)
+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
+ */
+
+#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
+#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
+
+#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
+#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long long get_qixis_addr(void);
+#endif
+#define QIXIS_BASE get_qixis_addr()
+#define QIXIS_BASE_PHYS 0x20000000
+#define QIXIS_BASE_PHYS_EARLY 0xC000000
+#define QIXIS_STAT_PRES1 0xb
+#define QIXIS_SDID_MASK 0x07
+#define QIXIS_ESDHC_NO_ADAPTER 0x7
+
+#define CONFIG_SYS_NAND_BASE 0x530000000ULL
+#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
+
+/* Debug Server firmware */
+#define CONFIG_FSL_DEBUG_SERVER
+/* 2 sec timeout */
+#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
+
+/* MC firmware */
+#define CONFIG_FSL_MC_ENET
+/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
+#ifdef CONFIG_LS2085A
+#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
+#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
+#endif
+
+/*
+ * Carve out a DDR region which will not be used by u-boot/Linux
+ *
+ * It will be used by MC and Debug Server. The MC region must be
+ * 512MB aligned, so the min size to hide is 512MB.
+ */
+#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
+#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
+#define CONFIG_SYS_MEM_TOP_HIDE_MIN (512UL * 1024 * 1024)
+#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
+#endif
+
+/* PCIe */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_PCIE4 /* PCIE controler 4 */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#ifdef CONFIG_LS2080A
+#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
+#endif
+
+#ifdef CONFIG_LS2085A
+#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
+#endif
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
+#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
+
+/* Command line configuration */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+#define CONFIG_ARCH_EARLY_INIT_R
+
+/* Physical Memory Map */
+/* fixme: these need to be checked against the board */
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+
+#define CONFIG_NR_DRAM_BANKS 3
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x581200000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,mmio,0x21c0500,115200 " \
+ "ramdisk_size=0x2000000 default_hugepagesz=2m" \
+ " hugepagesz=2m hugepages=16"
+#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
+ "$kernel_size && bootm $kernel_load"
+#define CONFIG_BOOTDELAY 10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#ifndef __ASSEMBLY__
+unsigned long get_dram_size_to_hide(void);
+#endif
+
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+#define CONFIG_SPL_BSS_START_ADDR 0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MAX_SIZE 0x16000
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_TEXT_BASE 0x1800a000
+
+#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+
+#endif /* __LS2_COMMON_H */
--- /dev/null
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS2_EMU_H
+#define __LS2_EMU_H
+
+#include "ls2080a_common.h"
+
+#ifdef CONFIG_LS2080A
+#define CONFIG_IDENT_STRING " LS2080A-EMU"
+#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-EMU"
+#endif
+
+#ifdef CONFIG_LS2085A
+#define CONFIG_IDENT_STRING " LS2085A-EMU"
+#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU"
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 133333333
+
+#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
+#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS3 0x53
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
+#endif
+
+#define CONFIG_FSL_DDR_SYNC_REFRESH
+
+#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/*
+ * NOR Flash Timing Params
+ */
+#define CONFIG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x1) | \
+ FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
+ FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
+ FTIM2_NOR_TCH(0x0) | \
+ FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3 0x04000000
+#define CONFIG_SYS_IFC_CCR 0x01000000
+
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
+
+/*
+ * This trick allows users to load MC images into DDR directly without
+ * copying from NOR flash. It dramatically improves speed.
+ */
+#define CONFIG_SYS_LS_MC_FW_IN_DDR
+#define CONFIG_SYS_LS_MC_DPL_IN_DDR
+#define CONFIG_SYS_LS_MC_DPC_IN_DDR
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x1000
+
+#endif /* __LS2_EMU_H */
--- /dev/null
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS2_SIMU_H
+#define __LS2_SIMU_H
+
+#include "ls2080a_common.h"
+
+#ifdef CONFIG_LS2080A
+#define CONFIG_IDENT_STRING " LS2080A-SIMU"
+#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-SIMU"
+#endif
+
+#ifdef CONFIG_LS2085A
+#define CONFIG_IDENT_STRING " LS2085A-SIMU"
+#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU"
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 133333333
+
+#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
+#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
+#endif
+
+/* SMSC 91C111 ethernet configuration */
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE (0x2210000)
+
+#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+
+/*
+ * NOR Flash Timing Params
+ */
+#define CONFIG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x1) | \
+ FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
+ FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
+ FTIM2_NOR_TCH(0x0) | \
+ FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3 0x04000000
+#define CONFIG_SYS_IFC_CCR 0x01000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS 256
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+/* MMC */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_FW_IN_NOR
+#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
+
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
+
+#define CONFIG_SYS_LS_MC_DPC_IN_NOR
+#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x1000
+
+#endif /* __LS2_SIMU_H */
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS2_QDS_H
+#define __LS2_QDS_H
+
+#include "ls2080a_common.h"
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS3 0x53
+#define SPD_EEPROM_ADDRESS4 0x54
+#define SPD_EEPROM_ADDRESS5 0x55
+#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
+#endif
+#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
+
+/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
+
+#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
+
+#define CONFIG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1a) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x04000000
+#define CONFIG_SYS_IFC_CCR 0x01000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
+ CONFIG_SYS_FLASH_BASE + 0x40000000}
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS 256
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#define CONFIG_FSL_QIXIS /* use common QIXIS code */
+#define QIXIS_LBMAP_SWITCH 0x06
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_LBMAP_NAND 0x09
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_RCW_SRC_NAND 0x107
+#define QIXIS_RST_FORCE_MEM 0x01
+
+#define CONFIG_SYS_CSPR3_EXT (0x0)
+#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+ FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+ FTIM2_GPCM_TCH(0xf) | \
+ FTIM2_GPCM_TWP(0x3E))
+#define CONFIG_SYS_CS3_FTIM3 0x0
+
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (896 * 1024)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SPL_PAD_TO 0x20000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x2000
+#endif
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/*
+ * I2C
+ */
+#define I2C_MUX_PCA_ADDR 0x77
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT 0x8
+
+/* SPI */
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#endif
+
+/*
+ * MMC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
+ QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
+#endif
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_FSL_MEMAC
+#define CONFIG_PCI /* Enable PCIE */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#endif
+
+/* MMC */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Initial environment variables */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x581100000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x28000000\0"
+
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_FSL_MEMAC
+#define CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define CONFIG_CMD_MII
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "DPNI1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+
+#endif /* __LS2_QDS_H */
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS2_RDB_H
+#define __LS2_RDB_H
+
+#include "ls2080a_common.h"
+
+#undef CONFIG_CONS_INDEX
+#define CONFIG_CONS_INDEX 2
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
+
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ 133333333
+#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS3 0x53
+#define SPD_EEPROM_ADDRESS4 0x54
+#define SPD_EEPROM_ADDRESS5 0x55
+#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
+#endif
+#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
+
+/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
+
+#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
+
+#define CONFIG_SYS_NOR0_CSPR \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY \
+ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1a) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x04000000
+#define CONFIG_SYS_IFC_CCR 0x01000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
+ CONFIG_SYS_FLASH_BASE + 0x40000000}
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS 256
+#define CONFIG_SYS_NAND_MAX_OOBFREE 2
+
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
+ | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
+ FTIM0_NAND_TWP(0x30) | \
+ FTIM0_NAND_TWCHT(0x0e) | \
+ FTIM0_NAND_TWH(0x14))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
+ FTIM1_NAND_TWBE(0xab) | \
+ FTIM1_NAND_TRR(0x1c) | \
+ FTIM1_NAND_TRP(0x30))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
+ FTIM2_NAND_TREH(0x14) | \
+ FTIM2_NAND_TWHRE(0x3c))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
+
+#define CONFIG_FSL_QIXIS /* use common QIXIS code */
+#define QIXIS_LBMAP_SWITCH 0x06
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_LBMAP_NAND 0x09
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RST_CTL_RESET_EN 0x30
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_RCW_SRC_NAND 0x119
+#define QIXIS_RST_FORCE_MEM 0x01
+
+#define CONFIG_SYS_CSPR3_EXT (0x0)
+#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+ FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
+ FTIM2_GPCM_TCH(0xf) | \
+ FTIM2_GPCM_TWP(0x3E))
+#define CONFIG_SYS_CS3_FTIM3 0x0
+
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (2048 * 1024)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SPL_PAD_TO 0x80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x2000
+#endif
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/*
+ * I2C
+ */
+#define I2C_MUX_PCA_ADDR 0x75
+#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT 0x8
+
+/* SPI */
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_BAR
+#endif
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_FSL_MEMAC
+#define CONFIG_PCI /* Enable PCIE */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#endif
+
+/* MMC */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+
+/* Initial environment variables */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "kernel_addr=0x100000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x581100000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
+ "earlycon=uart8250,mmio,0x21c0600,115200 " \
+ "ramdisk_size=0x2000000 default_hugepagesz=2m" \
+ " hugepagesz=2m hugepages=16"
+
+/* MAC/PHY configuration */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_AQUANTIA
+#define CONFIG_PHY_CORTINA
+#define CONFIG_PHYLIB
+#define CONFIG_SYS_CORTINA_FW_IN_NOR
+#define CONFIG_CORTINA_FW_ADDR 0x581000000
+#define CONFIG_CORTINA_FW_LENGTH 0x40000
+
+#define CORTINA_PHY_ADDR1 0x10
+#define CORTINA_PHY_ADDR2 0x11
+#define CORTINA_PHY_ADDR3 0x12
+#define CORTINA_PHY_ADDR4 0x13
+#define AQ_PHY_ADDR1 0x00
+#define AQ_PHY_ADDR2 0x01
+#define AQ_PHY_ADDR3 0x02
+#define AQ_PHY_ADDR4 0x03
+
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "DPNI1"
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHY_AQUANTIA
+#endif
+
+#endif /* __LS2_RDB_H */
+++ /dev/null
-/*
- * Copyright (C) 2014 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __LS2_COMMON_H
-#define __LS2_COMMON_H
-
-
-#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
-#define CONFIG_FSL_LSCH3
-#define CONFIG_LS2085A
-#define CONFIG_MP
-#define CONFIG_GICV3
-#define CONFIG_FSL_TZPC_BP147
-
-/* Errata fixes */
-#define CONFIG_ARM_ERRATA_828024
-#define CONFIG_ARM_ERRATA_826974
-
-#include <asm/arch/ls2085a_stream_id.h>
-#include <asm/arch/config.h>
-#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
-#define CONFIG_SYS_HAS_SERDES
-#endif
-
-/* Link Definitions */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
-
-/* We need architecture specific misc initializations */
-#define CONFIG_ARCH_MISC_INIT
-
-/* Link Definitions */
-#ifdef CONFIG_SPL
-#define CONFIG_SYS_TEXT_BASE 0x80400000
-#else
-#define CONFIG_SYS_TEXT_BASE 0x30100000
-#endif
-
-#ifdef CONFIG_EMU
-#define CONFIG_SYS_NO_FLASH
-#endif
-
-#define CONFIG_SUPPORT_RAW_INITRD
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F 1
-
-/* Flat Device Tree Definitions */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_STDOUT_VIA_ALIAS
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
-
-#ifndef CONFIG_SPL
-#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
-#endif
-#ifndef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
-#define CONFIG_SYS_DDR_RAW_TIMING
-#endif
-
-#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
-
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
-
-/*
- * SMP Definitinos
- */
-#define CPU_RELEASE_ADDR secondary_boot_func
-
-#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
-#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
-/*
- * DDR controller use 0 as the base address for binding.
- * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
- */
-#define CONFIG_SYS_DP_DDR_BASE_PHY 0
-#define CONFIG_DP_DDR_CTRL 2
-#define CONFIG_DP_DDR_NUM_CTRLS 1
-
-/* Generic Timer Definitions */
-/*
- * This is not an accurate number. It is used in start.S. The frequency
- * will be udpated later when get_bus_freq(0) is available.
- */
-#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
-
-/* I2C */
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
-
-/* Serial Port */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/* IFC */
-#define CONFIG_FSL_IFC
-
-/*
- * During booting, IFC is mapped at the region of 0x30000000.
- * But this region is limited to 256MB. To accommodate NOR, promjet
- * and FPGA. This region is divided as below:
- * 0x30000000 - 0x37ffffff : 128MB : NOR flash
- * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
- * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
- *
- * To accommodate bigger NOR flash and other devices, we will map IFC
- * chip selects to as below:
- * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
- * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
- * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
- * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
- * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
- *
- * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
- * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
- */
-
-#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
-#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
-
-#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
-
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
-#ifndef __ASSEMBLY__
-unsigned long long get_qixis_addr(void);
-#endif
-#define QIXIS_BASE get_qixis_addr()
-#define QIXIS_BASE_PHYS 0x20000000
-#define QIXIS_BASE_PHYS_EARLY 0xC000000
-#define QIXIS_STAT_PRES1 0xb
-#define QIXIS_SDID_MASK 0x07
-#define QIXIS_ESDHC_NO_ADAPTER 0x7
-
-#define CONFIG_SYS_NAND_BASE 0x530000000ULL
-#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
-
-/* Debug Server firmware */
-#define CONFIG_FSL_DEBUG_SERVER
-/* 2 sec timeout */
-#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000)
-
-/* MC firmware */
-#define CONFIG_FSL_MC_ENET
-/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
-#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
-#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
-
-/*
- * Carve out a DDR region which will not be used by u-boot/Linux
- *
- * It will be used by MC and Debug Server. The MC region must be
- * 512MB aligned, so the min size to hide is 512MB.
- */
-#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
-#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
-#define CONFIG_SYS_MEM_TOP_HIDE_MIN (512UL * 1024 * 1024)
-#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide()
-#endif
-
-/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controler 1 */
-#define CONFIG_PCIE2 /* PCIE controler 2 */
-#define CONFIG_PCIE3 /* PCIE controler 3 */
-#define CONFIG_PCIE4 /* PCIE controler 4 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
-
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
-
-/* Command line configuration */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
-#define CONFIG_ARCH_EARLY_INIT_R
-
-/* Physical Memory Map */
-/* fixme: these need to be checked against the board */
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-
-#define CONFIG_NR_DRAM_BANKS 3
-
-#define CONFIG_HWCONFIG
-#define HWCONFIG_BUFFER_SIZE 128
-
-#define CONFIG_DISPLAY_CPUINFO
-
-/* Initial environment variables */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:bank_intlv=auto\0" \
- "loadaddr=0x80100000\0" \
- "kernel_addr=0x100000\0" \
- "ramdisk_addr=0x800000\0" \
- "ramdisk_size=0x2000000\0" \
- "fdt_high=0xa0000000\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "kernel_start=0x581200000\0" \
- "kernel_load=0xa0000000\0" \
- "kernel_size=0x2800000\0" \
- "console=ttyAMA0,38400n8\0"
-
-#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
- "earlycon=uart8250,mmio,0x21c0500,115200 " \
- "ramdisk_size=0x2000000 default_hugepagesz=2m" \
- " hugepagesz=2m hugepages=16"
-#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
- "$kernel_size && bootm $kernel_load"
-#define CONFIG_BOOTDELAY 10
-
-/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_MAXARGS 64 /* max command args */
-
-#ifndef __ASSEMBLY__
-unsigned long get_dram_size_to_hide(void);
-#endif
-
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
-
-#define CONFIG_SPL_BSS_START_ADDR 0x80100000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_MAX_SIZE 0x16000
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_TEXT_BASE 0x1800a000
-
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
-#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-
-#endif /* __LS2_COMMON_H */
+++ /dev/null
-/*
- * Copyright 2014 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __LS2_EMU_H
-#define __LS2_EMU_H
-
-#include "ls2085a_common.h"
-
-#define CONFIG_IDENT_STRING " LS2085A-EMU"
-#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU"
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 133333333
-
-#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
-#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
-
-#define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS3 0x53
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
-
-#define CONFIG_FSL_DDR_SYNC_REFRESH
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/*
- * NOR Flash Timing Params
- */
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
- FTIM0_NOR_TEADC(0x1) | \
- FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
- FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
- FTIM2_NOR_TCH(0x0) | \
- FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
-
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
-
-/*
- * This trick allows users to load MC images into DDR directly without
- * copying from NOR flash. It dramatically improves speed.
- */
-#define CONFIG_SYS_LS_MC_FW_IN_DDR
-#define CONFIG_SYS_LS_MC_DPL_IN_DDR
-#define CONFIG_SYS_LS_MC_DPC_IN_DDR
-
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
-
-/* Store environment at top of flash */
-#define CONFIG_ENV_IS_NOWHERE 1
-#define CONFIG_ENV_SIZE 0x1000
-
-#endif /* __LS2_EMU_H */
+++ /dev/null
-/*
- * Copyright (C) 2014 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __LS2_SIMU_H
-#define __LS2_SIMU_H
-
-#include "ls2085a_common.h"
-
-#define CONFIG_IDENT_STRING " LS2085A-SIMU"
-#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU"
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 133333333
-
-#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
-#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
-
-/* SMSC 91C111 ethernet configuration */
-#define CONFIG_SMC91111
-#define CONFIG_SMC91111_BASE (0x2210000)
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-
-/*
- * NOR Flash Timing Params
- */
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
- FTIM0_NOR_TEADC(0x1) | \
- FTIM0_NOR_TEAHC(0x1))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
- FTIM1_NOR_TRAD_NOR(0x1))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
- FTIM2_NOR_TCH(0x0) | \
- FTIM2_NOR_TWP(0x1))
-#define CONFIG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
-
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#endif
-
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-/* MMC */
-#define CONFIG_MMC
-#ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
-
-/* MC firmware */
-#define CONFIG_SYS_LS_MC_FW_IN_NOR
-#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL
-
-#define CONFIG_SYS_LS_MC_DPL_IN_NOR
-#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
-
-#define CONFIG_SYS_LS_MC_DPC_IN_NOR
-#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL
-
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
-
-/* Store environment at top of flash */
-#define CONFIG_ENV_IS_NOWHERE 1
-#define CONFIG_ENV_SIZE 0x1000
-
-#endif /* __LS2_SIMU_H */
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __LS2_QDS_H
-#define __LS2_QDS_H
-
-#include "ls2085a_common.h"
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-#define CONFIG_SYS_FSL_CLK
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
-
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS3 0x53
-#define SPD_EEPROM_ADDRESS4 0x54
-#define SPD_EEPROM_ADDRESS5 0x55
-#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
-
-/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
-
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1a) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
-
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
- CONFIG_SYS_FLASH_BASE + 0x40000000}
-#endif
-
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define QIXIS_LBMAP_SWITCH 0x06
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_LBMAP_NAND 0x09
-#define QIXIS_RST_CTL_RESET 0x31
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define QIXIS_RCW_SRC_NAND 0x107
-#define QIXIS_RST_FORCE_MEM 0x01
-
-#define CONFIG_SYS_CSPR3_EXT (0x0)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
- FTIM2_GPCM_TCH(0xf) | \
- FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET (896 * 1024)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SPL_PAD_TO 0x20000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
-#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
-#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x2000
-#endif
-
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
-
-/* MC firmware */
-#define CONFIG_SYS_LS_MC_FW_IN_NOR
-#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL
-
-#define CONFIG_SYS_LS_MC_DPL_IN_NOR
-#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL
-
-#define CONFIG_SYS_LS_MC_DPC_IN_NOR
-#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL
-
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
-#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
-#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x580900000ULL
-
-/*
- * I2C
- */
-#define I2C_MUX_PCA_ADDR 0x77
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
-
-/* I2C bus multiplexer */
-#define I2C_MUX_CH_DEFAULT 0x8
-
-/* SPI */
-#ifdef CONFIG_FSL_DSPI
-#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
-#endif
-
-/*
- * MMC
- */
-#ifdef CONFIG_MMC
-#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
- QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
-#endif
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_CMD_DATE
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-#define CONFIG_FSL_MEMAC
-#define CONFIG_PCI /* Enable PCIE */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI
-#endif
-
-/* MMC */
-#define CONFIG_MMC
-#ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-/* Initial environment variables */
-#undef CONFIG_EXTRA_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:bank_intlv=auto\0" \
- "loadaddr=0x80100000\0" \
- "kernel_addr=0x100000\0" \
- "ramdisk_addr=0x800000\0" \
- "ramdisk_size=0x2000000\0" \
- "fdt_high=0xa0000000\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "kernel_start=0x581100000\0" \
- "kernel_load=0xa0000000\0" \
- "kernel_size=0x28000000\0"
-
-#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_FSL_MEMAC
-#define CONFIG_PHYLIB
-#define CONFIG_PHYLIB_10G
-#define CONFIG_CMD_MII
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_TERANETICS
-#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
-#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
-#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
-#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-
-#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
-#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
-#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
-#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
-#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
-#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
-#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
-#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
-#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
-#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
-#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
-#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
-#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
-#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
-#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
-#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_ETHPRIME "DPNI1"
-#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
-
-#endif
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_CMD_EXT2
-
-#endif /* __LS2_QDS_H */
+++ /dev/null
-/*
- * Copyright 2015 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __LS2_RDB_H
-#define __LS2_RDB_H
-
-#include "ls2085a_common.h"
-
-#undef CONFIG_CONS_INDEX
-#define CONFIG_CONS_INDEX 2
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#define CONFIG_SYS_FSL_CLK
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ 133333333
-#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
-
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#define SPD_EEPROM_ADDRESS1 0x51
-#define SPD_EEPROM_ADDRESS2 0x52
-#define SPD_EEPROM_ADDRESS3 0x53
-#define SPD_EEPROM_ADDRESS4 0x54
-#define SPD_EEPROM_ADDRESS5 0x55
-#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
-
-/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
-
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
-
-#define CONFIG_SYS_NOR0_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1a) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x04000000
-#define CONFIG_SYS_IFC_CCR 0x01000000
-
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
- CONFIG_SYS_FLASH_BASE + 0x40000000}
-#endif
-
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
- | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
- | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
- | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
- FTIM0_NAND_TWP(0x30) | \
- FTIM0_NAND_TWCHT(0x0e) | \
- FTIM0_NAND_TWH(0x14))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
- FTIM1_NAND_TWBE(0xab) | \
- FTIM1_NAND_TRR(0x1c) | \
- FTIM1_NAND_TRP(0x30))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
- FTIM2_NAND_TREH(0x14) | \
- FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
-#define CONFIG_FSL_QIXIS /* use common QIXIS code */
-#define QIXIS_LBMAP_SWITCH 0x06
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_DFLTBANK 0x00
-#define QIXIS_LBMAP_ALTBANK 0x04
-#define QIXIS_LBMAP_NAND 0x09
-#define QIXIS_RST_CTL_RESET 0x31
-#define QIXIS_RST_CTL_RESET_EN 0x30
-#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
-#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
-#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
-#define QIXIS_RCW_SRC_NAND 0x119
-#define QIXIS_RST_FORCE_MEM 0x01
-
-#define CONFIG_SYS_CSPR3_EXT (0x0)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
-/* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
- FTIM2_GPCM_TCH(0xf) | \
- FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET (2048 * 1024)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_SPL_PAD_TO 0x80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x2000
-#endif
-
-/* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
-
-/* MC firmware */
-#define CONFIG_SYS_LS_MC_FW_IN_NOR
-#define CONFIG_SYS_LS_MC_FW_ADDR 0x580300000ULL
-
-#define CONFIG_SYS_LS_MC_DPL_IN_NOR
-#define CONFIG_SYS_LS_MC_DPL_ADDR 0x580700000ULL
-
-#define CONFIG_SYS_LS_MC_DPC_IN_NOR
-#define CONFIG_SYS_LS_MC_DPC_ADDR 0x580800000ULL
-
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
-#define CONFIG_SYS_LS_MC_AIOP_IMG_IN_NOR
-#define CONFIG_SYS_LS_MC_AIOP_IMG_ADDR 0x580900000ULL
-
-/*
- * I2C
- */
-#define I2C_MUX_PCA_ADDR 0x75
-#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
-
-/* I2C bus multiplexer */
-#define I2C_MUX_CH_DEFAULT 0x8
-
-/* SPI */
-#ifdef CONFIG_FSL_DSPI
-#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_BAR
-#endif
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_CMD_DATE
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-
-#define CONFIG_FSL_MEMAC
-#define CONFIG_PCI /* Enable PCIE */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI
-#endif
-
-/* MMC */
-#define CONFIG_MMC
-#ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-#endif
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
-#define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_CMD_EXT2
-
-/* Initial environment variables */
-#undef CONFIG_EXTRA_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:bank_intlv=auto\0" \
- "loadaddr=0x80100000\0" \
- "kernel_addr=0x100000\0" \
- "ramdisk_addr=0x800000\0" \
- "ramdisk_size=0x2000000\0" \
- "fdt_high=0xa0000000\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "kernel_start=0x581100000\0" \
- "kernel_load=0xa0000000\0" \
- "kernel_size=0x2800000\0"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
- "earlycon=uart8250,mmio,0x21c0600,115200 " \
- "ramdisk_size=0x2000000 default_hugepagesz=2m" \
- " hugepagesz=2m hugepages=16"
-
-/* MAC/PHY configuration */
-#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_AQUANTIA
-#define CONFIG_PHY_CORTINA
-#define CONFIG_PHYLIB
-#define CONFIG_SYS_CORTINA_FW_IN_NOR
-#define CONFIG_CORTINA_FW_ADDR 0x581000000
-#define CONFIG_CORTINA_FW_LENGTH 0x40000
-
-#define CORTINA_PHY_ADDR1 0x10
-#define CORTINA_PHY_ADDR2 0x11
-#define CORTINA_PHY_ADDR3 0x12
-#define CORTINA_PHY_ADDR4 0x13
-#define AQ_PHY_ADDR1 0x00
-#define AQ_PHY_ADDR2 0x01
-#define AQ_PHY_ADDR3 0x02
-#define AQ_PHY_ADDR4 0x03
-
-#define CONFIG_MII
-#define CONFIG_ETHPRIME "DPNI1"
-#define CONFIG_PHY_GIGE
-#define CONFIG_PHY_AQUANTIA
-#endif
-
-#endif /* __LS2_RDB_H */
#define CONFIG_SUPPORT_RAW_INITRD
/* ST M25P40 */
-#undef CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_STMICRO
#undef CONFIG_ENV_SPI_MAX_HZ
#define CONFIG_ENV_SPI_MAX_HZ 25000000
#undef CONFIG_SF_DEFAULT_SPEED
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
* Serial Port
*/
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* EEPROM */
#ifdef CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#endif
/* SPI FLASH */
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
*/
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (115200 * 16)
/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SPANSION
/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
# define CONSOLE_ARG "console=console=ttyUL0,115200\0"
#elif XILINX_UART16550_BASEADDR
-# define CONFIG_SYS_NS16550 1
# define CONFIG_SYS_NS16550_SERIAL
# if defined(__MICROBLAZEEL__)
# define CONFIG_SYS_NS16550_REG_SIZE -4
#ifdef SPIFLASH
# define CONFIG_SYS_NO_FLASH 1
# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
-# define CONFIG_XILINX_SPI 1
# define CONFIG_SPI 1
-# define CONFIG_SPI_FLASH_STMICRO 1
# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */
/*
* RTC configuration
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/*
* NS16550 Configuration
*/
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL)
-#define CONFIG_DW_SERIAL
-#endif
-
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#if !defined(CONFIG_DM_SERIAL)
* Common SPI Flash configuration
*/
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_MACRONIX 1
#endif
/*
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
/* this may vary and depends on the installed chip */
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#endif
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_CMD_TIME
-#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SYS_FSL_QSPI_LE
#define CONFIG_SYS_FSL_QSPI_AHB
#ifdef CONFIG_MX6SX_SABRESD_REVA
#define CONFIG_CMD_CACHE
#endif
-#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
* set Linux BASE_BAUD to 403200.
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
--- /dev/null
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ * Luka Perkov <luka.perkov@sartura.hr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_NSA310S_H
+#define _CONFIG_NSA310S_H
+
+/* high level configuration options */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KW88F6192 1 /* SOC Name */
+#define CONFIG_KW88F6702 1 /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/* add target to build it automatically upon "make" */
+#define CONFIG_BUILD_TARGET "u-boot.kwb"
+
+/* compression configuration */
+#define CONFIG_BZIP2
+#define CONFIG_LZMA
+
+/* commands configuration */
+#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* environment variables configuration */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_OFFSET 0xe0000
+
+/* default environment variables */
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part root; " \
+ "ubifsmount ubi:rootfs; " \
+ "ubifsload 0x800000 ${kernel}; " \
+ "ubifsload 0x700000 ${fdt}; " \
+ "ubifsumount; " \
+ "fdt addr 0x700000; fdt resize; fdt chosen; " \
+ "bootz 0x800000 - 0x700000"
+
+#define CONFIG_MTDPARTS \
+ "mtdparts=orion_nand:" \
+ "0xe0000@0x0(uboot)," \
+ "0x20000@0xe0000(uboot_env)," \
+ "0x100000@0x100000(second_stage_uboot)," \
+ "-@0x200000(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS \
+ "kernel=/boot/zImage\0" \
+ "fdt=/boot/nsa310s.dtb\0" \
+ "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0"
+
+/* Ethernet driver configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 1
+#define CONFIG_PHY_GIGE
+#define CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/* SATA driver configuration */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /* CONFIG_CMD_IDE */
+
+/* RTC driver configuration */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_NSA310S_H */
#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* NS16550 Configuration
*/
-#undef CONFIG_OMAP_SERIAL
+#undef CONFIG_SYS_NS16550_CLK
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
/*
* SERIAL
*/
-# define CONFIG_SYS_NS16550
# define CONFIG_SYS_NS16550_SERIAL
# define CONFIG_SYS_NS16550_REG_SIZE 1
# define CONFIG_CONS_INDEX 1
/* SF Configs */
#define CONFIG_CMD_SF
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
#if defined(CONFIG_SPI_FLASH)
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
#if defined(CONFIG_PCI)
/*
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
/* PCI host support */
#define CONFIG_PCI
-#define CONFIG_PCI_TEGRA
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PCI_ENUM
/* PCI networking support */
#define CONFIG_RTL8169
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ (8 * 1024 * 1024))
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
#define CONFIG_PHY_MICREL
/* QSPI Configs*/
-#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SYS_FSL_QSPI_LE
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* SPL */
#define CONFIG_SPL_POWER_SUPPORT
/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_QUAD
#define CONFIG_SYS_NO_FLASH
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_NE2000_BASE 0xb4000300
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 115200
#define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 115200
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
#undef CONFIG_INTEL_ICH6_GPIO
/* SPI is not supported */
-#undef CONFIG_ICH_SPI
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_NOWHERE
--- /dev/null
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_RK3036_COMMON_H
+#define __CONFIG_RK3036_COMMON_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_THUMB_BUILD
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
+#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
+#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_TEXT_BASE 0x60000000
+#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
+#define CONFIG_SYS_LOAD_ADDR 0x60800800
+#define CONFIG_SPL_STACK 0x10081fff
+#define CONFIG_SPL_TEXT_BASE 0x10081004
+
+#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10)
+#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
+
+#define CONFIG_ROCKCHIP_COMMON
+
+/* MMC/SD IP block */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_TIME
+
+#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CONFIG_NR_DRAM_BANKS 1
+#define SDRAM_BANK_SIZE (512UL << 20UL)
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+
+#define CONFIG_CMD_I2C
+
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x60000000\0" \
+ "pxefile_addr_r=0x60100000\0" \
+ "fdt_addr_r=0x61f00000\0" \
+ "kernel_addr_r=0x62000000\0" \
+ "ramdisk_addr_r=0x64000000\0"
+
+/* First try to boot from SD (index 0), then eMMC (index 1 */
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1)
+
+#include <config_distro_bootcmd.h>
+
+/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
+ * so limit the fdt reallocation to that */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x7fffffff\0" \
+ ENV_MEM_LAYOUT_SETTINGS \
+ BOOTENV
+#endif
+
+#endif
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_BAUDRATE 115200
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_COUNTER (TIMER7_BASE + 8)
+#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
+#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SPL_BOARD_INIT
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
#define CONFIG_SYS_TEXT_BASE 0x00100000
#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
#define CONFIG_SYS_LOAD_ADDR 0x00800800
#define CONFIG_SPL_STACK 0xff718000
#define CONFIG_SPL_TEXT_BASE 0xff704004
+#define CONFIG_ROCKCHIP_COMMON
+#define CONFIG_SPL_ROCKCHIP_COMMON
+
/* MMC/SD IP block */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SPI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_CMD_I2C
* limit the fdt reallocation to that */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x1fffffff\0" \
+ "initrd_high=0x1fffffff\0" \
ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
#endif
--- /dev/null
+/*
+ * Configuration file for the SAMA5D2 Xplained Board.
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* No NOR flash, this definition should put before common header */
+#define CONFIG_SYS_NO_FLASH
+
+#include "at91-sama5_common.h"
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE ATMEL_BASE_UART1
+#define CONFIG_USART_ID ATMEL_ID_UART1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE 0x20000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+#undef CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_PIO4
+
+/* SerialFlash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_ATMEL_SPI0
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#endif
+
+/* NAND flash */
+#undef CONFIG_CMD_NAND
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SDHCI
+#define CONFIG_ATMEL_SDHCI
+#define CONFIG_ATMEL_SDHCI0
+#define CONFIG_ATMEL_SDHCI1
+#define CONFIG_SUPPORT_EMMC_BOOT
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_USB_STORAGE
+#endif
+
+/* USB device */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_ATMEL_USBA
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2 XPlained"
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_MACB_SEARCH_PHY
+
+/* LCD */
+/* #define CONFIG_LCD */
+
+#ifdef CONFIG_LCD
+#define LCD_BPP LCD_COLOR16
+#define LCD_OUTPUT_BPP 24
+#define CONFIG_LCD_LOGO
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_HLCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#endif
+
+#ifdef CONFIG_SYS_USE_MMC
+
+/* bootstrap + u-boot + env in sd card */
+#undef FAT_ENV_DEVICE_AND_PART
+#undef CONFIG_BOOTCOMMAND
+
+#define FAT_ENV_DEVICE_AND_PART "1"
+#define CONFIG_BOOTCOMMAND "fatload mmc 1:1 0x21000000 at91-sama5d2_xplained.dtb; " \
+ "fatload mmc 1:1 0x22000000 zImage; " \
+ "bootz 0x22000000 - 0x21000000"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait"
+
+#endif
+
+#endif
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
#define CONFIG_ATMEL_SPI0
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 30000000
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
#define CONFIG_ATMEL_SPI0
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_CMD_SF
#define CONFIG_CMD_SF_TEST
#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_EON
-#define CONFIG_SPI_FLASH_GIGADEVICE
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_I2C
#define CONFIG_I2C_EDID
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
/* SPI */
#define CONFIG_SH_SPI 1
#define CONFIG_SH_SPI_BASE 0xfe002000
-#define CONFIG_SPI_FLASH_STMICRO 1
-#define CONFIG_SPI_FLASH_MACRONIX 1
/* MMCIF */
#define CONFIG_MMC 1
/* SPI */
#define CONFIG_SH_SPI 1
#define CONFIG_SH_SPI_BASE 0xfe002000
-#define CONFIG_SPI_FLASH_STMICRO 1
-#define CONFIG_SPI_FLASH_MACRONIX 1
/* MMCIF */
#define CONFIG_MMC 1
/* SPI */
#define CONFIG_SH_SPI 1
#define CONFIG_SH_SPI_BASE 0xfe002000
-#define CONFIG_SPI_FLASH_STMICRO 1
/* MMCIF */
#define CONFIG_MMC 1
#define CONFIG_SPI
#define CONFIG_OMAP3_SPI
#define CONFIG_MTD_DEVICE
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED (75000000)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_QUAD
#define CONFIG_SYS_NO_FLASH
*/
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_OMAP_SERIAL
-#else
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#endif
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_CONS_INDEX 3
#define CONFIG_SERIAL3 3
#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
#define __CONFIG_SOCFPGA_ARRIA5_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
/*
* The base address is configurable in QSys, each board must specify the
#define CONFIG_DWMMC
#define CONFIG_SOCFPGA_DWMMC
#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
/*
* QSPI support
*/
-#define CONFIG_CADENCE_QSPI
/* Enable multiple SPI NOR flash manufacturers */
-#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
-#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
#define CONFIG_CMD_MTDPARTS
/*
* Designware SPI support
*/
-#define CONFIG_DESIGNWARE_SPI
#define CONFIG_CMD_SPI
/*
* Serial Driver
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
#define __CONFIG_SOCFPGA_CYCLONE5_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
#ifndef __CONFIG_TERASIC_DE0_H__
#define __CONFIG_TERASIC_DE0_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
#ifndef __CONFIG_DENX_MCVEVK_H__
#define __CONFIG_DENX_MCVEVK_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#ifndef __CONFIG_TERASIC_SOCKIT_H__
#define __CONFIG_TERASIC_SOCKIT_H__
-#include <asm/arch/socfpga_base_addrs.h>
+#include <asm/arch/base_addr_ac5.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
"bootimage=zImage\0" \
"fdt_addr=100\0" \
"fdtimage=socfpga.dtb\0" \
- "fsloadcmd=ext2load\0" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"mmcroot=/dev/mmcblk0p2\0" \
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
--- /dev/null
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_SOCRATES_H__
+#define __CONFIG_SOCFPGA_SOCRATES_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "zImage"
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET 512 /* just after the MBR */
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER "EBV"
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME socfpga_socrates
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=zImage\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __CONFIG_SOCFPGA_SOCRATES_H__ */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* SPI */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_QUAD
#define CONFIG_SYS_NO_FLASH
* Serial Port
*/
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+ * QSPI support
+ */
#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
-#define CONFIG_CADENCE_QSPI
#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
-#define CONFIG_SPI_FLASH_WINBOND /* WINBOND */
#define CONFIG_CMD_SF
#endif
#define CONFIG_ARMV7_PSCI_NR_CPUS 2
#elif defined(CONFIG_MACH_SUN8I_A33)
#define CONFIG_ARMV7_PSCI_NR_CPUS 4
+#elif defined(CONFIG_MACH_SUN8I_H3)
+#define CONFIG_ARMV7_PSCI_NR_CPUS 4
#else
#error Unsupported sun8i variant
#endif
#endif
/* Serial & console */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
/* ns16550 reg in the low bits of cpu reg */
#define CONFIG_SYS_NS16550_CLK 24000000
-#ifdef CONFIG_DM_SERIAL
-# define CONFIG_DW_SERIAL
-#else
+#ifndef CONFIG_DM_SERIAL
# define CONFIG_SYS_NS16550_REG_SIZE -4
# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#endif
#define CONFIG_G_DNL_MANUFACTURER "Allwinner Technology"
#endif
+#ifdef CONFIG_USB_FUNCTION_DFU
+#define CONFIG_CMD_DFU
+#define CONFIG_DFU_RAM
+#endif
+
#ifdef CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
* 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
* 1M script, 1M pxe and the ramdisk at the end.
*/
+
+#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
+#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
+#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
+
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0xa000000\0" \
- "kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \
- "fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \
- "scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \
- "pxefile_addr_r=" __stringify(SDRAM_OFFSET(3200000)) "\0" \
- "ramdisk_addr_r=" __stringify(SDRAM_OFFSET(3300000)) "\0"
+ "kernel_addr_r=" KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" FDT_ADDR_R "\0" \
+ "scriptaddr=" SCRIPT_ADDR_R "\0" \
+ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
+ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0"
+
+#define DFU_ALT_INFO_RAM \
+ "dfu_alt_info_ram=" \
+ "kernel ram " KERNEL_ADDR_R " 0x1000000;" \
+ "fdt ram " FDT_ADDR_R " 0x100000;" \
+ "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0"
#ifdef CONFIG_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONSOLE_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
+ DFU_ALT_INFO_RAM \
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"console=ttyS0,115200\0" \
BOOTCMD_SUNXI_COMPAT \
*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_STMICRO
#define TAURUS_SPI_MASK (1 << 4)
#define TAURUS_SPI_CS_PIN AT91_PIN_PA3
/*
* UART configuration
*/
-#define CONFIG_DW_SERIAL
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK 166666666
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_MMC_ENV_PART 2
/* SPI */
-#define CONFIG_TEGRA20_SLINK
#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
/*
* NS16550 Configuration
*/
-#define CONFIG_TEGRA_SERIAL
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* Common HW configuration.
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_OMAP_SERIAL
-#endif
-
#include <asm/arch/omap.h>
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
/* UART Configuration */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
-#else
-#define CONFIG_KEYSTONE_SERIAL
#endif
#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
#endif
/* SPI Configuration */
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED 30000000
"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \
- "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
+ "burn_uboot_spi=sf probe; sf erase 0 0x80000; " \
"sf write ${loadaddr} 0 ${filesize}\0" \
"burn_uboot_nand=nand erase 0 0x100000; " \
"nand write ${loadaddr} 0 ${filesize}\0" \
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_OMAP_SERIAL
-#endif
-
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
/* NS16550 Configuration */
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#ifdef CONFIG_SPL_BUILD
# define CONFIG_SYS_NS16550_SERIAL
# define CONFIG_SYS_NS16550_REG_SIZE (-4)
-# define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#endif
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
/*
* Hardware drivers
*/
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK 48000000
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
-#else
-#define CONFIG_OMAP_SERIAL
#endif
#define CONFIG_CONS_INDEX 3
/*
* Hardware drivers
*/
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK 48000000
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK 48000000
-#else
-#define CONFIG_OMAP_SERIAL
#endif
/*
#define CONFIG_MXC_SPI
/* SPI Flash */
-#define CONFIG_SPI_FLASH_STMICRO
#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
/* EEPROM */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_BUS_NUM 1
#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
/* SPI */
-#define CONFIG_TEGRA20_SFLASH
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
/* PCI host support */
#define CONFIG_PCI
-#define CONFIG_PCI_TEGRA
#define CONFIG_PCI_PNP
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PCI_ENUM
/* PCI networking support */
#define CONFIG_RTL8169
#define CONFIG_OMAP3_SPI
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#ifdef CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
#define CONFIG_SYS_NS16550_CLK 12288000
#define CONFIG_SYS_NS16550_REG_SIZE -2
#endif
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 UART_1_BASE
#define CONFIG_CONS_INDEX 1
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_TEXT_BASE 0xe0000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#else
-#error "Unknown board variant"
#endif
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define GICD_BASE (0x2C010000)
#define GICC_BASE (0x2C02f000)
-#else
-#error "Unknown board variant"
#endif
#endif /* !CONFIG_GICV3 */
#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
-#define PHYS_SDRAM_2 (0x880000000)
/* Top 16MB reserved for secure world use */
#define DRAM_SEC_SIZE 0x01000000
#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
-#define PHYS_SDRAM_2_SIZE 0x180000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_2 (0x880000000)
+#define PHYS_SDRAM_2_SIZE 0x180000000
+#else
+#define CONFIG_NR_DRAM_BANKS 1
+#endif
+
/* Enable memtest */
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_BOOTDELAY 1
-#else
-#error "Unknown board variant"
#endif
-/* Do not preserve environment */
-#define CONFIG_ENV_IS_NOWHERE 1
-#define CONFIG_ENV_SIZE 0x1000
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS 64 /* max command args */
-/* Flash memory is available on the Juno board only */
-#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
-#define CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_FLASH_BASE 0x08000000
+/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT 259
+/* Store environment at top of flash in the same location as blank.img */
+/* in the Juno firmware. */
+#define CONFIG_ENV_ADDR 0x0BFC0000
+#define CONFIG_ENV_SECT_SIZE 0x00010000
#else
+#define CONFIG_SYS_FLASH_BASE 0x0C000000
+/* 256 x 256KiB sectors */
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+/* Store environment at top of flash */
+#define CONFIG_ENV_ADDR 0x0FFC0000
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#endif
+
#define CONFIG_CMD_ARMFLASH
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-#define CONFIG_SYS_FLASH_BASE 0x08000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
-/* Timeout values in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
-
-/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
-#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+#define FLASH_MAX_SECTOR_SIZE 0x00040000
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_IS_IN_FLASH 1
-#endif
#endif /* __VEXPRESS_AEMV8A_H */
#define CONFIG_PHY_MICREL
/* QSPI Configs*/
-#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SYS_FSL_QSPI_LE
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
/*-----------------------------------------------------------------------
* Serial Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
9600, 19200, 38400, 115200}
* CPU Features
*/
-#define CONFIG_SYS_X86_TSC_TIMER
-
#define CONFIG_SYS_STACK_SIZE (32 * 1024)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x200000
/*-----------------------------------------------------------------------
* FLASH configuration
*/
-#define CONFIG_ICH_SPI
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CMD_SF
#define CONFIG_CMD_SF_TEST
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
#else
#ifdef XPAR_UARTNS550_0_BASEADDR
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 4
#define CONFIG_CONS_INDEX 1
/* SPI */
#ifdef CONFIG_ZYNQ_SPI
-# define CONFIG_SPI_FLASH_SST
# define CONFIG_CMD_SF
#endif
* Serial Port
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
/* SPI */
#ifdef CONFIG_ZYNQ_SPI
-# define CONFIG_SPI_FLASH_SST
# define CONFIG_CMD_SF
#endif
#ifdef CONFIG_ZYNQ_QSPI
# define CONFIG_SF_DEFAULT_SPEED 30000000
# define CONFIG_SPI_FLASH_ISSI
-# define CONFIG_SPI_FLASH_SPANSION
-# define CONFIG_SPI_FLASH_STMICRO
-# define CONFIG_SPI_FLASH_WINBOND
# define CONFIG_SPI_FLASH_BAR
# define CONFIG_CMD_SF
#endif
# define CONFIG_ZYNQ_GEM0
# define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
# define CONFIG_ZYNQ_SDHCI0
-# define CONFIG_ZYNQ_SPI
#elif defined(CONFIG_ZC770_XM011)
--- /dev/null
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+
+/* core clocks */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_GPLL 3
+#define ARMCLK 4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU 64
+#define SCLK_SPI 65
+#define SCLK_SDMMC 68
+#define SCLK_SDIO 69
+#define SCLK_EMMC 71
+#define SCLK_NANDC 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S 82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER0 85
+#define SCLK_TIMER1 86
+#define SCLK_TIMER2 87
+#define SCLK_TIMER3 88
+#define SCLK_OTGPHY0 93
+#define SCLK_LCDC 100
+#define SCLK_HDMI 109
+#define SCLK_HEVC 111
+#define SCLK_I2S_OUT 113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV 115
+#define SCLK_EMMC_DRV 117
+#define SCLK_SDMMC_SAMPLE 118
+#define SCLK_SDIO_SAMPLE 119
+#define SCLK_EMMC_SAMPLE 121
+#define SCLK_PVTM_CORE 123
+#define SCLK_PVTM_GPU 124
+#define SCLK_PVTM_VIDEO 125
+#define SCLK_MAC 151
+#define SCLK_MACREF 152
+#define SCLK_SFC 160
+
+#define DCLK_LCDC 190
+
+/* aclk gates */
+#define ACLK_DMAC2 194
+#define ACLK_LCDC 197
+#define ACLK_VIO 203
+#define ACLK_VCODEC 208
+#define ACLK_CPU 209
+#define ACLK_PERI 210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GRF 329
+#define PCLK_I2C0 332
+#define PCLK_I2C1 333
+#define PCLK_I2C2 334
+#define PCLK_SPI 338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_PWM 350
+#define PCLK_TIMER 353
+#define PCLK_HDMI 360
+#define PCLK_CPU 362
+#define PCLK_PERI 363
+#define PCLK_DDRUPCTL 364
+#define PCLK_WDT 368
+
+/* hclk gates */
+#define HCLK_OTG0 449
+#define HCLK_OTG1 450
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO 457
+#define HCLK_EMMC 459
+#define HCLK_I2S 462
+#define HCLK_LCDC 465
+#define HCLK_ROM 467
+#define HCLK_VIO_BUS 472
+#define HCLK_VCODEC 476
+#define HCLK_CPU 477
+#define HCLK_PERI 478
+
+#define CLK_NR_CLKS (HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE0_DBG 4
+#define SRST_CORE1_DBG 5
+#define SRST_CORE0_POR 8
+#define SRST_CORE1_POR 9
+#define SRST_L2C 12
+#define SRST_TOPDBG 13
+#define SRST_STRC_SYS_A 14
+#define SRST_PD_CORE_NIU 15
+
+#define SRST_TIMER2 16
+#define SRST_CPUSYS_H 17
+#define SRST_AHB2APB_H 19
+#define SRST_TIMER3 20
+#define SRST_INTMEM 21
+#define SRST_ROM 22
+#define SRST_PERI_NIU 23
+#define SRST_I2S 24
+#define SRST_DDR_PLL 25
+#define SRST_GPU_DLL 26
+#define SRST_TIMER0 27
+#define SRST_TIMER1 28
+#define SRST_CORE_DLL 29
+#define SRST_EFUSE_P 30
+#define SRST_ACODEC_P 31
+
+#define SRST_GPIO0 32
+#define SRST_GPIO1 33
+#define SRST_GPIO2 34
+#define SRST_UART0 39
+#define SRST_UART1 40
+#define SRST_UART2 41
+#define SRST_I2C0 43
+#define SRST_I2C1 44
+#define SRST_I2C2 45
+#define SRST_SFC 47
+
+#define SRST_PWM0 48
+#define SRST_DAP 51
+#define SRST_DAP_SYS 52
+#define SRST_GRF 55
+#define SRST_PERIPHSYS_A 57
+#define SRST_PERIPHSYS_H 58
+#define SRST_PERIPHSYS_P 59
+#define SRST_CPU_PERI 61
+#define SRST_EMEM_PERI 62
+#define SRST_USB_PERI 63
+
+#define SRST_DMA2 64
+#define SRST_MAC 66
+#define SRST_NANDC 68
+#define SRST_USBOTG0 69
+#define SRST_OTGC0 71
+#define SRST_USBOTG1 72
+#define SRST_OTGC1 74
+#define SRST_DDRMSCH 79
+
+#define SRST_MMC0 81
+#define SRST_SDIO 82
+#define SRST_EMMC 83
+#define SRST_SPI0 84
+#define SRST_WDT 86
+#define SRST_DDRPHY 88
+#define SRST_DDRPHY_P 89
+#define SRST_DDRCTRL 90
+#define SRST_DDRCTRL_P 91
+
+#define SRST_HDMI_P 96
+#define SRST_VIO_BUS_H 99
+#define SRST_UTMI0 103
+#define SRST_UTMI1 104
+#define SRST_USBPOR 105
+
+#define SRST_VCODEC_A 112
+#define SRST_VCODEC_H 113
+#define SRST_VIO1_A 114
+#define SRST_HEVC 115
+#define SRST_VCODEC_NIU_A 116
+#define SRST_LCDC1_A 117
+#define SRST_LCDC1_H 118
+#define SRST_LCDC1_D 119
+#define SRST_GPU 120
+#define SRST_GPU_NIU_A 122
+
+#define SRST_DBG_P 131
+
+#endif
/* Status Register */
#define DWMCI_BUSY (1 << 9)
+#define DWMCI_FIFO_MASK 0x1ff
+#define DWMCI_FIFO_SHIFT 17
/* FIFOTH Register */
#define MSIZE(x) ((x) << 28)
unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
struct mmc_config cfg;
+
+ /* use fifo mode to read and write data */
+ bool fifo_mode;
};
struct dwmci_idmac {
COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */
- COMPAT_NVIDIA_TEGRA124_PCIE, /* Tegra 124 PCIe controller */
- COMPAT_NVIDIA_TEGRA210_PCIE, /* Tegra 210 PCIe controller */
- COMPAT_NVIDIA_TEGRA30_PCIE, /* Tegra 30 PCIe controller */
- COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */
COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
/* Tegra124 XUSB pad controller */
COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
#ifndef _FLASH_H_
#define _FLASH_H_
-#ifndef CONFIG_SYS_NO_FLASH
+#ifndef CONFIG_SYS_MAX_FLASH_SECT
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#endif
+
/*-----------------------------------------------------------------------
* FLASH Info: contains chip specific data, per FLASH bank
*/
#define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */
#define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */
-#endif /* !CONFIG_SYS_NO_FLASH */
-
#endif /* _FLASH_H_ */
/* Command IDs */
#define DPBP_CMDID_CLOSE 0x800
#define DPBP_CMDID_OPEN 0x804
+#define DPBP_CMDID_CREATE 0x904
+#define DPBP_CMDID_DESTROY 0x900
#define DPBP_CMDID_ENABLE 0x002
#define DPBP_CMDID_DISABLE 0x003
uint32_t cmd_flags,
uint16_t token);
+/**
+ * struct dpbp_cfg - Structure representing DPBP configuration
+ * @options: place holder
+ */
+struct dpbp_cfg {
+ uint32_t options;
+};
+
+/**
+ * dpbp_create() - Create the DPBP object.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg: Configuration structure
+ * @token: Returned token; use in subsequent API calls
+ *
+ * Create the DPBP object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpbp_open function to get an authentication
+ * token first.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpbp_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpbp_cfg *cfg,
+ uint16_t *token);
+
+/**
+ * dpbp_destroy() - Destroy the DPBP object and release all its resources.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPBP object
+ *
+ * Return: '0' on Success; error code otherwise.
+ */
+int dpbp_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
/**
* dpbp_enable() - Enable the DPBP.
* @mc_io: Pointer to MC portal's I/O object
/* Command IDs */
#define DPIO_CMDID_CLOSE 0x800
#define DPIO_CMDID_OPEN 0x803
+#define DPIO_CMDID_CREATE 0x903
+#define DPIO_CMDID_DESTROY 0x900
#define DPIO_CMDID_ENABLE 0x002
#define DPIO_CMDID_DISABLE 0x003
#define DPIO_CMD_OPEN(cmd, dpio_id) \
MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id)
+/* cmd, param, offset, width, type, arg_name */
+#define DPIO_CMD_CREATE(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 16, 2, enum dpio_channel_mode, \
+ cfg->channel_mode);\
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->num_priorities);\
+} while (0)
+
/* cmd, param, offset, width, type, arg_name */
#define DPIO_RSP_GET_ATTR(cmd, attr) \
do { \
DPIO_LOCAL_CHANNEL = 1,
};
+/**
+ * struct dpio_cfg - Structure representing DPIO configuration
+ * @channel_mode: Notification channel mode
+ * @num_priorities: Number of priorities for the notification channel (1-8);
+ * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
+ */
+struct dpio_cfg {
+ enum dpio_channel_mode channel_mode;
+ uint8_t num_priorities;
+};
+
+/**
+ * dpio_create() - Create the DPIO object.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg: Configuration structure
+ * @token: Returned token; use in subsequent API calls
+ *
+ * Create the DPIO object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ *
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpio_open() function to get an authentication
+ * token first.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpio_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpio_cfg *cfg,
+ uint16_t *token);
+
+/**
+ * dpio_destroy() - Destroy the DPIO object and release all its resources.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPIO object
+ *
+ * Return: '0' on Success; Error code otherwise
+ */
+int dpio_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
/**
* dpio_enable() - Enable the DPIO, allow I/O portal operations.
* @mc_io: Pointer to MC portal's I/O object
--- /dev/null
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_DPMAC_H
+#define __FSL_DPMAC_H
+
+/* DPMAC Version */
+#define DPMAC_VER_MAJOR 3
+#define DPMAC_VER_MINOR 1
+
+/* Command IDs */
+#define DPMAC_CMDID_CLOSE 0x800
+#define DPMAC_CMDID_OPEN 0x80c
+#define DPMAC_CMDID_CREATE 0x90c
+#define DPMAC_CMDID_DESTROY 0x900
+
+#define DPMAC_CMDID_GET_ATTR 0x004
+#define DPMAC_CMDID_RESET 0x005
+
+#define DPMAC_CMDID_MDIO_READ 0x0c0
+#define DPMAC_CMDID_MDIO_WRITE 0x0c1
+#define DPMAC_CMDID_GET_LINK_CFG 0x0c2
+#define DPMAC_CMDID_SET_LINK_STATE 0x0c3
+#define DPMAC_CMDID_GET_COUNTER 0x0c4
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_CREATE(cmd, cfg) \
+ MC_CMD_OP(cmd, 0, 0, 32, int, cfg->mac_id)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_OPEN(cmd, dpmac_id) \
+ MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\
+ MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\
+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, attr->version.major);\
+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, attr->version.minor);\
+ MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\
+ MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\
+ MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_MDIO_READ(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \
+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_RSP_MDIO_READ(cmd, data) \
+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \
+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \
+ MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \
+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \
+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \
+ MC_CMD_OP(cmd, 2, 0, 1, int, cfg->up); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_GET_COUNTER(cmd, type) \
+ MC_CMD_OP(cmd, 0, 0, 8, enum dpmac_counter, type)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPMAC_RSP_GET_COUNTER(cmd, counter) \
+ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter)
+
+/* Data Path MAC API
+ * Contains initialization APIs and runtime control APIs for DPMAC
+ */
+
+struct fsl_mc_io;
+
+/**
+ * dpmac_open() - Open a control session for the specified object.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpmac_id: DPMAC unique ID
+ * @token: Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpmac_create function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int dpmac_id,
+ uint16_t *token);
+
+/**
+ * dpmac_close() - Close the control session of the object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_close(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * enum dpmac_link_type - DPMAC link type
+ * @DPMAC_LINK_TYPE_NONE: No link
+ * @DPMAC_LINK_TYPE_FIXED: Link is fixed type
+ * @DPMAC_LINK_TYPE_PHY: Link by PHY ID
+ * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type
+ */
+enum dpmac_link_type {
+ DPMAC_LINK_TYPE_NONE,
+ DPMAC_LINK_TYPE_FIXED,
+ DPMAC_LINK_TYPE_PHY,
+ DPMAC_LINK_TYPE_BACKPLANE
+};
+
+/**
+ * enum dpmac_eth_if - DPMAC Ethrnet interface
+ * @DPMAC_ETH_IF_MII: MII interface
+ * @DPMAC_ETH_IF_RMII: RMII interface
+ * @DPMAC_ETH_IF_SMII: SMII interface
+ * @DPMAC_ETH_IF_GMII: GMII interface
+ * @DPMAC_ETH_IF_RGMII: RGMII interface
+ * @DPMAC_ETH_IF_SGMII: SGMII interface
+ * @DPMAC_ETH_IF_QSGMII: QSGMII interface
+ * @DPMAC_ETH_IF_XAUI: XAUI interface
+ * @DPMAC_ETH_IF_XFI: XFI interface
+ */
+enum dpmac_eth_if {
+ DPMAC_ETH_IF_MII,
+ DPMAC_ETH_IF_RMII,
+ DPMAC_ETH_IF_SMII,
+ DPMAC_ETH_IF_GMII,
+ DPMAC_ETH_IF_RGMII,
+ DPMAC_ETH_IF_SGMII,
+ DPMAC_ETH_IF_QSGMII,
+ DPMAC_ETH_IF_XAUI,
+ DPMAC_ETH_IF_XFI
+};
+
+/**
+ * struct dpmac_cfg - Structure representing DPMAC configuration
+ * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP,
+ * the MAC IDs are continuous.
+ * For example: 2 WRIOPs, 16 MACs in each:
+ * MAC IDs for the 1st WRIOP: 1-16,
+ * MAC IDs for the 2nd WRIOP: 17-32.
+ */
+struct dpmac_cfg {
+ int mac_id;
+};
+
+/**
+ * dpmac_create() - Create the DPMAC object.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg: Configuration structure
+ * @token: Returned token; use in subsequent API calls
+ *
+ * Create the DPMAC object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpmac_open function to get an authentication
+ * token first.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpmac_cfg *cfg,
+ uint16_t *token);
+
+/**
+ * dpmac_destroy() - Destroy the DPMAC object and release all its resources.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ *
+ * Return: '0' on Success; error code otherwise.
+ */
+int dpmac_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/* DPMAC IRQ Index and Events */
+
+/* IRQ index */
+#define DPMAC_IRQ_INDEX 0
+/* IRQ event - indicates a change in link state */
+#define DPMAC_IRQ_EVENT_LINK_CFG_REQ 0x00000001
+/* irq event - Indicates that the link state changed */
+#define DPMAC_IRQ_EVENT_LINK_CHANGED 0x00000002
+
+/**
+ * struct dpmac_attr - Structure representing DPMAC attributes
+ * @id: DPMAC object ID
+ * @phy_id: PHY ID
+ * @link_type: link type
+ * @eth_if: Ethernet interface
+ * @max_rate: Maximum supported rate - in Mbps
+ * @version: DPMAC version
+ */
+struct dpmac_attr {
+ int id;
+ int phy_id;
+ enum dpmac_link_type link_type;
+ enum dpmac_eth_if eth_if;
+ uint32_t max_rate;
+ /**
+ * struct version - Structure representing DPMAC version
+ * @major: DPMAC major version
+ * @minor: DPMAC minor version
+ */
+ struct {
+ uint16_t major;
+ uint16_t minor;
+ } version;
+};
+
+/**
+ * dpmac_get_attributes - Retrieve DPMAC attributes.
+ *
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @attr: Returned object's attributes
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_get_attributes(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_attr *attr);
+
+/**
+ * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters
+ * @phy_addr: MDIO device address
+ * @reg: Address of the register within the Clause 45 PHY device from which data
+ * is to be read
+ * @data: Data read/write from/to MDIO
+ */
+struct dpmac_mdio_cfg {
+ uint8_t phy_addr;
+ uint8_t reg;
+ uint16_t data;
+};
+
+/**
+ * dpmac_mdio_read() - Perform MDIO read transaction
+ * @mc_io: Pointer to opaque I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @cfg: Structure with MDIO transaction parameters
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_mdio_read(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_mdio_cfg *cfg);
+
+/**
+ * dpmac_mdio_write() - Perform MDIO write transaction
+ * @mc_io: Pointer to opaque I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @cfg: Structure with MDIO transaction parameters
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_mdio_write(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_mdio_cfg *cfg);
+
+/* DPMAC link configuration/state options */
+
+/* Enable auto-negotiation */
+#define DPMAC_LINK_OPT_AUTONEG 0x0000000000000001ULL
+/* Enable half-duplex mode */
+#define DPMAC_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL
+/* Enable pause frames */
+#define DPMAC_LINK_OPT_PAUSE 0x0000000000000004ULL
+/* Enable a-symmetric pause frames */
+#define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL
+
+/**
+ * struct dpmac_link_cfg - Structure representing DPMAC link configuration
+ * @rate: Link's rate - in Mbps
+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
+ */
+struct dpmac_link_cfg {
+ uint32_t rate;
+ uint64_t options;
+};
+
+/**
+ * dpmac_get_link_cfg() - Get Ethernet link configuration
+ * @mc_io: Pointer to opaque I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @cfg: Returned structure with the link configuration
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_link_cfg *cfg);
+
+/**
+ * struct dpmac_link_state - DPMAC link configuration request
+ * @rate: Rate in Mbps
+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
+ * @up: Link state
+ */
+struct dpmac_link_state {
+ uint32_t rate;
+ uint64_t options;
+ int up;
+};
+
+/**
+ * dpmac_set_link_state() - Set the Ethernet link status
+ * @mc_io: Pointer to opaque I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @link_state: Link state configuration
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpmac_set_link_state(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpmac_link_state *link_state);
+
+/**
+ * enum dpni_counter - DPNI counter types
+ * @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-octet frame and larger
+ * (up to max frame length specified),
+ * good or bad.
+ * @DPMAC_CNT_ING_FRAG: counts packet which is shorter than 64 octets received
+ * with a wrong CRC
+ * @DPMAC_CNT_ING_JABBER: counts packet longer than the maximum frame length
+ * specified, with a bad frame check sequence.
+ * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped packet due to internal errors.
+ * Occurs when a receive FIFO overflows.
+ * Includes also packets truncated as a result of
+ * the receive FIFO overflow.
+ * @DPMAC_CNT_ING_ALIGN_ERR: counts frame with an alignment error
+ * (optional used for wrong SFD)
+ * @DPMAC_CNT_EGR_UNDERSIZED: counts packet transmitted that was less than 64
+ * octets long with a good CRC.
+ * @DPMAC_CNT_ING_OVERSIZED: counts packet longer than the maximum frame length
+ * specified, with a good frame check sequence.
+ * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frame (regular and PFC).
+ * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frame transmitted
+ * (regular and PFC).
+ * @DPMAC_CNT_ING_BYTE: counts octet received except preamble for all valid
+ * frames and valid pause frames.
+ * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frame
+ * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frame
+ * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad packet received.
+ * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frame
+ * @DPMAC_CNT_ING_ERR_FRAME: counts frame received with an error
+ * (except for undersized/fragment frame)
+ * @DPMAC_CNT_EGR_BYTE: counts octet transmitted except preamble for all valid
+ * frames and valid pause frames transmitted.
+ * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frame
+ * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frame
+ * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frame
+ * @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error
+ * @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including
+ * pause frames.
+ */
+enum dpmac_counter {
+ DPMAC_CNT_ING_FRAME_64,
+ DPMAC_CNT_ING_FRAME_127,
+ DPMAC_CNT_ING_FRAME_255,
+ DPMAC_CNT_ING_FRAME_511,
+ DPMAC_CNT_ING_FRAME_1023,
+ DPMAC_CNT_ING_FRAME_1518,
+ DPMAC_CNT_ING_FRAME_1519_MAX,
+ DPMAC_CNT_ING_FRAG,
+ DPMAC_CNT_ING_JABBER,
+ DPMAC_CNT_ING_FRAME_DISCARD,
+ DPMAC_CNT_ING_ALIGN_ERR,
+ DPMAC_CNT_EGR_UNDERSIZED,
+ DPMAC_CNT_ING_OVERSIZED,
+ DPMAC_CNT_ING_VALID_PAUSE_FRAME,
+ DPMAC_CNT_EGR_VALID_PAUSE_FRAME,
+ DPMAC_CNT_ING_BYTE,
+ DPMAC_CNT_ING_MCAST_FRAME,
+ DPMAC_CNT_ING_BCAST_FRAME,
+ DPMAC_CNT_ING_ALL_FRAME,
+ DPMAC_CNT_ING_UCAST_FRAME,
+ DPMAC_CNT_ING_ERR_FRAME,
+ DPMAC_CNT_EGR_BYTE,
+ DPMAC_CNT_EGR_MCAST_FRAME,
+ DPMAC_CNT_EGR_BCAST_FRAME,
+ DPMAC_CNT_EGR_UCAST_FRAME,
+ DPMAC_CNT_EGR_ERR_FRAME,
+ DPMAC_CNT_ING_GOOD_FRAME
+};
+
+/**
+ * dpmac_get_counter() - Read a specific DPMAC counter
+ * @mc_io: Pointer to opaque I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPMAC object
+ * @type: The requested counter
+ * @counter: Returned counter value
+ *
+ * Return: The requested counter; '0' otherwise.
+ */
+int dpmac_get_counter(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpmac_counter type,
+ uint64_t *counter);
+
+#endif /* __FSL_DPMAC_H */
/* Command IDs */
#define DPNI_CMDID_OPEN 0x801
#define DPNI_CMDID_CLOSE 0x800
+#define DPNI_CMDID_CREATE 0x901
+#define DPNI_CMDID_DESTROY 0x900
#define DPNI_CMDID_ENABLE 0x002
#define DPNI_CMDID_DISABLE 0x003
#define DPNI_CMD_OPEN(cmd, dpni_id) \
MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id)
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_CREATE(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->adv.max_tcs); \
+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->adv.max_senders); \
+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->mac_addr[5]); \
+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->mac_addr[4]); \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->mac_addr[3]); \
+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->mac_addr[2]); \
+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->mac_addr[1]); \
+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->mac_addr[0]); \
+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->adv.options); \
+ MC_CMD_OP(cmd, 2, 0, 8, uint8_t, cfg->adv.max_unicast_filters); \
+ MC_CMD_OP(cmd, 2, 8, 8, uint8_t, cfg->adv.max_multicast_filters); \
+ MC_CMD_OP(cmd, 2, 16, 8, uint8_t, cfg->adv.max_vlan_filters); \
+ MC_CMD_OP(cmd, 2, 24, 8, uint8_t, cfg->adv.max_qos_entries); \
+ MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \
+ MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \
+ MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \
+ MC_CMD_OP(cmd, 3, 0, 8, uint8_t, cfg->adv.max_dist_per_tc[0]); \
+ MC_CMD_OP(cmd, 3, 8, 8, uint8_t, cfg->adv.max_dist_per_tc[1]); \
+ MC_CMD_OP(cmd, 3, 16, 8, uint8_t, cfg->adv.max_dist_per_tc[2]); \
+ MC_CMD_OP(cmd, 3, 24, 8, uint8_t, cfg->adv.max_dist_per_tc[3]); \
+ MC_CMD_OP(cmd, 3, 32, 8, uint8_t, cfg->adv.max_dist_per_tc[4]); \
+ MC_CMD_OP(cmd, 3, 40, 8, uint8_t, cfg->adv.max_dist_per_tc[5]); \
+ MC_CMD_OP(cmd, 3, 48, 8, uint8_t, cfg->adv.max_dist_per_tc[6]); \
+ MC_CMD_OP(cmd, 3, 56, 8, uint8_t, cfg->adv.max_dist_per_tc[7]); \
+ MC_CMD_OP(cmd, 4, 0, 16, uint16_t, \
+ cfg->adv.ipr_cfg.max_reass_frm_size); \
+ MC_CMD_OP(cmd, 4, 16, 16, uint16_t, \
+ cfg->adv.ipr_cfg.min_frag_size_ipv4); \
+ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, \
+ cfg->adv.ipr_cfg.min_frag_size_ipv6); \
+ MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \
+ MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \
+ MC_CMD_OP(cmd, 5, 0, 16, uint16_t, \
+ cfg->adv.ipr_cfg.max_open_frames_ipv4); \
+ MC_CMD_OP(cmd, 5, 16, 16, uint16_t, \
+ cfg->adv.ipr_cfg.max_open_frames_ipv6); \
+} while (0)
/* cmd, param, offset, width, type, arg_name */
#define DPNI_CMD_SET_POOLS(cmd, cfg) \
uint32_t cmd_flags,
uint16_t token);
+/* DPNI configuration options */
+
+/**
+ * Allow different distribution key profiles for different traffic classes;
+ * if not set, a single key profile is assumed
+ */
+#define DPNI_OPT_ALLOW_DIST_KEY_PER_TC 0x00000001
+
+/**
+ * Disable all non-error transmit confirmation; error frames are reported
+ * back to a common Tx error queue
+ */
+#define DPNI_OPT_TX_CONF_DISABLED 0x00000002
+
+/* Disable per-sender private Tx confirmation/error queue */
+#define DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED 0x00000004
+
+/**
+ * Support distribution based on hashed key;
+ * allows statistical distribution over receive queues in a traffic class
+ */
+#define DPNI_OPT_DIST_HASH 0x00000010
+
+/**
+ * Support distribution based on flow steering;
+ * allows explicit control of distribution over receive queues in a traffic
+ * class
+ */
+#define DPNI_OPT_DIST_FS 0x00000020
+
+/* Unicast filtering support */
+#define DPNI_OPT_UNICAST_FILTER 0x00000080
+/* Multicast filtering support */
+#define DPNI_OPT_MULTICAST_FILTER 0x00000100
+/* VLAN filtering support */
+#define DPNI_OPT_VLAN_FILTER 0x00000200
+/* Support IP reassembly on received packets */
+#define DPNI_OPT_IPR 0x00000800
+/* Support IP fragmentation on transmitted packets */
+#define DPNI_OPT_IPF 0x00001000
+/* VLAN manipulation support */
+#define DPNI_OPT_VLAN_MANIPULATION 0x00010000
+/* Support masking of QoS lookup keys */
+#define DPNI_OPT_QOS_MASK_SUPPORT 0x00020000
+/* Support masking of Flow Steering lookup keys */
+#define DPNI_OPT_FS_MASK_SUPPORT 0x00040000
+
/**
* struct dpni_ipr_cfg - Structure representing IP reassembly configuration
* @max_reass_frm_size: Maximum size of the reassembled frame
uint16_t max_open_frames_ipv6;
};
+/**
+ * struct dpni_cfg - Structure representing DPNI configuration
+ * @mac_addr: Primary MAC address
+ * @adv: Advanced parameters; default is all zeros;
+ * use this structure to change default settings
+ */
+struct dpni_cfg {
+ uint8_t mac_addr[6];
+ /**
+ * struct adv - Advanced parameters
+ * @options: Mask of available options; use 'DPNI_OPT_<X>' values
+ * @start_hdr: Selects the packet starting header for parsing;
+ * 'NET_PROT_NONE' is treated as default: 'NET_PROT_ETH'
+ * @max_senders: Maximum number of different senders; used as the number
+ * of dedicated Tx flows; Non-power-of-2 values are rounded
+ * up to the next power-of-2 value as hardware demands it;
+ * '0' will be treated as '1'
+ * @max_tcs: Maximum number of traffic classes (for both Tx and Rx);
+ * '0' will e treated as '1'
+ * @max_dist_per_tc: Maximum distribution size per Rx traffic class;
+ * Must be set to the required value minus 1;
+ * i.e. 0->1, 1->2, ... ,255->256;
+ * Non-power-of-2 values are rounded up to the next
+ * power-of-2 value as hardware demands it
+ * @max_unicast_filters: Maximum number of unicast filters;
+ * '0' is treated as '16'
+ * @max_multicast_filters: Maximum number of multicast filters;
+ * '0' is treated as '64'
+ * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in
+ * the QoS table; '0' is treated as '64'
+ * @max_qos_key_size: Maximum key size for the QoS look-up;
+ * '0' is treated as '24' which is enough for IPv4
+ * 5-tuple
+ * @max_dist_key_size: Maximum key size for the distribution;
+ * '0' is treated as '24' which is enough for IPv4 5-tuple
+ * @max_policers: Maximum number of policers;
+ * should be between '0' and max_tcs
+ * @max_congestion_ctrl: Maximum number of congestion control groups
+ * (CGs); covers early drop and congestion notification
+ * requirements for traffic classes;
+ * should be between '0' and max_tcs
+ * @ipr_cfg: IP reassembly configuration
+ */
+ struct {
+ uint32_t options;
+ enum net_prot start_hdr;
+ uint8_t max_senders;
+ uint8_t max_tcs;
+ uint8_t max_dist_per_tc[DPNI_MAX_TC];
+ uint8_t max_unicast_filters;
+ uint8_t max_multicast_filters;
+ uint8_t max_vlan_filters;
+ uint8_t max_qos_entries;
+ uint8_t max_qos_key_size;
+ uint8_t max_dist_key_size;
+ uint8_t max_policers;
+ uint8_t max_congestion_ctrl;
+ struct dpni_ipr_cfg ipr_cfg;
+ } adv;
+};
+
+/**
+ * dpni_create() - Create the DPNI object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg: Configuration structure
+ * @token: Returned token; use in subsequent API calls
+ *
+ * Create the DPNI object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ *
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpni_open() function to get an authentication
+ * token first.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_create(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ const struct dpni_cfg *cfg,
+ uint16_t *token);
+
+/**
+ * dpni_destroy() - Destroy the DPNI object and release all its resources.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ *
+ * Return: '0' on Success; error code otherwise.
+ */
+int dpni_destroy(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
/**
* struct dpni_pools_cfg - Structure representing buffer pools configuration
* @num_dpbp: Number of DPBPs
/* Command IDs */
#define DPRC_CMDID_CLOSE 0x800
#define DPRC_CMDID_OPEN 0x805
+#define DPRC_CMDID_CREATE 0x905
#define DPRC_CMDID_GET_ATTR 0x004
#define DPRC_CMDID_RESET_CONT 0x005
+#define DPRC_CMDID_CREATE_CONT 0x151
+#define DPRC_CMDID_DESTROY_CONT 0x152
#define DPRC_CMDID_GET_CONT_ID 0x830
#define DPRC_CMDID_GET_OBJ_COUNT 0x159
#define DPRC_CMDID_GET_OBJ 0x15A
#define DPRC_CMD_OPEN(cmd, container_id) \
MC_CMD_OP(cmd, 0, 0, 32, int, container_id)
+/* cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_CREATE_CONTAINER(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \
+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->options); \
+ MC_CMD_OP(cmd, 1, 32, 32, int, cfg->portal_id); \
+ MC_CMD_OP(cmd, 2, 0, 8, char, cfg->label[0]);\
+ MC_CMD_OP(cmd, 2, 8, 8, char, cfg->label[1]);\
+ MC_CMD_OP(cmd, 2, 16, 8, char, cfg->label[2]);\
+ MC_CMD_OP(cmd, 2, 24, 8, char, cfg->label[3]);\
+ MC_CMD_OP(cmd, 2, 32, 8, char, cfg->label[4]);\
+ MC_CMD_OP(cmd, 2, 40, 8, char, cfg->label[5]);\
+ MC_CMD_OP(cmd, 2, 48, 8, char, cfg->label[6]);\
+ MC_CMD_OP(cmd, 2, 56, 8, char, cfg->label[7]);\
+ MC_CMD_OP(cmd, 3, 0, 8, char, cfg->label[8]);\
+ MC_CMD_OP(cmd, 3, 8, 8, char, cfg->label[9]);\
+ MC_CMD_OP(cmd, 3, 16, 8, char, cfg->label[10]);\
+ MC_CMD_OP(cmd, 3, 24, 8, char, cfg->label[11]);\
+ MC_CMD_OP(cmd, 3, 32, 8, char, cfg->label[12]);\
+ MC_CMD_OP(cmd, 3, 40, 8, char, cfg->label[13]);\
+ MC_CMD_OP(cmd, 3, 48, 8, char, cfg->label[14]);\
+ MC_CMD_OP(cmd, 3, 56, 8, char, cfg->label[15]);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_CREATE_CONTAINER(cmd, child_container_id, child_portal_offset)\
+do { \
+ MC_RSP_OP(cmd, 1, 0, 32, int, child_container_id); \
+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, child_portal_offset);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \
+ MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id)
+
/* cmd, param, offset, width, type, arg_name */
#define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \
MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id)
char label[16];
};
+/**
+ * dprc_create_container() - Create child container
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPRC object
+ * @cfg: Child container configuration
+ * @child_container_id: Returned child container ID
+ * @child_portal_offset: Returned child portal offset from MC portal base
+ *
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dprc_create_container(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dprc_cfg *cfg,
+ int *child_container_id,
+ uint64_t *child_portal_offset);
+
+/**
+ * dprc_destroy_container() - Destroy child container.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPRC object
+ * @child_container_id: ID of the container to destroy
+ *
+ * This function terminates the child container, so following this call the
+ * child container ID becomes invalid.
+ *
+ * Notes:
+ * - All resources and objects of the destroyed container are returned to the
+ * parent container or destroyed if were created be the destroyed container.
+ * - This function destroy all the child containers of the specified
+ * container prior to destroying the container itself.
+ *
+ * warning: Only the parent container is allowed to destroy a child policy
+ * Container 0 can't be destroyed
+ *
+ * Return: '0' on Success; Error code otherwise.
+ *
+ */
+int dprc_destroy_container(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int child_container_id);
+
/**
* dprc_reset_container - Reset child container.
* @mc_io: Pointer to MC portal's I/O object
((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
(_portal_id) * SOC_MC_PORTAL_STRIDE))
+#define MC_PORTAL_OFFSET_TO_PORTAL_ID(_portal_offset) \
+ ((_portal_offset) / SOC_MC_PORTAL_STRIDE)
+
struct mc_ccsr_registers {
u32 reg_gcr1;
u32 reserved1;
};
int get_mc_boot_status(void);
+int get_dpl_apply_status(void);
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+int get_aiop_apply_status(void);
+#endif
+u64 mc_get_dram_addr(void);
unsigned long mc_get_dram_block_size(void);
int fsl_mc_ldpaa_init(bd_t *bis);
-void fsl_mc_ldpaa_exit(bd_t *bis);
+int fsl_mc_ldpaa_exit(bd_t *bd);
#endif
#include <linux/compat.h>
#include <linux/types.h>
#include <linux/stringify.h>
+#include <phy.h>
#include <fsl-mc/fsl_mc_sys.h>
#include <fsl-mc/fsl_mc_cmd.h>
#include <fsl-mc/fsl_dprc.h>
#include <fsl-mc/fsl_dpbp.h>
+#include <fsl-mc/fsl_dpni.h>
extern struct fsl_mc_io *dflt_mc_io;
/**
* struct dpbp_node - DPBP strucuture
* @uint16_t handle: DPBP object handle
- * @int dpbp_id: DPBP id
+ * @struct dpbp_attr: DPBP attribute
*/
struct fsl_dpbp_obj {
uint16_t dpbp_handle;
*/
struct fsl_dpio_obj {
int dpio_id;
+ uint16_t dpio_handle;
struct qbman_swp *sw_portal; /** SW portal object */
};
extern struct fsl_dpio_obj *dflt_dpio;
-int mc_init(void);
-int ldpaa_eth_init(struct dprc_obj_desc obj_desc);
+/**
+ * struct dpni_node - DPNI strucuture
+ * @int dpni_id: DPNI id
+ * @uint16_t handle: DPNI object handle
+ * @struct dpni_attr: DPNI attributes
+ * @struct dpni_buffer_layout: DPNI buffer layout
+ */
+struct fsl_dpni_obj {
+ int dpni_id;
+ uint16_t dpni_handle;
+ struct dpni_attr dpni_attrs;
+ struct dpni_buffer_layout buf_layout;
+};
+
+extern struct fsl_dpni_obj *dflt_dpni;
+
+int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr);
+int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if);
+int mc_apply_dpl(u64 mc_dpl_addr);
#endif /* _FSL_MC_PRIVATE_H_ */
struct wriop_dpmac_info {
u8 enabled;
u8 id;
- u8 phy_addr;
u8 board_mux;
+ int phy_addr;
void *phy_regs;
phy_interface_t enet_if;
struct phy_device *phydev;
void wriop_init_dpmac(int, int, int);
void wriop_disable_dpmac(int);
void wriop_enable_dpmac(int);
+u8 wriop_is_enabled_dpmac(int dpmac_id);
void wriop_set_mdio(int, struct mii_dev *);
struct mii_dev *wriop_get_mdio(int);
void wriop_set_phy_address(int, int);
/* processor specific function */
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num, int step);
+void remove_unused_controllers(fsl_ddr_info_t *info);
/* board specific function */
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
struct udevice **devp);
/**
- * i2c_get_chip() - get a device to use to access a chip on a bus number
+ * i2c_get_chip_for_busnum() - get a device to use to access a chip on
+ * a bus number
*
* This returns the device for the given chip address on a particular bus
* number.
#if defined(CONFIG_LS102XA)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
-#elif defined(CONFIG_LS2085A)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+#elif defined(CONFIG_LS1043A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
#endif
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
- CONFIG_SYS_FSL_XHCI_USB2_ADDR}
+ CONFIG_SYS_FSL_XHCI_USB2_ADDR, \
+ CONFIG_SYS_FSL_XHCI_USB3_ADDR}
#endif /* _ASM_ARCH_XHCI_FSL_H_ */
* @return - '0' on success, otherwise error
*/
int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf);
+
+/**
+ * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header
+ * and partition table entries (PTE)
+ *
+ * As a side effect if sets gpt_head and gpt_pte so they point to GPT data.
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_head - pointer to GPT header data read from medium
+ * @param gpt_pte - pointer to GPT partition table enties read from medium
+ *
+ * @return - '0' on success, otherwise error
+ */
+int gpt_verify_headers(block_dev_desc_t *dev_desc, gpt_header *gpt_head,
+ gpt_entry **gpt_pte);
+
+/**
+ * gpt_verify_partitions() - Function to check if partitions' name, start and
+ * size correspond to '$partitions' env variable
+ *
+ * This function checks if on medium stored GPT data is in sync with information
+ * provided in '$partitions' environment variable. Specificially, name, start
+ * and size of the partition is checked.
+ *
+ * @param dev_desc - block device descriptor
+ * @param partitions - partition data read from '$partitions' env variable
+ * @param parts - number of partitions read from '$partitions' env variable
+ * @param gpt_head - pointer to GPT header data read from medium
+ * @param gpt_pte - pointer to GPT partition table enties read from medium
+ *
+ * @return - '0' on success, otherwise error
+ */
+int gpt_verify_partitions(block_dev_desc_t *dev_desc,
+ disk_partition_t *partitions, int parts,
+ gpt_header *gpt_head, gpt_entry **gpt_pte);
#endif
#endif /* _PART_H */
/*
* Structure of a PCI controller (host bridge)
+ *
+ * With driver model this is dev_get_uclass_priv(bus)
*/
struct pci_controller {
#ifdef CONFIG_DM_PCI
pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
/* For driver model these are defined in macros in pci_compat.c */
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
extern int pci_hose_read_config_byte(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word(struct pci_controller *hose,
pci_dev_t dev, int where, u16 val);
extern int pci_hose_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u32 val);
+#endif
#ifndef CONFIG_DM_PCI
extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
#endif
+void pciauto_region_init(struct pci_region *res);
+void pciauto_region_align(struct pci_region *res, pci_size_t size);
+void pciauto_config_init(struct pci_controller *hose);
+int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
+ pci_addr_t *bar);
+
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
extern int pci_hose_scan(struct pci_controller *hose);
extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
-extern void pciauto_region_init(struct pci_region* res);
-extern void pciauto_region_align(struct pci_region *res, pci_size_t size);
-extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar);
extern void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
pci_dev_t dev, int sub_bus);
extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus);
-extern void pciauto_config_init(struct pci_controller *hose);
extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
unsigned short device,
unsigned short class);
#endif
+#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
const char * pci_class_str(u8 class);
int pci_last_busno(void);
extern void pci_mpc85xx_init (struct pci_controller *hose);
#endif
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
/**
* pci_write_bar32() - Write the address of a BAR including control bits
*
*/
pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
struct pci_device_id *ids, int *indexp);
+#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
/* Access sizes for PCI reads and writes */
enum pci_size_t {
*/
int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
+#ifdef CONFIG_DM_PCI_COMPAT
/* Compatibility with old naming */
static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
u32 value)
return pci_read_config8(pcidev, offset, valuep);
}
+#endif /* CONFIG_DM_PCI_COMPAT */
+
+/**
+ * dm_pciauto_config_device() - configure a device ready for use
+ *
+ * Space is allocated for each PCI base address register (BAR) so that the
+ * devices are mapped into memory and I/O space ready for use.
+ *
+ * @dev: Device to configure
+ * @return 0 if OK, -ve on error
+ */
+int dm_pciauto_config_device(struct udevice *dev);
+
+/**
+ * pci_conv_32_to_size() - convert a 32-bit read value to the given size
+ *
+ * Some PCI buses must always perform 32-bit reads. The data must then be
+ * shifted and masked to reflect the required access size and offset. This
+ * function performs this transformation.
+ *
+ * @value: Value to transform (32-bit value read from @offset & ~3)
+ * @offset: Register offset that was read
+ * @size: Required size of the result
+ * @return the value that would have been obtained if the read had been
+ * performed at the given offset with the correct size
+ */
+ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
+
+/**
+ * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
+ *
+ * Some PCI buses must always perform 32-bit writes. To emulate a smaller
+ * write the old 32-bit data must be read, updated with the required new data
+ * and written back as a 32-bit value. This function performs the
+ * transformation from the old value to the new value.
+ *
+ * @value: Value to transform (32-bit value read from @offset & ~3)
+ * @offset: Register offset that should be written
+ * @size: Required size of the write
+ * @return the value that should be written as a 32-bit access to @offset & ~3.
+ */
+ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
+ enum pci_size_t size);
+
+/**
+ * pci_get_controller() - obtain the controller to use for a bus
+ *
+ * @dev: Device to check
+ * @return pointer to the controller device for this bus
+ */
+struct udevice *pci_get_controller(struct udevice *dev);
+
+/**
+ * pci_get_regions() - obtain pointers to all the region types
+ *
+ * @dev: Device to check
+ * @iop: Returns a pointer to the I/O region, or NULL if none
+ * @memp: Returns a pointer to the memory region, or NULL if none
+ * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
+ * @return the number of non-NULL regions returned, normally 3
+ */
+int pci_get_regions(struct udevice *dev, struct pci_region **iop,
+ struct pci_region **memp, struct pci_region **prefp);
+
/**
* struct dm_pci_emul_ops - PCI device emulator operations
*/
#ifndef _TIMER_H_
#define _TIMER_H_
+/*
+ * timer_conv_64 - convert 32-bit counter value to 64-bit
+ *
+ * @count: 32-bit counter value
+ * @return: 64-bit counter value
+ */
+u64 timer_conv_64(u32 count);
+
/*
* Get the current timer count
*
- * @dev: The Timer device
+ * @dev: The timer device
* @count: pointer that returns the current timer count
* @return: 0 if OK, -ve on error
*/
-int timer_get_count(struct udevice *dev, unsigned long *count);
+int timer_get_count(struct udevice *dev, u64 *count);
+
/*
* Get the timer input clock frequency
*
- * @dev: The Timer device
+ * @dev: The timer device
* @return: the timer input clock frequency
*/
unsigned long timer_get_rate(struct udevice *dev);
/*
- * struct timer_ops - Driver model Timer operations
+ * struct timer_ops - Driver model timer operations
*
- * The uclass interface is implemented by all Timer devices which use
+ * The uclass interface is implemented by all timer devices which use
* driver model.
*/
struct timer_ops {
/*
* Get the current timer count
*
- * @dev: The Timer device
- * @count: pointer that returns the current timer count
+ * @dev: The timer device
+ * @count: pointer that returns the current 64-bit timer count
* @return: 0 if OK, -ve on error
*/
- int (*get_count)(struct udevice *dev, unsigned long *count);
+ int (*get_count)(struct udevice *dev, u64 *count);
};
/*
Thumb-2, about 420 bytes). Enable this option for safety when
using sprintf() with data you do not control.
+config USE_TINY_PRINTF
+ bool "Enable tiny printf() version"
+ help
+ This option enables a tiny, stripped down printf version.
+ This should only be used in space limited environments,
+ like SPL versions with hard memory limits. This version
+ reduces the code size by about 2.5KiB on armv7.
+
+ The supported format specifiers are %c, %s, %u/%d and %x.
+
config REGEX
bool "Enable regular expression support"
default y if NET
obj-y += time.o
obj-$(CONFIG_TRACE) += trace.o
obj-$(CONFIG_LIB_UUID) += uuid.o
-obj-y += vsprintf.o
obj-$(CONFIG_LIB_RAND) += rand.o
+ifdef CONFIG_SPL_BUILD
+# SPL U-Boot may use full-printf, tiny-printf or none at all
+ifdef CONFIG_USE_TINY_PRINTF
+obj-$(CONFIG_SPL_SERIAL_SUPPORT) += tiny-printf.o
+else
+obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o
+endif
+else
+# Main U-Boot always uses the full printf support
+obj-y += vsprintf.o
+endif
+
subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
- COMPAT(NVIDIA_TEGRA124_PCIE, "nvidia,tegra124-pcie"),
- COMPAT(NVIDIA_TEGRA210_PCIE, "nvidia,tegra210-pcie"),
- COMPAT(NVIDIA_TEGRA30_PCIE, "nvidia,tegra30-pcie"),
- COMPAT(NVIDIA_TEGRA20_PCIE, "nvidia,tegra20-pcie"),
COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
COMPAT(SMSC_LAN9215, "smsc,lan9215"),
return timer_get_rate(gd->timer);
}
-unsigned long notrace timer_read_counter(void)
+uint64_t notrace get_ticks(void)
{
- unsigned long count;
+ u64 count;
int ret;
ret = dm_timer_init();
return count;
}
-#endif /* CONFIG_TIMER */
+
+#else /* !CONFIG_TIMER */
uint64_t __weak notrace get_ticks(void)
{
return ((uint64_t)gd->timebase_h << 32) | gd->timebase_l;
}
+#endif /* CONFIG_TIMER */
+
/* Returns time in milliseconds */
static uint64_t notrace tick_to_time(uint64_t tick)
{
--- /dev/null
+/*
+ * Tiny printf version for SPL
+ *
+ * Copied from:
+ * http://www.sparetimelabs.com/printfrevisited/printfrevisited.php
+ *
+ * Copyright (C) 2004,2008 Kustaa Nyholm
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#include <common.h>
+#include <stdarg.h>
+#include <serial.h>
+
+static char *bf;
+static char zs;
+
+static void out(char c)
+{
+ *bf++ = c;
+}
+
+static void out_dgt(char dgt)
+{
+ out(dgt + (dgt < 10 ? '0' : 'a' - 10));
+ zs = 1;
+}
+
+static void div_out(unsigned int *num, unsigned int div)
+{
+ unsigned char dgt = 0;
+
+ while (*num >= div) {
+ *num -= div;
+ dgt++;
+ }
+
+ if (zs || dgt > 0)
+ out_dgt(dgt);
+}
+
+int printf(const char *fmt, ...)
+{
+ va_list va;
+ char ch;
+ char *p;
+ unsigned int num;
+ char buf[12];
+ unsigned int div;
+
+ va_start(va, fmt);
+
+ while ((ch = *(fmt++))) {
+ if (ch != '%') {
+ putc(ch);
+ } else {
+ char lz = 0;
+ char w = 0;
+
+ ch = *(fmt++);
+ if (ch == '0') {
+ ch = *(fmt++);
+ lz = 1;
+ }
+
+ if (ch >= '0' && ch <= '9') {
+ w = 0;
+ while (ch >= '0' && ch <= '9') {
+ w = (w * 10) + ch - '0';
+ ch = *fmt++;
+ }
+ }
+ bf = buf;
+ p = bf;
+ zs = 0;
+
+ switch (ch) {
+ case 0:
+ goto abort;
+ case 'u':
+ case 'd':
+ num = va_arg(va, unsigned int);
+ if (ch == 'd' && (int)num < 0) {
+ num = -(int)num;
+ out('-');
+ }
+ for (div = 1000000000; div; div /= 10)
+ div_out(&num, div);
+ break;
+ case 'x':
+ num = va_arg(va, unsigned int);
+ for (div = 0x10000000; div; div /= 0x10)
+ div_out(&num, div);
+ break;
+ case 'c':
+ out((char)(va_arg(va, int)));
+ break;
+ case 's':
+ p = va_arg(va, char*);
+ break;
+ case '%':
+ out('%');
+ default:
+ break;
+ }
+
+ *bf = 0;
+ bf = p;
+ while (*bf++ && w > 0)
+ w--;
+ while (w-- > 0)
+ putc(lz ? '0' : ' ');
+ while ((ch = *p++))
+ putc(ch);
+ }
+ }
+
+abort:
+ va_end(va);
+ return 0;
+}
return i;
}
+int printf(const char *fmt, ...)
+{
+ va_list args;
+ uint i;
+ char printbuffer[CONFIG_SYS_PBSIZE];
+
+ va_start(args, fmt);
+
+ /*
+ * For this to work, printbuffer must be larger than
+ * anything we ever want to print.
+ */
+ i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
+ va_end(args);
+
+ /* Print the string */
+ puts(printbuffer);
+ return i;
+}
+
+int vprintf(const char *fmt, va_list args)
+{
+ uint i;
+ char printbuffer[CONFIG_SYS_PBSIZE];
+
+ /*
+ * For this to work, printbuffer must be larger than
+ * anything we ever want to print.
+ */
+ i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
+
+ /* Print the string */
+ puts(printbuffer);
+ return i;
+}
+
static void panic_finish(void) __attribute__ ((noreturn));
static void panic_finish(void)
rsa-sign.o rsa-verify.o rsa-checksum.o \
rsa-mod-exp.o)
-ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o
+ROCKCHIP_OBS = $(if $(CONFIG_ARCH_ROCKCHIP),lib/rc4.o rkcommon.o rkimage.o rksd.o,)
# common objs for dumpimage and mkimage
dumpimage-mkimage-objs := aisimage.o \
# TODO(sjg@chromium.org): Is this correct on Mac OS?
+ifneq ($(CONFIG_ARCH_ROCKCHIP),)
+HOST_EXTRACFLAGS += \
+ -DCONFIG_ROCKCHIP_MAX_SPL_SIZE=$(CONFIG_ROCKCHIP_MAX_SPL_SIZE) \
+ -DCONFIG_ROCKCHIP_SPL_HDR="\"$(CONFIG_ROCKCHIP_SPL_HDR)\""
+endif
+
ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
# the mxsimage support within tools/mxsimage.c .
main_hdr = image;
/* Fill in the main header */
- main_hdr->blocksize = payloadsz + sizeof(uint32_t) - headersz;
- main_hdr->srcaddr = headersz;
+ main_hdr->blocksize =
+ cpu_to_le32(payloadsz + sizeof(uint32_t) - headersz);
+ main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = has_ext;
- main_hdr->destaddr = params->addr;
- main_hdr->execaddr = params->ep;
+ main_hdr->destaddr = cpu_to_le32(params->addr);
+ main_hdr->execaddr = cpu_to_le32(params->ep);
e = image_find_option(IMAGE_CFG_BOOT_FROM);
if (e)
main_hdr->nandeccmode = e->nandeccmode;
e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
if (e)
- main_hdr->nandpagesize = e->nandpagesz;
+ main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
main_hdr->checksum = image_checksum8(image,
sizeof(struct main_hdr_v0));
int cfgi, datai;
ext_hdr = image + sizeof(struct main_hdr_v0);
- ext_hdr->offset = 0x40;
+ ext_hdr->offset = cpu_to_le32(0x40);
for (cfgi = 0, datai = 0; cfgi < cfgn; cfgi++) {
e = &image_cfg[cfgi];
if (e->type != IMAGE_CFG_DATA)
continue;
- ext_hdr->rcfg[datai].raddr = e->regdata.raddr;
- ext_hdr->rcfg[datai].rdata = e->regdata.rdata;
+ ext_hdr->rcfg[datai].raddr =
+ cpu_to_le32(e->regdata.raddr);
+ ext_hdr->rcfg[datai].rdata =
+ cpu_to_le32(e->regdata.rdata);
datai++;
}
return 0;
}
- headersz += s.st_size +
- binarye->binary.nargs * sizeof(unsigned int);
+ headersz += sizeof(struct opt_hdr_v1) +
+ s.st_size +
+ (binarye->binary.nargs + 2) * sizeof(uint32_t);
if (hasext)
*hasext = 1;
}
cur += sizeof(struct main_hdr_v1);
/* Fill the main header */
- main_hdr->blocksize = payloadsz - headersz + sizeof(uint32_t);
- main_hdr->headersz_lsb = headersz & 0xFFFF;
+ main_hdr->blocksize =
+ cpu_to_le32(payloadsz - headersz + sizeof(uint32_t));
+ main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
- main_hdr->destaddr = params->addr;
- main_hdr->execaddr = params->ep;
- main_hdr->srcaddr = headersz;
+ main_hdr->destaddr = cpu_to_le32(params->addr);
+ main_hdr->execaddr = cpu_to_le32(params->ep);
+ main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = hasext;
main_hdr->version = 1;
e = image_find_option(IMAGE_CFG_BOOT_FROM);
binarye = image_find_option(IMAGE_CFG_BINARY);
if (binarye) {
struct opt_hdr_v1 *hdr = cur;
- unsigned int *args;
+ uint32_t *args;
size_t binhdrsz;
struct stat s;
int argi;
fstat(fileno(bin), &s);
binhdrsz = sizeof(struct opt_hdr_v1) +
- (binarye->binary.nargs + 1) * sizeof(unsigned int) +
+ (binarye->binary.nargs + 2) * sizeof(uint32_t) +
s.st_size;
/*
* next-header byte and 3-byte alignment at the end.
*/
binhdrsz = ALIGN_SUP(binhdrsz, 4) + 4;
- hdr->headersz_lsb = binhdrsz & 0xFFFF;
+ hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF);
hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
cur += sizeof(struct opt_hdr_v1);
args = cur;
- *args = binarye->binary.nargs;
+ *args = cpu_to_le32(binarye->binary.nargs);
args++;
for (argi = 0; argi < binarye->binary.nargs; argi++)
- args[argi] = binarye->binary.args[argi];
+ args[argi] = cpu_to_le32(binarye->binary.args[argi]);
- cur += (binarye->binary.nargs + 1) * sizeof(unsigned int);
+ cur += (binarye->binary.nargs + 1) * sizeof(uint32_t);
ret = fread(cur, s.st_size, 1, bin);
if (ret != 1) {
free(image_cfg);
/* Build and add image checksum header */
- checksum = image_checksum32((uint32_t *)ptr, sbuf->st_size);
+ checksum =
+ cpu_to_le32(image_checksum32((uint32_t *)ptr, sbuf->st_size));
size = write(ifd, &checksum, sizeof(uint32_t));
if (size != sizeof(uint32_t)) {
fprintf(stderr, "Error:%s - Checksum write %d bytes %s\n",
tparams->header_size = alloc_len;
tparams->hdr = hdr;
- return 0;
+ /*
+ * The resulting image needs to be 4-byte aligned. At least
+ * the Marvell hdrparser tool complains if its unaligned.
+ * By returning 1 here in this function, called via
+ * tparams->vrec_header() in mkimage.c, mkimage will
+ * automatically pad the the resulting image to a 4-byte
+ * size if necessary.
+ */
+ return 1;
}
/*
#ifndef _KWBIMAGE_H_
#define _KWBIMAGE_H_
+#include <compiler.h>
#include <stdint.h>
#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
#define OPT_HDR_V1_REGISTER_TYPE 0x3
#define KWBHEADER_V1_SIZE(hdr) \
- (((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb)
+ (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
enum kwbimage_cmd {
CMD_INVALID,
*
* @signature: Signature (must be RKSD_SIGNATURE)
* @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary
- * @code1_offset: Offset in blocks of the SPL code from this header
+ * @init_offset: Offset in blocks of the SPL code from this header
* block. E.g. 4 means 2KB after the start of this header.
* Other fields are not used by U-Boot
*/
uint32_t signature;
uint8_t reserved[4];
uint32_t disable_rc4;
- uint16_t code1_offset;
- uint16_t code2_offset;
- uint8_t reserved1[490];
- uint16_t usflashdatasize;
- uint16_t ucflashbootsize;
+ uint16_t init_offset;
+ uint8_t reserved1[492];
+ uint16_t init_size;
+ uint16_t init_boot_size;
uint8_t reserved2[2];
};
{
struct header0_info *hdr;
- if (file_size > RK_MAX_CODE1_SIZE)
+ if (file_size > CONFIG_ROCKCHIP_MAX_SPL_SIZE)
return -ENOSPC;
- memset(buf, '\0', RK_CODE1_OFFSET * RK_BLK_SIZE);
+ memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
hdr = (struct header0_info *)buf;
hdr->signature = RK_SIGNATURE;
hdr->disable_rc4 = 1;
- hdr->code1_offset = RK_CODE1_OFFSET;
- hdr->code2_offset = 8;
+ hdr->init_offset = RK_INIT_OFFSET;
- hdr->usflashdatasize = (file_size + RK_BLK_SIZE - 1) / RK_BLK_SIZE;
- hdr->usflashdatasize = (hdr->usflashdatasize + 3) & ~3;
- hdr->ucflashbootsize = hdr->usflashdatasize;
-
- debug("size=%x, %x\n", params->file_size, hdr->usflashdatasize);
+ hdr->init_size = (file_size + RK_BLK_SIZE - 1) / RK_BLK_SIZE;
+ hdr->init_size = (hdr->init_size + 3) & ~3;
+ hdr->init_boot_size = hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE;
rc4_encode(buf, RK_BLK_SIZE, rc4_key);
enum {
RK_BLK_SIZE = 512,
- RK_CODE1_OFFSET = 4,
- RK_MAX_CODE1_SIZE = 32 << 10,
+ RK_INIT_OFFSET = 4,
+ RK_MAX_BOOT_SIZE = 512 << 10,
};
/**
static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
- memcpy(buf, "RK32", 4);
+ memcpy(buf, CONFIG_ROCKCHIP_SPL_HDR, 4);
}
static int rkimage_extract_subimage(void *buf, struct image_tool_params *params)
#include "rkcommon.h"
enum {
- RKSD_SPL_HDR_START = RK_CODE1_OFFSET * RK_BLK_SIZE,
+ RKSD_SPL_HDR_START = RK_INIT_OFFSET * RK_BLK_SIZE,
RKSD_SPL_START = RKSD_SPL_HDR_START + 4,
RKSD_HEADER_LEN = RKSD_SPL_START,
};
size);
}
- memcpy(buf + RKSD_SPL_HDR_START, "RK32", 4);
+ memcpy(buf + RKSD_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4);
}
static int rksd_extract_subimage(void *buf, struct image_tool_params *params)
{
int pad_size;
- pad_size = RKSD_SPL_HDR_START + RK_MAX_CODE1_SIZE;
+ pad_size = RKSD_SPL_HDR_START + CONFIG_ROCKCHIP_MAX_SPL_SIZE;
debug("pad_size %x\n", pad_size);
return pad_size - params->file_size;
#include "rkcommon.h"
enum {
- RKSPI_SPL_HDR_START = RK_CODE1_OFFSET * RK_BLK_SIZE,
+ RKSPI_SPL_HDR_START = RK_INIT_OFFSET * RK_BLK_SIZE,
RKSPI_SPL_START = RKSPI_SPL_HDR_START + 4,
RKSPI_HEADER_LEN = RKSPI_SPL_START,
RKSPI_SECT_LEN = RK_BLK_SIZE * 4,
size);
}
- memcpy(buf + RKSPI_SPL_HDR_START, "RK32", 4);
+ memcpy(buf + RKSPI_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4);
/*
* Spread the image out so we only use the first 2KB of each 4KB
{
int pad_size;
- pad_size = (RK_MAX_CODE1_SIZE + 0x7ff) / 0x800 * 0x800;
+ pad_size = (CONFIG_ROCKCHIP_MAX_SPL_SIZE + 0x7ff) / 0x800 * 0x800;
params->orig_file_size = pad_size;
/* We will double the image size due to the SPI format */
projects / oweals / u-boot.git / commitdiff