4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/omap.h>
19 #include <asm/arch/ddr_defs.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mem.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sys_proto.h>
31 #include <asm/errno.h>
32 #include <linux/compiler.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/musb.h>
36 #include <asm/omap_musb.h>
37 #include <asm/davinci_rtc.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 #if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_OF_CONTROL)
43 * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
44 * the CONFIGs. At the same time, we should move this to the board files.
46 static const struct ns16550_platdata am33xx_serial[] = {
47 { CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
48 # ifdef CONFIG_SYS_NS16550_COM2
49 { CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
50 # ifdef CONFIG_SYS_NS16550_COM3
51 { CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
52 { CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
53 { CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
54 { CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
59 U_BOOT_DEVICES(am33xx_uarts) = {
60 { "serial_omap", &am33xx_serial[0] },
61 # ifdef CONFIG_SYS_NS16550_COM2
62 { "serial_omap", &am33xx_serial[1] },
63 # ifdef CONFIG_SYS_NS16550_COM3
64 { "serial_omap", &am33xx_serial[2] },
65 { "serial_omap", &am33xx_serial[3] },
66 { "serial_omap", &am33xx_serial[4] },
67 { "serial_omap", &am33xx_serial[5] },
74 #ifndef CONFIG_DM_GPIO
75 static const struct gpio_bank gpio_bank_am33xx[] = {
76 { (void *)AM33XX_GPIO0_BASE },
77 { (void *)AM33XX_GPIO1_BASE },
78 { (void *)AM33XX_GPIO2_BASE },
79 { (void *)AM33XX_GPIO3_BASE },
81 { (void *)AM33XX_GPIO4_BASE },
82 { (void *)AM33XX_GPIO5_BASE },
86 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
89 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
90 int cpu_mmc_init(bd_t *bis)
94 ret = omap_mmc_init(0, 0, 0, -1, -1);
98 return omap_mmc_init(1, 0, 0, -1, -1);
102 /* AM33XX has two MUSB controllers which can be host or gadget */
103 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
104 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
105 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
107 /* USB 2.0 PHY Control */
108 #define CM_PHY_PWRDN (1 << 0)
109 #define CM_PHY_OTG_PWRDN (1 << 1)
110 #define OTGVDET_EN (1 << 19)
111 #define OTGSESSENDEN (1 << 20)
113 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
116 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
117 OTGVDET_EN | OTGSESSENDEN);
119 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
123 static struct musb_hdrc_config musb_config = {
130 #ifdef CONFIG_AM335X_USB0
131 static void am33xx_otg0_set_phy_power(u8 on)
133 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
136 struct omap_musb_board_data otg0_board_data = {
137 .set_phy_power = am33xx_otg0_set_phy_power,
140 static struct musb_hdrc_platform_data otg0_plat = {
141 .mode = CONFIG_AM335X_USB0_MODE,
142 .config = &musb_config,
144 .platform_ops = &musb_dsps_ops,
145 .board_data = &otg0_board_data,
149 #ifdef CONFIG_AM335X_USB1
150 static void am33xx_otg1_set_phy_power(u8 on)
152 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
155 struct omap_musb_board_data otg1_board_data = {
156 .set_phy_power = am33xx_otg1_set_phy_power,
159 static struct musb_hdrc_platform_data otg1_plat = {
160 .mode = CONFIG_AM335X_USB1_MODE,
161 .config = &musb_config,
163 .platform_ops = &musb_dsps_ops,
164 .board_data = &otg1_board_data,
169 int arch_misc_init(void)
171 #ifdef CONFIG_AM335X_USB0
172 musb_register(&otg0_plat, &otg0_board_data,
173 (void *)USB0_OTG_BASE);
175 #ifdef CONFIG_AM335X_USB1
176 musb_register(&otg1_plat, &otg1_board_data,
177 (void *)USB1_OTG_BASE);
182 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
184 * In the case of non-SPL based booting we'll want to call these
185 * functions a tiny bit later as it will require gd to be set and cleared
186 * and that's not true in s_init in this case so we cannot do it there.
188 int board_early_init_f(void)
197 * This function is the place to do per-board things such as ramp up the
198 * MPU clock frequency.
200 __weak void am33xx_spl_board_init(void)
202 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
203 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
206 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
207 static void rtc32k_enable(void)
209 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
212 * Unlock the RTC's registers. For more details please see the
213 * RTC_SS section of the TRM. In order to unlock we need to
214 * write these specific values (keys) in this order.
216 writel(RTC_KICK0R_WE, &rtc->kick0r);
217 writel(RTC_KICK1R_WE, &rtc->kick1r);
219 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
220 writel((1 << 3) | (1 << 6), &rtc->osc);
224 static void uart_soft_reset(void)
226 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
229 regval = readl(&uart_base->uartsyscfg);
230 regval |= UART_RESET;
231 writel(regval, &uart_base->uartsyscfg);
232 while ((readl(&uart_base->uartsyssts) &
233 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
236 /* Disable smart idle */
237 regval = readl(&uart_base->uartsyscfg);
238 regval |= UART_SMART_IDLE_EN;
239 writel(regval, &uart_base->uartsyscfg);
242 static void watchdog_disable(void)
244 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
246 writel(0xAAAA, &wdtimer->wdtwspr);
247 while (readl(&wdtimer->wdtwwps) != 0x0)
249 writel(0x5555, &wdtimer->wdtwspr);
250 while (readl(&wdtimer->wdtwwps) != 0x0)
254 #ifdef CONFIG_SPL_BUILD
255 void board_init_f(ulong dummy)
257 board_early_init_f();
265 * The ROM will only have set up sufficient pinmux to allow for the
266 * first 4KiB NOR to be read, we must finish doing what we know of
267 * the NOR mux in this space in order to continue.
269 #ifdef CONFIG_NOR_BOOT
270 enable_norboot_pin_mux();
274 setup_clocks_for_console();
276 #if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
277 /* TODO: This does not work, gd is not available yet */
278 gd->baudrate = CONFIG_BAUDRATE;
280 gd->have_console = 1;
282 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
283 /* Enable RTC32K clock */