drivers/pci/pci_auto_old.c

   1 /*
   2  * arch/powerpc/kernel/pci_auto.c
   3  *
   4  * PCI autoconfiguration library
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Copyright 2000 MontaVista Software Inc.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <errno.h>
  15 #include <pci.h>
  16
  17 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  18 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  19 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  20 #endif
  21
  22 /*
  23  *
  24  */
  25
  26 void pciauto_setup_device(struct pci_controller *hose,
  27                           pci_dev_t dev, int bars_num,
  28                           struct pci_region *mem,
  29                           struct pci_region *prefetch,
  30                           struct pci_region *io)
  31 {
  32         u32 bar_response;
  33         pci_size_t bar_size;
  34         u16 cmdstat = 0;
  35         int bar, bar_nr = 0;
  36 #ifndef CONFIG_PCI_ENUM_ONLY
  37         u8 header_type;
  38         int rom_addr;
  39         pci_addr_t bar_value;
  40         struct pci_region *bar_res;
  41         int found_mem64 = 0;
  42 #endif
  43         u16 class;
  44
  45         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  46         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
  47
  48         for (bar = PCI_BASE_ADDRESS_0;
  49                 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  50                 /* Tickle the BAR and get the response */
  51 #ifndef CONFIG_PCI_ENUM_ONLY
  52                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
  53 #endif
  54                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
  55
  56                 /* If BAR is not implemented go to the next BAR */
  57                 if (!bar_response)
  58                         continue;
  59
  60 #ifndef CONFIG_PCI_ENUM_ONLY
  61                 found_mem64 = 0;
  62 #endif
  63
  64                 /* Check the BAR type and set our address mask */
  65                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  66                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
  67                                    & 0xffff) + 1;
  68 #ifndef CONFIG_PCI_ENUM_ONLY
  69                         bar_res = io;
  70 #endif
  71
  72                         debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
  73                               bar_nr, (unsigned long long)bar_size);
  74                 } else {
  75                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  76                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
  77                                 u32 bar_response_upper;
  78                                 u64 bar64;
  79
  80 #ifndef CONFIG_PCI_ENUM_ONLY
  81                                 pci_hose_write_config_dword(hose, dev, bar + 4,
  82                                         0xffffffff);
  83 #endif
  84                                 pci_hose_read_config_dword(hose, dev, bar + 4,
  85                                         &bar_response_upper);
  86
  87                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
  88
  89                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
  90 #ifndef CONFIG_PCI_ENUM_ONLY
  91                                 found_mem64 = 1;
  92 #endif
  93                         } else {
  94                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
  95                         }
  96 #ifndef CONFIG_PCI_ENUM_ONLY
  97                         if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
  98                                 bar_res = prefetch;
  99                         else
 100                                 bar_res = mem;
 101 #endif
 102
 103                         debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
 104                               bar_nr, bar_res == prefetch ? "Prf" : "Mem",
 105                               (unsigned long long)bar_size);
 106                 }
 107
 108 #ifndef CONFIG_PCI_ENUM_ONLY
 109                 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
 110                         /* Write it out and update our limit */
 111                         pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
 112
 113                         if (found_mem64) {
 114                                 bar += 4;
 115 #ifdef CONFIG_SYS_PCI_64BIT
 116                                 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 117 #else
 118                                 /*
 119                                  * If we are a 64-bit decoder then increment to the
 120                                  * upper 32 bits of the bar and force it to locate
 121                                  * in the lower 4GB of memory.
 122                                  */
 123                                 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 124 #endif
 125                         }
 126
 127                 }
 128 #endif
 129                 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 130                         PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 131
 132                 debug("\n");
 133
 134                 bar_nr++;
 135         }
 136
 137 #ifndef CONFIG_PCI_ENUM_ONLY
 138         /* Configure the expansion ROM address */
 139         pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 140         header_type &= 0x7f;
 141         if (header_type != PCI_HEADER_TYPE_CARDBUS) {
 142                 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
 143                            PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
 144                 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
 145                 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
 146                 if (bar_response) {
 147                         bar_size = -(bar_response & ~1);
 148                         debug("PCI Autoconfig: ROM, size=%#x, ",
 149                               (unsigned int)bar_size);
 150                         if (pciauto_region_allocate(mem, bar_size,
 151                                                     &bar_value) == 0) {
 152                                 pci_hose_write_config_dword(hose, dev, rom_addr,
 153                                                             bar_value);
 154                         }
 155                         cmdstat |= PCI_COMMAND_MEMORY;
 156                         debug("\n");
 157                 }
 158         }
 159 #endif
 160
 161         /* PCI_COMMAND_IO must be set for VGA device */
 162         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 163         if (class == PCI_CLASS_DISPLAY_VGA)
 164                 cmdstat |= PCI_COMMAND_IO;
 165
 166         pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 167         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 168                 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 169         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 170 }
 171
 172 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 173                                          pci_dev_t dev, int sub_bus)
 174 {
 175         struct pci_region *pci_mem;
 176         struct pci_region *pci_prefetch;
 177         struct pci_region *pci_io;
 178         u16 cmdstat, prefechable_64;
 179
 180 #ifdef CONFIG_DM_PCI
 181         /* The root controller has the region information */
 182         struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
 183
 184         pci_mem = ctlr_hose->pci_mem;
 185         pci_prefetch = ctlr_hose->pci_prefetch;
 186         pci_io = ctlr_hose->pci_io;
 187 #else
 188         pci_mem = hose->pci_mem;
 189         pci_prefetch = hose->pci_prefetch;
 190         pci_io = hose->pci_io;
 191 #endif
 192
 193         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 194         pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 195                                 &prefechable_64);
 196         prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 197
 198         /* Configure bus number registers */
 199 #ifdef CONFIG_DM_PCI
 200         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
 201         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
 202 #else
 203         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
 204                                    PCI_BUS(dev) - hose->first_busno);
 205         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
 206                                    sub_bus - hose->first_busno);
 207 #endif
 208         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 209
 210         if (pci_mem) {
 211                 /* Round memory allocator to 1MB boundary */
 212                 pciauto_region_align(pci_mem, 0x100000);
 213
 214                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 215                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
 216                                         (pci_mem->bus_lower & 0xfff00000) >> 16);
 217
 218                 cmdstat |= PCI_COMMAND_MEMORY;
 219         }
 220
 221         if (pci_prefetch) {
 222                 /* Round memory allocator to 1MB boundary */
 223                 pciauto_region_align(pci_prefetch, 0x100000);
 224
 225                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 226                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 227                                         (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 228                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 229 #ifdef CONFIG_SYS_PCI_64BIT
 230                         pci_hose_write_config_dword(hose, dev,
 231                                         PCI_PREF_BASE_UPPER32,
 232                                         pci_prefetch->bus_lower >> 32);
 233 #else
 234                         pci_hose_write_config_dword(hose, dev,
 235                                         PCI_PREF_BASE_UPPER32,
 236                                         0x0);
 237 #endif
 238
 239                 cmdstat |= PCI_COMMAND_MEMORY;
 240         } else {
 241                 /* We don't support prefetchable memory for now, so disable */
 242                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
 243                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 244                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
 245                         pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
 246                         pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
 247                 }
 248         }
 249
 250         if (pci_io) {
 251                 /* Round I/O allocator to 4KB boundary */
 252                 pciauto_region_align(pci_io, 0x1000);
 253
 254                 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
 255                                         (pci_io->bus_lower & 0x0000f000) >> 8);
 256                 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
 257                                         (pci_io->bus_lower & 0xffff0000) >> 16);
 258
 259                 cmdstat |= PCI_COMMAND_IO;
 260         }
 261
 262         /* Enable memory and I/O accesses, enable bus master */
 263         pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 264                                         cmdstat | PCI_COMMAND_MASTER);
 265 }
 266
 267 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 268                                           pci_dev_t dev, int sub_bus)
 269 {
 270         struct pci_region *pci_mem;
 271         struct pci_region *pci_prefetch;
 272         struct pci_region *pci_io;
 273
 274 #ifdef CONFIG_DM_PCI
 275         /* The root controller has the region information */
 276         struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
 277
 278         pci_mem = ctlr_hose->pci_mem;
 279         pci_prefetch = ctlr_hose->pci_prefetch;
 280         pci_io = ctlr_hose->pci_io;
 281 #else
 282         pci_mem = hose->pci_mem;
 283         pci_prefetch = hose->pci_prefetch;
 284         pci_io = hose->pci_io;
 285 #endif
 286
 287         /* Configure bus number registers */
 288 #ifdef CONFIG_DM_PCI
 289         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
 290 #else
 291         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
 292                                    sub_bus - hose->first_busno);
 293 #endif
 294
 295         if (pci_mem) {
 296                 /* Round memory allocator to 1MB boundary */
 297                 pciauto_region_align(pci_mem, 0x100000);
 298
 299                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
 300                                 (pci_mem->bus_lower - 1) >> 16);
 301         }
 302
 303         if (pci_prefetch) {
 304                 u16 prefechable_64;
 305
 306                 pci_hose_read_config_word(hose, dev,
 307                                         PCI_PREF_MEMORY_LIMIT,
 308                                         &prefechable_64);
 309                 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 310
 311                 /* Round memory allocator to 1MB boundary */
 312                 pciauto_region_align(pci_prefetch, 0x100000);
 313
 314                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
 315                                 (pci_prefetch->bus_lower - 1) >> 16);
 316                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 317 #ifdef CONFIG_SYS_PCI_64BIT
 318                         pci_hose_write_config_dword(hose, dev,
 319                                         PCI_PREF_LIMIT_UPPER32,
 320                                         (pci_prefetch->bus_lower - 1) >> 32);
 321 #else
 322                         pci_hose_write_config_dword(hose, dev,
 323                                         PCI_PREF_LIMIT_UPPER32,
 324                                         0x0);
 325 #endif
 326         }
 327
 328         if (pci_io) {
 329                 /* Round I/O allocator to 4KB boundary */
 330                 pciauto_region_align(pci_io, 0x1000);
 331
 332                 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
 333                                 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
 334                 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
 335                                 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
 336         }
 337 }
 338
 339
 340 /*
 341  * HJF: Changed this to return int. I think this is required
 342  * to get the correct result when scanning bridges
 343  */
 344 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 345 {
 346         struct pci_region *pci_mem;
 347         struct pci_region *pci_prefetch;
 348         struct pci_region *pci_io;
 349         unsigned int sub_bus = PCI_BUS(dev);
 350         unsigned short class;
 351         int n;
 352
 353 #ifdef CONFIG_DM_PCI
 354         /* The root controller has the region information */
 355         struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
 356
 357         pci_mem = ctlr_hose->pci_mem;
 358         pci_prefetch = ctlr_hose->pci_prefetch;
 359         pci_io = ctlr_hose->pci_io;
 360 #else
 361         pci_mem = hose->pci_mem;
 362         pci_prefetch = hose->pci_prefetch;
 363         pci_io = hose->pci_io;
 364 #endif
 365
 366         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 367
 368         switch (class) {
 369         case PCI_CLASS_BRIDGE_PCI:
 370                 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
 371                       PCI_DEV(dev));
 372
 373                 pciauto_setup_device(hose, dev, 2, pci_mem,
 374                                      pci_prefetch, pci_io);
 375
 376 #ifdef CONFIG_DM_PCI
 377                 n = dm_pci_hose_probe_bus(hose, dev);
 378                 if (n < 0)
 379                         return n;
 380                 sub_bus = (unsigned int)n;
 381 #else
 382                 /* Passing in current_busno allows for sibling P2P bridges */
 383                 hose->current_busno++;
 384                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 385                 /*
 386                  * need to figure out if this is a subordinate bridge on the bus
 387                  * to be able to properly set the pri/sec/sub bridge registers.
 388                  */
 389                 n = pci_hose_scan_bus(hose, hose->current_busno);
 390
 391                 /* figure out the deepest we've gone for this leg */
 392                 sub_bus = max((unsigned int)n, sub_bus);
 393                 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 394
 395                 sub_bus = hose->current_busno;
 396 #endif
 397                 break;
 398
 399         case PCI_CLASS_BRIDGE_CARDBUS:
 400                 /*
 401                  * just do a minimal setup of the bridge,
 402                  * let the OS take care of the rest
 403                  */
 404                 pciauto_setup_device(hose, dev, 0, pci_mem,
 405                                      pci_prefetch, pci_io);
 406
 407                 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 408                       PCI_DEV(dev));
 409
 410 #ifndef CONFIG_DM_PCI
 411                 hose->current_busno++;
 412 #endif
 413                 break;
 414
 415 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 416         case PCI_CLASS_BRIDGE_OTHER:
 417                 debug("PCI Autoconfig: Skipping bridge device %d\n",
 418                       PCI_DEV(dev));
 419                 break;
 420 #endif
 421 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
 422         case PCI_CLASS_BRIDGE_OTHER:
 423                 /*
 424                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 425                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 426                  * device claiming resources io/mem/irq.. we only allow for
 427                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 428                  */
 429                 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
 430                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 431                         hose->pci_prefetch, hose->pci_io);
 432                 break;
 433 #endif
 434
 435         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 436                 debug("PCI AutoConfig: Found PowerPC device\n");
 437
 438         default:
 439                 pciauto_setup_device(hose, dev, 6, pci_mem,
 440                                      pci_prefetch, pci_io);
 441                 break;
 442         }
 443
 444         return sub_bus;
 445 }