verified boot (secure boot using RSA). This option enables that
feature.
+config SPL_FIT
+ bool "Support Flattened Image Tree within SPL"
+ depends on FIT
+ depends on SPL
+
config FIT_VERBOSE
bool "Display verbose messages on FIT boot"
depends on FIT
format support in this case, enable it using
CONFIG_IMAGE_FORMAT_LEGACY.
+config SPL_FIT_SIGNATURE
+ bool "Enable signature verification of FIT firmware within SPL"
+ depends on SPL_FIT
+ depends on SPL_DM
+ select SPL_RSA
+
config FIT_BEST_MATCH
bool "Select the best match for the kernel device tree"
depends on FIT
{
switch (imxtype) {
case MXC_CPU_MX23:
- return "23"; /* Quad-Plus version of the mx6 */
+ return "23";
case MXC_CPU_MX28:
- return "28"; /* Dual-Plus version of the mx6 */
+ return "28";
default:
return "??";
}
{
u32 mask, *addr;
- if (is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6ul()) {
mask = MXC_CCM_CCGR3_ENET_MASK;
addr = &imx_ccm->CCGR3;
} else {
{
u32 mask;
- if (is_cpu_type(MXC_CPU_MX6UL))
+ if (is_mx6ul())
mask = MXC_CCM_CCGR5_UART_MASK;
else
mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR2);
} else {
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6sx() || is_mx6ul()) {
mask = MXC_CCM_CCGR6_I2C4_MASK;
addr = &imx_ccm->CCGR6;
} else {
switch (pll) {
case PLL_BUS:
- if (!is_cpu_type(MXC_CPU_MX6UL)) {
+ if (!is_mx6ul()) {
if (pfd_num == 3) {
/* No PFD3 on PPL2 */
return 0;
u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1);
- if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
- is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6sl() || is_mx6sx() ||
+ is_mx6dqp() || is_mx6ul()) {
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */
}
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
- if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
- is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
}
cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
- if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
- is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
return MXC_HCLK / (cspi_podf + 1);
}
u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
- is_cpu_type(MXC_CPU_MX6SL)) {
+ if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
- if (is_cpu_type(MXC_CPU_MX6SL)) {
+ if (is_mx6sl()) {
if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
freq = MXC_HCLK;
else
debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
- if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) {
+ if (!is_mx6sx() && !is_mx6ul()) {
debug("This chip not support lcd!\n");
return;
}
return;
}
- if (is_cpu_type(MXC_CPU_MX6SX)) {
+ if (is_mx6sx()) {
reg = readl(&imx_ccm->cscdr2);
/* Can't change clocks when clock not from pre-mux */
if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
((postd - 1) <<
MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
- } else if (is_cpu_type(MXC_CPU_MX6SX)) {
+ } else if (is_mx6sx()) {
/* Setting LCDIF2 for i.MX6SX */
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
return;
u32 reg = 0;
u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
- if (is_cpu_type(MXC_CPU_MX6SX)) {
+ if (is_mx6sx()) {
if ((base_addr != LCDIF1_BASE_ADDR) &&
(base_addr != LCDIF2_BASE_ADDR)) {
puts("Wrong LCD interface!\n");
MXC_CCM_CCGR3_DISP_AXI_MASK) :
(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
MXC_CCM_CCGR3_DISP_AXI_MASK);
- } else if (is_cpu_type(MXC_CPU_MX6UL)) {
+ } else if (is_mx6ul()) {
if (base_addr != LCDIF1_BASE_ADDR) {
puts("Wrong LCD interface!\n");
return -EINVAL;
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
} else if (fec_id == 1) {
/* Only i.MX6SX/UL support ENET2 */
- if (!(is_cpu_type(MXC_CPU_MX6SX) ||
- is_cpu_type(MXC_CPU_MX6UL)))
+ if (!(is_mx6sx() || is_mx6ul()))
return -EINVAL;
reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
- if (is_cpu_type(MXC_CPU_MX6SX))
+ if (is_mx6sx())
lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
else
lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
/* Make sure PFDs are disabled at boot. */
reg = readl(&mxc_ccm->analog_pfd_528);
/* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
- if (is_cpu_type(MXC_CPU_MX6DL))
+ if (is_mx6sdl())
reg |= 0x80008080;
else
reg |= 0x80808080;
int reg;
reg = readl(&mxc_ccm->analog_pfd_528);
- if (is_cpu_type(MXC_CPU_MX6DL))
+ if (is_mx6sdl())
reg &= ~(0x80008080);
else
reg &= ~(0x80808080);
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#define MMDC1(entry, value) do { \
- if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
- !is_cpu_type(MXC_CPU_MX6SL)) \
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) \
mmdc1->entry = value; \
} while (0)
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
- !is_cpu_type(MXC_CPU_MX6SL))
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+ if (is_mx6dq() || is_mx6dqp()) {
if (mem_speed > 1066)
mem_speed = 1066; /* 1066 MT/s */
* Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
* up to 528 MHz, so reduce the clock to fit chip specs
*/
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+ if (is_mx6dq() || is_mx6dqp()) {
if (clock > 528)
clock = 528; /* 528 MHz */
}
#define OCOTP_CFG3_SPEED_1GHZ 2
#define OCOTP_CFG3_SPEED_1P2GHZ 3
+/*
+ * For i.MX6UL
+ */
+#define OCOTP_CFG3_SPEED_528MHZ 1
+#define OCOTP_CFG3_SPEED_696MHZ 2
+
u32 get_cpu_speed_grade_hz(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
+ if (is_mx6ul()) {
+ if (val == OCOTP_CFG3_SPEED_528MHZ)
+ return 528000000;
+ else if (val == OCOTP_CFG3_SPEED_696MHZ)
+ return 69600000;
+ else
+ return 0;
+ }
+
switch (val) {
/* Valid for IMX6DQ */
case OCOTP_CFG3_SPEED_1P2GHZ:
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ if (is_mx6dq() || is_mx6dqp())
return 1200000000;
/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
case OCOTP_CFG3_SPEED_1GHZ:
return 996000000;
/* Valid for IMX6DQ */
case OCOTP_CFG3_SPEED_850MHZ:
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ if (is_mx6dq() || is_mx6dqp())
return 852000000;
/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
case OCOTP_CFG3_SPEED_800MHZ:
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+ if (is_mx6sx() || is_mx6ul() || is_mx6sl())
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
else
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
- if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) &&
- dev_id == 1) {
+ if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) {
u32 value = readl(&fuse->mac_addr2);
mac[0] = value >> 24 ;
mac[1] = value >> 16 ;
u32 mask528;
u32 reg, periph1, periph2;
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+ if (is_mx6sx() || is_mx6ul())
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
return;
}
+
+void reset_misc(void)
+{
+#ifdef CONFIG_VIDEO_MXS
+ lcdif_power_down();
+#endif
+}
+
.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
};
-struct vcores_data dra752_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS659038_REG_ADDR_SMPS12,
- .mpu.pmic = &tps659038,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS659038_REG_ADDR_SMPS45,
- .eve.pmic = &tps659038,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS659038_REG_ADDR_SMPS6,
- .gpu.pmic = &tps659038,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS659038_REG_ADDR_SMPS7,
- .core.pmic = &tps659038,
-
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS659038_REG_ADDR_SMPS8,
- .iva.pmic = &tps659038,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data dra722_volts = {
- .mpu.value = VDD_MPU_DRA7,
- .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS65917_REG_ADDR_SMPS1,
- .mpu.pmic = &tps659038,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .core.value = VDD_CORE_DRA7,
- .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS65917_REG_ADDR_SMPS2,
- .core.pmic = &tps659038,
-
- /*
- * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
- * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
- */
- .gpu.value = VDD_GPU_DRA7,
- .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS65917_REG_ADDR_SMPS3,
- .gpu.pmic = &tps659038,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- .eve.value = VDD_EVE_DRA7,
- .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS65917_REG_ADDR_SMPS3,
- .eve.pmic = &tps659038,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .iva.value = VDD_IVA_DRA7,
- .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS65917_REG_ADDR_SMPS3,
- .iva.pmic = &tps659038,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
case DRA752_ES2_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
- *omap_vcores = &dra752_volts;
*ctrl = &dra7xx_ctrl;
break;
case DRA722_ES2_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra72x_dplls;
- *omap_vcores = &dra722_volts;
*ctrl = &dra7xx_ctrl;
break;
#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif
+#ifdef CONFIG_LS2080A
+ u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+#endif
#ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
out_le32(cltbenr, 0xf);
#endif
+#ifdef CONFIG_LS2080A
+ /*
+ * In certain Layerscape SoCs, the clock for each core's
+ * has an enable bit in the PMU Physical Core Time Base Enable
+ * Register (PCTBENR), which allows the watchdog to operate.
+ */
+ setbits_le32(pctbenr, 0xff);
+#endif
+
/* Enable clock for timer
* This is a global setting.
*/
mcmemsize: MC DRAM block size. If this variable is not defined, the value
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+mcinitcmd: This environment variable is defined to initiate MC and DPL deployment
+ from the location where it is stored(NOR, NAND, SD, SATA, USB)during
+ u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
+ will be null and MC will not be booted and DPL will not be applied
+ during U-boot booting.However the MC, DPC and DPL can be applied from
+ console independently.
+ The variable needs to be set from the console once and then on
+ rebooting the parameters set in the varible will automatically be
+ executed. The commmand is demostrated taking an example of mc boot
+ using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash:
+
+ cp.b 0xa0000000 0x580300000 $filesize
+ cp.b 0x80000000 0x580800000 $filesize
+ cp.b 0x90000000 0x580700000 $filesize
+
+ setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000'
+
+ If only linux is to be booted then the mcinitcmd environment should be set as
+
+ setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
+
+ Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where
+ MC binary, DPC binary and DPL binary are stored and 0x580300000, 0x580800000
+ and 0x580700000 are addresses in NOR where these are copied. It is to be
+ noted that these addresses in 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
+ can be replaced with the addresses of DDR to
+ which these will be copied in case of these binaries being stored in other
+ devices like SATA, USB, NAND, SD etc.
+
Booting from NAND
-------------------
Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
aliases {
+ spi0 = &qspi;
spi1 = &dspi;
};
};
reg = <2>;
};
};
+
+&qspi {
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: s25fs256s@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
+
+ qspi: quadspi@1550000 {
+ compatible = "fsl,vf610-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ num-cs = <4>;
+ };
};
#define hab_rvt_report_event_p \
( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
+ (is_mx6dqp()) ? \
((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
)
#define hab_rvt_report_status_p \
( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
)
#define hab_rvt_authenticate_image_p \
( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
)
#define hab_rvt_entry_p \
( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
+ (is_mx6dqp()) ? \
((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
)
#define hab_rvt_exit_p \
( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
+ (is_mx6dqp()) ? \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
+ (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
+ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
((hab_rvt_exit_t *)HAB_RVT_EXIT) \
)
*/
/* Check MMU enabled */
if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
- if (is_cpu_type(MXC_CPU_MX6Q) ||
- is_cpu_type(MXC_CPU_MX6D)) {
+ if (is_mx6dq()) {
/*
* This won't work on Rev 1.0.0 of
* i.MX6Q/D, since their ROM doesn't
*/
if (!is_mx6dqp())
writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
- } else if (is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO)) {
+ } else if (is_mx6sdl()) {
writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
- } else if (is_cpu_type(MXC_CPU_MX6SL)) {
+ } else if (is_mx6sl()) {
writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
}
}
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
- if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
+ if (is_mx6sx() || is_mx7()) {
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
writew(enable, &wdog1->wmcr);
writew(enable, &wdog2->wmcr);
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
- is_soc_type(MXC_SOC_MX7))
+ if (is_mx6sx() || is_mx6ul() || is_mx7())
writew(enable, &wdog3->wmcr);
#ifdef CONFIG_MX7D
writew(enable, &wdog4->wmcr);
#if defined(CONFIG_MX6QDL)
stride = 2;
- if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ if (!is_mx6dq())
p += 1;
#else
stride = 1;
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
- if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ if (!is_mx6dq() && !is_mx6dqp())
return 1;
ret = enable_sata_clock();
static inline int gpt_has_clk_source_osc(void)
{
#if defined(CONFIG_MX6)
- if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
- (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
- is_cpu_type(MXC_CPU_MX6UL))
+ if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
+ is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul())
return 1;
return 0;
i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
/* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
- if (is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO) ||
- is_cpu_type(MXC_CPU_MX6SX) ||
- is_cpu_type(MXC_CPU_MX6UL)) {
+ if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) {
i |= GPTCR_24MEN;
/* Produce 3Mhz clock */
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+ { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE},
/* For IFC Region #1, only the first 4MB is cache-enabled */
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+ { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
#define DCFG_RCWSR13 0x130
#define DCFG_RCWSR13_DSPI (0 << 8)
+#define DCFG_RCWSR15 0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
#define DCFG_DCSR_BASE 0X700100000ULL
#define DCFG_DCSR_PORCR1 0x000
/* Supplemental Configuration */
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
+#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
#define CCM_PLL11_CTRL_UPD (0x1 << 30)
#define CCM_PLL11_CTRL_EN (0x1 << 31)
+#if defined(CONFIG_MACH_SUN50I)
+/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
+#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
+#else
#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
+#endif
#define AXI_GATE_OFFSET_DRAM 0
#define is_cpu_type(cpu) (get_cpu_type() == cpu)
#define is_soc_type(soc) (get_soc_type() == soc)
+#define is_mx6() (is_soc_type(MXC_SOC_MX6))
+#define is_mx7() (is_soc_type(MXC_SOC_MX7))
+
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
+#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
+#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
+#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
The total size of the L1 Dcache, if known at compile time.
config SYS_DCACHE_LINE_SIZE
- hex
+ int
default 0
help
The size of L1 Dcache lines, if known at compile time.
if (start_addr == stop)
return;
- cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
+ cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
}
#include <dm.h>
#include <errno.h>
#include <malloc.h>
+#include <syscon.h>
#include <asm/control_regs.h>
#include <asm/coreboot_tables.h>
#include <asm/cpu.h>
uclass_first_device(UCLASS_PCH, &dev);
uclass_first_device(UCLASS_LPC, &dev);
+ /* Set up pin control if available */
+ ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
+ debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
+
return 0;
}
};
};
+ pch_pinctrl {
+ compatible = "intel,x86-pinctrl";
+ reg = <0 0>;
+
+ /*
+ * As of today, the latest version FSP (gold4) for BayTrail
+ * misses the PAD configuration of the SD controller's Card
+ * Detect signal. The default PAD value for the CD pin sets
+ * the pin to work in GPIO mode, which causes card detect
+ * status cannot be reflected by the Present State register
+ * in the SD controller (bit 16 & bit 18 are always zero).
+ *
+ * Configure this pin to function 1 (SD controller).
+ */
+ sdmmc3_cd@0 {
+ pad-offset = <0x3a0>;
+ mode-func = <1>;
+ };
+ };
+
pci {
compatible = "pci-x86";
#address-cells = <3>;
fsp,mrc-init-mmio-size = <0x800>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
- fsp,emmc-boot-mode = <2>;
+ fsp,emmc-boot-mode = <1>;
fsp,enable-sdio;
fsp,enable-sdcard;
fsp,enable-hsuart1;
pch_pinctrl {
compatible = "intel,x86-pinctrl";
+ reg = <0 0>;
+
+ /*
+ * As of today, the latest version FSP (gold4) for BayTrail
+ * misses the PAD configuration of the SD controller's Card
+ * Detect signal. The default PAD value for the CD pin sets
+ * the pin to work in GPIO mode, which causes card detect
+ * status cannot be reflected by the Present State register
+ * in the SD controller (bit 16 & bit 18 are always zero).
+ *
+ * Configure this pin to function 1 (SD controller).
+ */
+ sdmmc3_cd@0 {
+ pad-offset = <0x3a0>;
+ mode-func = <1>;
+ };
};
chosen {
fsp,mrc-init-mmio-size = <0x800>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
- fsp,emmc-boot-mode = <2>;
+ fsp,emmc-boot-mode = <1>;
fsp,enable-sdio;
fsp,enable-sdcard;
fsp,enable-hsuart1;
pch_pinctrl {
compatible = "intel,x86-pinctrl";
+ reg = <0 0>;
/* GPIO E0 */
soc_gpio_s5_0@0 {
output-value = <1>;
direction = <PIN_OUTPUT>;
};
+
+ /*
+ * As of today, the latest version FSP (gold4) for BayTrail
+ * misses the PAD configuration of the SD controller's Card
+ * Detect signal. The default PAD value for the CD pin sets
+ * the pin to work in GPIO mode, which causes card detect
+ * status cannot be reflected by the Present State register
+ * in the SD controller (bit 16 & bit 18 are always zero).
+ *
+ * Configure this pin to function 1 (SD controller).
+ */
+ sdmmc3_cd@0 {
+ pad-offset = <0x3a0>;
+ mode-func = <1>;
+ };
};
chosen {
fsp,mrc-init-mmio-size = <0x800>;
fsp,mrc-init-spd-addr1 = <0xa0>;
fsp,mrc-init-spd-addr2 = <0xa2>;
- fsp,emmc-boot-mode = <2>;
+ fsp,emmc-boot-mode = <1>;
fsp,enable-sdio;
fsp,enable-sdcard;
fsp,enable-hsuart1;
int acpi_create_madt_lapics(u32 current)
{
struct udevice *dev;
- int length = 0;
+ int total_length = 0;
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
-
- length += acpi_create_madt_lapic(
- (struct acpi_madt_lapic *)current,
- plat->cpu_id, plat->cpu_id);
+ int length = acpi_create_madt_lapic(
+ (struct acpi_madt_lapic *)current,
+ plat->cpu_id, plat->cpu_id);
current += length;
+ total_length += length;
}
- return length;
+ return total_length;
}
int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
#include "ls2080aqds_qixis.h"
+#define MC_BOOT_ENV_VAR "mcinitcmd"
#ifdef CONFIG_FSL_MC_ENET
/* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
int board_eth_init(bd_t *bis)
{
int error;
+ char *mc_boot_env_var;
#ifdef CONFIG_FSL_MC_ENET
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
}
}
+ mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
+ if (mc_boot_env_var)
+ run_command_list(mc_boot_env_var, -1, 0);
error = cpu_eth_init(bis);
if (hwconfig_f("xqsgmii", env_hwconfig)) {
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
+#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
+ else if (sw == 0xf)
+ puts("QSPI\n");
else if (sw == 0x15)
printf("IFCCard\n");
else
else
config_board_mux(MUX_TYPE_SDHC);
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+ val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+ if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+ QIXIS_WRITE(brdcfg[9],
+ (QIXIS_READ(brdcfg[9]) & 0xf8) |
+ FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
int board_early_init_f(void)
{
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+ i2c_early_init_f();
+#endif
fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+ /* input clk: 1/2 platform clk, output: input/20 */
+ out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
return 0;
}
DECLARE_GLOBAL_DATA_PTR;
+#define MC_BOOT_ENV_VAR "mcinitcmd"
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
+ char *mc_boot_env_var;
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
}
}
+ mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
+ if (mc_boot_env_var)
+ run_command_list(mc_boot_env_var, -1, 0);
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
}
#endif
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-
static void setup_fec(void)
{
if (is_mx6dqp()) {
if (is_mx6dqp())
setenv("board_rev", "MX6QP");
- else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ else if (is_mx6dq())
setenv("board_rev", "MX6Q");
- else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+ else if (is_mx6sdl())
setenv("board_rev", "MX6DL");
#endif
if (is_mx6dqp())
setenv("board_rev", "MX6QP");
- else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ else if (is_mx6dq())
setenv("board_rev", "MX6Q");
- else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+ else if (is_mx6sdl())
setenv("board_rev", "MX6DL");
#endif
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret) {
- printf("Warning: failed to initialize "
- "mmc dev %d\n", i);
- return ret;
- }
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize "
+ "mmc dev %d\n", i);
+ return ret;
+ }
}
return 0;
The SPL decides to boot either U-Boot (u-boot.img) or the OS (args + kernel)
based on the return value of the spl_start_uboot() function. While often
this can simply be the state of a GPIO based pushbutton or DIP switch, for
-Gateworks Ventana, we use the U-Boot environment 'boot_os' variable which if
-set to '1' will choose to boot the OS rather than U-Boot. While the choice
-of adding env support to the SPL adds a little bit of time to the boot
-process as well as (significant really) SPL code space this was deemed most
-flexible as within the large variety of Gateworks Ventana boards not all of
-them have a user pushbutton and that pushbutton may be configured as a hard
-reset per user configuration.
+Gateworks Ventana, we use an EEPROM register on i2c-0 at 0x50:0x00:
+set to '0' will choose to boot to U-Boot and otherwise it will boot to OS.
To use Falcon mode it is required that you first 'prepare' the 'args' data
that is stored on your boot medium along with the kernel (which can be any
# flash args (at 17MB)
Ventana > nand erase.part args && nand write 18000000 args 100000
- # set boot_os env var to enable booting to Linux
- Ventana > setenv boot_os 1 && saveenv
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
Be sure to adjust 'bootargs' above to your OS needs (this will be different
for various distros such as OpenWrt, Yocto, Android, etc). You can use the
# write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
Ventana > mmc write 18000000 0x800 0x800
- # set boot_os to enable falcon mode
- Ventana > setenv boot_os 1 && saveenv
+ # set i2c register 0x50:0x00=0 to boot to Linux
+ Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1
Be sure to adjust 'bootargs' above to your OS needs (this will be different
for various distros such as OpenWrt, Yocto, Android, etc). You can use the
/* common to add baseboards */
static iomux_v3_cfg_t const gw_gpio_pads[] = {
- /* MSATA_EN */
- IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+ /* SD3_VSELECT */
+ IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
};
/* prototype */
};
static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
+ /* MSATA_EN */
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
};
static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
+ /* MSATA_EN */
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* CAN_STBY */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* USB_HUBRST# */
};
static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
+ /* MSATA_EN */
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* CAN_STBY */
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* PANLEDG# */
};
static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
+ /* MSATA_EN */
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* USBOTG_SEL */
IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
/* USB_HUBRST# */
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
+static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG),
+
+ /* VID_PWR */
+ IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
+ /* PCI_RST# */
+ IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
/*
* Board Specific GPIO
.vidin_en = IMX_GPIO_NR(3, 31),
.usb_sel = IMX_GPIO_NR(1, 2),
.wdis = IMX_GPIO_NR(7, 12),
+ .msata_en = GP_MSATA_SEL,
},
/* GW53xx */
.gps_shdn = IMX_GPIO_NR(1, 27),
.vidin_en = IMX_GPIO_NR(3, 31),
.wdis = IMX_GPIO_NR(7, 12),
+ .msata_en = GP_MSATA_SEL,
},
/* GW54xx */
.dioi2c_en = IMX_GPIO_NR(4, 5),
.pcie_sson = IMX_GPIO_NR(1, 20),
.wdis = IMX_GPIO_NR(5, 17),
+ .msata_en = GP_MSATA_SEL,
},
/* GW551x */
.pcie_rst = IMX_GPIO_NR(1, 29),
.usb_sel = IMX_GPIO_NR(1, 7),
.wdis = IMX_GPIO_NR(7, 12),
+ .msata_en = GP_MSATA_SEL,
+ },
+
+ /* GW553x */
+ {
+ .gpio_pads = gw553x_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
+ .dio_cfg = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+ IMX_GPIO_NR(1, 18),
+ { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+ 4
+ },
+ },
+ .num_gpios = 4,
+ .leds = {
+ IMX_GPIO_NR(4, 10),
+ IMX_GPIO_NR(4, 11),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 0),
+ .vidin_en = IMX_GPIO_NR(5, 20),
+ .wdis = IMX_GPIO_NR(7, 12),
},
};
gpio_request(GP_USB_OTG_PWR, "usbotg_pwr");
gpio_direction_output(GP_USB_OTG_PWR, 0);
- /* MSATA Enable - default to PCI */
- gpio_request(GP_MSATA_SEL, "msata_en");
- gpio_direction_output(GP_MSATA_SEL, 0);
-
/* RS232_EN# */
gpio_request(GP_RS232_EN, "rs232_en");
gpio_direction_output(GP_RS232_EN, 0);
}
}
+ /* MSATA Enable - default to PCI */
+ if (gpio_cfg[board].msata_en) {
+ gpio_request(gpio_cfg[board].msata_en, "msata_en");
+ gpio_direction_output(gpio_cfg[board].msata_en, 0);
+ }
+
/* Expansion Mezzanine IO */
if (gpio_cfg[board].mezz_pwren) {
gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
gpio_request(gpio_cfg[board].wdis, "wlan_dis");
gpio_direction_output(gpio_cfg[board].wdis, 1);
}
+
+ /* sense vselect pin to see if we support uhs-i */
+ gpio_request(GP_SD3_VSELECT, "sd3_vselect");
+ gpio_direction_input(GP_SD3_VSELECT);
+ gpio_cfg[board].usd_vsel = !gpio_get_value(GP_SD3_VSELECT);
}
/* setup GPIO pinmux and default configuration per baseboard and env */
gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
/* MSATA Enable */
- if (is_cpu_type(MXC_CPU_MX6Q) &&
- test_bit(EECONFIG_SATA, info->config)) {
+ if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
gpio_direction_output(GP_MSATA_SEL,
- (hwconfig("msata")) ? 1 : 0);
+ (hwconfig("msata")) ? 1 : 0);
}
/* USBOTG Select (PCISKT or FrontPanel) */
ctrl);
gpio_requestf(cfg->gpio_param, "dio%d", i);
gpio_direction_input(cfg->gpio_param);
- } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
+ } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
cfg->pwm_padmux) {
+ if (!cfg->pwm_param) {
+ printf("DIO%d: Error: pwm config invalid\n",
+ i);
+ continue;
+ }
if (!quiet)
printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
}
if (!quiet) {
- if (is_cpu_type(MXC_CPU_MX6Q) &&
- (test_bit(EECONFIG_SATA, info->config))) {
+ if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
printf("MSATA: %s\n", (hwconfig("msata") ?
"enabled" : "disabled"));
}
#define GP_SD3_CD IMX_GPIO_NR(7, 0)
#define GP_RS232_EN IMX_GPIO_NR(2, 11)
#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
+#define GP_SD3_VSELECT IMX_GPIO_NR(6, 14)
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
int pcie_sson;
int usb_sel;
int wdis;
+ int msata_en;
+ bool usd_vsel;
};
extern struct ventana gpio_cfg[GW_UNKNOWN];
} else if (info->model[4] == '2') {
type = GW552x;
break;
+ } else if (info->model[4] == '3') {
+ type = GW553x;
+ break;
}
/* fall through */
default:
/* list of config bits that the bootloader will remove from dtb if not set */
struct ventana_eeprom_config econfig[] = {
{ "eth0", "ethernet0", EECONFIG_ETH0 },
- { "eth1", "ethernet1", EECONFIG_ETH1 },
- { "sata", "ahci0", EECONFIG_SATA },
- { "pcie", NULL, EECONFIG_PCIE},
- { "lvds0", NULL, EECONFIG_LVDS0 },
- { "lvds1", NULL, EECONFIG_LVDS1 },
{ "usb0", NULL, EECONFIG_USB0 },
{ "usb1", NULL, EECONFIG_USB1 },
{ "mmc0", NULL, EECONFIG_SD0 },
{ "mmc1", NULL, EECONFIG_SD1 },
{ "mmc2", NULL, EECONFIG_SD2 },
{ "mmc3", NULL, EECONFIG_SD3 },
- { "uart0", NULL, EECONFIG_UART0 },
- { "uart1", NULL, EECONFIG_UART1 },
- { "uart2", NULL, EECONFIG_UART2 },
- { "uart3", NULL, EECONFIG_UART3 },
- { "uart4", NULL, EECONFIG_UART4 },
- { "ipu0", NULL, EECONFIG_IPU0 },
- { "ipu1", NULL, EECONFIG_IPU1 },
- { "can0", NULL, EECONFIG_FLEXCAN },
- { "i2c0", NULL, EECONFIG_I2C0 },
- { "i2c1", NULL, EECONFIG_I2C1 },
- { "i2c2", NULL, EECONFIG_I2C2 },
- { "vpu", NULL, EECONFIG_VPU },
- { "csi0", NULL, EECONFIG_CSI0 },
- { "csi1", NULL, EECONFIG_CSI1 },
- { "spi0", NULL, EECONFIG_ESPCI0 },
- { "spi1", NULL, EECONFIG_ESPCI1 },
- { "spi2", NULL, EECONFIG_ESPCI2 },
- { "spi3", NULL, EECONFIG_ESPCI3 },
- { "spi4", NULL, EECONFIG_ESPCI4 },
- { "spi5", NULL, EECONFIG_ESPCI5 },
- { "gps", "pps", EECONFIG_GPS },
- { "hdmi_in", NULL, EECONFIG_HDMI_IN },
- { "hdmi_out", NULL, EECONFIG_HDMI_OUT },
- { "cvbs_in", NULL, EECONFIG_VID_IN },
- { "cvbs_out", NULL, EECONFIG_VID_OUT },
- { "nand", NULL, EECONFIG_NAND },
{ /* Sentinel */ }
};
#include <i2c.h>
#include <linux/ctype.h>
+#include "ventana_eeprom.h"
#include "gsc.h"
/*
puts("fRD\n");
} else {
ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
+ if (reg == GSC_HWMON_TEMP && ui > 0x8000)
+ ui -= 0xffff;
if (ui == 0xffffff)
puts("invalid\n");
else
int gsc_info(int verbose)
{
- const char *model = getenv("model");
unsigned char buf[16];
i2c_set_bus_num(0);
gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
&buf[GSC_SC_STATUS], 1);
}
+ if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) {
+ int ui = buf[0] | buf[1]<<8;
+ if (ui > 0x8000)
+ ui -= 0xffff;
+ printf(" board temp at %dC", ui / 10);
+ }
puts("\n");
if (!verbose)
return CMD_RET_SUCCESS;
read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3);
read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3);
- read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3);
+ if (strncasecmp((const char*) ventana_info.model, "GW553", 5))
+ read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3);
read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3);
read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3);
- switch (model[3]) {
+ switch (ventana_info.model[3]) {
case '1': /* GW51xx */
read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
break;
}
#ifdef CONFIG_CMD_GSC
+static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ unsigned char reg;
+ unsigned long secs = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ secs = simple_strtoul(argv[1], NULL, 10);
+ printf("GSC Sleeping for %ld seconds\n", secs);
+
+ i2c_set_bus_num(0);
+ reg = (secs >> 24) & 0xff;
+ if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, ®, 1))
+ goto error;
+ reg = (secs >> 16) & 0xff;
+ if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, ®, 1))
+ goto error;
+ reg = (secs >> 8) & 0xff;
+ if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, ®, 1))
+ goto error;
+ reg = secs & 0xff;
+ if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, ®, 1))
+ goto error;
+ if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
+ goto error;
+ reg |= (1 << 2);
+ if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
+ goto error;
+ reg &= ~(1 << 2);
+ reg |= 0x3;
+ if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
+ goto error;
+
+ return CMD_RET_SUCCESS;
+
+error:
+ printf("i2c error\n");
+ return CMD_RET_FAILURE;
+}
+
static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned char reg;
if (strcasecmp(argv[1], "wd") == 0)
return do_gsc_wd(cmdtp, flag, --argc, ++argv);
+ else if (strcasecmp(argv[1], "sleep") == 0)
+ return do_gsc_sleep(cmdtp, flag, --argc, ++argv);
return CMD_RET_USAGE;
}
U_BOOT_CMD(
gsc, 4, 1, do_gsc, "GSC configuration",
- "[wd enable [30|60]]|[wd disable]\n"
+ "[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n"
);
#endif /* CONFIG_CMD_GSC */
#include <asm/io.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
+#include <hwconfig.h>
#include <i2c.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- /* CD */
- IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
/* ENET */
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FEC_MXC
- if (board_type != GW551x && board_type != GW552x) {
+ struct ventana_board_info *info = &ventana_info;
+
+ if (test_bit(EECONFIG_ETH0, info->config)) {
setup_iomux_enet(GP_PHY_RST);
cpu_eth_init(bis);
}
writel(reg, &iomux->gpr[2]);
/* Enable Backlight */
+ gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
+ gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
- /* Backlight CABEN on LVDS connector */
- gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
+ /* LVDS Backlight GPIO on LVDS connector - output low */
SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
setenv("model_base", str);
sprintf(fdt, "%s-%s.dtb", cputype, str);
setenv("fdt_file1", fdt);
- if (board_type != GW551x && board_type != GW552x)
+ if (board_type != GW551x &&
+ board_type != GW552x &&
+ board_type != GW553x)
str[4] = 'x';
str[5] = 'x';
str[6] = 0;
return 0;
}
+/* enable a property of a node if the node is found */
+static inline void ft_enable_path(void *blob, const char *path)
+{
+ int i = fdt_path_offset(blob, path);
+ if (i >= 0) {
+ debug("enabling %s\n", path);
+ fdt_status_okay(blob, i);
+ }
+}
+
+/* remove a property of a node if the node is found */
+static inline void ft_delprop_path(void *blob, const char *path,
+ const char *name)
+{
+ int i = fdt_path_offset(blob, path);
+ if (i) {
+ debug("removing %s/%s\n", path, name);
+ fdt_delprop(blob, i, name);
+ }
+}
+
/*
* called prior to booting kernel or by 'fdt boardsetup' command
*
range[1] = cpu_to_fdt32(23);
}
}
+
+ /* these have broken usd_vsel */
+ if (strstr((const char *)info->model, "SP318-B") ||
+ strstr((const char *)info->model, "SP331-B"))
+ gpio_cfg[board_type].usd_vsel = 0;
}
/*
ft_sethdmiinfmt(blob, "yuv422bt656");
}
+ /* Configure DIO */
+ for (i = 0; i < gpio_cfg[board_type].num_gpios; i++) {
+ struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
+ char arg[10];
+
+ sprintf(arg, "dio%d", i);
+ if (!hwconfig(arg))
+ continue;
+ if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
+ {
+ char path[48];
+ sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
+ 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
+ printf(" Enabling pwm%d for DIO%d\n",
+ cfg->pwm_param, i);
+ ft_enable_path(blob, path);
+ }
+ }
+
+ /* remove no-1-8-v if UHS-I support is present */
+ if (gpio_cfg[board_type].usd_vsel) {
+ debug("Enabling UHS-I support\n");
+ ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
+ "no-1-8-v");
+ }
+
/*
* Peripheral Config:
* remove nodes by alias path if EEPROM config tells us the
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <environment.h>
+#include <i2c.h>
#include <spl.h>
#include "gsc.h"
.trasmin = 3500,
};
+/* MT41K512M16HA-125 (8Gb density) */
+static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
+ .mem_speed = 1600,
+ .density = 8,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 16,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
/*
* calibration - these are the various CPU/DDR3 combinations we support
*/
.p1_mpwrdlctl = 0X40304239,
};
+static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x002A0025,
+ .p0_mpwldectrl1 = 0x003A002A,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x43430356,
+ .p0_mpdgctrl1 = 0x033C0335,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x4B373F42,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x303E3C36,
+};
+
static void spl_dram_init(int width, int size_mb, int board_model)
{
struct mx6_ddr3_cfg *mem = NULL;
else
calib = &mx6sdl_256x32_mmdc_calib;
debug("4gB density\n");
+ } else if (width == 32 && size_mb == 2048) {
+ mem = &mt41k512m16ha_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_512x32_mmdc_calib;
+ debug("8gB density\n");
} else if (width == 64 && size_mb == 512) {
mem = &mt41k64m16jt_125;
debug("1gB density\n");
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* disable boot watchdog */
- gsc_boot_wd_disable();
}
/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
/* return 1 if we wish to boot to uboot vs os (falcon mode) */
int spl_start_uboot(void)
{
- int ret = 1;
+ unsigned char ret = 1;
debug("%s\n", __func__);
#ifdef CONFIG_SPL_ENV_SUPPORT
debug("boot_os=%s\n", getenv("boot_os"));
if (getenv_yesno("boot_os") == 1)
ret = 0;
+#else
+ /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
+ i2c_set_bus_num(0);
+ gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
#endif
+ if (!ret)
+ gsc_boot_wd_disable();
+
debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
return ret;
}
GW54xx,
GW551x,
GW552x,
+ GW553x,
GW_UNKNOWN,
GW_BADCRC,
};
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
+
+#ifdef CONFIG_VIDEO_IPUV3
/* We need at least 200ms between power on and backlight on
* as per specifications from CHI MEI */
mdelay(250);
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
pwm_enable(0);
+#endif
return 0;
}
}
}
+struct vcores_data dra752_volts = {
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
+ .mpu.pmic = &tps659038,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
+ .eve.pmic = &tps659038,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6,
+ .gpu.pmic = &tps659038,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS7,
+ .core.pmic = &tps659038,
+
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8,
+ .iva.pmic = &tps659038,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+struct vcores_data dra722_volts = {
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS65917_REG_ADDR_SMPS1,
+ .mpu.pmic = &tps659038,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS65917_REG_ADDR_SMPS2,
+ .core.pmic = &tps659038,
+
+ /*
+ * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
+ * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
+ */
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS65917_REG_ADDR_SMPS3,
+ .gpu.pmic = &tps659038,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS65917_REG_ADDR_SMPS3,
+ .eve.pmic = &tps659038,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS65917_REG_ADDR_SMPS3,
+ .iva.pmic = &tps659038,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
/**
* @brief board_init
*
}
#endif /* CONFIG_SPL_BUILD */
+void vcores_init(void)
+{
+ if (board_is_dra74x_evm()) {
+ *omap_vcores = &dra752_volts;
+ } else if (board_is_dra72x_evm()) {
+ *omap_vcores = &dra722_volts;
+ } else {
+ /* If EEPROM is not populated */
+ if (is_dra72x())
+ *omap_vcores = &dra722_volts;
+ else
+ *omap_vcores = &dra752_volts;
+ }
+}
+
void set_muxconf_regs(void)
{
do_set_mux32((*ctrl)->control_padconf_core_base,
disk_partition_t *parts;
int errno = 0;
uint64_t size_ll, start_ll;
+ lbaint_t offset = 0;
debug("%s: lba num: 0x%x %d\n", __func__,
(unsigned int)dev_desc->lba, (unsigned int)dev_desc->lba);
}
if (extract_env(val, &p))
p = val;
- size_ll = ustrtoull(p, &p, 0);
- parts[i].size = lldiv(size_ll, dev_desc->blksz);
+ if ((strcmp(p, "-") == 0)) {
+ /* remove first usable lba and last block */
+ parts[i].size = dev_desc->lba - 34 - 1 - offset;
+ } else {
+ size_ll = ustrtoull(p, &p, 0);
+ parts[i].size = lldiv(size_ll, dev_desc->blksz);
+ }
+
free(val);
/* start address */
free(val);
}
+ offset += parts[i].size + parts[i].start;
+
/* bootable */
if (found_key(tok, "bootable"))
parts[i].bootable = 1;
endif # !CONFIG_SPL_BUILD
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
+CONFIG_INITIAL_USB_SCAN_DELAY=2000
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_USB_EHCI_HCD=y
+CONFIG_AXP_ALDO3_VOLT=3300
+CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FPGA=n
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FPGA=n
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FPGA=n
CONFIG_CMD_GPIO=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+CONFIG_CMD_NET=n
+CONFIG_CMD_NFS=n
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FAT=n
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
+CONFIG_EFI_LOADER=n
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LS2080AQDS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT,LS2080A"
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DM=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
Pin nodes must be children of the pinctrl master node and can
contain the following properties:
- pad-offset - (required) offset in the IOBASE for the pin to configure
-- gpio-offset - (required) 2 cells
+- gpio-offset - (required only when 'mode-gpio' is set) 2 cells
- offset in the GPIOBASE for the pin to configure
- the bit shift in this register (4 = bit 4)
- mode-gpio - (optional) standalone property to force the pin into GPIO mode
in case of 'mode-gpio' property set:
- output-value - (optional) this set the default output value of the GPIO
- direction - (optional) this set the direction of the gpio
-- pull-str - (optional) this set the pull strength of the pin
+- pull-strength - (optional) this set the pull strength of the pin
- pull-assign - (optional) this set the pull assignement (up/down) of the pin
-- invert - (optional) this input pin is inverted
+- invert - (optional) this input pin is inverted
Example:
pin_usb_host_en0@0 {
- gpio-offset = <0x80 8>;
- pad-offset = <0x260>;
- mode-gpio;
- output-value = <1>;
- direction = <PIN_OUTPUT>;
+ gpio-offset = <0x80 8>;
+ pad-offset = <0x260>;
+ mode-gpio;
+ output-value = <1>;
+
direction = <PIN_OUTPUT>;
};
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/
struct ahci_probe_ent *probe_ent = NULL;
#if defined(CONFIG_MX6)
- if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ if (!is_mx6dq() && !is_mx6dqp())
return 1;
#endif
if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
.name = "mod_exp_sw",
.id = UCLASS_MOD_EXP,
.ops = &mod_exp_ops_sw,
+ .flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DEVICE(mod_exp_sw) = {
#include <fdtdec.h>
#include <pch.h>
#include <pci.h>
-#include <syscon.h>
#include <asm/cpu.h>
#include <asm/gpio.h>
#include <asm/io.h>
struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct broadwell_bank_priv *priv = dev_get_priv(dev);
- struct udevice *pinctrl;
- int ret;
-
- /* Set up pin control if available */
- ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
- debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
#include <fdtdec.h>
#include <pch.h>
#include <pci.h>
-#include <syscon.h>
#include <asm/cpu.h>
#include <asm/gpio.h>
#include <asm/io.h>
struct ich6_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ich6_bank_priv *bank = dev_get_priv(dev);
- struct udevice *pinctrl;
-
- /* Set up pin control if available */
- syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
{
}
+/* implement possible for i2c specific early i2c init */
+__weak void i2c_early_init_f(void)
+{
+}
+
/*
* i2c_init_all():
*
#define IMX_I2C_REGSHIFT 2
#define VF610_I2C_REGSHIFT 0
+
+#define I2C_EARLY_INIT_INDEX 0
+#ifdef CONFIG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
+#else
+#define I2C_IFDR_DIV_CONSERVATIVE 0x7e
+#endif
+
/* Register index */
#define IADR 0
#define IFDR 1
bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
}
+/*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+ ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+ bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+ & I2C_QUIRK_FLAG ? true : false;
+ int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+ /* Set I2C divider value */
+ writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+ /* Reset module */
+ writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+ writeb(0, base + (I2SR << reg_shift));
+ /* Enable I2C */
+ writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
+
/*
* Init I2C Bus
*/
{
u32 phy_index;
- if (is_cpu_type(MXC_CPU_MX6SL)) {
+ if (is_mx6sl()) {
phy_index = index;
- } else if (is_cpu_type(MXC_CPU_MX6UL)) {
+ } else if (is_mx6ul()) {
if (index >= 6)
phy_index = fuse_bank_physical(5) + (index - 6) + 3;
else
int max_ecc_strength_supported;
/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
- if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
+ if (is_mx6sx() || is_mx7())
max_ecc_strength_supported = 62;
else
max_ecc_strength_supported = 40;
/* Do not access reserved register for i.MX6UL */
- if (!is_cpu_type(MXC_CPU_MX6UL)) {
+ if (!is_mx6ul()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
access the SPI NOR flash on platforms embedding this Intel
ICH IP core.
+config PIC32_SPI
+ bool "Microchip PIC32 SPI driver"
+ depends on MACH_PIC32
+ help
+ Enable the Microchip PIC32 SPI driver. This driver can be used
+ to access the SPI NOR flash, MMC-over-SPI on platforms based on
+ Microchip PIC32 family devices.
+
config ROCKCHIP_SPI
bool "Rockchip SPI driver"
help
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
--- /dev/null
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Copyright (c) 2015, Microchip Technology Inc.
+ * Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <linux/compat.h>
+#include <malloc.h>
+#include <spi.h>
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <dt-bindings/clock/microchip,clock.h>
+#include <mach/pic32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PIC32 SPI controller registers */
+struct pic32_reg_spi {
+ struct pic32_reg_atomic ctrl;
+ struct pic32_reg_atomic status;
+ struct pic32_reg_atomic buf;
+ struct pic32_reg_atomic baud;
+ struct pic32_reg_atomic ctrl2;
+};
+
+/* Bit fields in SPI Control Register */
+#define PIC32_SPI_CTRL_MSTEN BIT(5) /* Enable SPI Master */
+#define PIC32_SPI_CTRL_CKP BIT(6) /* active low */
+#define PIC32_SPI_CTRL_CKE BIT(8) /* Tx on falling edge */
+#define PIC32_SPI_CTRL_SMP BIT(9) /* Rx at middle or end of tx */
+#define PIC32_SPI_CTRL_BPW_MASK 0x03 /* Bits per word */
+#define PIC32_SPI_CTRL_BPW_8 0x0
+#define PIC32_SPI_CTRL_BPW_16 0x1
+#define PIC32_SPI_CTRL_BPW_32 0x2
+#define PIC32_SPI_CTRL_BPW_SHIFT 10
+#define PIC32_SPI_CTRL_ON BIT(15) /* Macro enable */
+#define PIC32_SPI_CTRL_ENHBUF BIT(16) /* Enable enhanced buffering */
+#define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */
+#define PIC32_SPI_CTRL_MSSEN BIT(28) /* SPI macro will drive SS */
+#define PIC32_SPI_CTRL_FRMEN BIT(31) /* Enable framing mode */
+
+/* Bit fields in SPI Status Register */
+#define PIC32_SPI_STAT_RX_OV BIT(6) /* err, s/w needs to clear */
+#define PIC32_SPI_STAT_TF_LVL_MASK 0x1f
+#define PIC32_SPI_STAT_TF_LVL_SHIFT 16
+#define PIC32_SPI_STAT_RF_LVL_MASK 0x1f
+#define PIC32_SPI_STAT_RF_LVL_SHIFT 24
+
+/* Bit fields in SPI Baud Register */
+#define PIC32_SPI_BAUD_MASK 0x1ff
+
+struct pic32_spi_priv {
+ struct pic32_reg_spi *regs;
+ u32 fifo_depth; /* FIFO depth in bytes */
+ u32 fifo_n_word; /* FIFO depth in words */
+ struct gpio_desc cs_gpio;
+
+ /* Current SPI slave specific */
+ ulong clk_rate;
+ u32 speed_hz; /* spi-clk rate */
+ int mode;
+
+ /* Current message/transfer state */
+ const void *tx;
+ const void *tx_end;
+ const void *rx;
+ const void *rx_end;
+ u32 len;
+
+ /* SPI FiFo accessor */
+ void (*rx_fifo)(struct pic32_spi_priv *);
+ void (*tx_fifo)(struct pic32_spi_priv *);
+};
+
+static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
+{
+ writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
+}
+
+static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
+{
+ writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
+}
+
+static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
+{
+ u32 sr = readl(&priv->regs->status.raw);
+
+ return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
+}
+
+static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
+{
+ u32 sr = readl(&priv->regs->status.raw);
+
+ return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
+}
+
+/* Return the max entries we can fill into tx fifo */
+static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
+{
+ u32 tx_left, tx_room, rxtx_gap;
+
+ tx_left = (priv->tx_end - priv->tx) / n_bytes;
+ tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);
+
+ rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
+ rxtx_gap /= n_bytes;
+ return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
+}
+
+/* Return the max entries we should read out of rx fifo */
+static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
+{
+ u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;
+
+ return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
+}
+
+#define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \
+static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv) \
+{ \
+ __type val; \
+ u32 mx = pic32_rx_max(priv, sizeof(__type)); \
+ \
+ for (; mx; mx--) { \
+ val = read##__bwl(&priv->regs->buf.raw); \
+ if (priv->rx_end - priv->len) \
+ *(__type *)(priv->rx) = val; \
+ priv->rx += sizeof(__type); \
+ } \
+} \
+ \
+static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv) \
+{ \
+ __type val; \
+ u32 mx = pic32_tx_max(priv, sizeof(__type)); \
+ \
+ for (; mx ; mx--) { \
+ val = (__type) ~0U; \
+ if (priv->tx_end - priv->len) \
+ val = *(__type *)(priv->tx); \
+ write##__bwl(val, &priv->regs->buf.raw); \
+ priv->tx += sizeof(__type); \
+ } \
+}
+BUILD_SPI_FIFO_RW(byte, u8, b);
+BUILD_SPI_FIFO_RW(word, u16, w);
+BUILD_SPI_FIFO_RW(dword, u32, l);
+
+static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
+ unsigned int wordlen)
+{
+ u32 bits_per_word;
+ u32 val;
+
+ switch (wordlen) {
+ case 8:
+ priv->rx_fifo = pic32_spi_rx_byte;
+ priv->tx_fifo = pic32_spi_tx_byte;
+ bits_per_word = PIC32_SPI_CTRL_BPW_8;
+ break;
+ case 16:
+ priv->rx_fifo = pic32_spi_rx_word;
+ priv->tx_fifo = pic32_spi_tx_word;
+ bits_per_word = PIC32_SPI_CTRL_BPW_16;
+ break;
+ case 32:
+ priv->rx_fifo = pic32_spi_rx_dword;
+ priv->tx_fifo = pic32_spi_tx_dword;
+ bits_per_word = PIC32_SPI_CTRL_BPW_32;
+ break;
+ default:
+ printf("pic32-spi: unsupported wordlen\n");
+ return -EINVAL;
+ }
+
+ /* set bits-per-word */
+ val = readl(&priv->regs->ctrl.raw);
+ val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
+ val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
+ writel(val, &priv->regs->ctrl.raw);
+
+ /* calculate maximum number of words fifo can hold */
+ priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);
+
+ return 0;
+}
+
+static int pic32_spi_claim_bus(struct udevice *slave)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+ /* enable chip */
+ pic32_spi_enable(priv);
+
+ return 0;
+}
+
+static int pic32_spi_release_bus(struct udevice *slave)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+ /* disable chip */
+ pic32_spi_disable(priv);
+
+ return 0;
+}
+
+static void spi_cs_activate(struct pic32_spi_priv *priv)
+{
+ if (!dm_gpio_is_valid(&priv->cs_gpio))
+ return;
+
+ dm_gpio_set_value(&priv->cs_gpio, 1);
+}
+
+static void spi_cs_deactivate(struct pic32_spi_priv *priv)
+{
+ if (!dm_gpio_is_valid(&priv->cs_gpio))
+ return;
+
+ dm_gpio_set_value(&priv->cs_gpio, 0);
+}
+
+static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
+ const void *tx_buf, void *rx_buf,
+ unsigned long flags)
+{
+ struct dm_spi_slave_platdata *slave_plat;
+ struct udevice *bus = slave->parent;
+ struct pic32_spi_priv *priv;
+ int len = bitlen / 8;
+ int ret = 0;
+ ulong tbase;
+
+ priv = dev_get_priv(bus);
+ slave_plat = dev_get_parent_platdata(slave);
+
+ debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
+ bus->seq, slave_plat->cs, flags);
+ debug("msg tx %p, rx %p submitted of %d byte(s)\n",
+ tx_buf, rx_buf, len);
+
+ /* assert cs */
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(priv);
+
+ /* set current transfer information */
+ priv->tx = tx_buf;
+ priv->rx = rx_buf;
+ priv->tx_end = priv->tx + len;
+ priv->rx_end = priv->rx + len;
+ priv->len = len;
+
+ /* transact by polling */
+ tbase = get_timer(0);
+ for (;;) {
+ priv->tx_fifo(priv);
+ priv->rx_fifo(priv);
+
+ /* received sufficient data */
+ if (priv->rx >= priv->rx_end) {
+ ret = 0;
+ break;
+ }
+
+ if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
+ printf("pic32_spi: error, xfer timedout.\n");
+ flags |= SPI_XFER_END;
+ ret = -ETIMEDOUT;
+ break;
+ }
+ }
+
+ /* deassert cs */
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(priv);
+
+ return ret;
+}
+
+static int pic32_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(bus);
+ u32 div;
+
+ debug("%s: %s, speed %u\n", __func__, bus->name, speed);
+
+ /* div = [clk_in / (2 * spi_clk)] - 1 */
+ div = (priv->clk_rate / 2 / speed) - 1;
+ div &= PIC32_SPI_BAUD_MASK;
+ writel(div, &priv->regs->baud.raw);
+
+ priv->speed_hz = speed;
+
+ return 0;
+}
+
+static int pic32_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(bus);
+ u32 val;
+
+ debug("%s: %s, mode %d\n", __func__, bus->name, mode);
+
+ /* set spi-clk mode */
+ val = readl(&priv->regs->ctrl.raw);
+ /* HIGH when idle */
+ if (mode & SPI_CPOL)
+ val |= PIC32_SPI_CTRL_CKP;
+ else
+ val &= ~PIC32_SPI_CTRL_CKP;
+
+ /* TX at idle-to-active clk transition */
+ if (mode & SPI_CPHA)
+ val &= ~PIC32_SPI_CTRL_CKE;
+ else
+ val |= PIC32_SPI_CTRL_CKE;
+
+ /* RX at end of tx */
+ val |= PIC32_SPI_CTRL_SMP;
+ writel(val, &priv->regs->ctrl.raw);
+
+ priv->mode = mode;
+
+ return 0;
+}
+
+static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+ return pic32_spi_set_word_size(priv, wordlen);
+}
+
+static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
+{
+ u32 val;
+
+ /* disable module */
+ pic32_spi_disable(priv);
+
+ val = readl(&priv->regs->ctrl);
+
+ /* enable enhanced fifo of 128bit deep */
+ val |= PIC32_SPI_CTRL_ENHBUF;
+ priv->fifo_depth = 16;
+
+ /* disable framing mode */
+ val &= ~PIC32_SPI_CTRL_FRMEN;
+
+ /* enable master mode */
+ val |= PIC32_SPI_CTRL_MSTEN;
+
+ /* select clk source */
+ val &= ~PIC32_SPI_CTRL_MCLKSEL;
+
+ /* set manual /CS mode */
+ val &= ~PIC32_SPI_CTRL_MSSEN;
+
+ writel(val, &priv->regs->ctrl);
+
+ /* clear rx overflow indicator */
+ writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
+}
+
+static int pic32_spi_probe(struct udevice *bus)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
+ struct udevice *clkdev;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, bus->of_offset, "reg", &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+ if (!priv->regs)
+ return -EINVAL;
+
+ dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ "spi-max-frequency", 250000000);
+ /* get clock rate */
+ ret = clk_get_by_index(bus, 0, &clkdev);
+ if (ret < 0) {
+ printf("pic32-spi: error, clk not found\n");
+ return ret;
+ }
+ priv->clk_rate = clk_get_periph_rate(clkdev, ret);
+
+ /* initialize HW */
+ pic32_spi_hw_init(priv);
+
+ /* set word len */
+ pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
+
+ /* PIC32 SPI controller can automatically drive /CS during transfer
+ * depending on fifo fill-level. /CS will stay asserted as long as
+ * TX fifo is non-empty, else will be deasserted confirming completion
+ * of the ongoing transfer. To avoid this sort of error we will drive
+ * /CS manually by toggling cs-gpio pins.
+ */
+ ret = gpio_request_by_name_nodev(gd->fdt_blob, bus->of_offset,
+ "cs-gpios", 0,
+ &priv->cs_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ printf("pic32-spi: error, cs-gpios not found\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dm_spi_ops pic32_spi_ops = {
+ .claim_bus = pic32_spi_claim_bus,
+ .release_bus = pic32_spi_release_bus,
+ .xfer = pic32_spi_xfer,
+ .set_speed = pic32_spi_set_speed,
+ .set_mode = pic32_spi_set_mode,
+ .set_wordlen = pic32_spi_set_wordlen,
+};
+
+static const struct udevice_id pic32_spi_ids[] = {
+ { .compatible = "microchip,pic32mzda-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(pic32_spi) = {
+ .name = "pic32_spi",
+ .id = UCLASS_SPI,
+ .of_match = pic32_spi_ids,
+ .ops = &pic32_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct pic32_spi_priv),
+ .probe = pic32_spi_probe,
+};
int musb_usb_remove(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
musb_stop(host->host);
+ sunxi_usb_phy_exit(0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+#endif
+ clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+
return 0;
}
/*
* Env Settings
*/
-#ifndef CONFIG_BOOTDELAY
-# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-# else
-# endif
-#endif
#ifndef CONFIG_BOOTCOMMAND
# define CONFIG_BOOTCOMMAND "run ramboot"
#endif
#define CONFIG_MXC_OCOTP
/* SATA Configs */
-#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#define CONFIG_LIBATA
+#endif
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_DOS_PARTITION
/* USB Configs */
+#ifdef CONFIG_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
#define CONFIG_G_DNL_MANUFACTURER "Advantech"
+#endif
/* Networking Configs */
+#ifdef CONFIG_NET
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
+#endif
/* Serial Flash */
#ifdef CONFIG_CMD_SF
"bootm; " \
"fi;\0" \
-#define CONFIG_BOOTCOMMAND \
- "usb start; " \
- "setenv dev usb; " \
- "setenv devnum 0; " \
- "setenv rootdev sda1; " \
- "run tryboot; " \
- \
+#define CONFIG_MMCBOOTCOMMAND \
"setenv dev mmc; " \
- "setenv rootdev mmcblk0p1; " \
+ "setenv rootdev mmcblk0p${partnum}; " \
\
"setenv devnum ${sddev}; " \
"if mmc dev ${devnum}; then " \
"run tryboot; " \
- "setenv rootdev mmcblk1p1; " \
+ "setenv rootdev mmcblk1p${partnum}; " \
"fi; " \
\
"setenv devnum ${emmcdev}; " \
"if mmc dev ${devnum}; then " \
"run tryboot; " \
"fi; " \
+
+#define CONFIG_USBBOOTCOMMAND \
+ "usb start; " \
+ "setenv dev usb; " \
+ "setenv devnum 0; " \
+ "setenv rootdev sda${partnum}; " \
+ "run tryboot; " \
\
+ CONFIG_MMCBOOTCOMMAND \
"bmode usb; " \
+#ifdef CONFIG_CMD_USB
+#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
+#else
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+#endif
+
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+
/* Framebuffer */
-#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
+#endif
#define CONFIG_PWM_IMX
#define CONFIG_IMX6_PWM_PER_CLK 66000000
/* Falcon Mode */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#include "mx6_common.h"
+#undef CONFIG_SPL_EXT_SUPPORT
#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */
#define CONFIG_DM_THERMAL
#endif
-/* GPIO */
-#define CONFIG_MXC_GPIO
-
/* Thermal */
#define CONFIG_IMX_THERMAL
/* Miscellaneous configurable options */
#define CONFIG_HWCONFIG
+#define CONFIG_PREBOOT
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
\
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
+ "disk=0\0" \
+ "part=1\0" \
\
"fdt_high=0xffffffff\0" \
"fdt_addr=0x18000000\0" \
"initrd_high=0xffffffff\0" \
+ "fixfdt=" \
+ "fdt addr ${fdt_addr}\0" \
"bootdir=boot\0" \
"loadfdt=" \
"if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \
"echo Loaded DTB from ${bootdir}/${fdt_file}; " \
+ "run fixfdt; " \
"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \
"echo Loaded DTB from ${bootdir}/${fdt_file1}; " \
+ "run fixfdt; " \
"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \
"echo Loaded DTB from ${bootdir}/${fdt_file2}; " \
+ "run fixfdt; " \
"fi\0" \
\
+ "fs=ext4\0" \
"script=6x_bootscript-ventana\0" \
"loadscript=" \
"if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \
- "source; " \
+ "source ${loadaddr}; " \
"fi\0" \
\
"uimage=uImage\0" \
- "mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \
+ "mmc_root=/dev/mmcblk0p1 rootfstype=${fs} rootwait rw\0" \
"mmc_boot=" \
- "setenv fsload 'ext2load mmc 0:1'; " \
- "mmc dev 0 && mmc rescan && " \
+ "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \
+ "mmc dev ${disk} && mmc rescan && " \
"setenv dtype mmc; run loadscript; " \
"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
"setenv bootargs console=${console},${baudrate} " \
- "root=/dev/mmcblk0p1 rootfstype=ext4 " \
+ "root=/dev/mmcblk0p1 rootfstype=${fs} " \
"rootwait rw ${video} ${extra}; " \
- "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "if run loadfdt; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"bootm; " \
"fi\0" \
\
"sata_boot=" \
- "setenv fsload 'ext2load sata 0:1'; sata init && " \
+ "setenv fsload \"${fs}load sata ${disk}:${part}\"; " \
+ "sata init && " \
"setenv dtype sata; run loadscript; " \
"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
"setenv bootargs console=${console},${baudrate} " \
- "root=/dev/sda1 rootfstype=ext4 " \
+ "root=/dev/sda1 rootfstype=${fs} " \
"rootwait rw ${video} ${extra}; " \
- "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "if run loadfdt; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"bootm; " \
"fi; " \
"fi\0" \
"usb_boot=" \
- "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \
+ "setenv fsload \"${fs}load usb ${disk}:${part}\"; " \
+ "usb start && usb dev ${disk} && " \
"setenv dtype usb; run loadscript; " \
"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
"setenv bootargs console=${console},${baudrate} " \
- "root=/dev/sda1 rootfstype=ext4 " \
+ "root=/dev/sda1 rootfstype=${fs} " \
"rootwait rw ${video} ${extra}; " \
- "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "if run loadfdt; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"bootm; " \
"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
"setenv bootargs console=${console},${baudrate} " \
"root=${root} ${video} ${extra}; " \
- "if run loadfdt && fdt addr ${fdt_addr}; then " \
+ "if run loadfdt; then " \
"ubifsumount; " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
/* Link Definitions */
+#ifndef CONFIG_QSPI_BOOT
#ifdef CONFIG_SPL
#define CONFIG_SYS_TEXT_BASE 0x80400000
#else
#define CONFIG_SYS_TEXT_BASE 0x30100000
#endif
+#endif
#ifdef CONFIG_EMU
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
-#ifndef CONFIG_SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#endif
-
#ifndef __ASSEMBLY__
unsigned long long get_qixis_addr(void);
#endif
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (640 * 1024)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
/*
* NOR Flash Timing Params
*/
#endif
#define CONFIG_SYS_FSL_CLK
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
+#endif
+
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x04
#define QIXIS_LBMAP_NAND 0x09
+#define QIXIS_LBMAP_QSPI 0x0f
#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RCW_SRC_NAND 0x107
+#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0x0)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x20010000
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x2000
#endif
+#endif
/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define I2C_MUX_CH_DEFAULT 0x8
/* SPI */
-#ifdef CONFIG_FSL_DSPI
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
#define CONFIG_SPI_FLASH
+
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM 4
+#endif
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI 0x1
+
#endif
/*
#endif
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#ifndef CONFIG_BOOTDELAY
-#endif
-
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_LOADADDR 0x80800000
#define CONFIG_SYS_TEXT_BASE 0x87800000
-#ifndef CONFIG_BOOTDELAY
-#endif
-
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
-/* override default CONFIG_BOOTDELAY */
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"machid=ffffffff\0" \
"fdt_high=0x87000000\0" \
"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
"bootm 0x08044000 - 0x08042000\0"
-#define CONFIG_AUTOBOOT
-
/*
* Command line configuration.
*/
* the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x10000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
+#define CONFIG_SYS_INIT_RAM_SIZE 0xA000 /* 40 KiB */
#else
#define CONFIG_SYS_INIT_RAM_ADDR 0x0
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
-/* FIXME: 40 KiB instead of 32 KiB ? */
-#define LOW_LEVEL_SRAM_STACK 0x00018000
+#define LOW_LEVEL_SRAM_STACK 0x0001A000
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#else
/* end of 32 KiB in sram */
"tftp_root=/\0" \
"nfs_root=/export\0" \
"mem_lpae=1\0" \
- "mem_reserve=512M\0" \
"addr_ubi=0x82000000\0" \
"addr_secdb_key=0xc000000\0" \
"name_kern=zImage\0" \
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
- "image=uImage\0" \
+ "image=zImage\0" \
+ "fdt_file=imx51-ts4800.dtb\0" \
+ "fdt_addr=0x90fe0000\0" \
"mmcdev=0\0" \
- "mmcpart=1\0" \
- "mmcargs=setenv bootargs root=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcpart=2\0" \
+ "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+ "mmcargs=setenv bootargs root=${mmcroot}\0" \
"addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs addtty; " \
- "bootm; "
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo ERR: cannot load FDT; " \
+ "fi; "
+
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
* Initialization, must be called once on start up, may be called
* repeatedly to change the speed and slave addresses.
*/
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
void i2c_init(int speed, int slaveaddr);
void i2c_init_board(void);
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
obj-$(CONFIG_EFI) += efi/
obj-$(CONFIG_EFI_LOADER) += efi_loader/
-obj-$(CONFIG_RSA) += rsa/
obj-$(CONFIG_LZMA) += lzma/
obj-$(CONFIG_LZO) += lzo/
obj-$(CONFIG_ZLIB) += zlib/
obj-y += crc16.o
obj-$(CONFIG_ERRNO_STR) += errno_str.o
obj-$(CONFIG_FIT) += fdtdec_common.o
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec.o
obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
obj-$(CONFIG_GZIP) += gunzip.o
obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o
obj-$(CONFIG_PHYSMEM) += physmem.o
obj-y += qsort.o
obj-y += rc4.o
-obj-$(CONFIG_SHA1) += sha1.o
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o
-obj-$(CONFIG_SHA256) += sha256.o
obj-$(CONFIG_TPM) += tpm.o
obj-$(CONFIG_RBTREE) += rbtree.o
obj-$(CONFIG_BITREVERSE) += bitrev.o
obj-y += list_sort.o
endif
+obj-$(CONFIG_$(SPL_)RSA) += rsa/
+obj-$(CONFIG_$(SPL_)SHA1) += sha1.o
+obj-$(CONFIG_$(SPL_)SHA256) += sha256.o
+
obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/
ifdef CONFIG_SPL_OF_CONTROL
obj-$(CONFIG_OF_LIBFDT) += libfdt/
option. The software based modular exponentiation is built into
mkimage irrespective of this option.
+config SPL_RSA
+ bool "Use RSA Library within SPL"
+ depends on RSA
+
if RSA
config RSA_SOFTWARE_EXP
bool "Enable driver for RSA Modular Exponentiation in software"
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o
+obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o
obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o
Usage
-----
-This tool takes one input file. (let's say 'recipe' file here.)
-The recipe describes the list of config options you want to move.
-Each line takes the form:
-<config_name> <type> <default>
-(the fields must be separated with whitespaces.)
-
-<config_name> is the name of config option.
-
-<type> is the type of the option. It must be one of bool, tristate,
-string, int, and hex.
-
-<default> is the default value of the option. It must be appropriate
-value corresponding to the option type. It must be either y or n for
-the bool type. Tristate options can also take m (although U-Boot has
-not supported the module feature).
-
-You can add two or more lines in the recipe file, so you can move
-multiple options at once.
-
-Let's say, for example, you want to move CONFIG_CMD_USB and
-CONFIG_SYS_TEXT_BASE.
-
-The type should be bool, hex, respectively. So, the recipe file
-should look like this:
-
- $ cat recipe
- CONFIG_CMD_USB bool n
- CONFIG_SYS_TEXT_BASE hex 0x00000000
-
-Next you must edit the Kconfig to add the menu entries for the configs
+First, you must edit the Kconfig to add the menu entries for the configs
you are moving.
-And then run this tool giving the file name of the recipe
+And then run this tool giving CONFIG names you want to move.
+For example, if you want to move CONFIG_CMD_USB and CONFIG_SYS_TEXT_BASE,
+simply type as follows:
- $ tools/moveconfig.py recipe
+ $ tools/moveconfig.py CONFIG_CMD_USB CONFIG_SYS_TEXT_BASE
-The tool walks through all the defconfig files to move the config
-options specified by the recipe file.
+The tool walks through all the defconfig files and move the given CONFIGs.
The log is also displayed on the terminal.
-Each line is printed in the format
-<defconfig_name> : <action>
+The log is printed for each defconfig as follows:
-<defconfig_name> is the name of the defconfig
-(without the suffix _defconfig).
+<defconfig_name>
+ <action1>
+ <action2>
+ <action3>
+ ...
-<action> shows what the tool did for that defconfig.
+<defconfig_name> is the name of the defconfig.
+
+<action*> shows what the tool did for that defconfig.
It looks like one of the followings:
- Move 'CONFIG_... '
This config option was moved to the defconfig
- - Default value 'CONFIG_...'. Do nothing.
- The value of this option is the same as default.
- We do not have to add it to the defconfig.
+ - CONFIG_... is not defined in Kconfig. Do nothing.
+ The entry for this CONFIG was not found in Kconfig.
+ There are two common cases:
+ - You forgot to create an entry for the CONFIG before running
+ this tool, or made a typo in a CONFIG passed to this tool.
+ - The entry was hidden due to unmet 'depends on'.
+ This is correct behavior.
- - 'CONFIG_...' already exists in Kconfig. Do nothing.
- This config option is already defined in Kconfig.
- We do not need/want to touch it.
+ - 'CONFIG_...' is the same as the define in Kconfig. Do nothing.
+ The define in the config header matched the one in Kconfig.
+ We do not need to touch it.
- Undefined. Do nothing.
This config option was not found in the config header.
Nothing to do.
- - Failed to process. Skip.
+ - Compiler is missing. Do nothing.
+ The compiler specified for this architecture was not found
+ in your PATH environment.
+ (If -e option is passed, the tool exits immediately.)
+
+ - Failed to process.
An error occurred during processing this defconfig. Skipped.
(If -e option is passed, the tool exits immediately on error.)
Just in case, please do 'git diff' to see what happened.
-How does it works?
-------------------
+How does it work?
+-----------------
This tool runs configuration and builds include/autoconf.mk for every
defconfig. The config options defined in Kconfig appear in the .config
file (unless they are hidden because of unmet dependency.)
On the other hand, the config options defined by board headers are seen
in include/autoconf.mk. The tool looks for the specified options in both
-of them to decide the appropriate action for the options. If the option
-is found in the .config or the value is the same as the specified default,
-the option does not need to be touched. If the option is found in
-include/autoconf.mk, but not in the .config, and the value is different
-from the default, the tools adds the option to the defconfig.
+of them to decide the appropriate action for the options. If the given
+config option is found in the .config, but its value does not match the
+one from the board header, the config option in the .config is replaced
+with the define in the board header. Then, the .config is synced by
+"make savedefconfig" and the defconfig is updated with it.
For faster processing, this tool handles multi-threading. It creates
separate build directories where the out-of-tree build is run. The
Specify a file containing a list of defconfigs to move
-n, --dry-run
- Peform a trial run that does not make any changes. It is useful to
+ Perform a trial run that does not make any changes. It is useful to
see what is going to happen before one actually runs it.
-e, --exit-on-error
Exit immediately if Make exits with a non-zero status while processing
a defconfig file.
+ -s, --force-sync
+ Do "make savedefconfig" forcibly for all the defconfig files.
+ If not specified, "make savedefconfig" only occurs for cases
+ where at least one CONFIG was moved.
+
-H, --headers-only
Only cleanup the headers; skip the defconfig processing
Specify the number of threads to run simultaneously. If not specified,
the number of threads is the same as the number of CPU cores.
+ -r, --git-ref
+ Specify the git ref to clone for building the autoconf.mk. If unspecified
+ use the CWD. This is useful for when changes to the Kconfig affect the
+ default values and you want to capture the state of the defconfig from
+ before that change was in effect. If in doubt, specify a ref pre-Kconfig
+ changes (use HEAD if Kconfig changes are not committed). Worst case it will
+ take a bit longer to run, but will always do the right thing.
+
-v, --verbose
Show any build errors as boards are built
"""
+import filecmp
import fnmatch
import multiprocessing
import optparse
STATE_SAVEDEFCONFIG = 3
ACTION_MOVE = 0
-ACTION_DEFAULT_VALUE = 1
-ACTION_ALREADY_EXIST = 2
-ACTION_UNDEFINED = 3
+ACTION_NO_ENTRY = 1
+ACTION_NO_CHANGE = 2
COLOR_BLACK = '0;30'
COLOR_RED = '0;31'
if not os.path.exists(f):
sys.exit('Please run at the top of source directory.')
+def check_clean_directory():
+ """Exit if the source tree is not clean."""
+ for f in ('.config', 'include/config'):
+ if os.path.exists(f):
+ sys.exit("source tree is not clean, please run 'make mrproper'")
+
def get_make_cmd():
"""Get the command name of GNU Make.
def color_text(color_enabled, color, string):
"""Return colored string."""
if color_enabled:
- return '\033[' + color + 'm' + string + '\033[0m'
+ # LF should not be surrounded by the escape sequence.
+ # Otherwise, additional whitespace or line-feed might be printed.
+ return '\n'.join([ '\033[' + color + 'm' + s + '\033[0m' if s else ''
+ for s in string.split('\n') ])
else:
return string
-def log_msg(color_enabled, color, defconfig, msg):
- """Return the formated line for the log."""
- return defconfig[:-len('_defconfig')].ljust(37) + ': ' + \
- color_text(color_enabled, color, msg) + '\n'
-
-def update_cross_compile():
+def update_cross_compile(color_enabled):
"""Update per-arch CROSS_COMPILE via environment variables
The default CROSS_COMPILE values are available
export CROSS_COMPILE_ARM=...
export CROSS_COMPILE_POWERPC=...
+
+ Then, this function checks if specified compilers really exist in your
+ PATH environment.
"""
archs = []
for arch in archs:
env = 'CROSS_COMPILE_' + arch.upper()
cross_compile = os.environ.get(env)
- if cross_compile:
- CROSS_COMPILE[arch] = cross_compile
+ if not cross_compile:
+ cross_compile = CROSS_COMPILE.get(arch, '')
+
+ for path in os.environ["PATH"].split(os.pathsep):
+ gcc_path = os.path.join(path, cross_compile + 'gcc')
+ if os.path.isfile(gcc_path) and os.access(gcc_path, os.X_OK):
+ break
+ else:
+ print >> sys.stderr, color_text(color_enabled, COLOR_YELLOW,
+ 'warning: %sgcc: not found in PATH. %s architecture boards will be skipped'
+ % (cross_compile, arch))
+ cross_compile = None
+
+ CROSS_COMPILE[arch] = cross_compile
def cleanup_one_header(header_path, patterns, dry_run):
"""Clean regex-matched lines away from a file.
if not i in matched:
f.write(line)
-def cleanup_headers(config_attrs, dry_run):
+def cleanup_headers(configs, dry_run):
"""Delete config defines from board headers.
Arguments:
- config_attrs: A list of dictionaris, each of them includes the name,
- the type, and the default value of the target config.
+ configs: A list of CONFIGs to remove.
dry_run: make no changes, but still display log.
"""
while True:
return
patterns = []
- for config_attr in config_attrs:
- config = config_attr['config']
+ for config in configs:
patterns.append(re.compile(r'#\s*define\s+%s\W' % config))
patterns.append(re.compile(r'#\s*undef\s+%s\W' % config))
patterns, dry_run)
### classes ###
+class Progress:
+
+ """Progress Indicator"""
+
+ def __init__(self, total):
+ """Create a new progress indicator.
+
+ Arguments:
+ total: A number of defconfig files to process.
+ """
+ self.current = 0
+ self.total = total
+
+ def inc(self):
+ """Increment the number of processed defconfig files."""
+
+ self.current += 1
+
+ def show(self):
+ """Display the progress."""
+ print ' %d defconfigs out of %d\r' % (self.current, self.total),
+ sys.stdout.flush()
+
class KconfigParser:
"""A parser of .config and include/autoconf.mk."""
re_arch = re.compile(r'CONFIG_SYS_ARCH="(.*)"')
re_cpu = re.compile(r'CONFIG_SYS_CPU="(.*)"')
- def __init__(self, config_attrs, options, build_dir):
+ def __init__(self, configs, options, build_dir):
"""Create a new parser.
Arguments:
- config_attrs: A list of dictionaris, each of them includes the name,
- the type, and the default value of the target config.
+ configs: A list of CONFIGs to move.
options: option flags.
build_dir: Build directory.
"""
- self.config_attrs = config_attrs
+ self.configs = configs
self.options = options
- self.build_dir = build_dir
+ self.dotconfig = os.path.join(build_dir, '.config')
+ self.autoconf = os.path.join(build_dir, 'include', 'autoconf.mk')
+ self.config_autoconf = os.path.join(build_dir, 'include', 'config',
+ 'auto.conf')
+ self.defconfig = os.path.join(build_dir, 'defconfig')
def get_cross_compile(self):
"""Parse .config file and return CROSS_COMPILE.
Returns:
A string storing the compiler prefix for the architecture.
+ Return a NULL string for architectures that do not require
+ compiler prefix (Sandbox and native build is the case).
+ Return None if the specified compiler is missing in your PATH.
+ Caller should distinguish '' and None.
"""
arch = ''
cpu = ''
- dotconfig = os.path.join(self.build_dir, '.config')
- for line in open(dotconfig):
+ for line in open(self.dotconfig):
m = self.re_arch.match(line)
if m:
arch = m.group(1)
if m:
cpu = m.group(1)
- assert arch, 'Error: arch is not defined in %s' % defconfig
+ if not arch:
+ return None
# fix-up for aarch64
if arch == 'arm' and cpu == 'armv8':
arch = 'aarch64'
- return CROSS_COMPILE.get(arch, '')
+ return CROSS_COMPILE.get(arch, None)
- def parse_one_config(self, config_attr, defconfig_lines, autoconf_lines):
+ def parse_one_config(self, config, dotconfig_lines, autoconf_lines):
"""Parse .config, defconfig, include/autoconf.mk for one config.
This function looks for the config options in the lines from
which action should be taken for this defconfig.
Arguments:
- config_attr: A dictionary including the name, the type,
- and the default value of the target config.
- defconfig_lines: lines from the original defconfig file.
+ config: CONFIG name to parse.
+ dotconfig_lines: lines from the .config file.
autoconf_lines: lines from the include/autoconf.mk file.
Returns:
A tupple of the action for this defconfig and the line
matched for the config.
"""
- config = config_attr['config']
not_set = '# %s is not set' % config
- if config_attr['type'] in ('bool', 'tristate') and \
- config_attr['default'] == 'n':
- default = not_set
- else:
- default = config + '=' + config_attr['default']
-
- for line in defconfig_lines:
+ for line in dotconfig_lines:
line = line.rstrip()
if line.startswith(config + '=') or line == not_set:
- return (ACTION_ALREADY_EXIST, line)
-
- if config_attr['type'] in ('bool', 'tristate'):
- value = not_set
+ old_val = line
+ break
else:
- value = '(undefined)'
+ return (ACTION_NO_ENTRY, config)
for line in autoconf_lines:
line = line.rstrip()
if line.startswith(config + '='):
- value = line
+ new_val = line
break
-
- if value == default:
- action = ACTION_DEFAULT_VALUE
- elif value == '(undefined)':
- action = ACTION_UNDEFINED
else:
- action = ACTION_MOVE
+ new_val = not_set
- return (action, value)
+ if old_val == new_val:
+ return (ACTION_NO_CHANGE, new_val)
- def update_defconfig(self, defconfig):
- """Parse files for the config options and update the defconfig.
+ # If this CONFIG is neither bool nor trisate
+ if old_val[-2:] != '=y' and old_val[-2:] != '=m' and old_val != not_set:
+ # tools/scripts/define2mk.sed changes '1' to 'y'.
+ # This is a problem if the CONFIG is int type.
+ # Check the type in Kconfig and handle it correctly.
+ if new_val[-2:] == '=y':
+ new_val = new_val[:-1] + '1'
- This function parses the given defconfig, the generated .config
- and include/autoconf.mk searching the target options.
- Move the config option(s) to the defconfig or do nothing if unneeded.
- Also, display the log to show what happened to this defconfig.
+ return (ACTION_MOVE, new_val)
+
+ def update_dotconfig(self):
+ """Parse files for the config options and update the .config.
+
+ This function parses the generated .config and include/autoconf.mk
+ searching the target options.
+ Move the config option(s) to the .config as needed.
Arguments:
defconfig: defconfig name.
+
+ Returns:
+ Return a tuple of (updated flag, log string).
+ The "updated flag" is True if the .config was updated, False
+ otherwise. The "log string" shows what happend to the .config.
"""
- defconfig_path = os.path.join('configs', defconfig)
- dotconfig_path = os.path.join(self.build_dir, '.config')
- autoconf_path = os.path.join(self.build_dir, 'include', 'autoconf.mk')
results = []
+ updated = False
- with open(defconfig_path) as f:
- defconfig_lines = f.readlines()
+ with open(self.dotconfig) as f:
+ dotconfig_lines = f.readlines()
- with open(autoconf_path) as f:
+ with open(self.autoconf) as f:
autoconf_lines = f.readlines()
- for config_attr in self.config_attrs:
- result = self.parse_one_config(config_attr, defconfig_lines,
+ for config in self.configs:
+ result = self.parse_one_config(config, dotconfig_lines,
autoconf_lines)
results.append(result)
if action == ACTION_MOVE:
actlog = "Move '%s'" % value
log_color = COLOR_LIGHT_GREEN
- elif action == ACTION_DEFAULT_VALUE:
- actlog = "Default value '%s'. Do nothing." % value
+ elif action == ACTION_NO_ENTRY:
+ actlog = "%s is not defined in Kconfig. Do nothing." % value
log_color = COLOR_LIGHT_BLUE
- elif action == ACTION_ALREADY_EXIST:
- actlog = "'%s' already defined in Kconfig. Do nothing." % value
+ elif action == ACTION_NO_CHANGE:
+ actlog = "'%s' is the same as the define in Kconfig. Do nothing." \
+ % value
log_color = COLOR_LIGHT_PURPLE
- elif action == ACTION_UNDEFINED:
- actlog = "Undefined. Do nothing."
- log_color = COLOR_DARK_GRAY
else:
sys.exit("Internal Error. This should not happen.")
- log += log_msg(self.options.color, log_color, defconfig, actlog)
+ log += color_text(self.options.color, log_color, actlog) + '\n'
- # Some threads are running in parallel.
- # Print log in one shot to not mix up logs from different threads.
- print log,
+ with open(self.dotconfig, 'a') as f:
+ for (action, value) in results:
+ if action == ACTION_MOVE:
+ f.write(value + '\n')
+ updated = True
+
+ self.results = results
+ os.remove(self.config_autoconf)
+ os.remove(self.autoconf)
+
+ return (updated, log)
+
+ def check_defconfig(self):
+ """Check the defconfig after savedefconfig
+
+ Returns:
+ Return additional log if moved CONFIGs were removed again by
+ 'make savedefconfig'.
+ """
+
+ log = ''
+
+ with open(self.defconfig) as f:
+ defconfig_lines = f.readlines()
- if not self.options.dry_run:
- with open(dotconfig_path, 'a') as f:
- for (action, value) in results:
- if action == ACTION_MOVE:
- f.write(value + '\n')
+ for (action, value) in self.results:
+ if action != ACTION_MOVE:
+ continue
+ if not value + '\n' in defconfig_lines:
+ log += color_text(self.options.color, COLOR_YELLOW,
+ "'%s' was removed by savedefconfig.\n" %
+ value)
- os.remove(os.path.join(self.build_dir, 'include', 'config', 'auto.conf'))
- os.remove(autoconf_path)
+ return log
class Slot:
for faster processing.
"""
- def __init__(self, config_attrs, options, devnull, make_cmd):
+ def __init__(self, configs, options, progress, devnull, make_cmd, reference_src_dir):
"""Create a new process slot.
Arguments:
- config_attrs: A list of dictionaris, each of them includes the name,
- the type, and the default value of the target config.
+ configs: A list of CONFIGs to move.
options: option flags.
+ progress: A progress indicator.
devnull: A file object of '/dev/null'.
make_cmd: command name of GNU Make.
+ reference_src_dir: Determine the true starting config state from this
+ source tree.
"""
self.options = options
+ self.progress = progress
self.build_dir = tempfile.mkdtemp()
self.devnull = devnull
self.make_cmd = (make_cmd, 'O=' + self.build_dir)
- self.parser = KconfigParser(config_attrs, options, self.build_dir)
+ self.reference_src_dir = reference_src_dir
+ self.parser = KconfigParser(configs, options, self.build_dir)
self.state = STATE_IDLE
self.failed_boards = []
This function makes sure the temporary directory is cleaned away
even if Python suddenly dies due to error. It should be done in here
- because it is guranteed the destructor is always invoked when the
+ because it is guaranteed the destructor is always invoked when the
instance of the class gets unreferenced.
If the subprocess is still running, wait until it finishes.
pass
shutil.rmtree(self.build_dir)
- def add(self, defconfig, num, total):
+ def add(self, defconfig):
"""Assign a new subprocess for defconfig and add it to the slot.
If the slot is vacant, create a new subprocess for processing the
"""
if self.state != STATE_IDLE:
return False
- cmd = list(self.make_cmd)
- cmd.append(defconfig)
- self.ps = subprocess.Popen(cmd, stdout=self.devnull,
- stderr=subprocess.PIPE)
+
self.defconfig = defconfig
- self.state = STATE_DEFCONFIG
- self.num = num
- self.total = total
+ self.log = ''
+ self.use_git_ref = True if self.options.git_ref else False
+ self.do_defconfig()
return True
def poll(self):
If the configuration is successfully finished, assign a new
subprocess to build include/autoconf.mk.
If include/autoconf.mk is generated, invoke the parser to
- parse the .config and the include/autoconf.mk, and then set the
- slot back to the idle state.
+ parse the .config and the include/autoconf.mk, moving
+ config options to the .config as needed.
+ If the .config was updated, run "make savedefconfig" to sync
+ it, update the original defconfig, and then set the slot back
+ to the idle state.
Returns:
Return True if the subprocess is terminated, False otherwise
return False
if self.ps.poll() != 0:
- errmsg = 'Failed to process.'
- errout = self.ps.stderr.read()
- if errout.find('gcc: command not found') != -1:
- errmsg = 'Compiler not found ('
- errmsg += color_text(self.options.color, COLOR_YELLOW,
- self.cross_compile)
- errmsg += color_text(self.options.color, COLOR_LIGHT_RED,
- ')')
- print >> sys.stderr, log_msg(self.options.color,
- COLOR_LIGHT_RED,
- self.defconfig,
- errmsg),
- if self.options.verbose:
- print >> sys.stderr, color_text(self.options.color,
- COLOR_LIGHT_CYAN, errout)
- if self.options.exit_on_error:
- sys.exit("Exit on error.")
+ self.handle_error()
+ elif self.state == STATE_DEFCONFIG:
+ if self.options.git_ref and not self.use_git_ref:
+ self.do_savedefconfig()
else:
- # If --exit-on-error flag is not set,
- # skip this board and continue.
- # Record the failed board.
- self.failed_boards.append(self.defconfig)
- self.state = STATE_IDLE
- return True
+ self.do_autoconf()
+ elif self.state == STATE_AUTOCONF:
+ if self.use_git_ref:
+ self.use_git_ref = False
+ self.do_defconfig()
+ else:
+ self.do_savedefconfig()
+ elif self.state == STATE_SAVEDEFCONFIG:
+ self.update_defconfig()
+ else:
+ sys.exit("Internal Error. This should not happen.")
- if self.state == STATE_AUTOCONF:
- self.parser.update_defconfig(self.defconfig)
+ return True if self.state == STATE_IDLE else False
- print ' %d defconfigs out of %d\r' % (self.num + 1, self.total),
- sys.stdout.flush()
+ def handle_error(self):
+ """Handle error cases."""
- """Save off the defconfig in a consistent way"""
- cmd = list(self.make_cmd)
- cmd.append('savedefconfig')
- self.ps = subprocess.Popen(cmd, stdout=self.devnull,
- stderr=subprocess.PIPE)
- self.state = STATE_SAVEDEFCONFIG
- return False
+ self.log += color_text(self.options.color, COLOR_LIGHT_RED,
+ "Failed to process.\n")
+ if self.options.verbose:
+ self.log += color_text(self.options.color, COLOR_LIGHT_CYAN,
+ self.ps.stderr.read())
+ self.finish(False)
- if self.state == STATE_SAVEDEFCONFIG:
- defconfig_path = os.path.join(self.build_dir, 'defconfig')
- shutil.move(defconfig_path,
- os.path.join('configs', self.defconfig))
- self.state = STATE_IDLE
- return True
+ def do_defconfig(self):
+ """Run 'make <board>_defconfig' to create the .config file."""
+
+ cmd = list(self.make_cmd)
+ cmd.append(self.defconfig)
+ if self.use_git_ref:
+ cmd.append('-C')
+ cmd.append(self.reference_src_dir)
+ self.ps = subprocess.Popen(cmd, stdout=self.devnull,
+ stderr=subprocess.PIPE)
+ self.state = STATE_DEFCONFIG
+
+ def do_autoconf(self):
+ """Run 'make include/config/auto.conf'."""
self.cross_compile = self.parser.get_cross_compile()
+ if self.cross_compile is None:
+ self.log += color_text(self.options.color, COLOR_YELLOW,
+ "Compiler is missing. Do nothing.\n")
+ self.finish(False)
+ return
+
cmd = list(self.make_cmd)
if self.cross_compile:
cmd.append('CROSS_COMPILE=%s' % self.cross_compile)
cmd.append('KCONFIG_IGNORE_DUPLICATES=1')
cmd.append('include/config/auto.conf')
- """This will be screen-scraped, so be sure the expected text will be
- returned consistently on every machine by setting LANG=C"""
+ if self.use_git_ref:
+ cmd.append('-C')
+ cmd.append(self.reference_src_dir)
self.ps = subprocess.Popen(cmd, stdout=self.devnull,
- env=dict(os.environ, LANG='C'),
stderr=subprocess.PIPE)
self.state = STATE_AUTOCONF
- return False
+
+ def do_savedefconfig(self):
+ """Update the .config and run 'make savedefconfig'."""
+
+ (updated, log) = self.parser.update_dotconfig()
+ self.log += log
+
+ if not self.options.force_sync and not updated:
+ self.finish(True)
+ return
+ if updated:
+ self.log += color_text(self.options.color, COLOR_LIGHT_GREEN,
+ "Syncing by savedefconfig...\n")
+ else:
+ self.log += "Syncing by savedefconfig (forced by option)...\n"
+
+ cmd = list(self.make_cmd)
+ cmd.append('savedefconfig')
+ self.ps = subprocess.Popen(cmd, stdout=self.devnull,
+ stderr=subprocess.PIPE)
+ self.state = STATE_SAVEDEFCONFIG
+
+ def update_defconfig(self):
+ """Update the input defconfig and go back to the idle state."""
+
+ self.log += self.parser.check_defconfig()
+ orig_defconfig = os.path.join('configs', self.defconfig)
+ new_defconfig = os.path.join(self.build_dir, 'defconfig')
+ updated = not filecmp.cmp(orig_defconfig, new_defconfig)
+
+ if updated:
+ self.log += color_text(self.options.color, COLOR_LIGHT_BLUE,
+ "defconfig was updated.\n")
+
+ if not self.options.dry_run and updated:
+ shutil.move(new_defconfig, orig_defconfig)
+ self.finish(True)
+
+ def finish(self, success):
+ """Display log along with progress and go to the idle state.
+
+ Arguments:
+ success: Should be True when the defconfig was processed
+ successfully, or False when it fails.
+ """
+ # output at least 30 characters to hide the "* defconfigs out of *".
+ log = self.defconfig.ljust(30) + '\n'
+
+ log += '\n'.join([ ' ' + s for s in self.log.split('\n') ])
+ # Some threads are running in parallel.
+ # Print log atomically to not mix up logs from different threads.
+ print >> (sys.stdout if success else sys.stderr), log
+
+ if not success:
+ if self.options.exit_on_error:
+ sys.exit("Exit on error.")
+ # If --exit-on-error flag is not set, skip this board and continue.
+ # Record the failed board.
+ self.failed_boards.append(self.defconfig)
+
+ self.progress.inc()
+ self.progress.show()
+ self.state = STATE_IDLE
def get_failed_boards(self):
"""Returns a list of failed boards (defconfigs) in this slot.
"""Controller of the array of subprocess slots."""
- def __init__(self, config_attrs, options):
+ def __init__(self, configs, options, progress, reference_src_dir):
"""Create a new slots controller.
Arguments:
- config_attrs: A list of dictionaris containing the name, the type,
- and the default value of the target CONFIG.
+ configs: A list of CONFIGs to move.
options: option flags.
+ progress: A progress indicator.
+ reference_src_dir: Determine the true starting config state from this
+ source tree.
"""
self.options = options
self.slots = []
devnull = get_devnull()
make_cmd = get_make_cmd()
for i in range(options.jobs):
- self.slots.append(Slot(config_attrs, options, devnull, make_cmd))
+ self.slots.append(Slot(configs, options, progress, devnull,
+ make_cmd, reference_src_dir))
- def add(self, defconfig, num, total):
+ def add(self, defconfig):
"""Add a new subprocess if a vacant slot is found.
Arguments:
Return True on success or False on failure
"""
for slot in self.slots:
- if slot.add(defconfig, num, total):
+ if slot.add(defconfig):
return True
return False
for board in failed_boards:
f.write(board + '\n')
-def move_config(config_attrs, options):
+class WorkDir:
+ def __init__(self):
+ """Create a new working directory."""
+ self.work_dir = tempfile.mkdtemp()
+
+ def __del__(self):
+ """Delete the working directory
+
+ This function makes sure the temporary directory is cleaned away
+ even if Python suddenly dies due to error. It should be done in here
+ because it is guaranteed the destructor is always invoked when the
+ instance of the class gets unreferenced.
+ """
+ shutil.rmtree(self.work_dir)
+
+ def get(self):
+ return self.work_dir
+
+def move_config(configs, options):
"""Move config options to defconfig files.
Arguments:
- config_attrs: A list of dictionaris, each of them includes the name,
- the type, and the default value of the target config.
+ configs: A list of CONFIGs to move.
options: option flags
"""
- if len(config_attrs) == 0:
- print 'Nothing to do. exit.'
- sys.exit(0)
-
- print 'Move the following CONFIG options (jobs: %d)' % options.jobs
- for config_attr in config_attrs:
- print ' %s (type: %s, default: %s)' % (config_attr['config'],
- config_attr['type'],
- config_attr['default'])
+ if len(configs) == 0:
+ if options.force_sync:
+ print 'No CONFIG is specified. You are probably syncing defconfigs.',
+ else:
+ print 'Neither CONFIG nor --force-sync is specified. Nothing will happen.',
+ else:
+ print 'Move ' + ', '.join(configs),
+ print '(jobs: %d)\n' % options.jobs
+
+ reference_src_dir = ''
+
+ if options.git_ref:
+ work_dir = WorkDir()
+ reference_src_dir = work_dir.get()
+ print "Cloning git repo to a separate work directory..."
+ subprocess.check_output(['git', 'clone', os.getcwd(), '.'],
+ cwd=reference_src_dir)
+ print "Checkout '%s' to build the original autoconf.mk." % \
+ subprocess.check_output(['git', 'rev-parse', '--short',
+ options.git_ref]).strip()
+ subprocess.check_output(['git', 'checkout', options.git_ref],
+ stderr=subprocess.STDOUT,
+ cwd=reference_src_dir)
if options.defconfigs:
defconfigs = [line.strip() for line in open(options.defconfigs)]
for filename in fnmatch.filter(filenames, '*_defconfig'):
defconfigs.append(os.path.join(dirpath, filename))
- slots = Slots(config_attrs, options)
+ progress = Progress(len(defconfigs))
+ slots = Slots(configs, options, progress, reference_src_dir)
# Main loop to process defconfig files:
# Add a new subprocess into a vacant slot.
# Sleep if there is no available slot.
- for i, defconfig in enumerate(defconfigs):
- while not slots.add(defconfig, i, len(defconfigs)):
+ for defconfig in defconfigs:
+ while not slots.add(defconfig):
while not slots.available():
# No available slot: sleep for a while
time.sleep(SLEEP_TIME)
print ''
slots.show_failed_boards()
-def bad_recipe(filename, linenum, msg):
- """Print error message with the file name and the line number and exit."""
- sys.exit("%s: line %d: error : " % (filename, linenum) + msg)
-
-def parse_recipe(filename):
- """Parse the recipe file and retrieve the config attributes.
-
- This function parses the given recipe file and gets the name,
- the type, and the default value of the target config options.
-
- Arguments:
- filename: path to file to be parsed.
- Returns:
- A list of dictionaris, each of them includes the name,
- the type, and the default value of the target config.
- """
- config_attrs = []
- linenum = 1
-
- for line in open(filename):
- tokens = line.split()
- if len(tokens) != 3:
- bad_recipe(filename, linenum,
- "%d fields in this line. Each line must contain 3 fields"
- % len(tokens))
-
- (config, type, default) = tokens
-
- # prefix the option name with CONFIG_ if missing
- if not config.startswith('CONFIG_'):
- config = 'CONFIG_' + config
-
- # sanity check of default values
- if type == 'bool':
- if not default in ('y', 'n'):
- bad_recipe(filename, linenum,
- "default for bool type must be either y or n")
- elif type == 'tristate':
- if not default in ('y', 'm', 'n'):
- bad_recipe(filename, linenum,
- "default for tristate type must be y, m, or n")
- elif type == 'string':
- if default[0] != '"' or default[-1] != '"':
- bad_recipe(filename, linenum,
- "default for string type must be surrounded by double-quotations")
- elif type == 'int':
- try:
- int(default)
- except:
- bad_recipe(filename, linenum,
- "type is int, but default value is not decimal")
- elif type == 'hex':
- if len(default) < 2 or default[:2] != '0x':
- bad_recipe(filename, linenum,
- "default for hex type must be prefixed with 0x")
- try:
- int(default, 16)
- except:
- bad_recipe(filename, linenum,
- "type is hex, but default value is not hexadecimal")
- else:
- bad_recipe(filename, linenum,
- "unsupported type '%s'. type must be one of bool, tristate, string, int, hex"
- % type)
-
- config_attrs.append({'config': config, 'type': type, 'default': default})
- linenum += 1
-
- return config_attrs
-
def main():
try:
cpu_count = multiprocessing.cpu_count()
parser.add_option('-e', '--exit-on-error', action='store_true',
default=False,
help='exit immediately on any error')
+ parser.add_option('-s', '--force-sync', action='store_true', default=False,
+ help='force sync by savedefconfig')
parser.add_option('-H', '--headers-only', dest='cleanup_headers_only',
action='store_true', default=False,
help='only cleanup the headers')
parser.add_option('-j', '--jobs', type='int', default=cpu_count,
help='the number of jobs to run simultaneously')
+ parser.add_option('-r', '--git-ref', type='string',
+ help='the git ref to clone for building the autoconf.mk')
parser.add_option('-v', '--verbose', action='store_true', default=False,
help='show any build errors as boards are built')
- parser.usage += ' recipe_file\n\n' + \
- 'The recipe_file should describe config options you want to move.\n' + \
- 'Each line should contain config_name, type, default_value\n\n' + \
- 'Example:\n' + \
- 'CONFIG_FOO bool n\n' + \
- 'CONFIG_BAR int 100\n' + \
- 'CONFIG_BAZ string "hello"\n'
+ parser.usage += ' CONFIG ...'
- (options, args) = parser.parse_args()
+ (options, configs) = parser.parse_args()
- if len(args) != 1:
+ if len(configs) == 0 and not options.force_sync:
parser.print_usage()
sys.exit(1)
- config_attrs = parse_recipe(args[0])
-
- update_cross_compile()
+ # prefix the option name with CONFIG_ if missing
+ configs = [ config if config.startswith('CONFIG_') else 'CONFIG_' + config
+ for config in configs ]
check_top_directory()
+ check_clean_directory()
+
+ update_cross_compile(options.color)
+
if not options.cleanup_headers_only:
- move_config(config_attrs, options)
+ move_config(configs, options)
- cleanup_headers(config_attrs, options.dry_run)
+ if configs:
+ cleanup_headers(configs, options.dry_run)
if __name__ == '__main__':
main()
s/=\(..*\)/="\1"/;
# but remove again from decimal numbers
s/="\([0-9][0-9]*\)"/=\1/;
+ # ... and from negative decimal numbers
+ s/="\(-[1-9][0-9]*\)"/=\1/;
# ... and from hex numbers
s/="\(0[Xx][0-9a-fA-F][0-9a-fA-F]*\)"/=\1/;
# ... and from configs defined from other configs
projects / oweals / u-boot.git / commitdiff