-----------------------------------
ANDROID AB
M: Igor Opaniuk <igor.opaniuk@gmail.com>
-R: Sam Protsenko <semen.protsenko@linaro.org>
+R: Sam Protsenko <joe.skb7@gmail.com>
S: Maintained
F: cmd/ab_select.c
F: common/android_ab.c
select SUPPORT_SPL
imply CMD_DM
+config ARCH_IMXRT
+ bool "NXP i.MXRT platform"
+ select CPU_V7M
+ select DM
+ select DM_SERIAL
+ select SUPPORT_SPL
+ imply CMD_DM
+
config ARCH_MX23
bool "NXP i.MX23 family"
select CPU_ARM926EJS
source "arch/arm/mach-imx/imx8m/Kconfig"
+source "arch/arm/mach-imx/imxrt/Kconfig"
+
source "arch/arm/mach-imx/mxs/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
libs-y += arch/arm/mach-imx/
endif
else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610))
libs-y += arch/arm/mach-imx/
endif
endif
void invalidate_dcache_all(void)
{
}
+
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+ enum dcache_option option)
+{
+}
+
#endif
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
imx8qm-rom7720-a1.dtb \
fsl-imx8qxp-ai_ml.dtb \
fsl-imx8qxp-colibri.dtb \
- fsl-imx8qxp-mek.dtb
+ fsl-imx8qxp-mek.dtb \
+ imx8-deneb.dtb \
+ imx8-giedi.dtb
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
imx8mq-evk.dtb \
imx8mp-evk.dtb
+dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
+
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \
r8a7790-stout-u-boot.dtb \
k3-j721e-r5-common-proc-board.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7622-rfb.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
+ mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
reg = <0x0 0x5a800000 0x0 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&clk IMX8QXP_I2C0_CLK>;
- clock-names = "per";
+ clocks = <&clk IMX8QXP_I2C0_CLK>,
+ <&clk IMX8QXP_I2C0_IPG_CLK>;
+ clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c0>;
reg = <0x0 0x5a820000 0x0 0x4000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&clk IMX8QXP_I2C2_CLK>;
- clock-names = "per";
+ clocks = <&clk IMX8QXP_I2C2_CLK>,
+ <&clk IMX8QXP_I2C2_IPG_CLK>;
+ clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
+ broken-cd;
keep-power-in-suspend;
wakeup-source;
status = "okay";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Siemens AG
+ */
+
+#include "imx8qxp-capricorn.dtsi"
+
+/ {
+ model = "Siemens Deneb";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Siemens AG
+ */
+
+#include "imx8qxp-capricorn.dtsi"
+
+/ {
+ model = "Siemens Giedi";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Siemens AG
+ */
+
+&{/imx8qx-pm} {
+
+ u-boot,dm-spl;
+};
+
+&mu {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pd_lsio {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+ u-boot,dm-spl;
+};
+
+&pd_dma {
+ u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+ u-boot,dm-spl;
+};
+
+&pd_dma_lpuart2 {
+ u-boot,dm-spl;
+};
+
+&pd_conn {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+ u-boot,dm-spl;
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpio6 {
+ u-boot,dm-spl;
+};
+
+&gpio7 {
+ u-boot,dm-spl;
+};
+
+&lpuart0 {
+ u-boot,dm-spl;
+};
+
+&lpuart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ *
+ * Copyright 2019 Siemens AG
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+#include "imx8qxp-capricorn-u-boot.dtsi"
+
+/ {
+ model = "Siemens Giedi";
+ compatible = "siemens,capricorn", "fsl,imx8qxp";
+
+ chosen {
+ bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
+ stdout-path = &lpuart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ run {
+ label = "run";
+ gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ flt {
+ label = "flt";
+ gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ svc {
+ label = "svc";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ com1_tx {
+ label = "com1-tx";
+ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ com1_rx {
+ label = "com1-rx";
+ gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ com2_tx {
+ label = "com2-tx";
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ com2_rx {
+ label = "com2-rx";
+ gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ cloud {
+ label = "cloud";
+ gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ wlan {
+ label = "wlan";
+ gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ dbg1 {
+ label = "dbg1";
+ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ dbg2 {
+ label = "dbg2";
+ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ dbg3 {
+ label = "dbg3";
+ gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ dbg4 {
+ label = "dbg4";
+ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ muxcgrp: imx8qxp-som {
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021
+ SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021
+ SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021
+ SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021
+ SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021
+ SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021
+ SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021
+ SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021
+ SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021
+ SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021
+ SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021
+ SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
+ SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021
+ >;
+ };
+
+ pinctrl_lpi2c0: lpi2c0grp {
+ fsl,pins = <
+ SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020
+ SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x0C000020
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x0C000020
+ SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x0C000020
+ >;
+ };
+
+ pinctrl_lpuart2: lpuart2grp {
+ fsl,pins = <
+ SC_P_UART2_RX_ADMA_UART2_RX 0x06000020
+ SC_P_UART2_TX_ADMA_UART2_TX 0x06000020
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
+ SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
+ SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
+ SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
+ SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
+ SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
+ SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
+ SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021
+ //SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
+ SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021
+ >;
+ };
+
+ pinctrl_fec2: fec2grp {
+ fsl,pins = <
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
+ SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
+
+ SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060
+ SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060
+
+ SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060
+ SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
+ SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
+ SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060
+ SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
+ SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
+ SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
+ SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */
+ >;
+ };
+ };
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c0>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ status = "okay";
+};
+
+&lpuart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart2>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ clock-frequency=<52000000>;
+ no-1-8-v;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&fec1 {
+ status ="disabled";
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec2>;
+ phy-mode = "rmii";
+
+ phy-handle = <ðphy1>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/ {
+ chosen {
+ u-boot,dm-spl;
+ };
+};
+
+&lpuart1 { /* console */
+ u-boot,dm-spl;
+};
+
+&semc {
+ bank1: bank@0 {
+ u-boot,dm-spl;
+ };
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+
+ imxrt1050-evk {
+ u-boot,dm-spl;
+ pinctrl_lpuart1: lpuart1grp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_semc: semcgrp {
+ u-boot,dm-spl;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/dts-v1/;
+#include "imxrt1050.dtsi"
+#include "imxrt1050-evk-u-boot.dtsi"
+#include <dt-bindings/pinctrl/pins-imxrt1050.h>
+
+/ {
+ model = "NXP IMXRT1050-evk board";
+ compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
+
+ chosen {
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x80000000 0x2000000>;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&semc {
+ /*
+ * Memory configuration from sdram datasheet IS42S16160J-6BLI
+ */
+ fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
+ MUX_CSX0_SDRAM_CS1
+ 0
+ 0
+ 0
+ 0>;
+ fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
+ BL_8
+ COL_9BITS
+ CL_3>;
+ fsl,sdram-timing = /bits/ 8 <0x2
+ 0x2
+ 0x9
+ 0x1
+ 0x5
+ 0x6
+
+ 0x20
+ 0x09
+ 0x01
+ 0x00
+
+ 0x04
+ 0x0A
+ 0x21
+ 0x50>;
+
+ bank1: bank@0 {
+ fsl,base-address = <0x80000000>;
+ fsl,memory-size = <MEM_SIZE_32M>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+
+ imxrt1050-evk {
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
+ 0xf1
+ MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
+ 0xf1
+ >;
+ };
+
+ pinctrl_semc: semcgrp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
+ 0xf1 /* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
+ 0xf1 /* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
+ 0xf1 /* SEMC_D2 */
+ MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
+ 0xf1 /* SEMC_D3 */
+ MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
+ 0xf1 /* SEMC_D4 */
+ MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
+ 0xf1 /* SEMC_D5 */
+ MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
+ 0xf1 /* SEMC_D6 */
+ MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
+ 0xf1 /* SEMC_D7 */
+ MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
+ 0xf1 /* SEMC_DM0 */
+ MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
+ 0xf1 /* SEMC_A0 */
+ MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
+ 0xf1 /* SEMC_A1 */
+ MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
+ 0xf1 /* SEMC_A2 */
+ MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
+ 0xf1 /* SEMC_A3 */
+ MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
+ 0xf1 /* SEMC_A4 */
+ MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
+ 0xf1 /* SEMC_A5 */
+ MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
+ 0xf1 /* SEMC_A6 */
+ MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
+ 0xf1 /* SEMC_A7 */
+ MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
+ 0xf1 /* SEMC_A8 */
+ MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
+ 0xf1 /* SEMC_A9 */
+ MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
+ 0xf1 /* SEMC_A11 */
+ MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
+ 0xf1 /* SEMC_A12 */
+ MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
+ 0xf1 /* SEMC_BA0 */
+ MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
+ 0xf1 /* SEMC_BA1 */
+ MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
+ 0xf1 /* SEMC_A10 */
+ MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
+ 0xf1 /* SEMC_CAS */
+ MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
+ 0xf1 /* SEMC_RAS */
+ MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
+ 0xf1 /* SEMC_CLK */
+ MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
+ 0xf1 /* SEMC_CKE */
+ MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
+ 0xf1 /* SEMC_WE */
+ MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
+ 0xf1 /* SEMC_CS0 */
+ MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
+ 0xf1 /* SEMC_D8 */
+ MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
+ 0xf1 /* SEMC_D9 */
+ MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
+ 0xf1 /* SEMC_D10 */
+ MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
+ 0xf1 /* SEMC_D11 */
+ MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
+ 0xf1 /* SEMC_D12 */
+ MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
+ 0xf1 /* SEMC_D13 */
+ MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
+ 0xf1 /* SEMC_D14 */
+ MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
+ 0xf1 /* SEMC_D15 */
+ MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
+ 0xf1 /* SEMC_DM1 */
+ MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
+ (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
+ 0x1B000
+ MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
+ 0xB069
+ MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
+ 0x17061
+ MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
+ 0x17061
+ >;
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ pinctrl-2 = <&pinctrl_usdhc0>;
+ pinctrl-3 = <&pinctrl_usdhc0>;
+ status = "okay";
+
+ cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt1050-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/memory/imxrt-sdram.h>
+
+/ {
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ mmc0 = &usdhc1;
+ serial0 = &lpuart1;
+ };
+
+ clocks {
+ u-boot,dm-spl;
+
+ osc {
+ u-boot,dm-spl;
+ compatible = "fsl,imx-osc", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ semc: semc@402f0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-semc";
+ reg = <0x402f0000 0x4000>;
+ clocks = <&clks IMXRT1050_CLK_SEMC>;
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ lpuart1: serial@40184000 {
+ compatible = "fsl,imxrt-lpuart";
+ reg = <0x40184000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMXRT1050_CLK_LPUART1>;
+ clock-names = "per";
+ status = "disabled";
+ };
+
+ iomuxc: iomuxc@401f8000 {
+ compatible = "fsl,imxrt-iomuxc";
+ reg = <0x401f8000 0x4000>;
+ fsl,mux_mask = <0x7>;
+ };
+
+ clks: ccm@400fc000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt1050-ccm";
+ reg = <0x400fc000 0x4000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ };
+
+ usdhc1: usdhc@402c0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-usdhc";
+ reg = <0x402c0000 0x10000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMXRT1050_CLK_USDHC1>;
+ clock-names = "per";
+ bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@401b8000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401b8000 0x4000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@401bc000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401bc000 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@401c0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401c0000 0x4000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@401c4000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x401c4000 0x4000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@400c0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+ reg = <0x400c0000 0x4000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7622.dtsi"
+#include "mt7622-u-boot.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "mt7622-rfb";
+ compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ aliases {
+ spi0 = &snfi;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+
+&pinctrl {
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ snor_pins: snor-pins {
+ mux {
+ function = "flash";
+ groups = "spi_nor";
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_tx_rx" ;
+ };
+ };
+
+ watchdog_pins: watchdog-default {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "emmc";
+ groups = "emmc";
+ };
+
+ /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+ * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+ * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+ */
+ conf-cmd-dat {
+ pins = "NDL0", "NDL1", "NDL2",
+ "NDL3", "NDL4", "NDL5",
+ "NDL6", "NDL7", "NRB";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "NCLE";
+ bias-pull-down;
+ };
+
+ };
+
+ mmc1_pins_default: mmc1default {
+ mux {
+ function = "sd";
+ groups = "sd_0";
+ };
+ /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+ * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+ * DAT2, DAT3, CMD, CLK for SD respectively.
+ */
+ conf-cmd-data {
+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+ "I2S2_IN","I2S4_OUT";
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ conf-clk {
+ pins = "I2S3_OUT";
+ drive-strength = <12>;
+ bias-pull-down;
+ };
+ conf-cd {
+ pins = "TXD3";
+ bias-pull-up;
+ };
+
+ };
+};
+
+&snfi {
+ pinctrl-names = "default", "snfi";
+ pinctrl-0 = <&snor_pins>;
+ pinctrl-1 = <&snfi_pins>;
+ status = "okay";
+
+ spi-flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ status = "okay";
+ bus-width = <8>;
+ max-frequency = <50000000>;
+ cap-sd-highspeed;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_3p3v>;
+ non-removable;
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+ status = "okay";
+ bus-width = <4>;
+ max-frequency = <50000000>;
+ cap-sd-highspeed;
+ r_smpl = <1>;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_3p3v>;
+};
+
+&watchdog {
+ pinctrl-names = "default";
+ pinctrl-0 = <&watchdog_pins>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+&topckgen {
+ u-boot,dm-pre-reloc;
+};
+
+&pericfg {
+ u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+ u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&snfi {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7622-clk.h>
+
+/ {
+ compatible = "mediatek,mt7622";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clock-frequency = <1300000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ clock-frequency = <1300000000>;
+ };
+ };
+
+ snfi: snfi@1100d000 {
+ compatible = "mediatek,mtk-snfi-spi";
+ reg = <0x1100d000 0x2000>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
+ <&topckgen CLK_TOP_NFI_INFRA_SEL>;
+
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
+ <&topckgen CLK_TOP_UNIVPLL2_D8>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ timer0: timer@10004000 {
+ compatible = "mediatek,timer";
+ reg = <0x10004000 0x80>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&system_clk>;
+ clock-names = "system-clk";
+ };
+
+ system_clk: dummy13m {
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ #clock-cells = <0>;
+ };
+
+ infracfg: infracfg@10000000 {
+ compatible = "mediatek,mt7622-infracfg",
+ "syscon";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pericfg: pericfg@10002000 {
+ compatible = "mediatek,mt7622-pericfg", "syscon";
+ reg = <0x10002000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt7622-scpsys",
+ "syscon";
+ #power-domain-cells = <1>;
+ reg = <0x10006000 0x1000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ infracfg = <&infracfg>;
+ clocks = <&topckgen CLK_TOP_HIF_SEL>;
+ clock-names = "hif_sel";
+ };
+
+ sysirq: interrupt-controller@10200620 {
+ compatible = "mediatek,sysirq";
+ reg = <0x10200620 0x20>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ };
+
+ apmixedsys: apmixedsys@10209000 {
+ compatible = "mediatek,mt7622-apmixedsys";
+ reg = <0x10209000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen: topckgen@10210000 {
+ compatible = "mediatek,mt7622-topckgen";
+ reg = <0x10210000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pinctrl: pinctrl@10211000 {
+ compatible = "mediatek,mt7622-pinctrl";
+ reg = <0x10211000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ watchdog: watchdog@10212000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10212000 0x800>;
+ };
+
+ gic: interrupt-controller@10300000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x10310000 0x1000>,
+ <0x10320000 0x1000>,
+ <0x10340000 0x2000>,
+ <0x10360000 0x2000>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11002000 0x400>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART0_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt7622-mmc";
+ reg = <0x11230000 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
+ <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt7622-mmc";
+ reg = <0x11240000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+&topckgen {
+ u-boot,dm-pre-reloc;
+};
+
+&topckgen {
+ u-boot,dm-pre-reloc;
+};
+
+&pericfg {
+ u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+ u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
compatible = "mediatek,mt7623-topckgen";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
infracfg: syscon@10001000 {
compatible = "mediatek,mt7623-infracfg", "syscon";
reg = <0x10001000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
pericfg: syscon@10003000 {
compatible = "mediatek,mt7623-pericfg", "syscon";
reg = <0x10003000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
pinctrl: pinctrl@10005000 {
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>;
clock-names = "system-clk";
- u-boot,dm-pre-reloc;
};
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt7623-apmixedsys";
reg = <0x10209000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
gic: interrupt-controller@10211000 {
<&pericfg CLK_PERI_UART2>;
clock-names = "baud", "bus";
status = "disabled";
- u-boot,dm-pre-reloc;
};
uart3: serial@11005000 {
/dts-v1/;
#include "mt7623.dtsi"
+#include "mt7623-u-boot.dtsi"
/ {
model = "Bananapi BPI-R2";
#endif
};
};
+
+&infracfg {
+ u-boot,dm-pre-reloc;
+};
+
+&pericfg {
+ u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+ u-boot,dm-pre-reloc;
+};
+
+&mcucfg {
+ u-boot,dm-pre-reloc;
+};
+
+&dramc {
+ u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+ u-boot,dm-pre-reloc;
+};
+
+&topckgen {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&snfi {
+ u-boot,dm-pre-reloc;
+};
/dts-v1/;
#include "mt7629.dtsi"
+#include "mt7629-rfb-u-boot.dtsi"
/ {
model = "MediaTek MT7629 RFB";
compatible = "mediatek,mt7629-infracfg", "syscon";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
pericfg: syscon@10002000 {
compatible = "mediatek,mt7629-pericfg", "syscon";
reg = <0x10002000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
timer0: timer@10004000 {
clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
<&topckgen CLK_TOP_10M_SEL>;
clock-names = "mux", "src";
- u-boot,dm-pre-reloc;
};
scpsys: scpsys@10006000 {
compatible = "mediatek,mt7629-mcucfg", "syscon";
reg = <0x10200000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
sysirq: interrupt-controller@10200a80 {
<&topckgen CLK_TOP_MEM_SEL>,
<&topckgen CLK_TOP_DMPLL>;
clock-names = "phy", "phy_mux", "mem", "mem_mux";
- u-boot,dm-pre-reloc;
};
apmixedsys: clock-controller@10209000 {
compatible = "mediatek,mt7629-apmixedsys";
reg = <0x10209000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
topckgen: clock-controller@10210000 {
compatible = "mediatek,mt7629-topckgen";
reg = <0x10210000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
watchdog: watchdog@10212000 {
status = "disabled";
assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
- u-boot,dm-pre-reloc;
};
uart1: serial@11003000 {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
};
ethsys: syscon@1b000000 {
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ *
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8512.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "MT8512 BM1 EMMC";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x20000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&pinctrl {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_rxd_txd";
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ *
+ */
+
+#include <dt-bindings/clock/mt8512-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt8512";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0xc000000 0x40000>, /* GICD */
+ <0xc080000 0x200000>; /* GICR */
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ topckgen: clock-controller@10000000 {
+ compatible = "mediatek,mt8512-topckgen";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen_cg: clock-controller-cg@10000000 {
+ compatible = "mediatek,mt8512-topckgen-cg";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: clock-controller@10001000 {
+ compatible = "mediatek,mt8512-infracfg";
+ reg = <0x10001000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pinctrl: pinctrl@10005000 {
+ compatible = "mediatek,mt8512-pinctrl";
+ reg = <0x10005000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ watchdog0: watchdog@10007000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10007000 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>;
+ #reset-cells = <1>;
+ status = "disabled";
+ timeout-sec = <60>;
+ reset-on-timeout;
+ };
+
+ timer0: apxgpt@10008000 {
+ compatible = "mediatek,timer";
+ reg = <0x10008000 0x1000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYS_26M_D2>,
+ <&topckgen CLK_TOP_CLK32K>,
+ <&infracfg CLK_INFRA_APXGPT>;
+ clock-names = "clk13m",
+ "clk32k",
+ "bus";
+ };
+
+ apmixedsys: clock-controller@1000c000 {
+ compatible = "mediatek,mt8512-apmixedsys";
+ reg = <0x1000c000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x10200a80 0x50>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11002000 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_CLK26M>,
+ <&infracfg CLK_INFRA_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8512-mmc";
+ reg = <0x11230000 0x1000>,
+ <0x11cd0000 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&infracfg CLK_INFRA_MSDC0>,
+ <&infracfg CLK_INFRA_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+};
\ No newline at end of file
--- /dev/null
+#include <config.h>
+
+#include "tegra-u-boot.dtsi"
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#endif /* __ASM_ARCH_CLOCK_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/* GPIO registers */
+struct gpio_regs {
+ u32 gpio_dr; /* data */
+ u32 gpio_dir; /* direction */
+ u32 gpio_psr; /* pad satus */
+};
+#endif
+
+#endif /* __ASM_ARCH_GPIO_H__ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define GPIO1_BASE_ADDR 0x401B8000
+#define GPIO2_BASE_ADDR 0x401BC000
+#define GPIO3_BASE_ADDR 0x401C0000
+#define GPIO4_BASE_ADDR 0x401C4000
+#define GPIO5_BASE_ADDR 0x400C0000
+
+#define ANATOP_BASE_ADDR 0x400d8000
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef _ASM_ARCH_IMXRT_H
+#define _ASM_ARCH_IMXRT_H
+
+#endif /* _ASM_ARCH_IMXRT_H */
+
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
+#include <asm/mach-imx/sys_proto.h>
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
obj-$(CONFIG_GPT_TIMER) += timer.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt))
obj-y += misc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
+obj-$(CONFIG_ARCH_IMXRT) += imxrt/
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
select BOARD_LATE_INIT
select IMX8QXP
+config TARGET_DENEB
+ bool "Support i.MX8QXP Capricorn Deneb board"
+ select BOARD_LATE_INIT
+ select IMX8QXP
+
+config TARGET_GIEDI
+ bool "Support i.MX8QXP Capricorn Giedi board"
+ select BOARD_LATE_INIT
+ select IMX8QXP
+
config TARGET_IMX8QM_MEK
bool "Support i.MX8QM MEK board"
select BOARD_LATE_INIT
source "board/advantech/imx8qm_rom7720_a1/Kconfig"
source "board/toradex/apalis-imx8/Kconfig"
source "board/toradex/colibri-imx8x/Kconfig"
+source "board/siemens/capricorn/Kconfig"
endif
--- /dev/null
+if ARCH_IMXRT
+
+config IMXRT
+ bool
+
+config IMXRT1050
+ bool
+ select IMXRT
+
+config SYS_SOC
+ default "imxrt"
+
+choice
+ prompt "NXP i.MXRT board select"
+ optional
+
+config TARGET_IMXRT1050_EVK
+ bool "Support imxrt1050 EVK board"
+ select IMXRT1050
+
+endchoice
+
+source "board/freescale/imxrt1050-evk/Kconfig"
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+#
+
+obj-y := soc.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7_mpu.h>
+
+int arch_cpu_init(void)
+{
+ int i;
+
+ struct mpu_region_config imxrt1050_region_config[] = {
+ { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
+ STRONG_ORDER, REGION_4GB },
+ { PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, (ffs(PHYS_SDRAM_SIZE) - 2) },
+ { DMAMEM_BASE,
+ REGION_2, XN_DIS, PRIV_RW_USR_RW,
+ STRONG_ORDER, (ffs(DMAMEM_SZ_ALL) - 2) },
+ };
+
+ /*
+ * Configure the memory protection unit (MPU) to allow full access to
+ * the whole 4GB address space.
+ */
+ disable_mpu();
+ for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++)
+ mpu_config(&imxrt1050_region_config[i]);
+ enable_mpu();
+
+ return 0;
+}
config SYS_VENDOR
default "mediatek"
+config MT8512
+ bool "MediaTek MT8512 SoC"
+ default n
+
choice
prompt "MediaTek board select"
+config TARGET_MT7622
+ bool "MediaTek MT7622 SoC"
+ select ARM64
+ help
+ The MediaTek MT7622 is a ARM64-based SoC with a dual-core Cortex-A53.
+ including UART, SPI, USB3.0, SD and MMC cards, NAND, SNFI, PWM, PCIe,
+ Gigabit Ethernet, I2C, built-in Wi-Fi, and PCIe.
+
config TARGET_MT7623
bool "MediaTek MT7623 SoC"
select CPU_V7A
including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
+config TARGET_MT8512
+ bool "MediaTek MT8512 M1 Board"
+ select ARM64
+ select MT8512
+ help
+ The MediaTek MT8512 is a ARM64-based SoC with a quad-core Cortex-A53.
+ including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
+ Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
+ chip and several DDR3 and DDR4 options.
+
config TARGET_MT8516
bool "MediaTek MT8516 SoC"
select ARM64
endchoice
+source "board/mediatek/mt7622/Kconfig"
source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
+source "board/mediatek/mt8512/Kconfig"
source "board/mediatek/mt8518/Kconfig"
source "board/mediatek/pumpkin/Kconfig"
obj-y += cpu.o
obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_MT8512) += mt8512/
+obj-$(CONFIG_TARGET_MT7622) += mt7622/
obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/armv8/mmu.h>
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT7622\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+ return fdtdec_setup_mem_size_base();
+
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+static struct mm_region mt7622_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+struct mm_region *mem_map = mt7622_mem_map;
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Configuration for MediaTek MT8512 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <wdt.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <dt-bindings/clock/mt8512-clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ /* limit stack below tee reserve memory */
+ return gd->ram_size - 6 * SZ_1M;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = get_effective_memsize();
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ struct udevice *watchdog_dev = NULL;
+
+ if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev))
+ if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev))
+ psci_system_reset();
+
+ wdt_expire_now(watchdog_dev, 0);
+}
+
+int print_cpuinfo(void)
+{
+ debug("CPU: MediaTek MT8512\n");
+ return 0;
+}
+
+static struct mm_region mt8512_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt8512_mem_map;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: input argument
+ * x4: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+.global armv8_el2_to_aarch32
+armv8_el2_to_aarch32:
+ mov x3, x2
+ mov x2, x1
+ mov x1, x4
+ mov x4, #0
+ /* Define in src\bsp\trustzone\atf\v1.2\ */
+ /* mt8xxx\plat\mediatek\common\sip_svc.h */
+ /* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/
+ ldr x0, =0xC2000200
+ SMC #0
+ ret
$ git clone https://source.codeaurora.org/external/imx/imx-atf
$ cd imx-atf/
-$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2
-$ make PLAT=imx8qxp bl31
+$ git checkout origin/imx_4.19.35_1.1.0 -b imx_4.19.35_1.1.0
+$ make PLAT=imx8qx bl31
Get scfw_tcm.bin and ahab-container.img
==============================
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-0.7.bin
-$ chmod +x imx-sc-firmware-0.7.bin
-$ ./imx-sc-firmware-0.7.bin
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin
-$ chmod +x firmware-imx-7.6.bin
-$ ./firmware-imx-7.6.bin
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.2.7.1.bin
+$ chmod +x imx-sc-firmware-1.2.7.1.bin
+$ ./imx-sc-firmware-1.2.7.1.bin
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-2.3.1.bin
+$ chmod +x imx-seco-2.3.1.bin
+$ ./imx-seco-2.3.1.bin
Copy the following binaries to U-Boot folder:
-$ cp imx-atf/build/imx8qxp/release/bl31.bin .
-$ cp u-boot/u-boot.bin .
-
-Copy the following firmwares U-Boot folder :
-
-$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
-$ cp imx-sc-firmware-0.7/mx8qx-mek-scfw-tcm.bin .
+$ cp imx-atf/build/imx8qx/release/bl31.bin .
+$ cp imx-seco-2.3.1/firmware/seco/mx8qx-ahab-container.img ./ahab-container.img
+$ cp imx-sc-firmware-1.2.7.1/mx8qx-mek-scfw-tcm.bin .
Build U-Boot
============
--- /dev/null
+if TARGET_IMXRT1050_EVK
+
+config SYS_BOARD
+ string
+ default "imxrt1050-evk"
+
+config SYS_VENDOR
+ string
+ default "freescale"
+
+config SYS_SOC
+ string
+ default "imxrt1050"
+
+config SYS_CONFIG_NAME
+ string
+ default "imxrt1050-evk"
+
+config IMX_CONFIG
+ default "board/freescale/imxrt1050-evk/imximage.cfg"
+
+endif
--- /dev/null
+IMXRT1050 EVALUATION KIT
+M: Giulio Benetti <giulio.benetti@benettiengineering.com>
+S: Maintained
+F: board/freescale/imxrt1050-evk
+F: include/configs/imxrt1050-evk.h
+F: configs/imxrt1050-evk_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+
+obj-y := imxrt1050-evk.o
--- /dev/null
+How to use U-Boot on NXP i.MXRT1050 EVK
+-----------------------------------------------
+
+- Build U-Boot for i.MXRT1050 EVK:
+
+$ make mrproper
+$ make imxrt1050-evk_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/sdb bs=1k seek=128; sync
+
+- Jumper settings:
+
+SW7: 1 0 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Connect the USB cable between the EVK and the PC for the console.
+(The USB console connector is the one close the ethernet connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Set all FlexRAM as OCRAM(01b) */
+DATA 4 0x400AC044 0x55555555
+/* Use FLEXRAM_BANK_CFG to config FlexRAM */
+SET_BIT 4 0x400AC040 0x4
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SUPPORT_SPL
+ int rv;
+ struct udevice *dev;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+ }
+
+#endif
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ debug("SPL: booting kernel\n");
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+ struct udevice *dev;
+ int rv;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv)
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+}
+
+void spl_board_init(void)
+{
+ spl_dram_init();
+ preloader_console_init();
+ arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+#endif
+
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ return 0;
+}
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- /* VSELECT */
- MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- /* CD */
- MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* RST_B */
- MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-/*
- * mx6ul_14x14_evk board default supports sd card. If want to use
- * EMMC, need to do board rework for sd2.
- * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
- * emmc, need to define this macro.
- */
-#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
-static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- /*
- * RST_B
- */
- MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-#else
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-/*
- * The evk board uses DAT3 to detect CD card plugin,
- * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
- */
-static iomux_v3_cfg_t const usdhc2_cd_pad =
- MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
-
-static iomux_v3_cfg_t const usdhc2_dat3_pad =
- MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
- MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
-#endif
static void setup_iomux_uart(void)
{
}
#endif
-#ifdef CONFIG_FSL_ESDHC_IMX
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC1_BASE_ADDR, 0, 4},
-#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
- {USDHC2_BASE_ADDR, 0, 8},
-#else
- {USDHC2_BASE_ADDR, 0, 4},
-#endif
+#ifdef CONFIG_SPL_BUILD
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
-#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
-#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
-#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC2_BASE_ADDR, 0, 4},
+};
int board_mmc_getcd(struct mmc *mmc)
{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- ret = !gpio_get_value(USDHC1_CD_GPIO);
- break;
- case USDHC2_BASE_ADDR:
-#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
- ret = 1;
-#else
- imx_iomux_v3_setup_pad(usdhc2_cd_pad);
- gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
- gpio_direction_input(USDHC2_CD_GPIO);
-
- /*
- * Since it is the DAT3 pin, this pin is pulled to
- * low voltage if no card
- */
- ret = gpio_get_value(USDHC2_CD_GPIO);
-
- imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
-#endif
- break;
- }
-
- return ret;
+ return 1;
}
int board_mmc_init(bd_t *bis)
{
- int i, ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 USDHC1
- * mmc1 USDHC2
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
- gpio_direction_input(USDHC1_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
- gpio_direction_output(USDHC1_PWR_GPIO, 0);
- udelay(500);
- gpio_direction_output(USDHC1_PWR_GPIO, 1);
- break;
- case 1:
-#if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
-#else
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-#endif
- gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
- gpio_direction_output(USDHC2_PWR_GPIO, 0);
- udelay(500);
- gpio_direction_output(USDHC2_PWR_GPIO, 1);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret) {
- printf("Warning: failed to initialize mmc dev %d\n", i);
- return ret;
- }
- }
- return 0;
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
#endif
--- /dev/null
+if TARGET_MT7622
+
+config SYS_BOARD
+ default "mt7622"
+
+config SYS_CONFIG_NAME
+ default "mt7622"
+
+config MTK_BROM_HEADER_INFO
+ string
+ default "lk=1"
+
+config MTK_BROM_HEADER_INFO
+ string
+ default "media=nor"
+
+endif
--- /dev/null
+MT7622
+M: Sam Shih <sam.shih@mediatek.com>
+S: Maintained
+F: board/mediatek/mt7622
+F: include/configs/mt7622.h
+F: configs/mt7622_rfb_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt7622_rfb.o
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <common.h>
+#include <config.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
+
+int board_late_init(void)
+{
+ gd->env_valid = 1; //to load environment variable from persistent store
+ env_relocate();
+ return 0;
+}
--- /dev/null
+if TARGET_MT8512
+
+config SYS_BOARD
+ default "mt8512"
+
+config SYS_CONFIG_NAME
+ default "mt8512"
+
+
+config MTK_BROM_HEADER_INFO
+ string
+ default "media=nor"
+
+endif
--- /dev/null
+MT8512
+M: Mingming lee <mingming.lee@mediatek.com>
+S: Maintained
+F: board/mediatek/mt8512
+F: include/configs/mt8512.h
+F: configs/mt8512_bm1_emmc_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt8512.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = gd->ram_base + 0x100;
+
+ debug("gd->fdt_blob is %p\n", gd->fdt_blob);
+ return 0;
+}
--- /dev/null
+if TARGET_GIEDI
+
+config SYS_BOARD
+ default "capricorn"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_CONFIG_NAME
+ default "giedi"
+
+endif
+
+if TARGET_DENEB
+
+config SYS_BOARD
+ default "capricorn"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_CONFIG_NAME
+ default "deneb"
+
+endif
--- /dev/null
+CAPRICORN BOARD
+M: Anatolij Gustschin <agust@denx.de>
+S: Maintained
+F: board/siemens/capricorn/
+F: include/configs/capricorn-common.h
+F: include/configs/deneb.h
+F: include/configs/giedi.h
+F: include/configs/siemens-ccp-common.h
+F: include/configs/siemens-env-common.h
+F: configs/deneb_defconfig
+F: configs/giedi_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Siemens AG
+#
+
+obj-y += board.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += ../common/factoryset.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2019 NXP
+ *
+ * Copyright 2019 Siemens AG
+ *
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <netdev.h>
+#include <env_internal.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <led.h>
+#include <pca953x.h>
+#include <power-domain.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+#ifndef CONFIG_SPL
+#include <asm/arch-imx8/clock.h>
+#endif
+#include "../common/factoryset.h"
+
+#define GPIO_PAD_CTRL \
+ ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL \
+ ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+ (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL \
+ ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart2_pads[] = {
+ SC_P_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ SC_P_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx8_iomux_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+int board_early_init_f(void)
+{
+ /* Set UART clock root to 80 MHz */
+ sc_pm_clock_rate_t rate = SC_80MHZ;
+ int ret;
+
+ ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+ ret |= sc_pm_setup_uart(SC_R_UART_2, rate);
+ if (ret)
+ return ret;
+
+ setup_iomux_uart();
+
+ return 0;
+}
+
+#define ENET_PHY_RESET IMX_GPIO_NR(0, 3)
+#define ENET_TEST_1 IMX_GPIO_NR(0, 8)
+#define ENET_TEST_2 IMX_GPIO_NR(0, 9)
+
+/*#define ETH_IO_TEST*/
+static iomux_cfg_t enet_reset[] = {
+ SC_P_ESAI0_SCKT | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+#ifdef ETH_IO_TEST
+ /* GPIO0.IO08 MODE3: TXD0 */
+ SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(4) |
+ MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+ /* GPIO0.IO09 MODE3: TXD1 */
+ SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(4) |
+ MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+#endif
+};
+
+static void enet_device_phy_reset(void)
+{
+ int ret = 0;
+
+ imx8_iomux_setup_multiple_pads(enet_reset, ARRAY_SIZE(enet_reset));
+
+ ret = gpio_request(ENET_PHY_RESET, "enet_phy_reset");
+ if (!ret) {
+ gpio_direction_output(ENET_PHY_RESET, 1);
+ gpio_set_value(ENET_PHY_RESET, 0);
+ /* SMSC9303 TRM chapter 14.5.2 */
+ udelay(200);
+ gpio_set_value(ENET_PHY_RESET, 1);
+ } else {
+ printf("ENET RESET failed!\n");
+ }
+
+#ifdef ETH_IO_TEST
+ ret = gpio_request(ENET_TEST_1, "enet_test1");
+ if (!ret) {
+ int i;
+
+ printf("ENET TEST 1!\n");
+ for (i = 0; i < 20; i++) {
+ gpio_direction_output(ENET_TEST_1, 1);
+ gpio_set_value(ENET_TEST_1, 0);
+ udelay(50);
+ gpio_set_value(ENET_TEST_1, 1);
+ udelay(50);
+ }
+ gpio_free(ENET_TEST_1);
+ } else {
+ printf("GPIO for ENET TEST 1 failed!\n");
+ }
+ ret = gpio_request(ENET_TEST_2, "enet_test2");
+ if (!ret) {
+ int i;
+
+ printf("ENET TEST 2!\n");
+ for (i = 0; i < 20; i++) {
+ gpio_direction_output(ENET_TEST_2, 1);
+ gpio_set_value(ENET_TEST_2, 0);
+ udelay(50);
+ gpio_set_value(ENET_TEST_2, 1);
+ udelay(50);
+ }
+ gpio_free(ENET_TEST_2);
+ } else {
+ printf("GPIO for ENET TEST 2 failed!\n");
+ }
+#endif
+}
+
+int setup_gpr_fec(void)
+{
+ sc_ipc_t ipc_handle = -1;
+ sc_err_t err = 0;
+ unsigned int test;
+
+ /*
+ * TX_CLK_SEL: it controls a mux between clock coming from the pad 50M
+ * input pin and clock generated internally to connectivity subsystem
+ * 0: internal clock
+ * 1: external clock ---> your choice for RMII
+ *
+ * CLKDIV_SEL: it controls a div by 2 on the internal clock path à
+ * it should be don’t care when using external clock
+ * 0: non-divided clock
+ * 1: clock divided by 2
+ * 50_DISABLE or 125_DISABLE:
+ * it’s used to disable the clock tree going outside the chip
+ * when reference clock is generated internally.
+ * It should be don’t care when reference clock is provided
+ * externally.
+ * 0: clock is enabled
+ * 1: clock is disabled
+ *
+ * SC_C_TXCLK = 24,
+ * SC_C_CLKDIV = 25,
+ * SC_C_DISABLE_50 = 26,
+ * SC_C_DISABLE_125 = 27,
+ */
+
+ err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1);
+ if (err != SC_ERR_NONE)
+ printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK);
+
+ sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
+ debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test);
+
+ err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0);
+ if (err != SC_ERR_NONE)
+ printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV);
+
+ sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test);
+ debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test);
+
+ err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0);
+ if (err != SC_ERR_NONE)
+ printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50);
+
+ sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
+ debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test);
+
+ err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1);
+ if (err != SC_ERR_NONE)
+ printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125);
+
+ sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
+ debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test);
+
+ err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1);
+ if (err != SC_ERR_NONE)
+ printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125);
+
+ sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test);
+ debug("TEST SC_C %d-->%d\n\r", SC_C_SEL_125, test);
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+#endif
+
+static int setup_fec(void)
+{
+ setup_gpr_fec();
+ /* Reset ENET PHY */
+ enet_device_phy_reset();
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
+#ifndef CONFIG_SPL_BUILD
+/* LED's */
+static int board_led_init(void)
+{
+ struct udevice *bus, *dev;
+ u8 pca_led[2] = { 0x00, 0x00 };
+ int ret;
+
+ /* init all GPIO LED's */
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ /* enable all leds on PCA9552 */
+ ret = uclass_get_device_by_seq(UCLASS_I2C, PCA9552_1_I2C_BUS, &bus);
+ if (ret) {
+ printf("ERROR: I2C get %d\n", ret);
+ return ret;
+ }
+
+ ret = dm_i2c_probe(bus, PCA9552_1_I2C_ADDR, 0, &dev);
+ if (ret) {
+ printf("ERROR: PCA9552 probe failed\n");
+ return ret;
+ }
+
+ ret = dm_i2c_write(dev, 0x16, pca_led, sizeof(pca_led));
+ if (ret) {
+ printf("ERROR: PCA9552 write failed\n");
+ return ret;
+ }
+
+ mdelay(1);
+ return ret;
+}
+#endif /* !CONFIG_SPL_BUILD */
+
+int checkboard(void)
+{
+ puts("Board: Capricorn\n");
+
+ /*
+ * Running build_info() doesn't work with current SCFW blob.
+ * Uncomment below call when new blob is available.
+ */
+ /*build_info();*/
+
+ print_bootinfo();
+ return 0;
+}
+
+int board_init(void)
+{
+ setup_fec();
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+static int check_mmc_autodetect(void)
+{
+ char *autodetect_str = env_get("mmcautodetect");
+
+ if (autodetect_str && (strcmp(autodetect_str, "yes") == 0))
+ return 1;
+
+ return 0;
+}
+
+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{
+ return dev_no;
+}
+
+void board_late_mmc_env_init(void)
+{
+ char cmd[32];
+ char mmcblk[32];
+ u32 dev_no = mmc_get_env_dev();
+
+ if (!check_mmc_autodetect())
+ return;
+
+ env_set_ulong("mmcdev", dev_no);
+
+ /* Set mmcblk env */
+ sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+ mmc_map_to_kernel_blk(dev_no));
+ env_set("mmcroot", mmcblk);
+
+ sprintf(cmd, "mmc dev %d", dev_no);
+ run_command(cmd, 0);
+}
+
+#ifndef CONFIG_SPL_BUILD
+int factoryset_read_eeprom(int i2c_addr);
+
+static int load_parameters_from_factoryset(void)
+{
+ int ret;
+
+ ret = factoryset_read_eeprom(EEPROM_I2C_ADDR);
+ if (ret)
+ return ret;
+
+ return factoryset_env_set();
+}
+
+int board_late_init(void)
+{
+ env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+ env_set("sec_boot", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_env_init();
+#endif
+ /* Init LEDs */
+ if (board_led_init())
+ printf("I2C LED init failed\n");
+
+ /* Set environment from factoryset */
+ if (load_parameters_from_factoryset())
+ printf("Loading factoryset parameters failed!\n");
+
+ return 0;
+}
+
+/* Service button */
+#define MAX_PIN_NUMBER 128
+#define BOARD_DEFAULT_BUTTON_GPIO IMX_GPIO_NR(1, 31)
+
+unsigned char get_button_state(char * const envname, unsigned char def)
+{
+ int button = 0;
+ int gpio;
+ char *ptr_env;
+
+ /* If button is not found we take default */
+ ptr_env = env_get(envname);
+ if (!ptr_env) {
+ printf("Using default: %u\n", def);
+ gpio = def;
+ } else {
+ gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0);
+ if (gpio > MAX_PIN_NUMBER)
+ gpio = def;
+ }
+
+ gpio_request(gpio, "");
+ gpio_direction_input(gpio);
+ if (gpio_get_value(gpio))
+ button = 1;
+ else
+ button = 0;
+
+ gpio_free(gpio);
+
+ return button;
+}
+
+/*
+ * This command returns the status of the user button on
+ * Input - none
+ * Returns - 1 if button is held down
+ * 0 if button is not held down
+ */
+static int
+do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int button = 0;
+
+ button = get_button_state("button_usr1", BOARD_DEFAULT_BUTTON_GPIO);
+
+ if (argc > 1)
+ printf("Button state: %u\n", button);
+
+ return button;
+}
+
+U_BOOT_CMD(
+ usrbutton, CONFIG_SYS_MAXARGS, 2, do_userbutton,
+ "Return the status of user button",
+ "[print]"
+);
+
+#define ERST IMX_GPIO_NR(0, 3)
+
+static int
+do_eth_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ gpio_request(ERST, "ERST");
+ gpio_direction_output(ERST, 0);
+ udelay(200);
+ gpio_set_value(ERST, 1);
+ return 0;
+}
+
+U_BOOT_CMD(
+ switch_rst, CONFIG_SYS_MAXARGS, 2, do_eth_reset,
+ "Reset eth phy",
+ "[print]"
+);
+#endif /* ! CONFIG_SPL_BUILD */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ *
+ * Refer doc/README.imx8image for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU capricorn-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Copyright 2019 Siemens AG
+ *
+ */
+#include <common.h>
+#include <spl.h>
+#include <dm.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+
+ uclass_find_first_device(UCLASS_MISC, &dev);
+
+ for (; dev; uclass_find_next_device(&dev)) {
+ if (device_probe(dev))
+ continue;
+ }
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* This file is to create a container image could be loaded by SPL */
+BOOT_FROM SD 0x400
+SOC_TYPE IMX8QX
+CONTAINER
+IMAGE A35 bl31.bin 0x80000000
+IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE
#include <env_internal.h>
#include <i2c.h>
#include <asm/io.h>
+#if !CONFIG_IS_ENABLED(TARGET_GIEDI) && !CONFIG_IS_ENABLED(TARGET_DENEB)
#include <asm/arch/cpu.h>
+#endif
#include <asm/arch/sys_proto.h>
#include <asm/unaligned.h>
#include <net.h>
#include <common.h>
#include <i2c.h>
#include <miiphy.h>
-#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../../freescale/common/pfuze.h"
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
-
#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
};
#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const fec1_pads[] = {
- MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
- MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
- MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11)
-
-static void setup_iomux_fec(void)
-{
- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
- gpio_request(FEC1_RST_GPIO, "phy_rst");
- gpio_direction_output(FEC1_RST_GPIO, 0);
- udelay(500);
- gpio_set_value(FEC1_RST_GPIO, 1);
-}
-
-int board_eth_init(bd_t *bis)
-{
- setup_iomux_fec();
-
- return fecmxc_initialize_multi(bis, 0,
- CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
-}
-
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_DM_VIDEO
-
setup_lcd();
-
#endif
#ifdef CONFIG_FEC_MXC
setup_fec();
ret = pmic_get("pfuze100@8", &dev);
if (ret < 0) {
- printf("pmic_get() ret %d\n", ret);
+ debug("pmic_get() ret %d\n", ret);
return 0;
}
return 0;
} else if (strncmp(argv[1], "part", 4) == 0) {
if (blk_list_part(if_type))
- printf("\nno %s devices available\n", if_name);
+ printf("\nno %s partition table available\n",
+ if_name);
return 0;
}
return CMD_RET_USAGE;
this option to build system-specific drivers for hash acceleration
as part of an SPL build.
-config SPL_DMA_SUPPORT
+config SPL_DMA
bool "Support DMA drivers"
help
Enable DMA (direct-memory-access) drivers in SPL. These drivers
spl_image->entry_point = image_get_ep(header);
spl_image->size = image_get_data_size(header);
} else {
- spl_image->entry_point = image_get_load(header);
+ spl_image->entry_point = image_get_ep(header);
/* Load including the header */
- spl_image->load_addr = spl_image->entry_point -
+ spl_image->load_addr = image_get_load(header) -
header_size;
spl_image->size = image_get_data_size(header) +
header_size;
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
+CONFIG_TARGET_DENEB=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
+CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8-deneb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_OFFSET_REDUND=0x2000
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MV88E61XX_SWITCH=y
+CONFIG_MV88E61XX_CPU_PORT=5
+CONFIG_MV88E61XX_PHY_PORTS=0x7
+CONFIG_MV88E61XX_FIXED_PORTS=0x0
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B050000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+# CONFIG_SPL_WDT is not set
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOOTCOUNT_LIMIT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SAVEENV=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
+CONFIG_TARGET_GIEDI=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
+CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_OFFSET_REDUND=0x2000
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MV88E61XX_SWITCH=y
+CONFIG_MV88E61XX_CPU_PORT=5
+CONFIG_MV88E61XX_PHY_PORTS=0x7
+CONFIG_MV88E61XX_FIXED_PORTS=0x0
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B050000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+# CONFIG_SPL_WDT is not set
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_DM_GPIO=y
CONFIG_SPL_FORCE_MMC_BOOT=y
CONFIG_SPL_MMC_TINY=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
CONFIG_BOOTDELAY=3
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_CLK=y
CONFIG_CLK_IMX8=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMXRT=y
+CONFIG_SYS_TEXT_BASE=0x80002000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_ENV_OFFSET=0x80000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_IMXRT1050_EVK=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_SIZE_LIMIT=131072
+CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x20209000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SD_BOOT=y
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
+# CONFIG_SPL_CRC32_SUPPORT is not set
+# CONFIG_SPL_DM_GPIO is not set
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_TFTP_BLOCKSIZE=512
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_OF_TRANSLATE is not set
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMXRT1050=y
+CONFIG_CLK_IMXRT1050=y
+CONFIG_MXC_GPIO=y
+# CONFIG_INPUT is not set
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMXRT=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_IMXRT_SDRAM=y
+CONFIG_FSL_LPUART=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_HEXDUMP=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TARGET_MT7622=y
+CONFIG_SYS_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_LOG_MAX_LEVEL=6
+CONFIG_DEFAULT_FDT_FILE="mt7622-rfb"
+CONFIG_SYS_PROMPT="MT7622> "
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SMC=y
+CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7622=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SNFI_SPI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_TIMER=y
+CONFIG_MTK_TIMER=y
+CONFIG_WDT_MTK=y
+CONFIG_LZ4=y
+CONFIG_LZO=y
+CONFIG_HEXDUMP=y
CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MEDIATEK=y
+CONFIG_TARGET_MT7623=y
CONFIG_SYS_TEXT_BASE=0x81e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x1000
--- /dev/null
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_TEXT_BASE=0x44e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_TARGET_MT8512=y
+CONFIG_SYS_PROMPT="MT8512> "
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_OF_LIBFDT=y
+# CONFIG_FDT_DEBUG is not set
+CONFIG_LZMA=y
+CONFIG_LZ4=y
+CONFIG_LZO=y
+CONFIG_GZIP=y
+CONFIG_BZIP2=y
+CONFIG_CMD_BOOTMENU=y
+CONFIG_MENU_SHOW=y
+CONFIG_DEFAULT_FDT_FILE="mt8512-bm1-emmc.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="mt8512-bm1-emmc"
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_MT8512=y
+CONFIG_PINCONF=y
+CONFIG_DM_GPIO=y
+CONFIG_RAM=y
+CONFIG_BAUDRATE=921600
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM=y
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_WDT=y
+CONFIG_WDT_MTK=y
+CONFIG_CLK=y
+CONFIG_TIMER=y
+CONFIG_MTK_TIMER=y
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MTK=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_ETHER=y
-CONFIG_USB_ETH_CDC=y
-CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_BPP8=y
CONFIG_VIDEO_BPP16=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MISC_INIT_R=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_DMA_SUPPORT=y
+CONFIG_SPL_DMA=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o)
CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/raw/libnand.o)
CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc)
-CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
+CONFIG_SPL_DMA (drivers/dma/libdma.o)
CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/raw/nand_spl_load.o)
CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o)
.. kernel-doc:: lib/efi_loader/efi_net.c
:internal:
+Random number generator protocol
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: lib/efi_loader/efi_rng.c
+ :internal:
+
Text IO protocols
~~~~~~~~~~~~~~~~~
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/
obj-$(CONFIG_SPL_DM_RESET) += reset/
-obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/
+obj-$(CONFIG_SPL_DMA) += dma/
obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
obj-$(CONFIG_SPL_USB_ETHER) += net/phy/
return clk_get_by_index(dev, index, clk);
}
+int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
+{
+ int index;
+
+ debug("%s(node=%p, name=%s, clk=%p)\n", __func__,
+ ofnode_get_name(node), name, clk);
+ clk->dev = NULL;
+
+ index = ofnode_stringlist_search(node, "clock-names", name);
+ if (index < 0) {
+ debug("fdt_stringlist_search() failed: %d\n", index);
+ return index;
+ }
+
+ return clk_get_by_index_nodev(node, index, clk);
+}
+
+int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
+{
+ int ret;
+
+ ret = clk_get_by_name_nodev(node, name, clk);
+ if (ret == -ENODATA)
+ return 0;
+
+ return ret;
+}
+
int clk_release_all(struct clk *clk, int count)
{
int i, ret;
const struct clk_ops *ops;
debug("%s(clk=%p)\n", __func__, clk);
- if (!clk)
+ if (!clk_valid(clk))
return 0;
ops = clk_dev_ops(clk->dev);
const struct clk_ops *ops;
debug("%s(clk=%p)\n", __func__, clk);
- if (!clk)
+ if (!clk_valid(clk))
return 0;
ops = clk_dev_ops(clk->dev);
struct clk *pclk;
debug("%s(clk=%p)\n", __func__, clk);
- if (!clk)
+ if (!clk_valid(clk))
return NULL;
pdev = dev_get_parent(clk->dev);
struct clk *pclk;
debug("%s(clk=%p)\n", __func__, clk);
- if (!clk)
+ if (!clk_valid(clk))
return 0;
pclk = clk_get_parent(clk);
const struct clk_ops *ops;
debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
- if (!clk)
+ if (!clk_valid(clk))
return 0;
ops = clk_dev_ops(clk->dev);
const struct clk_ops *ops;
debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
- if (!clk)
+ if (!clk_valid(clk))
return 0;
ops = clk_dev_ops(clk->dev);
int ret;
debug("%s(clk=%p)\n", __func__, clk);
- if (!clk)
+ if (!clk_valid(clk))
return 0;
ops = clk_dev_ops(clk->dev);
int ret;
debug("%s(clk=%p)\n", __func__, clk);
- if (!clk)
+ if (!clk_valid(clk))
return 0;
ops = clk_dev_ops(clk->dev);
{
struct clk *clk = devm_clk_get(dev, id);
- if (IS_ERR(clk))
+ if (PTR_ERR(clk) == -ENODATA)
return NULL;
return clk;
return to_clk_fixed_rate(clk->dev)->fixed_rate;
}
+/* avoid clk_enable() return -ENOSYS */
+static int dummy_enable(struct clk *clk)
+{
+ return 0;
+}
+
const struct clk_ops clk_fixed_rate_ops = {
.get_rate = clk_fixed_rate_get_rate,
+ .enable = dummy_enable,
};
static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
select CLK_CCF
help
This enables support clock driver for i.MX8MP platforms.
+
+config SPL_CLK_IMXRT1050
+ bool "SPL clock support for i.MXRT1050"
+ depends on ARCH_IMXRT && SPL
+ select SPL_CLK
+ select SPL_CLK_CCF
+ help
+ This enables SPL DM/DTS support for clock driver in i.MXRT1050
+
+config CLK_IMXRT1050
+ bool "Clock support for i.MXRT1050"
+ depends on ARCH_IMXRT
+ select CLK
+ select CLK_CCF
+ help
+ This enables support clock driver for i.MXRT1050 platforms.
clk-composite-8m.o
obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
clk-composite-8m.o
+
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
pm_clk = SC_PM_CLK_CPU;
break;
case IMX8QXP_I2C0_CLK:
+ case IMX8QXP_I2C0_IPG_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C1_CLK:
+ case IMX8QXP_I2C1_IPG_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C2_CLK:
+ case IMX8QXP_I2C2_IPG_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C3_CLK:
+ case IMX8QXP_I2C3_IPG_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
switch (clk->id) {
case IMX8QXP_I2C0_CLK:
+ case IMX8QXP_I2C0_IPG_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C1_CLK:
+ case IMX8QXP_I2C1_IPG_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C2_CLK:
+ case IMX8QXP_I2C2_IPG_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C3_CLK:
+ case IMX8QXP_I2C3_IPG_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
switch (clk->id) {
case IMX8QXP_I2C0_CLK:
+ case IMX8QXP_I2C0_IPG_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C1_CLK:
+ case IMX8QXP_I2C1_IPG_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C2_CLK:
+ case IMX8QXP_I2C2_IPG_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C3_CLK:
+ case IMX8QXP_I2C3_IPG_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dt-bindings/clock/imxrt1050-clock.h>
+
+#include "clk.h"
+
+static ulong imxrt1050_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu)\n", __func__, clk->id);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_get_rate(c);
+}
+
+static ulong imxrt1050_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ return clk_set_rate(c, rate);
+}
+
+static int __imxrt1050_clk_enable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int ret;
+
+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+ ret = clk_get_by_id(clk->id, &c);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ret = clk_enable(c);
+ else
+ ret = clk_disable(c);
+
+ return ret;
+}
+
+static int imxrt1050_clk_disable(struct clk *clk)
+{
+ return __imxrt1050_clk_enable(clk, 0);
+}
+
+static int imxrt1050_clk_enable(struct clk *clk)
+{
+ return __imxrt1050_clk_enable(clk, 1);
+}
+
+static struct clk_ops imxrt1050_clk_ops = {
+ .set_rate = imxrt1050_clk_set_rate,
+ .get_rate = imxrt1050_clk_get_rate,
+ .enable = imxrt1050_clk_enable,
+ .disable = imxrt1050_clk_disable,
+};
+
+static const char * const pll_ref_sels[] = {"osc", "dummy", };
+static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", };
+static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", };
+static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
+static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", };
+
+static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", };
+static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
+static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
+static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
+static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
+static const char *const lcdif_sels[] = { "pll2_sys", "pll3_pfd3_454_74m", "pll5_video:", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_664_62m"};
+
+static int imxrt1050_clk_probe(struct udevice *dev)
+{
+ void *base;
+
+ /* Anatop clocks */
+ base = (void *)ANATOP_BASE_ADDR;
+
+ clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
+ imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,
+ imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,
+ imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+ clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,
+ imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+
+ clk_dm(IMXRT1050_CLK_PLL1_ARM,
+ imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
+ base + 0x0, 0x7f));
+ clk_dm(IMXRT1050_CLK_PLL2_SYS,
+ imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
+ base + 0x30, 0x1));
+ clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,
+ imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
+ "pll3_usb_otg_ref_sel",
+ base + 0x10, 0x1));
+ clk_dm(IMXRT1050_CLK_PLL5_VIDEO,
+ imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
+ base + 0xa0, 0x7f));
+
+ /* PLL bypass out */
+ clk_dm(IMXRT1050_CLK_PLL1_BYPASS,
+ imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
+ pll1_bypass_sels,
+ ARRAY_SIZE(pll1_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMXRT1050_CLK_PLL2_BYPASS,
+ imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
+ pll2_bypass_sels,
+ ARRAY_SIZE(pll2_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMXRT1050_CLK_PLL3_BYPASS,
+ imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
+ pll3_bypass_sels,
+ ARRAY_SIZE(pll3_bypass_sels),
+ CLK_SET_RATE_PARENT));
+ clk_dm(IMXRT1050_CLK_PLL5_BYPASS,
+ imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
+ pll5_bypass_sels,
+ ARRAY_SIZE(pll5_bypass_sels),
+ CLK_SET_RATE_PARENT));
+
+ clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,
+ imx_clk_divider("video_post_div_sel", "pll5_video",
+ base + 0xa0, 19, 2));
+ clk_dm(IMXRT1050_CLK_VIDEO_DIV,
+ imx_clk_divider("video_div", "video_post_div_sel",
+ base + 0x170, 30, 2));
+
+ clk_dm(IMXRT1050_CLK_PLL3_80M,
+ imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
+
+ clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,
+ imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
+ clk_dm(IMXRT1050_CLK_PLL2_PFD1_594M,
+ imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1));
+ clk_dm(IMXRT1050_CLK_PLL2_PFD2_396M,
+ imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2));
+ clk_dm(IMXRT1050_CLK_PLL3_PFD1_664_62M,
+ imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0,
+ 1));
+ clk_dm(IMXRT1050_CLK_PLL3_PFD3_454_74M,
+ imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0,
+ 3));
+
+ /* CCM clocks */
+ base = dev_read_addr_ptr(dev);
+ if (base == (void *)FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ clk_dm(IMXRT1050_CLK_ARM_PODF,
+ imx_clk_divider("arm_podf", "pll1_arm",
+ base + 0x10, 0, 3));
+
+ clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,
+ imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
+ pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
+ clk_dm(IMXRT1050_CLK_PERIPH_SEL,
+ imx_clk_mux("periph_sel", base + 0x14, 25, 1,
+ periph_sels, ARRAY_SIZE(periph_sels)));
+ clk_dm(IMXRT1050_CLK_USDHC1_SEL,
+ imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ clk_dm(IMXRT1050_CLK_USDHC2_SEL,
+ imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+ usdhc_sels, ARRAY_SIZE(usdhc_sels)));
+ clk_dm(IMXRT1050_CLK_LPUART_SEL,
+ imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
+ lpuart_sels, ARRAY_SIZE(lpuart_sels)));
+ clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,
+ imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
+ semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
+ clk_dm(IMXRT1050_CLK_SEMC_SEL,
+ imx_clk_mux("semc_sel", base + 0x14, 6, 1,
+ semc_sels, ARRAY_SIZE(semc_sels)));
+ clk_dm(IMXRT1050_CLK_LCDIF_SEL,
+ imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
+ lcdif_sels, ARRAY_SIZE(lcdif_sels)));
+
+ clk_dm(IMXRT1050_CLK_AHB_PODF,
+ imx_clk_divider("ahb_podf", "periph_sel",
+ base + 0x14, 10, 3));
+ clk_dm(IMXRT1050_CLK_USDHC1_PODF,
+ imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+ base + 0x24, 11, 3));
+ clk_dm(IMXRT1050_CLK_USDHC2_PODF,
+ imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+ base + 0x24, 16, 3));
+ clk_dm(IMXRT1050_CLK_LPUART_PODF,
+ imx_clk_divider("lpuart_podf", "lpuart_sel",
+ base + 0x24, 0, 6));
+ clk_dm(IMXRT1050_CLK_SEMC_PODF,
+ imx_clk_divider("semc_podf", "semc_sel",
+ base + 0x14, 16, 3));
+ clk_dm(IMXRT1050_CLK_LCDIF_PRED,
+ imx_clk_divider("lcdif_pred", "lcdif_sel",
+ base + 0x38, 12, 3));
+ clk_dm(IMXRT1050_CLK_LCDIF_PODF,
+ imx_clk_divider("lcdif_podf", "lcdif_pred",
+ base + 0x18, 23, 3));
+
+ clk_dm(IMXRT1050_CLK_USDHC1,
+ imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+ clk_dm(IMXRT1050_CLK_USDHC2,
+ imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+ clk_dm(IMXRT1050_CLK_LPUART1,
+ imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
+ clk_dm(IMXRT1050_CLK_SEMC,
+ imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
+ clk_dm(IMXRT1050_CLK_LCDIF,
+ imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+
+#ifdef CONFIG_SPL_BUILD
+ struct clk *clk, *clk1;
+
+ /* bypass pll1 before setting its rate */
+ clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
+ clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
+ clk_set_parent(clk1, clk);
+
+ clk_get_by_id(IMXRT1050_CLK_PLL1_ARM, &clk);
+ clk_enable(clk);
+ clk_set_rate(clk, 1056000000UL);
+
+ clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
+ clk_set_parent(clk1, clk);
+
+ clk_get_by_id(IMXRT1050_CLK_SEMC_SEL, &clk1);
+ clk_get_by_id(IMXRT1050_CLK_SEMC_ALT_SEL, &clk);
+ clk_set_parent(clk1, clk);
+
+ clk_get_by_id(IMXRT1050_CLK_PLL2_SYS, &clk);
+ clk_enable(clk);
+ clk_set_rate(clk, 528000000UL);
+
+ clk_get_by_id(IMXRT1050_CLK_PLL2_BYPASS, &clk1);
+ clk_set_parent(clk1, clk);
+
+ /* Configure PLL3_USB_OTG to 480MHz */
+ clk_get_by_id(IMXRT1050_CLK_PLL3_USB_OTG, &clk);
+ clk_enable(clk);
+ clk_set_rate(clk, 480000000UL);
+
+ clk_get_by_id(IMXRT1050_CLK_PLL3_BYPASS, &clk1);
+ clk_set_parent(clk1, clk);
+
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id imxrt1050_clk_ids[] = {
+ { .compatible = "fsl,imxrt1050-ccm" },
+ { },
+};
+
+U_BOOT_DRIVER(imxrt1050_clk) = {
+ .name = "clk_imxrt1050",
+ .id = UCLASS_CLK,
+ .of_match = imxrt1050_clk_ids,
+ .ops = &imxrt1050_clk_ops,
+ .probe = imxrt1050_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
return tmp;
}
+static unsigned long clk_pfd_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk_pfd *pfd = to_clk_pfd(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ u64 tmp = parent_rate;
+ u8 frac;
+
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+ if (frac < 12)
+ frac = 12;
+ else if (frac > 35)
+ frac = 35;
+
+ writel(0x3f << (pfd->idx * 8), pfd->reg + CLR);
+ writel(frac << (pfd->idx * 8), pfd->reg + SET);
+
+ return 0;
+}
+
static const struct clk_ops clk_pfd_ops = {
.get_rate = clk_pfd_recalc_rate,
+ .set_rate = clk_pfd_set_rate,
};
struct clk *imx_clk_pfd(const char *name, const char *parent_name,
#include <common.h>
#include <asm/io.h>
+#include <div64.h>
#include <malloc.h>
#include <clk-uclass.h>
#include <dm/device.h>
#include <clk.h>
#include "clk.h"
-#define UBOOT_DM_CLK_IMX_PLLV3 "imx_clk_pllv3"
+#define UBOOT_DM_CLK_IMX_PLLV3_GENERIC "imx_clk_pllv3_generic"
+#define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys"
+#define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb"
+#define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av"
+
+#define PLL_NUM_OFFSET 0x10
+#define PLL_DENOM_OFFSET 0x20
+
+#define BM_PLL_POWER (0x1 << 12)
+#define BM_PLL_LOCK (0x1 << 31)
struct clk_pllv3 {
struct clk clk;
void __iomem *base;
+ u32 power_bit;
+ bool powerup_set;
u32 div_mask;
u32 div_shift;
};
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
-static ulong clk_pllv3_get_rate(struct clk *clk)
+static ulong clk_pllv3_generic_get_rate(struct clk *clk)
{
struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
unsigned long parent_rate = clk_get_parent_rate(clk);
return (div == 1) ? parent_rate * 22 : parent_rate * 20;
}
+static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ u32 val, div;
+
+ if (rate == parent_rate * 22)
+ div = 1;
+ else if (rate == parent_rate * 20)
+ div = 0;
+ else
+ return -EINVAL;
+
+ val = readl(pll->base);
+ val &= ~(pll->div_mask << pll->div_shift);
+ val |= (div << pll->div_shift);
+ writel(val, pll->base);
+
+ /* Wait for PLL to lock */
+ while (!(readl(pll->base) & BM_PLL_LOCK))
+ ;
+
+ return 0;
+}
+
+static int clk_pllv3_generic_enable(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ u32 val;
+
+ val = readl(pll->base);
+ if (pll->powerup_set)
+ val |= pll->power_bit;
+ else
+ val &= ~pll->power_bit;
+ writel(val, pll->base);
+
+ return 0;
+}
+
+static int clk_pllv3_generic_disable(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ u32 val;
+
+ val = readl(pll->base);
+ if (pll->powerup_set)
+ val &= ~pll->power_bit;
+ else
+ val |= pll->power_bit;
+ writel(val, pll->base);
+
+ return 0;
+}
+
static const struct clk_ops clk_pllv3_generic_ops = {
- .get_rate = clk_pllv3_get_rate,
+ .get_rate = clk_pllv3_generic_get_rate,
+ .enable = clk_pllv3_generic_enable,
+ .disable = clk_pllv3_generic_disable,
+ .set_rate = clk_pllv3_generic_set_rate,
+};
+
+static ulong clk_pllv3_sys_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ u32 div = readl(pll->base) & pll->div_mask;
+
+ return parent_rate * div / 2;
+}
+
+static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ unsigned long min_rate = parent_rate * 54 / 2;
+ unsigned long max_rate = parent_rate * 108 / 2;
+ u32 val, div;
+
+ if (rate < min_rate || rate > max_rate)
+ return -EINVAL;
+
+ div = rate * 2 / parent_rate;
+ val = readl(pll->base);
+ val &= ~pll->div_mask;
+ val |= div;
+ writel(val, pll->base);
+
+ /* Wait for PLL to lock */
+ while (!(readl(pll->base) & BM_PLL_LOCK))
+ ;
+
+ return 0;
+}
+
+static const struct clk_ops clk_pllv3_sys_ops = {
+ .enable = clk_pllv3_generic_enable,
+ .disable = clk_pllv3_generic_disable,
+ .get_rate = clk_pllv3_sys_get_rate,
+ .set_rate = clk_pllv3_sys_set_rate,
+};
+
+static ulong clk_pllv3_av_get_rate(struct clk *clk)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
+ u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
+ u32 div = readl(pll->base) & pll->div_mask;
+ u64 temp64 = (u64)parent_rate;
+
+ temp64 *= mfn;
+ do_div(temp64, mfd);
+
+ return parent_rate * div + (unsigned long)temp64;
+}
+
+static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+ unsigned long parent_rate = clk_get_parent_rate(clk);
+ unsigned long min_rate = parent_rate * 27;
+ unsigned long max_rate = parent_rate * 54;
+ u32 val, div;
+ u32 mfn, mfd = 1000000;
+ u32 max_mfd = 0x3FFFFFFF;
+ u64 temp64;
+
+ if (rate < min_rate || rate > max_rate)
+ return -EINVAL;
+
+ if (parent_rate <= max_mfd)
+ mfd = parent_rate;
+
+ div = rate / parent_rate;
+ temp64 = (u64)(rate - div * parent_rate);
+ temp64 *= mfd;
+ do_div(temp64, parent_rate);
+ mfn = temp64;
+
+ val = readl(pll->base);
+ val &= ~pll->div_mask;
+ val |= div;
+ writel(val, pll->base);
+ writel(mfn, pll->base + PLL_NUM_OFFSET);
+ writel(mfd, pll->base + PLL_DENOM_OFFSET);
+
+ /* Wait for PLL to lock */
+ while (!(readl(pll->base) & BM_PLL_LOCK))
+ ;
+
+ return 0;
+}
+
+static const struct clk_ops clk_pllv3_av_ops = {
+ .enable = clk_pllv3_generic_enable,
+ .disable = clk_pllv3_generic_disable,
+ .get_rate = clk_pllv3_av_get_rate,
+ .set_rate = clk_pllv3_av_set_rate,
};
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
if (!pll)
return ERR_PTR(-ENOMEM);
+ pll->power_bit = BM_PLL_POWER;
+
switch (type) {
case IMX_PLLV3_GENERIC:
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
+ pll->div_shift = 0;
+ pll->powerup_set = false;
+ break;
+ case IMX_PLLV3_SYS:
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
+ pll->div_shift = 0;
+ pll->powerup_set = false;
+ break;
case IMX_PLLV3_USB:
- drv_name = UBOOT_DM_CLK_IMX_PLLV3;
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
+ pll->div_shift = 1;
+ pll->powerup_set = true;
+ break;
+ case IMX_PLLV3_AV:
+ drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
+ pll->div_shift = 0;
+ pll->powerup_set = false;
break;
default:
kfree(pll);
}
U_BOOT_DRIVER(clk_pllv3_generic) = {
- .name = UBOOT_DM_CLK_IMX_PLLV3,
+ .name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
.id = UCLASS_CLK,
.ops = &clk_pllv3_generic_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+U_BOOT_DRIVER(clk_pllv3_sys) = {
+ .name = UBOOT_DM_CLK_IMX_PLLV3_SYS,
+ .id = UCLASS_CLK,
+ .ops = &clk_pllv3_sys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(clk_pllv3_usb) = {
+ .name = UBOOT_DM_CLK_IMX_PLLV3_USB,
+ .id = UCLASS_CLK,
+ .ops = &clk_pllv3_generic_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(clk_pllv3_av) = {
+ .name = UBOOT_DM_CLK_IMX_PLLV3_AV,
+ .id = UCLASS_CLK,
+ .ops = &clk_pllv3_av_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
+obj-$(CONFIG_MT8512) += clk-mt8512.o
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
+obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7622 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch-mediatek/reset.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt7622-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT7622_CLKSQ_STB_CON0 0x20
+#define MT7622_PLL_ISO_CON0 0x2c
+#define MT7622_PLL_FMAX (2500UL * MHZ)
+#define MT7622_CON0_RST_BAR BIT(24)
+
+#define MCU_AXI_DIV 0x640
+#define AXI_DIV_MSK GENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+#define MCU_BUS_MUX 0x7c0
+#define MCU_BUS_MSK GENMASK(10, 9)
+#define MCU_BUS_SEL(x) ((x) << 9)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = MT7622_CON0_RST_BAR, \
+ .fmax = MT7622_PLL_FMAX, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+ 21, 0x214, 24, 0x214, 0),
+ PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+ 7, 0x224, 24, 0x224, 14),
+ PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
+ 21, 0x300, 1, 0x304, 0),
+ PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
+ 21, 0x314, 1, 0x318, 0),
+ PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0,
+ 31, 0x324, 1, 0x328, 0),
+ PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0,
+ 31, 0x334, 1, 0x338, 0),
+ PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0,
+ 21, 0x344, 1, 0x348, 0),
+ PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
+ 21, 0x358, 1, 0x35c, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
+ FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
+ FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
+ FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
+ FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
+ FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
+ FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
+ FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
+ FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
+ FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
+ FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
+ FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
+ FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
+ FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
+ FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
+ FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
+ FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
+ FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
+ FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
+ FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
+ FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
+ FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
+ FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
+ FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
+ FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
+ FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
+ FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
+ FACTOR1(CLK_TOP_UNIVPLL1_D16, CLK_TOP_UNIVPLL, 1, 32),
+ FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
+ FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
+ FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
+ FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
+ FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
+ FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
+ FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
+ FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
+ FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
+ FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
+ FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
+ FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1),
+ FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
+ FACTOR0(CLK_TOP_AUD1PLL, CLK_APMIXED_AUD1PLL, 1, 1),
+ FACTOR0(CLK_TOP_AUD2PLL, CLK_APMIXED_AUD2PLL, 1, 1),
+ FACTOR1(CLK_TOP_AUD_I2S2_MCK, CLK_TOP_I2S2_MCK_SEL, 1, 2),
+ FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_UNIVPLL2_D4, 1, 4),
+ FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
+ FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
+ FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
+};
+
+static const int axi_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL_D5,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL_D7
+};
+
+static const int mem_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_DMPLL
+};
+
+static const int ddrphycfg_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int eth_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL_D5,
+ -1,
+ CLK_TOP_UNIVPLL_D7
+};
+
+static const int pwm_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL2_D4
+};
+
+static const int f10m_ref_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL4_D16
+};
+
+static const int nfi_infra_parents[] = {
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_UNIVPLL1_D8,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_SYSPLL1_D4
+};
+
+static const int flash_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL_D80_D4,
+ CLK_TOP_SYSPLL2_D8,
+ CLK_TOP_SYSPLL3_D4,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL1_D8,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_UNIVPLL2_D4
+};
+
+static const int uart_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int spi0_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL3_D2,
+ CLK_XTAL,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL1_D8,
+ CLK_XTAL
+};
+
+static const int spi1_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL3_D2,
+ CLK_XTAL,
+ CLK_TOP_SYSPLL4_D4,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL1_D8,
+ CLK_XTAL
+};
+
+static const int msdc30_0_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL2_D16,
+ CLK_TOP_UNIV48M
+};
+
+static const int a1sys_hp_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_AUD1PLL,
+ CLK_TOP_AUD2PLL,
+ CLK_XTAL
+};
+
+static const int intdir_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_TOP_SGMIIPLL
+};
+
+static const int aud_intbus_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_SYSPLL3_D2
+};
+
+static const int pmicspi_parents[] = {
+ CLK_XTAL,
+ -1,
+ -1,
+ -1,
+ -1,
+ CLK_TOP_UNIVPLL2_D16
+};
+
+static const int atb_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL_D5
+};
+
+static const int audio_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL3_D4,
+ CLK_TOP_SYSPLL4_D4,
+ CLK_TOP_UNIVPLL1_D16
+};
+
+static const int usb20_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_XTAL
+};
+
+static const int aud1_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_AUD1PLL
+};
+
+static const int asm_l_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL_D5,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL2_D4
+};
+
+static const int apll1_ck_parents[] = {
+ CLK_TOP_AUD1_SEL,
+ CLK_TOP_AUD2_SEL
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
+ MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
+ MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
+
+ /* CLK_CFG_1 */
+ MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
+ MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
+ MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
+ MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
+
+ /* CLK_CFG_2 */
+ MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
+ MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
+ MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
+ MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
+
+ /* CLK_CFG_3 */
+ MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
+ MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23),
+ MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31),
+
+ /* CLK_CFG_4 */
+ MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
+ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
+ MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
+ MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31),
+
+ /* CLK_CFG_5 */
+ MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
+ MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
+ CLK_DOMAIN_SCPSYS),
+ MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
+ MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
+
+ /* CLK_CFG_6 */
+ MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
+ MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
+ MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
+ MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
+
+ /* CLK_CFG_7 */
+ MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7),
+ MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
+
+ /* CLK_AUDDIV_0 */
+ MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
+ MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
+ MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
+ MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
+ MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
+ MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
+};
+
+/* infracfg */
+static const struct mtk_gate_regs infra_cg_regs = {
+ .set_ofs = 0x40,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x48,
+};
+
+#define GATE_INFRA(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate infra_cgs[] = {
+ GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0),
+ GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
+ GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5),
+ GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16),
+ GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18),
+ GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22),
+};
+
+/* pericfg */
+static const struct mtk_gate_regs peri0_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x10,
+ .sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs peri1_cg_regs = {
+ .set_ofs = 0xC,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x1C,
+};
+
+#define GATE_PERI0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &peri0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_PERI1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &peri1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate peri_cgs[] = {
+ /* PERI0 */
+ GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
+ GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
+ GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
+ GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
+ GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
+ GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
+ GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
+ GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
+ GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9),
+ GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
+ GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
+ GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
+ GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17),
+ GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
+ GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
+ GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
+ GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
+ GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
+ GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
+ GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
+ GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
+ GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
+ GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
+ GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29),
+ GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
+ GATE_PERI1(CLK_PERI_NFIECC_PD, CLK_TOP_AXI_SEL, 31),
+
+ /* PERI1 */
+ GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH_SEL, 1),
+ GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2),
+};
+
+/* ethsys */
+static const struct mtk_gate_regs eth_cg_regs = {
+ .sta_ofs = 0x30,
+};
+
+#define GATE_ETH(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = ð_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate eth_cgs[] = {
+ GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5),
+ GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6),
+ GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
+ GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
+ GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
+};
+
+static const struct mtk_gate_regs sgmii_cg_regs = {
+ .sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &sgmii_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+}
+
+static const struct mtk_gate sgmii_cgs[] = {
+ GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
+ GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
+ GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
+ GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
+};
+
+static const struct mtk_clk_tree mt7622_clk_tree = {
+ .xtal_rate = 25 * MHZ,
+ .xtal2_rate = 25 * MHZ,
+ .fdivs_offs = CLK_TOP_TO_USB3_SYS,
+ .muxes_offs = CLK_TOP_AXI_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static int mt7622_mcucfg_probe(struct udevice *dev)
+{
+ void __iomem *base;
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -ENOENT;
+
+ clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
+ AXI_DIV_SEL(0x12));
+ clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
+ MCU_BUS_SEL(0x1));
+
+ return 0;
+}
+
+static int mt7622_apmixedsys_probe(struct udevice *dev)
+{
+ struct mtk_clk_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = mtk_common_clk_init(dev, &mt7622_clk_tree);
+ if (ret)
+ return ret;
+
+ /* reduce clock square disable time */
+ // writel(0x501, priv->base + MT7622_CLKSQ_STB_CON0);
+ writel(0x98940501, priv->base + MT7622_CLKSQ_STB_CON0);
+
+ /* extend pwr/iso control timing to 1us */
+ writel(0x80008, priv->base + MT7622_PLL_ISO_CON0);
+
+ return 0;
+}
+
+static int mt7622_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt7622_clk_tree);
+}
+
+static int mt7622_infracfg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs);
+}
+
+static int mt7622_pericfg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
+}
+
+static int mt7622_ethsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
+}
+
+static int mt7622_ethsys_bind(struct udevice *dev)
+{
+ int ret = 0;
+
+#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+ if (ret)
+ debug("Warning: failed to bind reset controller\n");
+#endif
+
+ return ret;
+}
+
+static int mt7622_sgmiisys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
+}
+
+static const struct udevice_id mt7622_apmixed_compat[] = {
+ { .compatible = "mediatek,mt7622-apmixedsys" },
+ { }
+};
+
+static const struct udevice_id mt7622_topckgen_compat[] = {
+ { .compatible = "mediatek,mt7622-topckgen" },
+ { }
+};
+
+static const struct udevice_id mt7622_infracfg_compat[] = {
+ { .compatible = "mediatek,mt7622-infracfg", },
+ { }
+};
+
+static const struct udevice_id mt7622_pericfg_compat[] = {
+ { .compatible = "mediatek,mt7622-pericfg", },
+ { }
+};
+
+static const struct udevice_id mt7622_ethsys_compat[] = {
+ { .compatible = "mediatek,mt7622-ethsys", },
+ { }
+};
+
+static const struct udevice_id mt7622_sgmiisys_compat[] = {
+ { .compatible = "mediatek,mt7622-sgmiisys", },
+ { }
+};
+
+static const struct udevice_id mt7622_mcucfg_compat[] = {
+ { .compatible = "mediatek,mt7622-mcucfg" },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_mcucfg) = {
+ .name = "mt7622-mcucfg",
+ .id = UCLASS_SYSCON,
+ .of_match = mt7622_mcucfg_compat,
+ .probe = mt7622_mcucfg_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt7622-clock-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_apmixed_compat,
+ .probe = mt7622_apmixedsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt7622-clock-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_topckgen_compat,
+ .probe = mt7622_topckgen_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+ .name = "mt7622-clock-infracfg",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_infracfg_compat,
+ .probe = mt7622_infracfg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_pericfg) = {
+ .name = "mt7622-clock-pericfg",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_pericfg_compat,
+ .probe = mt7622_pericfg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_ethsys) = {
+ .name = "mt7622-clock-ethsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_ethsys_compat,
+ .probe = mt7622_ethsys_probe,
+ .bind = mt7622_ethsys_bind,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
+ .name = "mt7622-clock-sgmiisys",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_sgmiisys_compat,
+ .probe = mt7622_sgmiisys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
};
+static const struct mtk_gate_regs ssusb_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+#define GATE_SSUSB(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &ssusb_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+}
+
+static const struct mtk_gate ssusb_cgs[] = {
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
+ GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
+ GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
+ GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
+ GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_TO_USB3_MCU, 7),
+ GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_TO_USB3_DMA, 8),
+};
+
static const struct mtk_clk_tree mt7629_clk_tree = {
.xtal_rate = 40 * MHZ,
.xtal2_rate = 20 * MHZ,
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs);
}
+static int mt7629_ssusbsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs);
+}
+
static const struct udevice_id mt7629_apmixed_compat[] = {
{ .compatible = "mediatek,mt7629-apmixedsys" },
{ }
{ }
};
+static const struct udevice_id mt7629_ssusbsys_compat[] = {
+ { .compatible = "mediatek,mt7629-ssusbsys" },
+ { }
+};
+
static const struct udevice_id mt7629_mcucfg_compat[] = {
{ .compatible = "mediatek,mt7629-mcucfg" },
{ }
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
+
+U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+ .name = "mt7629-clock-ssusbsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7629_ssusbsys_compat,
+ .probe = mt7629_ssusbsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8512 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8512-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8512_PLL_FMAX (3800UL * MHZ)
+#define MT8512_PLL_FMIN (1500UL * MHZ)
+#define MT8512_CON0_RST_BAR BIT(23)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = MT8512_CON0_RST_BAR, \
+ .fmax = MT8512_PLL_FMAX, \
+ .fmin = MT8512_PLL_FMIN, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = 8, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcw_chg_reg = _pcw_chg_reg, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001,
+ 0, 22, 0x0310, 24, 0x0310, 0, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001,
+ HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
+ PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001,
+ HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
+ PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001,
+ 0, 22, 0x0354, 24, 0x0354, 0, 0),
+ PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001,
+ 0, 32, 0x0320, 24, 0x0324, 0, 0x0320),
+ PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001,
+ 0, 32, 0x0364, 24, 0x0368, 0, 0x0364),
+ PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x00000001,
+ 0, 22, 0x0378, 24, 0x0378, 0, 0),
+ PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001,
+ 0, 22, 0x0394, 24, 0x0394, 0, 0),
+ PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x00000001,
+ 0, 22, 0x03A4, 24, 0x03A4, 0, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+ FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
+ FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
+ FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+ FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL2, 1, 2),
+ FACTOR1(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
+ FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
+ FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
+ FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
+ FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
+ FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
+ FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
+ FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
+ FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
+ FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
+ FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
+ FACTOR0(CLK_TOP_TCONPLL_D2, CLK_APMIXED_TCONPLL, 1, 2),
+ FACTOR0(CLK_TOP_TCONPLL_D4, CLK_APMIXED_TCONPLL, 1, 4),
+ FACTOR0(CLK_TOP_TCONPLL_D8, CLK_APMIXED_TCONPLL, 1, 8),
+ FACTOR0(CLK_TOP_TCONPLL_D16, CLK_APMIXED_TCONPLL, 1, 16),
+ FACTOR0(CLK_TOP_TCONPLL_D32, CLK_APMIXED_TCONPLL, 1, 32),
+ FACTOR0(CLK_TOP_TCONPLL_D64, CLK_APMIXED_TCONPLL, 1, 64),
+ FACTOR1(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 2, 13),
+ FACTOR1(CLK_TOP_USB20_192M_D2, CLK_TOP_USB20_192M, 1, 2),
+ FACTOR1(CLK_TOP_USB20_192M_D4_T, CLK_TOP_USB20_192M, 1, 4),
+ FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+ FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2),
+ FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3),
+ FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4),
+ FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8),
+ FACTOR0(CLK_TOP_APLL1_D16, CLK_APMIXED_APLL1, 1, 16),
+ FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+ FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2),
+ FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3),
+ FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4),
+ FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8),
+ FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16),
+ FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+ FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2),
+ FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
+ FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
+ FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1),
+ FACTOR0(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2),
+ FACTOR0(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4),
+ FACTOR0(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8),
+ FACTOR0(CLK_TOP_IPPLL, CLK_APMIXED_IPPLL, 1, 1),
+ FACTOR0(CLK_TOP_IPPLL_D2, CLK_APMIXED_IPPLL, 1, 2),
+ FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2),
+};
+
+static const int axi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_CLK32K
+};
+
+static const int mem_parents[] = {
+ CLK_TOP_DSPPLL,
+ CLK_TOP_IPPLL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int uart_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int spi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int spis_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_SYSPLL4_D2
+};
+
+static const int msdc50_0_hc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL2_D2
+};
+
+static const int msdc50_0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int msdc50_2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MSDCPLL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4
+};
+
+static const int audio_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_APLL1_D4,
+ CLK_TOP_APLL2_D4
+};
+
+static const int aud_intbus_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_APLL2_D8,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_APLL1_D8,
+ CLK_TOP_UNIVPLL3_D4
+};
+
+static const int hapll1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1,
+ CLK_TOP_APLL1_D2,
+ CLK_TOP_APLL1_D3,
+ CLK_TOP_APLL1_D4,
+ CLK_TOP_APLL1_D8,
+ CLK_TOP_APLL1_D16,
+ CLK_TOP_SYS_26M_D2
+};
+
+static const int hapll2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2,
+ CLK_TOP_APLL2_D2,
+ CLK_TOP_APLL2_D3,
+ CLK_TOP_APLL2_D4,
+ CLK_TOP_APLL2_D8,
+ CLK_TOP_APLL2_D16,
+ CLK_TOP_SYS_26M_D2
+};
+
+static const int asm_l_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL_D5
+};
+
+static const int aud_spdif_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_TOP_DSPPLL
+};
+
+static const int aud_1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1
+};
+
+static const int aud_2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2
+};
+
+static const int ssusb_sys_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL3_D2
+};
+
+static const int spm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int i2c_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL2_D8,
+ CLK_TOP_CLK32K
+};
+
+static const int pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_CLK32K
+};
+
+static const int dsp_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DSPPLL,
+ CLK_TOP_DSPPLL_D2,
+ CLK_TOP_DSPPLL_D4,
+ CLK_TOP_DSPPLL_D8,
+ CLK_TOP_APLL2_D4,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_CLK32K
+};
+
+static const int nfi2x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_SYSPLL_D7,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_MSDCPLL_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int spinfi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL3_D2
+};
+
+static const int ecc_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL_D5,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int gcpu_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2
+};
+
+static const int gcpu_cpm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4
+};
+
+static const int mbist_diag_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYS_26M_D2
+};
+
+static const int ip0_nna_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DSPPLL,
+ CLK_TOP_DSPPLL_D2,
+ CLK_TOP_DSPPLL_D4,
+ CLK_TOP_IPPLL,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_IPPLL_D2,
+ CLK_TOP_MSDCPLL_D2
+};
+
+static const int ip2_wfst_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_IPPLL,
+ CLK_TOP_IPPLL_D2,
+ CLK_TOP_SYS_26M_D2,
+ CLK_TOP_MSDCPLL
+};
+
+static const int sflash_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL1_D16,
+ CLK_TOP_SYSPLL2_D8,
+ CLK_TOP_SYSPLL3_D4,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL1_D8,
+ CLK_TOP_USB20_192M_D2,
+ CLK_TOP_UNIVPLL2_D4
+};
+
+static const int sram_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DSPPLL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_APLL1,
+ CLK_TOP_APLL2,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYS_26M_D2
+};
+
+static const int mm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_SYSPLL_D3,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL_D5,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D3
+};
+
+static const int dpi0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_TCONPLL_D2,
+ CLK_TOP_TCONPLL_D4,
+ CLK_TOP_TCONPLL_D8,
+ CLK_TOP_TCONPLL_D16,
+ CLK_TOP_TCONPLL_D32,
+ CLK_TOP_TCONPLL_D64
+};
+
+static const int dbg_atclk_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int occ_104m_parents[] = {
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int occ_68m_parents[] = {
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int occ_182m_parents[] = {
+ CLK_TOP_SYSPLL2_D2,
+ CLK_TOP_UNIVPLL1_D4,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents,
+ 0x040, 0x044, 0x048, 0, 3, 7,
+ 0x4, 0, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents,
+ 0x040, 0x044, 0x048, 8, 2, 15,
+ 0x4, 1, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents,
+ 0x040, 0x044, 0x048, 16, 1, 23,
+ 0x4, 2, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents,
+ 0x040, 0x044, 0x048, 24, 3, 31,
+ 0x4, 3, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_1 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents,
+ 0x050, 0x054, 0x058, 0, 3, 7,
+ 0x4, 4, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents,
+ 0x050, 0x054, 0x058, 8, 2, 15,
+ 0x4, 5, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents,
+ 0x050, 0x054, 0x058, 16, 2, 23,
+ 0x4, 6, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents,
+ 0x050, 0x054, 0x058, 24, 3, 31,
+ 0x4, 7, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_2 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents,
+ 0x060, 0x064, 0x068, 0, 3, 7,
+ 0x4, 8, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents,
+ 0x060, 0x064, 0x068, 8, 3, 15,
+ 0x4, 9, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents,
+ 0x060, 0x064, 0x068, 16, 2, 23,
+ 0x4, 10, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents,
+ 0x060, 0x064, 0x068, 24, 3, 31,
+ 0x4, 11, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_3 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents,
+ 0x070, 0x074, 0x078, 0, 3, 7,
+ 0x4, 12, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents,
+ 0x070, 0x074, 0x078, 8, 3, 15,
+ 0x4, 13, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents,
+ 0x070, 0x074, 0x078, 16, 3, 23,
+ 0x4, 14, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents,
+ 0x070, 0x074, 0x078, 24, 3, 31,
+ 0x4, 15, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_4 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents,
+ 0x080, 0x084, 0x088, 0, 2, 7,
+ 0x4, 16, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents,
+ 0x080, 0x084, 0x088, 8, 2, 15,
+ 0x4, 17, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents,
+ 0x080, 0x084, 0x088, 16, 2, 23,
+ 0x4, 18, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents,
+ 0x080, 0x084, 0x088, 24, 2, 31,
+ 0x4, 19, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_5 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents,
+ 0x090, 0x094, 0x098, 0, 1, 7,
+ 0x4, 20, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents,
+ 0x090, 0x094, 0x098, 8, 1, 15,
+ 0x4, 21, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents,
+ 0x090, 0x094, 0x098, 16, 2, 23,
+ 0x4, 22, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents,
+ 0x090, 0x094, 0x098, 24, 2, 31,
+ 0x4, 23, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_6 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents,
+ 0x0a0, 0x0a4, 0x0a8, 0, 1, 7,
+ 0x4, 24, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents,
+ 0x0a0, 0x0a4, 0x0a8, 8, 3, 15,
+ 0x4, 25, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents,
+ 0x0a0, 0x0a4, 0x0a8, 16, 3, 23,
+ 0x4, 26, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents,
+ 0x0a0, 0x0a4, 0x0a8, 24, 3, 31,
+ 0x4, 27, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_7 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents,
+ 0x0b0, 0x0b4, 0x0b8, 0, 3, 7,
+ 0x4, 28, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents,
+ 0x0b0, 0x0b4, 0x0b8, 8, 3, 15,
+ 0x4, 29, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents,
+ 0x0b0, 0x0b4, 0x0b8, 16, 2, 23,
+ 0x4, 30, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents,
+ 0x0b0, 0x0b4, 0x0b8, 24, 3, 31,
+ 0x4, 31, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_8 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents,
+ 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
+ 0x8, 0, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents,
+ 0x0c0, 0x0c4, 0x0c8, 8, 1, 15,
+ 0x8, 1, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents,
+ 0x0c0, 0x0c4, 0x0c8, 16, 3, 23,
+ 0x8, 2, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents,
+ 0x0c0, 0x0c4, 0x0c8, 24, 3, 31,
+ 0x8, 3, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_9 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents,
+ 0x0d0, 0x0d4, 0x0d8, 0, 3, 7,
+ 0x8, 4, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents,
+ 0x0d0, 0x0d4, 0x0d8, 8, 3, 15,
+ 0x8, 5, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents,
+ 0x0d0, 0x0d4, 0x0d8, 16, 3, 23,
+ 0x8, 6, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents,
+ 0x0d0, 0x0d4, 0x0d8, 24, 3, 31,
+ 0x8, 7, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_10 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents,
+ 0x0e0, 0x0e4, 0x0e8, 0, 3, 7,
+ 0x8, 8, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents,
+ 0x0e0, 0x0e4, 0x0e8, 8, 2, 15,
+ 0x8, 9, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents,
+ 0x0e0, 0x0e4, 0x0e8, 16, 1, 23,
+ 0x8, 10, CLK_MUX_SETCLR_UPD),
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents,
+ 0x0e0, 0x0e4, 0x0e8, 24, 1, 31,
+ 0x8, 11, CLK_MUX_SETCLR_UPD),
+ /* CLK_CFG_11 */
+ MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents,
+ 0x0ec, 0x0f0, 0x0f4, 0, 2, 7,
+ 0x8, 12, CLK_MUX_SETCLR_UPD),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x104,
+ .clr_ofs = 0x104,
+ .sta_ofs = 0x104,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
+ GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
+ GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
+ GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4_T, 8),
+ GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4_T, 9),
+ GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
+ GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
+};
+
+static const struct mtk_gate_regs infra0_cg_regs = {
+ .set_ofs = 0x294,
+ .clr_ofs = 0x294,
+ .sta_ofs = 0x294,
+};
+
+static const struct mtk_gate_regs infra1_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra3_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra4_cg_regs = {
+ .set_ofs = 0xc0,
+ .clr_ofs = 0xc4,
+ .sta_ofs = 0xc8,
+};
+
+static const struct mtk_gate_regs infra5_cg_regs = {
+ .set_ofs = 0xd0,
+ .clr_ofs = 0xd4,
+ .sta_ofs = 0xd8,
+};
+
+#define GATE_INFRA0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA2(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA3(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA4(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra4_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_INFRA5(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate infra_clks[] = {
+ /* INFRA0 */
+ GATE_INFRA0(CLK_INFRA_DSP_AXI, CLK_TOP_AXI_SEL, 8),
+ /* INFRA1 */
+ GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6),
+ GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8),
+ GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9),
+ GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10),
+ GATE_INFRA1(CLK_INFRA_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
+ GATE_INFRA1(CLK_INFRA_PWM1, CLK_TOP_PWM_SEL, 16),
+ GATE_INFRA1(CLK_INFRA_PWM2, CLK_TOP_PWM_SEL, 17),
+ GATE_INFRA1(CLK_INFRA_PWM3, CLK_TOP_PWM_SEL, 18),
+ GATE_INFRA1(CLK_INFRA_PWM4, CLK_TOP_PWM_SEL, 19),
+ GATE_INFRA1(CLK_INFRA_PWM5, CLK_TOP_PWM_SEL, 20),
+ GATE_INFRA1(CLK_INFRA_PWM, CLK_TOP_PWM_SEL, 21),
+ GATE_INFRA1(CLK_INFRA_UART0, CLK_TOP_UART_SEL, 22),
+ GATE_INFRA1(CLK_INFRA_UART1, CLK_TOP_UART_SEL, 23),
+ GATE_INFRA1(CLK_INFRA_UART2, CLK_TOP_UART_SEL, 24),
+ GATE_INFRA1(CLK_INFRA_DSP_UART, CLK_TOP_UART_SEL, 26),
+ GATE_INFRA1(CLK_INFRA_GCE_26M, CLK_TOP_CLK26M, 27),
+ GATE_INFRA1(CLK_INFRA_CQDMA_FPC, CLK_TOP_AXI_SEL, 28),
+ GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31),
+ /* INFRA2 */
+ GATE_INFRA2(CLK_INFRA_SPI, CLK_TOP_SPI_SEL, 1),
+ GATE_INFRA2(CLK_INFRA_MSDC0, CLK_TOP_MSDC50_0_HC_SEL, 2),
+ GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, 4),
+ GATE_INFRA2(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7),
+ GATE_INFRA2(CLK_INFRA_GCPU, CLK_TOP_AXI_SEL, 8),
+ GATE_INFRA2(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 9),
+ GATE_INFRA2(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10),
+ GATE_INFRA2(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14),
+ GATE_INFRA2(CLK_INFRA_AP_DMA, CLK_TOP_AXI_SEL, 18),
+ GATE_INFRA2(CLK_INFRA_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
+ GATE_INFRA2(CLK_INFRA_AUDIO, CLK_TOP_AXI_SEL, 25),
+ GATE_INFRA2(CLK_INFRA_FLASHIF, CLK_TOP_SFLASH_SEL, 29),
+ /* INFRA3 */
+ GATE_INFRA3(CLK_INFRA_PWM_FB6, CLK_TOP_PWM_SEL, 0),
+ GATE_INFRA3(CLK_INFRA_PWM_FB7, CLK_TOP_PWM_SEL, 1),
+ GATE_INFRA3(CLK_INFRA_AUD_ASRC, CLK_TOP_AXI_SEL, 3),
+ GATE_INFRA3(CLK_INFRA_AUD_26M, CLK_TOP_CLK26M, 4),
+ GATE_INFRA3(CLK_INFRA_SPIS, CLK_TOP_AXI_SEL, 6),
+ GATE_INFRA3(CLK_INFRA_CQ_DMA, CLK_TOP_AXI_SEL, 27),
+ /* INFRA4 */
+ GATE_INFRA4(CLK_INFRA_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
+ GATE_INFRA4(CLK_INFRA_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
+ GATE_INFRA4(CLK_INFRA_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
+ GATE_INFRA4(CLK_INFRA_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
+ GATE_INFRA4(CLK_INFRA_IRRX_26M, CLK_TOP_AXI_SEL, 22),
+ GATE_INFRA4(CLK_INFRA_IRRX_32K, CLK_TOP_CLK32K, 23),
+ GATE_INFRA4(CLK_INFRA_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
+ GATE_INFRA4(CLK_INFRA_I2C1_AXI, CLK_TOP_I2C_SEL, 25),
+ GATE_INFRA4(CLK_INFRA_I2C2_AXI, CLK_TOP_I2C_SEL, 26),
+ /* INFRA5 */
+ GATE_INFRA5(CLK_INFRA_NFI, CLK_TOP_NFI2X_CK_D2, 1),
+ GATE_INFRA5(CLK_INFRA_NFIECC, CLK_TOP_NFI2X_CK_D2, 2),
+ GATE_INFRA5(CLK_INFRA_NFI_HCLK, CLK_TOP_AXI_SEL, 3),
+ GATE_INFRA5(CLK_INFRA_SUSB_133, CLK_TOP_AXI_SEL, 7),
+ GATE_INFRA5(CLK_INFRA_USB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9),
+ GATE_INFRA5(CLK_INFRA_USB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
+};
+
+static const struct mtk_clk_tree mt8512_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .xtal2_rate = 26 * MHZ,
+ .fdivs_offs = CLK_TOP_SYSPLL1_D2,
+ .muxes_offs = CLK_TOP_AXI_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static int mt8512_apmixedsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8512_clk_tree);
+}
+
+static int mt8512_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8512_clk_tree);
+}
+
+static int mt8512_topckgen_cg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks);
+}
+
+static int mt8512_infracfg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks);
+}
+
+static const struct udevice_id mt8512_apmixed_compat[] = {
+ { .compatible = "mediatek,mt8512-apmixedsys", },
+ { }
+};
+
+static const struct udevice_id mt8512_topckgen_compat[] = {
+ { .compatible = "mediatek,mt8512-topckgen", },
+ { }
+};
+
+static const struct udevice_id mt8512_topckgen_cg_compat[] = {
+ { .compatible = "mediatek,mt8512-topckgen-cg", },
+ { }
+};
+
+static const struct udevice_id mt8512_infracfg_compat[] = {
+ { .compatible = "mediatek,mt8512-infracfg", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt8512-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt8512_apmixed_compat,
+ .probe = mt8512_apmixedsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt8512-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8512_topckgen_compat,
+ .probe = mt8512_topckgen_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+ .name = "mt8512-topckgen-cg",
+ .id = UCLASS_CLK,
+ .of_match = mt8512_topckgen_cg_compat,
+ .probe = mt8512_topckgen_cg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+ .name = "mt8512-infracfg",
+ .id = UCLASS_CLK,
+ .of_match = mt8512_infracfg_compat,
+ .probe = mt8512_infracfg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
* this function is recursively called to find the parent to calculate
* the accurate frequency.
*/
-static int mtk_clk_find_parent_rate(struct clk *clk, int id,
+static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
const struct driver *drv)
{
struct clk parent = { .id = id, };
if (++index == mux->num_parents)
return -EINVAL;
- /* switch mux to a select parent */
- val = readl(base + mux->mux_reg);
- val &= ~(mux->mux_mask << mux->mux_shift);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = (mux->mux_mask << mux->mux_shift);
+ writel(val, base + mux->mux_clr_reg);
- val |= index << mux->mux_shift;
- writel(val, base + mux->mux_reg);
+ val = (index << mux->mux_shift);
+ writel(val, base + mux->mux_set_reg);
+
+ if (mux->upd_shift >= 0)
+ writel(BIT(mux->upd_shift), base + mux->upd_reg);
+ } else {
+ /* switch mux to a select parent */
+ val = readl(base + mux->mux_reg);
+ val &= ~(mux->mux_mask << mux->mux_shift);
+
+ val |= index << mux->mux_shift;
+ writel(val, base + mux->mux_reg);
+ }
return 0;
}
{
int pcwbits = pll->pcwbits;
int pcwfbits;
+ int ibits;
u64 vco;
u8 c = 0;
/* The fractional part of the PLL divider. */
- pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;
vco = (u64)fin * pcw;
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
- u32 val;
+ u32 val, chg;
/* set postdiv */
val = readl(priv->base + pll->pd_reg);
/* set pcw */
val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
val |= pcw << pll->pcw_shift;
- val &= ~CON1_PCW_CHG;
- writel(val, priv->base + pll->pcw_reg);
- val |= CON1_PCW_CHG;
- writel(val, priv->base + pll->pcw_reg);
+ if (pll->pcw_chg_reg) {
+ chg = readl(priv->base + pll->pcw_chg_reg);
+ chg |= CON1_PCW_CHG;
+ writel(val, priv->base + pll->pcw_reg);
+ writel(chg, priv->base + pll->pcw_chg_reg);
+ } else {
+ val |= CON1_PCW_CHG;
+ writel(val, priv->base + pll->pcw_reg);
+ }
udelay(20);
}
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
- unsigned long fmin = 1000 * MHZ;
+ unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ;
u64 _pcw;
+ int ibits;
u32 val;
if (freq > pll->fmax)
}
/* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
- _pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS);
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ _pcw = ((u64)freq << val) << (pll->pcwbits - ibits);
do_div(_pcw, priv->tree->xtal2_rate);
*pcw = (u32)_pcw;
return rate;
}
-static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
+static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
return mtk_factor_recalc_rate(fdiv, rate);
}
-static int mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
+static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_composite *mux = &priv->tree->muxes[off];
return 0;
/* enable clock gate */
- val = readl(priv->base + mux->gate_reg);
- val &= ~BIT(mux->gate_shift);
- writel(val, priv->base + mux->gate_reg);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = BIT(mux->gate_shift);
+ writel(val, priv->base + mux->mux_clr_reg);
+ } else {
+ val = readl(priv->base + mux->gate_reg);
+ val &= ~BIT(mux->gate_shift);
+ writel(val, priv->base + mux->gate_reg);
+ }
if (mux->flags & CLK_DOMAIN_SCPSYS) {
/* enable scpsys clock off control */
return 0;
/* disable clock gate */
- val = readl(priv->base + mux->gate_reg);
- val |= BIT(mux->gate_shift);
- writel(val, priv->base + mux->gate_reg);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = BIT(mux->gate_shift);
+ writel(val, priv->base + mux->mux_set_reg);
+ } else {
+ val = readl(priv->base + mux->gate_reg);
+ val |= BIT(mux->gate_shift);
+ writel(val, priv->base + mux->gate_reg);
+ }
return 0;
}
#define HAVE_RST_BAR BIT(0)
#define CLK_DOMAIN_SCPSYS BIT(0)
+#define CLK_MUX_SETCLR_UPD BIT(1)
#define CLK_GATE_SETCLR BIT(0)
#define CLK_GATE_SETCLR_INV BIT(1)
u32 flags;
u32 rst_bar_mask;
u64 fmax;
+ u64 fmin;
int pcwbits;
+ int pcwibits;
u32 pcw_reg;
int pcw_shift;
+ u32 pcw_chg_reg;
};
/**
const int id;
const int *parent;
u32 mux_reg;
+ u32 mux_set_reg;
+ u32 mux_clr_reg;
+ u32 upd_reg;
u32 gate_reg;
u32 mux_mask;
signed char mux_shift;
+ signed char upd_shift;
signed char gate_shift;
signed char num_parents;
u16 flags;
.flags = 0, \
}
+#define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
+ _mux_clr_ofs, _shift, _width, _gate, \
+ _upd_ofs, _upd, _flags) { \
+ .id = _id, \
+ .mux_reg = _mux_ofs, \
+ .mux_set_reg = _mux_set_ofs, \
+ .mux_clr_reg = _mux_clr_ofs, \
+ .upd_reg = _upd_ofs, \
+ .upd_shift = _upd, \
+ .mux_shift = _shift, \
+ .mux_mask = BIT(_width) - 1, \
+ .gate_reg = _mux_ofs, \
+ .gate_shift = _gate, \
+ .parent = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .flags = _flags, \
+ }
+
struct mtk_gate_regs {
u32 sta_ofs;
u32 clr_ofs;
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
- defined(CONFIG_ARCH_IMX8)
+ defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
[3] = GPIO4_BASE_ADDR,
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
- defined(CONFIG_ARCH_IMX8)
+ defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
[4] = GPIO5_BASE_ADDR,
-#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M))
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+ defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT1050))
[5] = GPIO6_BASE_ADDR,
#endif
#endif
config FSL_USDHC
bool "Freescale/NXP i.MX uSDHC controller support"
- depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || TARGET_S32V234EVB
+ depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT || TARGET_S32V234EVB
select FSL_ESDHC_IMX
help
This enables the Ultra Secured Digital Host Controller enhancements
uint vendorspec;
uint mmcboot;
uint vendorspec2;
- uint tuning_ctrl; /* on i.MX6/7/8 */
+ uint tuning_ctrl; /* on i.MX6/7/8/RT */
char reserved5[44];
uint hostver; /* Host controller version register */
char reserved6[4]; /* reserved */
* Following is used when Driver Model is enabled for MMC
* @dev: pointer for the device
* @non_removable: 0: removable; 1: non-removable
+ * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
* @wp_enable: 1: enable checking wp; 0: no check
* @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
* @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
#endif
struct udevice *dev;
int non_removable;
+ int broken_cd;
int wp_enable;
int vs18_enable;
u32 flags;
#if CONFIG_IS_ENABLED(DM_MMC)
if (priv->non_removable)
return 1;
+
+ if (priv->broken_cd)
+ return 1;
#if CONFIG_IS_ENABLED(DM_GPIO)
if (dm_gpio_is_valid(&priv->cd_gpio))
return dm_gpio_get_value(&priv->cd_gpio);
ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
priv->strobe_dll_delay_target = val;
+ if (dev_read_bool(dev, "broken-cd"))
+ priv->broken_cd = 1;
+
if (dev_read_bool(dev, "non-removable")) {
priv->non_removable = 1;
} else {
init_clk_usdhc(dev->seq);
- if (CONFIG_IS_ENABLED(CLK)) {
- /* Assigned clock already set clock */
- ret = clk_get_by_name(dev, "per", &priv->per_clk);
- if (ret) {
- printf("Failed to get per_clk\n");
- return ret;
- }
- ret = clk_enable(&priv->per_clk);
- if (ret) {
- printf("Failed to enable per_clk\n");
- return ret;
- }
+#if CONFIG_IS_ENABLED(CLK)
+ /* Assigned clock already set clock */
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
+ if (ret) {
+ printf("Failed to get per_clk\n");
+ return ret;
+ }
+ ret = clk_enable(&priv->per_clk);
+ if (ret) {
+ printf("Failed to enable per_clk\n");
+ return ret;
+ }
- priv->sdhc_clk = clk_get_rate(&priv->per_clk);
- } else {
- priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
- if (priv->sdhc_clk <= 0) {
- dev_err(dev, "Unable to get clk for %s\n", dev->name);
- return -EINVAL;
- }
+ priv->sdhc_clk = clk_get_rate(&priv->per_clk);
+#else
+ priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+ if (priv->sdhc_clk <= 0) {
+ dev_err(dev, "Unable to get clk for %s\n", dev->name);
+ return -EINVAL;
}
+#endif
ret = fsl_esdhc_init(priv, plat);
if (ret) {
{ .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
{ .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
+ { .compatible = "fsl,imxrt-usdhc", },
{ .compatible = "fsl,esdhc", },
{ /* sentinel */ }
};
#include <mmc.h>
#include <errno.h>
#include <malloc.h>
+#include <mapmem.h>
#include <stdbool.h>
-#include <watchdog.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
#define SDC_FIFO_CFG_WRVALIDSEL BIT(24)
#define SDC_FIFO_CFG_RDVALIDSEL BIT(25)
+/* EMMC_TOP_CONTROL mask */
+#define PAD_RXDLY_SEL BIT(0)
+#define DELAY_EN BIT(1)
+#define PAD_DAT_RD_RXDLY2 (0x1f << 2)
+#define PAD_DAT_RD_RXDLY (0x1f << 7)
+#define PAD_DAT_RD_RXDLY_S 7
+#define PAD_DAT_RD_RXDLY2_SEL BIT(12)
+#define PAD_DAT_RD_RXDLY_SEL BIT(13)
+#define DATA_K_VALUE_SEL BIT(14)
+#define SDC_RX_ENH_EN BIT(15)
+
+/* EMMC_TOP_CMD mask */
+#define PAD_CMD_RXDLY2 (0x1f << 0)
+#define PAD_CMD_RXDLY (0x1f << 5)
+#define PAD_CMD_RXDLY_S 5
+#define PAD_CMD_RD_RXDLY2_SEL BIT(10)
+#define PAD_CMD_RD_RXDLY_SEL BIT(11)
+#define PAD_CMD_TX_DLY (0x1f << 12)
+
/* SDC_CFG_BUSWIDTH */
#define MSDC_BUS_1BITS 0x0
#define MSDC_BUS_4BITS 0x1
u32 sdc_fifo_cfg;
};
+struct msdc_top_regs {
+ u32 emmc_top_control;
+ u32 emmc_top_cmd;
+ u32 emmc50_pad_ctl0;
+ u32 emmc50_pad_ds_tune;
+ u32 emmc50_pad_dat0_tune;
+ u32 emmc50_pad_dat1_tune;
+ u32 emmc50_pad_dat2_tune;
+ u32 emmc50_pad_dat3_tune;
+ u32 emmc50_pad_dat4_tune;
+ u32 emmc50_pad_dat5_tune;
+ u32 emmc50_pad_dat6_tune;
+ u32 emmc50_pad_dat7_tune;
+};
+
struct msdc_compatible {
u8 clk_div_bits;
u8 sclk_cycle_shift;
struct msdc_host {
struct mtk_sd_regs *base;
+ struct msdc_top_regs *top_base;
struct mmc *mmc;
struct msdc_compatible *dev_comp;
blocks = data->blocks;
writel(CMD_INTS_MASK, &host->base->msdc_int);
+ writel(DATA_INTS_MASK, &host->base->msdc_int);
writel(blocks, &host->base->sdc_blk_num);
writel(cmd->cmdarg, &host->base->sdc_arg);
writel(rawcmd, &host->base->sdc_cmd);
u32 size;
int ret;
- WATCHDOG_RESET();
-
if (data->flags == MMC_DATA_WRITE)
host->last_data_write = 1;
- writel(DATA_INTS_MASK, &host->base->msdc_int);
-
size = data->blocks * data->blocksize;
if (data->flags == MMC_DATA_WRITE)
return delay_phase;
}
+static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
+{
+ void __iomem *tune_reg = &host->base->pad_tune;
+
+ if (host->dev_comp->pad_tune0)
+ tune_reg = &host->base->pad_tune0;
+
+ if (host->top_base)
+ clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
+ value << PAD_CMD_RXDLY_S);
+ else
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ value << MSDC_PAD_TUNE_CMDRDLY_S);
+}
+
+static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
+{
+ void __iomem *tune_reg = &host->base->pad_tune;
+
+ if (host->dev_comp->pad_tune0)
+ tune_reg = &host->base->pad_tune0;
+
+ if (host->top_base)
+ clrsetbits_le32(&host->top_base->emmc_top_control,
+ PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
+ else
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ value << MSDC_PAD_TUNE_DATRRDLY_S);
+}
+
static int hs400_tune_response(struct udevice *dev, u32 opcode)
{
struct msdc_plat *plat = dev_get_platdata(dev);
PAD_CMD_TUNE_RX_DLY3_S);
final_delay = final_cmd_delay.final_phase;
- dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
+ dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
return final_delay == 0xff ? -EIO : 0;
}
u32 rise_delay = 0, fall_delay = 0;
struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
u8 final_delay, final_maxlen;
- void __iomem *tune_reg = &host->base->pad_tune;
int i, ret;
- if (host->dev_comp->pad_tune0)
- tune_reg = &host->base->pad_tune0;
-
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
- i << MSDC_PAD_TUNE_CMDRDLY_S);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
- i << MSDC_PAD_TUNE_DATRRDLY_S);
-
+ msdc_set_cmd_delay(host, i);
+ msdc_set_data_delay(host, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
rise_delay |= (1 << i);
setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
- i << MSDC_PAD_TUNE_CMDRDLY_S);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
- i << MSDC_PAD_TUNE_DATRRDLY_S);
-
+ msdc_set_cmd_delay(host, i);
+ msdc_set_data_delay(host, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
fall_delay |= (1 << i);
if (final_maxlen == final_rise_delay.maxlen) {
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
- final_rise_delay.final_phase <<
- MSDC_PAD_TUNE_CMDRDLY_S);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
- final_rise_delay.final_phase <<
- MSDC_PAD_TUNE_DATRRDLY_S);
final_delay = final_rise_delay.final_phase;
} else {
setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
- final_fall_delay.final_phase <<
- MSDC_PAD_TUNE_CMDRDLY_S);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
- final_fall_delay.final_phase <<
- MSDC_PAD_TUNE_DATRRDLY_S);
final_delay = final_fall_delay.final_phase;
}
- dev_err(dev, "Final pad delay: %x\n", final_delay);
+ msdc_set_cmd_delay(host, final_delay);
+ msdc_set_data_delay(host, final_delay);
+ dev_info(dev, "Final pad delay: %x\n", final_delay);
return final_delay == 0xff ? -EIO : 0;
}
3 << MSDC_PB2_RESPWAIT_S);
if (host->dev_comp->enhance_rx) {
- setbits_le32(&host->base->sdc_adv_cfg0,
- SDC_RX_ENHANCE_EN);
+ if (host->top_base)
+ setbits_le32(&host->top_base->emmc_top_control,
+ SDC_RX_ENH_EN);
+ else
+ setbits_le32(&host->base->sdc_adv_cfg0,
+ SDC_RX_ENHANCE_EN);
} else {
clrsetbits_le32(&host->base->patch_bit2,
MSDC_PB2_RESPSTSENSEL_M,
cfg->f_min = host->src_clk_freq / (4 * 255);
else
cfg->f_min = host->src_clk_freq / (4 * 4095);
- cfg->f_max = host->src_clk_freq / 2;
cfg->b_max = 1024;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
struct msdc_plat *plat = dev_get_platdata(dev);
struct msdc_host *host = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
+ fdt_addr_t base, top_base;
int ret;
- host->base = (void *)dev_read_addr(dev);
- if (!host->base)
+ base = dev_read_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
return -EINVAL;
+ host->base = map_sysmem(base, 0);
+
+ top_base = dev_read_addr_index(dev, 1);
+ if (top_base == FDT_ADDR_T_NONE)
+ host->top_base = NULL;
+ else
+ host->top_base = map_sysmem(top_base, 0);
ret = mmc_of_parse(dev, cfg);
if (ret)
.enhance_rx = false
};
+static const struct msdc_compatible mt7622_compat = {
+ .clk_div_bits = 12,
+ .pad_tune0 = true,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+};
+
static const struct msdc_compatible mt7623_compat = {
.clk_div_bits = 12,
.sclk_cycle_shift = 20,
.enhance_rx = false
};
+static const struct msdc_compatible mt8512_compat = {
+ .clk_div_bits = 12,
+ .sclk_cycle_shift = 20,
+ .pad_tune0 = true,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+};
+
static const struct msdc_compatible mt8516_compat = {
.clk_div_bits = 12,
.sclk_cycle_shift = 20,
static const struct udevice_id msdc_ids[] = {
{ .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
+ { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat },
{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
+ { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
{ .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
{ .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
{}
struct mtk_phy_instance *instance = tphy->phys[phy->id];
int ret;
- /* we may use a fixed-clock here */
ret = clk_enable(&instance->ref_clk);
- if (ret && ret != -ENOSYS)
+ if (ret)
return ret;
switch (instance->type) {
tphy->phys[index] = instance;
index++;
- err = clk_get_by_index_nodev(subnode, 0, &instance->ref_clk);
+ err = clk_get_optional_nodev(subnode, "ref",
+ &instance->ref_clk);
if (err)
return err;
}
depends on PINCTRL_GENERIC
bool
+config PINCTRL_MT7622
+ bool "MT7622 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT7623
bool "MT7623 SoC pinctrl driver"
select PINCTRL_MTK
bool "MT7629 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT8512
+ bool "MT8512 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT8516
bool "MT8516 SoC pinctrl driver"
select PINCTRL_MTK
obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
+obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dm.h>
+
+#include "pinctrl-mtk-common.h"
+
+#define MT7622_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1)
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, 0)
+
+#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, 1)
+
+static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
+ PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
+ PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
+ PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
+ PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
+ PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
+ PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
+ PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
+ PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
+ PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
+ PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
+ PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
+ PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
+ PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
+ PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
+ PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
+ PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
+ PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
+ PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
+ PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
+ PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
+ PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
+ PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
+ PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
+ PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
+ PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
+ PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
+ PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
+ PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
+ PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
+ PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
+ PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
+ PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
+ PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
+ PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
+ PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
+ PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
+ PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
+ PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
+ PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
+ PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
+ PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
+ PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
+ PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
+ PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
+ PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
+ PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
+ PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
+ PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
+ PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
+ PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
+ PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
+ PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
+ PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
+ PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
+ PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
+ PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
+ PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
+ PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
+ PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
+ PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
+ PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
+ PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
+ PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
+ PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
+};
+
+static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
+ [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
+ [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
+};
+
+static const struct mtk_pin_desc mt7622_pins[] = {
+ MT7622_PIN(0, "GPIO_A"),
+ MT7622_PIN(1, "I2S1_IN"),
+ MT7622_PIN(2, "I2S1_OUT"),
+ MT7622_PIN(3, "I2S_BCLK"),
+ MT7622_PIN(4, "I2S_WS"),
+ MT7622_PIN(5, "I2S_MCLK"),
+ MT7622_PIN(6, "TXD0"),
+ MT7622_PIN(7, "RXD0"),
+ MT7622_PIN(8, "SPI_WP"),
+ MT7622_PIN(9, "SPI_HOLD"),
+ MT7622_PIN(10, "SPI_CLK"),
+ MT7622_PIN(11, "SPI_MOSI"),
+ MT7622_PIN(12, "SPI_MISO"),
+ MT7622_PIN(13, "SPI_CS"),
+ MT7622_PIN(14, "I2C_SDA"),
+ MT7622_PIN(15, "I2C_SCL"),
+ MT7622_PIN(16, "I2S2_IN"),
+ MT7622_PIN(17, "I2S3_IN"),
+ MT7622_PIN(18, "I2S4_IN"),
+ MT7622_PIN(19, "I2S2_OUT"),
+ MT7622_PIN(20, "I2S3_OUT"),
+ MT7622_PIN(21, "I2S4_OUT"),
+ MT7622_PIN(22, "GPIO_B"),
+ MT7622_PIN(23, "MDC"),
+ MT7622_PIN(24, "MDIO"),
+ MT7622_PIN(25, "G2_TXD0"),
+ MT7622_PIN(26, "G2_TXD1"),
+ MT7622_PIN(27, "G2_TXD2"),
+ MT7622_PIN(28, "G2_TXD3"),
+ MT7622_PIN(29, "G2_TXEN"),
+ MT7622_PIN(30, "G2_TXC"),
+ MT7622_PIN(31, "G2_RXD0"),
+ MT7622_PIN(32, "G2_RXD1"),
+ MT7622_PIN(33, "G2_RXD2"),
+ MT7622_PIN(34, "G2_RXD3"),
+ MT7622_PIN(35, "G2_RXDV"),
+ MT7622_PIN(36, "G2_RXC"),
+ MT7622_PIN(37, "NCEB"),
+ MT7622_PIN(38, "NWEB"),
+ MT7622_PIN(39, "NREB"),
+ MT7622_PIN(40, "NDL4"),
+ MT7622_PIN(41, "NDL5"),
+ MT7622_PIN(42, "NDL6"),
+ MT7622_PIN(43, "NDL7"),
+ MT7622_PIN(44, "NRB"),
+ MT7622_PIN(45, "NCLE"),
+ MT7622_PIN(46, "NALE"),
+ MT7622_PIN(47, "NDL0"),
+ MT7622_PIN(48, "NDL1"),
+ MT7622_PIN(49, "NDL2"),
+ MT7622_PIN(50, "NDL3"),
+ MT7622_PIN(51, "MDI_TP_P0"),
+ MT7622_PIN(52, "MDI_TN_P0"),
+ MT7622_PIN(53, "MDI_RP_P0"),
+ MT7622_PIN(54, "MDI_RN_P0"),
+ MT7622_PIN(55, "MDI_TP_P1"),
+ MT7622_PIN(56, "MDI_TN_P1"),
+ MT7622_PIN(57, "MDI_RP_P1"),
+ MT7622_PIN(58, "MDI_RN_P1"),
+ MT7622_PIN(59, "MDI_RP_P2"),
+ MT7622_PIN(60, "MDI_RN_P2"),
+ MT7622_PIN(61, "MDI_TP_P2"),
+ MT7622_PIN(62, "MDI_TN_P2"),
+ MT7622_PIN(63, "MDI_TP_P3"),
+ MT7622_PIN(64, "MDI_TN_P3"),
+ MT7622_PIN(65, "MDI_RP_P3"),
+ MT7622_PIN(66, "MDI_RN_P3"),
+ MT7622_PIN(67, "MDI_RP_P4"),
+ MT7622_PIN(68, "MDI_RN_P4"),
+ MT7622_PIN(69, "MDI_TP_P4"),
+ MT7622_PIN(70, "MDI_TN_P4"),
+ MT7622_PIN(71, "PMIC_SCL"),
+ MT7622_PIN(72, "PMIC_SDA"),
+ MT7622_PIN(73, "SPIC1_CLK"),
+ MT7622_PIN(74, "SPIC1_MOSI"),
+ MT7622_PIN(75, "SPIC1_MISO"),
+ MT7622_PIN(76, "SPIC1_CS"),
+ MT7622_PIN(77, "GPIO_D"),
+ MT7622_PIN(78, "WATCHDOG"),
+ MT7622_PIN(79, "RTS3_N"),
+ MT7622_PIN(80, "CTS3_N"),
+ MT7622_PIN(81, "TXD3"),
+ MT7622_PIN(82, "RXD3"),
+ MT7622_PIN(83, "PERST0_N"),
+ MT7622_PIN(84, "PERST1_N"),
+ MT7622_PIN(85, "WLED_N"),
+ MT7622_PIN(86, "EPHY_LED0_N"),
+ MT7622_PIN(87, "AUXIN0"),
+ MT7622_PIN(88, "AUXIN1"),
+ MT7622_PIN(89, "AUXIN2"),
+ MT7622_PIN(90, "AUXIN3"),
+ MT7622_PIN(91, "TXD4"),
+ MT7622_PIN(92, "RXD4"),
+ MT7622_PIN(93, "RTS4_N"),
+ MT7622_PIN(94, "CTS4_N"),
+ MT7622_PIN(95, "PWM1"),
+ MT7622_PIN(96, "PWM2"),
+ MT7622_PIN(97, "PWM3"),
+ MT7622_PIN(98, "PWM4"),
+ MT7622_PIN(99, "PWM5"),
+ MT7622_PIN(100, "PWM6"),
+ MT7622_PIN(101, "PWM7"),
+ MT7622_PIN(102, "GPIO_E"),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins. The
+ * hardware probably has multiple combinations of these pinouts.
+ */
+
+/* EMMC */
+static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
+static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+
+static int mt7622_emmc_rst_pins[] = { 37, };
+static int mt7622_emmc_rst_funcs[] = { 1, };
+
+/* LED for EPHY */
+static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
+static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
+static int mt7622_ephy0_led_pins[] = { 86, };
+static int mt7622_ephy0_led_funcs[] = { 0, };
+static int mt7622_ephy1_led_pins[] = { 91, };
+static int mt7622_ephy1_led_funcs[] = { 2, };
+static int mt7622_ephy2_led_pins[] = { 92, };
+static int mt7622_ephy2_led_funcs[] = { 2, };
+static int mt7622_ephy3_led_pins[] = { 93, };
+static int mt7622_ephy3_led_funcs[] = { 2, };
+static int mt7622_ephy4_led_pins[] = { 94, };
+static int mt7622_ephy4_led_funcs[] = { 2, };
+
+/* Embedded Switch */
+static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+ 62, 63, 64, 65, 66, 67, 68, 69, 70, };
+static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
+static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, };
+static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, };
+/* RGMII via ESW */
+static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
+ 67, 68, 69, 70, };
+static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, };
+
+/* RGMII via GMAC1 */
+static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
+ 67, 68, 69, 70, };
+static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, };
+
+/* RGMII via GMAC2 */
+static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
+ 33, 34, 35, 36, };
+static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, };
+
+/* I2C */
+static int mt7622_i2c0_pins[] = { 14, 15, };
+static int mt7622_i2c0_funcs[] = { 0, 0, };
+static int mt7622_i2c1_0_pins[] = { 55, 56, };
+static int mt7622_i2c1_0_funcs[] = { 0, 0, };
+static int mt7622_i2c1_1_pins[] = { 73, 74, };
+static int mt7622_i2c1_1_funcs[] = { 3, 3, };
+static int mt7622_i2c1_2_pins[] = { 87, 88, };
+static int mt7622_i2c1_2_funcs[] = { 0, 0, };
+static int mt7622_i2c2_0_pins[] = { 57, 58, };
+static int mt7622_i2c2_0_funcs[] = { 0, 0, };
+static int mt7622_i2c2_1_pins[] = { 75, 76, };
+static int mt7622_i2c2_1_funcs[] = { 3, 3, };
+static int mt7622_i2c2_2_pins[] = { 89, 90, };
+static int mt7622_i2c2_2_funcs[] = { 0, 0, };
+
+/* I2S */
+static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
+static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
+static int mt7622_i2s1_in_data_pins[] = { 1, };
+static int mt7622_i2s1_in_data_funcs[] = { 0, };
+static int mt7622_i2s2_in_data_pins[] = { 16, };
+static int mt7622_i2s2_in_data_funcs[] = { 0, };
+static int mt7622_i2s3_in_data_pins[] = { 17, };
+static int mt7622_i2s3_in_data_funcs[] = { 0, };
+static int mt7622_i2s4_in_data_pins[] = { 18, };
+static int mt7622_i2s4_in_data_funcs[] = { 0, };
+static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
+static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
+static int mt7622_i2s1_out_data_pins[] = { 2, };
+static int mt7622_i2s1_out_data_funcs[] = { 0, };
+static int mt7622_i2s2_out_data_pins[] = { 19, };
+static int mt7622_i2s2_out_data_funcs[] = { 0, };
+static int mt7622_i2s3_out_data_pins[] = { 20, };
+static int mt7622_i2s3_out_data_funcs[] = { 0, };
+static int mt7622_i2s4_out_data_pins[] = { 21, };
+static int mt7622_i2s4_out_data_funcs[] = { 0, };
+
+/* IR */
+static int mt7622_ir_0_tx_pins[] = { 16, };
+static int mt7622_ir_0_tx_funcs[] = { 4, };
+static int mt7622_ir_1_tx_pins[] = { 59, };
+static int mt7622_ir_1_tx_funcs[] = { 5, };
+static int mt7622_ir_2_tx_pins[] = { 99, };
+static int mt7622_ir_2_tx_funcs[] = { 3, };
+static int mt7622_ir_0_rx_pins[] = { 17, };
+static int mt7622_ir_0_rx_funcs[] = { 4, };
+static int mt7622_ir_1_rx_pins[] = { 60, };
+static int mt7622_ir_1_rx_funcs[] = { 5, };
+static int mt7622_ir_2_rx_pins[] = { 100, };
+static int mt7622_ir_2_rx_funcs[] = { 3, };
+
+/* MDIO */
+static int mt7622_mdc_mdio_pins[] = { 23, 24, };
+static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
+
+/* PCIE */
+static int mt7622_pcie0_0_waken_pins[] = { 14, };
+static int mt7622_pcie0_0_waken_funcs[] = { 2, };
+static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
+static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
+static int mt7622_pcie0_1_waken_pins[] = { 79, };
+static int mt7622_pcie0_1_waken_funcs[] = { 4, };
+static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
+static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
+static int mt7622_pcie1_0_waken_pins[] = { 14, };
+static int mt7622_pcie1_0_waken_funcs[] = { 3, };
+static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
+static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
+
+static int mt7622_pcie0_pad_perst_pins[] = { 83, };
+static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
+static int mt7622_pcie1_pad_perst_pins[] = { 84, };
+static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
+
+/* PMIC bus */
+static int mt7622_pmic_bus_pins[] = { 71, 72, };
+static int mt7622_pmic_bus_funcs[] = { 0, 0, };
+
+/* Parallel NAND */
+static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, };
+static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, };
+
+/* PWM */
+static int mt7622_pwm_ch1_0_pins[] = { 51, };
+static int mt7622_pwm_ch1_0_funcs[] = { 3, };
+static int mt7622_pwm_ch1_1_pins[] = { 73, };
+static int mt7622_pwm_ch1_1_funcs[] = { 4, };
+static int mt7622_pwm_ch1_2_pins[] = { 95, };
+static int mt7622_pwm_ch1_2_funcs[] = { 0, };
+static int mt7622_pwm_ch2_0_pins[] = { 52, };
+static int mt7622_pwm_ch2_0_funcs[] = { 3, };
+static int mt7622_pwm_ch2_1_pins[] = { 74, };
+static int mt7622_pwm_ch2_1_funcs[] = { 4, };
+static int mt7622_pwm_ch2_2_pins[] = { 96, };
+static int mt7622_pwm_ch2_2_funcs[] = { 0, };
+static int mt7622_pwm_ch3_0_pins[] = { 53, };
+static int mt7622_pwm_ch3_0_funcs[] = { 3, };
+static int mt7622_pwm_ch3_1_pins[] = { 75, };
+static int mt7622_pwm_ch3_1_funcs[] = { 4, };
+static int mt7622_pwm_ch3_2_pins[] = { 97, };
+static int mt7622_pwm_ch3_2_funcs[] = { 0, };
+static int mt7622_pwm_ch4_0_pins[] = { 54, };
+static int mt7622_pwm_ch4_0_funcs[] = { 3, };
+static int mt7622_pwm_ch4_1_pins[] = { 67, };
+static int mt7622_pwm_ch4_1_funcs[] = { 3, };
+static int mt7622_pwm_ch4_2_pins[] = { 76, };
+static int mt7622_pwm_ch4_2_funcs[] = { 4, };
+static int mt7622_pwm_ch4_3_pins[] = { 98, };
+static int mt7622_pwm_ch4_3_funcs[] = { 0, };
+static int mt7622_pwm_ch5_0_pins[] = { 68, };
+static int mt7622_pwm_ch5_0_funcs[] = { 3, };
+static int mt7622_pwm_ch5_1_pins[] = { 77, };
+static int mt7622_pwm_ch5_1_funcs[] = { 4, };
+static int mt7622_pwm_ch5_2_pins[] = { 99, };
+static int mt7622_pwm_ch5_2_funcs[] = { 0, };
+static int mt7622_pwm_ch6_0_pins[] = { 69, };
+static int mt7622_pwm_ch6_0_funcs[] = { 3, };
+static int mt7622_pwm_ch6_1_pins[] = { 78, };
+static int mt7622_pwm_ch6_1_funcs[] = { 4, };
+static int mt7622_pwm_ch6_2_pins[] = { 81, };
+static int mt7622_pwm_ch6_2_funcs[] = { 4, };
+static int mt7622_pwm_ch6_3_pins[] = { 100, };
+static int mt7622_pwm_ch6_3_funcs[] = { 0, };
+static int mt7622_pwm_ch7_0_pins[] = { 70, };
+static int mt7622_pwm_ch7_0_funcs[] = { 3, };
+static int mt7622_pwm_ch7_1_pins[] = { 82, };
+static int mt7622_pwm_ch7_1_funcs[] = { 4, };
+static int mt7622_pwm_ch7_2_pins[] = { 101, };
+static int mt7622_pwm_ch7_2_funcs[] = { 0, };
+
+/* SD */
+static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
+static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
+static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
+static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
+
+/* Serial NAND */
+static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
+static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
+
+/* SPI NOR */
+static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
+static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
+
+/* SPIC */
+static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
+static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
+static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
+static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
+static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
+static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
+static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
+static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
+static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
+static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
+static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
+static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
+
+/* TDM */
+static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
+static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
+static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static int mt7622_tdm_0_out_data_pins[] = { 20, };
+static int mt7622_tdm_0_out_data_funcs[] = { 3, };
+static int mt7622_tdm_0_in_data_pins[] = { 21, };
+static int mt7622_tdm_0_in_data_funcs[] = { 3, };
+static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
+static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
+static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static int mt7622_tdm_1_out_data_pins[] = { 55, };
+static int mt7622_tdm_1_out_data_funcs[] = { 3, };
+static int mt7622_tdm_1_in_data_pins[] = { 56, };
+static int mt7622_tdm_1_in_data_funcs[] = { 3, };
+
+/* UART */
+static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
+static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
+static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
+static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
+static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
+static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
+static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
+static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
+static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
+static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
+static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
+static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
+static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
+static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
+static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
+static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
+static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
+static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
+static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
+static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
+static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
+static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
+static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
+static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
+static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
+static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
+static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
+static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
+static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
+static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
+static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
+static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
+static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
+static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
+static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
+static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
+static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
+static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
+static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
+static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
+
+/* Watchdog */
+static int mt7622_watchdog_pins[] = { 78, };
+static int mt7622_watchdog_funcs[] = { 0, };
+
+/* WLAN LED */
+static int mt7622_wled_pins[] = { 85, };
+static int mt7622_wled_funcs[] = { 0, };
+
+static const struct mtk_group_desc mt7622_groups[] = {
+ PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
+ PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
+ PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
+ PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
+ PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
+ PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
+ PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
+ PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
+ PINCTRL_PIN_GROUP("esw", mt7622_esw),
+ PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
+ PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
+ PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
+ PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
+ PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
+ PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
+ PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
+ PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
+ PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
+ PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
+ PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
+ PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
+ PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
+ PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
+ PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
+ PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
+ PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
+ PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
+ PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
+ PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
+ PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
+ PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
+ PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
+ PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
+ PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
+ PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
+ PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
+ PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
+ PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
+ PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
+ PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
+ PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
+ PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
+ PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
+ PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
+ PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
+ PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
+ PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
+ PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
+ PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
+ PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
+ PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
+ PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
+ PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
+ PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
+ PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
+ PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
+ PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
+ PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
+ PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
+ PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
+ PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
+ PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
+ PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
+ PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
+ PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
+ PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
+ PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0),
+ PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1),
+ PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2),
+ PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
+ PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
+ PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
+ PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
+ PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
+ PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
+ PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
+ PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
+ PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
+ PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
+ PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
+ mt7622_tdm_0_out_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
+ mt7622_tdm_0_in_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data),
+ PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
+ PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
+ mt7622_tdm_1_out_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
+ mt7622_tdm_1_in_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data),
+ PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
+ PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
+ PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
+ PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
+ PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
+ PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
+ PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
+ PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
+ PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
+ PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
+ PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
+ PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
+ PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
+ PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
+ PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
+ PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
+ PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
+ PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
+ PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
+ PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
+ PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
+ PINCTRL_PIN_GROUP("wled", mt7622_wled),
+};
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
+static const char *const mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
+ "esw_p2_p3_p4", "mdc_mdio",
+ "rgmii_via_gmac1",
+ "rgmii_via_gmac2",
+ "rgmii_via_esw", };
+static const char *const mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
+ "i2c1_2", "i2c2_0", "i2c2_1",
+ "i2c2_2", };
+static const char *const mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
+ "i2s_in_mclk_bclk_ws",
+ "i2s1_in_data", "i2s2_in_data",
+ "i2s3_in_data", "i2s4_in_data",
+ "i2s1_out_data", "i2s2_out_data",
+ "i2s3_out_data", "i2s4_out_data", };
+static const char *const mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
+ "ir_0_rx", "ir_1_rx", "ir_2_rx"};
+static const char *const mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
+ "ephy1_led", "ephy2_led",
+ "ephy3_led", "ephy4_led",
+ "wled", };
+static const char *const mt7622_flash_groups[] = { "par_nand", "snfi",
+ "spi_nor"};
+static const char *const mt7622_pcie_groups[] = { "pcie0_0_waken",
+ "pcie0_0_clkreq", "pcie0_1_waken",
+ "pcie0_1_clkreq", "pcie1_0_waken",
+ "pcie1_0_clkreq", "pcie0_pad_perst",
+ "pcie1_pad_perst", };
+static const char *const mt7622_pmic_bus_groups[] = { "pmic_bus", };
+static const char *const mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
+ "pwm_ch1_2", "pwm_ch2_0",
+ "pwm_ch2_1", "pwm_ch2_2",
+ "pwm_ch3_0", "pwm_ch3_1",
+ "pwm_ch3_2", "pwm_ch4_0",
+ "pwm_ch4_1", "pwm_ch4_2",
+ "pwm_ch4_3", "pwm_ch5_0",
+ "pwm_ch5_1", "pwm_ch5_2",
+ "pwm_ch6_0", "pwm_ch6_1",
+ "pwm_ch6_2", "pwm_ch6_3",
+ "pwm_ch7_0", "pwm_ch7_1",
+ "pwm_ch7_2", };
+static const char *const mt7622_sd_groups[] = { "sd_0", "sd_1", };
+static const char *const mt7622_spic_groups[] = { "spic0_0", "spic0_1",
+ "spic1_0", "spic1_1", "spic2_0",
+ "spic2_0_wp_hold", };
+static const char *const mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
+ "tdm_0_in_mclk_bclk_ws",
+ "tdm_0_out_data",
+ "tdm_0_in_data",
+ "tdm_1_out_mclk_bclk_ws",
+ "tdm_1_in_mclk_bclk_ws",
+ "tdm_1_out_data",
+ "tdm_1_in_data", };
+
+static const char *const mt7622_uart_groups[] = { "uart0_0_tx_rx",
+ "uart1_0_tx_rx", "uart1_0_rts_cts",
+ "uart1_1_tx_rx", "uart1_1_rts_cts",
+ "uart2_0_tx_rx", "uart2_0_rts_cts",
+ "uart2_1_tx_rx", "uart2_1_rts_cts",
+ "uart2_2_tx_rx", "uart2_2_rts_cts",
+ "uart2_3_tx_rx",
+ "uart3_0_tx_rx",
+ "uart3_1_tx_rx", "uart3_1_rts_cts",
+ "uart4_0_tx_rx",
+ "uart4_1_tx_rx", "uart4_1_rts_cts",
+ "uart4_2_tx_rx",
+ "uart4_2_rts_cts",};
+static const char *const mt7622_wdt_groups[] = { "watchdog", };
+
+static const struct mtk_function_desc mt7622_functions[] = {
+ {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
+ {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
+ {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
+ {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
+ {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
+ {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
+ {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
+ {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
+ {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
+ {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
+ {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
+ {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
+ {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
+ {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
+ {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
+};
+
+static struct mtk_pinctrl_soc mt7622_data = {
+ .name = "mt7622_pinctrl",
+ .reg_cal = mt7622_reg_cals,
+ .pins = mt7622_pins,
+ .npins = ARRAY_SIZE(mt7622_pins),
+ .grps = mt7622_groups,
+ .ngrps = ARRAY_SIZE(mt7622_groups),
+ .funcs = mt7622_functions,
+ .nfuncs = ARRAY_SIZE(mt7622_functions),
+ .gpio_mode = 1,
+ .rev = MTK_PINCTRL_V0,
+};
+
+static int mtk_pinctrl_mt7622_probe(struct udevice *dev)
+{
+ return mtk_pinctrl_common_probe(dev, &mt7622_data);
+}
+
+static const struct udevice_id mt7622_pctrl_match[] = {
+ { .compatible = "mediatek,mt7622-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt7622_pinctrl) = {
+ .name = "mt7622_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = mt7622_pctrl_match,
+ .ops = &mtk_pinctrl_ops,
+ .probe = mtk_pinctrl_mt7622_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+};
+
+
.ngrps = ARRAY_SIZE(mt7623_groups),
.funcs = mt7623_functions,
.nfuncs = ARRAY_SIZE(mt7623_functions),
+ .gpio_mode = 0,
+ .rev = MTK_PINCTRL_V1,
};
/*
.ngrps = ARRAY_SIZE(mt7629_groups),
.funcs = mt7629_functions,
.nfuncs = ARRAY_SIZE(mt7629_functions),
+ .gpio_mode = 0,
+ .rev = MTK_PINCTRL_V1,
};
static int mtk_pinctrl_mt7629_probe(struct udevice *dev)
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#include <dm.h>
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, false)
+#define PIN_FIELDS(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, true)
+#define PIN_FIELD30(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 30, false)
+
+static const struct mtk_pin_field_calc mt8512_pin_mode_range[] = {
+ PIN_FIELD30(0, 115, 0x1E0, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_dir_range[] = {
+ PIN_FIELD(0, 115, 0x140, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_di_range[] = {
+ PIN_FIELD(0, 115, 0x000, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_do_range[] = {
+ PIN_FIELD(0, 115, 0x860, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_pullen_range[] = {
+ PIN_FIELD(0, 115, 0x900, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_pullsel_range[] = {
+ PIN_FIELD(0, 115, 0x0A0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_ies_range[] = {
+ PIN_FIELDS(0, 2, 0x410, 0x10, 0, 1),
+ PIN_FIELDS(3, 5, 0x410, 0x10, 1, 1),
+ PIN_FIELDS(6, 7, 0x410, 0x10, 2, 1),
+ PIN_FIELDS(8, 11, 0x410, 0x10, 3, 1),
+ PIN_FIELDS(12, 15, 0x410, 0x10, 4, 1),
+ PIN_FIELDS(16, 19, 0x410, 0x10, 5, 1),
+ PIN_FIELD(20, 20, 0x410, 0x10, 6, 1),
+ PIN_FIELDS(21, 25, 0x410, 0x10, 7, 1),
+ PIN_FIELDS(26, 27, 0x410, 0x10, 8, 1),
+ PIN_FIELDS(28, 31, 0x410, 0x10, 9, 1),
+ PIN_FIELD(32, 32, 0x410, 0x10, 10, 1),
+ PIN_FIELDS(33, 39, 0x410, 0x10, 11, 1),
+ PIN_FIELD(40, 40, 0x410, 0x10, 12, 1),
+ PIN_FIELDS(41, 43, 0x410, 0x10, 13, 1),
+ PIN_FIELDS(44, 47, 0x410, 0x10, 14, 1),
+ PIN_FIELDS(48, 51, 0x410, 0x10, 15, 1),
+ PIN_FIELDS(52, 53, 0x410, 0x10, 16, 1),
+ PIN_FIELDS(54, 57, 0x410, 0x10, 17, 1),
+ PIN_FIELDS(58, 63, 0x410, 0x10, 18, 1),
+ PIN_FIELDS(64, 65, 0x410, 0x10, 19, 1),
+ PIN_FIELDS(66, 67, 0x410, 0x10, 20, 1),
+ PIN_FIELDS(68, 69, 0x410, 0x10, 21, 1),
+ PIN_FIELD(70, 70, 0x410, 0x10, 22, 1),
+ PIN_FIELD(71, 71, 0x410, 0x10, 23, 1),
+ PIN_FIELD(72, 72, 0x410, 0x10, 24, 1),
+ PIN_FIELD(73, 73, 0x410, 0x10, 25, 1),
+ PIN_FIELD(74, 74, 0x410, 0x10, 26, 1),
+ PIN_FIELD(75, 75, 0x410, 0x10, 27, 1),
+ PIN_FIELD(76, 76, 0x410, 0x10, 28, 1),
+ PIN_FIELD(77, 77, 0x410, 0x10, 29, 1),
+ PIN_FIELD(78, 78, 0x410, 0x10, 30, 1),
+ PIN_FIELD(79, 79, 0x410, 0x10, 31, 1),
+ PIN_FIELD(80, 80, 0x420, 0x10, 0, 1),
+ PIN_FIELD(81, 81, 0x420, 0x10, 1, 1),
+ PIN_FIELD(82, 82, 0x420, 0x10, 2, 1),
+ PIN_FIELD(83, 83, 0x420, 0x10, 3, 1),
+ PIN_FIELD(84, 84, 0x420, 0x10, 4, 1),
+ PIN_FIELDS(85, 86, 0x420, 0x10, 5, 1),
+ PIN_FIELD(87, 87, 0x420, 0x10, 6, 1),
+ PIN_FIELDS(88, 91, 0x420, 0x10, 7, 1),
+ PIN_FIELDS(92, 98, 0x420, 0x10, 8, 1),
+ PIN_FIELDS(99, 101, 0x420, 0x10, 9, 1),
+ PIN_FIELDS(102, 104, 0x420, 0x10, 10, 1),
+ PIN_FIELDS(105, 111, 0x420, 0x10, 11, 1),
+ PIN_FIELDS(112, 115, 0x420, 0x10, 12, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_smt_range[] = {
+ PIN_FIELDS(0, 2, 0x470, 0x10, 0, 1),
+ PIN_FIELDS(3, 5, 0x470, 0x10, 1, 1),
+ PIN_FIELDS(6, 7, 0x470, 0x10, 2, 1),
+ PIN_FIELDS(8, 11, 0x470, 0x10, 3, 1),
+ PIN_FIELDS(12, 15, 0x470, 0x10, 4, 1),
+ PIN_FIELDS(16, 19, 0x470, 0x10, 5, 1),
+ PIN_FIELD(20, 20, 0x470, 0x10, 6, 1),
+ PIN_FIELDS(21, 25, 0x470, 0x10, 7, 1),
+ PIN_FIELDS(26, 27, 0x470, 0x10, 8, 1),
+ PIN_FIELDS(28, 31, 0x470, 0x10, 9, 1),
+ PIN_FIELD(32, 32, 0x470, 0x10, 10, 1),
+ PIN_FIELDS(33, 39, 0x470, 0x10, 11, 1),
+ PIN_FIELD(40, 40, 0x470, 0x10, 12, 1),
+ PIN_FIELDS(41, 43, 0x470, 0x10, 13, 1),
+ PIN_FIELDS(44, 47, 0x470, 0x10, 14, 1),
+ PIN_FIELDS(48, 51, 0x470, 0x10, 15, 1),
+ PIN_FIELDS(52, 53, 0x470, 0x10, 16, 1),
+ PIN_FIELDS(54, 57, 0x470, 0x10, 17, 1),
+ PIN_FIELDS(58, 63, 0x470, 0x10, 18, 1),
+ PIN_FIELDS(64, 65, 0x470, 0x10, 19, 1),
+ PIN_FIELDS(66, 67, 0x470, 0x10, 20, 1),
+ PIN_FIELDS(68, 69, 0x470, 0x10, 21, 1),
+ PIN_FIELD(70, 70, 0x470, 0x10, 22, 1),
+ PIN_FIELD(71, 71, 0x470, 0x10, 23, 1),
+ PIN_FIELD(72, 72, 0x470, 0x10, 24, 1),
+ PIN_FIELD(73, 73, 0x470, 0x10, 25, 1),
+ PIN_FIELD(74, 74, 0x470, 0x10, 26, 1),
+ PIN_FIELD(75, 75, 0x470, 0x10, 27, 1),
+ PIN_FIELD(76, 76, 0x470, 0x10, 28, 1),
+ PIN_FIELD(77, 77, 0x470, 0x10, 29, 1),
+ PIN_FIELD(78, 78, 0x470, 0x10, 30, 1),
+ PIN_FIELD(79, 79, 0x470, 0x10, 31, 1),
+ PIN_FIELD(80, 80, 0x480, 0x10, 0, 1),
+ PIN_FIELD(81, 81, 0x480, 0x10, 1, 1),
+ PIN_FIELD(82, 82, 0x480, 0x10, 2, 1),
+ PIN_FIELD(83, 83, 0x480, 0x10, 3, 1),
+ PIN_FIELD(84, 84, 0x480, 0x10, 4, 1),
+ PIN_FIELDS(85, 86, 0x480, 0x10, 5, 1),
+ PIN_FIELD(87, 87, 0x480, 0x10, 6, 1),
+ PIN_FIELDS(88, 91, 0x480, 0x10, 7, 1),
+ PIN_FIELDS(92, 98, 0x480, 0x10, 8, 1),
+ PIN_FIELDS(99, 101, 0x480, 0x10, 9, 1),
+ PIN_FIELDS(102, 104, 0x480, 0x10, 10, 1),
+ PIN_FIELDS(105, 111, 0x480, 0x10, 11, 1),
+ PIN_FIELDS(112, 115, 0x480, 0x10, 12, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_drv_range[] = {
+ PIN_FIELDS(0, 2, 0x710, 0x10, 0, 4),
+ PIN_FIELDS(3, 5, 0x710, 0x10, 4, 4),
+ PIN_FIELDS(6, 7, 0x710, 0x10, 8, 4),
+ PIN_FIELDS(8, 11, 0x710, 0x10, 12, 4),
+ PIN_FIELDS(12, 15, 0x710, 0x10, 16, 4),
+ PIN_FIELDS(16, 19, 0x710, 0x10, 20, 4),
+ PIN_FIELD(20, 20, 0x710, 0x10, 24, 4),
+ PIN_FIELDS(21, 25, 0x710, 0x10, 28, 4),
+ PIN_FIELDS(26, 27, 0x720, 0x10, 0, 4),
+ PIN_FIELDS(28, 31, 0x720, 0x10, 4, 4),
+ PIN_FIELD(32, 32, 0x720, 0x10, 8, 4),
+ PIN_FIELDS(33, 39, 0x720, 0x10, 12, 4),
+ PIN_FIELD(40, 40, 0x720, 0x10, 16, 4),
+ PIN_FIELDS(41, 43, 0x720, 0x10, 20, 4),
+ PIN_FIELDS(44, 47, 0x720, 0x10, 24, 4),
+ PIN_FIELDS(48, 51, 0x720, 0x10, 28, 4),
+ PIN_FIELDS(52, 53, 0x730, 0x10, 0, 4),
+ PIN_FIELDS(54, 57, 0x730, 0x10, 4, 4),
+ PIN_FIELDS(58, 63, 0x730, 0x10, 8, 4),
+ PIN_FIELDS(64, 65, 0x730, 0x10, 12, 4),
+ PIN_FIELDS(66, 67, 0x730, 0x10, 16, 4),
+ PIN_FIELDS(68, 69, 0x730, 0x10, 20, 4),
+ PIN_FIELD(70, 70, 0x730, 0x10, 24, 4),
+ PIN_FIELD(71, 71, 0x730, 0x10, 28, 4),
+ PIN_FIELDS(72, 75, 0x740, 0x10, 0, 4),
+ PIN_FIELDS(76, 79, 0x740, 0x10, 16, 4),
+ PIN_FIELD(80, 80, 0x750, 0x10, 0, 4),
+ PIN_FIELD(81, 81, 0x750, 0x10, 4, 4),
+ PIN_FIELD(82, 82, 0x750, 0x10, 8, 4),
+ PIN_FIELDS(83, 86, 0x740, 0x10, 16, 4),
+ PIN_FIELD(87, 87, 0x750, 0x10, 24, 4),
+ PIN_FIELDS(88, 91, 0x750, 0x10, 28, 4),
+ PIN_FIELDS(92, 98, 0x760, 0x10, 0, 4),
+ PIN_FIELDS(99, 101, 0x760, 0x10, 4, 4),
+ PIN_FIELDS(102, 104, 0x760, 0x10, 8, 4),
+ PIN_FIELDS(105, 111, 0x760, 0x10, 12, 4),
+ PIN_FIELDS(112, 115, 0x760, 0x10, 16, 4),
+};
+
+static const struct mtk_pin_reg_calc mt8512_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8512_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8512_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8512_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8512_pin_do_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8512_pin_ies_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8512_pin_smt_range),
+ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8512_pin_pullsel_range),
+ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8512_pin_pullen_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8512_pin_drv_range),
+};
+
+static const struct mtk_pin_desc mt8512_pins[] = {
+ MTK_PIN(0, "GPIO0", DRV_GRP4),
+ MTK_PIN(1, "GPIO1", DRV_GRP4),
+ MTK_PIN(2, "GPIO2", DRV_GRP4),
+ MTK_PIN(3, "GPIO3", DRV_GRP4),
+ MTK_PIN(4, "GPIO4", DRV_GRP4),
+ MTK_PIN(5, "GPIO5", DRV_GRP4),
+ MTK_PIN(6, "GPIO6", DRV_GRP4),
+ MTK_PIN(7, "GPIO7", DRV_GRP4),
+ MTK_PIN(8, "GPIO8", DRV_GRP4),
+ MTK_PIN(9, "GPIO9", DRV_GRP4),
+ MTK_PIN(10, "GPIO10", DRV_GRP4),
+ MTK_PIN(11, "GPIO11", DRV_GRP4),
+ MTK_PIN(12, "GPIO12", DRV_GRP4),
+ MTK_PIN(13, "GPIO13", DRV_GRP4),
+ MTK_PIN(14, "GPIO14", DRV_GRP4),
+ MTK_PIN(15, "GPIO15", DRV_GRP4),
+ MTK_PIN(16, "GPIO16", DRV_GRP4),
+ MTK_PIN(17, "GPIO17", DRV_GRP4),
+ MTK_PIN(18, "GPIO18", DRV_GRP4),
+ MTK_PIN(19, "GPIO19", DRV_GRP4),
+ MTK_PIN(20, "GPIO20", DRV_GRP4),
+ MTK_PIN(21, "AUDIO_SYNC", DRV_GRP4),
+ MTK_PIN(22, "WIFI_INTB", DRV_GRP4),
+ MTK_PIN(23, "BT_INTB", DRV_GRP4),
+ MTK_PIN(24, "BT_STEREO", DRV_GRP4),
+ MTK_PIN(25, "RSTNB", DRV_GRP4),
+ MTK_PIN(26, "USB_ID", DRV_GRP4),
+ MTK_PIN(27, "USB_DRV", DRV_GRP4),
+ MTK_PIN(28, "EINT_GAUGEING", DRV_GRP4),
+ MTK_PIN(29, "CHG_IRQ", DRV_GRP4),
+ MTK_PIN(30, "CHG_OTG", DRV_GRP4),
+ MTK_PIN(31, "CHG_CEB", DRV_GRP4),
+ MTK_PIN(32, "FL_EN", DRV_GRP4),
+ MTK_PIN(33, "WAN_SMS_RDY", DRV_GRP4),
+ MTK_PIN(34, "SOC2WAN_RESET", DRV_GRP4),
+ MTK_PIN(35, "WAN_FM_RDY", DRV_GRP4),
+ MTK_PIN(36, "WAN_DIS", DRV_GRP4),
+ MTK_PIN(37, "WAN_VBUS_EN", DRV_GRP4),
+ MTK_PIN(38, "WAN_VBAT_EN", DRV_GRP4),
+ MTK_PIN(39, "WAN_PWR_EN", DRV_GRP4),
+ MTK_PIN(40, "KPROW0", DRV_GRP4),
+ MTK_PIN(41, "KPROW1", DRV_GRP4),
+ MTK_PIN(42, "KPCOL0", DRV_GRP4),
+ MTK_PIN(43, "KPCOL1", DRV_GRP4),
+ MTK_PIN(44, "PWM0", DRV_GRP4),
+ MTK_PIN(45, "PWM1", DRV_GRP4),
+ MTK_PIN(46, "PWM2", DRV_GRP4),
+ MTK_PIN(47, "PWM3", DRV_GRP4),
+ MTK_PIN(48, "JTMS", DRV_GRP4),
+ MTK_PIN(49, "JTCK", DRV_GRP4),
+ MTK_PIN(50, "JTDI", DRV_GRP4),
+ MTK_PIN(51, "JTDO", DRV_GRP4),
+ MTK_PIN(52, "URXD0", DRV_GRP4),
+ MTK_PIN(53, "UTXD0", DRV_GRP4),
+ MTK_PIN(54, "URXD1", DRV_GRP4),
+ MTK_PIN(55, "UTXD1", DRV_GRP4),
+ MTK_PIN(56, "URTS1", DRV_GRP4),
+ MTK_PIN(57, "UCTS1", DRV_GRP4),
+ MTK_PIN(58, "RTC32K_CK", DRV_GRP4),
+ MTK_PIN(59, "PMIC_DVS_REQ0", DRV_GRP4),
+ MTK_PIN(60, "PMIC_DVS_REQ1", DRV_GRP4),
+ MTK_PIN(61, "WATCHDOG", DRV_GRP4),
+ MTK_PIN(62, "PMIC_INT", DRV_GRP4),
+ MTK_PIN(63, "SUSPEND", DRV_GRP4),
+ MTK_PIN(64, "SDA0", DRV_GRP4),
+ MTK_PIN(65, "SCL0", DRV_GRP4),
+ MTK_PIN(66, "SDA1", DRV_GRP4),
+ MTK_PIN(67, "SCL1", DRV_GRP4),
+ MTK_PIN(68, "SDA2", DRV_GRP4),
+ MTK_PIN(69, "SCL2", DRV_GRP4),
+ MTK_PIN(70, "MSDC1_CMD", DRV_GRP4),
+ MTK_PIN(71, "MSDC1_CLK", DRV_GRP4),
+ MTK_PIN(72, "MSDC1_DAT0", DRV_GRP4),
+ MTK_PIN(73, "MSDC1_DAT1", DRV_GRP4),
+ MTK_PIN(74, "MSDC1_DAT2", DRV_GRP4),
+ MTK_PIN(75, "MSDC1_DAT3", DRV_GRP4),
+ MTK_PIN(76, "MSDC0_DAT7", DRV_GRP4),
+ MTK_PIN(77, "MSDC0_DAT6", DRV_GRP4),
+ MTK_PIN(78, "MSDC0_DAT5", DRV_GRP4),
+ MTK_PIN(79, "MSDC0_DAT4", DRV_GRP4),
+ MTK_PIN(80, "MSDC0_RSTB", DRV_GRP4),
+ MTK_PIN(81, "MSDC0_CMD", DRV_GRP4),
+ MTK_PIN(82, "MSDC0_CLK", DRV_GRP4),
+ MTK_PIN(83, "MSDC0_DAT3", DRV_GRP4),
+ MTK_PIN(84, "MSDC0_DAT2", DRV_GRP4),
+ MTK_PIN(85, "MSDC0_DAT1", DRV_GRP4),
+ MTK_PIN(86, "MSDC0_DAT0", DRV_GRP4),
+ MTK_PIN(87, "SPDIF", DRV_GRP4),
+ MTK_PIN(88, "PCM_CLK", DRV_GRP4),
+ MTK_PIN(89, "PCM_SYNC", DRV_GRP4),
+ MTK_PIN(90, "PCM_RX", DRV_GRP4),
+ MTK_PIN(91, "PCM_TX", DRV_GRP4),
+ MTK_PIN(92, "I2SIN_MCLK", DRV_GRP4),
+ MTK_PIN(93, "I2SIN_LRCK", DRV_GRP4),
+ MTK_PIN(94, "I2SIN_BCK", DRV_GRP4),
+ MTK_PIN(95, "I2SIN_DAT0", DRV_GRP4),
+ MTK_PIN(96, "I2SIN_DAT1", DRV_GRP4),
+ MTK_PIN(97, "I2SIN_DAT2", DRV_GRP4),
+ MTK_PIN(98, "I2SIN_DAT3", DRV_GRP4),
+ MTK_PIN(99, "DMIC0_CLK", DRV_GRP4),
+ MTK_PIN(100, "DMIC0_DAT0", DRV_GRP4),
+ MTK_PIN(101, "DMIC0_DAT1", DRV_GRP4),
+ MTK_PIN(102, "DMIC1_CLK", DRV_GRP4),
+ MTK_PIN(103, "DMIC1_DAT0", DRV_GRP4),
+ MTK_PIN(104, "DMIC1_DAT1", DRV_GRP4),
+ MTK_PIN(105, "I2SO_BCK", DRV_GRP4),
+ MTK_PIN(106, "I2SO_LRCK", DRV_GRP4),
+ MTK_PIN(107, "I2SO_MCLK", DRV_GRP4),
+ MTK_PIN(108, "I2SO_DAT0", DRV_GRP4),
+ MTK_PIN(109, "I2SO_DAT1", DRV_GRP4),
+ MTK_PIN(110, "I2SO_DAT2", DRV_GRP4),
+ MTK_PIN(111, "I2SO_DAT3", DRV_GRP4),
+ MTK_PIN(112, "SPI_CSB", DRV_GRP4),
+ MTK_PIN(113, "SPI_CLK", DRV_GRP4),
+ MTK_PIN(114, "SPI_MISO", DRV_GRP4),
+ MTK_PIN(115, "SPI_MOSI", DRV_GRP4),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
+/* UART */
+static int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, };
+static int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, };
+static int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, };
+static int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, };
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt8512_uart_groups[] = { "uart0_0_rxd_txd",
+ "uart1_0_rxd_txd",
+ "uart2_0_rxd_txd", };
+
+/* SNAND */
+static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
+static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
+
+/* MMC0 */
+static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
+ 85, 86, };
+static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static const struct mtk_group_desc mt8512_groups[] = {
+ PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8512_uart1_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8512_uart2_0_rxd_txd),
+
+ PINCTRL_PIN_GROUP("msdc0", mt8512_msdc0),
+
+ PINCTRL_PIN_GROUP("snfi", mt8512_snfi),
+};
+
+static const char *const mt8512_msdc_groups[] = { "msdc0" };
+
+static const struct mtk_function_desc mt8512_functions[] = {
+ {"uart", mt8512_uart_groups, ARRAY_SIZE(mt8512_uart_groups)},
+ {"msdc", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
+ {"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
+};
+
+static struct mtk_pinctrl_soc mt8512_data = {
+ .name = "mt8512_pinctrl",
+ .reg_cal = mt8512_reg_cals,
+ .pins = mt8512_pins,
+ .npins = ARRAY_SIZE(mt8512_pins),
+ .grps = mt8512_groups,
+ .ngrps = ARRAY_SIZE(mt8512_groups),
+ .funcs = mt8512_functions,
+ .nfuncs = ARRAY_SIZE(mt8512_functions),
+};
+
+static int mtk_pinctrl_mt8512_probe(struct udevice *dev)
+{
+ return mtk_pinctrl_common_probe(dev, &mt8512_data);
+}
+
+static const struct udevice_id mt8512_pctrl_match[] = {
+ { .compatible = "mediatek,mt8512-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt8512_pinctrl) = {
+ .name = "mt8512_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = mt8512_pctrl_match,
+ .ops = &mtk_pinctrl_ops,
+ .probe = mtk_pinctrl_mt8512_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+};
.ngrps = ARRAY_SIZE(mt8516_groups),
.funcs = mt8516_functions,
.nfuncs = ARRAY_SIZE(mt8516_functions),
+ .gpio_mode = 0,
+ .rev = MTK_PINCTRL_V1,
};
static int mtk_pinctrl_mt8516_probe(struct udevice *dev)
.ngrps = ARRAY_SIZE(mt8518_groups),
.funcs = mt8518_functions,
.nfuncs = ARRAY_SIZE(mt8518_functions),
+ .gpio_mode = 0,
+ .rev = MTK_PINCTRL_V1,
};
static int mtk_pinctrl_mt8518_probe(struct udevice *dev)
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
};
-int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
+
+int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg)
+{
+ int err, disable, pullup;
+
+ disable = (arg == PIN_CONFIG_BIAS_DISABLE);
+ pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
+
+ if (disable) {
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, 0);
+ if (err)
+ return err;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, 0);
+ if (err)
+ return err;
+
+ } else {
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, pullup);
+ if (err)
+ return err;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, !pullup);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg)
+{
+ int err, disable, pullup;
+
+ disable = (arg == PIN_CONFIG_BIAS_DISABLE);
+ pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
+
+ if (disable) {
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0);
+ if (err)
+ return err;
+ } else {
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 1);
+ if (err)
+ return err;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL,
+ pullup);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg)
+{
+ int err;
+
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1);
+ if (err)
+ return err;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0);
+ if (err)
+ return err;
+ return 0;
+}
+
+int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg)
{
struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
*/
if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
arg = (arg / tb->step - 1) * tb->scal;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E4,
+ arg & 0x1);
+ if (err)
+ return err;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E8,
+ (arg & 0x2) >> 1);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+
+int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
+{
+ struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
+ const struct mtk_drive_desc *tb;
+ int err = -ENOTSUPP;
+ tb = &mtk_drive[desc->drv_n];
+ if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
+ arg = (arg / tb->step - 1) * tb->scal;
err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg);
if (err)
return err;
unsigned int param, unsigned int arg)
{
int err = 0;
+ struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+ int rev = priv->soc->rev;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
- arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
- (param == PIN_CONFIG_BIAS_PULL_UP) ? 3 : 2;
-
- err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL,
- arg & 1);
- if (err)
- goto err;
-
- err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN,
- !!(arg & 2));
+ if (rev == MTK_PINCTRL_V0)
+ err = mtk_pinconf_bias_set_v0(dev, pin, param);
+ else
+ err = mtk_pinconf_bias_set_v1(dev, pin, param);
if (err)
goto err;
break;
goto err;
break;
case PIN_CONFIG_INPUT_ENABLE:
- err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1);
- if (err)
- goto err;
- err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0);
+ if (rev == MTK_PINCTRL_V1)
+ err = mtk_pinconf_input_enable_v1(dev, pin, param);
if (err)
goto err;
break;
goto err;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
- err = mtk_pinconf_drive_set(dev, pin, arg);
+ if (rev == MTK_PINCTRL_V0)
+ err = mtk_pinconf_drive_set_v0(dev, pin, arg);
+ else
+ err = mtk_pinconf_drive_set_v1(dev, pin, arg);
if (err)
goto err;
break;
static int mtk_gpio_request(struct udevice *dev, unsigned int off,
const char *label)
{
- return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, 0);
+ struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);
+
+ return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE,
+ priv->soc->gpio_mode);
}
static int mtk_gpio_probe(struct udevice *dev)
* Copyright (C) 2018 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com>
*/
-
#ifndef __PINCTRL_MEDIATEK_H__
#define __PINCTRL_MEDIATEK_H__
+#define MTK_PINCTRL_V0 0x0
+#define MTK_PINCTRL_V1 0x1
+
#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
#define MTK_PIN(_number, _name, _drv_n) { \
.number = _number, \
PINCTRL_PIN_REG_DIR,
PINCTRL_PIN_REG_DI,
PINCTRL_PIN_REG_DO,
- PINCTRL_PIN_REG_IES,
PINCTRL_PIN_REG_SMT,
+ PINCTRL_PIN_REG_PD,
+ PINCTRL_PIN_REG_PU,
+ PINCTRL_PIN_REG_E4,
+ PINCTRL_PIN_REG_E8,
+ PINCTRL_PIN_REG_IES,
PINCTRL_PIN_REG_PULLEN,
PINCTRL_PIN_REG_PULLSEL,
PINCTRL_PIN_REG_DRV,
int ngrps;
const struct mtk_function_desc *funcs;
int nfuncs;
+ int gpio_mode;
+ int rev;
};
/**
familiy, e.g. i.MX28. This feature depends on device tree
configuration.
+config PINCTRL_IMXRT
+ bool "IMXRT pinctrl driver"
+ depends on ARCH_IMXRT && PINCTRL_FULL
+ select DEVRES
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imxrt pinctrl driver
+
+ This provides a simple pinctrl driver for i.MXRT SoC familiy.
+ This feature depends on device tree configuration. This driver
+ is different from the linux one, this is a simple implementation,
+ only parses the 'fsl,pins' property and configure related
+ registers.
+
config PINCTRL_VYBRID
bool "Vybrid (vf610) pinctrl driver"
depends on ARCH_VF610 && PINCTRL_FULL
obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o
+obj-$(CONFIG_PINCTRL_IMXRT) += pinctrl-imxrt.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+static struct imx_pinctrl_soc_info imxrt_pinctrl_soc_info = {
+ .flags = ZERO_OFFSET_VALID,
+};
+
+static int imxrt_pinctrl_probe(struct udevice *dev)
+{
+ struct imx_pinctrl_soc_info *info =
+ (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+ return imx_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id imxrt_pinctrl_match[] = {
+ { .compatible = "fsl,imxrt-iomuxc",
+ .data = (ulong)&imxrt_pinctrl_soc_info },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imxrt_pinctrl) = {
+ .name = "imxrt-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(imxrt_pinctrl_match),
+ .probe = imxrt_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .ops = &imx_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
#define DCM_TOP_EN BIT(0)
enum scp_domain_type {
+ SCPSYS_MT7622,
SCPSYS_MT7623,
SCPSYS_MT7629,
};
case SCPSYS_MT7623:
scpd->data = scp_domain_mt7623;
break;
+ case SCPSYS_MT7622:
case SCPSYS_MT7629:
scpd->data = scp_domain_mt7629;
break;
}
static const struct udevice_id mtk_power_domain_ids[] = {
+ {
+ .compatible = "mediatek,mt7622-scpsys",
+ .data = SCPSYS_MT7622,
+ },
{
.compatible = "mediatek,mt7623-scpsys",
.data = SCPSYS_MT7623,
Enabling this config adds support for the DDR memory controller
on J721E family of SoCs.
+config IMXRT_SDRAM
+ bool "Enable i.MXRT SDRAM support"
+ depends on RAM
+ help
+ i.MXRT family devices support smart external memory controller(SEMC)
+ to support external memories like sdram, psram & nand.
+ This driver is for the sdram memory interface with the SEMC.
+
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
+
+obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+
+/* SDRAM Command Code */
+#define SD_CC_ARD 0x0 /* Master Bus (AXI) command - Read */
+#define SD_CC_AWR 0x1 /* Master Bus (AXI) command - Write */
+#define SD_CC_IRD 0x8 /* IP command - Read */
+#define SD_CC_IWR 0x9 /* IP command - Write */
+#define SD_CC_IMS 0xA /* IP command - Set Mode Register */
+#define SD_CC_IACT 0xB /* IP command - ACTIVE */
+#define SD_CC_IAF 0xC /* IP command - Auto Refresh */
+#define SD_CC_ISF 0xD /* IP Command - Self Refresh */
+#define SD_CC_IPRE 0xE /* IP command - Precharge */
+#define SD_CC_IPREA 0xF /* IP command - Precharge ALL */
+
+#define SEMC_MCR_MDIS BIT(1)
+#define SEMC_MCR_DQSMD BIT(2)
+
+#define SEMC_INTR_IPCMDERR BIT(1)
+#define SEMC_INTR_IPCMDDONE BIT(0)
+
+#define SEMC_IPCMD_KEY 0xA55A0000
+
+struct imxrt_semc_regs {
+ /* 0x0 */
+ u32 mcr;
+ u32 iocr;
+ u32 bmcr0;
+ u32 bmcr1;
+ u32 br[9];
+
+ /* 0x34 */
+ u32 res1;
+ u32 inten;
+ u32 intr;
+ /* 0x40 */
+ u32 sdramcr0;
+ u32 sdramcr1;
+ u32 sdramcr2;
+ u32 sdramcr3;
+ /* 0x50 */
+ u32 nandcr0;
+ u32 nandcr1;
+ u32 nandcr2;
+ u32 nandcr3;
+ /* 0x60 */
+ u32 norcr0;
+ u32 norcr1;
+ u32 norcr2;
+ u32 norcr3;
+ /* 0x70 */
+ u32 sramcr0;
+ u32 sramcr1;
+ u32 sramcr2;
+ u32 sramcr3;
+ /* 0x80 */
+ u32 dbicr0;
+ u32 dbicr1;
+ u32 res2[2];
+ /* 0x90 */
+ u32 ipcr0;
+ u32 ipcr1;
+ u32 ipcr2;
+ u32 ipcmd;
+ /* 0xA0 */
+ u32 iptxdat;
+ u32 res3[3];
+ /* 0xB0 */
+ u32 iprxdat;
+ u32 res4[3];
+ /* 0xC0 */
+ u32 sts[16];
+};
+
+#define SEMC_IOCR_MUX_A8_SHIFT 0
+#define SEMC_IOCR_MUX_CSX0_SHIFT 3
+#define SEMC_IOCR_MUX_CSX1_SHIFT 6
+#define SEMC_IOCR_MUX_CSX2_SHIFT 9
+#define SEMC_IOCR_MUX_CSX3_SHIFT 12
+#define SEMC_IOCR_MUX_RDY_SHIFT 15
+
+struct imxrt_sdram_mux {
+ u8 a8;
+ u8 csx0;
+ u8 csx1;
+ u8 csx2;
+ u8 csx3;
+ u8 rdy;
+};
+
+#define SEMC_SDRAMCR0_PS_SHIFT 0
+#define SEMC_SDRAMCR0_BL_SHIFT 4
+#define SEMC_SDRAMCR0_COL_SHIFT 8
+#define SEMC_SDRAMCR0_CL_SHIFT 10
+
+struct imxrt_sdram_control {
+ u8 memory_width;
+ u8 burst_len;
+ u8 no_columns;
+ u8 cas_latency;
+};
+
+#define SEMC_SDRAMCR1_PRE2ACT_SHIFT 0
+#define SEMC_SDRAMCR1_ACT2RW_SHIFT 4
+#define SEMC_SDRAMCR1_RFRC_SHIFT 8
+#define SEMC_SDRAMCR1_WRC_SHIFT 13
+#define SEMC_SDRAMCR1_CKEOFF_SHIFT 16
+#define SEMC_SDRAMCR1_ACT2PRE_SHIFT 20
+
+#define SEMC_SDRAMCR2_SRRC_SHIFT 0
+#define SEMC_SDRAMCR2_REF2REF_SHIFT 8
+#define SEMC_SDRAMCR2_ACT2ACT_SHIFT 16
+#define SEMC_SDRAMCR2_ITO_SHIFT 24
+
+#define SEMC_SDRAMCR3_REN BIT(0)
+#define SEMC_SDRAMCR3_REBL_SHIFT 1
+#define SEMC_SDRAMCR3_PRESCALE_SHIFT 8
+#define SEMC_SDRAMCR3_RT_SHIFT 16
+#define SEMC_SDRAMCR3_UT_SHIFT 24
+
+struct imxrt_sdram_timing {
+ u8 pre2act;
+ u8 act2rw;
+ u8 rfrc;
+ u8 wrc;
+ u8 ckeoff;
+ u8 act2pre;
+
+ u8 srrc;
+ u8 ref2ref;
+ u8 act2act;
+ u8 ito;
+
+ u8 rebl;
+ u8 prescale;
+ u8 rt;
+ u8 ut;
+};
+
+enum imxrt_semc_bank {
+ SDRAM_BANK1,
+ SDRAM_BANK2,
+ SDRAM_BANK3,
+ SDRAM_BANK4,
+ MAX_SDRAM_BANK,
+};
+
+#define SEMC_BR_VLD_MASK 1
+#define SEMC_BR_MS_SHIFT 1
+
+struct bank_params {
+ enum imxrt_semc_bank target_bank;
+ u32 base_address;
+ u32 memory_size;
+};
+
+struct imxrt_sdram_params {
+ struct imxrt_semc_regs *base;
+
+ struct imxrt_sdram_mux *sdram_mux;
+ struct imxrt_sdram_control *sdram_control;
+ struct imxrt_sdram_timing *sdram_timing;
+
+ struct bank_params bank_params[MAX_SDRAM_BANK];
+ u8 no_sdram_banks;
+};
+
+static int imxrt_sdram_wait_ipcmd_done(struct imxrt_semc_regs *regs)
+{
+ do {
+ readl(®s->intr);
+
+ if (regs->intr & SEMC_INTR_IPCMDDONE)
+ return 0;
+ if (regs->intr & SEMC_INTR_IPCMDERR)
+ return -EIO;
+
+ mdelay(50);
+ } while (1);
+}
+
+static int imxrt_sdram_ipcmd(struct imxrt_semc_regs *regs, u32 mem_addr,
+ u32 ipcmd, u32 wd, u32 *rd)
+{
+ int ret;
+
+ if (ipcmd == SD_CC_IWR || ipcmd == SD_CC_IMS)
+ writel(wd, ®s->iptxdat);
+
+ /* set slave address for every command as specified on RM */
+ writel(mem_addr, ®s->ipcr0);
+
+ /* execute command */
+ writel(SEMC_IPCMD_KEY | ipcmd, ®s->ipcmd);
+
+ ret = imxrt_sdram_wait_ipcmd_done(regs);
+ if (ret < 0)
+ return ret;
+
+ if (ipcmd == SD_CC_IRD) {
+ if (!rd)
+ return -EINVAL;
+
+ *rd = readl(®s->iprxdat);
+ }
+
+ return 0;
+}
+
+int imxrt_sdram_init(struct udevice *dev)
+{
+ struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ struct imxrt_sdram_mux *mux = params->sdram_mux;
+ struct imxrt_sdram_control *ctrl = params->sdram_control;
+ struct imxrt_sdram_timing *time = params->sdram_timing;
+ struct imxrt_semc_regs *regs = params->base;
+ struct bank_params *bank_params;
+ u32 rd;
+ int i;
+
+ /* enable the SEMC controller */
+ clrbits_le32(®s->mcr, SEMC_MCR_MDIS);
+ /* set DQS mode from DQS pad */
+ setbits_le32(®s->mcr, SEMC_MCR_DQSMD);
+
+ for (i = 0, bank_params = params->bank_params;
+ i < params->no_sdram_banks; bank_params++,
+ i++)
+ writel((bank_params->base_address & 0xfffff000)
+ | bank_params->memory_size << SEMC_BR_MS_SHIFT
+ | SEMC_BR_VLD_MASK,
+ ®s->br[bank_params->target_bank]);
+
+ writel(mux->a8 << SEMC_IOCR_MUX_A8_SHIFT
+ | mux->csx0 << SEMC_IOCR_MUX_CSX0_SHIFT
+ | mux->csx1 << SEMC_IOCR_MUX_CSX1_SHIFT
+ | mux->csx2 << SEMC_IOCR_MUX_CSX2_SHIFT
+ | mux->csx3 << SEMC_IOCR_MUX_CSX3_SHIFT
+ | mux->rdy << SEMC_IOCR_MUX_RDY_SHIFT,
+ ®s->iocr);
+
+ writel(ctrl->memory_width << SEMC_SDRAMCR0_PS_SHIFT
+ | ctrl->burst_len << SEMC_SDRAMCR0_BL_SHIFT
+ | ctrl->no_columns << SEMC_SDRAMCR0_COL_SHIFT
+ | ctrl->cas_latency << SEMC_SDRAMCR0_CL_SHIFT,
+ ®s->sdramcr0);
+
+ writel(time->pre2act << SEMC_SDRAMCR1_PRE2ACT_SHIFT
+ | time->act2rw << SEMC_SDRAMCR1_ACT2RW_SHIFT
+ | time->rfrc << SEMC_SDRAMCR1_RFRC_SHIFT
+ | time->wrc << SEMC_SDRAMCR1_WRC_SHIFT
+ | time->ckeoff << SEMC_SDRAMCR1_CKEOFF_SHIFT
+ | time->act2pre << SEMC_SDRAMCR1_ACT2PRE_SHIFT,
+ ®s->sdramcr1);
+
+ writel(time->srrc << SEMC_SDRAMCR2_SRRC_SHIFT
+ | time->ref2ref << SEMC_SDRAMCR2_REF2REF_SHIFT
+ | time->act2act << SEMC_SDRAMCR2_ACT2ACT_SHIFT
+ | time->ito << SEMC_SDRAMCR2_ITO_SHIFT,
+ ®s->sdramcr2);
+
+ writel(time->rebl << SEMC_SDRAMCR3_REBL_SHIFT
+ | time->prescale << SEMC_SDRAMCR3_PRESCALE_SHIFT
+ | time->rt << SEMC_SDRAMCR3_RT_SHIFT
+ | time->ut << SEMC_SDRAMCR3_UT_SHIFT
+ | SEMC_SDRAMCR3_REN,
+ ®s->sdramcr3);
+
+ writel(2, ®s->ipcr1);
+
+ for (i = 0, bank_params = params->bank_params;
+ i < params->no_sdram_banks; bank_params++,
+ i++) {
+ mdelay(250);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IPREA,
+ 0, &rd);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
+ 0, &rd);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IAF,
+ 0, &rd);
+ imxrt_sdram_ipcmd(regs, bank_params->base_address, SD_CC_IMS,
+ ctrl->burst_len | (ctrl->cas_latency << 4),
+ &rd);
+ mdelay(250);
+ }
+
+ return 0;
+}
+
+static int imxrt_semc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ ofnode bank_node;
+ u8 bank = 0;
+
+ params->sdram_mux =
+ (struct imxrt_sdram_mux *)
+ dev_read_u8_array_ptr(dev,
+ "fsl,sdram-mux",
+ sizeof(struct imxrt_sdram_mux));
+ if (!params->sdram_mux) {
+ pr_err("fsl,sdram-mux not found");
+ return -EINVAL;
+ }
+
+ params->sdram_control =
+ (struct imxrt_sdram_control *)
+ dev_read_u8_array_ptr(dev,
+ "fsl,sdram-control",
+ sizeof(struct imxrt_sdram_control));
+ if (!params->sdram_control) {
+ pr_err("fsl,sdram-control not found");
+ return -EINVAL;
+ }
+
+ params->sdram_timing =
+ (struct imxrt_sdram_timing *)
+ dev_read_u8_array_ptr(dev,
+ "fsl,sdram-timing",
+ sizeof(struct imxrt_sdram_timing));
+ if (!params->sdram_timing) {
+ pr_err("fsl,sdram-timing not found");
+ return -EINVAL;
+ }
+
+ dev_for_each_subnode(bank_node, dev) {
+ struct bank_params *bank_params;
+ char *bank_name;
+ int ret;
+
+ /* extract the bank index from DT */
+ bank_name = (char *)ofnode_get_name(bank_node);
+ strsep(&bank_name, "@");
+ if (!bank_name) {
+ pr_err("missing sdram bank index");
+ return -EINVAL;
+ }
+
+ bank_params = ¶ms->bank_params[bank];
+ strict_strtoul(bank_name, 10,
+ (unsigned long *)&bank_params->target_bank);
+ if (bank_params->target_bank >= MAX_SDRAM_BANK) {
+ pr_err("Found bank %d , but only bank 0,1,2,3 are supported",
+ bank_params->target_bank);
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u32(bank_node,
+ "fsl,memory-size",
+ &bank_params->memory_size);
+ if (ret < 0) {
+ pr_err("fsl,memory-size not found");
+ return -EINVAL;
+ }
+
+ ret = ofnode_read_u32(bank_node,
+ "fsl,base-address",
+ &bank_params->base_address);
+ if (ret < 0) {
+ pr_err("fsl,base-address not found");
+ return -EINVAL;
+ }
+
+ debug("Found bank %s %u\n", bank_name,
+ bank_params->target_bank);
+ bank++;
+ }
+
+ params->no_sdram_banks = bank;
+ debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
+
+ return 0;
+}
+
+static int imxrt_semc_probe(struct udevice *dev)
+{
+ struct imxrt_sdram_params *params = dev_get_platdata(dev);
+ int ret;
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ params->base = (struct imxrt_semc_regs *)addr;
+
+#ifdef CONFIG_CLK
+ struct clk clk;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+#endif
+ ret = imxrt_sdram_init(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int imxrt_semc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ return 0;
+}
+
+static struct ram_ops imxrt_semc_ops = {
+ .get_info = imxrt_semc_get_info,
+};
+
+static const struct udevice_id imxrt_semc_ids[] = {
+ { .compatible = "fsl,imxrt-semc", .data = 0 },
+ { }
+};
+
+U_BOOT_DRIVER(imxrt_semc) = {
+ .name = "imxrt_semc",
+ .id = UCLASS_RAM,
+ .of_match = imxrt_semc_ids,
+ .ops = &imxrt_semc_ops,
+ .ofdata_to_platdata = imxrt_semc_ofdata_to_platdata,
+ .probe = imxrt_semc_probe,
+ .platdata_auto_alloc_size = sizeof(struct imxrt_sdram_params),
+};
config DM_SERIAL
bool "Enable Driver Model for serial drivers"
depends on DM
+ select SYS_MALLOC_F
help
Enable driver model for serial. This replaces
drivers/serial/serial.c with the serial uclass, which
config SPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in SPL"
depends on DM_SERIAL && SPL_DM
+ select SYS_SPL_MALLOC_F
default y
help
Enable driver model for serial in SPL. This replaces
config TPL_DM_SERIAL
bool "Enable Driver Model for serial drivers in TPL"
depends on DM_SERIAL && TPL_DM
+ select SYS_TPL_MALLOC_F
default y if TPL && DM_SERIAL
help
Enable driver model for serial in TPL. This replaces
#define FIFO_RXSIZE_MASK 0x7
#define FIFO_RXSIZE_OFF 0
#define FIFO_TXFE 0x80
-#ifdef CONFIG_ARCH_IMX8
+#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
#define FIFO_RXFE 0x08
#else
#define FIFO_RXFE 0x40
DEV_VF610 = 1,
DEV_LS1021A,
DEV_MX7ULP,
- DEV_IMX8
+ DEV_IMX8,
+ DEV_IMXRT,
};
struct lpuart_serial_platdata {
lpuart_write32(plat->flags, &base->match, 0);
- if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) {
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
+ plat->devtype == DEV_IMXRT) {
_lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
} else {
/* provide data bits, parity, stop bit, etc */
struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
if (is_lpuart32(dev)) {
- if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8)
+ if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
+ plat->devtype == DEV_IMXRT)
_lpuart32_serial_setbrg_7ulp(dev, baudrate);
else
_lpuart32_serial_setbrg(dev, baudrate);
static int lpuart_serial_probe(struct udevice *dev)
{
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk per_clk;
+ int ret;
+
+ ret = clk_get_by_name(dev, "per", &per_clk);
+ if (!ret) {
+ ret = clk_enable(&per_clk);
+ if (ret) {
+ dev_err(dev, "Failed to get per clk: %d\n", ret);
+ return ret;
+ }
+ } else {
+ dev_warn(dev, "Failed to get per clk: %d\n", ret);
+ }
+#endif
+
if (is_lpuart32(dev))
return _lpuart32_serial_init(dev);
else
plat->devtype = DEV_VF610;
else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
plat->devtype = DEV_IMX8;
+ else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
+ plat->devtype = DEV_IMXRT;
return 0;
}
{ .compatible = "fsl,vf610-lpuart"},
{ .compatible = "fsl,imx8qm-lpuart",
.data = LPUART_FLAG_REGMAP_32BIT_REG },
+ { .compatible = "fsl,imxrt-lpuart",
+ .data = LPUART_FLAG_REGMAP_32BIT_REG },
{ }
};
config OF_CONTROL
bool "Run-time configuration via Device Tree"
select DTC
+ select OF_LIBFDT if !OF_PLATDATA
help
This feature provides for run-time configuration of U-Boot
via a flattened device tree.
config SPL_OF_CONTROL
bool "Enable run-time configuration via Device Tree in SPL"
depends on SPL && OF_CONTROL
+ select SPL_OF_LIBFDT if !SPL_OF_PLATDATA
help
Some boards use device tree in U-Boot but only have 4KB of SRAM
which is not enough to support device tree. Disable this option to
config TPL_OF_CONTROL
bool "Enable run-time configuration via Device Tree in TPL"
depends on TPL && OF_CONTROL
+ select TPL_OF_LIBFDT if !TPL_OF_PLATDATA
help
Some boards use device tree in U-Boot but only have 4KB of SRAM
which is not enough to support device tree. Enable this option to
#ifndef _ASM_GENERIC_SECTIONS_H_
#define _ASM_GENERIC_SECTIONS_H_
+#include <linux/types.h>
+
/* References to section boundaries */
extern char _text[], _stext[], _etext[];
*/
int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk);
+/**
+ * clk_get_by_name_nodev - Get/request a clock by name without a device.
+ *
+ * This is a version of clk_get_by_name() that does not use a device.
+ *
+ * @node: The client ofnode.
+ * @name: The name of the clock to request, within the client's list of
+ * clocks.
+ * @clock: A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk);
+
+/**
+ * clock_get_optional_nodev - Get/request an optinonal clock by name
+ * without a device.
+ * @node: The client ofnode.
+ * @name: The name of the clock to request.
+ * @name: The name of the clock to request, within the client's list of
+ * clocks.
+ * @clock: A pointer to a clock struct to initialize.
+ *
+ * Behaves the same as clk_get_by_name_nodev() except where there is
+ * no clock producer, in this case, skip the error number -ENODATA, and
+ * the function returns 0.
+ */
+int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk);
+
/**
* devm_clk_get - lookup and obtain a managed reference to a clock producer.
* @dev: device for clock "consumer"
return -ENOSYS;
}
+static inline int
+clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
+{
+ return -ENOSYS;
+}
+
+static inline int
+clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
+{
+ return -ENOSYS;
+}
+
static inline int clk_release_all(struct clk *clk, int count)
{
return -ENOSYS;
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2019 Siemens AG
+ */
+
+#ifndef __IMX8X_CAPRICORN_H
+#define __IMX8X_CAPRICORN_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#include "siemens-env-common.h"
+#include "siemens-ccp-common.h"
+
+/* SPL config */
+#ifdef CONFIG_SPL_BUILD
+
+#define CONFIG_SPL_MAX_SIZE (124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
+
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x013E000
+#define CONFIG_SPL_BSS_START_ADDR 0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
+#define CONFIG_MALLOC_F_ADDR 0x00120000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_FACTORYSET
+
+#undef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Commands */
+#define CONFIG_CMD_READ
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+/* ENET Config */
+#define CONFIG_FEC_XCV_TYPE RMII
+#define FEC_QUIRK_ENET_MAC
+
+/* ENET1 connects to base board and MUX with ESAI */
+#define CONFIG_FEC_ENET_DEV 1
+#define CONFIG_FEC_MXC_PHYADDR 0x0
+#define CONFIG_ETHPRIME "eth1"
+
+/* I2C Configuration */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_I2C_SPEED 400000
+/* EEPROM */
+#define EEPROM_I2C_BUS 0 /* I2C0 */
+#define EEPROM_I2C_ADDR 0x50
+/* PCA9552 */
+#define PCA9552_1_I2C_BUS 1 /* I2C1 */
+#define PCA9552_1_I2C_ADDR 0x60
+#endif /* !CONFIG_SPL_BUILD */
+
+/* AHAB */
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
+#define MFG_ENV_SETTINGS_DEFAULT \
+ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+ "rdinit=/linuxrc " \
+ "clk_ignore_unused "\
+ "\0" \
+ "kboot=booti\0"\
+ "bootcmd_mfg=run mfgtool_args;" \
+ "if iminfo ${initrd_addr}; then " \
+ "if test ${tee} = yes; then " \
+ "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
+ "else " \
+ "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
+ "fi; " \
+ "else " \
+ "echo \"Run fastboot ...\"; fastboot 0; " \
+ "fi;\0"
+
+/* Boot M4 */
+#define M4_BOOT_ENV \
+ "m4_0_image=m4_0.bin\0" \
+ "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
+ "${loadaddr} ${m4_0_image}\0" \
+ "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+
+#define CONFIG_MFG_ENV_SETTINGS \
+ MFG_ENV_SETTINGS_DEFAULT \
+ "initrd_addr=0x83100000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "emmc_dev=0\0"
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_MFG_ENV_SETTINGS \
+ M4_BOOT_ENV \
+ AHAB_ENV \
+ ENV_COMMON \
+ "script=boot.scr\0" \
+ "image=Image\0" \
+ "panel=NULL\0" \
+ "console=ttyLP2\0" \
+ "fdt_addr=0x83000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "cntr_addr=0x88000000\0" \
+ "cntr_file=os_cntr_signed.bin\0" \
+ "initrd_addr=0x83800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "netdev=eth0\0" \
+ "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
+ "hostname=capricorn\0" \
+ ENV_EMMC \
+ ENV_NET
+
+#define CONFIG_BOOTCOMMAND \
+ "if usrbutton; then " \
+ "run flash_self_test; " \
+ "reset; " \
+ "fi;" \
+ "run flash_self;" \
+ "reset;"
+
+/* Default location for tftp and bootm */
+#define CONFIG_LOADADDR 0x80280000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_ENV
+
+/* Environment organisation */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1, eMMC */
+#define CONFIG_SYS_MMC_ENV_PART 2 /* 2nd boot partition */
+
+/* On CCP board, USDHC1 is for eMMC */
+#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_2 0x880000000
+/* DDR3 board total DDR is 1 GB */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
+
+#define CONFIG_SYS_MEMTEST_START 0xA0000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+ (PHYS_SDRAM_1_SIZE >> 2))
+
+/* Console buffer and boot args */
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 8000000 /* 8MHz */
+
+#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
+#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
+
+#endif /* __IMX8X_CAPRICORN_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Siemens AG
+ *
+ */
+
+#ifndef __DENEB_H
+#define __DENEB_H
+
+#include "capricorn-common.h"
+
+#undef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "06")
+
+/* DDR3 board total DDR is 2 GB */
+#undef PHYS_SDRAM_1_SIZE
+#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
+
+#endif /* __DENEB_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Siemens AG
+ *
+ */
+
+#ifndef __GIEDI_H
+#define __GIEDI_H
+
+#include "capricorn-common.h"
+
+#undef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
+
+/* DDR3 board total DDR is 1 GB */
+#undef PHYS_SDRAM_1_SIZE
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
+
+#endif /* __GIEDI_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __IMXRT1050_EVK_H
+#define __IMXRT1050_EVK_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x20280000
+
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SYS_LOAD_ADDR 0x20209000
+#else
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+#define CONFIG_LOADADDR 0x80000000
+#endif
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
+
+#define PHYS_SDRAM 0x80000000
+#define PHYS_SDRAM_SIZE (32 * 1024 * 1024)
+
+#define DMAMEM_SZ_ALL (1 * 1024 * 1024)
+#define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \
+ DMAMEM_SZ_ALL)
+
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+
+/* For SPL */
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_SPL_LEN 0x00008000
+#define CONFIG_SYS_UBOOT_START 0x800023FD
+#endif
+/* For SPL ends */
+
+#endif /* __IMXRT1050_EVK_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT7629 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#ifndef __MT7622_H
+#define __MT7622_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_MAXARGS 8
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#define CONFIG_SYS_CBSIZE SZ_1K
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* Uboot definition */
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+
+/* SPL -> Uboot */
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \
+ GENERATED_GBL_DATA_SIZE)
+/* UBoot -> Kernel */
+#define CONFIG_LOADADDR 0x4007ff28
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* DRAM */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+
+/* Ethernet */
+#define CONFIG_IPADDR 192.168.1.1
+#define CONFIG_SERVERIP 192.168.1.3
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT8512 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#ifndef __MT8512_H
+#define __MT8512_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
+
+#define CONFIG_CPU_ARMV8
+
+#define COUNTER_FREQUENCY 13000000
+
+#define CONFIG_SYS_LOAD_ADDR 0x41000000
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
+/* Uboot definition */
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + \
+ SZ_2M - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* ENV Setting */
+#if defined(CONFIG_MMC_MTK)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OVERWRITE
+
+/* MMC offset in block unit,and block size is 0x200 */
+#define ENV_BOOT_READ_IMAGE \
+ "boot_rd_img=mmc dev 0" \
+ ";mmc read ${loadaddr} 0x27000 0x8000" \
+ ";iminfo ${loadaddr}\0"
+#endif
+
+/* Console configuration */
+#define ENV_DEVICE_SETTINGS \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+#define ENV_BOOT_CMD \
+ "mtk_boot=run boot_rd_img;bootm;\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x6c000000\0" \
+ ENV_DEVICE_SETTINGS \
+ ENV_BOOT_READ_IMAGE \
+ ENV_BOOT_CMD \
+ "bootcmd=run mtk_boot;\0" \
+
+#endif
#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
-/* Network */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 1
-
-#define CONFIG_PHY_ATHEROS
-
-/* ENET1 */
-#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
-
/* MMC Config */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Be very careful updating CONFIG_IDENT_STRING
+ * This string will control the update flow whether an U-Boot should be
+ * updated or not. If the version of installed U-Boot (in flash) is smaller
+ * than the version to be installed (from update file), an update will
+ * be performed.
+ *
+ * General rules:
+ * 1. First 4 characters ' ##v' or IDENT_MAGIC represent kind of a magic number
+ * to identify the following strings after easily. Don't change them!
+ *
+ * 2. First 2 digits after 'v' or CCP_MAJOR are updated with U-Boot version
+ * change, e.g. from 2015.04 to 2018.03
+ *
+ * 3. Second 2 digits after '.' or CCP_MINOR are updated if we want to upgrade
+ * U-Boot within an U-Boot version.
+ */
+#define CCP_IDENT_MAGIC " ##v"
+#define GENERATE_CCP_VERSION(MAJOR, MINOR) CCP_IDENT_MAGIC MAJOR "." MINOR
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/* Common env settings */
+
+/** set_bootargs()
+ * input:
+ * console: string, tty, etc.
+ * baudrate: string, tty baudrate
+ * testargs: string
+ * optargs: string
+ * output:
+ * bootargs: string, default boot string
+ */
+#define ENV_BOOTARGS_DEFAULT "set_bootargs=" \
+ "setenv bootargs " \
+ "console=${console} " \
+ "${testargs} " \
+ "${optargs}\0"
+
+/** set_bootargs_net()
+ * input:
+ * kernel_name:
+ * dtb_name:
+ * project_dir:
+ * output:
+ */
+#define ENV_NET_FCT_NETARGS "set_bootargs_net=" \
+ "run set_bootargs;" \
+ "setenv bootfile ${project_dir}/boot/${kernel_name};" \
+ "setenv bootdtb ${project_dir}/boot/${dtb_name_nfs}.dtb;" \
+ "setenv rootpath /home/projects/${project_dir}/;" \
+ "setenv bootargs ${bootargs} " \
+ "root=/dev/nfs " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} " \
+ "ip=${ipaddr}:${serverip}:" \
+ "${gatewayip}:${netmask}:${hostname}:eth0:off\0"
+
+/** net_nfs()
+ * input:
+ * output:
+ */
+#define ENV_NET_FCT_BOOT "net_nfs=" \
+ "echo Booting from network ...; " \
+ "run set_bootargs_net; " \
+ "tftpboot ${dtb_loadaddr} ${serverip}:${bootdtb};" \
+ "if test $? -eq 1;" \
+ "then " \
+ "echo Loading default.dtb!;" \
+ "tftpboot ${dtb_loadaddr} ${serverip}:${project_dir}/boot/${dtb_name_default}.dtb;" \
+ "fi;" \
+ "tftpboot ${kernel_loadaddr} ${serverip}:${bootfile};" \
+ "printenv bootargs;" \
+ "booti ${kernel_loadaddr} - ${dtb_loadaddr}\0"
+
+/** check_update()
+ * input:
+ * upgrade_available: [0|1], if set to 1 check bootcount variables
+ * bootcount: int, bootcount
+ * bootlimit: int, limit cootcount
+ * toggle_partition(): - toggles active partition set
+ * output:
+ * upgrade_available: [0|1], set to 0 if bootcount > bootlimit
+ */
+#define ENV_FCT_CHECK_UPGRADE "check_upgrade="\
+ "if test ${upgrade_available} -eq 1; " \
+ "then " \
+ "echo upgrade_available is set; " \
+ "if test ${bootcount} -gt ${bootlimit}; " \
+ "then " \
+ "setenv upgrade_available 0;" \
+ "echo toggle partition;" \
+ "run toggle_partition;" \
+ "fi;" \
+ "fi;\0"
+
+/** toggle_partition()
+ * input:
+ * partitionset_active: [A|B], selected partition set
+ * output:
+ * partitionset_active: [A|B], toggle
+ */
+#define ENV_FCT_TOGGLE_PARTITION "toggle_partition="\
+ "setenv ${partitionset_active} true;" \
+ "if test -n ${A}; " \
+ "then " \
+ "setenv partitionset_active B; " \
+ "env delete A; " \
+ "fi;" \
+ "if test -n ${B}; "\
+ "then " \
+ "setenv partitionset_active A; " \
+ "env delete B; " \
+ "fi;" \
+ "saveenv\0"
+
+/** set_partition()
+ * input:
+ * partitionset_active: [A|B], selected partition set
+ * rootfs_name: string, mmc device file in kernel, e.g. /dev/mmcblk0
+ * output:
+ * mmc_active_vol: string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2
+ * mmc_part_nr: int, partition number of mmc, e.g. /dev/mmcblk0p2 --> 2
+ */
+#define ENV_EMMC_FCT_SET_ACTIVE_PARTITION "set_partition=" \
+ "setenv ${partitionset_active} true;" \
+ "if test -n ${A}; " \
+ "then " \
+ "setenv mmc_part_nr 1;" \
+ "fi;" \
+ "if test -n ${B}; " \
+ "then " \
+ "setenv mmc_part_nr 2;" \
+ "fi;" \
+ "setenv mmc_active_vol ${rootfs_name}p${mmc_part_nr} \0"
+
+/** set_bootargs_mmc()
+ * input:
+ * bootargs: string, default bootargs
+ * mmc_active_vol string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2
+ * ip_method: string, [none|?]
+ * output:
+ * bootargs: string
+ */
+#define ENV_EMMC_FCT_SET_EMMC_BOOTARGS "set_bootargs_mmc=" \
+ "setenv bootargs ${bootargs} " \
+ "root=${mmc_active_vol} rw " \
+ "rootdelay=1 rootwait " \
+ "rootfstype=ext4 " \
+ "ip=${ip_method} \0"
+
+/** mmc_load_bootfiles()
+ * input:
+ * mmc_part_nr:
+ * dtb_loadaddr:
+ * dtb_name:
+ * kernel_loadaddr:
+ * kernel_name:
+ */
+#define ENV_EMMC_FCT_LOADFROM_EMMC "mmc_load_bootfiles=" \
+ "echo Loading from eMMC ...;" \
+ "ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name}.dtb;" \
+ "if test $? -eq 1;" \
+ "then " \
+ "echo Loading default.dtb!;" \
+ "ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name_default}.dtb;" \
+ "fi;" \
+ "ext4load mmc 0:${mmc_part_nr} ${kernel_loadaddr} boot/${kernel_name};" \
+ "printenv bootargs;\0"
+
+/** mmc_boot()
+ * input:
+ * mmc_part_nr:
+ * dtb_loadaddr:
+ * dtb_name:
+ * kernel_loadaddr:
+ * kernel_name:
+ */
+#define ENV_EMMC_FCT_EMMC_BOOT "mmc_boot=" \
+ "run set_bootargs;" \
+ "run check_upgrade; " \
+ "run set_partition;" \
+ "run set_bootargs_mmc;" \
+ "run mmc_load_bootfiles;" \
+ "echo Booting from eMMC ...; " \
+ "booti ${kernel_loadaddr} - ${dtb_loadaddr} \0"
+
+#define ENV_EMMC_ALIASES "" \
+ "flash_self=run mmc_boot\0" \
+ "flash_self_test=setenv testargs test; " \
+ "run mmc_boot\0"
+
+#define ENV_COMMON "" \
+ "project_dir=targetdir/rootfs\0" \
+ "serverip=192.168.251.2\0" \
+ "ipaddr=192.168.251.1\0" \
+ "dtb_name_nfs=default\0" \
+ "dtb_name_default=default\0" \
+ "kernel_name=Image\0" \
+ "partitionset_active=A\0" \
+ "dtb_loadaddr=0x83000000\0" \
+ "kernel_loadaddr=0x80280000\0" \
+ "ip_method=none\0" \
+ "rootfs_name=/dev/mmcblk0\0" \
+ "upgrade_available=0\0" \
+ "bootlimit=3\0" \
+ "altbootcmd=run bootcmd\0" \
+ "optargs=\0" \
+
+/**********************************************************************/
+
+#define ENV_EMMC ENV_EMMC_FCT_EMMC_BOOT \
+ ENV_EMMC_FCT_LOADFROM_EMMC \
+ ENV_EMMC_FCT_SET_EMMC_BOOTARGS \
+ ENV_EMMC_FCT_SET_ACTIVE_PARTITION \
+ ENV_FCT_CHECK_UPGRADE \
+ ENV_EMMC_ALIASES \
+ ENV_FCT_TOGGLE_PARTITION
+
+#define ENV_NET ENV_NET_FCT_BOOT \
+ ENV_NET_FCT_NETARGS \
+ ENV_BOOTARGS_DEFAULT
int dma_get_cfg(struct dma *dma, u32 cfg_id, void **cfg_data);
#endif /* CONFIG_DMA_CHANNELS */
+#if CONFIG_IS_ENABLED(DMA)
/*
* dma_get_device - get a DMA device which supports transfer
* type of transfer_type
transferred and on failure return error code.
*/
int dma_memcpy(void *dst, void *src, size_t len);
+#else
+static inline int dma_get_device(u32 transfer_type, struct udevice **devp)
+{
+ return -ENOSYS;
+}
+static inline int dma_memcpy(void *dst, void *src, size_t len)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_DMA */
#endif /* _DMA_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H
+#define __DT_BINDINGS_CLOCK_IMXRT1050_H
+
+#define IMXRT1050_CLK_DUMMY 0
+#define IMXRT1050_CLK_CKIL 1
+#define IMXRT1050_CLK_CKIH 2
+#define IMXRT1050_CLK_OSC 3
+#define IMXRT1050_CLK_PLL2_PFD0_352M 4
+#define IMXRT1050_CLK_PLL2_PFD1_594M 5
+#define IMXRT1050_CLK_PLL2_PFD2_396M 6
+#define IMXRT1050_CLK_PLL3_PFD0_720M 7
+#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8
+#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9
+#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10
+#define IMXRT1050_CLK_PLL2_198M 11
+#define IMXRT1050_CLK_PLL3_120M 12
+#define IMXRT1050_CLK_PLL3_80M 13
+#define IMXRT1050_CLK_PLL3_60M 14
+#define IMXRT1050_CLK_PLL1_BYPASS 15
+#define IMXRT1050_CLK_PLL2_BYPASS 16
+#define IMXRT1050_CLK_PLL3_BYPASS 17
+#define IMXRT1050_CLK_PLL5_BYPASS 19
+#define IMXRT1050_CLK_PLL1_REF_SEL 20
+#define IMXRT1050_CLK_PLL2_REF_SEL 21
+#define IMXRT1050_CLK_PLL3_REF_SEL 22
+#define IMXRT1050_CLK_PLL5_REF_SEL 23
+#define IMXRT1050_CLK_PRE_PERIPH_SEL 24
+#define IMXRT1050_CLK_PERIPH_SEL 25
+#define IMXRT1050_CLK_SEMC_ALT_SEL 26
+#define IMXRT1050_CLK_SEMC_SEL 27
+#define IMXRT1050_CLK_USDHC1_SEL 28
+#define IMXRT1050_CLK_USDHC2_SEL 29
+#define IMXRT1050_CLK_LPUART_SEL 30
+#define IMXRT1050_CLK_LCDIF_SEL 31
+#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32
+#define IMXRT1050_CLK_VIDEO_DIV 33
+#define IMXRT1050_CLK_ARM_PODF 34
+#define IMXRT1050_CLK_LPUART_PODF 35
+#define IMXRT1050_CLK_USDHC1_PODF 36
+#define IMXRT1050_CLK_USDHC2_PODF 37
+#define IMXRT1050_CLK_SEMC_PODF 38
+#define IMXRT1050_CLK_AHB_PODF 39
+#define IMXRT1050_CLK_LCDIF_PRED 40
+#define IMXRT1050_CLK_LCDIF_PODF 41
+#define IMXRT1050_CLK_USDHC1 42
+#define IMXRT1050_CLK_USDHC2 43
+#define IMXRT1050_CLK_LPUART1 44
+#define IMXRT1050_CLK_SEMC 45
+#define IMXRT1050_CLK_LCDIF 46
+#define IMXRT1050_CLK_PLL1_ARM 47
+#define IMXRT1050_CLK_PLL2_SYS 48
+#define IMXRT1050_CLK_PLL3_USB_OTG 49
+#define IMXRT1050_CLK_PLL4_AUDIO 50
+#define IMXRT1050_CLK_PLL5_VIDEO 51
+#define IMXRT1050_CLK_PLL6_ENET 52
+#define IMXRT1050_CLK_PLL7_USB_HOST 53
+#define IMXRT1050_CLK_END 54
+
+#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef _DT_BINDINGS_CLK_MT7622_H
+#define _DT_BINDINGS_CLK_MT7622_H
+
+/* TOPCKGEN */
+
+/* FIXED_CLKS */
+#define CLK_TOP_TO_U2_PHY 0
+#define CLK_TOP_TO_U2_PHY_1P 1
+#define CLK_TOP_PCIE0_PIPE_EN 2
+#define CLK_TOP_PCIE1_PIPE_EN 3
+#define CLK_TOP_SSUSB_TX250M 4
+#define CLK_TOP_SSUSB_EQ_RX250M 5
+#define CLK_TOP_SSUSB_CDR_REF 6
+#define CLK_TOP_SSUSB_CDR_FB 7
+#define CLK_TOP_SATA_ASIC 8
+#define CLK_TOP_SATA_RBC 9
+/* FIXED_DIVS */
+#define CLK_TOP_TO_USB3_SYS 10
+#define CLK_TOP_P1_1MHZ 11
+#define CLK_TOP_4MHZ 12
+#define CLK_TOP_P0_1MHZ 13
+#define CLK_TOP_TXCLK_SRC_PRE 14
+#define CLK_TOP_RTC 15
+#define CLK_TOP_MEMPLL 16
+#define CLK_TOP_DMPLL 17
+#define CLK_TOP_SYSPLL_D2 18
+#define CLK_TOP_SYSPLL1_D2 19
+#define CLK_TOP_SYSPLL1_D4 20
+#define CLK_TOP_SYSPLL1_D8 21
+#define CLK_TOP_SYSPLL2_D4 22
+#define CLK_TOP_SYSPLL2_D8 23
+#define CLK_TOP_SYSPLL_D5 24
+#define CLK_TOP_SYSPLL3_D2 25
+#define CLK_TOP_SYSPLL3_D4 26
+#define CLK_TOP_SYSPLL4_D2 27
+#define CLK_TOP_SYSPLL4_D4 28
+#define CLK_TOP_SYSPLL4_D16 29
+#define CLK_TOP_UNIVPLL 30
+#define CLK_TOP_UNIVPLL_D2 31
+#define CLK_TOP_UNIVPLL1_D2 32
+#define CLK_TOP_UNIVPLL1_D4 33
+#define CLK_TOP_UNIVPLL1_D8 34
+#define CLK_TOP_UNIVPLL1_D16 35
+#define CLK_TOP_UNIVPLL2_D2 36
+#define CLK_TOP_UNIVPLL2_D4 37
+#define CLK_TOP_UNIVPLL2_D8 38
+#define CLK_TOP_UNIVPLL2_D16 39
+#define CLK_TOP_UNIVPLL_D5 40
+#define CLK_TOP_UNIVPLL3_D2 41
+#define CLK_TOP_UNIVPLL3_D4 42
+#define CLK_TOP_UNIVPLL3_D16 43
+#define CLK_TOP_UNIVPLL_D7 44
+#define CLK_TOP_UNIVPLL_D80_D4 45
+#define CLK_TOP_UNIV48M 46
+#define CLK_TOP_SGMIIPLL 47
+#define CLK_TOP_SGMIIPLL_D2 48
+#define CLK_TOP_AUD1PLL 49
+#define CLK_TOP_AUD2PLL 50
+#define CLK_TOP_AUD_I2S2_MCK 51
+#define CLK_TOP_TO_USB3_REF 52
+#define CLK_TOP_PCIE1_MAC_EN 53
+#define CLK_TOP_PCIE0_MAC_EN 54
+#define CLK_TOP_ETH_500M 55
+/* TOP_MUXES */
+#define CLK_TOP_AXI_SEL 56
+#define CLK_TOP_MEM_SEL 57
+#define CLK_TOP_DDRPHYCFG_SEL 58
+#define CLK_TOP_ETH_SEL 59
+#define CLK_TOP_PWM_SEL 60
+#define CLK_TOP_F10M_REF_SEL 61
+#define CLK_TOP_NFI_INFRA_SEL 62
+#define CLK_TOP_FLASH_SEL 63
+#define CLK_TOP_UART_SEL 64
+#define CLK_TOP_SPI0_SEL 65
+#define CLK_TOP_SPI1_SEL 66
+#define CLK_TOP_MSDC50_0_SEL 67
+#define CLK_TOP_MSDC30_0_SEL 68
+#define CLK_TOP_MSDC30_1_SEL 69
+#define CLK_TOP_A1SYS_HP_SEL 70
+#define CLK_TOP_A2SYS_HP_SEL 71
+#define CLK_TOP_INTDIR_SEL 72
+#define CLK_TOP_AUD_INTBUS_SEL 73
+#define CLK_TOP_PMICSPI_SEL 74
+#define CLK_TOP_SCP_SEL 75
+#define CLK_TOP_ATB_SEL 76
+#define CLK_TOP_HIF_SEL 77
+#define CLK_TOP_AUDIO_SEL 78
+#define CLK_TOP_U2_SEL 79
+#define CLK_TOP_AUD1_SEL 80
+#define CLK_TOP_AUD2_SEL 81
+#define CLK_TOP_IRRX_SEL 82
+#define CLK_TOP_IRTX_SEL 83
+#define CLK_TOP_ASM_L_SEL 84
+#define CLK_TOP_ASM_M_SEL 85
+#define CLK_TOP_ASM_H_SEL 86
+#define CLK_TOP_APLL1_SEL 87
+#define CLK_TOP_APLL2_SEL 88
+#define CLK_TOP_I2S0_MCK_SEL 89
+#define CLK_TOP_I2S1_MCK_SEL 90
+#define CLK_TOP_I2S2_MCK_SEL 91
+#define CLK_TOP_I2S3_MCK_SEL 92
+#define CLK_TOP_APLL1_DIV 93
+#define CLK_TOP_APLL2_DIV 94
+#define CLK_TOP_I2S0_MCK_DIV 95
+#define CLK_TOP_I2S1_MCK_DIV 96
+#define CLK_TOP_I2S2_MCK_DIV 97
+#define CLK_TOP_I2S3_MCK_DIV 98
+#define CLK_TOP_A1SYS_HP_DIV 99
+#define CLK_TOP_A2SYS_HP_DIV 100
+#define CLK_TOP_APLL1_DIV_PD 101
+#define CLK_TOP_APLL2_DIV_PD 102
+#define CLK_TOP_I2S0_MCK_DIV_PD 103
+#define CLK_TOP_I2S1_MCK_DIV_PD 104
+#define CLK_TOP_I2S2_MCK_DIV_PD 105
+#define CLK_TOP_I2S3_MCK_DIV_PD 106
+
+/* INFRACFG */
+
+#define CLK_INFRA_DBGCLK_PD 0
+#define CLK_INFRA_TRNG 1
+#define CLK_INFRA_AUDIO_PD 2
+#define CLK_INFRA_IRRX_PD 3
+#define CLK_INFRA_APXGPT_PD 4
+#define CLK_INFRA_PMIC_PD 5
+
+/* PERICFG */
+
+#define CLK_PERI_THERM_PD 0
+#define CLK_PERI_PWM1_PD 1
+#define CLK_PERI_PWM2_PD 2
+#define CLK_PERI_PWM3_PD 3
+#define CLK_PERI_PWM4_PD 4
+#define CLK_PERI_PWM5_PD 5
+#define CLK_PERI_PWM6_PD 6
+#define CLK_PERI_PWM7_PD 7
+#define CLK_PERI_PWM_PD 8
+#define CLK_PERI_AP_DMA_PD 9
+#define CLK_PERI_MSDC30_0_PD 10
+#define CLK_PERI_MSDC30_1_PD 11
+#define CLK_PERI_UART0_PD 12
+#define CLK_PERI_UART1_PD 13
+#define CLK_PERI_UART2_PD 14
+#define CLK_PERI_UART3_PD 15
+#define CLK_PERI_BTIF_PD 16
+#define CLK_PERI_I2C0_PD 17
+#define CLK_PERI_I2C1_PD 18
+#define CLK_PERI_I2C2_PD 19
+#define CLK_PERI_SPI1_PD 20
+#define CLK_PERI_AUXADC_PD 21
+#define CLK_PERI_SPI0_PD 22
+#define CLK_PERI_SNFI_PD 23
+#define CLK_PERI_NFI_PD 24
+#define CLK_PERI_NFIECC_PD 25
+#define CLK_PERI_FLASH_PD 26
+#define CLK_PERI_IRTX_PD 27
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIV2PLL 2
+#define CLK_APMIXED_ETH1PLL 3
+#define CLK_APMIXED_ETH2PLL 4
+#define CLK_APMIXED_AUD1PLL 5
+#define CLK_APMIXED_AUD2PLL 6
+#define CLK_APMIXED_TRGPLL 7
+#define CLK_APMIXED_SGMIPLL 8
+
+/* AUDIOSYS */
+
+#define CLK_AUDIO_AFE 0
+#define CLK_AUDIO_HDMI 1
+#define CLK_AUDIO_SPDF 2
+#define CLK_AUDIO_APLL 3
+#define CLK_AUDIO_I2SIN1 4
+#define CLK_AUDIO_I2SIN2 5
+#define CLK_AUDIO_I2SIN3 6
+#define CLK_AUDIO_I2SIN4 7
+#define CLK_AUDIO_I2SO1 8
+#define CLK_AUDIO_I2SO2 9
+#define CLK_AUDIO_I2SO3 10
+#define CLK_AUDIO_I2SO4 11
+#define CLK_AUDIO_ASRCI1 12
+#define CLK_AUDIO_ASRCI2 13
+#define CLK_AUDIO_ASRCO1 14
+#define CLK_AUDIO_ASRCO2 15
+#define CLK_AUDIO_INTDIR 16
+#define CLK_AUDIO_A1SYS 17
+#define CLK_AUDIO_A2SYS 18
+#define CLK_AUDIO_UL1 19
+#define CLK_AUDIO_UL2 20
+#define CLK_AUDIO_UL3 21
+#define CLK_AUDIO_UL4 22
+#define CLK_AUDIO_UL5 23
+#define CLK_AUDIO_UL6 24
+#define CLK_AUDIO_DL1 25
+#define CLK_AUDIO_DL2 26
+#define CLK_AUDIO_DL3 27
+#define CLK_AUDIO_DL4 28
+#define CLK_AUDIO_DL5 29
+#define CLK_AUDIO_DL6 30
+#define CLK_AUDIO_DLMCH 31
+#define CLK_AUDIO_ARB1 32
+#define CLK_AUDIO_AWB 33
+#define CLK_AUDIO_AWB3 34
+#define CLK_AUDIO_DAI 35
+#define CLK_AUDIO_MOD 36
+#define CLK_AUDIO_ASRCI3 37
+#define CLK_AUDIO_ASRCI4 38
+#define CLK_AUDIO_ASRCO3 39
+#define CLK_AUDIO_ASRCO4 40
+#define CLK_AUDIO_MEM_ASRC1 41
+#define CLK_AUDIO_MEM_ASRC2 42
+#define CLK_AUDIO_MEM_ASRC3 43
+#define CLK_AUDIO_MEM_ASRC4 44
+#define CLK_AUDIO_MEM_ASRC5 45
+#define CLK_AUDIO_AFE_CONN 46
+#define CLK_AUDIO_NR_CLK 47
+
+/* SSUSBSYS */
+
+#define CLK_SSUSB_U2_PHY_1P_EN 0
+#define CLK_SSUSB_U2_PHY_EN 1
+#define CLK_SSUSB_REF_EN 2
+#define CLK_SSUSB_SYS_EN 3
+#define CLK_SSUSB_MCU_EN 4
+#define CLK_SSUSB_DMA_EN 5
+#define CLK_SSUSB_NR_CLK 6
+
+/* PCIESYS */
+
+#define CLK_PCIE_P1_AUX_EN 0
+#define CLK_PCIE_P1_OBFF_EN 1
+#define CLK_PCIE_P1_AHB_EN 2
+#define CLK_PCIE_P1_AXI_EN 3
+#define CLK_PCIE_P1_MAC_EN 4
+#define CLK_PCIE_P1_PIPE_EN 5
+#define CLK_PCIE_P0_AUX_EN 6
+#define CLK_PCIE_P0_OBFF_EN 7
+#define CLK_PCIE_P0_AHB_EN 8
+#define CLK_PCIE_P0_AXI_EN 9
+#define CLK_PCIE_P0_MAC_EN 10
+#define CLK_PCIE_P0_PIPE_EN 11
+#define CLK_SATA_AHB_EN 12
+#define CLK_SATA_AXI_EN 13
+#define CLK_SATA_ASIC_EN 14
+#define CLK_SATA_RBC_EN 15
+#define CLK_SATA_PM_EN 16
+#define CLK_PCIE_NR_CLK 17
+
+/* ETHSYS */
+
+#define CLK_ETH_HSDMA_EN 0
+#define CLK_ETH_ESW_EN 1
+#define CLK_ETH_GP2_EN 2
+#define CLK_ETH_GP1_EN 3
+#define CLK_ETH_GP0_EN 4
+
+/* SGMIISYS */
+
+#define CLK_SGMII_TX250M_EN 0
+#define CLK_SGMII_RX250M_EN 1
+#define CLK_SGMII_CDR_REF 2
+#define CLK_SGMII_CDR_FB 3
+
+#endif /* _DT_BINDINGS_CLK_MT7622_H */
+
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8512_H
+#define _DT_BINDINGS_CLK_MT8512_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL 0
+#define CLK_TOP_CLK32K 1
+#define CLK_TOP_SYSPLL1_D2 2
+#define CLK_TOP_SYSPLL1_D4 3
+#define CLK_TOP_SYSPLL1_D8 4
+#define CLK_TOP_SYSPLL1_D16 5
+#define CLK_TOP_SYSPLL_D3 6
+#define CLK_TOP_SYSPLL2_D2 7
+#define CLK_TOP_SYSPLL2_D4 8
+#define CLK_TOP_SYSPLL2_D8 9
+#define CLK_TOP_SYSPLL_D5 10
+#define CLK_TOP_SYSPLL3_D4 11
+#define CLK_TOP_SYSPLL_D7 12
+#define CLK_TOP_SYSPLL4_D2 13
+#define CLK_TOP_UNIVPLL 14
+#define CLK_TOP_UNIVPLL_D2 15
+#define CLK_TOP_UNIVPLL1_D2 16
+#define CLK_TOP_UNIVPLL1_D4 17
+#define CLK_TOP_UNIVPLL1_D8 18
+#define CLK_TOP_UNIVPLL_D3 19
+#define CLK_TOP_UNIVPLL2_D2 20
+#define CLK_TOP_UNIVPLL2_D4 21
+#define CLK_TOP_UNIVPLL2_D8 22
+#define CLK_TOP_UNIVPLL_D5 23
+#define CLK_TOP_UNIVPLL3_D2 24
+#define CLK_TOP_UNIVPLL3_D4 25
+#define CLK_TOP_TCONPLL_D2 26
+#define CLK_TOP_TCONPLL_D4 27
+#define CLK_TOP_TCONPLL_D8 28
+#define CLK_TOP_TCONPLL_D16 29
+#define CLK_TOP_TCONPLL_D32 30
+#define CLK_TOP_TCONPLL_D64 31
+#define CLK_TOP_USB20_192M 32
+#define CLK_TOP_USB20_192M_D2 33
+#define CLK_TOP_USB20_192M_D4_T 34
+#define CLK_TOP_APLL1 35
+#define CLK_TOP_APLL1_D2 36
+#define CLK_TOP_APLL1_D3 37
+#define CLK_TOP_APLL1_D4 38
+#define CLK_TOP_APLL1_D8 39
+#define CLK_TOP_APLL1_D16 40
+#define CLK_TOP_APLL2 41
+#define CLK_TOP_APLL2_D2 42
+#define CLK_TOP_APLL2_D3 43
+#define CLK_TOP_APLL2_D4 44
+#define CLK_TOP_APLL2_D8 45
+#define CLK_TOP_APLL2_D16 46
+#define CLK_TOP_CLK26M 47
+#define CLK_TOP_SYS_26M_D2 48
+#define CLK_TOP_MSDCPLL 49
+#define CLK_TOP_MSDCPLL_D2 50
+#define CLK_TOP_DSPPLL 51
+#define CLK_TOP_DSPPLL_D2 52
+#define CLK_TOP_DSPPLL_D4 53
+#define CLK_TOP_DSPPLL_D8 54
+#define CLK_TOP_IPPLL 55
+#define CLK_TOP_IPPLL_D2 56
+#define CLK_TOP_NFI2X_CK_D2 57
+#define CLK_TOP_AXI_SEL 58
+#define CLK_TOP_MEM_SEL 59
+#define CLK_TOP_UART_SEL 60
+#define CLK_TOP_SPI_SEL 61
+#define CLK_TOP_SPIS_SEL 62
+#define CLK_TOP_MSDC50_0_HC_SEL 63
+#define CLK_TOP_MSDC2_2_HC_SEL 64
+#define CLK_TOP_MSDC50_0_SEL 65
+#define CLK_TOP_MSDC50_2_SEL 66
+#define CLK_TOP_MSDC30_1_SEL 67
+#define CLK_TOP_AUDIO_SEL 68
+#define CLK_TOP_AUD_INTBUS_SEL 69
+#define CLK_TOP_HAPLL1_SEL 70
+#define CLK_TOP_HAPLL2_SEL 71
+#define CLK_TOP_A2SYS_SEL 72
+#define CLK_TOP_A1SYS_SEL 73
+#define CLK_TOP_ASM_L_SEL 74
+#define CLK_TOP_ASM_M_SEL 75
+#define CLK_TOP_ASM_H_SEL 76
+#define CLK_TOP_AUD_SPDIF_SEL 77
+#define CLK_TOP_AUD_1_SEL 78
+#define CLK_TOP_AUD_2_SEL 79
+#define CLK_TOP_SSUSB_SYS_SEL 80
+#define CLK_TOP_SSUSB_XHCI_SEL 81
+#define CLK_TOP_SPM_SEL 82
+#define CLK_TOP_I2C_SEL 83
+#define CLK_TOP_PWM_SEL 84
+#define CLK_TOP_DSP_SEL 85
+#define CLK_TOP_NFI2X_SEL 86
+#define CLK_TOP_SPINFI_SEL 87
+#define CLK_TOP_ECC_SEL 88
+#define CLK_TOP_GCPU_SEL 89
+#define CLK_TOP_GCPU_CPM_SEL 90
+#define CLK_TOP_MBIST_DIAG_SEL 91
+#define CLK_TOP_IP0_NNA_SEL 92
+#define CLK_TOP_IP1_NNA_SEL 93
+#define CLK_TOP_IP2_WFST_SEL 94
+#define CLK_TOP_SFLASH_SEL 95
+#define CLK_TOP_SRAM_SEL 96
+#define CLK_TOP_MM_SEL 97
+#define CLK_TOP_DPI0_SEL 98
+#define CLK_TOP_DBG_ATCLK_SEL 99
+#define CLK_TOP_OCC_104M_SEL 100
+#define CLK_TOP_OCC_68M_SEL 101
+#define CLK_TOP_OCC_182M_SEL 102
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_CONN_32K 0
+#define CLK_TOP_CONN_26M 1
+#define CLK_TOP_DSP_32K 2
+#define CLK_TOP_DSP_26M 3
+#define CLK_TOP_USB20_48M_EN 4
+#define CLK_TOP_UNIVPLL_48M_EN 5
+#define CLK_TOP_SSUSB_TOP_CK_EN 6
+#define CLK_TOP_SSUSB_PHY_CK_EN 7
+#define CLK_TOP_I2SI1_MCK 8
+#define CLK_TOP_TDMIN_MCK 9
+#define CLK_TOP_I2SO1_MCK 10
+
+/* INFRASYS */
+
+#define CLK_INFRA_DSP_AXI 0
+#define CLK_INFRA_APXGPT 1
+#define CLK_INFRA_ICUSB 2
+#define CLK_INFRA_GCE 3
+#define CLK_INFRA_THERM 4
+#define CLK_INFRA_PWM_HCLK 5
+#define CLK_INFRA_PWM1 6
+#define CLK_INFRA_PWM2 7
+#define CLK_INFRA_PWM3 8
+#define CLK_INFRA_PWM4 9
+#define CLK_INFRA_PWM5 10
+#define CLK_INFRA_PWM 11
+#define CLK_INFRA_UART0 12
+#define CLK_INFRA_UART1 13
+#define CLK_INFRA_UART2 14
+#define CLK_INFRA_DSP_UART 15
+#define CLK_INFRA_GCE_26M 16
+#define CLK_INFRA_CQDMA_FPC 17
+#define CLK_INFRA_BTIF 18
+#define CLK_INFRA_SPI 19
+#define CLK_INFRA_MSDC0 20
+#define CLK_INFRA_MSDC1 21
+#define CLK_INFRA_DVFSRC 22
+#define CLK_INFRA_GCPU 23
+#define CLK_INFRA_TRNG 24
+#define CLK_INFRA_AUXADC 25
+#define CLK_INFRA_AUXADC_MD 26
+#define CLK_INFRA_AP_DMA 27
+#define CLK_INFRA_DEBUGSYS 28
+#define CLK_INFRA_AUDIO 29
+#define CLK_INFRA_FLASHIF 30
+#define CLK_INFRA_PWM_FB6 31
+#define CLK_INFRA_PWM_FB7 32
+#define CLK_INFRA_AUD_ASRC 33
+#define CLK_INFRA_AUD_26M 34
+#define CLK_INFRA_SPIS 35
+#define CLK_INFRA_CQ_DMA 36
+#define CLK_INFRA_AP_MSDC0 37
+#define CLK_INFRA_MD_MSDC0 38
+#define CLK_INFRA_MSDC0_SRC 39
+#define CLK_INFRA_MSDC1_SRC 40
+#define CLK_INFRA_IRRX_26M 41
+#define CLK_INFRA_IRRX_32K 42
+#define CLK_INFRA_I2C0_AXI 43
+#define CLK_INFRA_I2C1_AXI 44
+#define CLK_INFRA_I2C2_AXI 45
+#define CLK_INFRA_NFI 46
+#define CLK_INFRA_NFIECC 47
+#define CLK_INFRA_NFI_HCLK 48
+#define CLK_INFRA_SUSB_133 49
+#define CLK_INFRA_USB_SYS 50
+#define CLK_INFRA_USB_XHCI 51
+#define CLK_INFRA_NR_CLK 52
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIVPLL2 2
+#define CLK_APMIXED_MSDCPLL 3
+#define CLK_APMIXED_APLL1 4
+#define CLK_APMIXED_APLL2 5
+#define CLK_APMIXED_IPPLL 6
+#define CLK_APMIXED_DSPPLL 7
+#define CLK_APMIXED_TCONPLL 8
+#define CLK_APMIXED_NR_CLK 9
+
+#endif /* _DT_BINDINGS_CLK_MT8512_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef DT_BINDINGS_IMXRT_SDRAM_H
+#define DT_BINDINGS_IMXRT_SDRAM_H
+
+#define MEM_SIZE_4K 0x00
+#define MEM_SIZE_8K 0x01
+#define MEM_SIZE_16K 0x02
+#define MEM_SIZE_32K 0x03
+#define MEM_SIZE_64K 0x04
+#define MEM_SIZE_128K 0x05
+#define MEM_SIZE_256K 0x06
+#define MEM_SIZE_512K 0x07
+#define MEM_SIZE_1M 0x08
+#define MEM_SIZE_2M 0x09
+#define MEM_SIZE_4M 0x0A
+#define MEM_SIZE_8M 0x0B
+#define MEM_SIZE_16M 0x0C
+#define MEM_SIZE_32M 0x0D
+#define MEM_SIZE_64M 0x0E
+#define MEM_SIZE_128M 0x0F
+#define MEM_SIZE_256M 0x10
+#define MEM_SIZE_512M 0x11
+#define MEM_SIZE_1G 0x12
+#define MEM_SIZE_2G 0x13
+#define MEM_SIZE_4G 0x14
+
+#define MUX_A8_SDRAM_A8 0x0
+#define MUX_A8_NAND_CE 0x1
+#define MUX_A8_NOR_CE 0x2
+#define MUX_A8_PSRAM_CE 0x3
+#define MUX_A8_DBI_CSX 0x4
+
+#define MUX_CSX0_NOR_PSRAM_A24 0x0
+#define MUX_CSX0_SDRAM_CS1 0x1
+#define MUX_CSX0_SDRAM_CS2 0x2
+#define MUX_CSX0_SDRAM_CS3 0x3
+#define MUX_CSX0_NAND_CE 0x4
+#define MUX_CSX0_NOR_CE 0x5
+#define MUX_CSX0_PSRAM_CE 0x6
+#define MUX_CSX0_DBI_CSX 0x7
+
+#define MUX_CSX1_NOR_PSRAM_A25 0x0
+#define MUX_CSX1_SDRAM_CS1 0x1
+#define MUX_CSX1_SDRAM_CS2 0x2
+#define MUX_CSX1_SDRAM_CS3 0x3
+#define MUX_CSX1_NAND_CE 0x4
+#define MUX_CSX1_NOR_CE 0x5
+#define MUX_CSX1_PSRAM_CE 0x6
+#define MUX_CSX1_DBI_CSX 0x7
+
+#define MUX_CSX2_NOR_PSRAM_A26 0x0
+#define MUX_CSX2_SDRAM_CS1 0x1
+#define MUX_CSX2_SDRAM_CS2 0x2
+#define MUX_CSX2_SDRAM_CS3 0x3
+#define MUX_CSX2_NAND_CE 0x4
+#define MUX_CSX2_NOR_CE 0x5
+#define MUX_CSX2_PSRAM_CE 0x6
+#define MUX_CSX2_DBI_CSX 0x7
+
+#define MUX_CSX3_NOR_PSRAM_A27 0x0
+#define MUX_CSX3_SDRAM_CS1 0x1
+#define MUX_CSX3_SDRAM_CS2 0x2
+#define MUX_CSX3_SDRAM_CS3 0x3
+#define MUX_CSX3_NAND_CE 0x4
+#define MUX_CSX3_NOR_CE 0x5
+#define MUX_CSX3_PSRAM_CE 0x6
+#define MUX_CSX3_DBI_CSX 0x7
+
+#define MUX_RDY_NAND_RDY_WAIT 0x0
+#define MUX_RDY_SDRAM_CS1 0x1
+#define MUX_RDY_SDRAM_CS2 0x2
+#define MUX_RDY_SDRAM_CS3 0x3
+#define MUX_RDY_NOR_CE 0x4
+#define MUX_RDY_PSRAM_CE 0x5
+#define MUX_RDY_DBI_CSX 0x6
+#define MUX_RDY_NOR_PSRAM_A27 0x7
+
+#define MEM_WIDTH_8BITS 0x0
+#define MEM_WIDTH_16BITS 0x1
+
+#define BL_1 0x0
+#define BL_2 0x1
+#define BL_4 0x2
+#define BL_8 0x3
+
+#define COL_12BITS 0x0
+#define COL_11BITS 0x1
+#define COL_10BITS 0x2
+#define COL_9BITS 0x3
+
+#define CL_1 0x0
+#define CL_2 0x2
+#define CL_3 0x3
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
+#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
+
+#define IMX_PAD_SION 0x40000000
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4
+#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1
+
+#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1
+
+#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1
+#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3
+#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4
+
+#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4
+
+#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3
+#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3
+
+#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3
+
+#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1
+
+#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2
+
+#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3
+
+#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2
+#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0
+
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0
+#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0
+
+#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */
*
*/
-#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8)
+#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
+ defined(CONFIG_ARCH_IMXRT)
struct lpuart_fsl_reg32 {
u32 verid;
u32 param;
struct efi_driver_binding_extended_protocol *bp =
(struct efi_driver_binding_extended_protocol *)this;
- EFI_ENTRY("%p, %pUl, %ls", this, controller_handle,
+ EFI_ENTRY("%p, %p, %ls", this, controller_handle,
efi_dp_str(remaining_device_path));
/* Attach driver to controller */
efi_status_t ret;
efi_uintn_t count;
struct efi_open_protocol_info_entry *entry_buffer;
- efi_guid_t *guid_controller = NULL;
+ struct efi_driver_binding_extended_protocol *bp =
+ (struct efi_driver_binding_extended_protocol *)this;
- EFI_ENTRY("%p, %pUl, %zu, %p", this, controller_handle,
+ EFI_ENTRY("%p, %p, %zu, %p", this, controller_handle,
number_of_children, child_handle_buffer);
/* Destroy provided child controllers */
/* Destroy all children */
ret = EFI_CALL(systab.boottime->open_protocol_information(
- controller_handle, guid_controller,
+ controller_handle, bp->ops->protocol,
&entry_buffer, &count));
if (ret != EFI_SUCCESS)
goto out;
/* Detach driver from controller */
ret = EFI_CALL(systab.boottime->close_protocol(
- controller_handle, guid_controller,
+ controller_handle, bp->ops->protocol,
this->driver_binding_handle, controller_handle));
out:
return EFI_EXIT(ret);
select REGEX
imply CFB_CONSOLE_ANSI
imply USB_KEYBOARD_FN_KEYS
+ imply VIDEO_ANSI
help
Select this option if you want to run UEFI applications (like GNU
GRUB or iPXE) on top of U-Boot. If this option is enabled, U-Boot
ret = EFI_CALL(image_obj->entry(image_handle, &systab));
/*
- * Usually UEFI applications call Exit() instead of returning.
- * But because the world doesn't consist of ponies and unicorns,
- * we're happy to emulate that behavior on behalf of a payload
- * that forgot.
+ * Control is returned from a started UEFI image either by calling
+ * Exit() (where exit data can be provided) or by simply returning from
+ * the entry point. In the latter case call Exit() on behalf of the
+ * image.
*/
return EFI_CALL(systab.boottime->exit(image_handle, ret, 0, NULL));
}
const efi_guid_t efi_guid_rng_protocol = EFI_RNG_PROTOCOL_GUID;
+/**
+ * platform_get_rng_device() - retrieve random number generator
+ *
+ * This function retrieves the udevice implementing a hardware random
+ * number generator.
+ *
+ * This function may be overridden if special initialization is needed.
+ *
+ * @dev: udevice
+ * Return: status code
+ */
__weak efi_status_t platform_get_rng_device(struct udevice **dev)
{
int ret;
return EFI_SUCCESS;
}
+/**
+ * rng_getinfo() - get information about random number generation
+ *
+ * This function implement the GetInfo() service of the EFI random number
+ * generator protocol. See the UEFI spec for details.
+ *
+ * @this: random number generator protocol instance
+ * @rng_algorithm_list_size: number of random number generation algorithms
+ * @rng_algorithm_list: descriptions of random number generation
+ * algorithms
+ * Return: status code
+ */
static efi_status_t EFIAPI rng_getinfo(struct efi_rng_protocol *this,
efi_uintn_t *rng_algorithm_list_size,
efi_guid_t *rng_algorithm_list)
return EFI_EXIT(ret);
}
+/**
+ * rng_getrng() - get random value
+ *
+ * This function implement the GetRng() service of the EFI random number
+ * generator protocol. See the UEFI spec for details.
+ *
+ * @this: random number generator protocol instance
+ * @rng_algorithm: random number generation algorithm
+ * @rng_value_length: number of random bytes to generate, buffer length
+ * @rng_value: buffer to receive random bytes
+ * Return: status code
+ */
static efi_status_t EFIAPI getrng(struct efi_rng_protocol *this,
efi_guid_t *rng_algorithm,
efi_uintn_t rng_value_length,
depends on CMD_BOOTEFI
imply FAT
imply FAT_WRITE
+ imply CMD_POWEROFF if PSCI_RESET || SYSRESET_PSCI
help
This adds a UEFI test application to U-Boot that can be executed
via the 'bootefi selftest' command. It provides extended tests of
disk_handle, &block_io_protocol_guid,
&block_io);
if (r != EFI_SUCCESS) {
- efi_st_todo(
+ efi_st_error(
"Failed to uninstall block I/O protocol\n");
- return EFI_ST_SUCCESS;
+ return EFI_ST_FAILURE;
}
}
/dts-v1/;
/ {
- model = "Sandbox Verified Boot Test";
- compatible = "sandbox";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ model = "Sandbox Verified Boot Test";
+ compatible = "sandbox";
reset@0 {
compatible = "sandbox,reset";
+ reg = <0>;
};
-
};
'''
projects / oweals / u-boot.git / commitdiff