drivers/clk/imx/clk-pllv3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <div64.h>
  10 #include <malloc.h>
  11 #include <clk-uclass.h>
  12 #include <dm/device.h>
  13 #include <dm/uclass.h>
  14 #include <clk.h>
  15 #include "clk.h"
  16
  17 #define UBOOT_DM_CLK_IMX_PLLV3_GENERIC  "imx_clk_pllv3_generic"
  18 #define UBOOT_DM_CLK_IMX_PLLV3_SYS      "imx_clk_pllv3_sys"
  19 #define UBOOT_DM_CLK_IMX_PLLV3_USB      "imx_clk_pllv3_usb"
  20 #define UBOOT_DM_CLK_IMX_PLLV3_AV       "imx_clk_pllv3_av"
  21
  22 #define PLL_NUM_OFFSET          0x10
  23 #define PLL_DENOM_OFFSET        0x20
  24
  25 #define BM_PLL_POWER            (0x1 << 12)
  26 #define BM_PLL_LOCK             (0x1 << 31)
  27
  28 struct clk_pllv3 {
  29         struct clk      clk;
  30         void __iomem    *base;
  31         u32             power_bit;
  32         bool            powerup_set;
  33         u32             div_mask;
  34         u32             div_shift;
  35 };
  36
  37 #define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
  38
  39 static ulong clk_pllv3_generic_get_rate(struct clk *clk)
  40 {
  41         struct clk_pllv3 *pll = to_clk_pllv3(dev_get_clk_ptr(clk->dev));
  42         unsigned long parent_rate = clk_get_parent_rate(clk);
  43
  44         u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
  45
  46         return (div == 1) ? parent_rate * 22 : parent_rate * 20;
  47 }
  48
  49 static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)
  50 {
  51         struct clk_pllv3 *pll = to_clk_pllv3(clk);
  52         unsigned long parent_rate = clk_get_parent_rate(clk);
  53         u32 val, div;
  54
  55         if (rate == parent_rate * 22)
  56                 div = 1;
  57         else if (rate == parent_rate * 20)
  58                 div = 0;
  59         else
  60                 return -EINVAL;
  61
  62         val = readl(pll->base);
  63         val &= ~(pll->div_mask << pll->div_shift);
  64         val |= (div << pll->div_shift);
  65         writel(val, pll->base);
  66
  67         /* Wait for PLL to lock */
  68         while (!(readl(pll->base) & BM_PLL_LOCK))
  69                 ;
  70
  71         return 0;
  72 }
  73
  74 static int clk_pllv3_generic_enable(struct clk *clk)
  75 {
  76         struct clk_pllv3 *pll = to_clk_pllv3(clk);
  77         u32 val;
  78
  79         val = readl(pll->base);
  80         if (pll->powerup_set)
  81                 val |= pll->power_bit;
  82         else
  83                 val &= ~pll->power_bit;
  84         writel(val, pll->base);
  85
  86         return 0;
  87 }
  88
  89 static int clk_pllv3_generic_disable(struct clk *clk)
  90 {
  91         struct clk_pllv3 *pll = to_clk_pllv3(clk);
  92         u32 val;
  93
  94         val = readl(pll->base);
  95         if (pll->powerup_set)
  96                 val &= ~pll->power_bit;
  97         else
  98                 val |= pll->power_bit;
  99         writel(val, pll->base);
 100
 101         return 0;
 102 }
 103
 104 static const struct clk_ops clk_pllv3_generic_ops = {
 105         .get_rate       = clk_pllv3_generic_get_rate,
 106         .enable         = clk_pllv3_generic_enable,
 107         .disable        = clk_pllv3_generic_disable,
 108         .set_rate       = clk_pllv3_generic_set_rate,
 109 };
 110
 111 static ulong clk_pllv3_sys_get_rate(struct clk *clk)
 112 {
 113         struct clk_pllv3 *pll = to_clk_pllv3(clk);
 114         unsigned long parent_rate = clk_get_parent_rate(clk);
 115         u32 div = readl(pll->base) & pll->div_mask;
 116
 117         return parent_rate * div / 2;
 118 }
 119
 120 static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)
 121 {
 122         struct clk_pllv3 *pll = to_clk_pllv3(clk);
 123         unsigned long parent_rate = clk_get_parent_rate(clk);
 124         unsigned long min_rate = parent_rate * 54 / 2;
 125         unsigned long max_rate = parent_rate * 108 / 2;
 126         u32 val, div;
 127
 128         if (rate < min_rate || rate > max_rate)
 129                 return -EINVAL;
 130
 131         div = rate * 2 / parent_rate;
 132         val = readl(pll->base);
 133         val &= ~pll->div_mask;
 134         val |= div;
 135         writel(val, pll->base);
 136
 137         /* Wait for PLL to lock */
 138         while (!(readl(pll->base) & BM_PLL_LOCK))
 139                 ;
 140
 141         return 0;
 142 }
 143
 144 static const struct clk_ops clk_pllv3_sys_ops = {
 145         .enable         = clk_pllv3_generic_enable,
 146         .disable        = clk_pllv3_generic_disable,
 147         .get_rate       = clk_pllv3_sys_get_rate,
 148         .set_rate       = clk_pllv3_sys_set_rate,
 149 };
 150
 151 static ulong clk_pllv3_av_get_rate(struct clk *clk)
 152 {
 153         struct clk_pllv3 *pll = to_clk_pllv3(clk);
 154         unsigned long parent_rate = clk_get_parent_rate(clk);
 155         u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
 156         u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
 157         u32 div = readl(pll->base) & pll->div_mask;
 158         u64 temp64 = (u64)parent_rate;
 159
 160         temp64 *= mfn;
 161         do_div(temp64, mfd);
 162
 163         return parent_rate * div + (unsigned long)temp64;
 164 }
 165
 166 static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)
 167 {
 168         struct clk_pllv3 *pll = to_clk_pllv3(clk);
 169         unsigned long parent_rate = clk_get_parent_rate(clk);
 170         unsigned long min_rate = parent_rate * 27;
 171         unsigned long max_rate = parent_rate * 54;
 172         u32 val, div;
 173         u32 mfn, mfd = 1000000;
 174         u32 max_mfd = 0x3FFFFFFF;
 175         u64 temp64;
 176
 177         if (rate < min_rate || rate > max_rate)
 178                 return -EINVAL;
 179
 180         if (parent_rate <= max_mfd)
 181                 mfd = parent_rate;
 182
 183         div = rate / parent_rate;
 184         temp64 = (u64)(rate - div * parent_rate);
 185         temp64 *= mfd;
 186         do_div(temp64, parent_rate);
 187         mfn = temp64;
 188
 189         val = readl(pll->base);
 190         val &= ~pll->div_mask;
 191         val |= div;
 192         writel(val, pll->base);
 193         writel(mfn, pll->base + PLL_NUM_OFFSET);
 194         writel(mfd, pll->base + PLL_DENOM_OFFSET);
 195
 196         /* Wait for PLL to lock */
 197         while (!(readl(pll->base) & BM_PLL_LOCK))
 198                 ;
 199
 200         return 0;
 201 }
 202
 203 static const struct clk_ops clk_pllv3_av_ops = {
 204         .enable         = clk_pllv3_generic_enable,
 205         .disable        = clk_pllv3_generic_disable,
 206         .get_rate       = clk_pllv3_av_get_rate,
 207         .set_rate       = clk_pllv3_av_set_rate,
 208 };
 209
 210 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 211                           const char *parent_name, void __iomem *base,
 212                           u32 div_mask)
 213 {
 214         struct clk_pllv3 *pll;
 215         struct clk *clk;
 216         char *drv_name;
 217         int ret;
 218
 219         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 220         if (!pll)
 221                 return ERR_PTR(-ENOMEM);
 222
 223         pll->power_bit = BM_PLL_POWER;
 224
 225         switch (type) {
 226         case IMX_PLLV3_GENERIC:
 227                 drv_name = UBOOT_DM_CLK_IMX_PLLV3_GENERIC;
 228                 pll->div_shift = 0;
 229                 pll->powerup_set = false;
 230                 break;
 231         case IMX_PLLV3_SYS:
 232                 drv_name = UBOOT_DM_CLK_IMX_PLLV3_SYS;
 233                 pll->div_shift = 0;
 234                 pll->powerup_set = false;
 235                 break;
 236         case IMX_PLLV3_USB:
 237                 drv_name = UBOOT_DM_CLK_IMX_PLLV3_USB;
 238                 pll->div_shift = 1;
 239                 pll->powerup_set = true;
 240                 break;
 241         case IMX_PLLV3_AV:
 242                 drv_name = UBOOT_DM_CLK_IMX_PLLV3_AV;
 243                 pll->div_shift = 0;
 244                 pll->powerup_set = false;
 245                 break;
 246         default:
 247                 kfree(pll);
 248                 return ERR_PTR(-ENOTSUPP);
 249         }
 250
 251         pll->base = base;
 252         pll->div_mask = div_mask;
 253         clk = &pll->clk;
 254
 255         ret = clk_register(clk, drv_name, name, parent_name);
 256         if (ret) {
 257                 kfree(pll);
 258                 return ERR_PTR(ret);
 259         }
 260
 261         return clk;
 262 }
 263
 264 U_BOOT_DRIVER(clk_pllv3_generic) = {
 265         .name   = UBOOT_DM_CLK_IMX_PLLV3_GENERIC,
 266         .id     = UCLASS_CLK,
 267         .ops    = &clk_pllv3_generic_ops,
 268         .flags = DM_FLAG_PRE_RELOC,
 269 };
 270
 271 U_BOOT_DRIVER(clk_pllv3_sys) = {
 272         .name   = UBOOT_DM_CLK_IMX_PLLV3_SYS,
 273         .id     = UCLASS_CLK,
 274         .ops    = &clk_pllv3_sys_ops,
 275         .flags = DM_FLAG_PRE_RELOC,
 276 };
 277
 278 U_BOOT_DRIVER(clk_pllv3_usb) = {
 279         .name   = UBOOT_DM_CLK_IMX_PLLV3_USB,
 280         .id     = UCLASS_CLK,
 281         .ops    = &clk_pllv3_generic_ops,
 282         .flags = DM_FLAG_PRE_RELOC,
 283 };
 284
 285 U_BOOT_DRIVER(clk_pllv3_av) = {
 286         .name   = UBOOT_DM_CLK_IMX_PLLV3_AV,
 287         .id     = UCLASS_CLK,
 288         .ops    = &clk_pllv3_av_ops,
 289         .flags = DM_FLAG_PRE_RELOC,
 290 };