// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*/
#include <common.h>
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
+ const char *conn;
+
+ /* Do NOT apply fixup for backplane modes specified in DT */
+ if (phyc == PHY_INTERFACE_MODE_XGMII) {
+ conn = fdt_getprop(blob, offset, "phy-connection-type", NULL);
+ if (is_backplane_mode(conn))
+ return 0;
+ }
return fdt_setprop_string(blob, offset, "phy-connection-type",
phy_string_for_interface(phyc));
}
#define DCFG_PORSR1 0x000
#define DCFG_PORSR1_RCW_SRC 0xff800000
#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
+#define DCFG_RCWSR12 0x12c
+#define DCFG_RCWSR12_SDHC_SHIFT 24
+#define DCFG_RCWSR12_SDHC_MASK 0x7
#define DCFG_RCWSR13 0x130
+#define DCFG_RCWSR13_SDHC_SHIFT 3
+#define DCFG_RCWSR13_SDHC_MASK 0x7
#define DCFG_RCWSR13_DSPI (0 << 8)
#define DCFG_RCWSR15 0x138
#define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2014 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
{
+ const char *conn;
+
+ /* Do NOT apply fixup for backplane modes specified in DT */
+ if (phyc == PHY_INTERFACE_MODE_XGMII) {
+ conn = fdt_getprop(blob, offset, "phy-connection-type", NULL);
+ if (is_backplane_mode(conn))
+ return 0;
+ }
return fdt_setprop_string(blob, offset, "phy-connection-type",
phy_string_for_interface(phyc));
}
print_ddr_info(0);
}
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+ void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
+ char esdhc1_path[] = "/soc/mmc@2140000";
+ char esdhc2_path[] = "/soc/mmc@2150000";
+ char dspi1_path[] = "/soc/spi@2100000";
+ char dspi2_path[] = "/soc/spi@2110000";
+ u32 mux_sdhc1, mux_sdhc2;
+ u32 io = 0;
+
+ /*
+ * The PMUX IO-expander for mux select is used to control
+ * the muxing of various onboard interfaces.
+ */
+
+ io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
+ mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
+
+ /* Disable esdhc1/dspi1 if not selected. */
+ if (mux_sdhc1 != 0)
+ do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+ sizeof("disabled"), 1);
+ if (mux_sdhc1 != 2)
+ do_fixup_by_path(blob, dspi1_path, "status", "disabled",
+ sizeof("disabled"), 1);
+
+ io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
+ mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
+
+ /* Disable esdhc2/dspi2 if not selected. */
+ if (mux_sdhc2 != 0)
+ do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
+ sizeof("disabled"), 1);
+ if (mux_sdhc2 != 2)
+ do_fixup_by_path(blob, dspi2_path, "status", "disabled",
+ sizeof("disabled"), 1);
+
+ return 0;
+}
+
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*/
#include <common.h>
enum fm_port port, int offset)
{
struct fixed_link f_link;
- const u32 *handle;
- const char *prop = NULL;
- int off;
+ const char *phyconn;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
switch (port) {
"qsgmii");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
(port == FM1_10GEC1 || port == FM1_10GEC2)) {
- handle = fdt_getprop(fdt, offset, "phy-handle", NULL);
- prop = NULL;
- if (handle) {
- off = fdt_node_offset_by_phandle(fdt,
- fdt32_to_cpu(*handle));
- prop = fdt_getprop(fdt, off, "backplane-mode", NULL);
- }
- if (!prop || strcmp(prop, "10gbase-kr")) {
+ phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
+ if (is_backplane_mode(phyconn)) {
+ /* Backplane KR mode: skip fixups */
+ printf("Interface %d in backplane KR mode\n", port);
+ } else {
/* XFI interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*
*/
return offset;
}
+ phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
+ if (is_backplane_mode(phy_string)) {
+ /* Backplane KR mode: skip fixups */
+ printf("Interface %d in backplane KR mode\n", dpmac_id);
+ return 0;
+ }
+
ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
if (ret)
printf("%d@%s %d\n", __LINE__, __func__, ret);
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
- u64 gic_lpi_base;
+ u64 __maybe_unused gic_lpi_base;
ft_cpu_setup(blob, bd);
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
*
* Shengzhou Liu <Shengzhou.Liu@freescale.com>
*/
char buf[32] = "serdes-1,";
struct fixed_link f_link;
int media_type = 0;
+ const char *phyconn;
int off;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
}
if (!media_type) {
- /* fixed-link is used for XFI fiber cable */
- f_link.phy_id = port;
- f_link.duplex = 1;
- f_link.link_speed = 10000;
- f_link.pause = 0;
- f_link.asym_pause = 0;
- fdt_delprop(fdt, offset, "phy-handle");
- fdt_setprop(fdt, offset, "fixed-link", &f_link,
- sizeof(f_link));
+ phyconn = fdt_getprop(fdt, offset,
+ "phy-connection-type",
+ NULL);
+ if (is_backplane_mode(phyconn)) {
+ /* Backplane KR mode: skip fixups */
+ printf("Interface %d in backplane KR mode\n",
+ port);
+ } else {
+ /* fixed-link for XFI fiber cable */
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link",
+ &f_link, sizeof(f_link));
+ }
} else {
/* set property for copper cable */
off = fdt_node_offset_by_compat_reg(fdt,
if (src == BOOT_SOURCE_IFC_NOR) {
addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
CONFIG_SYS_FSL_IFC_BASE);
+#ifdef CONFIG_CMD_NAND
} else if (src == BOOT_SOURCE_IFC_NAND) {
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
CONFIG_SYS_FMAN_FW_ADDR, rc);
}
+#endif
} else if (src == BOOT_SOURCE_QSPI_NOR) {
struct spi_flash *ucode_flash;
"kernel_size=0x2800000\0" \
"kernelheader_size=0x40000\0" \
"console=ttyS0,115200\0" \
+ "BOARD=ls1012afrwy\0" \
BOOTENV \
"boot_scripts=ls1012afrwy_boot.scr\0" \
"boot_script_hdr=hdr_ls1012afrwy_bs.out\0" \
"source ${scriptaddr}\0" \
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
- "bootm $load_addr#$board\0" \
+ "bootm $load_addr#$BOARD\0" \
"qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size; env exists secureboot " \
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
- "bootm $load_addr#$board\0" \
+ "bootm $load_addr#$BOARD\0" \
"sd_bootcmd=pfe stop; echo Trying load from sd card..;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
" && esbc_validate ${kernelheader_addr_r};" \
- "bootm $load_addr#$board\0"
+ "bootm $load_addr#$BOARD\0"
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
* Andy Fleming <afleming@gmail.com>
*
* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
[PHY_INTERFACE_MODE_NONE] = "",
};
+/* Backplane modes:
+ * are considered a sub-type of phy_interface_t: XGMII
+ * and are specified in "phy-connection-type" with one of the following strings
+ */
+static const char * const backplane_mode_strings[] = {
+ "10gbase-kr",
+ "40gbase-kr4",
+};
+
static inline const char *phy_string_for_interface(phy_interface_t i)
{
/* Default to unknown */
return phy_interface_strings[i];
}
+static inline bool is_backplane_mode(const char *phyconn)
+{
+ int i;
+
+ if (!phyconn)
+ return false;
+ for (i = 0; i < ARRAY_SIZE(backplane_mode_strings); i++) {
+ if (!strcmp(phyconn, backplane_mode_strings[i]))
+ return true;
+ }
+ return false;
+}
+
#endif /* _PHY_INTERFACE_H */
projects / oweals / u-boot.git / commitdiff