1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
10 #include <linux/errno.h>
11 #include <u-boot/crc.h>
14 #include <fsl_qe.h> /* For struct qe_firmware */
17 #include <spi_flash.h>
21 #include <asm/armv8/mmu.h>
22 #include <asm/arch/cpu.h>
25 struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
27 void *fm_muram_base(int fm_idx)
29 return muram[fm_idx].base;
32 void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
39 align_mask = align - 1;
40 save = muram[fm_idx].alloc;
42 off = (ulong)save & align_mask;
44 muram[fm_idx].alloc += (align - off);
45 off = size & align_mask;
47 size += (align - off);
48 if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
49 muram[fm_idx].alloc = save;
50 printf("%s: run out of ram.\n", __func__);
54 ret = muram[fm_idx].alloc;
55 muram[fm_idx].alloc += size;
56 memset((void *)ret, 0, size);
61 static void fm_init_muram(int fm_idx, void *reg)
65 muram[fm_idx].base = base;
66 muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
67 muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
68 muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
72 * fm_upload_ucode - Fman microcode upload worker function
74 * This function does the actual uploading of an Fman microcode
77 static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
78 u32 *ucode, unsigned int size)
81 unsigned int timeout = 1000000;
83 /* enable address auto increase */
84 out_be32(&imem->iadd, IRAM_IADD_AIE);
85 /* write microcode to IRAM */
86 for (i = 0; i < size / 4; i++)
87 out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
89 /* verify if the writing is over */
90 out_be32(&imem->iadd, 0);
91 while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
94 printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
96 /* enable microcode from IRAM */
97 out_be32(&imem->iready, IRAM_READY);
101 * Upload an Fman firmware
103 * This function is similar to qe_upload_firmware(), exception that it uploads
104 * a microcode to the Fman instead of the QE.
106 * Because the process for uploading a microcode to the Fman is similar for
107 * that of the QE, the QE firmware binary format is used for Fman microcode.
108 * It should be possible to unify these two functions, but for now we keep them
111 static int fman_upload_firmware(int fm_idx,
112 struct fm_imem *fm_imem,
113 const struct qe_firmware *firmware)
117 size_t calc_size = sizeof(struct qe_firmware);
119 const struct qe_header *hdr;
122 printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
126 hdr = &firmware->header;
127 length = be32_to_cpu(hdr->length);
129 /* Check the magic */
130 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
131 (hdr->magic[2] != 'F')) {
132 printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
137 /* Check the version */
138 if (hdr->version != 1) {
139 printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
144 /* Validate some of the fields */
145 if ((firmware->count != 1)) {
146 printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
150 /* Validate the length and check if there's a CRC */
151 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
153 for (i = 0; i < firmware->count; i++)
155 * For situations where the second RISC uses the same microcode
156 * as the first, the 'code_offset' and 'count' fields will be
157 * zero, so it's okay to add those.
159 calc_size += sizeof(u32) *
160 be32_to_cpu(firmware->microcode[i].count);
162 /* Validate the length */
163 if (length != calc_size + sizeof(u32)) {
164 printf("Fman%u: Invalid length in firmware header\n",
170 * Validate the CRC. We would normally call crc32_no_comp(), but that
171 * function isn't available unless you turn on JFFS support.
173 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
174 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
175 printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
179 /* Loop through each microcode. */
180 for (i = 0; i < firmware->count; i++) {
181 const struct qe_microcode *ucode = &firmware->microcode[i];
183 /* Upload a microcode if it's present */
184 if (be32_to_cpu(ucode->code_offset)) {
187 printf("Fman%u: Uploading microcode version %u.%u.%u\n",
188 fm_idx + 1, ucode->major, ucode->minor,
190 code = (void *)firmware +
191 be32_to_cpu(ucode->code_offset);
192 ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
193 fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
200 static u32 fm_assign_risc(int port_id)
203 risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
204 val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
205 val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
210 static void fm_init_fpm(struct fm_fpm *fpm)
215 setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
216 FMFPEE_CER | FMFPEE_DER);
218 /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
220 /* offline/parser port */
221 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
222 port_id = OH_PORT_ID_BASE + i;
223 val = fm_assign_risc(port_id);
224 out_be32(&fpm->fpmprc, val);
227 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
228 port_id = RX_PORT_1G_BASE + i;
229 val = fm_assign_risc(port_id);
230 out_be32(&fpm->fpmprc, val);
233 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
234 port_id = TX_PORT_1G_BASE + i;
235 val = fm_assign_risc(port_id);
236 out_be32(&fpm->fpmprc, val);
239 port_id = RX_PORT_10G_BASE;
240 val = fm_assign_risc(port_id);
241 out_be32(&fpm->fpmprc, val);
243 port_id = TX_PORT_10G_BASE;
244 val = fm_assign_risc(port_id);
245 out_be32(&fpm->fpmprc, val);
247 /* disable the dispatch limit in IM case */
248 out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
250 out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
252 /* clear risc events */
253 for (i = 0; i < 4; i++)
254 out_be32(&fpm->fpmcev[i], 0xffffffff);
257 out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
260 static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
267 /* alloc free buffer pool in MURAM */
268 base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
270 printf("%s: no muram for free buffer pool\n", __func__);
273 offset = base - fm_muram_base(fm_idx);
275 /* Need 128KB total free buffer pool size */
277 blk = FM_FREE_POOL_SIZE / 256;
278 /* in IM, we must not begin from offset 0 in MURAM */
279 val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
280 out_be32(&bmi->fmbm_cfg1, val);
282 /* disable all BMI interrupt */
283 out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
285 /* clear all events */
286 out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
289 * set port parameters - FMBM_PP_x
290 * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
291 * max dma 10G Rx/Tx=3, others is 1
292 * set port FIFO size - FMBM_PFS_x
293 * 4KB for all Rx and Tx ports
295 /* offline/parser port */
296 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
297 port_id = OH_PORT_ID_BASE + i - 1;
298 /* max tasks=1, max dma=1, no extra */
299 out_be32(&bmi->fmbm_pp[port_id], 0);
300 /* port FIFO size - 256 bytes, no extra */
301 out_be32(&bmi->fmbm_pfs[port_id], 0);
304 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
305 port_id = RX_PORT_1G_BASE + i - 1;
306 /* max tasks=4, max dma=1, no extra */
307 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
308 /* FIFO size - 4KB, no extra */
309 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
311 /* Tx 1G port FIFO size - 4KB, no extra */
312 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
313 port_id = TX_PORT_1G_BASE + i - 1;
314 /* max tasks=4, max dma=1, no extra */
315 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
316 /* FIFO size - 4KB, no extra */
317 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
320 port_id = RX_PORT_10G_BASE - 1;
321 /* max tasks=12, max dma=3, no extra */
322 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
323 /* FIFO size - 4KB, no extra */
324 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
327 port_id = TX_PORT_10G_BASE - 1;
328 /* max tasks=12, max dma=3, no extra */
329 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
330 /* FIFO size - 4KB, no extra */
331 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
333 /* initialize internal buffers data base (linked list) */
334 out_be32(&bmi->fmbm_init, FMBM_INIT_START);
339 static void fm_init_qmi(struct fm_qmi_common *qmi)
341 /* disable all error interrupts */
342 out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
343 /* clear all error events */
344 out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
346 /* disable all interrupts */
347 out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
348 /* clear all interrupts */
349 out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
352 /* Init common part of FM, index is fm num# like fm as above */
353 #ifdef CONFIG_TFABOOT
354 int fm_init_common(int index, struct ccsr_fman *reg)
358 enum boot_src src = get_boot_src();
360 if (src == BOOT_SOURCE_IFC_NOR) {
361 addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
362 CONFIG_SYS_FSL_IFC_BASE);
363 #ifdef CONFIG_CMD_NAND
364 } else if (src == BOOT_SOURCE_IFC_NAND) {
365 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
367 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
369 rc = nand_read(get_nand_dev_by_index(0),
370 (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
371 &fw_length, (u_char *)addr);
372 if (rc == -EUCLEAN) {
373 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
374 CONFIG_SYS_FMAN_FW_ADDR, rc);
377 } else if (src == BOOT_SOURCE_QSPI_NOR) {
378 struct spi_flash *ucode_flash;
380 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
383 #ifdef CONFIG_DM_SPI_FLASH
386 /* speed and mode will be read from DT */
387 ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
388 CONFIG_ENV_SPI_CS, 0, 0, &new);
390 ucode_flash = dev_get_uclass_priv(new);
392 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
394 CONFIG_ENV_SPI_MAX_HZ,
395 CONFIG_ENV_SPI_MODE);
398 printf("SF: probe for ucode failed\n");
400 ret = spi_flash_read(ucode_flash,
401 CONFIG_SYS_FMAN_FW_ADDR +
402 CONFIG_SYS_FSL_QSPI_BASE,
403 CONFIG_SYS_QE_FMAN_FW_LENGTH,
406 printf("SF: read for ucode failed\n");
407 spi_flash_free(ucode_flash);
409 } else if (src == BOOT_SOURCE_SD_MMC) {
410 int dev = CONFIG_SYS_MMC_ENV_DEV;
412 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
413 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
414 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
415 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
418 printf("\nMMC cannot find device for ucode\n");
420 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
423 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
430 /* Upload the Fman microcode if it's present */
431 rc = fman_upload_firmware(index, ®->fm_imem, addr);
434 env_set_addr("fman_ucode", addr);
436 fm_init_muram(index, ®->muram);
437 fm_init_qmi(®->fm_qmi_common);
438 fm_init_fpm(®->fm_fpm);
440 /* clear DMA status */
441 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
444 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
446 return fm_init_bmi(index, ®->fm_bmi_common);
449 int fm_init_common(int index, struct ccsr_fman *reg)
452 #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
453 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
454 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
455 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
456 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
458 rc = nand_read(get_nand_dev_by_index(0),
459 (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
460 &fw_length, (u_char *)addr);
461 if (rc == -EUCLEAN) {
462 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
463 CONFIG_SYS_FMAN_FW_ADDR, rc);
465 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH)
466 struct spi_flash *ucode_flash;
467 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
470 #ifdef CONFIG_DM_SPI_FLASH
473 /* speed and mode will be read from DT */
474 ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
477 ucode_flash = dev_get_uclass_priv(new);
479 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
480 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
483 printf("SF: probe for ucode failed\n");
485 ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
486 CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
488 printf("SF: read for ucode failed\n");
489 spi_flash_free(ucode_flash);
491 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
492 int dev = CONFIG_SYS_MMC_ENV_DEV;
493 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
494 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
495 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
496 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
499 printf("\nMMC cannot find device for ucode\n");
501 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
504 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
507 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
508 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
513 /* Upload the Fman microcode if it's present */
514 rc = fman_upload_firmware(index, ®->fm_imem, addr);
517 env_set_addr("fman_ucode", addr);
519 fm_init_muram(index, ®->muram);
520 fm_init_qmi(®->fm_qmi_common);
521 fm_init_fpm(®->fm_fpm);
523 /* clear DMA status */
524 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
527 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
529 return fm_init_bmi(index, ®->fm_bmi_common);