ARM: tegra: Fix mux type for disp1 and disp2 clocks on Tegra210

On Tegra210 the parents for the disp1 and disp2 clocks are slightly
different from earlier chips. Only pll_p, pll_d_out0, pll_d2_out0 and
clk_m are valid parents (technically pll_d_out is as well, but U-Boot
doesn't know anything about it). Fix up the type name and the mux
definition.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index 06068c4b7b8d4406249b645138d59d5380b1d248..0d7cafea2017b4545b2e965905bf8e73878fad7a 100644 (file)
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -40,7 +40,7 @@ enum clock_type_id {
        CLOCK_TYPE_PDCT,
        CLOCK_TYPE_ACPT,
        CLOCK_TYPE_ASPTE,
-       CLOCK_TYPE_PMDACD2T,
+       CLOCK_TYPE_PDD2T,
        CLOCK_TYPE_PCST,
        CLOCK_TYPE_DP,
 
@@ -97,8 +97,8 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
        { CLK(AUDIO),   CLK(SFROM32KHZ),        CLK(PERIPH),    CLK(OSC),
                CLK(EPCI),      CLK(NONE),      CLK(NONE),      CLK(NONE),
                MASK_BITS_31_29},
-       { CLK(PERIPH),  CLK(MEMORY),    CLK(DISPLAY),   CLK(AUDIO),
-               CLK(CGENERAL),  CLK(DISPLAY2),  CLK(OSC),       CLK(NONE),
+       { CLK(PERIPH),  CLK(NONE),      CLK(DISPLAY),   CLK(NONE),
+               CLK(NONE),      CLK(DISPLAY2),  CLK(OSC),       CLK(NONE),
                MASK_BITS_31_29},
        { CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ),        CLK(OSC),
                CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
@@ -174,8 +174,8 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
        TYPE(PERIPHC_0bh,       CLOCK_TYPE_NONE),
        TYPE(PERIPHC_0ch,       CLOCK_TYPE_NONE),
        TYPE(PERIPHC_SBC1,      CLOCK_TYPE_PC2CC3M_T),
-       TYPE(PERIPHC_DISP1,     CLOCK_TYPE_PMDACD2T),
-       TYPE(PERIPHC_DISP2,     CLOCK_TYPE_PMDACD2T),
+       TYPE(PERIPHC_DISP1,     CLOCK_TYPE_PDD2T),
+       TYPE(PERIPHC_DISP2,     CLOCK_TYPE_PDD2T),
 
        /* 0x10 */
        TYPE(PERIPHC_10h,       CLOCK_TYPE_NONE),