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ARM: tegra: Fix mux type for disp1 and disp2 clocks on Tegra210
authorThierry Reding <treding@nvidia.com>
Mon, 15 Apr 2019 09:32:15 +0000 (11:32 +0200)
committerTom Warren <twarren@nvidia.com>
Wed, 5 Jun 2019 16:16:32 +0000 (09:16 -0700)
commitbca7910b7dad875e3e7d8e45dd41ab8a07e36133
treefa0f127fb8dae876ca8eb410a0c38b8575cab4d8tree | snapshot
parent0c4e2658e8e8489956e48a6c9842c5d21b9593fecommit | diff
ARM: tegra: Fix mux type for disp1 and disp2 clocks on Tegra210

On Tegra210 the parents for the disp1 and disp2 clocks are slightly
different from earlier chips. Only pll_p, pll_d_out0, pll_d2_out0 and
clk_m are valid parents (technically pll_d_out is as well, but U-Boot
doesn't know anything about it). Fix up the type name and the mux
definition.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/mach-tegra/tegra210/clock.c diff | blob | history
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