ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
-M: Fabio Estevam <fabio.estevam@nxp.com>
+M: Fabio Estevam <festevam@gmail.com>
R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-imx.git
SPL: spl/u-boot-spl.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
-ifeq ($(CONFIG_ARCH_IMX8M), y)
+ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y)
flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
endif
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8))
libs-y += arch/arm/mach-imx/
endif
else
imx6ul-isiot-nand.dtb \
imx6ul-opos6uldev.dtb \
imx6ul-14x14-evk.dtb \
- imx6ul-9x9-evk.dtb
+ imx6ul-9x9-evk.dtb \
+ imx6ul-phycore-segin.dtb
dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
-dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
- imx7d-sdb.dtb \
+dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+&mu {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pd_lsio {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+ u-boot,dm-spl;
+};
+
+&pd_conn {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+ u-boot,dm-spl;
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpio6 {
+ u-boot,dm-spl;
+};
+
+&gpio7 {
+ u-boot,dm-spl;
+};
+
+&lpuart0 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
/dts-v1/;
#include "fsl-imx8qxp.dtsi"
+#include "fsl-imx8qxp-mek-u-boot.dtsi"
/ {
model = "Freescale i.MX8QXP MEK";
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
- MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
- MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
- MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
- MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
- MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
- MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
-
- MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
- MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
- MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
- MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
- MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
- MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
-
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
>;
};
+ pinctrl_esdhc1: esdhc1grp {
+ fsl,pins = <
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ >;
+ };
+
+ pinctrl_esdhc2: esdhc2grp {
+ fsl,pins = <
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
+ MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
+ MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4
status = "okay";
};
+&esdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1>;
+ cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&esdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&fec {
pinctrl-names = "default";
phy-mode = "rmii";
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
+ mmc0 = &esdhc1;
+ mmc1 = &esdhc2;
};
tzic: tz-interrupt-controller@fffc000 {
reg = <0x50000000 0x10000000>;
ranges;
+ spba@50000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x50000000 0x40000>;
+ ranges;
+
+ esdhc1: esdhc@50004000 {
+ compatible = "fsl,imx53-esdhc";
+ reg = <0x50004000 0x4000>;
+ interrupts = <1>;
+ clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC1_PER_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ esdhc2: esdhc@50008000 {
+ compatible = "fsl,imx53-esdhc";
+ reg = <0x50008000 0x4000>;
+ interrupts = <2>;
+ clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC2_PER_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+ };
+
iomuxc: iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc";
reg = <0x53fa8000 0x4000>;
--- /dev/null
+/*
+ * Copyright 2018 Logic PD, Inc.
+ * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+ keyboard {
+ compatible = "gpio-keys";
+
+ btn0 {
+ gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
+ label = "btn0";
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+
+ btn1 {
+ gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
+ label = "btn1";
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+
+ btn2 {
+ gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
+ label = "btn2";
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ btn3 {
+ gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
+ label = "btn3";
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ gen_led0 {
+ label = "led0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led0>;
+ gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu0";
+ };
+
+ gen_led1 {
+ label = "led1";
+ gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ gen_led2 {
+ label = "led2";
+ gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ gen_led3 {
+ label = "led3";
+ gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ reg_usb_otg_vbus: regulator-otg-vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_h1_vbus: regulator-usbh1vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_3v3: regulator-3v3@2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_3v3>;
+ compatible = "regulator-fixed";
+ regulator-name = "reg_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_enet: regulator-ethernet@3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_pwr>;
+ compatible = "regulator-fixed";
+ regulator-name = "ethernet-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ vin-supply = <&sw4_reg>;
+ };
+
+ reg_audio: regulator-audio@4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_audio>;
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_aud";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <®_3v3>;
+ };
+
+ reg_hdmi: regulator-hdmi@5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_hdmi>;
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_3v3>;
+ };
+
+ reg_uart3: regulator-uart3@6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_uart3>;
+ compatible = "regulator-fixed";
+ regulator-name = "uart3-supply";
+ gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <®_3v3>;
+ };
+
+ reg_1v8: regulator-1v8@7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_1v8>;
+ compatible = "regulator-fixed";
+ regulator-name = "1v8-supply";
+ gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <®_3v3>;
+ };
+
+ reg_pcie: regulator@8 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie_reg>;
+ regulator-name = "MPCIE_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ mipi_pwr: regulator@9 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mipi_pwr>;
+ regulator-name = "mipi_pwr_en";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-wm8962";
+ model = "wm8962-audio";
+ ssi-controller = <&ssi2>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "Ext Spk", "SPKOUTL",
+ "Ext Spk", "SPKOUTR",
+ "AMIC", "MICBIAS",
+ "IN3R", "AMIC";
+ mux-int-port = <2>;
+ mux-ext-port = <4>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "disabled";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-duration = <10>;
+ phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
+ phy-supply = <®_enet>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ codec: wm8962@1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ DCVDD-supply = <®_audio>;
+ DBVDD-supply = <®_audio>;
+ AVDD-supply = <®_audio>;
+ CPVDD-supply = <®_audio>;
+ MICVDD-supply = <®_audio>;
+ PLLVDD-supply = <®_audio>;
+ SPKVDD1-supply = <®_audio>;
+ SPKVDD2-supply = <®_audio>;
+ gpio-cfg = <
+ 0x0000 /* 0:Default */
+ 0x0000 /* 1:Default */
+ 0x0013 /* 2:FN_DMICCLK */
+ 0x0000 /* 3:Default */
+ 0x8014 /* 4:FN_DMICCDAT */
+ 0x0000 /* 5:Default */
+ >;
+ };
+};
+
+&i2c3 {
+ ov5640: camera@10 {
+ compatible = "ovti,ov5640";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+ reg = <0x10>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ DOVDD-supply = <&mipi_pwr>;
+ AVDD-supply = <&mipi_pwr>;
+ DVDD-supply = <&mipi_pwr>;
+ reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+
+ port {
+ ov5640_to_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi2_in>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ pcf8575: gpio@20 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcf8574>;
+ compatible = "nxp,pcf8575";
+ reg = <0x20>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ lines-initial-states = <0x0710>;
+ wakeup-source;
+ };
+};
+
+&mipi_csi {
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_csi2_in: endpoint {
+ remote-endpoint = <&ov5640_to_mipi_csi2>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ vpcie-supply = <®_pcie>;
+ /* fsl,max-link-speed = <2>; */
+};
+
+&ssi2 {
+ status = "okay";
+};
+
+&iomuxc {
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
+ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
+ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
+ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_enet_pwr: enet_pwr {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
+ >;
+ };
+
+ pinctrl_mipi_pwr: pwr_mipi {
+ fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
+ };
+
+ pinctrl_ov5640: ov5640grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b1
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b1
+ >;
+ };
+
+ pinctrl_reg_hdmi: reg_hdmi {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0xd17059
+ MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17069
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10069
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17069
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17069
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17069
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17069
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* ENET_INT */
+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1b0b0 /* ETHR_nRST */
+ >;
+ };
+
+ pinctrl_reg_audio: audio-reg {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+ >;
+ };
+
+ pinctrl_pcie: pcie {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_pcie_reg: pciereggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+
+ pinctrl_pcf8574: pcf8575-pins {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
+ >;
+ };
+
+ pinctrl_lcd: lcdgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* R_LCD_DCLK */
+ MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* R_LCD_HSYNC */
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* R_LCD_VSYNC */
+ MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* R_LCD_MDISP */
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_reg_uart3: uart3reg {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ >;
+ };
+
+ pinctrl_reg_3v3: reg-3v3 {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0
+ >;
+ };
+
+ pinctrl_reg_1v8: reg-1v8 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ >;
+ };
+
+ pinctrl_led0: led0 {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ >;
+ };
+};
--- /dev/null
+/*
+ * Copyright 2018 Logic PD
+ * This file is adapted from imx6qdl-sabresd.dtsi.
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
+
+ reg_wl18xx_vmmc: regulator-wl18xx {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1837";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+};
+
+/* Reroute power feeding the CPU to come from the external PMIC */
+®_arm
+{
+ vin-supply = <&sw1a_reg>;
+};
+
+®_soc
+{
+ vin-supply = <&sw1c_reg>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+ nand-on-flash-bbt;
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ pmic: pfuze100@08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-name = "vddcore";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-name = "vddsoc";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "gen_3v3";
+ regulator-boot-on;
+ /* regulator-always-on; */
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-name = "sw3a_vddr";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-name = "sw3b_vddr";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "gen_rgmii";
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ regulator-name = "gen_5v0";
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "gen_vsns";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "gen_1v5";
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-name = "vgen2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-name = "gen_vadj_0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-name = "gen_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-name = "gen_adj_1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-name = "gen_2v5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ coin_reg: coin {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ temp_sense0: tmp102@4a {
+ compatible = "ti,tmp102";
+ reg = <0x4a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tempsense>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ temp_sense1: tmp102@49 {
+ compatible = "ti,tmp102";
+ reg = <0x49>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ mfg_eeprom: at24@51 {
+ compatible = "atmel,24c64";
+ pagesize = <32>;
+ read-only;
+ reg = <0x51>;
+ };
+
+ user_eeprom: at24@52 {
+ compatible = "atmel,24c64";
+ pagesize = <32>;
+ reg = <0x52>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
+ MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049
+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */
+ >;
+ };
+
+ pinctrl_tempsense: tempsensegrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Temp Sense Alert */
+ >;
+ };
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+ uart-has-rtscts;
+ bluetooth {
+ compatible = "ti,wl1837-st";
+ enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ non-removable;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ status = "okay";
+ vmmc-supply = <&sw2_reg>;
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ non-removable;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_wl18xx_vmmc>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1837";
+ reg = <2>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
/*
- * Copyright 2017 Logic PD, Inc.
+ * Copyright 2018 Logic PD, Inc.
* Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
*/
/dts-v1/;
-
-#include "imx6qdl-logicpd.dtsi"
+#include "imx6q.dtsi"
+#include "imx6-logicpd-som.dtsi"
+#include "imx6-logicpd-baseboard.dtsi"
/ {
- model = "Logic PD i.MX6QDL SOM";
+ model = "Logic PD i.MX6QD SOM-M3 (HDMI)";
compatible = "fsl,imx6q";
- reg_usb_otg_vbus: regulator-otg-vbus@0 {
- compatible = "regulator-fixed";
- regulator-name = "usb_otg_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ backlight: backlight_lvds {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 20000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ power-supply = <®_lcd>;
};
- reg_usb_h1_vbus: regulator-usbh1vbus@1 {
+ reg_lcd: regulator-lcd {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_reg>;
compatible = "regulator-fixed";
- regulator-name = "usb_h1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
+ regulator-name = "lcd_panel_pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ vin-supply = <®_3v3>;
+ startup-delay-us = <500000>;
};
- reg_3v3: regulator-3v3@2 {
+ lcd_reset: lcd_reset {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_reset>;
compatible = "regulator-fixed";
- regulator-name = "reg_3v3";
+ regulator-name = "nLCD_RESET";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <®_lcd>;
+ };
+
+ panel-lvds0 {
+ compatible = "ampire,am800480b3tmqw";
+ backlight = <&backlight>;
+
+ port {
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
};
};
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
status = "okay";
};
-&usbh1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbh1>;
- vbus-supply = <®_usb_h1_vbus>;
- status = "okay";
+&i2c1 {
+ ili_touch: ilitouch@26 {
+ compatible = "ili,ili2117a";
+ reg = <0x26>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touchscreen>;
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>;
+ ili2117a,poll-period = <10>;
+ ili2117a,max-touch = <2>;
+ };
};
-&usbh2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbh2>;
- phy_type = "hsic";
- disable-over-current;
- status = "okay";
+®_hdmi {
+ regulator-always-on;
};
-&usbotg {
- vbus-supply = <®_usb_otg_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg>;
- disable-over-current;
+&ldb {
status = "okay";
+
+ lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+ };
+
};
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rmii";
- phy-speed = <10>;
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+ <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
+};
+
+&pwm3 {
status = "okay";
};
&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- no-1-8-v;
- keep-power-in-suspend;
- status = "okay";
};
&iomuxc {
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* nINT */
- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 /* Ethernet Reset */
- >;
- };
-
- pinctrl_gpio_leds: gpioledsgrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x130b0
- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x130b0
- MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x130b0
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
- >;
- };
- pinctrl_uart3: uart3grp {
+ pinctrl_lcd_reg: lcdreg {
fsl,pins = <
- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
+ MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x100b0 /* R_LCD_PANEL_PWR */
>;
};
- pinctrl_usbh1: usbh1grp {
+ pinctrl_lcd_reset: lcdreset {
fsl,pins = <
- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* USB_H1_PWR_EN */
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 /* LCD_nRESET */
>;
};
- pinctrl_usbh2: usbh2grp {
+ pinctrl_touchscreen: touchscreengrp {
fsl,pins = <
- MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x17030
- MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x13030
- >;
- };
-
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 /* USB_OTG_PWR_EN */
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* TOUCH_nPINTDAV */
>;
};
};
+
+++ /dev/null
-/*
- * Copyright 2016 Logic PD
- * This file is adapted from imx6qdl-sabresd.dtsi.
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "imx6q.dtsi"
-
-/ {
- chosen {
- stdout-path = &uart1;
- };
-
- memory {
- reg = <0x10000000 0x80000000>;
- };
-};
-
-/* Reroute power feeding the CPU to come from the external PMIC */
-®_arm
-{
- vin-supply = <&sw1a_reg>;
-};
-
-®_soc
-{
- vin-supply = <&sw1c_reg>;
-};
-
-&clks {
- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-};
-
-&i2c3 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-
- pmic: pfuze100@08 {
- compatible = "fsl,pfuze100";
- reg = <0x08>;
-
- regulators {
- sw1a_reg: sw1ab {
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1450000>;
- regulator-name = "vddcore";
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- sw1c_reg: sw1c {
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1450000>;
- regulator-name = "vddsoc";
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
- sw2_reg: sw2 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "gen_3v3";
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw3a_reg: sw3a {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-name = "sw3a_vddr";
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw3b_reg: sw3b {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <1975000>;
- regulator-name = "sw3b_vddr";
- regulator-boot-on;
- regulator-always-on;
- };
-
- sw4_reg: sw4 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "gen_rgmii";
- };
-
-
- swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- regulator-name = "gen_5v0";
- };
-
- snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "gen_vsns";
- regulator-boot-on;
- regulator-always-on;
- };
-
- vref_reg: vrefddr {
- regulator-boot-on;
- regulator-always-on;
- };
-
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "gen_1v5";
- };
-
- vgen2_reg: vgen2 {
- regulator-name = "vgen2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- vgen3_reg: vgen3 {
- regulator-name = "gen_vadj_0";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- vgen4_reg: vgen4 {
- regulator-name = "gen_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- vgen5_reg: vgen5 {
- regulator-name = "gen_adj_1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vgen6_reg: vgen6 {
- regulator-name = "gen_2v5";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- regulator-always-on;
- };
- };
- };
-
- mfg_eeprom: at24@51 {
- compatible = "atmel,24c64";
- pagesize = <32>;
- read-only;
- reg = <0x51>;
- };
-
- user_eeprom: at24@52 {
- compatible = "atmel,24c64";
- pagesize = <32>;
- reg = <0x52>;
- };
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
- MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0
- MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
- MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0
- MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0
- MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0
- MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0
- MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0
- MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0
- MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0
- MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0
- MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0
- MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0
- MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0
- MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0
- MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0
- MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0
- MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0
- MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0
- MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x80000000
- MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000
- MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x80000000
- MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000
- MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
- MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
- MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
- MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x80000000
- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000
- MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000
- MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x80000000
- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x80000000
- MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x80000000
- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
- MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x80000000
- MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x80000000
- MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x80000000
- MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x80000000
- MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x80000000
- MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x80000000
- MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x80000000
- MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x80000000
- MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000
- MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
- MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x80000000
- MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x80000000
- MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x80000000
- MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000
- MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000
- MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000
- MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
- MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
- MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
- MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x80000000
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
- MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
- MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x80000000
- MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000
- MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000
- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000
- MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000
- MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x80000000
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
- MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000
- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000
- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000
- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000
- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000
- MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000
- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
- MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x80000000
- MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x80000000
- MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x80000000
- MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x80000000
- MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x80000000
- MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x80000000
- MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x80000000
- MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x80000000
- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x80000000
- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WL_IRQ */
- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1f0b0 /* WLAN_EN */
- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1f0b0 /* BT_EN */
- >;
- };
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
- keep-power-in-suspend;
- enable-sdio-wakeup;
- status = "okay";
-};
-
-&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- non-removable;
- keep-power-in-suspend;
- enable-sdio-wakeup;
- vmmc-supply = <&sw2_reg>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- wlcore: wlcore@0 {
- compatible = "ti,wl1837";
- reg = <2>;
- interrupt-parent = <&gpio7>;
- interrupts = <1 GPIO_ACTIVE_HIGH>;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on dts[i] from Phytec barebox port:
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+
+#include "imx6ul.dtsi"
+
+/ {
+ model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
+ compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <1>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ fsl,no-blockmark-swap;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x0 0x400000>;
+ };
+
+ partition@400000 {
+ label = "uboot-env";
+ reg = <0x400000 0x100000>;
+ };
+
+ partition@500000 {
+ label = "root";
+ reg = <0x500000 0x0>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ eeprom@52 {
+ compatible = "cat,24c32";
+ reg = <0x52>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ bus-width = <0x4>;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
+ MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
+ MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
+ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
+ MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
+ MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
+ MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
+ MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
+ MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
+ MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
+ MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
+ MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
+ MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
+ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
+ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
+ >;
+ };
+
+ pinctrl_i2c1: i2cgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1grp_gpio {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
+ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
+
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on dts[i] from Phytec barebox port:
+ * Copyright (C) 2016 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6ul-pcl063.dtsi"
+
+/ {
+ model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
+ compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063",
+ "fsl,imx6ul";
+};
+
+&i2c1 {
+ i2c_rtc: rtc@68 {
+ compatible = "microcrystal,rv4162";
+ reg = <0x68>;
+ status = "okay";
+ };
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1_id>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
+ MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
+ MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_usb_otg1_id: usbotg1idgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
+ >;
+ };
+
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+/dts-v1/;
+#include "imx7-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7D 1GB (eMMC)";
+ compatible = "toradex,imx7d-colibri-emmc", "fsl,imx7d";
+
+ aliases {
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc1;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
+ >;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+/dts-v1/;
+#include "imx7-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7S/D";
+ compatible = "toradex,imx7-colibri", "fsl,imx7";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ fsl,use-minimum-ecc;
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_gpmi_nand: gpmi-nand-grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CLK__NAND_CLE 0x71
+ MX7D_PAD_SD3_CMD__NAND_ALE 0x71
+ MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
+ MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
+ MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
+ MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
+ MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
+ MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
+ MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
+ MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
+ MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
+ MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
+ MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
+ MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
+ >;
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright 2016 Toradex AG
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include "imx7d.dtsi"
-
-/ {
- model = "Toradex Colibri iMX7S/D";
- compatible = "toradex,imx7-colibri", "fsl,imx7";
-
- chosen {
- stdout-path = &uart1;
- };
-};
-
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- fsl,use-minimum-ecc;
- nand-on-flash-bbt;
- nand-ecc-mode = "hw";
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
- scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- rn5t567@33 {
- compatible = "ricoh,rn5t567";
- reg = <0x33>;
- };
-};
-
-&i2c4 {
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c4>;
- pinctrl-1 = <&pinctrl_i2c4_gpio>;
- sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>;
- scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
- uart-has-rtscts;
- fsl,dte-mode;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_gpmi_nand: gpmi-nand-grp {
- fsl,pins = <
- MX7D_PAD_SD3_CLK__NAND_CLE 0x71
- MX7D_PAD_SD3_CMD__NAND_ALE 0x71
- MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
- MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
- MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
- MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
- MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
- MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
- MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
- MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
- MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
- MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
- MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
- MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
- >;
- };
-
- pinctrl_i2c4: i2c4-grp {
- fsl,pins = <
- MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
- MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
- >;
- };
-
- pinctrl_i2c4_gpio: i2c4-gpio-grp {
- fsl,pins = <
- MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
- MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
- >;
- };
-
- pinctrl_uart1: uart1-grp {
- fsl,pins = <
- MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
- MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
- MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
- MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
- >;
- };
-
- pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
- fsl,pins = <
- MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
- MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
- >;
- };
-};
-
-&iomuxc_lpsr {
- pinctrl_i2c1: i2c1-grp {
- fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
- MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1-gpio-grp {
- fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
- MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
- >;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2016-2019 Toradex AG
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx7d.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ rn5t567@33 {
+ compatible = "ricoh,rn5t567";
+ reg = <0x33>;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
+ uart-has-rtscts;
+ fsl,dte-mode;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
+ no-1-8-v;
+ cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c4: i2c4-grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
+ MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4-gpio-grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
+ MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
+ >;
+ };
+
+ pinctrl_uart1: uart1-grp {
+ fsl,pins = <
+ MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
+ MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
+ MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
+ MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
+ >;
+ };
+
+ pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
+ MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1-grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ >;
+ };
+};
+
+&iomuxc_lpsr {
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
+ >;
+ };
+
+ pinctrl_cd_usdhc1: usdhc1-cd-grp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */
+ >;
+ };
+};
#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
-#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
-#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
-#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 NXP Semiconductors.
+ * Author: Fabio Estevam <fabio.estevam@nxp.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx7s.dtsi"
+
+/ {
+ model = "Warp i.MX7 Board";
+ compatible = "warp,imx7s-warp", "fsl,imx7s";
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ aliases {
+ mmc0 = &usdhc3;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&pinctrl_gpio>;
+ autorepeat;
+
+ back {
+ label = "Back";
+ gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_BACK>;
+ wakeup-source;
+ };
+ };
+
+ reg_brcm: regulator-brcm {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_brcm_reg>;
+ regulator-name = "brcm_reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <200000>;
+ };
+
+ reg_bt: regulator-bt {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bt_reg>;
+ enable-active-high;
+ gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+ regulator-name = "bt_reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx7-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,cpu {
+ sound-dai = <&sai1>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+ };
+ };
+};
+
+&clks {
+ assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+ assigned-clock-rates = <884736000>;
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: pfuze3000@8 {
+ compatible = "fsl,pfuze3000";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1a {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ /* use sw1c_reg to align with pfuze100/pfuze200 */
+ sw1c_reg: sw1b {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vldo2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vccsd {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: v33 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ codec: sgtl5000@a {
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ compatible = "fsl,sgtl5000";
+ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1_mclk>;
+ VDDA-supply = <&vgen4_reg>;
+ VDDIO-supply = <&vgen4_reg>;
+ VDDD-supply = <&vgen2_reg>;
+ };
+
+ mpl3115@60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ };
+};
+
+&sai1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
+ <&clks IMX7D_SAI1_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+ assigned-clock-rates = <0>, <36864000>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6>;
+ assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ fsl,dte-mode;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ keep-power-in-suspend;
+ no-1-8-v;
+ non-removable;
+ vmmc-supply = <®_brcm>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <8>;
+ no-1-8-v;
+ fsl,tuning-step = <2>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_brcm_reg: brcmreggrp {
+ fsl,pins = <
+ MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
+ >;
+ };
+
+ pinctrl_bt_reg: btreggrp {
+ fsl,pins = <
+ MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
+ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
+ MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
+ MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
+ MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
+ MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
+ MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
+ MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
+ >;
+ };
+
+ pinctrl_sai1_mclk: sai1mclkgrp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
+ MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
+ MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
+ MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
+ >;
+ };
+
+ pinctrl_uart6: uart6grp {
+ fsl,pins = <
+ MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79
+ MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
+ MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
+ MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
+ >;
+ };
+};
+
+&iomuxc_lpsr {
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
+ >;
+ };
+};
};
enum imx6_bmode_emi {
- IMX6_BMODE_ONENAND,
IMX6_BMODE_NOR,
+ IMX6_BMODE_ONENAND,
};
enum imx6_bmode {
#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28)
#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29)
+#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
+#define L2X0_CACHE_ID_PART_L310 (3 << 6)
+#define L2X0_CACHE_ID_RTL_MASK 0x3f
+#define L2X0_CACHE_ID_RTL_R3P2 0x8
+
struct pl310_regs {
u32 pl310_cache_id;
u32 pl310_cache_type;
obj-$(CONFIG_GPT_TIMER) += timer.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8))
obj-y += misc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
ifeq ($(CONFIG_ARCH_IMX8), y)
CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh
IMAGE_TYPE := imx8image
+SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout ]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi)
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
else ifeq ($(CONFIG_ARCH_IMX8M), y)
IMAGE_TYPE := imx8mimage
endif
endif
+ifeq ($(CONFIG_ARCH_IMX8), y)
+SPL:
+
+MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout -T $(IMAGE_TYPE) -e 0x100000
+flash.bin: MKIMAGEOUTPUT = flash.log
+
+flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
+ifeq ($(SPL_DEPFILE_EXISTS),0)
+ $(call if_changed,mkimage)
+endif
+endif
+
else
MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
-T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- unsigned int val;
+ unsigned int val, cache_id;
/*
val = readl(&pl310->pl310_prefetch_ctrl);
- /* Turn on the L2 I/D prefetch */
- val |= 0x30000000;
+ /* Turn on the L2 I/D prefetch, double linefill */
+ /* Set prefetch offset with any value except 23 as per errata 765569 */
+ val |= 0x7000000f;
/*
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
- * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+ * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL/SX/DQP
+ * is r3p2.
* But according to ARM PL310 errata: 752271
* ID: 752271: Double linefill feature can cause data corruption
* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
* Workaround: The only workaround to this erratum is to disable the
* double linefill feature. This is the default behavior.
*/
-
-#ifndef CONFIG_MX6Q
- val |= 0x40800000;
-#endif
+ cache_id = readl(&pl310->pl310_cache_id);
+ if (((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310)
+ && ((cache_id & L2X0_CACHE_ID_RTL_MASK) < L2X0_CACHE_ID_RTL_R3P2))
+ val &= ~(1 << 30);
writel(val, &pl310->pl310_prefetch_ctrl);
val = readl(&pl310->pl310_power_ctrl);
}
/* Verify if IVT DCD pointer is NULL */
- if (ivt->dcd)
- puts("Warning: DCD pointer should be NULL\n");
+ if (ivt->dcd) {
+ puts("Error: DCD pointer must be NULL\n");
+ goto hab_authentication_exit;
+ }
start = ddr_start;
bytes = image_size;
config IMX8
bool
+config MU_BASE_SPL
+ hex "MU base address used in SPL"
+ default 0x5d1b0000
+ help
+ SPL runs in EL3 mode, it use MU0_A to communicate with SCU.
+ So we could not reuse the one in dts which is for normal U-Boot.
+
config IMX8QXP
select IMX8
+ select SUPPORT_SPL
bool
config SYS_SOC
int arch_cpu_init(void)
{
- struct pass_over_info_t *pass_over = get_pass_over_info();
-
- if (pass_over && pass_over->g_ap_mu == 0) {
- /*
- * When ap_mu is 0, means the U-Boot booted
- * from first container
- */
- sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
+#ifdef CONFIG_SPL_BUILD
+ struct pass_over_info_t *pass_over;
+
+ if (is_soc_rev(CHIP_REV_A)) {
+ pass_over = get_pass_over_info();
+ if (pass_over && pass_over->g_ap_mu == 0) {
+ /*
+ * When ap_mu is 0, means the U-Boot booted
+ * from first container
+ */
+ sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
+ }
}
+#endif
return 0;
}
printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
}
-#if CONFIG_IS_ENABLED(CPU)
-struct cpu_imx_platdata {
- const char *name;
- const char *rev;
- const char *type;
- u32 cpurev;
- u32 freq_mhz;
-};
-
u32 get_cpu_rev(void)
{
u32 id = 0, rev = 0;
return (id << 12) | rev;
}
+#if CONFIG_IS_ENABLED(CPU)
+struct cpu_imx_platdata {
+ const char *name;
+ const char *rev;
+ const char *type;
+ u32 cpurev;
+ u32 freq_mhz;
+};
+
const char *get_imx8_type(u32 imxtype)
{
switch (imxtype) {
#include <asm/io.h>
#include <asm/mach-imx/regs-common.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* 1 second delay should be plenty of time for block reset. */
#define RESET_MAX_TIMEOUT 1000000
return 0;
}
+
+static ulong get_sp(void)
+{
+ ulong ret;
+
+ asm("mov %0, sp" : "=r"(ret) : );
+ return ret;
+}
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+ ulong sp, bank_end;
+ int bank;
+
+ sp = get_sp();
+ debug("## Current stack ends at 0x%08lx ", sp);
+
+ /* adjust sp by 16K to be safe */
+ sp -= 4096 << 2;
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ if (sp < gd->bd->bi_dram[bank].start)
+ continue;
+ bank_end = gd->bd->bi_dram[bank].start +
+ gd->bd->bi_dram[bank].size;
+ if (sp >= bank_end)
+ continue;
+ lmb_reserve(lmb, sp, bank_end - sp);
+ break;
+ }
+}
[ -z "$BL31" ] && BL31="bl31.bin"
[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000"
[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000"
+[ -z "$BL33_LOAD_ADDR" ] && BL33_LOAD_ADDR="0x40200000"
if [ ! -f $BL31 ]; then
echo "ERROR: BL31 file $BL31 NOT found" >&2
type = "standalone";
arch = "arm64";
compression = "none";
- load = <0x40200000>;
+ load = <$BL33_LOAD_ADDR>;
};
atf@1 {
description = "ARM Trusted Firmware";
select MX6QDL
select SUPPORT_SPL
+config TARGET_PCL063
+ bool "PHYTEC PCL063 (phyCORE-i.MX6UL)"
+ select MX6UL
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_I2C
+ select DM_MMC
+ select DM_SERIAL
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config TARGET_SECOMX6
bool "secomx6 boards"
source "board/grinn/liteboard/Kconfig"
source "board/phytec/pcm058/Kconfig"
source "board/phytec/pfla02/Kconfig"
+source "board/phytec/pcl063/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/samtec/vining_2000/Kconfig"
void reset_misc(void)
{
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_VIDEO_MXS
lcdif_power_down();
#endif
+#endif
}
return BOOT_DEVICE_NONE;
}
-#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
+#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
u32 spl_boot_device(void)
{
case SD3_BOOT:
case MMC3_BOOT:
return BOOT_DEVICE_MMC1;
+#elif defined(CONFIG_IMX8)
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ return BOOT_DEVICE_MMC2_2;
+ case SD3_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case FLEXSPI_BOOT:
+ return BOOT_DEVICE_SPI;
#elif defined(CONFIG_IMX8M)
case SD1_BOOT:
case MMC1_BOOT:
return BOOT_DEVICE_NONE;
}
}
-#endif /* CONFIG_MX7 || CONFIG_IMX8M */
+#endif /* CONFIG_MX7 || CONFIG_IMX8M || CONFIG_IMX8 */
#ifdef CONFIG_SPL_USB_GADGET
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
/* for MMC return either RAW or FAT mode */
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
+ case BOOT_DEVICE_MMC2_2:
#if defined(CONFIG_SPL_FAT_SUPPORT)
return MMCSD_MODE_FS;
#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
Build U-Boot
====================
-$ export ARCH=arm64
$ export CROSS_COMPILE=aarch64-poky-linux-
$ make imx8mq_evk_defconfig
$ make flash.bin
#
obj-y += imx8qxp_mek.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
Build U-Boot
============
-
+$ export ATF_LOAD_ADDR=0x80000000
+$ export BL33_LOAD_ADDR=0x80020000
$ make imx8qxp_mek_defconfig
-$ make
+$ make flash.bin
+$ dd if=u-boot.itb of=flash.bin bs=512 seek=528
Flash the binary into the SD card
=================================
Burn the flash.bin binary to SD card offset 32KB:
-$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=1024 seek=32
+$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
Boot
====
/* Add scfw image with exec attribute */
IMAGE SCU mx8qx-mek-scfw-tcm.bin
/* Add ATF image with exec attribute */
-IMAGE A35 bl31.bin 0x80000000
-/* Add U-Boot image with load attribute */
-DATA A35 u-boot-dtb.bin 0x80020000
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
--- /dev/null
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+ int offset;
+
+ uclass_find_first_device(UCLASS_MISC, &dev);
+
+ for (; dev; uclass_find_next_device(&dev)) {
+ if (device_probe(dev))
+ continue;
+ }
+
+ offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
+ while (offset != -FDT_ERR_NOTFOUND) {
+ lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
+ NULL, true);
+ offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
+ "nxp,imx8-pd");
+ }
+
+ uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
+
+ for (; dev; uclass_find_next_device(&dev)) {
+ if (device_probe(dev))
+ continue;
+ }
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
F: board/logicpd/imx6/
F: include/configs/imx6_logic.h
F: configs/imx6q_logic_defconfig
+F: arch/arm/dts/imx6-logicpd-baseboard.dtsi
+F: arch/arm/dts/imx6-logicpd-som.dtsi
+F: arch/arm/dts/imx6q-logicpd.dts
Flashing U-Boot into the SD card
--------------------------------
+U-Boot is now building with SPL enabled which means there are two files to
+load into the SD card. Make sure the card is formatted with at least two
+partitions with the first partition being FAT32. First copy u-boot-dtb.img
+to the first partition then burn SPL to the SD card with dd.
+The SPL portion is programmed into a certain location for use by the internal
+bootROM and it cannot be changed. The following instructions assume the SD
+card is located as /dev/sdb.
+
+ cp u-boot-dtb.img /dev/media/logic/boot
+ sudo dd if=SPL of=/dev/sdb bs=1k seek=1 oflag=sync status=none && sync
-See README.imximage for details on booting from SD
Flashing U-Boot into NAND
-------------------------
kobs-ng init -v -x u-boot-dtb.imx
+
+Using Falcon Mode
+-----------------
+With Falcon Mode enabled, U-Boot can be bypassed by having SPL directly load
+the kernel. The device tree, Kernel and boot args must first be configured,
+and stored to a file on the micro SD card called 'args'
+The kernel uImage is built with LOAD_ADDR=0x12000000 and the device tree is
+assummed to be imx6q-logicpd.dtb.
+
+By default the mmcroot is set to the baseboard.
+
+ # Establish bootargs
+ run mmcargs
+
+ # Load Linux Kernel uImage
+ fatload mmc 1 $loadaddr uImage
+
+ # Load Device Tree
+ run loadfdt
+
+ # Setup the blob that will get passed to the kernel
+ spl export fdt ${loadaddr} - ${fdt_addr_r}
+
+ # Note the starting and ending address of the updated device tree.
+ # for this example:
+ # Loading Device Tree to 1ffdf000, end 1fff038b ... OK
+ # Notice that 0x1fff038b - 1ffdf000 = 0x1138b
+ # now Add 1, so the length is 0x1138c.
+
+ fatwrite mmc 1 0x1ffdf000 args 0x1138c
+
+ # Reset the board and it will bypass U-Boot and SPL will directly boot
+ # the uImage
+
+To interrupt the boot sequence and force U-Boot to load, hold the 'c' button
+while starting.
+
Additional Support Documentation can be found at:
https://support.logicpd.com/
MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+#ifndef CONFIG_SPL_BUILD
static void fixup_enet_clock(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
dm_gpio_set_value(&reset, 1);
mdelay(50);
}
+#endif
static void setup_iomux_uart(void)
{
int board_early_init_f(void)
{
+#ifndef CONFIG_SPL_BUILD
fixup_enet_clock();
+#endif
setup_iomux_uart();
setup_nand_pins();
return 0;
}
#endif
+/* SD interface */
+#define USDHC_PAD_CTRL \
+ (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[] = {
+ {USDHC1_BASE_ADDR}, /* SOM */
+ {USDHC2_BASE_ADDR} /* Baseboard */
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned int reg = readl(&psrc->sbmr1) >> 11;
+ /*
+ * Upon reading BOOT_CFG register the following map is done:
+ * Bit 11 and 12 of BOOT_CFG register can determine the current
+ * mmc port
+ * 0x1 SD1-SOM
+ * 0x2 SD2-Baseboard
+ */
+
+ reg &= 0x3; /* Only care about bottom 2 bits */
+
+ switch (reg) {
+ case 0:
+ SETUP_IOMUX_PADS(usdhc1_pads);
+ usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ case 1:
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[1].sdhc_clk;
+ break;
+ }
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[reg]);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+#endif
+
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
--- /dev/null
+if TARGET_PCL063
+
+config SYS_BOARD
+ default "pcl063"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_CONFIG_NAME
+ default "pcl063"
+
+endif
--- /dev/null
+PCL063 BOARD
+M: Martyn Welch <martyn.welch@collabora.com>
+S: Maintained
+F: arch/arm/dts/imx6ul-pcl063.dtsi
+F: arch/arm/dts/imx6ul-phycore-segin.dts
+F: board/phytec/pcl063/
+F: configs/phycore_pcl063_defconfig
+F: include/configs/pcl063.h
--- /dev/null
+# Copyright (C) 2018 Collabora Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pcl063.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
--- /dev/null
+How to use U-Boot on PHYTEC phyBOARD-i.MX6UL-Segin
+--------------------------------------------------
+
+- Configure and build U-Boot for phyCORE-i.MX6UL:
+
+ $ make mrproper
+ $ make phycore_pcl063_defconfig
+ $ make
+
+ This will generate SPL and u-boot-dtb.img images.
+
+- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card:
+
+ $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+ $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+ JP1: Open: Boot from NAND
+ Closed: Boot from SD/MMC1
+
+- Connect the Serial cable to UART0 and the PC for the console.
+
+- Insert the micro SD card in the board and power it up.
+
+- U-Boot messages should come up.
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on board/ccv/xpress/xpress.c:
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <linux/bitops.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
+ PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart5_pads[] = {
+ MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+}
+
+#ifdef CONFIG_NAND_MXS
+
+#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
+
+#define NANDREADYPC MUX_PAD_CTRL(NAND_PAD_READY0_CTRL)
+
+static iomux_v3_cfg_t const gpmi_pads[] = {
+ MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+ MX6_PAD_NAND_READY_B__RAWNAND_READY_B | NANDREADYPC,
+};
+
+static void setup_gpmi_nand(void)
+{
+ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+ setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+ (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+}
+
+#endif /* CONFIG_NAND_MXS */
+
+#ifdef CONFIG_FEC_MXC
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
+ PAD_CTL_SRE_FAST)
+
+#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \
+ PAD_CTL_ODE)
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_pads[] = {
+ MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+ MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+ imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ /*
+ * Use 50M anatop loopback REF_CLK1 for ENET1,
+ * clear gpr1[13], set gpr1[17].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ /*
+ * Use 50M anatop loopback REF_CLK2 for ENET2,
+ * clear gpr1[14], set gpr1[18].
+ */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+ ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ enable_enet_clk(1);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /*
+ * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
+ * 50 MHz RMII clock mode.
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif /* CONFIG_FEC_MXC */
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: PHYTEC phyCORE-i.MX6UL\n");
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on board/ccv/xpress/spl.c:
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/crm_regs.h>
+#include <fsl_esdhc.h>
+
+/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_addds = 0x00000030,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_ddrpke = 0x00000000,
+ .grp_ddrmode = 0x00020000,
+ .grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_odt0 = 0x00000030,
+ .dram_odt1 = 0x00000030,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x00000000,
+ .p0_mpdgctrl0 = 0x41480148,
+ .p0_mprddlctl = 0x40403E42,
+ .p0_mpwrdlctl = 0x40405852,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = 0, /* Bus size = 16bit */
+ .cs_density = 18,
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 1,
+ .rtt_nom = 1,
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .pd_fast_exit = 1,
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .ddr_type = DDR_TYPE_DDR3,
+ .refsel = 1, /* Refresh cycles at 32KHz */
+ .refr = 7, /* 8 refresh commands per refresh cycle */
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 933,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 1,
+ .trcd = 1391,
+ .trcmin = 4791,
+ .trasmin = 3400,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0xFFFFFFFF, &ccm->CCGR0);
+ writel(0xFFFFFFFF, &ccm->CCGR1);
+ writel(0xFFFFFFFF, &ccm->CCGR2);
+ writel(0xFFFFFFFF, &ccm->CCGR3);
+ writel(0xFFFFFFFF, &ccm->CCGR4);
+ writel(0xFFFFFFFF, &ccm->CCGR5);
+ writel(0xFFFFFFFF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+ mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
+ PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+ {
+ .esdhc_base = USDHC1_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+#endif /* CONFIG_FSL_ESDHC */
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* Setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* Setup iomux and fec */
+ board_early_init_f();
+
+ /* Setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+}
#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
+
+#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
+ PAD_CTL_DSE_3P3V_49OHM)
+
+#define LCD_SYNC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
+ PAD_CTL_DSE_3P3V_196OHM)
+
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
/* I2C4 for PMIC */
static struct i2c_pads_info i2c_pad_info4 = {
.scl = {
return 0;
}
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+ MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
+ MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
+ MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
+ MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+ MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_lcd(void)
+{
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+ /* Set Brightness to high */
+ gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
+ /* Set LCD enable to high */
+ gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
+}
+#endif
+
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_VIDEO_MXS
+ setup_lcd();
+#endif
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
F: include/configs/colibri_imx7.h
F: configs/colibri_imx7_defconfig
F: configs/colibri_imx7_emmc_defconfig
+F: arch/arm/dts/imx7-colibri.dtsi
+F: arch/arm/dts/imx7-colibri-emmc.dts
+F: arch/arm/dts/imx7-colibri-rawnand.dts
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
- PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
-
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-static iomux_v3_cfg_t const usdhc1_pads[] = {
- MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
#ifdef CONFIG_USB_EHCI_MX7
static iomux_v3_cfg_t const usb_cdet_pads[] = {
MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
}
#endif
-#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
-static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
- MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
- MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-#endif
-
#ifdef CONFIG_VIDEO_MXS
static iomux_v3_cfg_t const lcd_pads[] = {
MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
-#ifdef CONFIG_FSL_ESDHC
-
-#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0)
-
-static struct fsl_esdhc_cfg usdhc_cfg[] = {
-#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
- {USDHC3_BASE_ADDR},
-#endif
- {USDHC1_BASE_ADDR, 0, 4},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
- ret = !gpio_get_value(USDHC1_CD_GPIO);
- break;
-#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
- case USDHC3_BASE_ADDR:
- ret = 1;
- break;
-#endif
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int i, ret;
- /* USDHC1 is mmc0, USDHC3 is mmc1 */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
- gpio_direction_input(USDHC1_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- break;
-#ifdef CONFIG_TARGET_COLIBRI_IMX7_EMMC
- case 1:
- imx_iomux_v3_setup_multiple_pads(usdhc3_emmc_pads,
- ARRAY_SIZE(usdhc3_emmc_pads));
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- break;
-#endif
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) than supported by the board\n", i + 1);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
PAD_CTL_HYS)
-#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
- PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
-
-#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
- PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
-
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
- .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
- .gp = IMX_GPIO_NR(4, 8),
- },
- .sda = {
- .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
- .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
- .gp = IMX_GPIO_NR(4, 9),
- },
-};
-#endif
int dram_init(void)
{
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
};
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- /* Assume uSDHC3 emmc is always present */
- return 1;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
-#ifdef CONFIG_POWER
-#define I2C_PMIC 0
-static struct pmic *pfuze;
+#ifdef CONFIG_DM_PMIC
int power_init_board(void)
{
- int ret;
- unsigned int reg, rev_id;
-
- ret = power_pfuze3000_init(I2C_PMIC);
- if (ret)
- return ret;
+ struct udevice *dev;
+ int ret, dev_id, rev_id;
- pfuze = pmic_get("PFUZE3000");
- ret = pmic_probe(pfuze);
- if (ret)
+ ret = pmic_get("pfuze3000", &dev);
+ if (ret == -ENODEV)
+ return 0;
+ if (ret != 0)
return ret;
- pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
- pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
- printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+ dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+ rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* disable Low Power Mode during standby mode */
- pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
+ pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
return 0;
}
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- #ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- #endif
-
return 0;
}
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX7=y
CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SECURE_BOOT=y
CONFIG_TARGET_COLIBRI_IMX7=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
+# CONFIG_CMD_DEKBLOB is not set
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
CONFIG_BOOTDELAY=1
+# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri iMX7 # "
# CONFIG_CMD_BOOTD is not set
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_NAND_TORTURE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+# CONFIG_BOOTP_PXE is not set
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx7-bcb),1536k(u-boot1)ro,1536k(u-boot2)ro,512k(u-boot-env),-(ubi)"
CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri"
+CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DFU_MMC=y
+CONFIG_FSL_CAAM=y
+CONFIG_DFU_NAND=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
CONFIG_NAND=y
+CONFIG_NAND_MXS_DT=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PMIC_RN5T567=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
--- /dev/null
+CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SECURE_BOOT=y
+CONFIG_TARGET_COLIBRI_IMX7=y
+CONFIG_TARGET_COLIBRI_IMX7_EMMC=y
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+# CONFIG_CMD_DEKBLOB is not set
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
+CONFIG_BOOTDELAY=1
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SYS_PROMPT="Colibri iMX7 # "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_HASH is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-emmc"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_FSL_CAAM=y
+CONFIG_DFU_MMC=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RN5T567=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Toradex"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_MX6LOGICPD=y
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
+CONFIG_SPL_FAT_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOUNCE_BUFFER=y
-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_TPL_BANNER_PRINT is not set
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)"
CONFIG_CMD_UBI=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_SPL_DM=y
CONFIG_PCF8575_GPIO=y
-CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_I2C=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_FSL_ESDHC=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_FAT_WRITE=y
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
CONFIG_NR_DRAM_BANKS=3
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg"
CONFIG_BOOTDELAY=3
+CONFIG_LOG=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
CONFIG_DM_GPIO=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
# CONFIG_EFI_LOADER is not set
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_DM_MMC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020"
CONFIG_ENV_IS_IN_MMC=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_PCL063=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_BOOTDELAY=3
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_CACHE=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_DEFAULT="gpmi-nand:4m(uboot),1m(env),-(root)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin"
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Phytec"
+CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DFU_MMC=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_OF_LIBFDT=y
CONFIG_OPTEE_TZDRAM_SIZE=0x2000000
+CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp"
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DFU_MMC=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_OPTEE=y
CONFIG_USB=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_OF_LIBFDT=y
CONFIG_OPTEE_LOAD_ADDR=0x84000000
CONFIG_OPTEE_TZDRAM_SIZE=0x3000000
CONFIG_OPTEE_TZDRAM_BASE=0x9d000000
CONFIG_BOOTM_OPTEE=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7s-warp"
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
Now, max 24 bits chips and PCA953X compatible chips are
supported
+config SPL_DM_PCA953X
+ bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports in SPL"
+ depends on DM_GPIO
+ help
+ Say yes here to provide access to several register-oriented
+ SMBus I/O expanders, made mostly by NXP or TI. Compatible
+ models include:
+
+ 4 bits: pca9536, pca9537
+
+ 8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554,
+ pca9556, pca9557, pca9574, tca6408, xra1202
+
+ 16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575,
+ tca6416
+
+ 24 bits: tca6424
+
+ 40 bits: pca9505, pca9698
+
+ Now, max 24 bits chips and PCA953X compatible chips are
+ supported
+
config MPC8XXX_GPIO
bool "Freescale MPC8XXX GPIO driver"
depends on DM_GPIO
endif
obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
-obj-$(CONFIG_DM_PCA953X) += pca953x_gpio.o
+obj-$(CONFIG_$(SPL_)DM_PCA953X) += pca953x_gpio.o
obj-$(CONFIG_DM_74X164) += 74x164_gpio.o
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
+#ifdef CONFIG_SPL_BUILD
+ plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL;
+#else
plat->base = (struct mu_type *)addr;
+#endif
/* U-Boot not enable interrupts, so need to enable RX interrupts */
mu_hal_init(plat->base);
};
static const struct udevice_id fsl_esdhc_ids[] = {
+ { .compatible = "fsl,imx53-esdhc", },
{ .compatible = "fsl,imx6ul-usdhc", },
{ .compatible = "fsl,imx6sx-usdhc", },
{ .compatible = "fsl,imx6sl-usdhc", },
mtd = nand_to_mtd(&nand_chip);
/* set mtd functions */
nand_chip.cmdfunc = mxs_nand_command;
+ nand_chip.scan_bbt = nand_default_bbt;
nand_chip.numchips = 1;
/* identify flash device */
.read_rom_hwaddr = fecmxc_read_rom_hwaddr,
};
+static int device_get_phy_addr(struct udevice *dev)
+{
+ struct ofnode_phandle_args phandle_args;
+ int reg;
+
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle_args)) {
+ debug("Failed to find phy-handle");
+ return -ENODEV;
+ }
+
+ reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+ return reg;
+}
+
static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
{
struct phy_device *phydev;
+ int addr;
int mask = 0xffffffff;
+ addr = device_get_phy_addr(dev);
+ if (addr >= 0)
+ mask = 1 << addr;
+
#ifdef CONFIG_FEC_MXC_PHYADDR
mask = 1 << CONFIG_FEC_MXC_PHYADDR;
#endif
const struct fdt_property *prop;
u32 *pin_data;
int npins, size, pin_size;
- int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val;
+ int mux_reg, conf_reg, input_reg;
+ u32 input_val, mux_mode, config_val;
u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
int i, j = 0;
u32 ts;
int status;
- debug("%s: bitlen %d dout 0x%x din 0x%x\n",
- __func__, bitlen, (u32)dout, (u32)din);
+ debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
+ __func__, bitlen, (ulong)dout, (ulong)din);
mxcs->ctrl_reg = (mxcs->ctrl_reg &
~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND)
-#define CONFIG_BOOTCOMMAND "run emmcboot ; echo ; echo emmcboot failed ; " \
+#define CONFIG_BOOTCOMMAND "run ubiboot ; echo ; echo ubiboot failed ; " \
"setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;"
#define MODULE_EXTRA_ENV_SETTINGS \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
UBI_BOOTCMD
#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC)
-#define CONFIG_BOOTCOMMAND "run ubiboot ; echo ; echo ubiboot failed ; " \
+#define CONFIG_BOOTCOMMAND "run emmcboot ; echo ; echo emmcboot failed ; " \
"setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb && run distro_bootcmd;"
#define MODULE_EXTRA_ENV_SETTINGS \
"variant=-emmc\0" \
NFS_BOOTCMD \
SD_BOOTCMD \
MODULE_EXTRA_ENV_SETTINGS \
+ "boot_file=zImage\0" \
"console=ttymxc0\0" \
"defargs=\0" \
"fdt_board=eval-v3\0" \
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_TEXT_BASE 0x0
+#define CONFIG_SPL_MAX_SIZE (124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x250
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
+
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x013E000
+#define CONFIG_SPL_BSS_START_ADDR 0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
+#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_MALLOC_F_ADDR 0x00120000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_OF_EMBED
+#endif
+
#define CONFIG_REMAKE_ELF
#define CONFIG_BOARD_EARLY_INIT_F
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"netdev=eth0\0" \
"splashsource=mmc_fs\0" \
- "splashfile=usplash.bmp.gz\0" \
+ "splashfile=boot/usplash.bmp.gz\0" \
"splashimage=0x88000000\0" \
"splashpos=m,m\0" \
"addcons=" \
"setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off\0" \
- "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=" \
"setenv bootargs ${bootargs} ${miscargs}\0" \
"addargs=run addcons addmisc addmtd\0" \
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on include/configs/xpress.h:
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ */
+#ifndef __PCL063_H
+#define __PCL063_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/*
+ * There is a bug in some i.MX6UL processors that results in the initial
+ * portion of OCRAM being unavailable when booting from (at least) an SD
+ * card.
+ *
+ * Tweak the SPL text base address to avoid this.
+ */
+#undef CONFIG_SPL_TEXT_BASE
+#define CONFIG_SPL_TEXT_BASE 0x00909000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
+
+/* Console configs */
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE SZ_256M
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_SIZE (16 << 10)
+#define CONFIG_ENV_OFFSET (512 << 10)
+
+/* NAND */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=ttymxc0,115200n8\0" \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ "fdt_addr_r=0x82000000\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "pxefile_addr_r=0x87100000\0" \
+ "ramdisk_addr_r=0x82100000\0" \
+ "scriptaddr=0x87000000\0" \
+ BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(UBIFS, ubifs, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#endif /* __PCL063_H */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
+ "splashpos=m,m\0" \
"console=ttymxc4\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \
BOOTMENU_ENV \
"fdt_addr=0x83000000\0" \
"fdt_addr_r=0x83000000\0" \
#define CONFIG_POWER_PFUZE3000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
/* FLASH and environment organization */
#define CONFIG_ENV_SIZE SZ_8K
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* I2C configs */
-#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_SPEED 100000
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE3000
-#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
-
/* environment organization */
#define CONFIG_ENV_SIZE SZ_8K
} else if (soc == QM && core == CORE_CA72) {
meta = IMAGE_A72_DEFAULT_META(custom_partition);
} else {
- fprintf(stderr, "Error: invalid AP core id: %lu\n",
+ fprintf(stderr,
+ "Error: invalid AP core id: %" PRIu64 "\n",
core);
exit(EXIT_FAILURE);
}
core = CORE_CM4_1;
meta = IMAGE_M4_1_DEFAULT_META(custom_partition);
} else {
- fprintf(stderr, "Error: invalid m4 core id: %lu\n", core);
+ fprintf(stderr,
+ "Error: invalid m4 core id: %" PRIu64 "\n",
+ core);
exit(EXIT_FAILURE);
}
img->hab_flags |= IMG_TYPE_EXEC;
fprintf(stdout, "CONTAINER SW VERSION:\t0x%04x\n", sw_version);
build_container(soc, sector_size, emmc_fastboot,
- img_sp, true, fuse_version, sw_version, outfd);
+ img_sp, false, fuse_version, sw_version, outfd);
return 0;
}
projects / oweals / u-boot.git / commitdiff