board/technexion/pico-imx7d/pico-imx7d.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 NXP Semiconductors
   4  */
   5
   6 #include <asm/arch/clock.h>
   7 #include <asm/arch/crm_regs.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/mx7-pins.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/gpio.h>
  12 #include <asm/mach-imx/iomux-v3.h>
  13 #include <asm/mach-imx/mxc_i2c.h>
  14 #include <asm/io.h>
  15 #include <common.h>
  16 #include <fsl_esdhc.h>
  17 #include <i2c.h>
  18 #include <miiphy.h>
  19 #include <mmc.h>
  20 #include <netdev.h>
  21 #include <usb.h>
  22 #include <power/pmic.h>
  23 #include <power/pfuze3000_pmic.h>
  24 #include "../../freescale/common/pfuze.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
  29         PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  30
  31 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  32         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  33
  34 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  35 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
  36
  37 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  38
  39 #define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  40         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  41
  42
  43 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  44                          PAD_CTL_DSE_3P3V_49OHM)
  45
  46 #define LCD_SYNC_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  47                               PAD_CTL_DSE_3P3V_196OHM)
  48
  49 #ifdef CONFIG_SYS_I2C_MXC
  50 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  51
  52 /* I2C4 for PMIC */
  53 static struct i2c_pads_info i2c_pad_info4 = {
  54         .scl = {
  55                 .i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
  56                 .gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
  57                 .gp = IMX_GPIO_NR(6, 16),
  58         },
  59         .sda = {
  60                 .i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
  61                 .gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
  62                 .gp = IMX_GPIO_NR(6, 17),
  63         },
  64 };
  65 #endif
  66
  67 int dram_init(void)
  68 {
  69         gd->ram_size = imx_ddr_size();
  70
  71         return 0;
  72 }
  73
  74 #ifdef CONFIG_POWER
  75 #define I2C_PMIC        3
  76 int power_init_board(void)
  77 {
  78         struct pmic *p;
  79         int ret;
  80         unsigned int reg, rev_id;
  81
  82         ret = power_pfuze3000_init(I2C_PMIC);
  83         if (ret)
  84                 return ret;
  85
  86         p = pmic_get("PFUZE3000");
  87         ret = pmic_probe(p);
  88         if (ret)
  89                 return ret;
  90
  91         pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
  92         pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
  93         printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  94
  95         /* disable Low Power Mode during standby mode */
  96         pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
  97         reg |= 0x1;
  98         pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
  99
 100         /* SW1A/1B mode set to APS/APS */
 101         reg = 0x8;
 102         pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
 103         pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
 104
 105         /* SW1A/1B standby voltage set to 1.025V */
 106         reg = 0xd;
 107         pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
 108         pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
 109
 110         /* decrease SW1B normal voltage to 0.975V */
 111         pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
 112         reg &= ~0x1f;
 113         reg |= PFUZE3000_SW1AB_SETP(975);
 114         pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
 115
 116         return 0;
 117 }
 118 #endif
 119
 120 static iomux_v3_cfg_t const wdog_pads[] = {
 121         MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 122 };
 123
 124 static iomux_v3_cfg_t const uart5_pads[] = {
 125         MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 126         MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 127 };
 128
 129 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
 130         MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141 };
 142
 143 #ifdef CONFIG_FEC_MXC
 144 static iomux_v3_cfg_t const fec1_pads[] = {
 145         MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 146         MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
 147         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 148         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 149         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 150         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 151         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 152         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 153         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 154         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 155         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 156         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 157         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 158         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 159         MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 160         MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 161 };
 162
 163 #define FEC1_RST_GPIO   IMX_GPIO_NR(6, 11)
 164
 165 static void setup_iomux_fec(void)
 166 {
 167         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 168
 169         gpio_direction_output(FEC1_RST_GPIO, 0);
 170         udelay(500);
 171         gpio_set_value(FEC1_RST_GPIO, 1);
 172 }
 173
 174 int board_eth_init(bd_t *bis)
 175 {
 176         setup_iomux_fec();
 177
 178         return fecmxc_initialize_multi(bis, 0,
 179                 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
 180 }
 181
 182 static int setup_fec(void)
 183 {
 184         struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
 185                 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 186
 187         /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
 188         clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
 189                         (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
 190                         IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
 191
 192         return set_clk_enet(ENET_125MHZ);
 193 }
 194
 195 int board_phy_config(struct phy_device *phydev)
 196 {
 197         unsigned short val;
 198
 199         /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
 200         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 201         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 202         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 203
 204         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 205         val &= 0xffe7;
 206         val |= 0x18;
 207         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 208
 209         /* introduce tx clock delay */
 210         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 211         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 212         val |= 0x0100;
 213         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 214
 215         if (phydev->drv->config)
 216                 phydev->drv->config(phydev);
 217
 218         return 0;
 219 }
 220 #endif
 221
 222 static void setup_iomux_uart(void)
 223 {
 224         imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
 225 }
 226
 227 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 228         {USDHC3_BASE_ADDR},
 229 };
 230
 231 int board_mmc_getcd(struct mmc *mmc)
 232 {
 233         /* Assume uSDHC3 emmc is always present */
 234         return 1;
 235 }
 236
 237 int board_mmc_init(bd_t *bis)
 238 {
 239         imx_iomux_v3_setup_multiple_pads(
 240                         usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
 241         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 242
 243         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 244 }
 245
 246 int board_early_init_f(void)
 247 {
 248         setup_iomux_uart();
 249
 250 #ifdef CONFIG_SYS_I2C_MXC
 251         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
 252 #endif
 253
 254         return 0;
 255 }
 256
 257 #ifdef CONFIG_VIDEO_MXS
 258 static iomux_v3_cfg_t const lcd_pads[] = {
 259         MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 260         MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
 261         MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
 262         MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_SYNC_PAD_CTRL),
 263         MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 264         MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 265         MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 266         MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 267         MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 268         MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 269         MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 270         MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 271         MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 272         MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 273         MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 274         MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 275         MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 276         MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 277         MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 278         MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 279         MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 280         MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 281         MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 282         MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 283         MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 284         MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 285         MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 286         MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 287         MX7D_PAD_GPIO1_IO06__GPIO1_IO6  | MUX_PAD_CTRL(LCD_PAD_CTRL),
 288         MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 289 };
 290
 291 void setup_lcd(void)
 292 {
 293         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 294         /* Set Brightness to high */
 295         gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
 296         /* Set LCD enable to high */
 297         gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
 298 }
 299 #endif
 300
 301 int board_init(void)
 302 {
 303         /* address of boot parameters */
 304         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 305
 306 #ifdef CONFIG_VIDEO_MXS
 307         setup_lcd();
 308 #endif
 309 #ifdef CONFIG_FEC_MXC
 310         setup_fec();
 311 #endif
 312
 313         return 0;
 314 }
 315
 316 int board_late_init(void)
 317 {
 318         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 319
 320         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 321
 322         set_wdog_reset(wdog);
 323
 324         /*
 325          * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
 326          * since we use PMIC_PWRON to reset the board.
 327          */
 328         clrsetbits_le16(&wdog->wcr, 0, 0x10);
 329
 330         return 0;
 331 }
 332
 333 int checkboard(void)
 334 {
 335         puts("Board: i.MX7D PICOSOM\n");
 336
 337         return 0;
 338 }
 339
 340 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 341         MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 342 };
 343
 344 int board_ehci_hcd_init(int port)
 345 {
 346         switch (port) {
 347         case 0:
 348                 break;
 349         case 1:
 350                 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
 351                                                  ARRAY_SIZE(usb_otg2_pads));
 352                 break;
 353         default:
 354                 return -EINVAL;
 355         }
 356         return 0;
 357 }
 358
 359 int board_usb_phy_mode(int port)
 360 {
 361         switch (port) {
 362         case 0:
 363                 return USB_INIT_DEVICE;
 364         case 1:
 365                 return USB_INIT_HOST;
 366         default:
 367                 return -EINVAL;
 368         }
 369         return 0;
 370 }