stw r0, 4(sp)
mov fp, sp
+#ifdef CONFIG_DEBUG_UART
+ /* Set up the debug UART */
+ movhi r2, %hi(debug_uart_init@h)
+ ori r2, r2, %lo(debug_uart_init@h)
+ callr r2
+#endif
+
/* Allocate and initialize reserved area, update SP */
mov r4, sp
movhi r2, %hi(board_init_f_alloc_reserve@h)
depends on X86_RESET_VECTOR
default 0xfffff800
-config DM_PCI_COMPAT
- default y # Until we finish moving over to the new API
-
config BOARD_ROMSIZE_KB_512
bool
config BOARD_ROMSIZE_KB_1024
DECLARE_GLOBAL_DATA_PTR;
-static struct irq_router irq_router;
static struct irq_routing_table *pirq_routing_table;
-bool pirq_check_irq_routed(int link, u8 irq)
+bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
{
+ struct irq_router *priv = dev_get_priv(dev);
u8 pirq;
- int base = irq_router.link_base;
+ int base = priv->link_base;
- if (irq_router.config == PIRQ_VIA_PCI)
- pirq = x86_pci_read_config8(irq_router.bdf,
- LINK_N2V(link, base));
+ if (priv->config == PIRQ_VIA_PCI)
+ dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
else
- pirq = readb(irq_router.ibase + LINK_N2V(link, base));
+ pirq = readb(priv->ibase + LINK_N2V(link, base));
pirq &= 0xf;
return pirq == irq ? true : false;
}
-int pirq_translate_link(int link)
+int pirq_translate_link(struct udevice *dev, int link)
{
- return LINK_V2N(link, irq_router.link_base);
+ struct irq_router *priv = dev_get_priv(dev);
+
+ return LINK_V2N(link, priv->link_base);
}
-void pirq_assign_irq(int link, u8 irq)
+void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
{
- int base = irq_router.link_base;
+ struct irq_router *priv = dev_get_priv(dev);
+ int base = priv->link_base;
/* IRQ# 0/1/2/8/13 are reserved */
if (irq < 3 || irq == 8 || irq == 13)
return;
- if (irq_router.config == PIRQ_VIA_PCI)
- x86_pci_write_config8(irq_router.bdf,
- LINK_N2V(link, base), irq);
+ if (priv->config == PIRQ_VIA_PCI)
+ dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
else
- writeb(irq, irq_router.ibase + LINK_N2V(link, base));
+ writeb(irq, priv->ibase + LINK_N2V(link, base));
}
static struct irq_info *check_dup_entry(struct irq_info *slot_base,
return (i == entry_num) ? NULL : slot;
}
-static inline void fill_irq_info(struct irq_info *slot, int bus, int device,
- int pin, int pirq)
+static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
+ int bus, int device, int pin, int pirq)
{
slot->bus = bus;
slot->devfn = (device << 3) | 0;
- slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base);
- slot->irq[pin - 1].bitmap = irq_router.irq_mask;
+ slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base);
+ slot->irq[pin - 1].bitmap = priv->irq_mask;
}
static int create_pirq_routing_table(struct udevice *dev)
{
+ struct irq_router *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- struct fdt_pci_addr addr;
int node;
int len, count;
const u32 *cell;
struct irq_routing_table *rt;
struct irq_info *slot, *slot_base;
int irq_entries = 0;
- int parent;
int i;
int ret;
node = dev->of_offset;
- parent = dev->parent->of_offset;
- ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
- "reg", &addr);
- if (ret)
- return ret;
/* extract the bdf from fdt_pci_addr */
- irq_router.bdf = addr.phys_hi & 0xffff00;
+ priv->bdf = dm_pci_get_bdf(dev->parent);
ret = fdt_find_string(blob, node, "intel,pirq-config", "pci");
if (!ret) {
- irq_router.config = PIRQ_VIA_PCI;
+ priv->config = PIRQ_VIA_PCI;
} else {
ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase");
if (!ret)
- irq_router.config = PIRQ_VIA_IBASE;
+ priv->config = PIRQ_VIA_IBASE;
else
return -EINVAL;
}
ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
if (ret == -1)
return ret;
- irq_router.link_base = ret;
+ priv->link_base = ret;
- irq_router.irq_mask = fdtdec_get_int(blob, node,
- "intel,pirq-mask", PIRQ_BITMAP);
+ priv->irq_mask = fdtdec_get_int(blob, node,
+ "intel,pirq-mask", PIRQ_BITMAP);
- if (irq_router.config == PIRQ_VIA_IBASE) {
+ if (priv->config == PIRQ_VIA_IBASE) {
int ibase_off;
ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
* 2) memory range decoding is enabled.
* Hence we don't do any santify test here.
*/
- irq_router.ibase = x86_pci_read_config32(irq_router.bdf,
- ibase_off);
- irq_router.ibase &= ~0xf;
+ dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
+ priv->ibase &= ~0xf;
}
cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
/* Populate the PIRQ table fields */
rt->signature = PIRQ_SIGNATURE;
rt->version = PIRQ_VERSION;
- rt->rtr_bus = PCI_BUS(irq_router.bdf);
- rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) |
- PCI_FUNC(irq_router.bdf);
+ rt->rtr_bus = PCI_BUS(priv->bdf);
+ rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
* routing information in the device tree.
*/
if (slot->irq[pr.pin - 1].link !=
- LINK_N2V(pr.pirq, irq_router.link_base))
+ LINK_N2V(pr.pirq, priv->link_base))
debug("WARNING: Inconsistent PIRQ routing information\n");
continue;
}
slot = slot_base + irq_entries++;
}
debug("writing INT%c\n", 'A' + pr.pin - 1);
- fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin,
- pr.pirq);
+ fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
+ pr.pin, pr.pirq);
}
rt->size = irq_entries * sizeof(struct irq_info) + 32;
return ret;
}
/* Route PIRQ */
- pirq_route_irqs(pirq_routing_table->slots,
+ pirq_route_irqs(dev, pirq_routing_table->slots,
get_irq_slot_count(pirq_routing_table));
return 0;
.id = UCLASS_IRQ,
.of_match = irq_router_ids,
.probe = irq_router_probe,
+ .priv_auto_alloc_size = sizeof(struct irq_router),
};
UCLASS_DRIVER(irq) = {
#include <asm/arch/pch.h>
#include <asm/arch/sandybridge.h>
+#define GPIO_BASE 0x48
#define BIOS_CTRL 0xdc
static int pch_revision_id = -1;
return 0;
}
-static int bd82x6x_pch_get_sbase(struct udevice *dev, ulong *sbasep)
+static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
{
u32 rcba;
return 0;
}
-static enum pch_version bd82x6x_pch_get_version(struct udevice *dev)
-{
- return PCHV_9;
-}
-
static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
{
uint8_t bios_cntl;
return 0;
}
+static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+ u32 base;
+
+ /*
+ * GPIO_BASE moved to its current offset with ICH6, but prior to
+ * that it was unused (or undocumented). Check that it looks
+ * okay: not all ones or zeros.
+ *
+ * Note we don't need check bit0 here, because the Tunnel Creek
+ * GPIO base address register bit0 is reserved (read returns 0),
+ * while on the Ivybridge the bit0 is used to indicate it is an
+ * I/O space.
+ */
+ dm_pci_read_config32(dev, GPIO_BASE, &base);
+ if (base == 0x00000000 || base == 0xffffffff) {
+ debug("%s: unexpected BASE value\n", __func__);
+ return -ENODEV;
+ }
+
+ /*
+ * Okay, I guess we're looking at the right device. The actual
+ * GPIO registers are in the PCI device's I/O space, starting
+ * at the offset that we just read. Bit 0 indicates that it's
+ * an I/O address, not a memory address, so mask that off.
+ */
+ *gbasep = base & 1 ? base & ~3 : base & ~15;
+
+ return 0;
+}
+
static const struct pch_ops bd82x6x_pch_ops = {
- .get_sbase = bd82x6x_pch_get_sbase,
- .get_version = bd82x6x_pch_get_version,
+ .get_spi_base = bd82x6x_pch_get_spi_base,
.set_spi_protect = bd82x6x_set_spi_protect,
+ .get_gpio_base = bd82x6x_get_gpio_base,
};
static const struct udevice_id bd82x6x_ids[] = {
DECLARE_GLOBAL_DATA_PTR;
-static struct pci_controller *get_hose(void)
-{
- if (gd->hose)
- return gd->hose;
-
- return pci_bus_to_hose(0);
-}
-
-unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
-{
- uint8_t value;
-
- if (pci_hose_read_config_byte(get_hose(), dev, where, &value))
- return -1U;
-
- return value;
-}
-
-unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
-{
- uint16_t value;
-
- if (pci_hose_read_config_word(get_hose(), dev, where, &value))
- return -1U;
-
- return value;
-}
-
-unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
-{
- uint32_t value;
-
- if (pci_hose_read_config_dword(get_hose(), dev, where, &value))
- return -1U;
-
- return value;
-}
-
-void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
-{
- pci_hose_write_config_byte(get_hose(), dev, where, value);
-}
-
-void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
-{
- pci_hose_write_config_word(get_hose(), dev, where, value);
-}
-
-void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
-{
- pci_hose_write_config_dword(get_hose(), dev, where, value);
-}
-
int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
ulong *valuep, enum pci_size_t size)
{
for (func = 0; func < 8; func++) {
bdf = PCI_BDF(bus, device, func);
- vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID);
+ pci_read_config16(bdf, PCI_VENDOR_ID, &vendor);
if (vendor == 0xffff || vendor == 0x0000)
continue;
- pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN);
+ pci_read_config8(bdf, PCI_INTERRUPT_PIN, &pin);
/* PCI spec says all values except 1..4 are reserved */
if ((pin < 1) || (pin > 4))
debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
line, bus, device, func, 'A' + pin - 1);
- x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
+ pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
}
}
*/
#include <common.h>
+#include <pci.h>
#include <asm/irq.h>
-#include <asm/pci.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/arch/device.h>
u16 cmd;
/* Set the PM I/O base */
- x86_pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
+ pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
/* Enable access to the PM I/O space */
- cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND);
+ pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_IO;
- x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
+ pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
/* PM I/O Space Enable (PMIOSE) */
- en = x86_pci_read_config8(PIIX_PM, PMREGMISC);
+ pci_read_config8(PIIX_PM, PMREGMISC, &en);
en |= PMIOSE;
- x86_pci_write_config8(PIIX_PM, PMREGMISC, en);
+ pci_write_config8(PIIX_PM, PMREGMISC, en);
}
static void enable_pm_ich9(void)
{
/* Set the PM I/O base */
- x86_pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
+ pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
}
static void qemu_chipset_init(void)
* the same bitfield layout. Here we determine the offset based on its
* PCI device ID.
*/
- device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
+ pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
pam = i440fx ? I440FX_PAM : Q35_PAM;
* Configure legacy segments C/D/E/F to system RAM
*/
for (i = 0; i < PAM_NUM; i++)
- x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
+ pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
if (i440fx) {
/*
* registers to see whether legacy ports decode is turned on.
* This is to make Linux ata_piix driver happy.
*/
- x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
- x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
+ pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
+ pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
/* Enable I/O APIC */
- xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
+ pci_read_config16(PIIX_ISA, XBCS, &xbcs);
xbcs |= APIC_EN;
- x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
+ pci_write_config16(PIIX_ISA, XBCS, xbcs);
enable_pm_piix();
} else {
/* Configure PCIe ECAM base address */
- x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
- CONFIG_PCIE_ECAM_BASE | BAR_EN);
+ pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
+ CONFIG_PCIE_ECAM_BASE | BAR_EN);
enable_pm_ich9();
}
* connected to I/O APIC INTPIN#16-19. Instead they are routed
* to an irq number controled by the PIRQ routing register.
*/
- irq = x86_pci_read_config8(PCI_BDF(bus, dev, func),
- PCI_INTERRUPT_LINE);
+ pci_read_config8(PCI_BDF(bus, dev, func),
+ PCI_INTERRUPT_LINE, &irq);
} else {
/*
* ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
#include <asm/arch/device.h>
#include <asm/arch/mrc.h>
#include <asm/arch/msg_port.h>
+#include <asm/arch/quark.h>
#include "mrc_util.h"
#include "hte.h"
#include "smc.h"
*/
void dram_init_command(uint32_t data)
{
- pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, data);
- pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, 0);
+ qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, data);
+ qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, 0);
msg_port_setup(MSG_OP_DRAM_INIT, MEM_CTLR, 0);
DPF(D_REGWR, "WR32 %03X %08X %08X\n", MEM_CTLR, 0, data);
{},
};
-/*
- * TODO:
- *
- * This whole routine should be removed until we fully convert the ICH SPI
- * driver to DM and make use of DT to pass the bios control register offset
- */
-static void unprotect_spi_flash(void)
-{
- u32 bc;
-
- qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc);
- bc |= 0x1; /* unprotect the flash */
- qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc);
-}
-
static void quark_setup_mtrr(void)
{
u32 base, mask;
/* Turn on legacy segments (A/B/E/F) decode to system RAM */
quark_enable_legacy_seg();
- unprotect_spi_flash();
-
return 0;
}
struct tnc_rcba *rcba;
u32 base;
- base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
+ dm_pci_read_config32(dev->parent, LPC_RCBA, &base);
base &= ~MEM_BAR_EN;
rcba = (struct tnc_rcba *)base;
*/
#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <pci.h>
#include <asm/io.h>
#include <asm/irq.h>
-#include <asm/pci.h>
#include <asm/post.h>
#include <asm/arch/device.h>
#include <asm/arch/tnc.h>
#include <asm/fsp/fsp_support.h>
#include <asm/processor.h>
-static void unprotect_spi_flash(void)
+static int __maybe_unused disable_igd(void)
{
- u32 bc;
+ struct udevice *igd, *sdvo;
+ int ret;
- bc = x86_pci_read_config32(TNC_LPC, 0xd8);
- bc |= 0x1; /* unprotect the flash */
- x86_pci_write_config32(TNC_LPC, 0xd8, bc);
-}
+ ret = dm_pci_bus_find_bdf(TNC_IGD, &igd);
+ if (ret)
+ return ret;
+ if (!igd)
+ return 0;
+
+ ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
+ if (ret)
+ return ret;
+ if (!sdvo)
+ return 0;
-static void __maybe_unused disable_igd(void)
-{
/*
* According to Atom E6xx datasheet, setting VGA Disable (bit17)
* of Graphics Controller register (offset 0x50) prevents IGD
* two devices will be completely disabled (invisible in the PCI
* configuration space) unless a system reset is performed.
*/
- x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE);
- x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE);
+ dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE);
+ dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
+
+ /*
+ * After setting the function disable bit, IGD and SDVO devices will
+ * disappear in the PCI configuration space. This however creates an
+ * inconsistent state from a driver model PCI controller point of view,
+ * as these two PCI devices are still attached to its parent's child
+ * device list as maintained by the driver model. Some driver model PCI
+ * APIs like dm_pci_find_class(), are referring to the list to speed up
+ * the finding process instead of re-enumerating the whole PCI bus, so
+ * it gets the stale cached data which is wrong.
+ *
+ * Note x86 PCI enueration normally happens twice, in pre-relocation
+ * phase and post-relocation. One option might be to call disable_igd()
+ * in one of the pre-relocation initialization hooks so that it gets
+ * disabled in the first round, and when it comes to the second round
+ * driver model PCI will construct a correct list. Unfortunately this
+ * does not work as Intel FSP is used on this platform to perform low
+ * level initialization, and fsp_init_phase_pci() is called only once
+ * in the post-relocation phase. If we disable IGD and SDVO devices,
+ * fsp_init_phase_pci() simply hangs and never returns.
+ *
+ * So the only option we have is to manually remove these two devices.
+ */
+ ret = device_remove(igd);
+ if (ret)
+ return ret;
+ ret = device_unbind(igd);
+ if (ret)
+ return ret;
+ ret = device_remove(sdvo);
+ if (ret)
+ return ret;
+ ret = device_unbind(sdvo);
+ if (ret)
+ return ret;
+
+ return 0;
}
int arch_cpu_init(void)
int arch_early_init_r(void)
{
+ int ret = 0;
+
#ifdef CONFIG_DISABLE_IGD
- disable_igd();
+ ret = disable_igd();
#endif
- return 0;
-}
-
-int arch_misc_init(void)
-{
- unprotect_spi_flash();
-
- return 0;
+ return ret;
}
};
};
- gpioa {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0 0x20>;
- bank-name = "A";
- };
-
- gpiob {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x20 0x20>;
- bank-name = "B";
- };
-
- gpioc {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x40 0x20>;
- bank-name = "C";
- };
-
- gpiod {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x60 0x20>;
- bank-name = "D";
- };
-
- gpioe {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x80 0x20>;
- bank-name = "E";
- };
-
- gpiof {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0xA0 0x20>;
- bank-name = "F";
- };
-
pci {
compatible = "pci-x86";
#address-cells = <3>;
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch9";
+ #address-cells = <1>;
+ #size-cells = <1>;
irq-router {
compatible = "intel,irq-router";
spi: spi {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "intel,ich-spi";
+ compatible = "intel,ich9-spi";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
};
};
};
+
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x20>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x20 0x20>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x40 0x20>;
+ bank-name = "C";
+ };
+
+ gpiod {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x60 0x20>;
+ bank-name = "D";
+ };
+
+ gpioe {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x80 0x20>;
+ bank-name = "E";
+ };
+
+ gpiof {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0xA0 0x20>;
+ bank-name = "F";
+ };
};
};
spi: spi {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "intel,ich-spi";
+ compatible = "intel,ich9-spi";
spi-flash@0 {
reg = <0>;
compatible = "winbond,w25q128", "spi-flash";
};
- gpioa {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0 0x10>;
- bank-name = "A";
- };
-
- gpiob {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x30 0x10>;
- bank-name = "B";
- };
-
- gpioc {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x40 0x10>;
- bank-name = "C";
- };
-
chosen {
stdout-path = "/serial";
};
spi: spi {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "intel,ich-spi";
+ compatible = "intel,ich9-spi";
spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
};
};
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x10>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x30 0x10>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x40 0x10>;
+ bank-name = "C";
+ };
+
lpc {
compatible = "intel,bd82x6x-lpc";
#address-cells = <1>;
no-keyboard;
};
- gpioa {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0 0x10>;
- bank-name = "A";
- };
-
- gpiob {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x30 0x10>;
- bank-name = "B";
- };
-
- gpioc {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x40 0x10>;
- bank-name = "C";
- };
-
chosen {
stdout-path = "/serial";
};
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch9";
+ #address-cells = <1>;
+ #size-cells = <1>;
spi: spi {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "intel,ich-spi";
+ compatible = "intel,ich9-spi";
spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
};
};
};
+
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x10>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x30 0x10>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x40 0x10>;
+ bank-name = "C";
+ };
};
};
};
- gpioa {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0 0x20>;
- bank-name = "A";
- };
-
- gpiob {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x20 0x20>;
- bank-name = "B";
- };
-
chosen {
/*
* By default the legacy superio serial port is used as the
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch7";
+ #address-cells = <1>;
+ #size-cells = <1>;
irq-router {
compatible = "intel,queensbay-irq-router";
spi: spi {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "intel,ich-spi";
+ compatible = "intel,ich7-spi";
spi-flash@0 {
reg = <0>;
compatible = "sst,25vf016b",
memory-map = <0xffe00000 0x00200000>;
};
};
+
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x20>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x20 0x20>;
+ bank-name = "B";
+ };
};
};
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch7";
+ #address-cells = <1>;
+ #size-cells = <1>;
irq-router {
compatible = "intel,quark-irq-router";
spi: spi {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "intel,ich-spi";
+ compatible = "intel,ich7-spi";
spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
};
};
};
- };
- };
- gpioa {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0 0x20>;
- bank-name = "A";
- };
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x20>;
+ bank-name = "A";
+ };
- gpiob {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x20 0x20>;
- bank-name = "B";
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x20 0x20>;
+ bank-name = "B";
+ };
+ };
};
};
pch_pinctrl {
compatible = "intel,x86-pinctrl";
- io-base = <0x4c>;
/* GPIO E0 */
soc_gpio_s5_0@0 {
};
};
- gpioa {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0 0x20>;
- bank-name = "A";
- };
-
- gpiob {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x20 0x20>;
- bank-name = "B";
- };
-
- gpioc {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x40 0x20>;
- bank-name = "C";
- };
-
- gpiod {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x60 0x20>;
- bank-name = "D";
- };
-
- gpioe {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0x80 0x20>;
- bank-name = "E";
- };
-
- gpiof {
- compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
- reg = <0xA0 0x20>;
- bank-name = "F";
- };
-
chosen {
stdout-path = "/serial";
};
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "pci8086,0f1c", "intel,pch9";
+ #address-cells = <1>;
+ #size-cells = <1>;
irq-router {
compatible = "intel,irq-router";
spi: spi {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "intel,ich-spi";
+ compatible = "intel,ich9-spi";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
};
};
};
+
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x20>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x20 0x20>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x40 0x20>;
+ bank-name = "C";
+ };
+
+ gpiod {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x60 0x20>;
+ bank-name = "D";
+ };
+
+ gpioe {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x80 0x20>;
+ bank-name = "E";
+ };
+
+ gpiof {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0xA0 0x20>;
+ bank-name = "F";
+ };
};
};
+++ /dev/null
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
-#endif /* _X86_ARCH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2014, Google Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
-#endif /* _X86_ARCH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2015 Google, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-#endif /* _X86_ARCH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2014, Google Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x48
-
-#endif /* _X86_ARCH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x44
-
-#endif /* _X86_ARCH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x44
-
-#endif /* _X86_ARCH_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _X86_ARCH_GPIO_H_
-#define _X86_ARCH_GPIO_H_
-
-/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x44
-
-#endif /* _X86_ARCH_GPIO_H_ */
#define _X86_GPIO_H_
#include <linux/compiler.h>
-#include <asm/arch/gpio.h>
#include <asm-generic/gpio.h>
struct ich6_bank_platdata {
#ifndef __ASSEMBLY__
-#define DEFINE_PCI_DEVICE_TABLE(_table) \
- const struct pci_device_id _table[]
-
-struct pci_controller;
-
-void pci_setup_type1(struct pci_controller *hose);
-
-/*
- * Simple PCI access routines - these work from either the early PCI hose
- * or the 'real' one, created after U-Boot has memory available
- */
-unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where);
-unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where);
-unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where);
-
-void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
-void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
-void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
-
int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
ulong *valuep, enum pci_size_t size);
* Note: this function should be provided by the platform codes, as the
* implementation of interrupt router may be different.
*
+ * @dev: irq router's udevice
* @link: link number which represents a PIRQ
* @irq: the 8259 IRQ number
* @return: true if the irq is already routed to 8259 for a given link,
* false elsewise
*/
-bool pirq_check_irq_routed(int link, u8 irq);
+bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq);
/**
* pirq_translate_link() - Translate a link value
* Note: this function should be provided by the platform codes, as the
* implementation of interrupt router may be different.
*
+ * @dev: irq router's udevice
* @link: platform-specific link value
* @return: link number which represents a PIRQ
*/
-int pirq_translate_link(int link);
+int pirq_translate_link(struct udevice *dev, int link);
/**
* pirq_assign_irq() - Assign an IRQ to a PIRQ link
* Note: this function should be provided by the platform codes, as the
* implementation of interrupt router may be different.
*
+ * @dev: irq router's udevice
* @link: link number which represents a PIRQ
* @irq: IRQ to which the PIRQ is routed
*/
-void pirq_assign_irq(int link, u8 irq);
+void pirq_assign_irq(struct udevice *dev, int link, u8 irq);
/**
* pirq_route_irqs() - Route PIRQs to 8259 PIC
* The configuration source is taken from a struct irq_info table, the format
* of which is defined in PIRQ routing table spec and PCI BIOS spec.
*
+ * @dev: irq router's udevice
* @irq: pointer to the base address of the struct irq_info
* @num: number of entries in the struct irq_info
*/
-void pirq_route_irqs(struct irq_info *irq, int num);
+void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num);
/**
* copy_pirq_routing_table() - Copy a PIRQ routing table
obj-y += northbridge-uclass.o
obj-$(CONFIG_I8259_PIC) += i8259.o
obj-$(CONFIG_I8254_TIMER) += i8254.o
-ifndef CONFIG_DM_PCI
-obj-$(CONFIG_PCI) += pci_type1.o
-endif
obj-y += pirq_routing.o
obj-y += relocate.o
obj-y += physmem.o
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Support for type PCI configuration cycles.
- * based on pci_indirect.c
- */
-#include <common.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <asm/pci.h>
-
-#define cfg_read(val, addr, op) (*val = op((int)(addr)))
-#define cfg_write(val, addr, op) op((val), (int)(addr))
-
-#define TYPE1_PCI_OP(rw, size, type, op, mask) \
-static int \
-type1_##rw##_config_##size(struct pci_controller *hose, \
- pci_dev_t dev, int offset, type val) \
-{ \
- outl(dev | (offset & 0xfc) | PCI_CFG_EN, (int)hose->cfg_addr); \
- cfg_##rw(val, hose->cfg_data + (offset & mask), op); \
- return 0; \
-}
-
-TYPE1_PCI_OP(read, byte, u8 *, inb, 3)
-TYPE1_PCI_OP(read, word, u16 *, inw, 2)
-TYPE1_PCI_OP(read, dword, u32 *, inl, 0)
-
-TYPE1_PCI_OP(write, byte, u8, outb, 3)
-TYPE1_PCI_OP(write, word, u16, outw, 2)
-TYPE1_PCI_OP(write, dword, u32, outl, 0)
-
-void pci_setup_type1(struct pci_controller *hose)
-{
- pci_set_ops(hose,
- type1_read_config_byte,
- type1_read_config_word,
- type1_read_config_dword,
- type1_write_config_byte,
- type1_write_config_word,
- type1_write_config_dword);
-
- hose->cfg_addr = (unsigned int *)PCI_REG_ADDR;
- hose->cfg_data = (unsigned char *)PCI_REG_DATA;
-}
static bool irq_already_routed[16];
-static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap)
+static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap)
{
int i, link;
u8 irq = 0;
continue;
for (link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) {
- if (pirq_check_irq_routed(link, irq)) {
+ if (pirq_check_irq_routed(dev, link, irq)) {
irq_already_routed[irq] = true;
break;
}
return irq;
}
-void pirq_route_irqs(struct irq_info *irq, int num)
+void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num)
{
unsigned char irq_slot[MAX_INTX_ENTRIES];
unsigned char pirq[CONFIG_MAX_PIRQ_LINKS];
}
/* translate link value to link number */
- link = pirq_translate_link(link);
+ link = pirq_translate_link(dev, link);
/* yet not routed */
if (!pirq[link]) {
- irq = pirq_get_next_free_irq(pirq, bitmap);
+ irq = pirq_get_next_free_irq(dev, pirq, bitmap);
pirq[link] = irq;
} else {
irq = pirq[link];
irq_slot[intx] = irq;
/* Assign IRQ in the interrupt router */
- pirq_assign_irq(link, irq);
+ pirq_assign_irq(dev, link, irq);
}
/* Bus, device, slots IRQs for {A,B,C,D} */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/device.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/quark.h>
int board_early_init_f(void)
u32 base, port, val;
/* retrieve the GPIO IO base */
- qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, PCI_CFG_GPIOBASE, &base);
+ qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
base = (base & 0xffff) & ~0x7f;
/* enable the pin */
u32 base, port, val;
/* retrieve the GPIO IO base */
- qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, PCI_CFG_GPIOBASE, &base);
+ qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
base = (base & 0xffff) & ~0x7f;
/* pull it up (de-assert) */
static void process_fdt_options(const void *blob)
{
-#if defined(CONFIG_OF_CONTROL)
+#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_SYS_TEXT_BASE)
ulong addr;
/* Add an env variable to point to a kernel payload, if available */
addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0);
if (addr)
setenv_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr));
-#endif /* CONFIG_OF_CONTROL */
+#endif /* CONFIG_OF_CONTROL && CONFIG_SYS_TEXT_BASE */
}
const char *bootdelay_process(void)
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="efi"
CONFIG_TARGET_EFI=y
# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_IMLS is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NET is not set
CONFIG_OF_CONTROL=y
CONFIG_DEBUG_UART_BASE=0
CONFIG_DEBUG_UART_CLOCK=0
CONFIG_ICH_SPI=y
-# CONFIG_X86_SERIAL is not set
CONFIG_TIMER=y
CONFIG_EFI=y
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
+#include <pch.h>
#include <pci.h>
#include <asm/gpio.h>
#include <asm/io.h>
gd->arch.gpio_map = map;
}
-static int gpio_ich6_get_base(unsigned long base)
-{
- pci_dev_t pci_dev; /* handle for 0:1f:0 */
- u8 tmpbyte;
- u16 tmpword;
- u32 tmplong;
-
- /* Where should it be? */
- pci_dev = PCI_BDF(0, 0x1f, 0);
-
- /* Is the device present? */
- tmpword = x86_pci_read_config16(pci_dev, PCI_VENDOR_ID);
- if (tmpword != PCI_VENDOR_ID_INTEL) {
- debug("%s: wrong VendorID %x\n", __func__, tmpword);
- return -ENODEV;
- }
-
- tmpword = x86_pci_read_config16(pci_dev, PCI_DEVICE_ID);
- debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
- /*
- * We'd like to validate the Device ID too, but pretty much any
- * value is either a) correct with slight differences, or b)
- * correct but undocumented. We'll have to check a bunch of other
- * things instead...
- */
-
- /* I/O should already be enabled (it's a RO bit). */
- tmpword = x86_pci_read_config16(pci_dev, PCI_COMMAND);
- if (!(tmpword & PCI_COMMAND_IO)) {
- debug("%s: device IO not enabled\n", __func__);
- return -ENODEV;
- }
-
- /* Header Type must be normal (bits 6-0 only; see spec.) */
- tmpbyte = x86_pci_read_config8(pci_dev, PCI_HEADER_TYPE);
- if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
- debug("%s: invalid Header type\n", __func__);
- return -ENODEV;
- }
-
- /* Base Class must be a bridge device */
- tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_CODE);
- if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
- debug("%s: invalid class\n", __func__);
- return -ENODEV;
- }
- /* Sub Class must be ISA */
- tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE);
- if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
- debug("%s: invalid subclass\n", __func__);
- return -ENODEV;
- }
-
- /* Programming Interface must be 0x00 (no others exist) */
- tmpbyte = x86_pci_read_config8(pci_dev, PCI_CLASS_PROG);
- if (tmpbyte != 0x00) {
- debug("%s: invalid interface type\n", __func__);
- return -ENODEV;
- }
-
- /*
- * GPIOBASE moved to its current offset with ICH6, but prior to
- * that it was unused (or undocumented). Check that it looks
- * okay: not all ones or zeros.
- *
- * Note we don't need check bit0 here, because the Tunnel Creek
- * GPIO base address register bit0 is reserved (read returns 0),
- * while on the Ivybridge the bit0 is used to indicate it is an
- * I/O space.
- */
- tmplong = x86_pci_read_config32(pci_dev, base);
- if (tmplong == 0x00000000 || tmplong == 0xffffffff) {
- debug("%s: unexpected BASE value\n", __func__);
- return -ENODEV;
- }
-
- /*
- * Okay, I guess we're looking at the right device. The actual
- * GPIO registers are in the PCI device's I/O space, starting
- * at the offset that we just read. Bit 0 indicates that it's
- * an I/O address, not a memory address, so mask that off.
- */
- return tmplong & 1 ? tmplong & ~3 : tmplong & ~15;
-}
-
static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
{
u32 val;
int gpio_ich6_pinctrl_init(void)
{
+ struct udevice *pch;
int pin_node;
int node;
int ret;
- int gpiobase;
- int iobase_offset;
- int iobase = -1;
+ u32 gpiobase;
+ u32 iobase = -1;
+
+ ret = uclass_first_device(UCLASS_PCH, &pch);
+ if (ret)
+ return ret;
+ if (!pch)
+ return -ENODEV;
/*
* Get the memory/io base address to configure every pins.
* IOBASE is used to configure the mode/pads
* GPIOBASE is used to configure the direction and default value
*/
- gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE);
- if (gpiobase < 0) {
+ ret = pch_get_gpio_base(pch, &gpiobase);
+ if (ret) {
debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
gpiobase);
return -EINVAL;
* Get the IOBASE, this is not mandatory as this is not
* supported by all the CPU
*/
- iobase_offset = fdtdec_get_int(gd->fdt_blob, node, "io-base", -1);
- if (iobase_offset == -1) {
- debug("%s: io-base offset not present\n", __func__);
- } else {
- iobase = gpio_ich6_get_base(iobase_offset);
- if (IS_ERR_VALUE(iobase)) {
- debug("%s: invalid IOBASE address (%08x)\n", __func__,
- iobase);
- return -EINVAL;
- }
+ ret = pch_get_io_base(pch, &iobase);
+ if (ret && ret != -ENOSYS) {
+ debug("%s: invalid IOBASE address (%08x)\n", __func__,
+ iobase);
+ return -EINVAL;
}
for (pin_node = fdt_first_subnode(gd->fdt_blob, node);
static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
{
struct ich6_bank_platdata *plat = dev_get_platdata(dev);
- u16 gpiobase;
+ u32 gpiobase;
int offset;
+ int ret;
+
+ ret = pch_get_gpio_base(dev->parent, &gpiobase);
+ if (ret)
+ return ret;
- gpiobase = gpio_ich6_get_base(PCI_CFG_GPIOBASE);
offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
if (offset == -1) {
debug("%s: Invalid register offset %d\n", __func__, offset);
* or via a PCI bridge, fill in platdata before we probe the hardware.
*/
if (device_is_on_pci_bus(dev)) {
- pci_dev_t bdf = dm_pci_get_bdf(dev);
-
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
- iobase = pci_mem_to_phys(bdf, iobase);
+ iobase = dm_pci_mem_to_phys(dev, iobase);
pdata->iobase = iobase;
pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
#define TOUT_LOOP 100000
+#ifdef CONFIG_DM_ETH
+#define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
+#define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a)
+#else
#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
+#endif
#define E1000_DEFAULT_PCI_PBA 0x00000030
#define E1000_DEFAULT_PCIE_PBA 0x000a0026
/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
if (hw->mac_type == e1000_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+#ifdef CONFIG_DM_ETH
+ dm_pci_write_config16(hw->pdev, PCI_COMMAND,
+ hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
+#else
pci_write_config_word(hw->pdev, PCI_COMMAND,
hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
+#endif
}
/* Clear interrupt mask to stop board from generating interrupts */
/* If MWI was previously enabled, reenable it. */
if (hw->mac_type == e1000_82542_rev2_0) {
+#ifdef CONFIG_DM_ETH
+ dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
+#else
pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
+#endif
}
if (hw->mac_type != e1000_igb)
E1000_WRITE_REG(hw, PBA, pba);
/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
if (hw->mac_type == e1000_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+#ifdef CONFIG_DM_ETH
+ dm_pci_write_config16(hw->pdev, PCI_COMMAND,
+ hw->
+ pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
+#else
pci_write_config_word(hw->pdev, PCI_COMMAND,
hw->
pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
+#endif
E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
E1000_WRITE_FLUSH(hw);
mdelay(5);
E1000_WRITE_REG(hw, RCTL, 0);
E1000_WRITE_FLUSH(hw);
mdelay(1);
+#ifdef CONFIG_DM_ETH
+ dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
+#else
pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
+#endif
}
/* Zero out the Multicast HASH table */
default:
/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
if (hw->bus_type == e1000_bus_type_pcix) {
+#ifdef CONFIG_DM_ETH
+ dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
+ &pcix_cmd_word);
+ dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
+ &pcix_stat_hi_word);
+#else
pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
&pcix_cmd_word);
pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
&pcix_stat_hi_word);
+#endif
cmd_mmrbc =
(pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
PCIX_COMMAND_MMRBC_SHIFT;
if (cmd_mmrbc > stat_mmrbc) {
pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
+#ifdef CONFIG_DM_ETH
+ dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
+ pcix_cmd_word);
+#else
pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
pcix_cmd_word);
+#endif
}
}
break;
int result;
/* PCI config space info */
+#ifdef CONFIG_DM_ETH
+ dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
+ dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
+ dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
+ &hw->subsystem_vendor_id);
+ dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
+
+ dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
+ dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
+#else
pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
+#endif
/* identify the MAC */
result = e1000_set_mac_type(hw);
static LIST_HEAD(e1000_hw_list);
#endif
+#ifdef CONFIG_DM_ETH
+static int e1000_init_one(struct e1000_hw *hw, int cardnum,
+ struct udevice *devno, unsigned char enetaddr[6])
+#else
static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
unsigned char enetaddr[6])
+#endif
{
u32 val;
/* Assign the passed-in values */
+#ifdef CONFIG_DM_ETH
hw->pdev = devno;
+#else
+ hw->pdev = devno;
+#endif
hw->cardnum = cardnum;
/* Print a debug message with the IO base address */
+#ifdef CONFIG_DM_ETH
+ dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
+#else
pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
+#endif
E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
/* Try to enable I/O accesses and bus-mastering */
val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+#ifdef CONFIG_DM_ETH
+ dm_pci_write_config32(devno, PCI_COMMAND, val);
+#else
pci_write_config_dword(devno, PCI_COMMAND, val);
+#endif
/* Make sure it worked */
+#ifdef CONFIG_DM_ETH
+ dm_pci_read_config32(devno, PCI_COMMAND, &val);
+#else
pci_read_config_dword(devno, PCI_COMMAND, &val);
+#endif
if (!(val & PCI_COMMAND_MEMORY)) {
E1000_ERR(hw, "Can't enable I/O memory\n");
return -ENOSPC;
#ifndef CONFIG_E1000_NO_NVM
hw->eeprom_semaphore_present = true;
#endif
+#ifdef CONFIG_DM_ETH
+ hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0,
+ PCI_REGION_MEM);
+#else
hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM);
+#endif
hw->mac_type = e1000_undefined;
/* MAC and Phy settings */
hw->name = dev->name;
ret = e1000_init_one(hw, trailing_strtol(dev->name),
- dm_pci_get_bdf(dev), plat->enetaddr);
+ dev, plat->enetaddr);
if (ret < 0) {
printf(pr_fmt("failed to initialize card: %d\n"), ret);
return ret;
#endif
unsigned int cardnum;
+#ifdef CONFIG_DM_ETH
+ struct udevice *pdev;
+#else
pci_dev_t pdev;
+#endif
uint8_t *hw_addr;
e1000_mac_type mac_type;
e1000_phy_type phy_type;
memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
for (i = 0; i < PCH_GBE_DESC_NUM; i++)
- rx_desc->buffer_addr = pci_phys_to_mem(priv->bdf,
+ rx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev,
(u32)(priv->rx_buff[i]));
- writel(pci_phys_to_mem(priv->bdf, (u32)rx_desc),
+ writel(dm_pci_phys_to_mem(priv->dev, (u32)rx_desc),
&mac_regs->rx_dsc_base);
writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
&mac_regs->rx_dsc_size);
- writel(pci_phys_to_mem(priv->bdf, (u32)(rx_desc + 1)),
+ writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_desc + 1)),
&mac_regs->rx_dsc_sw_p);
}
memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
- writel(pci_phys_to_mem(priv->bdf, (u32)tx_desc),
+ writel(dm_pci_phys_to_mem(priv->dev, (u32)tx_desc),
&mac_regs->tx_dsc_base);
writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
&mac_regs->tx_dsc_size);
- writel(pci_phys_to_mem(priv->bdf, (u32)(tx_desc + 1)),
+ writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_desc + 1)),
&mac_regs->tx_dsc_sw_p);
}
if (length < 64)
frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
- tx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, (u32)packet);
+ tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (u32)packet);
tx_desc->length = length;
tx_desc->tx_words_eob = length + 3;
tx_desc->tx_frame_ctrl = frame_ctrl;
if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
priv->tx_idx = 0;
- writel(pci_phys_to_mem(priv->bdf, (u32)(tx_head + priv->tx_idx)),
+ writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_head + priv->tx_idx)),
&mac_regs->tx_dsc_sw_p);
start = get_timer(0);
if ((u32)rx_desc == hw_desc)
return -EAGAIN;
- buffer_addr = pci_mem_to_phys(priv->bdf, rx_desc->buffer_addr);
+ buffer_addr = dm_pci_mem_to_phys(priv->dev, rx_desc->buffer_addr);
*packetp = (uchar *)buffer_addr;
length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
if (++rx_swp >= PCH_GBE_DESC_NUM)
rx_swp = 0;
- writel(pci_phys_to_mem(priv->bdf, (u32)(rx_head + rx_swp)),
+ writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_head + rx_swp)),
&mac_regs->rx_dsc_sw_p);
return 0;
{
struct pch_gbe_priv *priv;
struct eth_pdata *plat = dev_get_platdata(dev);
- pci_dev_t devno;
u32 iobase;
- devno = dm_pci_get_bdf(dev);
-
/*
* The priv structure contains the descriptors and frame buffers which
* need a strict buswidth alignment (64 bytes). This is guaranteed by
*/
priv = dev_get_priv(dev);
- priv->bdf = devno;
+ priv->dev = dev;
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
+ dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
- iobase = pci_mem_to_phys(devno, iobase);
+ iobase = dm_pci_mem_to_phys(dev, iobase);
plat->iobase = iobase;
priv->mac_regs = (struct pch_gbe_regs *)iobase;
struct phy_device *phydev;
struct mii_dev *bus;
struct pch_gbe_regs *mac_regs;
- pci_dev_t bdf;
+ struct udevice *dev;
int rx_idx;
int tx_idx;
};
DECLARE_GLOBAL_DATA_PTR;
-int pch_get_sbase(struct udevice *dev, ulong *sbasep)
+int pch_get_spi_base(struct udevice *dev, ulong *sbasep)
{
struct pch_ops *ops = pch_get_ops(dev);
*sbasep = 0;
- if (!ops->get_sbase)
+ if (!ops->get_spi_base)
return -ENOSYS;
- return ops->get_sbase(dev, sbasep);
+ return ops->get_spi_base(dev, sbasep);
}
-enum pch_version pch_get_version(struct udevice *dev)
+int pch_set_spi_protect(struct udevice *dev, bool protect)
{
struct pch_ops *ops = pch_get_ops(dev);
- if (!ops->get_version)
+ if (!ops->set_spi_protect)
return -ENOSYS;
- return ops->get_version(dev);
+ return ops->set_spi_protect(dev, protect);
}
-int pch_set_spi_protect(struct udevice *dev, bool protect)
+int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
{
struct pch_ops *ops = pch_get_ops(dev);
- if (!ops->set_spi_protect)
+ *gbasep = 0;
+ if (!ops->get_gpio_base)
return -ENOSYS;
- return ops->set_spi_protect(dev, protect);
+ return ops->get_gpio_base(dev, gbasep);
+}
+
+int pch_get_io_base(struct udevice *dev, u32 *iobasep)
+{
+ struct pch_ops *ops = pch_get_ops(dev);
+
+ *iobasep = 0;
+ if (!ops->get_io_base)
+ return -ENOSYS;
+
+ return ops->get_io_base(dev, iobasep);
}
static int pch_uclass_post_bind(struct udevice *bus)
#include <dm.h>
#include <pch.h>
+#define GPIO_BASE 0x44
#define BIOS_CTRL 0xd8
-static int pch7_get_sbase(struct udevice *dev, ulong *sbasep)
+static int pch7_get_spi_base(struct udevice *dev, ulong *sbasep)
{
u32 rcba;
return 0;
}
-static enum pch_version pch7_get_version(struct udevice *dev)
-{
- return PCHV_7;
-}
-
static int pch7_set_spi_protect(struct udevice *dev, bool protect)
{
uint8_t bios_cntl;
return 0;
}
+static int pch7_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+ u32 base;
+
+ /*
+ * GPIO_BASE moved to its current offset with ICH6, but prior to
+ * that it was unused (or undocumented). Check that it looks
+ * okay: not all ones or zeros.
+ *
+ * Note we don't need check bit0 here, because the Tunnel Creek
+ * GPIO base address register bit0 is reserved (read returns 0),
+ * while on the Ivybridge the bit0 is used to indicate it is an
+ * I/O space.
+ */
+ dm_pci_read_config32(dev, GPIO_BASE, &base);
+ if (base == 0x00000000 || base == 0xffffffff) {
+ debug("%s: unexpected BASE value\n", __func__);
+ return -ENODEV;
+ }
+
+ /*
+ * Okay, I guess we're looking at the right device. The actual
+ * GPIO registers are in the PCI device's I/O space, starting
+ * at the offset that we just read. Bit 0 indicates that it's
+ * an I/O address, not a memory address, so mask that off.
+ */
+ *gbasep = base & 1 ? base & ~3 : base & ~15;
+
+ return 0;
+}
+
static const struct pch_ops pch7_ops = {
- .get_sbase = pch7_get_sbase,
- .get_version = pch7_get_version,
+ .get_spi_base = pch7_get_spi_base,
.set_spi_protect = pch7_set_spi_protect,
+ .get_gpio_base = pch7_get_gpio_base,
};
static const struct udevice_id pch7_ids[] = {
#include <dm.h>
#include <pch.h>
+#define GPIO_BASE 0x48
+#define IO_BASE 0x4c
#define SBASE_ADDR 0x54
-static int pch9_get_sbase(struct udevice *dev, ulong *sbasep)
+static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
{
uint32_t sbase_addr;
return 0;
}
-static enum pch_version pch9_get_version(struct udevice *dev)
+static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
{
- return PCHV_9;
+ u32 base;
+
+ /*
+ * GPIO_BASE moved to its current offset with ICH6, but prior to
+ * that it was unused (or undocumented). Check that it looks
+ * okay: not all ones or zeros.
+ *
+ * Note we don't need check bit0 here, because the Tunnel Creek
+ * GPIO base address register bit0 is reserved (read returns 0),
+ * while on the Ivybridge the bit0 is used to indicate it is an
+ * I/O space.
+ */
+ dm_pci_read_config32(dev, GPIO_BASE, &base);
+ if (base == 0x00000000 || base == 0xffffffff) {
+ debug("%s: unexpected BASE value\n", __func__);
+ return -ENODEV;
+ }
+
+ /*
+ * Okay, I guess we're looking at the right device. The actual
+ * GPIO registers are in the PCI device's I/O space, starting
+ * at the offset that we just read. Bit 0 indicates that it's
+ * an I/O address, not a memory address, so mask that off.
+ */
+ *gbasep = base & 1 ? base & ~3 : base & ~15;
+
+ return 0;
+}
+
+static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
+{
+ u32 base;
+
+ dm_pci_read_config32(dev, IO_BASE, &base);
+ if (base == 0x00000000 || base == 0xffffffff) {
+ debug("%s: unexpected BASE value\n", __func__);
+ return -ENODEV;
+ }
+
+ *iobasep = base & 1 ? base & ~3 : base & ~15;
+
+ return 0;
}
static const struct pch_ops pch9_ops = {
- .get_sbase = pch9_get_sbase,
- .get_version = pch9_get_version,
+ .get_spi_base = pch9_get_spi_base,
+ .get_gpio_base = pch9_get_gpio_base,
+ .get_io_base = pch9_get_io_base,
};
static const struct udevice_id pch9_ids[] = {
*
* This file is derived from the flashrom project.
*/
+
#include <common.h>
#include <dm.h>
#include <errno.h>
#include "ich.h"
-#define SPI_OPCODE_WREN 0x06
-#define SPI_OPCODE_FAST_READ 0x0b
+DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG_TRACE
#define debug_trace(fmt, args...) debug(fmt, ##args)
#define debug_trace(x, args...)
#endif
-struct ich_spi_platdata {
- enum pch_version ich_version; /* Controller version, 7 or 9 */
-};
-
-struct ich_spi_priv {
- int ichspi_lock;
- int locked;
- int opmenu;
- int menubytes;
- void *base; /* Base of register set */
- int preop;
- int optype;
- int addr;
- int data;
- unsigned databytes;
- int status;
- int control;
- int bbar;
- int bcr;
- uint32_t *pr; /* only for ich9 */
- int speed; /* pointer to speed control */
- ulong max_speed; /* Maximum bus speed in MHz */
- ulong cur_speed; /* Current bus speed */
- struct spi_trans trans; /* current transaction in progress */
-};
-
static u8 ich_readb(struct ich_spi_priv *priv, int reg)
{
u8 value = readb(priv->base + reg);
void *sbase;
/* SBASE is similar */
- pch_get_sbase(dev->parent, &sbase_addr);
+ pch_get_spi_base(dev->parent, &sbase_addr);
sbase = (void *)sbase_addr;
debug("%s: sbase=%p\n", __func__, sbase);
- if (plat->ich_version == PCHV_7) {
+ if (plat->ich_version == ICHV_7) {
struct ich7_spi_regs *ich7_spi = sbase;
ich7_spi = (struct ich7_spi_regs *)sbase;
ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
ctlr->preop = offsetof(struct ich7_spi_regs, preop);
ctlr->base = ich7_spi;
- } else if (plat->ich_version == PCHV_9) {
+ } else if (plat->ich_version == ICHV_9) {
struct ich9_spi_regs *ich9_spi = sbase;
ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
/* Work out the maximum speed we can support */
ctlr->max_speed = 20000000;
- if (plat->ich_version == PCHV_9 && ich9_can_do_33mhz(dev))
+ if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
ctlr->max_speed = 33000000;
debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
plat->ich_version, ctlr->base, ctlr->max_speed);
{
trans->type = 0xFF;
- /* Try to guess spi type from read/write sizes. */
+ /* Try to guess spi type from read/write sizes */
if (trans->bytesin == 0) {
if (trans->bytesout + data_bytes > 4)
/*
static int spi_setup_offset(struct spi_trans *trans)
{
- /* Separate the SPI address and data. */
+ /* Separate the SPI address and data */
switch (trans->type) {
case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
trans->in = din;
trans->bytesin = din ? bytes : 0;
- /* There has to always at least be an opcode. */
+ /* There has to always at least be an opcode */
if (!trans->bytesout) {
debug("ICH SPI: No opcode for transfer\n");
return -EPROTO;
if (ret < 0)
return ret;
- if (plat->ich_version == PCHV_7)
+ if (plat->ich_version == ICHV_7)
ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
else
ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
/* write it */
ich_writew(ctlr, control, ctlr->control);
- /* Wait for Cycle Done Status or Flash Cycle Error. */
+ /* Wait for Cycle Done Status or Flash Cycle Error */
status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
if (status < 0)
return status;
uint8_t bios_cntl;
int ret;
- /* Check the ICH version */
- plat->ich_version = pch_get_version(dev->parent);
-
ret = ich_init_controller(dev, plat, priv);
if (ret)
return ret;
* ICH 7 SPI controller only supports array read command
* and byte program command for SST flash
*/
- if (plat->ich_version == PCHV_7) {
+ if (plat->ich_version == ICHV_7) {
slave->mode_rx = SPI_RX_SLOW;
slave->mode = SPI_TX_BYTE;
}
return 0;
}
+static int ich_spi_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
+ "intel,ich7-spi");
+ if (ret == 0) {
+ plat->ich_version = ICHV_7;
+ } else {
+ ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
+ "intel,ich9-spi");
+ if (ret == 0)
+ plat->ich_version = ICHV_9;
+ }
+
+ return ret;
+}
+
static const struct dm_spi_ops ich_spi_ops = {
.xfer = ich_spi_xfer,
.set_speed = ich_spi_set_speed,
};
static const struct udevice_id ich_spi_ids[] = {
- { .compatible = "intel,ich-spi" },
+ { .compatible = "intel,ich7-spi" },
+ { .compatible = "intel,ich9-spi" },
{ }
};
.id = UCLASS_SPI,
.of_match = ich_spi_ids,
.ops = &ich_spi_ops,
+ .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
.priv_auto_alloc_size = sizeof(struct ich_spi_priv),
.child_pre_probe = ich_spi_child_pre_probe,
* This file is derived from the flashrom project.
*/
+#ifndef _ICH_H_
+#define _ICH_H_
+
struct ich7_spi_regs {
uint16_t spis;
uint16_t spic;
} __packed;
struct ich9_spi_regs {
- uint32_t bfpr; /* 0x00 */
+ uint32_t bfpr; /* 0x00 */
uint16_t hsfs;
uint16_t hsfc;
uint32_t faddr;
uint32_t _reserved0;
- uint32_t fdata[16]; /* 0x10 */
- uint32_t frap; /* 0x50 */
+ uint32_t fdata[16]; /* 0x10 */
+ uint32_t frap; /* 0x50 */
uint32_t freg[5];
uint32_t _reserved1[3];
- uint32_t pr[5]; /* 0x74 */
+ uint32_t pr[5]; /* 0x74 */
uint32_t _reserved2[2];
- uint8_t ssfs; /* 0x90 */
+ uint8_t ssfs; /* 0x90 */
uint8_t ssfc[3];
- uint16_t preop; /* 0x94 */
+ uint16_t preop; /* 0x94 */
uint16_t optype;
- uint8_t opmenu[8]; /* 0x98 */
+ uint8_t opmenu[8]; /* 0x98 */
uint32_t bbar;
uint8_t _reserved3[12];
- uint32_t fdoc; /* 0xb0 */
+ uint32_t fdoc; /* 0xb0 */
uint32_t fdod;
uint8_t _reserved4[8];
- uint32_t afc; /* 0xc0 */
+ uint32_t afc; /* 0xc0 */
uint32_t lvscc;
uint32_t uvscc;
uint8_t _reserved5[4];
- uint32_t fpb; /* 0xd0 */
+ uint32_t fpb; /* 0xd0 */
uint8_t _reserved6[28];
- uint32_t srdl; /* 0xf0 */
+ uint32_t srdl; /* 0xf0 */
uint32_t srdc;
uint32_t scs;
uint32_t bcr;
uint32_t offset;
};
-struct ich_spi_slave {
- struct spi_slave slave;
+#define SPI_OPCODE_WREN 0x06
+#define SPI_OPCODE_FAST_READ 0x0b
+
+enum ich_version {
+ ICHV_7,
+ ICHV_9,
+};
+
+struct ich_spi_platdata {
+ enum ich_version ich_version; /* Controller version, 7 or 9 */
+};
+
+struct ich_spi_priv {
+ int ichspi_lock;
+ int locked;
+ int opmenu;
+ int menubytes;
+ void *base; /* Base of register set */
+ int preop;
+ int optype;
+ int addr;
+ int data;
+ unsigned databytes;
+ int status;
+ int control;
+ int bbar;
+ int bcr;
+ uint32_t *pr; /* only for ich9 */
+ int speed; /* pointer to speed control */
+ ulong max_speed; /* Maximum bus speed in MHz */
+ ulong cur_speed; /* Current bus speed */
struct spi_trans trans; /* current transaction in progress */
- int speed; /* SPI speed in Hz */
};
+
+#endif /* _ICH_H_ */
#include <configs/x86-chromebook.h>
#define CONFIG_RTL8169
-/* Avoid a warning in the Realtek Ethernet driver */
-#define CONFIG_SYS_CACHELINE_SIZE 16
#endif /* __CONFIG_H */
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_EARLY_INIT_R
-#define CONFIG_ARCH_MISC_INIT
#define CONFIG_SMSC_LPC47M
#undef CONFIG_TPM_TIS_BASE_ADDRESS
-#undef CONFIG_CMD_IMLS
-
-#undef CONFIG_X86_SERIAL
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_NOWHERE
#undef CONFIG_VIDEO
#undef CONFIG_SCSI_AHCI
#undef CONFIG_CMD_SCSI
#undef CONFIG_INTEL_ICH6_GPIO
+#undef CONFIG_USB_EHCI_PCI
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \
"tftpboot $loadaddr $bootfile;" \
"zboot $loadaddr"
+#define CONFIG_BOOTDELAY 2
+
#endif /* __CONFIG_H */
#ifndef __pch_h
#define __pch_h
-enum pch_version {
- PCHV_UNKNOWN,
- PCHV_7,
- PCHV_9,
-};
-
#define PCH_RCBA 0xf0
#define BIOS_CTRL_BIOSWE BIT(0)
/* Operations for the Platform Controller Hub */
struct pch_ops {
/**
- * get_sbase() - get the address of SPI base
+ * get_spi_base() - get the address of SPI base
*
* @dev: PCH device to check
* @sbasep: Returns address of SPI base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no SPI base)
*/
- int (*get_sbase)(struct udevice *dev, ulong *sbasep);
-
- /**
- * get_version() - get the PCH version
- *
- * @return version, or -ENOSYS if unknown
- */
- enum pch_version (*get_version)(struct udevice *dev);
+ int (*get_spi_base)(struct udevice *dev, ulong *sbasep);
/**
* set_spi_protect() - set whether SPI flash is protected or not
* @return 0 on success, -ENOSYS if not implemented
*/
int (*set_spi_protect)(struct udevice *dev, bool protect);
+
+ /**
+ * get_gpio_base() - get the address of GPIO base
+ *
+ * @dev: PCH device to check
+ * @gbasep: Returns address of GPIO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
+ */
+ int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
+
+ /**
+ * get_io_base() - get the address of IO base
+ *
+ * @dev: PCH device to check
+ * @iobasep: Returns address of IO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no IO base)
+ */
+ int (*get_io_base)(struct udevice *dev, u32 *iobasep);
};
#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
/**
- * pch_get_sbase() - get the address of SPI base
+ * pch_get_spi_base() - get the address of SPI base
*
* @dev: PCH device to check
* @sbasep: Returns address of SPI base if available, else 0
* @return 0 if OK, -ve on error (e.g. there is no SPI base)
*/
-int pch_get_sbase(struct udevice *dev, ulong *sbasep);
-
-/**
- * pch_get_version() - get the PCH version
- *
- * @return version, or -ENOSYS if unknown
- */
-enum pch_version pch_get_version(struct udevice *dev);
+int pch_get_spi_base(struct udevice *dev, ulong *sbasep);
/**
* set_spi_protect() - set whether SPI flash is protected or not
*/
int pch_set_spi_protect(struct udevice *dev, bool protect);
+/**
+ * pch_get_gpio_base() - get the address of GPIO base
+ *
+ * @dev: PCH device to check
+ * @gbasep: Returns address of GPIO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
+ */
+int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
+
+/**
+ * pch_get_io_base() - get the address of IO base
+ *
+ * @dev: PCH device to check
+ * @iobasep: Returns address of IO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no IO base)
+ */
+int pch_get_io_base(struct udevice *dev, u32 *iobasep);
+
#endif
* functions, rather than byte/word/dword. But both are supported.
*/
int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
+int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
+int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
+int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
+int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
+int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
#ifdef CONFIG_DM_PCI_COMPAT
/* Compatibility with old naming */
return pci_write_config32(pcidev, offset, value);
}
-int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
-
/* Compatibility with old naming */
static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
u16 value)
return pci_write_config16(pcidev, offset, value);
}
-int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
-
/* Compatibility with old naming */
static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
u8 value)
return pci_write_config8(pcidev, offset, value);
}
-int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
-
/* Compatibility with old naming */
static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
u32 *valuep)
return pci_read_config32(pcidev, offset, valuep);
}
-int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
-
/* Compatibility with old naming */
static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
u16 *valuep)
return pci_read_config16(pcidev, offset, valuep);
}
-int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
-
/* Compatibility with old naming */
static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
u8 *valuep)
{
return pci_read_config8(pcidev, offset, valuep);
}
-
#endif /* CONFIG_DM_PCI_COMPAT */
/**
projects / oweals / u-boot.git / commitdiff