variables:
windows_vm: vs2017-win2016
ubuntu_vm: ubuntu-18.04
+ macos_vm: macOS-10.15
ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200403-27Apr2020
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# Tell MSYS2 not to ‘cd’ our startup directory to HOME
CHERE_INVOKING: yes
+ - job: tools_only_macOS
+ displayName: 'Ensure host tools build for macOS X'
+ pool:
+ vmImage: $(macos_vm)
+ steps:
+ - script: brew install make
+ displayName: Brew install dependencies
+ - script: |
+ gmake tools-only_config tools-only NO_SDL=1 \
+ HOSTCFLAGS="-I/usr/local/opt/openssl@1.1/include" \
+ HOSTLDFLAGS="-L/usr/local/opt/openssl@1.1/lib" \
+ -j$(sysctl -n hw.logicalcpu)
+ displayName: 'Perform tools-only build'
+
- job: cppcheck
displayName: 'Static code analysis with cppcheck'
pool:
# A bit shorter of a description is OK with us.
--min-conf-desc-length=2
+
+# Extra checks for U-Boot
+--u-boot
S: Maintained
F: arch/arm/include/asm/arch-owl/
F: arch/arm/mach-owl/
+F: doc/board/actions/
F: drivers/clk/owl/
F: drivers/serial/serial_owl.c
F: include/configs/owl-common.h
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-coldfire.git
F: arch/m68k/
+F: doc/arch/m68k.rst
DFU
M: Lukasz Majewski <lukma@denx.de>
ifeq ($(CONFIG_ARCH_ROCKCHIP),y)
-# rockchip image type
-ifeq ($(CONFIG_SPL_SPI_LOAD),y)
-ROCKCHIP_IMG_TYPE := rkspi
-else
-ROCKCHIP_IMG_TYPE := rksd
-endif
-
# TPL + SPL
ifeq ($(CONFIG_SPL)$(CONFIG_TPL),yy)
-MKIMAGEFLAGS_u-boot-tpl-rockchip.bin = -n $(CONFIG_SYS_SOC) -T $(ROCKCHIP_IMG_TYPE)
+MKIMAGEFLAGS_u-boot-tpl-rockchip.bin = -n $(CONFIG_SYS_SOC) -T rksd
tpl/u-boot-tpl-rockchip.bin: tpl/u-boot-tpl.bin FORCE
$(call if_changed,mkimage)
idbloader.img: tpl/u-boot-tpl-rockchip.bin spl/u-boot-spl.bin FORCE
$(call if_changed,cat)
else
-MKIMAGEFLAGS_idbloader.img = -n $(CONFIG_SYS_SOC) -T $(ROCKCHIP_IMG_TYPE)
+MKIMAGEFLAGS_idbloader.img = -n $(CONFIG_SYS_SOC) -T rksd
idbloader.img: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
endif
can be displayed via the splashscreen support or the
bmp command.
-- Compression support:
- CONFIG_GZIP
-
- Enabled by default to support gzip compressed images.
-
- CONFIG_BZIP2
-
- If this option is set, support for bzip2 compressed
- images is included. If not, only uncompressed and gzip
- compressed images are supported.
-
- NOTE: the bzip2 algorithm requires a lot of RAM, so
- the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
- be at least 4MB.
-
- MII/PHY support:
CONFIG_PHY_CLOCK_FREQ (ppc4xx)
This enable the NEW i2c subsystem, and will allow you to use
i2c commands at the u-boot command line (as long as you set
- CONFIG_CMD_I2C in CONFIG_COMMANDS) and communicate with i2c
- based realtime clock chips or other i2c devices. See
- common/cmd_i2c.c for a description of the command line
- interface.
-
- ported i2c driver to the new framework:
- - drivers/i2c/soft_i2c.c:
- - activate first bus with CONFIG_SYS_I2C_SOFT define
CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
for defining speed and slave address
- activate second bus with I2C_SOFT_DECLARATIONS2 define
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-roc-cc.dtb \
- rk3328-rock64.dtb
+ rk3328-rock64.dtb \
+ rk3328-rock-pi-e.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
rk3368-lion.dtb \
rk3399-nanopi-neo4.dtb \
rk3399-orangepi.dtb \
rk3399-pinebook-pro.dtb \
- rk3399-puma-ddr1333.dtb \
- rk3399-puma-ddr1600.dtb \
- rk3399-puma-ddr1866.dtb \
+ rk3399-puma-haikou.dtb \
rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
rk3399-rock-pi-4.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Radxa
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr3-666.dtsi"
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+};
+
+&sdmmc0m1_gpio {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_up_4ma {
+ u-boot,dm-spl;
+};
+
+&usb_host0_xhci {
+ vbus-supply = <&vcc5v0_host_xhci>;
+ status = "okay";
+};
+
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
+&vcc_sd {
+ u-boot,dm-spl;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Radxa
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Radxa Rockpi E";
+ compatible = "radxa,rock-pi-e", "rockchip,rk3328";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc5v0_host_xhci";
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ supports-emmc;
+ disable-wp;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc18_emmc>;
+ status = "okay";
+};
+
+&gmac2io {
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_io>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ snps,force_thresh_dma_mode;
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x26>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ status = "okay";
+ reg = <0x18>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_io>;
+ vcc6-supply = <&vcc_sys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_18: LDO_REG1 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_emmc: LDO_REG2 {
+ regulator-name = "vcc18_emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+ };
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_io>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ max-frequency = <150000000>;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ supports-sd;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
/ {
chosen {
+ stdout-path = "serial2:1500000n8";
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-
-#include "rk3399-puma-u-boot.dtsi"
-#include "rk3399-sdram-ddr3-1333.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-/dts-v1/;
-
-#include "rk3399-puma.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-
-#include "rk3399-puma-u-boot.dtsi"
-#include "rk3399-sdram-ddr3-1600.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-/dts-v1/;
-
-#include "rk3399-puma.dtsi"
-#include "rk3399-u-boot.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-
-#include "rk3399-puma-u-boot.dtsi"
-#include "rk3399-sdram-ddr3-1866.dtsi"
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-/dts-v1/;
-
-#include "rk3399-puma.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3399-u-boot.dtsi"
+
+#ifdef CONFIG_TARGET_PUMA_RK3399_RAM_DDR3_1333
+#include "rk3399-sdram-ddr3-1333.dtsi"
+#endif
+#ifdef CONFIG_TARGET_PUMA_RK3399_RAM_DDR3_1600
+#include "rk3399-sdram-ddr3-1600.dtsi"
+#endif
+#ifdef CONFIG_TARGET_PUMA_RK3399_RAM_DDR3_1866
+#include "rk3399-sdram-ddr3-1866.dtsi"
+#endif
+
+/ {
+ config {
+ u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
+ u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
+ u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
+ u-boot,boot-led = "module_led";
+ sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ u-boot,spl-boot-order = \
+ "same-as-spl", &norflash, &sdhci, &sdmmc;
+ };
+
+ aliases {
+ spi0 = &spi1;
+ spi1 = &spi5;
+ };
+
+ /*
+ * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
+ * eMMC and SPI flash powered-down initially (in fact it keeps the
+ * reset signal asserted). Even though it is an enable signal, we
+ * model this as a regulator.
+ */
+ bios_enable: bios_enable {
+ compatible = "regulator-fixed";
+ u-boot,dm-pre-reloc;
+ regulator-name = "bios_enable";
+ enable-active-high;
+ gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&gpio1 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
+
+&norflash {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include "rk3399-puma.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3399-Q7 SoM";
+ compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ pinctrl-0 = <&led_pin_module>, <&led_sd_haikou>;
+
+ sd-card-led {
+ label = "sd_card_led";
+ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+ };
+
+ i2s0-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Haikou,I2S-codec";
+ simple-audio-card,mclk-fs = <512>;
+
+ simple-audio-card,codec {
+ clocks = <&sgtl5000_clk>;
+ sound-dai = <&sgtl5000>;
+ };
+
+ simple-audio-card,cpu {
+ bitclock-master;
+ frame-master;
+ sound-dai = <&i2s0>;
+ };
+ };
+
+ sgtl5000_clk: sgtl5000-oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_baseboard: vcc3v3-baseboard {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_baseboard";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_baseboard: vcc5v0-baseboard {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_baseboard";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-name = "vcc5v0_otg";
+ regulator-always-on;
+ };
+
+ vdda_codec: vdda-codec {
+ compatible = "regulator-fixed";
+ regulator-name = "vdda_codec";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_baseboard>;
+ };
+
+ vddd_codec: vddd-codec {
+ compatible = "regulator-fixed";
+ regulator-name = "vddd_codec";
+ regulator-boot-on;
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1600000>;
+ vin-supply = <&vcc5v0_baseboard>;
+ };
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&i2c2 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ i2c-scl-rising-time-ns = <450>;
+ i2c-scl-falling-time-ns = <15>;
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&sgtl5000_clk>;
+ #sound-dai-cells = <0>;
+ VDDA-supply = <&vdda_codec>;
+ VDDIO-supply = <&vdda_codec>;
+ VDDD-supply = <&vddd_codec>;
+ status = "okay";
+ };
+};
+
+&i2c6 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ num-lanes = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&haikou_pin_hog>;
+
+ hog {
+ haikou_pin_hog: haikou-pin-hog {
+ rockchip,pins =
+ /* LID_BTN */
+ <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* BATLOW# */
+ <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* SLP_BTN# */
+ <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
+ /* BIOS_DISABLE# */
+ <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ led_sd_haikou: led-sd-gpio {
+ rockchip,pins =
+ <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb2 {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins =
+ <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ vmmc-supply = <&vcc3v3_baseboard>;
+ status = "okay";
+};
+
+&spi5 {
+ status = "okay";
+};
+
+&tcphy0 {
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&usbdrd3_0 {
+ status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&u2phy0_host {
+ phy-supply = <&vcc5v0_otg>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-
-#include "rk3399-u-boot.dtsi"
-/ {
- config {
- u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
- u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
- u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
- u-boot,boot-led = "module_led";
- sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- u-boot,spl-boot-order = \
- "same-as-spl", &norflash, &sdhci, &sdmmc;
- };
-
- aliases {
- spi0 = &spi1;
- spi1 = &spi5;
- };
-
- /*
- * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
- * eMMC and SPI flash powered-down initially (in fact it keeps the
- * reset signal asserted). Even though it is an enable signal, we
- * model this as a regulator.
- */
- bios_enable: bios_enable {
- compatible = "regulator-fixed";
- u-boot,dm-pre-reloc;
- regulator-name = "bios_enable";
- enable-active-high;
- gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-};
-
-&gpio1 {
- u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
- u-boot,dm-pre-reloc;
-};
-
-&norflash {
- u-boot,dm-pre-reloc;
-};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
- gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
enable-active-low;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x10>;
};
chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdhci, &sdmmc;
+ };
+
+ config {
+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
};
vcc_hub_en: vcc_hub_en-regulator {
vin-supply = <&vcc_vbus_typec0>;
};
+&spi1 {
+ spi_flash: flash@0 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
&vdd_log {
regulator-min-microvolt = <430000>;
regulator-init-microvolt = <950000>;
};
chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci;
+ };
+
+ config {
+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
+ };
+};
+
+&spi1 {
+ spi_flash: flash@0 {
+ u-boot,dm-pre-reloc;
};
};
status = "disabled";
};
+ uart4: serial@fc00c000 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0xfc00c000 0x100>;
+ clocks = <&uart4_clk>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
i2c1: i2c@fc028000 {
compatible = "atmel,sama5d2-i2c";
reg = <0xfc028000 0x100>;
#endif
#endif
+static inline void set_gd(volatile gd_t *gd_ptr)
+{
+#ifdef CONFIG_ARM64
+ __asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr));
+#else
+ __asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr));
+#endif
+}
+
#endif /* __ASM_GBL_DATA_H */
#ifdef CONFIG_ARMV7_PSCI
void psci_arch_cpu_entry(void);
+void psci_arch_init(void);
u32 psci_version(void);
s32 psci_features(u32 function_id, u32 psci_fid);
s32 psci_cpu_off(void);
MBUS_QOS_HIGHEST
};
-inline void mbus_configure_port(u8 port,
- bool bwlimit,
- bool priority,
- u8 qos, /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
- u8 waittime, /* 0 .. 0xf */
- u8 acs, /* 0 .. 0xff */
- u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */
- u16 bwl1,
- u16 bwl2)
+static inline void mbus_configure_port(u8 port,
+ bool bwlimit,
+ bool priority,
+ u8 qos, /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
+ u8 waittime, /* 0 .. 0xf */
+ u8 acs, /* 0 .. 0xff */
+ u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */
+ u16 bwl1,
+ u16 bwl2)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
+source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
# architecture-specific options below
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+config SIFIVE_FU540
+ bool
+ select ARCH_EARLY_INIT_R
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER
+ imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply CMD_CPU
+ imply SPL_CPU_SUPPORT
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 SiFive, Inc
+# Pragnesh Patel <pragnesh.patel@sifive.com>
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += dram.o
+obj-y += cpu.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <irq_func.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+ /*
+ * Ensure that we run from first 4GB so that all
+ * addresses used by U-Boot are 32bit addresses.
+ *
+ * This in-turn ensures that 32bit DMA capable
+ * devices work fine because DMA mapping APIs will
+ * provide 32bit DMA addresses only.
+ */
+ if (gd->ram_top > SZ_4G)
+ return SZ_4G;
+#endif
+ return gd->ram_top;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <dm.h>
+#include <log.h>
+
+int soc_spl_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
. = ALIGN(4);
_end = .;
+ _image_binary_end = .;
.bss : {
__bss_start = .;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2019 SiFive, Inc
+ */
+
+/ {
+ cpus {
+ assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+ assigned-clock-rates = <1000000000>;
+ u-boot,dm-spl;
+ cpu0: cpu@0 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu2: cpu@2 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu2_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu3: cpu@3 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu4: cpu@4 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu4_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+ otp: otp@10070000 {
+ compatible = "sifive,fu540-c000-otp";
+ reg = <0x0 0x10070000 0x0 0x0FFF>;
+ fuse-count = <0x1000>;
+ };
+ clint@2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>;
+ reg = <0x0 0x2000000 0x0 0xc0000>;
+ u-boot,dm-spl;
+ };
+ dmc: dmc@100b0000 {
+ compatible = "sifive,fu540-c000-ddr";
+ reg = <0x0 0x100b0000 0x0 0x0800
+ 0x0 0x100b2000 0x0 0x2000
+ 0x0 0x100b8000 0x0 0x0fff>;
+ clocks = <&prci PRCI_CLK_DDRPLL>;
+ clock-frequency = <933333324>;
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&prci {
+ u-boot,dm-spl;
+};
+
+&uart0 {
+ u-boot,dm-spl;
+};
+
+&qspi2 {
+ u-boot,dm-spl;
+};
+
+ð0 {
+ assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
+ assigned-clock-rates = <125000000>;
+};
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
clocks = <&prci PRCI_CLK_TLCLK>;
status = "disabled";
};
+ dma: dma@3000000 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <23 24 25 26 27 28 29 30>;
+ #dma-cells = <1>;
+ };
uart1: serial@10011000 {
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
reg = <0x0 0x10011000 0x0 0x1000>;
#pwm-cells = <3>;
status = "disabled";
};
-
+ l2cache: cache-controller@2010000 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
+ gpio: gpio@10060000 {
+ compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
+ <14>, <15>, <16>, <17>, <18>, <19>, <20>,
+ <21>, <22>;
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
};
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020 SiFive, Inc
+ */
+
+&dmc {
+ sifive,ddr-params = <
+ 0x00000a00 /* DENALI_CTL_00_DATA */
+ 0x00000000 /* DENALI_CTL_01_DATA */
+ 0x00000000 /* DENALI_CTL_02_DATA */
+ 0x00000000 /* DENALI_CTL_03_DATA */
+ 0x00000000 /* DENALI_CTL_04_DATA */
+ 0x00000000 /* DENALI_CTL_05_DATA */
+ 0x0000000a /* DENALI_CTL_06_DATA */
+ 0x0002d362 /* DENALI_CTL_07_DATA */
+ 0x00071073 /* DENALI_CTL_08_DATA */
+ 0x0a1c0255 /* DENALI_CTL_09_DATA */
+ 0x1c1c0400 /* DENALI_CTL_10_DATA */
+ 0x0404990b /* DENALI_CTL_11_DATA */
+ 0x2b050405 /* DENALI_CTL_12_DATA */
+ 0x0e0c081e /* DENALI_CTL_13_DATA */
+ 0x08090914 /* DENALI_CTL_14_DATA */
+ 0x00fde718 /* DENALI_CTL_15_DATA */
+ 0x00180a05 /* DENALI_CTL_16_DATA */
+ 0x008b130e /* DENALI_CTL_17_DATA */
+ 0x01000118 /* DENALI_CTL_18_DATA */
+ 0x0e032101 /* DENALI_CTL_19_DATA */
+ 0x00000000 /* DENALI_CTL_20_DATA */
+ 0x00000101 /* DENALI_CTL_21_DATA */
+ 0x00000000 /* DENALI_CTL_22_DATA */
+ 0x0a000000 /* DENALI_CTL_23_DATA */
+ 0x00000000 /* DENALI_CTL_24_DATA */
+ 0x01450100 /* DENALI_CTL_25_DATA */
+ 0x00001c36 /* DENALI_CTL_26_DATA */
+ 0x00000005 /* DENALI_CTL_27_DATA */
+ 0x00170006 /* DENALI_CTL_28_DATA */
+ 0x014e0300 /* DENALI_CTL_29_DATA */
+ 0x03010000 /* DENALI_CTL_30_DATA */
+ 0x000a0e00 /* DENALI_CTL_31_DATA */
+ 0x04030200 /* DENALI_CTL_32_DATA */
+ 0x0000031f /* DENALI_CTL_33_DATA */
+ 0x00070004 /* DENALI_CTL_34_DATA */
+ 0x00000000 /* DENALI_CTL_35_DATA */
+ 0x00000000 /* DENALI_CTL_36_DATA */
+ 0x00000000 /* DENALI_CTL_37_DATA */
+ 0x00000000 /* DENALI_CTL_38_DATA */
+ 0x00000000 /* DENALI_CTL_39_DATA */
+ 0x00000000 /* DENALI_CTL_40_DATA */
+ 0x00000000 /* DENALI_CTL_41_DATA */
+ 0x00000000 /* DENALI_CTL_42_DATA */
+ 0x00000000 /* DENALI_CTL_43_DATA */
+ 0x00000000 /* DENALI_CTL_44_DATA */
+ 0x00000000 /* DENALI_CTL_45_DATA */
+ 0x00000000 /* DENALI_CTL_46_DATA */
+ 0x00000000 /* DENALI_CTL_47_DATA */
+ 0x00000000 /* DENALI_CTL_48_DATA */
+ 0x00000000 /* DENALI_CTL_49_DATA */
+ 0x00000000 /* DENALI_CTL_50_DATA */
+ 0x00000000 /* DENALI_CTL_51_DATA */
+ 0x00000000 /* DENALI_CTL_52_DATA */
+ 0x00000000 /* DENALI_CTL_53_DATA */
+ 0x00000000 /* DENALI_CTL_54_DATA */
+ 0x00000000 /* DENALI_CTL_55_DATA */
+ 0x00000000 /* DENALI_CTL_56_DATA */
+ 0x00000000 /* DENALI_CTL_57_DATA */
+ 0x00000000 /* DENALI_CTL_58_DATA */
+ 0x00000000 /* DENALI_CTL_59_DATA */
+ 0x00000424 /* DENALI_CTL_60_DATA */
+ 0x00000201 /* DENALI_CTL_61_DATA */
+ 0x00001008 /* DENALI_CTL_62_DATA */
+ 0x00000000 /* DENALI_CTL_63_DATA */
+ 0x00000200 /* DENALI_CTL_64_DATA */
+ 0x00000000 /* DENALI_CTL_65_DATA */
+ 0x00000481 /* DENALI_CTL_66_DATA */
+ 0x00000400 /* DENALI_CTL_67_DATA */
+ 0x00000424 /* DENALI_CTL_68_DATA */
+ 0x00000201 /* DENALI_CTL_69_DATA */
+ 0x00001008 /* DENALI_CTL_70_DATA */
+ 0x00000000 /* DENALI_CTL_71_DATA */
+ 0x00000200 /* DENALI_CTL_72_DATA */
+ 0x00000000 /* DENALI_CTL_73_DATA */
+ 0x00000481 /* DENALI_CTL_74_DATA */
+ 0x00000400 /* DENALI_CTL_75_DATA */
+ 0x01010000 /* DENALI_CTL_76_DATA */
+ 0x00000000 /* DENALI_CTL_77_DATA */
+ 0x00000000 /* DENALI_CTL_78_DATA */
+ 0x00000000 /* DENALI_CTL_79_DATA */
+ 0x00000000 /* DENALI_CTL_80_DATA */
+ 0x00000000 /* DENALI_CTL_81_DATA */
+ 0x00000000 /* DENALI_CTL_82_DATA */
+ 0x00000000 /* DENALI_CTL_83_DATA */
+ 0x00000000 /* DENALI_CTL_84_DATA */
+ 0x00000000 /* DENALI_CTL_85_DATA */
+ 0x00000000 /* DENALI_CTL_86_DATA */
+ 0x00000000 /* DENALI_CTL_87_DATA */
+ 0x00000000 /* DENALI_CTL_88_DATA */
+ 0x00000000 /* DENALI_CTL_89_DATA */
+ 0x00000000 /* DENALI_CTL_90_DATA */
+ 0x00000000 /* DENALI_CTL_91_DATA */
+ 0x00000000 /* DENALI_CTL_92_DATA */
+ 0x00000000 /* DENALI_CTL_93_DATA */
+ 0x00000000 /* DENALI_CTL_94_DATA */
+ 0x00000000 /* DENALI_CTL_95_DATA */
+ 0x00000000 /* DENALI_CTL_96_DATA */
+ 0x00000000 /* DENALI_CTL_97_DATA */
+ 0x00000000 /* DENALI_CTL_98_DATA */
+ 0x00000000 /* DENALI_CTL_99_DATA */
+ 0x00000000 /* DENALI_CTL_100_DATA */
+ 0x00000000 /* DENALI_CTL_101_DATA */
+ 0x00000000 /* DENALI_CTL_102_DATA */
+ 0x00000000 /* DENALI_CTL_103_DATA */
+ 0x00000000 /* DENALI_CTL_104_DATA */
+ 0x00000003 /* DENALI_CTL_105_DATA */
+ 0x00000000 /* DENALI_CTL_106_DATA */
+ 0x00000000 /* DENALI_CTL_107_DATA */
+ 0x00000000 /* DENALI_CTL_108_DATA */
+ 0x00000000 /* DENALI_CTL_109_DATA */
+ 0x01000000 /* DENALI_CTL_110_DATA */
+ 0x00040000 /* DENALI_CTL_111_DATA */
+ 0x00800200 /* DENALI_CTL_112_DATA */
+ 0x00000200 /* DENALI_CTL_113_DATA */
+ 0x00000040 /* DENALI_CTL_114_DATA */
+ 0x01000100 /* DENALI_CTL_115_DATA */
+ 0x0a000002 /* DENALI_CTL_116_DATA */
+ 0x0101ffff /* DENALI_CTL_117_DATA */
+ 0x01010101 /* DENALI_CTL_118_DATA */
+ 0x01010101 /* DENALI_CTL_119_DATA */
+ 0x0000010b /* DENALI_CTL_120_DATA */
+ 0x00000c01 /* DENALI_CTL_121_DATA */
+ 0x00000000 /* DENALI_CTL_122_DATA */
+ 0x00000000 /* DENALI_CTL_123_DATA */
+ 0x00000000 /* DENALI_CTL_124_DATA */
+ 0x00000000 /* DENALI_CTL_125_DATA */
+ 0x00030300 /* DENALI_CTL_126_DATA */
+ 0x00000000 /* DENALI_CTL_127_DATA */
+ 0x00010001 /* DENALI_CTL_128_DATA */
+ 0x00000000 /* DENALI_CTL_129_DATA */
+ 0x00000000 /* DENALI_CTL_130_DATA */
+ 0x00000000 /* DENALI_CTL_131_DATA */
+ 0x00000000 /* DENALI_CTL_132_DATA */
+ 0x00000000 /* DENALI_CTL_133_DATA */
+ 0x00000000 /* DENALI_CTL_134_DATA */
+ 0x00000000 /* DENALI_CTL_135_DATA */
+ 0x00000000 /* DENALI_CTL_136_DATA */
+ 0x00000000 /* DENALI_CTL_137_DATA */
+ 0x00000000 /* DENALI_CTL_138_DATA */
+ 0x00000000 /* DENALI_CTL_139_DATA */
+ 0x00000000 /* DENALI_CTL_140_DATA */
+ 0x00000000 /* DENALI_CTL_141_DATA */
+ 0x00000000 /* DENALI_CTL_142_DATA */
+ 0x00000000 /* DENALI_CTL_143_DATA */
+ 0x00000000 /* DENALI_CTL_144_DATA */
+ 0x00000000 /* DENALI_CTL_145_DATA */
+ 0x00000000 /* DENALI_CTL_146_DATA */
+ 0x00000000 /* DENALI_CTL_147_DATA */
+ 0x00000000 /* DENALI_CTL_148_DATA */
+ 0x00000000 /* DENALI_CTL_149_DATA */
+ 0x00000000 /* DENALI_CTL_150_DATA */
+ 0x00000000 /* DENALI_CTL_151_DATA */
+ 0x00000000 /* DENALI_CTL_152_DATA */
+ 0x00000000 /* DENALI_CTL_153_DATA */
+ 0x00000000 /* DENALI_CTL_154_DATA */
+ 0x00000000 /* DENALI_CTL_155_DATA */
+ 0x00000000 /* DENALI_CTL_156_DATA */
+ 0x00000000 /* DENALI_CTL_157_DATA */
+ 0x00000000 /* DENALI_CTL_158_DATA */
+ 0x00000000 /* DENALI_CTL_159_DATA */
+ 0x00000000 /* DENALI_CTL_160_DATA */
+ 0x02010102 /* DENALI_CTL_161_DATA */
+ 0x0107070d /* DENALI_CTL_162_DATA */
+ 0x04040400 /* DENALI_CTL_163_DATA */
+ 0x03000503 /* DENALI_CTL_164_DATA */
+ 0x00000000 /* DENALI_CTL_165_DATA */
+ 0x00000000 /* DENALI_CTL_166_DATA */
+ 0x00000000 /* DENALI_CTL_167_DATA */
+ 0x00000000 /* DENALI_CTL_168_DATA */
+ 0x280d0000 /* DENALI_CTL_169_DATA */
+ 0x01000000 /* DENALI_CTL_170_DATA */
+ 0x00000000 /* DENALI_CTL_171_DATA */
+ 0x00010001 /* DENALI_CTL_172_DATA */
+ 0x00000000 /* DENALI_CTL_173_DATA */
+ 0x00000000 /* DENALI_CTL_174_DATA */
+ 0x00000000 /* DENALI_CTL_175_DATA */
+ 0x00000000 /* DENALI_CTL_176_DATA */
+ 0x00000000 /* DENALI_CTL_177_DATA */
+ 0x00000000 /* DENALI_CTL_178_DATA */
+ 0x00000000 /* DENALI_CTL_179_DATA */
+ 0x00000000 /* DENALI_CTL_180_DATA */
+ 0x01000000 /* DENALI_CTL_181_DATA */
+ 0x00000001 /* DENALI_CTL_182_DATA */
+ 0x00000100 /* DENALI_CTL_183_DATA */
+ 0x00000101 /* DENALI_CTL_184_DATA */
+ 0x67676701 /* DENALI_CTL_185_DATA */
+ 0x67676767 /* DENALI_CTL_186_DATA */
+ 0x67676767 /* DENALI_CTL_187_DATA */
+ 0x67676767 /* DENALI_CTL_188_DATA */
+ 0x67676767 /* DENALI_CTL_189_DATA */
+ 0x67676767 /* DENALI_CTL_190_DATA */
+ 0x67676767 /* DENALI_CTL_191_DATA */
+ 0x67676767 /* DENALI_CTL_192_DATA */
+ 0x67676767 /* DENALI_CTL_193_DATA */
+ 0x01000067 /* DENALI_CTL_194_DATA */
+ 0x00000001 /* DENALI_CTL_195_DATA */
+ 0x00000101 /* DENALI_CTL_196_DATA */
+ 0x00000000 /* DENALI_CTL_197_DATA */
+ 0x00000000 /* DENALI_CTL_198_DATA */
+ 0x00000000 /* DENALI_CTL_199_DATA */
+ 0x00000000 /* DENALI_CTL_200_DATA */
+ 0x00000000 /* DENALI_CTL_201_DATA */
+ 0x00000000 /* DENALI_CTL_202_DATA */
+ 0x00000000 /* DENALI_CTL_203_DATA */
+ 0x00000000 /* DENALI_CTL_204_DATA */
+ 0x00000000 /* DENALI_CTL_205_DATA */
+ 0x00000000 /* DENALI_CTL_206_DATA */
+ 0x00000000 /* DENALI_CTL_207_DATA */
+ 0x00000001 /* DENALI_CTL_208_DATA */
+ 0x00000000 /* DENALI_CTL_209_DATA */
+ 0x007fffff /* DENALI_CTL_210_DATA */
+ 0x00000000 /* DENALI_CTL_211_DATA */
+ 0x007fffff /* DENALI_CTL_212_DATA */
+ 0x00000000 /* DENALI_CTL_213_DATA */
+ 0x007fffff /* DENALI_CTL_214_DATA */
+ 0x00000000 /* DENALI_CTL_215_DATA */
+ 0x007fffff /* DENALI_CTL_216_DATA */
+ 0x00000000 /* DENALI_CTL_217_DATA */
+ 0x007fffff /* DENALI_CTL_218_DATA */
+ 0x00000000 /* DENALI_CTL_219_DATA */
+ 0x007fffff /* DENALI_CTL_220_DATA */
+ 0x00000000 /* DENALI_CTL_221_DATA */
+ 0x007fffff /* DENALI_CTL_222_DATA */
+ 0x00000000 /* DENALI_CTL_223_DATA */
+ 0x037fffff /* DENALI_CTL_224_DATA */
+ 0xffffffff /* DENALI_CTL_225_DATA */
+ 0x000f000f /* DENALI_CTL_226_DATA */
+ 0x00ffff03 /* DENALI_CTL_227_DATA */
+ 0x000fffff /* DENALI_CTL_228_DATA */
+ 0x0003000f /* DENALI_CTL_229_DATA */
+ 0xffffffff /* DENALI_CTL_230_DATA */
+ 0x000f000f /* DENALI_CTL_231_DATA */
+ 0x00ffff03 /* DENALI_CTL_232_DATA */
+ 0x000fffff /* DENALI_CTL_233_DATA */
+ 0x0003000f /* DENALI_CTL_234_DATA */
+ 0xffffffff /* DENALI_CTL_235_DATA */
+ 0x000f000f /* DENALI_CTL_236_DATA */
+ 0x00ffff03 /* DENALI_CTL_237_DATA */
+ 0x000fffff /* DENALI_CTL_238_DATA */
+ 0x0003000f /* DENALI_CTL_239_DATA */
+ 0xffffffff /* DENALI_CTL_240_DATA */
+ 0x000f000f /* DENALI_CTL_241_DATA */
+ 0x00ffff03 /* DENALI_CTL_242_DATA */
+ 0x000fffff /* DENALI_CTL_243_DATA */
+ 0x6407000f /* DENALI_CTL_244_DATA */
+ 0x01640001 /* DENALI_CTL_245_DATA */
+ 0x00000000 /* DENALI_CTL_246_DATA */
+ 0x00000000 /* DENALI_CTL_247_DATA */
+ 0x00001700 /* DENALI_CTL_248_DATA */
+ 0x00386c05 /* DENALI_CTL_249_DATA */
+ 0x02000200 /* DENALI_CTL_250_DATA */
+ 0x02000200 /* DENALI_CTL_251_DATA */
+ 0x0000386c /* DENALI_CTL_252_DATA */
+ 0x00023438 /* DENALI_CTL_253_DATA */
+ 0x02020d10 /* DENALI_CTL_254_DATA */
+ 0x00140303 /* DENALI_CTL_255_DATA */
+ 0x00000000 /* DENALI_CTL_256_DATA */
+ 0x00000000 /* DENALI_CTL_257_DATA */
+ 0x00001403 /* DENALI_CTL_258_DATA */
+ 0x00000000 /* DENALI_CTL_259_DATA */
+ 0x00000000 /* DENALI_CTL_260_DATA */
+ 0x00000000 /* DENALI_CTL_261_DATA */
+ 0x00000000 /* DENALI_CTL_262_DATA */
+ 0x0d010000 /* DENALI_CTL_263_DATA */
+ 0x00000008 /* DENALI_CTL_264_DATA */
+ 0x31706542 /* DENALI_PHY_00_DATA */
+ 0x0004c008 /* DENALI_PHY_01_DATA */
+ 0x000000da /* DENALI_PHY_02_DATA */
+ 0x00000000 /* DENALI_PHY_03_DATA */
+ 0x00000000 /* DENALI_PHY_04_DATA */
+ 0x00010000 /* DENALI_PHY_05_DATA */
+ 0x01DDDD90 /* DENALI_PHY_06_DATA */
+ 0x01DDDD90 /* DENALI_PHY_07_DATA */
+ 0x01030000 /* DENALI_PHY_08_DATA */
+ 0x01000000 /* DENALI_PHY_09_DATA */
+ 0x00c00000 /* DENALI_PHY_10_DATA */
+ 0x00000007 /* DENALI_PHY_11_DATA */
+ 0x00000000 /* DENALI_PHY_12_DATA */
+ 0x00000000 /* DENALI_PHY_13_DATA */
+ 0x04000408 /* DENALI_PHY_14_DATA */
+ 0x00000408 /* DENALI_PHY_15_DATA */
+ 0x00e4e400 /* DENALI_PHY_16_DATA */
+ 0x00000000 /* DENALI_PHY_17_DATA */
+ 0x00000000 /* DENALI_PHY_18_DATA */
+ 0x00000000 /* DENALI_PHY_19_DATA */
+ 0x00000000 /* DENALI_PHY_20_DATA */
+ 0x00000000 /* DENALI_PHY_21_DATA */
+ 0x00000000 /* DENALI_PHY_22_DATA */
+ 0x00000000 /* DENALI_PHY_23_DATA */
+ 0x00000000 /* DENALI_PHY_24_DATA */
+ 0x00000000 /* DENALI_PHY_25_DATA */
+ 0x00000000 /* DENALI_PHY_26_DATA */
+ 0x00000000 /* DENALI_PHY_27_DATA */
+ 0x00000000 /* DENALI_PHY_28_DATA */
+ 0x00000000 /* DENALI_PHY_29_DATA */
+ 0x00000000 /* DENALI_PHY_30_DATA */
+ 0x00000000 /* DENALI_PHY_31_DATA */
+ 0x00000000 /* DENALI_PHY_32_DATA */
+ 0x00200000 /* DENALI_PHY_33_DATA */
+ 0x00000000 /* DENALI_PHY_34_DATA */
+ 0x00000000 /* DENALI_PHY_35_DATA */
+ 0x00000000 /* DENALI_PHY_36_DATA */
+ 0x00000000 /* DENALI_PHY_37_DATA */
+ 0x00000000 /* DENALI_PHY_38_DATA */
+ 0x00000000 /* DENALI_PHY_39_DATA */
+ 0x02800280 /* DENALI_PHY_40_DATA */
+ 0x02800280 /* DENALI_PHY_41_DATA */
+ 0x02800280 /* DENALI_PHY_42_DATA */
+ 0x02800280 /* DENALI_PHY_43_DATA */
+ 0x00000280 /* DENALI_PHY_44_DATA */
+ 0x00000000 /* DENALI_PHY_45_DATA */
+ 0x00000000 /* DENALI_PHY_46_DATA */
+ 0x00000000 /* DENALI_PHY_47_DATA */
+ 0x00000000 /* DENALI_PHY_48_DATA */
+ 0x00000000 /* DENALI_PHY_49_DATA */
+ 0x00800080 /* DENALI_PHY_50_DATA */
+ 0x00800080 /* DENALI_PHY_51_DATA */
+ 0x00800080 /* DENALI_PHY_52_DATA */
+ 0x00800080 /* DENALI_PHY_53_DATA */
+ 0x00800080 /* DENALI_PHY_54_DATA */
+ 0x00800080 /* DENALI_PHY_55_DATA */
+ 0x00800080 /* DENALI_PHY_56_DATA */
+ 0x00800080 /* DENALI_PHY_57_DATA */
+ 0x00800080 /* DENALI_PHY_58_DATA */
+ 0x000100da /* DENALI_PHY_59_DATA */
+ 0x01000200 /* DENALI_PHY_60_DATA */
+ 0x00000000 /* DENALI_PHY_61_DATA */
+ 0x00000000 /* DENALI_PHY_62_DATA */
+ 0x00000002 /* DENALI_PHY_63_DATA */
+ 0x51313152 /* DENALI_PHY_64_DATA */
+ 0x80013130 /* DENALI_PHY_65_DATA */
+ 0x02000080 /* DENALI_PHY_66_DATA */
+ 0x00100001 /* DENALI_PHY_67_DATA */
+ 0x0c064208 /* DENALI_PHY_68_DATA */
+ 0x000f0c0f /* DENALI_PHY_69_DATA */
+ 0x01000140 /* DENALI_PHY_70_DATA */
+ 0x0000000c /* DENALI_PHY_71_DATA */
+ 0x00000000 /* DENALI_PHY_72_DATA */
+ 0x00000000 /* DENALI_PHY_73_DATA */
+ 0x00000000 /* DENALI_PHY_74_DATA */
+ 0x00000000 /* DENALI_PHY_75_DATA */
+ 0x00000000 /* DENALI_PHY_76_DATA */
+ 0x00000000 /* DENALI_PHY_77_DATA */
+ 0x00000000 /* DENALI_PHY_78_DATA */
+ 0x00000000 /* DENALI_PHY_79_DATA */
+ 0x00000000 /* DENALI_PHY_80_DATA */
+ 0x00000000 /* DENALI_PHY_81_DATA */
+ 0x00000000 /* DENALI_PHY_82_DATA */
+ 0x00000000 /* DENALI_PHY_83_DATA */
+ 0x00000000 /* DENALI_PHY_84_DATA */
+ 0x00000000 /* DENALI_PHY_85_DATA */
+ 0x00000000 /* DENALI_PHY_86_DATA */
+ 0x00000000 /* DENALI_PHY_87_DATA */
+ 0x00000000 /* DENALI_PHY_88_DATA */
+ 0x00000000 /* DENALI_PHY_89_DATA */
+ 0x00000000 /* DENALI_PHY_90_DATA */
+ 0x00000000 /* DENALI_PHY_91_DATA */
+ 0x00000000 /* DENALI_PHY_92_DATA */
+ 0x00000000 /* DENALI_PHY_93_DATA */
+ 0x00000000 /* DENALI_PHY_94_DATA */
+ 0x00000000 /* DENALI_PHY_95_DATA */
+ 0x00000000 /* DENALI_PHY_96_DATA */
+ 0x00000000 /* DENALI_PHY_97_DATA */
+ 0x00000000 /* DENALI_PHY_98_DATA */
+ 0x00000000 /* DENALI_PHY_99_DATA */
+ 0x00000000 /* DENALI_PHY_100_DATA */
+ 0x00000000 /* DENALI_PHY_101_DATA */
+ 0x00000000 /* DENALI_PHY_102_DATA */
+ 0x00000000 /* DENALI_PHY_103_DATA */
+ 0x00000000 /* DENALI_PHY_104_DATA */
+ 0x00000000 /* DENALI_PHY_105_DATA */
+ 0x00000000 /* DENALI_PHY_106_DATA */
+ 0x00000000 /* DENALI_PHY_107_DATA */
+ 0x00000000 /* DENALI_PHY_108_DATA */
+ 0x00000000 /* DENALI_PHY_109_DATA */
+ 0x00000000 /* DENALI_PHY_110_DATA */
+ 0x00000000 /* DENALI_PHY_111_DATA */
+ 0x00000000 /* DENALI_PHY_112_DATA */
+ 0x00000000 /* DENALI_PHY_113_DATA */
+ 0x00000000 /* DENALI_PHY_114_DATA */
+ 0x00000000 /* DENALI_PHY_115_DATA */
+ 0x00000000 /* DENALI_PHY_116_DATA */
+ 0x00000000 /* DENALI_PHY_117_DATA */
+ 0x00000000 /* DENALI_PHY_118_DATA */
+ 0x00000000 /* DENALI_PHY_119_DATA */
+ 0x00000000 /* DENALI_PHY_120_DATA */
+ 0x00000000 /* DENALI_PHY_121_DATA */
+ 0x00000000 /* DENALI_PHY_122_DATA */
+ 0x00000000 /* DENALI_PHY_123_DATA */
+ 0x00000000 /* DENALI_PHY_124_DATA */
+ 0x00000000 /* DENALI_PHY_125_DATA */
+ 0x00000000 /* DENALI_PHY_126_DATA */
+ 0x00000000 /* DENALI_PHY_127_DATA */
+ 0x40263571 /* DENALI_PHY_128_DATA */
+ 0x0004c008 /* DENALI_PHY_129_DATA */
+ 0x000000da /* DENALI_PHY_130_DATA */
+ 0x00000000 /* DENALI_PHY_131_DATA */
+ 0x00000000 /* DENALI_PHY_132_DATA */
+ 0x00010000 /* DENALI_PHY_133_DATA */
+ 0x01DDDD90 /* DENALI_PHY_134_DATA */
+ 0x01DDDD90 /* DENALI_PHY_135_DATA */
+ 0x01030000 /* DENALI_PHY_136_DATA */
+ 0x01000000 /* DENALI_PHY_137_DATA */
+ 0x00c00000 /* DENALI_PHY_138_DATA */
+ 0x00000007 /* DENALI_PHY_139_DATA */
+ 0x00000000 /* DENALI_PHY_140_DATA */
+ 0x00000000 /* DENALI_PHY_141_DATA */
+ 0x04000408 /* DENALI_PHY_142_DATA */
+ 0x00000408 /* DENALI_PHY_143_DATA */
+ 0x00e4e400 /* DENALI_PHY_144_DATA */
+ 0x00000000 /* DENALI_PHY_145_DATA */
+ 0x00000000 /* DENALI_PHY_146_DATA */
+ 0x00000000 /* DENALI_PHY_147_DATA */
+ 0x00000000 /* DENALI_PHY_148_DATA */
+ 0x00000000 /* DENALI_PHY_149_DATA */
+ 0x00000000 /* DENALI_PHY_150_DATA */
+ 0x00000000 /* DENALI_PHY_151_DATA */
+ 0x00000000 /* DENALI_PHY_152_DATA */
+ 0x00000000 /* DENALI_PHY_153_DATA */
+ 0x00000000 /* DENALI_PHY_154_DATA */
+ 0x00000000 /* DENALI_PHY_155_DATA */
+ 0x00000000 /* DENALI_PHY_156_DATA */
+ 0x00000000 /* DENALI_PHY_157_DATA */
+ 0x00000000 /* DENALI_PHY_158_DATA */
+ 0x00000000 /* DENALI_PHY_159_DATA */
+ 0x00000000 /* DENALI_PHY_160_DATA */
+ 0x00200000 /* DENALI_PHY_161_DATA */
+ 0x00000000 /* DENALI_PHY_162_DATA */
+ 0x00000000 /* DENALI_PHY_163_DATA */
+ 0x00000000 /* DENALI_PHY_164_DATA */
+ 0x00000000 /* DENALI_PHY_165_DATA */
+ 0x00000000 /* DENALI_PHY_166_DATA */
+ 0x00000000 /* DENALI_PHY_167_DATA */
+ 0x02800280 /* DENALI_PHY_168_DATA */
+ 0x02800280 /* DENALI_PHY_169_DATA */
+ 0x02800280 /* DENALI_PHY_170_DATA */
+ 0x02800280 /* DENALI_PHY_171_DATA */
+ 0x00000280 /* DENALI_PHY_172_DATA */
+ 0x00000000 /* DENALI_PHY_173_DATA */
+ 0x00000000 /* DENALI_PHY_174_DATA */
+ 0x00000000 /* DENALI_PHY_175_DATA */
+ 0x00000000 /* DENALI_PHY_176_DATA */
+ 0x00000000 /* DENALI_PHY_177_DATA */
+ 0x00800080 /* DENALI_PHY_178_DATA */
+ 0x00800080 /* DENALI_PHY_179_DATA */
+ 0x00800080 /* DENALI_PHY_180_DATA */
+ 0x00800080 /* DENALI_PHY_181_DATA */
+ 0x00800080 /* DENALI_PHY_182_DATA */
+ 0x00800080 /* DENALI_PHY_183_DATA */
+ 0x00800080 /* DENALI_PHY_184_DATA */
+ 0x00800080 /* DENALI_PHY_185_DATA */
+ 0x00800080 /* DENALI_PHY_186_DATA */
+ 0x000100da /* DENALI_PHY_187_DATA */
+ 0x01000200 /* DENALI_PHY_188_DATA */
+ 0x00000000 /* DENALI_PHY_189_DATA */
+ 0x00000000 /* DENALI_PHY_190_DATA */
+ 0x00000002 /* DENALI_PHY_191_DATA */
+ 0x51313152 /* DENALI_PHY_192_DATA */
+ 0x80013130 /* DENALI_PHY_193_DATA */
+ 0x02000080 /* DENALI_PHY_194_DATA */
+ 0x00100001 /* DENALI_PHY_195_DATA */
+ 0x0c064208 /* DENALI_PHY_196_DATA */
+ 0x000f0c0f /* DENALI_PHY_197_DATA */
+ 0x01000140 /* DENALI_PHY_198_DATA */
+ 0x0000000c /* DENALI_PHY_199_DATA */
+ 0x00000000 /* DENALI_PHY_200_DATA */
+ 0x00000000 /* DENALI_PHY_201_DATA */
+ 0x00000000 /* DENALI_PHY_202_DATA */
+ 0x00000000 /* DENALI_PHY_203_DATA */
+ 0x00000000 /* DENALI_PHY_204_DATA */
+ 0x00000000 /* DENALI_PHY_205_DATA */
+ 0x00000000 /* DENALI_PHY_206_DATA */
+ 0x00000000 /* DENALI_PHY_207_DATA */
+ 0x00000000 /* DENALI_PHY_208_DATA */
+ 0x00000000 /* DENALI_PHY_209_DATA */
+ 0x00000000 /* DENALI_PHY_210_DATA */
+ 0x00000000 /* DENALI_PHY_211_DATA */
+ 0x00000000 /* DENALI_PHY_212_DATA */
+ 0x00000000 /* DENALI_PHY_213_DATA */
+ 0x00000000 /* DENALI_PHY_214_DATA */
+ 0x00000000 /* DENALI_PHY_215_DATA */
+ 0x00000000 /* DENALI_PHY_216_DATA */
+ 0x00000000 /* DENALI_PHY_217_DATA */
+ 0x00000000 /* DENALI_PHY_218_DATA */
+ 0x00000000 /* DENALI_PHY_219_DATA */
+ 0x00000000 /* DENALI_PHY_220_DATA */
+ 0x00000000 /* DENALI_PHY_221_DATA */
+ 0x00000000 /* DENALI_PHY_222_DATA */
+ 0x00000000 /* DENALI_PHY_223_DATA */
+ 0x00000000 /* DENALI_PHY_224_DATA */
+ 0x00000000 /* DENALI_PHY_225_DATA */
+ 0x00000000 /* DENALI_PHY_226_DATA */
+ 0x00000000 /* DENALI_PHY_227_DATA */
+ 0x00000000 /* DENALI_PHY_228_DATA */
+ 0x00000000 /* DENALI_PHY_229_DATA */
+ 0x00000000 /* DENALI_PHY_230_DATA */
+ 0x00000000 /* DENALI_PHY_231_DATA */
+ 0x00000000 /* DENALI_PHY_232_DATA */
+ 0x00000000 /* DENALI_PHY_233_DATA */
+ 0x00000000 /* DENALI_PHY_234_DATA */
+ 0x00000000 /* DENALI_PHY_235_DATA */
+ 0x00000000 /* DENALI_PHY_236_DATA */
+ 0x00000000 /* DENALI_PHY_237_DATA */
+ 0x00000000 /* DENALI_PHY_238_DATA */
+ 0x00000000 /* DENALI_PHY_239_DATA */
+ 0x00000000 /* DENALI_PHY_240_DATA */
+ 0x00000000 /* DENALI_PHY_241_DATA */
+ 0x00000000 /* DENALI_PHY_242_DATA */
+ 0x00000000 /* DENALI_PHY_243_DATA */
+ 0x00000000 /* DENALI_PHY_244_DATA */
+ 0x00000000 /* DENALI_PHY_245_DATA */
+ 0x00000000 /* DENALI_PHY_246_DATA */
+ 0x00000000 /* DENALI_PHY_247_DATA */
+ 0x00000000 /* DENALI_PHY_248_DATA */
+ 0x00000000 /* DENALI_PHY_249_DATA */
+ 0x00000000 /* DENALI_PHY_250_DATA */
+ 0x00000000 /* DENALI_PHY_251_DATA */
+ 0x00000000 /* DENALI_PHY_252_DATA */
+ 0x00000000 /* DENALI_PHY_253_DATA */
+ 0x00000000 /* DENALI_PHY_254_DATA */
+ 0x00000000 /* DENALI_PHY_255_DATA */
+ 0x46052371 /* DENALI_PHY_256_DATA */
+ 0x0004c008 /* DENALI_PHY_257_DATA */
+ 0x000000da /* DENALI_PHY_258_DATA */
+ 0x00000000 /* DENALI_PHY_259_DATA */
+ 0x00000000 /* DENALI_PHY_260_DATA */
+ 0x00010000 /* DENALI_PHY_261_DATA */
+ 0x01DDDD90 /* DENALI_PHY_262_DATA */
+ 0x01DDDD90 /* DENALI_PHY_263_DATA */
+ 0x01030000 /* DENALI_PHY_264_DATA */
+ 0x01000000 /* DENALI_PHY_265_DATA */
+ 0x00c00000 /* DENALI_PHY_266_DATA */
+ 0x00000007 /* DENALI_PHY_267_DATA */
+ 0x00000000 /* DENALI_PHY_268_DATA */
+ 0x00000000 /* DENALI_PHY_269_DATA */
+ 0x04000408 /* DENALI_PHY_270_DATA */
+ 0x00000408 /* DENALI_PHY_271_DATA */
+ 0x00e4e400 /* DENALI_PHY_272_DATA */
+ 0x00000000 /* DENALI_PHY_273_DATA */
+ 0x00000000 /* DENALI_PHY_274_DATA */
+ 0x00000000 /* DENALI_PHY_275_DATA */
+ 0x00000000 /* DENALI_PHY_276_DATA */
+ 0x00000000 /* DENALI_PHY_277_DATA */
+ 0x00000000 /* DENALI_PHY_278_DATA */
+ 0x00000000 /* DENALI_PHY_279_DATA */
+ 0x00000000 /* DENALI_PHY_280_DATA */
+ 0x00000000 /* DENALI_PHY_281_DATA */
+ 0x00000000 /* DENALI_PHY_282_DATA */
+ 0x00000000 /* DENALI_PHY_283_DATA */
+ 0x00000000 /* DENALI_PHY_284_DATA */
+ 0x00000000 /* DENALI_PHY_285_DATA */
+ 0x00000000 /* DENALI_PHY_286_DATA */
+ 0x00000000 /* DENALI_PHY_287_DATA */
+ 0x00000000 /* DENALI_PHY_288_DATA */
+ 0x00200000 /* DENALI_PHY_289_DATA */
+ 0x00000000 /* DENALI_PHY_290_DATA */
+ 0x00000000 /* DENALI_PHY_291_DATA */
+ 0x00000000 /* DENALI_PHY_292_DATA */
+ 0x00000000 /* DENALI_PHY_293_DATA */
+ 0x00000000 /* DENALI_PHY_294_DATA */
+ 0x00000000 /* DENALI_PHY_295_DATA */
+ 0x02800280 /* DENALI_PHY_296_DATA */
+ 0x02800280 /* DENALI_PHY_297_DATA */
+ 0x02800280 /* DENALI_PHY_298_DATA */
+ 0x02800280 /* DENALI_PHY_299_DATA */
+ 0x00000280 /* DENALI_PHY_300_DATA */
+ 0x00000000 /* DENALI_PHY_301_DATA */
+ 0x00000000 /* DENALI_PHY_302_DATA */
+ 0x00000000 /* DENALI_PHY_303_DATA */
+ 0x00000000 /* DENALI_PHY_304_DATA */
+ 0x00000000 /* DENALI_PHY_305_DATA */
+ 0x00800080 /* DENALI_PHY_306_DATA */
+ 0x00800080 /* DENALI_PHY_307_DATA */
+ 0x00800080 /* DENALI_PHY_308_DATA */
+ 0x00800080 /* DENALI_PHY_309_DATA */
+ 0x00800080 /* DENALI_PHY_310_DATA */
+ 0x00800080 /* DENALI_PHY_311_DATA */
+ 0x00800080 /* DENALI_PHY_312_DATA */
+ 0x00800080 /* DENALI_PHY_313_DATA */
+ 0x00800080 /* DENALI_PHY_314_DATA */
+ 0x000100da /* DENALI_PHY_315_DATA */
+ 0x00000200 /* DENALI_PHY_316_DATA */
+ 0x00000000 /* DENALI_PHY_317_DATA */
+ 0x00000000 /* DENALI_PHY_318_DATA */
+ 0x00000002 /* DENALI_PHY_319_DATA */
+ 0x51313152 /* DENALI_PHY_320_DATA */
+ 0x80013130 /* DENALI_PHY_321_DATA */
+ 0x02000080 /* DENALI_PHY_322_DATA */
+ 0x00100001 /* DENALI_PHY_323_DATA */
+ 0x0c064208 /* DENALI_PHY_324_DATA */
+ 0x000f0c0f /* DENALI_PHY_325_DATA */
+ 0x01000140 /* DENALI_PHY_326_DATA */
+ 0x0000000c /* DENALI_PHY_327_DATA */
+ 0x00000000 /* DENALI_PHY_328_DATA */
+ 0x00000000 /* DENALI_PHY_329_DATA */
+ 0x00000000 /* DENALI_PHY_330_DATA */
+ 0x00000000 /* DENALI_PHY_331_DATA */
+ 0x00000000 /* DENALI_PHY_332_DATA */
+ 0x00000000 /* DENALI_PHY_333_DATA */
+ 0x00000000 /* DENALI_PHY_334_DATA */
+ 0x00000000 /* DENALI_PHY_335_DATA */
+ 0x00000000 /* DENALI_PHY_336_DATA */
+ 0x00000000 /* DENALI_PHY_337_DATA */
+ 0x00000000 /* DENALI_PHY_338_DATA */
+ 0x00000000 /* DENALI_PHY_339_DATA */
+ 0x00000000 /* DENALI_PHY_340_DATA */
+ 0x00000000 /* DENALI_PHY_341_DATA */
+ 0x00000000 /* DENALI_PHY_342_DATA */
+ 0x00000000 /* DENALI_PHY_343_DATA */
+ 0x00000000 /* DENALI_PHY_344_DATA */
+ 0x00000000 /* DENALI_PHY_345_DATA */
+ 0x00000000 /* DENALI_PHY_346_DATA */
+ 0x00000000 /* DENALI_PHY_347_DATA */
+ 0x00000000 /* DENALI_PHY_348_DATA */
+ 0x00000000 /* DENALI_PHY_349_DATA */
+ 0x00000000 /* DENALI_PHY_350_DATA */
+ 0x00000000 /* DENALI_PHY_351_DATA */
+ 0x00000000 /* DENALI_PHY_352_DATA */
+ 0x00000000 /* DENALI_PHY_353_DATA */
+ 0x00000000 /* DENALI_PHY_354_DATA */
+ 0x00000000 /* DENALI_PHY_355_DATA */
+ 0x00000000 /* DENALI_PHY_356_DATA */
+ 0x00000000 /* DENALI_PHY_357_DATA */
+ 0x00000000 /* DENALI_PHY_358_DATA */
+ 0x00000000 /* DENALI_PHY_359_DATA */
+ 0x00000000 /* DENALI_PHY_360_DATA */
+ 0x00000000 /* DENALI_PHY_361_DATA */
+ 0x00000000 /* DENALI_PHY_362_DATA */
+ 0x00000000 /* DENALI_PHY_363_DATA */
+ 0x00000000 /* DENALI_PHY_364_DATA */
+ 0x00000000 /* DENALI_PHY_365_DATA */
+ 0x00000000 /* DENALI_PHY_366_DATA */
+ 0x00000000 /* DENALI_PHY_367_DATA */
+ 0x00000000 /* DENALI_PHY_368_DATA */
+ 0x00000000 /* DENALI_PHY_369_DATA */
+ 0x00000000 /* DENALI_PHY_370_DATA */
+ 0x00000000 /* DENALI_PHY_371_DATA */
+ 0x00000000 /* DENALI_PHY_372_DATA */
+ 0x00000000 /* DENALI_PHY_373_DATA */
+ 0x00000000 /* DENALI_PHY_374_DATA */
+ 0x00000000 /* DENALI_PHY_375_DATA */
+ 0x00000000 /* DENALI_PHY_376_DATA */
+ 0x00000000 /* DENALI_PHY_377_DATA */
+ 0x00000000 /* DENALI_PHY_378_DATA */
+ 0x00000000 /* DENALI_PHY_379_DATA */
+ 0x00000000 /* DENALI_PHY_380_DATA */
+ 0x00000000 /* DENALI_PHY_381_DATA */
+ 0x00000000 /* DENALI_PHY_382_DATA */
+ 0x00000000 /* DENALI_PHY_383_DATA */
+ 0x37654120 /* DENALI_PHY_384_DATA */
+ 0x0004c008 /* DENALI_PHY_385_DATA */
+ 0x000000da /* DENALI_PHY_386_DATA */
+ 0x00000000 /* DENALI_PHY_387_DATA */
+ 0x00000000 /* DENALI_PHY_388_DATA */
+ 0x00010000 /* DENALI_PHY_389_DATA */
+ 0x01DDDD90 /* DENALI_PHY_390_DATA */
+ 0x01DDDD90 /* DENALI_PHY_391_DATA */
+ 0x01030000 /* DENALI_PHY_392_DATA */
+ 0x01000000 /* DENALI_PHY_393_DATA */
+ 0x00c00000 /* DENALI_PHY_394_DATA */
+ 0x00000007 /* DENALI_PHY_395_DATA */
+ 0x00000000 /* DENALI_PHY_396_DATA */
+ 0x00000000 /* DENALI_PHY_397_DATA */
+ 0x04000408 /* DENALI_PHY_398_DATA */
+ 0x00000408 /* DENALI_PHY_399_DATA */
+ 0x00e4e400 /* DENALI_PHY_400_DATA */
+ 0x00000000 /* DENALI_PHY_401_DATA */
+ 0x00000000 /* DENALI_PHY_402_DATA */
+ 0x00000000 /* DENALI_PHY_403_DATA */
+ 0x00000000 /* DENALI_PHY_404_DATA */
+ 0x00000000 /* DENALI_PHY_405_DATA */
+ 0x00000000 /* DENALI_PHY_406_DATA */
+ 0x00000000 /* DENALI_PHY_407_DATA */
+ 0x00000000 /* DENALI_PHY_408_DATA */
+ 0x00000000 /* DENALI_PHY_409_DATA */
+ 0x00000000 /* DENALI_PHY_410_DATA */
+ 0x00000000 /* DENALI_PHY_411_DATA */
+ 0x00000000 /* DENALI_PHY_412_DATA */
+ 0x00000000 /* DENALI_PHY_413_DATA */
+ 0x00000000 /* DENALI_PHY_414_DATA */
+ 0x00000000 /* DENALI_PHY_415_DATA */
+ 0x00000000 /* DENALI_PHY_416_DATA */
+ 0x00200000 /* DENALI_PHY_417_DATA */
+ 0x00000000 /* DENALI_PHY_418_DATA */
+ 0x00000000 /* DENALI_PHY_419_DATA */
+ 0x00000000 /* DENALI_PHY_420_DATA */
+ 0x00000000 /* DENALI_PHY_421_DATA */
+ 0x00000000 /* DENALI_PHY_422_DATA */
+ 0x00000000 /* DENALI_PHY_423_DATA */
+ 0x02800280 /* DENALI_PHY_424_DATA */
+ 0x02800280 /* DENALI_PHY_425_DATA */
+ 0x02800280 /* DENALI_PHY_426_DATA */
+ 0x02800280 /* DENALI_PHY_427_DATA */
+ 0x00000280 /* DENALI_PHY_428_DATA */
+ 0x00000000 /* DENALI_PHY_429_DATA */
+ 0x00000000 /* DENALI_PHY_430_DATA */
+ 0x00000000 /* DENALI_PHY_431_DATA */
+ 0x00000000 /* DENALI_PHY_432_DATA */
+ 0x00000000 /* DENALI_PHY_433_DATA */
+ 0x00800080 /* DENALI_PHY_434_DATA */
+ 0x00800080 /* DENALI_PHY_435_DATA */
+ 0x00800080 /* DENALI_PHY_436_DATA */
+ 0x00800080 /* DENALI_PHY_437_DATA */
+ 0x00800080 /* DENALI_PHY_438_DATA */
+ 0x00800080 /* DENALI_PHY_439_DATA */
+ 0x00800080 /* DENALI_PHY_440_DATA */
+ 0x00800080 /* DENALI_PHY_441_DATA */
+ 0x00800080 /* DENALI_PHY_442_DATA */
+ 0x000100da /* DENALI_PHY_443_DATA */
+ 0x00000200 /* DENALI_PHY_444_DATA */
+ 0x00000000 /* DENALI_PHY_445_DATA */
+ 0x00000000 /* DENALI_PHY_446_DATA */
+ 0x00000002 /* DENALI_PHY_447_DATA */
+ 0x51313152 /* DENALI_PHY_448_DATA */
+ 0x80013130 /* DENALI_PHY_449_DATA */
+ 0x02000080 /* DENALI_PHY_450_DATA */
+ 0x00100001 /* DENALI_PHY_451_DATA */
+ 0x0c064208 /* DENALI_PHY_452_DATA */
+ 0x000f0c0f /* DENALI_PHY_453_DATA */
+ 0x01000140 /* DENALI_PHY_454_DATA */
+ 0x0000000c /* DENALI_PHY_455_DATA */
+ 0x00000000 /* DENALI_PHY_456_DATA */
+ 0x00000000 /* DENALI_PHY_457_DATA */
+ 0x00000000 /* DENALI_PHY_458_DATA */
+ 0x00000000 /* DENALI_PHY_459_DATA */
+ 0x00000000 /* DENALI_PHY_460_DATA */
+ 0x00000000 /* DENALI_PHY_461_DATA */
+ 0x00000000 /* DENALI_PHY_462_DATA */
+ 0x00000000 /* DENALI_PHY_463_DATA */
+ 0x00000000 /* DENALI_PHY_464_DATA */
+ 0x00000000 /* DENALI_PHY_465_DATA */
+ 0x00000000 /* DENALI_PHY_466_DATA */
+ 0x00000000 /* DENALI_PHY_467_DATA */
+ 0x00000000 /* DENALI_PHY_468_DATA */
+ 0x00000000 /* DENALI_PHY_469_DATA */
+ 0x00000000 /* DENALI_PHY_470_DATA */
+ 0x00000000 /* DENALI_PHY_471_DATA */
+ 0x00000000 /* DENALI_PHY_472_DATA */
+ 0x00000000 /* DENALI_PHY_473_DATA */
+ 0x00000000 /* DENALI_PHY_474_DATA */
+ 0x00000000 /* DENALI_PHY_475_DATA */
+ 0x00000000 /* DENALI_PHY_476_DATA */
+ 0x00000000 /* DENALI_PHY_477_DATA */
+ 0x00000000 /* DENALI_PHY_478_DATA */
+ 0x00000000 /* DENALI_PHY_479_DATA */
+ 0x00000000 /* DENALI_PHY_480_DATA */
+ 0x00000000 /* DENALI_PHY_481_DATA */
+ 0x00000000 /* DENALI_PHY_482_DATA */
+ 0x00000000 /* DENALI_PHY_483_DATA */
+ 0x00000000 /* DENALI_PHY_484_DATA */
+ 0x00000000 /* DENALI_PHY_485_DATA */
+ 0x00000000 /* DENALI_PHY_486_DATA */
+ 0x00000000 /* DENALI_PHY_487_DATA */
+ 0x00000000 /* DENALI_PHY_488_DATA */
+ 0x00000000 /* DENALI_PHY_489_DATA */
+ 0x00000000 /* DENALI_PHY_490_DATA */
+ 0x00000000 /* DENALI_PHY_491_DATA */
+ 0x00000000 /* DENALI_PHY_492_DATA */
+ 0x00000000 /* DENALI_PHY_493_DATA */
+ 0x00000000 /* DENALI_PHY_494_DATA */
+ 0x00000000 /* DENALI_PHY_495_DATA */
+ 0x00000000 /* DENALI_PHY_496_DATA */
+ 0x00000000 /* DENALI_PHY_497_DATA */
+ 0x00000000 /* DENALI_PHY_498_DATA */
+ 0x00000000 /* DENALI_PHY_499_DATA */
+ 0x00000000 /* DENALI_PHY_500_DATA */
+ 0x00000000 /* DENALI_PHY_501_DATA */
+ 0x00000000 /* DENALI_PHY_502_DATA */
+ 0x00000000 /* DENALI_PHY_503_DATA */
+ 0x00000000 /* DENALI_PHY_504_DATA */
+ 0x00000000 /* DENALI_PHY_505_DATA */
+ 0x00000000 /* DENALI_PHY_506_DATA */
+ 0x00000000 /* DENALI_PHY_507_DATA */
+ 0x00000000 /* DENALI_PHY_508_DATA */
+ 0x00000000 /* DENALI_PHY_509_DATA */
+ 0x00000000 /* DENALI_PHY_510_DATA */
+ 0x00000000 /* DENALI_PHY_511_DATA */
+ 0x24316750 /* DENALI_PHY_512_DATA */
+ 0x0004c008 /* DENALI_PHY_513_DATA */
+ 0x000000da /* DENALI_PHY_514_DATA */
+ 0x00000000 /* DENALI_PHY_515_DATA */
+ 0x00000000 /* DENALI_PHY_516_DATA */
+ 0x00010000 /* DENALI_PHY_517_DATA */
+ 0x01DDDD90 /* DENALI_PHY_518_DATA */
+ 0x01DDDD90 /* DENALI_PHY_519_DATA */
+ 0x01030000 /* DENALI_PHY_520_DATA */
+ 0x01000000 /* DENALI_PHY_521_DATA */
+ 0x00c00000 /* DENALI_PHY_522_DATA */
+ 0x00000007 /* DENALI_PHY_523_DATA */
+ 0x00000000 /* DENALI_PHY_524_DATA */
+ 0x00000000 /* DENALI_PHY_525_DATA */
+ 0x04000408 /* DENALI_PHY_526_DATA */
+ 0x00000408 /* DENALI_PHY_527_DATA */
+ 0x00e4e400 /* DENALI_PHY_528_DATA */
+ 0x00000000 /* DENALI_PHY_529_DATA */
+ 0x00000000 /* DENALI_PHY_530_DATA */
+ 0x00000000 /* DENALI_PHY_531_DATA */
+ 0x00000000 /* DENALI_PHY_532_DATA */
+ 0x00000000 /* DENALI_PHY_533_DATA */
+ 0x00000000 /* DENALI_PHY_534_DATA */
+ 0x00000000 /* DENALI_PHY_535_DATA */
+ 0x00000000 /* DENALI_PHY_536_DATA */
+ 0x00000000 /* DENALI_PHY_537_DATA */
+ 0x00000000 /* DENALI_PHY_538_DATA */
+ 0x00000000 /* DENALI_PHY_539_DATA */
+ 0x00000000 /* DENALI_PHY_540_DATA */
+ 0x00000000 /* DENALI_PHY_541_DATA */
+ 0x00000000 /* DENALI_PHY_542_DATA */
+ 0x00000000 /* DENALI_PHY_543_DATA */
+ 0x00000000 /* DENALI_PHY_544_DATA */
+ 0x00200000 /* DENALI_PHY_545_DATA */
+ 0x00000000 /* DENALI_PHY_546_DATA */
+ 0x00000000 /* DENALI_PHY_547_DATA */
+ 0x00000000 /* DENALI_PHY_548_DATA */
+ 0x00000000 /* DENALI_PHY_549_DATA */
+ 0x00000000 /* DENALI_PHY_550_DATA */
+ 0x00000000 /* DENALI_PHY_551_DATA */
+ 0x02800280 /* DENALI_PHY_552_DATA */
+ 0x02800280 /* DENALI_PHY_553_DATA */
+ 0x02800280 /* DENALI_PHY_554_DATA */
+ 0x02800280 /* DENALI_PHY_555_DATA */
+ 0x00000280 /* DENALI_PHY_556_DATA */
+ 0x00000000 /* DENALI_PHY_557_DATA */
+ 0x00000000 /* DENALI_PHY_558_DATA */
+ 0x00000000 /* DENALI_PHY_559_DATA */
+ 0x00000000 /* DENALI_PHY_560_DATA */
+ 0x00000000 /* DENALI_PHY_561_DATA */
+ 0x00800080 /* DENALI_PHY_562_DATA */
+ 0x00800080 /* DENALI_PHY_563_DATA */
+ 0x00800080 /* DENALI_PHY_564_DATA */
+ 0x00800080 /* DENALI_PHY_565_DATA */
+ 0x00800080 /* DENALI_PHY_566_DATA */
+ 0x00800080 /* DENALI_PHY_567_DATA */
+ 0x00800080 /* DENALI_PHY_568_DATA */
+ 0x00800080 /* DENALI_PHY_569_DATA */
+ 0x00800080 /* DENALI_PHY_570_DATA */
+ 0x000100da /* DENALI_PHY_571_DATA */
+ 0x00000200 /* DENALI_PHY_572_DATA */
+ 0x00000000 /* DENALI_PHY_573_DATA */
+ 0x00000000 /* DENALI_PHY_574_DATA */
+ 0x00000002 /* DENALI_PHY_575_DATA */
+ 0x51313152 /* DENALI_PHY_576_DATA */
+ 0x80013130 /* DENALI_PHY_577_DATA */
+ 0x02000080 /* DENALI_PHY_578_DATA */
+ 0x00100001 /* DENALI_PHY_579_DATA */
+ 0x0c064208 /* DENALI_PHY_580_DATA */
+ 0x000f0c0f /* DENALI_PHY_581_DATA */
+ 0x01000140 /* DENALI_PHY_582_DATA */
+ 0x0000000c /* DENALI_PHY_583_DATA */
+ 0x00000000 /* DENALI_PHY_584_DATA */
+ 0x00000000 /* DENALI_PHY_585_DATA */
+ 0x00000000 /* DENALI_PHY_586_DATA */
+ 0x00000000 /* DENALI_PHY_587_DATA */
+ 0x00000000 /* DENALI_PHY_588_DATA */
+ 0x00000000 /* DENALI_PHY_589_DATA */
+ 0x00000000 /* DENALI_PHY_590_DATA */
+ 0x00000000 /* DENALI_PHY_591_DATA */
+ 0x00000000 /* DENALI_PHY_592_DATA */
+ 0x00000000 /* DENALI_PHY_593_DATA */
+ 0x00000000 /* DENALI_PHY_594_DATA */
+ 0x00000000 /* DENALI_PHY_595_DATA */
+ 0x00000000 /* DENALI_PHY_596_DATA */
+ 0x00000000 /* DENALI_PHY_597_DATA */
+ 0x00000000 /* DENALI_PHY_598_DATA */
+ 0x00000000 /* DENALI_PHY_599_DATA */
+ 0x00000000 /* DENALI_PHY_600_DATA */
+ 0x00000000 /* DENALI_PHY_601_DATA */
+ 0x00000000 /* DENALI_PHY_602_DATA */
+ 0x00000000 /* DENALI_PHY_603_DATA */
+ 0x00000000 /* DENALI_PHY_604_DATA */
+ 0x00000000 /* DENALI_PHY_605_DATA */
+ 0x00000000 /* DENALI_PHY_606_DATA */
+ 0x00000000 /* DENALI_PHY_607_DATA */
+ 0x00000000 /* DENALI_PHY_608_DATA */
+ 0x00000000 /* DENALI_PHY_609_DATA */
+ 0x00000000 /* DENALI_PHY_610_DATA */
+ 0x00000000 /* DENALI_PHY_611_DATA */
+ 0x00000000 /* DENALI_PHY_612_DATA */
+ 0x00000000 /* DENALI_PHY_613_DATA */
+ 0x00000000 /* DENALI_PHY_614_DATA */
+ 0x00000000 /* DENALI_PHY_615_DATA */
+ 0x00000000 /* DENALI_PHY_616_DATA */
+ 0x00000000 /* DENALI_PHY_617_DATA */
+ 0x00000000 /* DENALI_PHY_618_DATA */
+ 0x00000000 /* DENALI_PHY_619_DATA */
+ 0x00000000 /* DENALI_PHY_620_DATA */
+ 0x00000000 /* DENALI_PHY_621_DATA */
+ 0x00000000 /* DENALI_PHY_622_DATA */
+ 0x00000000 /* DENALI_PHY_623_DATA */
+ 0x00000000 /* DENALI_PHY_624_DATA */
+ 0x00000000 /* DENALI_PHY_625_DATA */
+ 0x00000000 /* DENALI_PHY_626_DATA */
+ 0x00000000 /* DENALI_PHY_627_DATA */
+ 0x00000000 /* DENALI_PHY_628_DATA */
+ 0x00000000 /* DENALI_PHY_629_DATA */
+ 0x00000000 /* DENALI_PHY_630_DATA */
+ 0x00000000 /* DENALI_PHY_631_DATA */
+ 0x00000000 /* DENALI_PHY_632_DATA */
+ 0x00000000 /* DENALI_PHY_633_DATA */
+ 0x00000000 /* DENALI_PHY_634_DATA */
+ 0x00000000 /* DENALI_PHY_635_DATA */
+ 0x00000000 /* DENALI_PHY_636_DATA */
+ 0x00000000 /* DENALI_PHY_637_DATA */
+ 0x00000000 /* DENALI_PHY_638_DATA */
+ 0x00000000 /* DENALI_PHY_639_DATA */
+ 0x35174620 /* DENALI_PHY_640_DATA */
+ 0x0004c008 /* DENALI_PHY_641_DATA */
+ 0x000000da /* DENALI_PHY_642_DATA */
+ 0x00000000 /* DENALI_PHY_643_DATA */
+ 0x00000000 /* DENALI_PHY_644_DATA */
+ 0x00010000 /* DENALI_PHY_645_DATA */
+ 0x01DDDD90 /* DENALI_PHY_646_DATA */
+ 0x01DDDD90 /* DENALI_PHY_647_DATA */
+ 0x01030000 /* DENALI_PHY_648_DATA */
+ 0x01000000 /* DENALI_PHY_649_DATA */
+ 0x00c00000 /* DENALI_PHY_650_DATA */
+ 0x00000007 /* DENALI_PHY_651_DATA */
+ 0x00000000 /* DENALI_PHY_652_DATA */
+ 0x00000000 /* DENALI_PHY_653_DATA */
+ 0x04000408 /* DENALI_PHY_654_DATA */
+ 0x00000408 /* DENALI_PHY_655_DATA */
+ 0x00e4e400 /* DENALI_PHY_656_DATA */
+ 0x00000000 /* DENALI_PHY_657_DATA */
+ 0x00000000 /* DENALI_PHY_658_DATA */
+ 0x00000000 /* DENALI_PHY_659_DATA */
+ 0x00000000 /* DENALI_PHY_660_DATA */
+ 0x00000000 /* DENALI_PHY_661_DATA */
+ 0x00000000 /* DENALI_PHY_662_DATA */
+ 0x00000000 /* DENALI_PHY_663_DATA */
+ 0x00000000 /* DENALI_PHY_664_DATA */
+ 0x00000000 /* DENALI_PHY_665_DATA */
+ 0x00000000 /* DENALI_PHY_666_DATA */
+ 0x00000000 /* DENALI_PHY_667_DATA */
+ 0x00000000 /* DENALI_PHY_668_DATA */
+ 0x00000000 /* DENALI_PHY_669_DATA */
+ 0x00000000 /* DENALI_PHY_670_DATA */
+ 0x00000000 /* DENALI_PHY_671_DATA */
+ 0x00000000 /* DENALI_PHY_672_DATA */
+ 0x00200000 /* DENALI_PHY_673_DATA */
+ 0x00000000 /* DENALI_PHY_674_DATA */
+ 0x00000000 /* DENALI_PHY_675_DATA */
+ 0x00000000 /* DENALI_PHY_676_DATA */
+ 0x00000000 /* DENALI_PHY_677_DATA */
+ 0x00000000 /* DENALI_PHY_678_DATA */
+ 0x00000000 /* DENALI_PHY_679_DATA */
+ 0x02800280 /* DENALI_PHY_680_DATA */
+ 0x02800280 /* DENALI_PHY_681_DATA */
+ 0x02800280 /* DENALI_PHY_682_DATA */
+ 0x02800280 /* DENALI_PHY_683_DATA */
+ 0x00000280 /* DENALI_PHY_684_DATA */
+ 0x00000000 /* DENALI_PHY_685_DATA */
+ 0x00000000 /* DENALI_PHY_686_DATA */
+ 0x00000000 /* DENALI_PHY_687_DATA */
+ 0x00000000 /* DENALI_PHY_688_DATA */
+ 0x00000000 /* DENALI_PHY_689_DATA */
+ 0x00800080 /* DENALI_PHY_690_DATA */
+ 0x00800080 /* DENALI_PHY_691_DATA */
+ 0x00800080 /* DENALI_PHY_692_DATA */
+ 0x00800080 /* DENALI_PHY_693_DATA */
+ 0x00800080 /* DENALI_PHY_694_DATA */
+ 0x00800080 /* DENALI_PHY_695_DATA */
+ 0x00800080 /* DENALI_PHY_696_DATA */
+ 0x00800080 /* DENALI_PHY_697_DATA */
+ 0x00800080 /* DENALI_PHY_698_DATA */
+ 0x000100da /* DENALI_PHY_699_DATA */
+ 0x00000200 /* DENALI_PHY_700_DATA */
+ 0x00000000 /* DENALI_PHY_701_DATA */
+ 0x00000000 /* DENALI_PHY_702_DATA */
+ 0x00000002 /* DENALI_PHY_703_DATA */
+ 0x51313152 /* DENALI_PHY_704_DATA */
+ 0x80013130 /* DENALI_PHY_705_DATA */
+ 0x02000080 /* DENALI_PHY_706_DATA */
+ 0x00100001 /* DENALI_PHY_707_DATA */
+ 0x0c064208 /* DENALI_PHY_708_DATA */
+ 0x000f0c0f /* DENALI_PHY_709_DATA */
+ 0x01000140 /* DENALI_PHY_710_DATA */
+ 0x0000000c /* DENALI_PHY_711_DATA */
+ 0x00000000 /* DENALI_PHY_712_DATA */
+ 0x00000000 /* DENALI_PHY_713_DATA */
+ 0x00000000 /* DENALI_PHY_714_DATA */
+ 0x00000000 /* DENALI_PHY_715_DATA */
+ 0x00000000 /* DENALI_PHY_716_DATA */
+ 0x00000000 /* DENALI_PHY_717_DATA */
+ 0x00000000 /* DENALI_PHY_718_DATA */
+ 0x00000000 /* DENALI_PHY_719_DATA */
+ 0x00000000 /* DENALI_PHY_720_DATA */
+ 0x00000000 /* DENALI_PHY_721_DATA */
+ 0x00000000 /* DENALI_PHY_722_DATA */
+ 0x00000000 /* DENALI_PHY_723_DATA */
+ 0x00000000 /* DENALI_PHY_724_DATA */
+ 0x00000000 /* DENALI_PHY_725_DATA */
+ 0x00000000 /* DENALI_PHY_726_DATA */
+ 0x00000000 /* DENALI_PHY_727_DATA */
+ 0x00000000 /* DENALI_PHY_728_DATA */
+ 0x00000000 /* DENALI_PHY_729_DATA */
+ 0x00000000 /* DENALI_PHY_730_DATA */
+ 0x00000000 /* DENALI_PHY_731_DATA */
+ 0x00000000 /* DENALI_PHY_732_DATA */
+ 0x00000000 /* DENALI_PHY_733_DATA */
+ 0x00000000 /* DENALI_PHY_734_DATA */
+ 0x00000000 /* DENALI_PHY_735_DATA */
+ 0x00000000 /* DENALI_PHY_736_DATA */
+ 0x00000000 /* DENALI_PHY_737_DATA */
+ 0x00000000 /* DENALI_PHY_738_DATA */
+ 0x00000000 /* DENALI_PHY_739_DATA */
+ 0x00000000 /* DENALI_PHY_740_DATA */
+ 0x00000000 /* DENALI_PHY_741_DATA */
+ 0x00000000 /* DENALI_PHY_742_DATA */
+ 0x00000000 /* DENALI_PHY_743_DATA */
+ 0x00000000 /* DENALI_PHY_744_DATA */
+ 0x00000000 /* DENALI_PHY_745_DATA */
+ 0x00000000 /* DENALI_PHY_746_DATA */
+ 0x00000000 /* DENALI_PHY_747_DATA */
+ 0x00000000 /* DENALI_PHY_748_DATA */
+ 0x00000000 /* DENALI_PHY_749_DATA */
+ 0x00000000 /* DENALI_PHY_750_DATA */
+ 0x00000000 /* DENALI_PHY_751_DATA */
+ 0x00000000 /* DENALI_PHY_752_DATA */
+ 0x00000000 /* DENALI_PHY_753_DATA */
+ 0x00000000 /* DENALI_PHY_754_DATA */
+ 0x00000000 /* DENALI_PHY_755_DATA */
+ 0x00000000 /* DENALI_PHY_756_DATA */
+ 0x00000000 /* DENALI_PHY_757_DATA */
+ 0x00000000 /* DENALI_PHY_758_DATA */
+ 0x00000000 /* DENALI_PHY_759_DATA */
+ 0x00000000 /* DENALI_PHY_760_DATA */
+ 0x00000000 /* DENALI_PHY_761_DATA */
+ 0x00000000 /* DENALI_PHY_762_DATA */
+ 0x00000000 /* DENALI_PHY_763_DATA */
+ 0x00000000 /* DENALI_PHY_764_DATA */
+ 0x00000000 /* DENALI_PHY_765_DATA */
+ 0x00000000 /* DENALI_PHY_766_DATA */
+ 0x00000000 /* DENALI_PHY_767_DATA */
+ 0x15203476 /* DENALI_PHY_768_DATA */
+ 0x0004c008 /* DENALI_PHY_769_DATA */
+ 0x000000da /* DENALI_PHY_770_DATA */
+ 0x00000000 /* DENALI_PHY_771_DATA */
+ 0x00000000 /* DENALI_PHY_772_DATA */
+ 0x00010000 /* DENALI_PHY_773_DATA */
+ 0x01DDDD90 /* DENALI_PHY_774_DATA */
+ 0x01DDDD90 /* DENALI_PHY_775_DATA */
+ 0x01030000 /* DENALI_PHY_776_DATA */
+ 0x01000000 /* DENALI_PHY_777_DATA */
+ 0x00c00000 /* DENALI_PHY_778_DATA */
+ 0x00000007 /* DENALI_PHY_779_DATA */
+ 0x00000000 /* DENALI_PHY_780_DATA */
+ 0x00000000 /* DENALI_PHY_781_DATA */
+ 0x04000408 /* DENALI_PHY_782_DATA */
+ 0x00000408 /* DENALI_PHY_783_DATA */
+ 0x00e4e400 /* DENALI_PHY_784_DATA */
+ 0x00000000 /* DENALI_PHY_785_DATA */
+ 0x00000000 /* DENALI_PHY_786_DATA */
+ 0x00000000 /* DENALI_PHY_787_DATA */
+ 0x00000000 /* DENALI_PHY_788_DATA */
+ 0x00000000 /* DENALI_PHY_789_DATA */
+ 0x00000000 /* DENALI_PHY_790_DATA */
+ 0x00000000 /* DENALI_PHY_791_DATA */
+ 0x00000000 /* DENALI_PHY_792_DATA */
+ 0x00000000 /* DENALI_PHY_793_DATA */
+ 0x00000000 /* DENALI_PHY_794_DATA */
+ 0x00000000 /* DENALI_PHY_795_DATA */
+ 0x00000000 /* DENALI_PHY_796_DATA */
+ 0x00000000 /* DENALI_PHY_797_DATA */
+ 0x00000000 /* DENALI_PHY_798_DATA */
+ 0x00000000 /* DENALI_PHY_799_DATA */
+ 0x00000000 /* DENALI_PHY_800_DATA */
+ 0x00200000 /* DENALI_PHY_801_DATA */
+ 0x00000000 /* DENALI_PHY_802_DATA */
+ 0x00000000 /* DENALI_PHY_803_DATA */
+ 0x00000000 /* DENALI_PHY_804_DATA */
+ 0x00000000 /* DENALI_PHY_805_DATA */
+ 0x00000000 /* DENALI_PHY_806_DATA */
+ 0x00000000 /* DENALI_PHY_807_DATA */
+ 0x02800280 /* DENALI_PHY_808_DATA */
+ 0x02800280 /* DENALI_PHY_809_DATA */
+ 0x02800280 /* DENALI_PHY_810_DATA */
+ 0x02800280 /* DENALI_PHY_811_DATA */
+ 0x00000280 /* DENALI_PHY_812_DATA */
+ 0x00000000 /* DENALI_PHY_813_DATA */
+ 0x00000000 /* DENALI_PHY_814_DATA */
+ 0x00000000 /* DENALI_PHY_815_DATA */
+ 0x00000000 /* DENALI_PHY_816_DATA */
+ 0x00000000 /* DENALI_PHY_817_DATA */
+ 0x00800080 /* DENALI_PHY_818_DATA */
+ 0x00800080 /* DENALI_PHY_819_DATA */
+ 0x00800080 /* DENALI_PHY_820_DATA */
+ 0x00800080 /* DENALI_PHY_821_DATA */
+ 0x00800080 /* DENALI_PHY_822_DATA */
+ 0x00800080 /* DENALI_PHY_823_DATA */
+ 0x00800080 /* DENALI_PHY_824_DATA */
+ 0x00800080 /* DENALI_PHY_825_DATA */
+ 0x00800080 /* DENALI_PHY_826_DATA */
+ 0x000100da /* DENALI_PHY_827_DATA */
+ 0x00000200 /* DENALI_PHY_828_DATA */
+ 0x00000000 /* DENALI_PHY_829_DATA */
+ 0x00000000 /* DENALI_PHY_830_DATA */
+ 0x00000002 /* DENALI_PHY_831_DATA */
+ 0x51313152 /* DENALI_PHY_832_DATA */
+ 0x80013130 /* DENALI_PHY_833_DATA */
+ 0x02000080 /* DENALI_PHY_834_DATA */
+ 0x00100001 /* DENALI_PHY_835_DATA */
+ 0x0c064208 /* DENALI_PHY_836_DATA */
+ 0x000f0c0f /* DENALI_PHY_837_DATA */
+ 0x01000140 /* DENALI_PHY_838_DATA */
+ 0x0000000c /* DENALI_PHY_839_DATA */
+ 0x00000000 /* DENALI_PHY_840_DATA */
+ 0x00000000 /* DENALI_PHY_841_DATA */
+ 0x00000000 /* DENALI_PHY_842_DATA */
+ 0x00000000 /* DENALI_PHY_843_DATA */
+ 0x00000000 /* DENALI_PHY_844_DATA */
+ 0x00000000 /* DENALI_PHY_845_DATA */
+ 0x00000000 /* DENALI_PHY_846_DATA */
+ 0x00000000 /* DENALI_PHY_847_DATA */
+ 0x00000000 /* DENALI_PHY_848_DATA */
+ 0x00000000 /* DENALI_PHY_849_DATA */
+ 0x00000000 /* DENALI_PHY_850_DATA */
+ 0x00000000 /* DENALI_PHY_851_DATA */
+ 0x00000000 /* DENALI_PHY_852_DATA */
+ 0x00000000 /* DENALI_PHY_853_DATA */
+ 0x00000000 /* DENALI_PHY_854_DATA */
+ 0x00000000 /* DENALI_PHY_855_DATA */
+ 0x00000000 /* DENALI_PHY_856_DATA */
+ 0x00000000 /* DENALI_PHY_857_DATA */
+ 0x00000000 /* DENALI_PHY_858_DATA */
+ 0x00000000 /* DENALI_PHY_859_DATA */
+ 0x00000000 /* DENALI_PHY_860_DATA */
+ 0x00000000 /* DENALI_PHY_861_DATA */
+ 0x00000000 /* DENALI_PHY_862_DATA */
+ 0x00000000 /* DENALI_PHY_863_DATA */
+ 0x00000000 /* DENALI_PHY_864_DATA */
+ 0x00000000 /* DENALI_PHY_865_DATA */
+ 0x00000000 /* DENALI_PHY_866_DATA */
+ 0x00000000 /* DENALI_PHY_867_DATA */
+ 0x00000000 /* DENALI_PHY_868_DATA */
+ 0x00000000 /* DENALI_PHY_869_DATA */
+ 0x00000000 /* DENALI_PHY_870_DATA */
+ 0x00000000 /* DENALI_PHY_871_DATA */
+ 0x00000000 /* DENALI_PHY_872_DATA */
+ 0x00000000 /* DENALI_PHY_873_DATA */
+ 0x00000000 /* DENALI_PHY_874_DATA */
+ 0x00000000 /* DENALI_PHY_875_DATA */
+ 0x00000000 /* DENALI_PHY_876_DATA */
+ 0x00000000 /* DENALI_PHY_877_DATA */
+ 0x00000000 /* DENALI_PHY_878_DATA */
+ 0x00000000 /* DENALI_PHY_879_DATA */
+ 0x00000000 /* DENALI_PHY_880_DATA */
+ 0x00000000 /* DENALI_PHY_881_DATA */
+ 0x00000000 /* DENALI_PHY_882_DATA */
+ 0x00000000 /* DENALI_PHY_883_DATA */
+ 0x00000000 /* DENALI_PHY_884_DATA */
+ 0x00000000 /* DENALI_PHY_885_DATA */
+ 0x00000000 /* DENALI_PHY_886_DATA */
+ 0x00000000 /* DENALI_PHY_887_DATA */
+ 0x00000000 /* DENALI_PHY_888_DATA */
+ 0x00000000 /* DENALI_PHY_889_DATA */
+ 0x00000000 /* DENALI_PHY_890_DATA */
+ 0x00000000 /* DENALI_PHY_891_DATA */
+ 0x00000000 /* DENALI_PHY_892_DATA */
+ 0x00000000 /* DENALI_PHY_893_DATA */
+ 0x00000000 /* DENALI_PHY_894_DATA */
+ 0x00000000 /* DENALI_PHY_895_DATA */
+ 0x41753206 /* DENALI_PHY_896_DATA */
+ 0x0004c008 /* DENALI_PHY_897_DATA */
+ 0x000000da /* DENALI_PHY_898_DATA */
+ 0x00000000 /* DENALI_PHY_899_DATA */
+ 0x00000000 /* DENALI_PHY_900_DATA */
+ 0x00010000 /* DENALI_PHY_901_DATA */
+ 0x01DDDD90 /* DENALI_PHY_902_DATA */
+ 0x01DDDD90 /* DENALI_PHY_903_DATA */
+ 0x01030000 /* DENALI_PHY_904_DATA */
+ 0x01000000 /* DENALI_PHY_905_DATA */
+ 0x00c00000 /* DENALI_PHY_906_DATA */
+ 0x00000007 /* DENALI_PHY_907_DATA */
+ 0x00000000 /* DENALI_PHY_908_DATA */
+ 0x00000000 /* DENALI_PHY_909_DATA */
+ 0x04000408 /* DENALI_PHY_910_DATA */
+ 0x00000408 /* DENALI_PHY_911_DATA */
+ 0x00e4e400 /* DENALI_PHY_912_DATA */
+ 0x00000000 /* DENALI_PHY_913_DATA */
+ 0x00000000 /* DENALI_PHY_914_DATA */
+ 0x00000000 /* DENALI_PHY_915_DATA */
+ 0x00000000 /* DENALI_PHY_916_DATA */
+ 0x00000000 /* DENALI_PHY_917_DATA */
+ 0x00000000 /* DENALI_PHY_918_DATA */
+ 0x00000000 /* DENALI_PHY_919_DATA */
+ 0x00000000 /* DENALI_PHY_920_DATA */
+ 0x00000000 /* DENALI_PHY_921_DATA */
+ 0x00000000 /* DENALI_PHY_922_DATA */
+ 0x00000000 /* DENALI_PHY_923_DATA */
+ 0x00000000 /* DENALI_PHY_924_DATA */
+ 0x00000000 /* DENALI_PHY_925_DATA */
+ 0x00000000 /* DENALI_PHY_926_DATA */
+ 0x00000000 /* DENALI_PHY_927_DATA */
+ 0x00000000 /* DENALI_PHY_928_DATA */
+ 0x00200000 /* DENALI_PHY_929_DATA */
+ 0x00000000 /* DENALI_PHY_930_DATA */
+ 0x00000000 /* DENALI_PHY_931_DATA */
+ 0x00000000 /* DENALI_PHY_932_DATA */
+ 0x00000000 /* DENALI_PHY_933_DATA */
+ 0x00000000 /* DENALI_PHY_934_DATA */
+ 0x00000000 /* DENALI_PHY_935_DATA */
+ 0x02800280 /* DENALI_PHY_936_DATA */
+ 0x02800280 /* DENALI_PHY_937_DATA */
+ 0x02800280 /* DENALI_PHY_938_DATA */
+ 0x02800280 /* DENALI_PHY_939_DATA */
+ 0x00000280 /* DENALI_PHY_940_DATA */
+ 0x00000000 /* DENALI_PHY_941_DATA */
+ 0x00000000 /* DENALI_PHY_942_DATA */
+ 0x00000000 /* DENALI_PHY_943_DATA */
+ 0x00000000 /* DENALI_PHY_944_DATA */
+ 0x00000000 /* DENALI_PHY_945_DATA */
+ 0x00800080 /* DENALI_PHY_946_DATA */
+ 0x00800080 /* DENALI_PHY_947_DATA */
+ 0x00800080 /* DENALI_PHY_948_DATA */
+ 0x00800080 /* DENALI_PHY_949_DATA */
+ 0x00800080 /* DENALI_PHY_950_DATA */
+ 0x00800080 /* DENALI_PHY_951_DATA */
+ 0x00800080 /* DENALI_PHY_952_DATA */
+ 0x00800080 /* DENALI_PHY_953_DATA */
+ 0x00800080 /* DENALI_PHY_954_DATA */
+ 0x000100da /* DENALI_PHY_955_DATA */
+ 0x00000200 /* DENALI_PHY_956_DATA */
+ 0x00000000 /* DENALI_PHY_957_DATA */
+ 0x00000000 /* DENALI_PHY_958_DATA */
+ 0x00000002 /* DENALI_PHY_959_DATA */
+ 0x51313152 /* DENALI_PHY_960_DATA */
+ 0x80013130 /* DENALI_PHY_961_DATA */
+ 0x02000080 /* DENALI_PHY_962_DATA */
+ 0x00100001 /* DENALI_PHY_963_DATA */
+ 0x0c064208 /* DENALI_PHY_964_DATA */
+ 0x000f0c0f /* DENALI_PHY_965_DATA */
+ 0x01000140 /* DENALI_PHY_966_DATA */
+ 0x0000000c /* DENALI_PHY_967_DATA */
+ 0x00000000 /* DENALI_PHY_968_DATA */
+ 0x00000000 /* DENALI_PHY_969_DATA */
+ 0x00000000 /* DENALI_PHY_970_DATA */
+ 0x00000000 /* DENALI_PHY_971_DATA */
+ 0x00000000 /* DENALI_PHY_972_DATA */
+ 0x00000000 /* DENALI_PHY_973_DATA */
+ 0x00000000 /* DENALI_PHY_974_DATA */
+ 0x00000000 /* DENALI_PHY_975_DATA */
+ 0x00000000 /* DENALI_PHY_976_DATA */
+ 0x00000000 /* DENALI_PHY_977_DATA */
+ 0x00000000 /* DENALI_PHY_978_DATA */
+ 0x00000000 /* DENALI_PHY_979_DATA */
+ 0x00000000 /* DENALI_PHY_980_DATA */
+ 0x00000000 /* DENALI_PHY_981_DATA */
+ 0x00000000 /* DENALI_PHY_982_DATA */
+ 0x00000000 /* DENALI_PHY_983_DATA */
+ 0x00000000 /* DENALI_PHY_984_DATA */
+ 0x00000000 /* DENALI_PHY_985_DATA */
+ 0x00000000 /* DENALI_PHY_986_DATA */
+ 0x00000000 /* DENALI_PHY_987_DATA */
+ 0x00000000 /* DENALI_PHY_988_DATA */
+ 0x00000000 /* DENALI_PHY_989_DATA */
+ 0x00000000 /* DENALI_PHY_990_DATA */
+ 0x00000000 /* DENALI_PHY_991_DATA */
+ 0x00000000 /* DENALI_PHY_992_DATA */
+ 0x00000000 /* DENALI_PHY_993_DATA */
+ 0x00000000 /* DENALI_PHY_994_DATA */
+ 0x00000000 /* DENALI_PHY_995_DATA */
+ 0x00000000 /* DENALI_PHY_996_DATA */
+ 0x00000000 /* DENALI_PHY_997_DATA */
+ 0x00000000 /* DENALI_PHY_998_DATA */
+ 0x00000000 /* DENALI_PHY_999_DATA */
+ 0x00000000 /* DENALI_PHY_1000_DATA */
+ 0x00000000 /* DENALI_PHY_1001_DATA */
+ 0x00000000 /* DENALI_PHY_1002_DATA */
+ 0x00000000 /* DENALI_PHY_1003_DATA */
+ 0x00000000 /* DENALI_PHY_1004_DATA */
+ 0x00000000 /* DENALI_PHY_1005_DATA */
+ 0x00000000 /* DENALI_PHY_1006_DATA */
+ 0x00000000 /* DENALI_PHY_1007_DATA */
+ 0x00000000 /* DENALI_PHY_1008_DATA */
+ 0x00000000 /* DENALI_PHY_1009_DATA */
+ 0x00000000 /* DENALI_PHY_1010_DATA */
+ 0x00000000 /* DENALI_PHY_1011_DATA */
+ 0x00000000 /* DENALI_PHY_1012_DATA */
+ 0x00000000 /* DENALI_PHY_1013_DATA */
+ 0x00000000 /* DENALI_PHY_1014_DATA */
+ 0x00000000 /* DENALI_PHY_1015_DATA */
+ 0x00000000 /* DENALI_PHY_1016_DATA */
+ 0x00000000 /* DENALI_PHY_1017_DATA */
+ 0x00000000 /* DENALI_PHY_1018_DATA */
+ 0x00000000 /* DENALI_PHY_1019_DATA */
+ 0x00000000 /* DENALI_PHY_1020_DATA */
+ 0x00000000 /* DENALI_PHY_1021_DATA */
+ 0x00000000 /* DENALI_PHY_1022_DATA */
+ 0x00000000 /* DENALI_PHY_1023_DATA */
+ 0x36025174 /* DENALI_PHY_1024_DATA */
+ 0x0004c008 /* DENALI_PHY_1025_DATA */
+ 0x000000da /* DENALI_PHY_1026_DATA */
+ 0x00000000 /* DENALI_PHY_1027_DATA */
+ 0x00000000 /* DENALI_PHY_1028_DATA */
+ 0x00010000 /* DENALI_PHY_1029_DATA */
+ 0x01DDDD90 /* DENALI_PHY_1030_DATA */
+ 0x01DDDD90 /* DENALI_PHY_1031_DATA */
+ 0x01030000 /* DENALI_PHY_1032_DATA */
+ 0x01000000 /* DENALI_PHY_1033_DATA */
+ 0x00c00000 /* DENALI_PHY_1034_DATA */
+ 0x00000007 /* DENALI_PHY_1035_DATA */
+ 0x00000000 /* DENALI_PHY_1036_DATA */
+ 0x00000000 /* DENALI_PHY_1037_DATA */
+ 0x04000408 /* DENALI_PHY_1038_DATA */
+ 0x00000408 /* DENALI_PHY_1039_DATA */
+ 0x00e4e400 /* DENALI_PHY_1040_DATA */
+ 0x00000000 /* DENALI_PHY_1041_DATA */
+ 0x00000000 /* DENALI_PHY_1042_DATA */
+ 0x00000000 /* DENALI_PHY_1043_DATA */
+ 0x00000000 /* DENALI_PHY_1044_DATA */
+ 0x00000000 /* DENALI_PHY_1045_DATA */
+ 0x00000000 /* DENALI_PHY_1046_DATA */
+ 0x00000000 /* DENALI_PHY_1047_DATA */
+ 0x00000000 /* DENALI_PHY_1048_DATA */
+ 0x00000000 /* DENALI_PHY_1049_DATA */
+ 0x00000000 /* DENALI_PHY_1050_DATA */
+ 0x00000000 /* DENALI_PHY_1051_DATA */
+ 0x00000000 /* DENALI_PHY_1052_DATA */
+ 0x00000000 /* DENALI_PHY_1053_DATA */
+ 0x00000000 /* DENALI_PHY_1054_DATA */
+ 0x00000000 /* DENALI_PHY_1055_DATA */
+ 0x00000000 /* DENALI_PHY_1056_DATA */
+ 0x00200000 /* DENALI_PHY_1057_DATA */
+ 0x00000000 /* DENALI_PHY_1058_DATA */
+ 0x00000000 /* DENALI_PHY_1059_DATA */
+ 0x00000000 /* DENALI_PHY_1060_DATA */
+ 0x00000000 /* DENALI_PHY_1061_DATA */
+ 0x00000000 /* DENALI_PHY_1062_DATA */
+ 0x00000000 /* DENALI_PHY_1063_DATA */
+ 0x02800280 /* DENALI_PHY_1064_DATA */
+ 0x02800280 /* DENALI_PHY_1065_DATA */
+ 0x02800280 /* DENALI_PHY_1066_DATA */
+ 0x02800280 /* DENALI_PHY_1067_DATA */
+ 0x00000280 /* DENALI_PHY_1068_DATA */
+ 0x00000000 /* DENALI_PHY_1069_DATA */
+ 0x00000000 /* DENALI_PHY_1070_DATA */
+ 0x00000000 /* DENALI_PHY_1071_DATA */
+ 0x00000000 /* DENALI_PHY_1072_DATA */
+ 0x00000000 /* DENALI_PHY_1073_DATA */
+ 0x00800080 /* DENALI_PHY_1074_DATA */
+ 0x00800080 /* DENALI_PHY_1075_DATA */
+ 0x00800080 /* DENALI_PHY_1076_DATA */
+ 0x00800080 /* DENALI_PHY_1077_DATA */
+ 0x00800080 /* DENALI_PHY_1078_DATA */
+ 0x00800080 /* DENALI_PHY_1079_DATA */
+ 0x00800080 /* DENALI_PHY_1080_DATA */
+ 0x00800080 /* DENALI_PHY_1081_DATA */
+ 0x00800080 /* DENALI_PHY_1082_DATA */
+ 0x000100da /* DENALI_PHY_1083_DATA */
+ 0x00000200 /* DENALI_PHY_1084_DATA */
+ 0x00000000 /* DENALI_PHY_1085_DATA */
+ 0x00000000 /* DENALI_PHY_1086_DATA */
+ 0x00000002 /* DENALI_PHY_1087_DATA */
+ 0x51313152 /* DENALI_PHY_1088_DATA */
+ 0x80013130 /* DENALI_PHY_1089_DATA */
+ 0x02000080 /* DENALI_PHY_1090_DATA */
+ 0x00100001 /* DENALI_PHY_1091_DATA */
+ 0x0c064208 /* DENALI_PHY_1092_DATA */
+ 0x000f0c0f /* DENALI_PHY_1093_DATA */
+ 0x01000140 /* DENALI_PHY_1094_DATA */
+ 0x0000000c /* DENALI_PHY_1095_DATA */
+ 0x00000000 /* DENALI_PHY_1096_DATA */
+ 0x00000000 /* DENALI_PHY_1097_DATA */
+ 0x00000000 /* DENALI_PHY_1098_DATA */
+ 0x00000000 /* DENALI_PHY_1099_DATA */
+ 0x00000000 /* DENALI_PHY_1100_DATA */
+ 0x00000000 /* DENALI_PHY_1101_DATA */
+ 0x00000000 /* DENALI_PHY_1102_DATA */
+ 0x00000000 /* DENALI_PHY_1103_DATA */
+ 0x00000000 /* DENALI_PHY_1104_DATA */
+ 0x00000000 /* DENALI_PHY_1105_DATA */
+ 0x00000000 /* DENALI_PHY_1106_DATA */
+ 0x00000000 /* DENALI_PHY_1107_DATA */
+ 0x00000000 /* DENALI_PHY_1108_DATA */
+ 0x00000000 /* DENALI_PHY_1109_DATA */
+ 0x00000000 /* DENALI_PHY_1110_DATA */
+ 0x00000000 /* DENALI_PHY_1111_DATA */
+ 0x00000000 /* DENALI_PHY_1112_DATA */
+ 0x00000000 /* DENALI_PHY_1113_DATA */
+ 0x00000000 /* DENALI_PHY_1114_DATA */
+ 0x00000000 /* DENALI_PHY_1115_DATA */
+ 0x00000000 /* DENALI_PHY_1116_DATA */
+ 0x00000000 /* DENALI_PHY_1117_DATA */
+ 0x00000000 /* DENALI_PHY_1118_DATA */
+ 0x00000000 /* DENALI_PHY_1119_DATA */
+ 0x00000000 /* DENALI_PHY_1120_DATA */
+ 0x00000000 /* DENALI_PHY_1121_DATA */
+ 0x00000000 /* DENALI_PHY_1122_DATA */
+ 0x00000000 /* DENALI_PHY_1123_DATA */
+ 0x00000000 /* DENALI_PHY_1124_DATA */
+ 0x00000000 /* DENALI_PHY_1125_DATA */
+ 0x00000000 /* DENALI_PHY_1126_DATA */
+ 0x00000000 /* DENALI_PHY_1127_DATA */
+ 0x00000000 /* DENALI_PHY_1128_DATA */
+ 0x00000000 /* DENALI_PHY_1129_DATA */
+ 0x00000000 /* DENALI_PHY_1130_DATA */
+ 0x00000000 /* DENALI_PHY_1131_DATA */
+ 0x00000000 /* DENALI_PHY_1132_DATA */
+ 0x00000000 /* DENALI_PHY_1133_DATA */
+ 0x00000000 /* DENALI_PHY_1134_DATA */
+ 0x00000000 /* DENALI_PHY_1135_DATA */
+ 0x00000000 /* DENALI_PHY_1136_DATA */
+ 0x00000000 /* DENALI_PHY_1137_DATA */
+ 0x00000000 /* DENALI_PHY_1138_DATA */
+ 0x00000000 /* DENALI_PHY_1139_DATA */
+ 0x00000000 /* DENALI_PHY_1140_DATA */
+ 0x00000000 /* DENALI_PHY_1141_DATA */
+ 0x00000000 /* DENALI_PHY_1142_DATA */
+ 0x00000000 /* DENALI_PHY_1143_DATA */
+ 0x00000000 /* DENALI_PHY_1144_DATA */
+ 0x00000000 /* DENALI_PHY_1145_DATA */
+ 0x00000000 /* DENALI_PHY_1146_DATA */
+ 0x00000000 /* DENALI_PHY_1147_DATA */
+ 0x00000000 /* DENALI_PHY_1148_DATA */
+ 0x00000000 /* DENALI_PHY_1149_DATA */
+ 0x00000000 /* DENALI_PHY_1150_DATA */
+ 0x00000000 /* DENALI_PHY_1151_DATA */
+ 0x00000000 /* DENALI_PHY_1152_DATA */
+ 0x00000000 /* DENALI_PHY_1153_DATA */
+ 0x00050000 /* DENALI_PHY_1154_DATA */
+ 0x00000000 /* DENALI_PHY_1155_DATA */
+ 0x00000000 /* DENALI_PHY_1156_DATA */
+ 0x00000000 /* DENALI_PHY_1157_DATA */
+ 0x00000100 /* DENALI_PHY_1158_DATA */
+ 0x00000000 /* DENALI_PHY_1159_DATA */
+ 0x00000000 /* DENALI_PHY_1160_DATA */
+ 0x00506401 /* DENALI_PHY_1161_DATA */
+ 0x01221102 /* DENALI_PHY_1162_DATA */
+ 0x00000122 /* DENALI_PHY_1163_DATA */
+ 0x00000000 /* DENALI_PHY_1164_DATA */
+ 0x000B1F00 /* DENALI_PHY_1165_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1166_DATA */
+ 0x0B1F0B1B /* DENALI_PHY_1167_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1168_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1169_DATA */
+ 0x00000B00 /* DENALI_PHY_1170_DATA */
+ 0x42080010 /* DENALI_PHY_1171_DATA */
+ 0x01000100 /* DENALI_PHY_1172_DATA */
+ 0x01000100 /* DENALI_PHY_1173_DATA */
+ 0x01000100 /* DENALI_PHY_1174_DATA */
+ 0x01000100 /* DENALI_PHY_1175_DATA */
+ 0x00000000 /* DENALI_PHY_1176_DATA */
+ 0x00000000 /* DENALI_PHY_1177_DATA */
+ 0x00000000 /* DENALI_PHY_1178_DATA */
+ 0x00000000 /* DENALI_PHY_1179_DATA */
+ 0x00000000 /* DENALI_PHY_1180_DATA */
+ 0x00000803 /* DENALI_PHY_1181_DATA */
+ 0x223FFF00 /* DENALI_PHY_1182_DATA */
+ 0x000008FF /* DENALI_PHY_1183_DATA */
+ 0x0000057F /* DENALI_PHY_1184_DATA */
+ 0x0000057F /* DENALI_PHY_1185_DATA */
+ 0x00037FFF /* DENALI_PHY_1186_DATA */
+ 0x00037FFF /* DENALI_PHY_1187_DATA */
+ 0x00004410 /* DENALI_PHY_1188_DATA */
+ 0x00004410 /* DENALI_PHY_1189_DATA */
+ 0x00004410 /* DENALI_PHY_1190_DATA */
+ 0x00004410 /* DENALI_PHY_1191_DATA */
+ 0x00004410 /* DENALI_PHY_1192_DATA */
+ 0x00037FFF /* DENALI_PHY_1193_DATA */
+ 0x00037FFF /* DENALI_PHY_1194_DATA */
+ 0x00000000 /* DENALI_PHY_1195_DATA */
+ 0x00000000 /* DENALI_PHY_1196_DATA */
+ 0x00000000 /* DENALI_PHY_1197_DATA */
+ 0x04000000 /* DENALI_PHY_1198_DATA */
+ 0x00000000 /* DENALI_PHY_1199_DATA */
+ 0x00000000 /* DENALI_PHY_1200_DATA */
+ 0x00000108 /* DENALI_PHY_1201_DATA */
+ 0x00000000 /* DENALI_PHY_1202_DATA */
+ 0x00000000 /* DENALI_PHY_1203_DATA */
+ 0x00000000 /* DENALI_PHY_1204_DATA */
+ 0x00000001 /* DENALI_PHY_1205_DATA */
+ 0x00000000 /* DENALI_PHY_1206_DATA */
+ 0x00000000 /* DENALI_PHY_1207_DATA */
+ 0x00000000 /* DENALI_PHY_1208_DATA */
+ 0x00000000 /* DENALI_PHY_1209_DATA */
+ 0x00000000 /* DENALI_PHY_1210_DATA */
+ 0x00000000 /* DENALI_PHY_1211_DATA */
+ 0x00020100 /* DENALI_PHY_1212_DATA */
+ 0x00000000 /* DENALI_PHY_1213_DATA */
+ 0x00000000 /* DENALI_PHY_1214_DATA */
+ >;
+};
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
+#include "fu540-c000-u-boot.dtsi"
+#include "fu540-hifive-unleashed-a00-ddr.dtsi"
+
/ {
aliases {
spi0 = &qspi0;
spi2 = &qspi2;
};
+
+ hfclk {
+ u-boot,dm-spl;
+ };
+
+ rtcclk {
+ u-boot,dm-spl;
+ };
+
+};
+
+&qspi2 {
+ mmc@0 {
+ u-boot,dm-spl;
+ };
+};
+
+&gpio {
+ u-boot,dm-spl;
};
/* Copyright (c) 2018-2019 SiFive, Inc */
#include "fu540-c000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
#define RTCCLK_FREQ 1000000
clock-frequency = <RTCCLK_FREQ>;
clock-output-names = "rtcclk";
};
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ };
};
&uart0 {
&pwm1 {
status = "okay";
};
+
+&gpio {
+ status = "okay";
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 SiFive Inc
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __CLK_SIFIVE_H
+#define __CLK_SIFIVE_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 SiFive, Inc.
+ */
+
+#ifndef _GPIO_SIFIVE_H
+#define _GPIO_SIFIVE_H
+
+#define GPIO_INPUT_VAL 0x00
+#define GPIO_INPUT_EN 0x04
+#define GPIO_OUTPUT_EN 0x08
+#define GPIO_OUTPUT_VAL 0x0C
+#define GPIO_RISE_IE 0x18
+#define GPIO_RISE_IP 0x1C
+#define GPIO_FALL_IE 0x20
+#define GPIO_FALL_IP 0x24
+#define GPIO_HIGH_IE 0x28
+#define GPIO_HIGH_IP 0x2C
+#define GPIO_LOW_IE 0x30
+#define GPIO_LOW_IP 0x34
+#define GPIO_OUTPUT_XOR 0x40
+
+#define NR_GPIOS 16
+
+enum gpio_state {
+ LOW,
+ HIGH
+};
+
+/* Details about a GPIO bank */
+struct sifive_gpio_platdata {
+ void *base; /* address of registers in physical memory */
+};
+
+#define SIFIVE_GENERIC_GPIO_NR(port, index) \
+ (((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
+
+#endif /* _GPIO_SIFIVE_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _SPL_SIFIVE_H
+#define _SPL_SIFIVE_H
+
+int soc_spl_init(void);
+
+#endif /* _SPL_SIFIVE_H */
#define SBI_FID_REMOTE_SFENCE_VMA_ASID SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID
#endif
-#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
#define SBI_ERR_DENIED -4
#define SBI_ERR_INVALID_ADDRESS -5
-extern unsigned long sbi_spec_version;
struct sbiret {
long error;
long value;
#include <asm/encoding.h>
#include <asm/sbi.h>
-/* default SBI version is 0.1 */
-unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
-
struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
unsigned long arg1, unsigned long arg2,
unsigned long arg3, unsigned long arg4,
#endif
}
+/**
+ * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
+ * @extid: The extension ID to be probed.
+ *
+ * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise.
+ */
+int sbi_probe_extension(int extid)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid,
+ 0, 0, 0, 0, 0);
+ if (!ret.error)
+ if (ret.value)
+ return ret.value;
+
+ return -ENOTSUPP;
+}
+
#ifdef CONFIG_SBI_V01
/**
(unsigned long)hart_mask, start, size, asid, 0, 0);
}
-/**
- * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
- * @extid: The extension ID to be probed.
- *
- * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise.
- */
-int sbi_probe_extension(int extid)
-{
- struct sbiret ret;
-
- ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid,
- 0, 0, 0, 0, 0);
- if (!ret.error)
- if (ret.value)
- return ret.value;
-
- return -ENOTSUPP;
-}
#endif /* CONFIG_SBI_V01 */
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make nanopi-k2_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make odroid-c2_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make p200_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make p201_defconfig
> make
U-Boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make khadas-vim_defconfig
> make
U-Boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make libretech-ac_defconfig
> make
U-Boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make libretech-cc_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make p212_defconfig
> make
U-Boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make khadas-vim2_defconfig
> make
U-Boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make khadas-vim2_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make s400_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make sei510_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make sei610_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make u200_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make khadas-vim3_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make khadas-vim3l_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make odroid-n2_defconfig
> make
u-boot compilation
==================
- > export ARCH=arm
> export CROSS_COMPILE=aarch64-none-elf-
> make w400_defconfig
> make
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_CMD_USB
static void board_usb_hw_init(void)
{
atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1);
}
+#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
}
#endif
+#ifdef CONFIG_CMD_USB
static void board_usb_hw_init(void)
{
atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, ATMEL_PIO_PUEN_MASK);
}
+#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
static void board_uart0_hw_init(void)
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_CMD_USB
static void board_usb_hw_init(void)
{
atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
}
+#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
Build U-Boot
============
$ make imx8mm_beacon_defconfig
-$ make flash.bin ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000
+$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000
Burn U-Boot to microSD Card
===========================
Build and program U-Boot to NOR flash
==================================
1. Build u-boot.bin image example:
- export ARCH=powerpc
export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
make C293PCIE
Build and burn U-Boot to NOR flash
==================================
1. Build u-boot.bin image
- export ARCH=powerpc
export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
make P1010RDB_NOR
Build images for different boot mode
====================================
First setup cross compile environment on build host
- $ export ARCH=powerpc
$ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
1. For NOR boot
To build U-Boot for the Dual and Quad variants:
make imx6q_logic_defconfig
- make u-boot.imx ARCH=arm CROSS_COMPILE=arm-linux-
+ make u-boot.imx CROSS_COMPILE=arm-linux-
Flashing U-Boot into the SD card
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
-#ifdef CONFIG_CMD_NAND
+#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
/* NAND */
static iomux_v3_cfg_t const nfc_pads[] = {
IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL)),
SETUP_IOMUX_PADS(gpios_pads);
}
-#ifdef CONFIG_CMD_NAND
+#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
static void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
setup_gpios();
-#ifdef CONFIG_CMD_NAND
+#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
setup_gpmi_nand();
#endif
return 0;
.refr = 7, /* 8 refresh commands per refresh cycle */
};
-#ifdef CONFIG_CMD_NAND
+#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
/* Enable NAND */
setup_gpmi_nand();
#endif
> cd ../u-boot
> export CROSS_COMPILE=arm-linux-gnueabihf-
- > export ARCH=arm
> make evb-rk3229_defconfig
> make
> make u-boot.itb
S: Maintained
F: configs/rock64-rk3328_defconfig
F: arch/arm/dts/rk3328-rock64-u-boot.dtsi
+
+ROCKPIE-RK3328
+M: Banglang Huang <banglang.huang@foxmail.com>
+S: Maintained
+F: configs/rock-pi-e-rk3328_defconfig
+F: arch/arm/dts/rk3328-rock-pi-e.dts
+F: arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
==============
> cd ../u-boot
- > export ARCH=arm64
> export CROSS_COMPILE=aarch64-linux-gnu-
> make evb-rk3399_defconfig
for firefly-rk3399, use below instead:
default "sifive"
config SYS_CPU
- default "generic"
+ default "fu540"
config SYS_CONFIG_NAME
default "sifive-fu540"
config SYS_TEXT_BASE
+ default 0x80200000 if SPL
default 0x80000000 if !RISCV_SMODE
default 0x80200000 if RISCV_SMODE
+config SPL_TEXT_BASE
+ default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+ default 0x80000000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select GENERIC_RISCV
+ select SIFIVE_FU540
+ select SUPPORT_SPL
+ select RAM
+ select SPL_RAM if SPL
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
imply CMD_FAT
imply CMD_FS_GENERIC
+ imply CMD_GPT
+ imply PARTITION_TYPE_GUID
imply CMD_NET
imply CMD_PING
imply CMD_SF
imply SIFIVE_GPIO
imply CMD_GPIO
imply SMP
+ imply MISC
+ imply SIFIVE_OTP
endif
M: Atish Patra <atish.patra@wdc.com>
S: Maintained
F: board/sifive/fu540/
+F: doc/board/sifive/fu540.rst
F: include/configs/sifive-fu540.h
F: configs/sifive_fu540_defconfig
# Copyright (c) 2019 Western Digital Corporation or its affiliates.
obj-y += fu540.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
* Anup Patel <anup.patel@wdc.com>
*/
-#include <common.h>
#include <dm.h>
#include <env.h>
#include <init.h>
+#include <log.h>
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <misc.h>
+#include <spl.h>
+
+/*
+ * This define is a value used for error/unknown serial.
+ * If we really care about distinguishing errors and 0 is
+ * valid, we'll need a different one.
+ */
+#define ERROR_READING_SERIAL_NUMBER 0
#ifdef CONFIG_MISC_INIT_R
-#define FU540_OTP_BASE_ADDR 0x10070000
-
-struct fu540_otp_regs {
- u32 pa; /* Address input */
- u32 paio; /* Program address input */
- u32 pas; /* Program redundancy cell selection input */
- u32 pce; /* OTP Macro enable input */
- u32 pclk; /* Clock input */
- u32 pdin; /* Write data input */
- u32 pdout; /* Read data output */
- u32 pdstb; /* Deep standby mode enable input (active low) */
- u32 pprog; /* Program mode enable input */
- u32 ptc; /* Test column enable input */
- u32 ptm; /* Test mode enable input */
- u32 ptm_rep;/* Repair function test mode enable input */
- u32 ptr; /* Test row enable input */
- u32 ptrim; /* Repair function enable input */
- u32 pwe; /* Write enable input (defines program cycle) */
-} __packed;
-
-#define BYTES_PER_FUSE 4
-#define NUM_FUSES 0x1000
-
-static int fu540_otp_read(int offset, void *buf, int size)
+#if CONFIG_IS_ENABLED(SIFIVE_OTP)
+static u32 otp_read_serialnum(struct udevice *dev)
{
- struct fu540_otp_regs *regs = (void __iomem *)FU540_OTP_BASE_ADDR;
- unsigned int i;
- int fuseidx = offset / BYTES_PER_FUSE;
- int fusecount = size / BYTES_PER_FUSE;
- u32 fusebuf[fusecount];
-
- /* check bounds */
- if (offset < 0 || size < 0)
- return -EINVAL;
- if (fuseidx >= NUM_FUSES)
- return -EINVAL;
- if ((fuseidx + fusecount) > NUM_FUSES)
- return -EINVAL;
+ int ret;
+ u32 serial[2] = {0};
- /* init OTP */
- writel(0x01, ®s->pdstb); /* wake up from stand-by */
- writel(0x01, ®s->ptrim); /* enable repair function */
- writel(0x01, ®s->pce); /* enable input */
-
- /* read all requested fuses */
- for (i = 0; i < fusecount; i++, fuseidx++) {
- writel(fuseidx, ®s->pa);
-
- /* cycle clock to read */
- writel(0x01, ®s->pclk);
- mdelay(1);
- writel(0x00, ®s->pclk);
- mdelay(1);
-
- /* read the value */
- fusebuf[i] = readl(®s->pdout);
- }
+ for (int i = 0xfe * 4; i > 0; i -= 8) {
+ ret = misc_read(dev, i, serial, sizeof(serial));
- /* shut down */
- writel(0, ®s->pce);
- writel(0, ®s->ptrim);
- writel(0, ®s->pdstb);
+ if (ret != sizeof(serial)) {
+ printf("%s: error reading serial from OTP\n", __func__);
+ break;
+ }
- /* copy out */
- memcpy(buf, fusebuf, size);
+ if (serial[0] == ~serial[1])
+ return serial[0];
+ }
- return 0;
+ return ERROR_READING_SERIAL_NUMBER;
}
+#endif
static u32 fu540_read_serialnum(void)
{
+ u32 serial = ERROR_READING_SERIAL_NUMBER;
+
+#if CONFIG_IS_ENABLED(SIFIVE_OTP)
+ struct udevice *dev;
int ret;
- u32 serial[2] = {0};
- for (int i = 0xfe * 4; i > 0; i -= 8) {
- ret = fu540_otp_read(i, serial, sizeof(serial));
- if (ret) {
- printf("%s: error reading from OTP\n", __func__);
- break;
- }
- if (serial[0] == ~serial[1])
- return serial[0];
+ /* init OTP */
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(sifive_otp), &dev);
+
+ if (ret) {
+ debug("%s: could not find otp device\n", __func__);
+ return serial;
}
- return 0;
+ /* read serial from OTP and set env var */
+ serial = otp_read_serialnum(dev);
+#endif
+
+ return serial;
}
static void fu540_setup_macaddr(u32 serialnum)
return 0;
}
+
+#ifdef CONFIG_SPL
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ return BOOT_DEVICE_MMC1;
+#else
+ puts("Unknown boot device\n");
+ hang();
+#endif
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <init.h>
+#include <spl.h>
+#include <misc.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
+
+#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
+
+int init_clk_and_ddr(void)
+{
+ int ret;
+
+ ret = soc_spl_init();
+ if (ret) {
+ debug("FU540 SPL init failed: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * GEMGXL init VSC8541 PHY reset sequence;
+ * leave pull-down active for 2ms
+ */
+ udelay(2000);
+ ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
+ if (ret) {
+ debug("gem_phy_reset gpio request failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set GPIO 12 (PHY NRESET) */
+ ret = gpio_direction_output(GEM_PHY_RESET, 1);
+ if (ret) {
+ debug("gem_phy_reset gpio direction set failed: %d\n", ret);
+ return ret;
+ }
+
+ udelay(1);
+
+ /* Reset PHY again to enter unmanaged mode */
+ gpio_set_value(GEM_PHY_RESET, 0);
+ udelay(1);
+ gpio_set_value(GEM_PHY_RESET, 1);
+ mdelay(15);
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ ret = spl_early_init();
+ if (ret)
+ panic("spl_early_init() failed: %d\n", ret);
+
+ arch_cpu_init_dm();
+
+ preloader_console_init();
+
+ ret = init_clk_and_ddr();
+ if (ret)
+ panic("init_clk_and_ddr() failed: %d\n", ret);
+}
world in this case.
- Build u-boot
- Set environment variable of CROSS_COMPILE for your toolchain and ARCH=arm
+ Set environment variable of CROSS_COMPILE for your toolchain
$ make pico-imx7d_bl33_defconfig
$ make all
Build the TPL/SPL stage
=======================
- > make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm
+ > make CROSS_COMPILE=aarch64-unknown-elf-
Build the full U-Boot and a FIT image including the ATF
=======================================================
- > make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm u-boot.itb
+ > make CROSS_COMPILE=aarch64-unknown-elf- u-boot.itb
Flash the image
===============
config ENV_OFFSET
default 0x3fc000 if ENV_IS_IN_SPI_FLASH
+choice
+ prompt "Theobroma Systems RK3399-Q7 DDR Option"
+ default TARGET_PUMA_RK3399_RAM_DDR3_1333
+
+config TARGET_PUMA_RK3399_RAM_DDR3_1333
+ bool "DDR3-1333MHz"
+
+config TARGET_PUMA_RK3399_RAM_DDR3_1600
+ bool "DDR3-1600MHz"
+
+config TARGET_PUMA_RK3399_RAM_DDR3_1866
+ bool "DDR3-1866MHz"
+
+endchoice
+
endif
+++ /dev/null
-#!/bin/sh
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
-#
-# Based on the board/sunxi/mksunxi_fit_atf.sh
-#
-# Script to generate FIT image source for 64-bit puma boards with
-# U-Boot proper, ATF, PMU firmware and devicetree.
-#
-# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
-
-[ -z "$BL31" ] && BL31="bl31.bin"
-
-if [ ! -f $BL31 ]; then
- echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2
- echo "Please read Building section in doc/README.rockchip" >&2
- BL31=/dev/null
-fi
-
-[ -z "$PMUM0" ] && PMUM0="rk3399m0.bin"
-
-if [ ! -f $PMUM0 ]; then
- echo "WARNING: PMUM0 file $PMUM0 NOT found, resulting binary is non-functional" >&2
- echo "Please read Building section in doc/README.rockchip" >&2
- PMUM0=/dev/null
-fi
-
-cat << __HEADER_EOF
-/* SPDX-License-Identifier: GPL-2.0+ OR X11 */
-/*
- * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
- *
- * Minimal dts for a SPL FIT image payload.
- */
-
-/dts-v1/;
-
-/ {
- description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB";
- #address-cells = <1>;
-
- images {
- uboot {
- description = "U-Boot (64-bit)";
- data = /incbin/("u-boot-nodtb.bin");
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = <0x4a000000>;
- };
- atf {
- description = "ARM Trusted Firmware";
- data = /incbin/("$BL31");
- type = "firmware";
- arch = "arm64";
- os = "arm-trusted-firmware";
- compression = "none";
- load = <0x1000>;
- entry = <0x1000>;
- };
- pmu {
- description = "Cortex-M0 firmware";
- data = /incbin/("$PMUM0");
- type = "pmu-firmware";
- compression = "none";
- load = <0x180000>;
- };
- fdt {
- description = "RK3399-Q7 (Puma) flat device-tree";
- data = /incbin/("$1");
- type = "flat_dt";
- compression = "none";
- };
-__HEADER_EOF
-
-cat << __CONF_HEADER_EOF
- };
-
- configurations {
- default = "conf";
- conf {
- description = "Theobroma Systems RK3399-Q7 (Puma) SoM";
- firmware = "atf";
- loadables = "uboot", "pmu";
- fdt = "fdt";
- };
-__CONF_HEADER_EOF
-
-cat << __ITS_EOF
- };
-};
-__ITS_EOF
int misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+ u8 cpuid[cpuid_length];
+ int ret;
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+ if (ret)
+ return ret;
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
+ if (ret)
+ return ret;
- ret = rockchip_setup_macaddr();
- if (ret)
- return ret;
+ ret = rockchip_setup_macaddr();
+ if (ret)
+ return ret;
setup_iodomain();
setup_boottargets();
serialnr->low = (u32)(serial & 0xffffffff);
}
#endif
-
-/**
- * Switch power at an external regulator (for our root hub).
- *
- * @param ctrl pointer to the xHCI controller
- * @param port port number as in the control message (one-based)
- * @param enable boolean indicating whether to enable or disable power
- * @return returns 0 on success, an error-code on failure
- */
-static int board_usb_port_power_set(struct udevice *dev, int port,
- bool enable)
-{
-#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_REGULATOR)
- /* We start counting ports at 0, while USB counts from 1. */
- int index = port - 1;
- const char *regname = NULL;
- struct udevice *regulator;
- const char *prop = "tsd,usb-port-power";
- int ret;
-
- debug("%s: ctrl '%s' port %d enable %s\n", __func__,
- dev_read_name(dev), port, enable ? "true" : "false");
-
- ret = dev_read_string_index(dev, prop, index, ®name);
- if (ret < 0) {
- debug("%s: ctrl '%s' port %d: no entry in '%s'\n",
- __func__, dev_read_name(dev), port, prop);
- return ret;
- }
-
- ret = regulator_get_by_platname(regname, ®ulator);
- if (ret) {
- debug("%s: ctrl '%s' port %d: could not get regulator '%s'\n",
- __func__, dev_read_name(dev), port, regname);
- return ret;
- }
-
- regulator_set_enable(regulator, enable);
- return 0;
-#else
- return -ENOTSUPP;
-#endif
-}
-
-void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
-{
- struct udevice *dev = hub->pusb_dev->dev;
- struct udevice *ctrl;
-
- /* We are only interested in our root-hubs */
- if (usb_hub_is_root_hub(dev) == false)
- return;
-
- ctrl = usb_get_bus(dev);
- if (!ctrl) {
- debug("%s: could not retrieve ctrl for hub\n", __func__);
- return;
- }
-
- /*
- * To work around an incompatibility between the single-threaded
- * USB stack in U-Boot and (a strange low-power mode of) the USB
- * hub we have on-module, we need to delay powering on the hub
- * until the first time the port is probed.
- */
- board_usb_port_power_set(ctrl, port, true);
-}
4. U-Boot:
4.1. R5:
-$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig O=/tmp/r5
-$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
+$ make CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig O=/tmp/r5
+$ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
4.2. A53:
-$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig O=/tmp/a53
-$ make
ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a53
+$ make CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig O=/tmp/a53
+$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a53
Target Images
--------------
4. U-Boot:
4.1. R5:
-$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=/tmp/r5
-$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
+$ make CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=/tmp/r5
+$ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
4.2. A72:
-$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
-$ make
ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72
+$ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
+$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72
Target Images
--------------
Build instructions:
===================
Examples for k2hk, for k2e, k2l and k2g just replace k2hk prefix accordingly.
-Don't forget to add ARCH=arm and CROSS_COMPILE.
+Don't forget to add CROSS_COMPILE.
To build u-boot.bin, u-boot-spi.gph, MLO:
>make k2hk_evm_defconfig
> cd ../u-boot
> cp ../rkbin/rk33/rk3399_bl31_v1.00.elf ./bl31.elf
- > export ARCH=arm64
> export CROSS_COMPILE=aarch64-linux-gnu-
> make rock960-rk3399_defconfig
> make
config CMD_FITUPD
bool "fitImage update command"
+ depends on UPDATE_TFTP
help
Implements the 'fitupd' command, which allows to automatically
store software updates present on a TFTP server in NOR Flash
*
* Decode the value of UEFI load option variable and print information.
*/
-static void show_efi_boot_opt_data(u16 *varname16, void *data, size_t size)
+static void show_efi_boot_opt_data(u16 *varname16, void *data, size_t *size)
{
struct efi_load_option lo;
char *label, *p;
size_t label_len16, label_len;
u16 *dp_str;
+ efi_status_t ret;
- efi_deserialize_load_option(&lo, data);
+ ret = efi_deserialize_load_option(&lo, data, size);
+ if (ret != EFI_SUCCESS) {
+ printf("%ls: invalid load option\n", varname16);
+ return;
+ }
label_len16 = u16_strlen(lo.label);
label_len = utf16_utf8_strnlen(lo.label, label_len16);
printf(" data:\n");
print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1,
- lo.optional_data, size + (u8 *)data -
- (u8 *)lo.optional_data, true);
+ lo.optional_data, *size, true);
free(label);
}
&efi_global_variable_guid,
NULL, &size, data));
if (ret == EFI_SUCCESS)
- show_efi_boot_opt_data(varname16, data, size);
+ show_efi_boot_opt_data(varname16, data, &size);
free(data);
}
}
goto out;
}
- efi_deserialize_load_option(&lo, data);
+ ret = efi_deserialize_load_option(&lo, data, &size);
+ if (ret != EFI_SUCCESS) {
+ printf("%ls: invalid load option\n", var_name16);
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
label_len16 = u16_strlen(lo.label);
label_len = utf16_utf8_strnlen(lo.label, label_len16);
#include <command.h>
#include <net.h>
-#if !defined(CONFIG_UPDATE_TFTP)
-#error "CONFIG_UPDATE_TFTP required"
-#endif
-
static int do_fitupd(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
new = spi_flash_probe(bus, cs, speed, mode);
flash = new;
-
if (!new) {
printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
return 1;
}
-
- flash = new;
#endif
return 0;
if (hdr->kernel_addr == ANDROID_IMAGE_DEFAULT_KERNEL_ADDR)
return (ulong)hdr + hdr->page_size;
+ /*
+ * abootimg creates images where all load addresses are 0
+ * and we need to fix them.
+ */
+ if (hdr->kernel_addr == 0 && hdr->ramdisk_addr == 0)
+ return env_get_ulong("kernel_addr_r", 16, 0);
+
return hdr->kernel_addr;
}
ARCH_MX6 || ARCH_MX7 || \
ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \
ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
- OMAP44XX || OMAP54XX || AM33XX || AM43XX
+ OMAP44XX || OMAP54XX || AM33XX || AM43XX || TARGET_SIFIVE_FU540
help
Use sector number for specifying U-Boot location on MMC/SD in
raw mode.
default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \
OMAP54XX || AM33XX || AM43XX || ARCH_K3
default 0x4000 if ARCH_ROCKCHIP
+ default 0x822 if TARGET_SIFIVE_FU540
help
Address on the MMC to load U-Boot from, when the MMC is being used
in raw mode. Units: MMC sectors (1 sector = 512 bytes).
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=1
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_LATE_INIT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_AR933X=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_AR933X=y
CONFIG_AR933X_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_NFS is not set
+CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_NFS is not set
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_SPI=y
CONFIG_ZYNQMP_GQSPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_ATMEL_USART=y
CONFIG_WDT=y
CONFIG_WDT_AT91=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11B=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_MMC=y
-CONFIG_EFI_PARTITION=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
+CONFIG_CMD_ASKENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_PRIOR_STAGE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
# CONFIG_WATCHDOG is not set
CONFIG_WDT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
-CONFIG_CMD_SPI=y
+# CONFIG_CMD_SF is not set
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
+# CONFIG_GZIP is not set
CONFIG_TPL_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
+# CONFIG_GZIP is not set
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_TPM=y
+# CONFIG_GZIP is not set
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_TPM=y
+# CONFIG_GZIP is not set
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_TPM=y
+# CONFIG_GZIP is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
+CONFIG_BOARD_LATE_INIT=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_CMD_PCA953X=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_NFS is not set
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_FIT_VERBOSE=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
# CONFIG_VIDEO_VESA is not set
+# CONFIG_GZIP is not set
CONFIG_USB_KEYBOARD=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_CRS3XX_98DX3236=y
CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_ENV_OFFSET=0x80000
-# CONFIG_EFI_LOADER is not set
+CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_BUILD_TARGET="u-boot.kwb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_BEST_MATCH=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_KEYED_CTRLC=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_I2C is not set
+CONFIG_CMD_MTD=y
CONFIG_CMD_SPI=y
CONFIG_CMD_CACHE=y
-# CONFIG_CMD_UBI is not set
-CONFIG_CMD_MTD=y
CONFIG_CMD_MTDPARTS=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BLK=y
-# CONFIG_DM_I2C is not set
-# CONFIG_SYS_I2C_MVTWSI is not set
# CONFIG_MMC is not set
CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
CONFIG_DM_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_FIT=y
-CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_FIT_BEST_MATCH=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+# CONFIG_EFI_LOADER is not set
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_AUTOBOOT_KEYED_CTRLC=y
CONFIG_CMD_CPU=y
+# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
+CONFIG_BZIP2=y
CONFIG_SYS_PROMPT="display5 > "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_ELF is not set
+CONFIG_CMD_SPL=y
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_PROMPT="display5 factory > "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_ELF is not set
+CONFIG_CMD_SPL=y
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_FS_EXT4=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_DM_ETH is not set
-CONFIG_DEBUG_EFI_CONSOLE=y
# CONFIG_REGEX is not set
+# CONFIG_GZIP is not set
CONFIG_EFI=y
# CONFIG_EFI_LOADER is not set
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_PCI_PNP is not set
+# CONFIG_GZIP is not set
CONFIG_EFI=y
CONFIG_EFI_STUB=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_PCI_PNP is not set
+# CONFIG_GZIP is not set
CONFIG_EFI=y
CONFIG_EFI_STUB=y
CONFIG_EFI_STUB_64BIT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME=y
+CONFIG_PCI=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_SPI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
+# CONFIG_GZIP is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_NFS is not set
+CONFIG_CMD_BMP=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_CLS=y
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_AUTOBOOT_KEYED_CTRLC=y
CONFIG_CMD_CPU=y
+# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard"
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
+CONFIG_BZIP2=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_SPL_NAND_OFS=0x1100000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
+CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DEBUG_UART=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_DEBUG_UART=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200n8"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
+CONFIG_BZIP2=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
+CONFIG_BZIP2=y
CONFIG_BOOTDELAY=3
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_CMD_SPL=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl-mipi> "
+CONFIG_CMD_SPL=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
-CONFIG_DEBUG_UART_MXC=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
+CONFIG_CMD_SPL=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
-CONFIG_DEBUG_UART_MXC=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_DM_VIDEO=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
+CONFIG_CMD_SPL=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_FUSE=y
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
-CONFIG_USB_KEYBOARD=y
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
-CONFIG_USB_KEYBOARD=y
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_MESON_G12A=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
CONFIG_USB_GADGET_PRODUCT_NUM=0xfada
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_MESON_GX_VPU_POWER_DOMAIN=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_MISC_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_IMLS=y
+CONFIG_CMD_SPL=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_IMLS=y
+CONFIG_CMD_SPL=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_LATE_INIT=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_LATE_INIT=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11B=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_DEFAULT_FDT_FILE="imx25-pdk.dtb"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_FUSE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
+CONFIG_CMD_FUSE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x20000000
+# CONFIG_CMD_FUSE is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_CACHE=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_SOFT_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_SOFT_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_SOFT_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_READ=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
+CONFIG_BZIP2=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-# CONFIG_CMD_NAND is not set
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
+CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_RAM_RK3399_LPDDR4=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_TARGET_PINEBOOK_PRO_RK3399=y
-CONFIG_BAUDRATE=1500000
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb"
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_MTD_SUPPORT=y
CONFIG_TPL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_SF=y
CONFIG_CMD_TIME=y
-CONFIG_CMD_USB=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinebook-pro"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_BOOTDELAY=3
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
-CONFIG_ROCKCHIP_SPI=y
CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
-CONFIG_PMIC_RK8XX=y
+CONFIG_NVME=y
+CONFIG_PCI=y
CONFIG_DM_PMIC_FAN53555=y
+CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-# CONFIG_USB_XHCI_ROCKCHIP is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_RTL8152=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USE_TINY_PRINTF=y
-CONFIG_SPL_TINY_MEMSET=y
-CONFIG_ERRNO_STR=y
CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_BPP16=y
-CONFIG_VIDEO_BPP32=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_EDP=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0xff8c2000
CONFIG_DEBUG_UART=y
-CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-ddr1600"
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
CONFIG_DM_RTC=y
CONFIG_RTC_ISL1208=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_RAM=y
CONFIG_BAUDRATE=921600
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_MTK=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_MTK_SERIAL=y
CONFIG_WDT=y
CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
CONFIG_FRAMEBUFFER_VESA_MODE=0x144
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
CONFIG_FRAMEBUFFER_VESA_MODE=0x144
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ENV_SIZE=0x6000
+CONFIG_ENV_OFFSET=0x460000
+CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROC_PC_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
CONFIG_TPL_GPIO_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
-CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ENV_SIZE=0x6000
+CONFIG_ENV_OFFSET=0x460000
+CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROC_PC_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
CONFIG_TPL_GPIO_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x4000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SMBIOS_PRODUCT_NAME="rock-pi-e_rk3328"
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+CONFIG_SMBIOS_MANUFACTURER="radxa"
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-# CONFIG_USB_XHCI_ROCKCHIP is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROCKPRO64_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_MISC_INIT_R=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME=y
+CONFIG_PCI=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
+CONFIG_DM_RESET=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_TARGET_RPI_4_32B=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
-CONFIG_NR_DRAM_BANKS=4
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_ARCH_FIXUP_FDT_MEMORY=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_RPI_4=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
-CONFIG_NR_DRAM_BANKS=4
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_ARCH_FIXUP_FDT_MEMORY=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_TARGET_RPI_ARM64=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
-CONFIG_NR_DRAM_BANKS=4
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc7c00000
CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_RNG=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV8803=y
-CONFIG_DEBUG_UART_SANDBOX=y
CONFIG_SANDBOX_SERIAL=y
CONFIG_SMEM=y
CONFIG_SANDBOX_SMEM=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
+CONFIG_BZIP2=y
CONFIG_RISCV=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_ENV_SIZE=0x20000
+CONFIG_SPL_MMC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_TARGET_SIFIVE_FU540=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
CONFIG_DM_MTD=y
CONFIG_SYSCON=y
# CONFIG_PCI_PNP is not set
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_REGULATOR_TPS65090=y
CONFIG_DM_PWM=y
CONFIG_PWM_EXYNOS=y
-CONFIG_DEBUG_UART_S5P=y
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_SAMSUNG=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_SYS_MEMTEST_END=0x88000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_REGULATOR_TPS65090=y
CONFIG_DM_PWM=y
CONFIG_PWM_EXYNOS=y
-CONFIG_DEBUG_UART_S5P=y
CONFIG_SOUND=y
CONFIG_I2S=y
CONFIG_I2S_SAMSUNG=y
CONFIG_BOOTARGS="console=ttyAS1,115200 CONSOLE=/dev/ttyAS1 consoleblank=0 root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait mem=992M@0x40000000 vmalloc=256m"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="stih410-b2260 => "
+CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_LATE_INIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_LATE_INIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="stm32h743i-disco"
+CONFIG_BOARD_LATE_INIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="stm32h743i-eval"
+CONFIG_BOARD_LATE_INIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DEBUG_UART_ATMEL=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_TIME=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT2=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_TIME=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT2=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
CONFIG_CMD_TIME=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT2=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_CONSOLE_SCROLL_LINES=5
+# CONFIG_GZIP is not set
CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_DM_SERIAL=y
-CONFIG_DEBUG_UART_PL011=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x18000000
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x18000000
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x18000000
CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
# CONFIG_NETDEVICES is not set
CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
CONFIG_CMD_PING=y
# CONFIG_ISO_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
-CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RESET=y
-CONFIG_DEBUG_UART_MESON=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_MESON_SERIAL=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DEBUG_MVEBU_A3700_UART=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_CMD_SPL=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_PMECC_CAP=4
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_LZMA=y
+CONFIG_LZO=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530"
CONFIG_ENV_ADDR=0x100000
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
-CONFIG_MTD_UBI=y
CONFIG_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_MVEBU=y
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_MMC is not set
+CONFIG_ARM_DCC=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ARM_DCC=y
CONFIG_FAT_WRITE=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ARM_DCC=y
CONFIG_FAT_WRITE=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
+CONFIG_ARM_DCC=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_PHY_XILINX=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
+CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_MMC is not set
+CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ARASAN=y
CONFIG_SYS_NAND_MAX_CHIPS=2
+CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ARASAN=y
+CONFIG_ARM_DCC=y
CONFIG_PANIC_HANG=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ARM_DCC=y
CONFIG_SPI=y
CONFIG_ZYNQMP_GQSPI=y
CONFIG_PANIC_HANG=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_TIMER=y
CONFIG_CADENCE_TTC_TIMER=y
CONFIG_ZYNQ_GEM=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
+CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_SPI=y
CONFIG_ZYNQ_SPI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_ZYNQ=y
+CONFIG_ARM_DCC=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
+CONFIG_ARM_DCC=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_DEBUG_UART_ARM_DCC=y
+CONFIG_ARM_DCC=y
CONFIG_ZYNQ_QSPI=y
+# CONFIG_GZIP is not set
# CONFIG_EFI_LOADER is not set
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
+
+Writing tests
+-------------
+
+All new commands should have tests. Tests for existing commands are very
+welcome.
+
+It is fairly easy to write a test for a command. Enable it in sandbox, and
+then add code that runs the command and checks the output.
+
+Here is an example:
+
+/* Test 'acpi items' command */
+static int dm_test_acpi_cmd_items(struct unit_test_state *uts)
+{
+ struct acpi_ctx ctx;
+ void *buf;
+
+ buf = malloc(BUF_SIZE);
+ ut_assertnonnull(buf);
+
+ ctx.current = buf;
+ ut_assertok(acpi_fill_ssdt(&ctx));
+ console_record_reset();
+ run_command("acpi items", 0);
+ ut_assert_nextline("dev 'acpi-test', type 1, size 2");
+ ut_assert_nextline("dev 'acpi-test2', type 1, size 2");
+ ut_assert_console_end();
+
+ ctx.current = buf;
+ ut_assertok(acpi_inject_dsdt(&ctx));
+ console_record_reset();
+ run_command("acpi items", 0);
+ ut_assert_nextline("dev 'acpi-test', type 2, size 2");
+ ut_assert_nextline("dev 'acpi-test2', type 2, size 2");
+ ut_assert_console_end();
+
+ console_record_reset();
+ run_command("acpi items -d", 0);
+ ut_assert_nextline("dev 'acpi-test', type 2, size 2");
+ ut_assert_nextlines_are_dump(2);
+ ut_assert_nextline("%s", "");
+ ut_assert_nextline("dev 'acpi-test2', type 2, size 2");
+ ut_assert_nextlines_are_dump(2);
+ ut_assert_nextline("%s", "");
+ ut_assert_console_end();
+
+ return 0;
+}
+DM_TEST(dm_test_acpi_cmd_items, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
Supported CPU families
----------------------
-Please "make menuconfig" with ARCH=m68k, or check arch/m68k/cpu to see the
+Please "make menuconfig" and select "m68k" or check arch/m68k/cpu to see the
currently supported processor and families.
board=M5475DFE
make distclean
- make ARCH=m68k ${board}_defconfig
- make ARCH=m68k KBUILD_VERBOSE=1
+ make ${board}_defconfig
+ make KBUILD_VERBOSE=1
Adopted toolchains
$ make clean
$ export CROSS_COMPILE=aarch64-linux-gnu-
- $ make ARCH=arm cubieboard7_defconfig
+ $ make cubieboard7_defconfig
$ make u-boot-dtb.img -j16
u-boot-dtb.img can now be flashed to debian image partition mounted on host machine.
- Rockchip Evb-RK3328 (evb-rk3328)
- Pine64 Rock64 (rock64-rk3328)
- Firefly-RK3328 (roc-cc-rk3328)
+ - Radxa Rockpi E (rock-pi-e-rk3328)
* rk3368
- GeekBox (geekbox)
- PX5 EVB (evb-px5)
Note: for rockchip 32-bit platforms the U-Boot proper image
is u-boot-dtb.img
+SPI
+^^^
+
+Generating idbloader for SPI boot would require to input a multi image
+image format to mkimage tool instead of concerting (like for MMC boot).
+
+SPL-alone SPI boot image::
+
+ ./tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader.img
+
+TPL+SPL SPI boot image::
+
+ ./tools/mkimage -n rk3399 -T rkspi -d tpl/u-boot-tpl.bin:spl/u-boot-spl.bin idbloader.img
+
+Copy SPI boot images into SD card and boot from SD::
+
+ sf probe
+ load mmc 1:1 $kernel_addr_r idbloader.img
+ sf erase 0 +$filesize
+ sf write $kernel_addr_r 0 ${filesize}
+ load mmc 1:1 ${kernel_addr_r} u-boot.itb
+ sf erase 0x60000 +$filesize
+ sf write $kernel_addr_r 0x60000 ${filesize}
+
TODO
----
- Add missing SoC's with it boards list
.. Jagan Teki <jagan@amarulasolutions.com>
-.. Sunday 24 May 2020 10:08:41 PM IST
+.. Tuesday 02 June 2020 12:18:57 AM IST
4. SiFive SPI Driver.
5. MMC SPI Driver for MMC/SD support.
-TODO:
-
-1. U-Boot expects the serial console device entry to be present under /chosen
- DT node. Without a serial console U-Boot will panic. Example:
-
-.. code-block:: none
-
- chosen {
- stdout-path = "/soc/serial@10010000:115200";
- };
+Booting from MMC using FSBL
+---------------------------
Building
--------
.. code-block:: none
- export ARCH=riscv
export CROSS_COMPILE=<riscv64 toolchain prefix>
3. make sifive_fu540_defconfig
.. code-block:: none
-
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<path to u-boot-dtb.bin>
+
make PLATFORM=generic FW_PAYLOAD_PATH=<path to u-boot-dtb.bin>
More detailed description of steps required to build FW_PAYLOAD firmware
is beyond the scope of this document. Please refer OpenSBI documenation.
Please press Enter to activate this console.
/ #
+
+Booting from MMC using U-Boot SPL
+---------------------------------
+
+Building
+--------
+
+Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
+cloned and built for FU540 as below:
+
+.. code-block:: console
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=generic
+ export OPENSBI=<path to opensbi/build/platform/generic/firmware/fw_dynamic.bin>
+
+Now build the U-Boot SPL and U-Boot proper
+
+.. code-block:: console
+
+ cd <U-Boot-dir>
+ make sifive_fu540_defconfig
+ make
+
+This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
+
+
+Flashing
+--------
+
+ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type
+5B193300-FC78-40CD-8002-E86C45580B47
+
+U-Boot SPL expects a U-Boot FIT image (u-boot.itb) from a partition with GUID
+type 2E54B353-1271-4842-806F-E436D6AF6985
+
+FIT image (u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
+device tree blob (hifive-unleashed-a00.dtb)
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: none
+
+ # sudo sgdisk --clear \
+ > --set-alignment=2 \
+ > --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
+ > --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
+ > --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \
+ > /dev/sda
+
+Program the SD card
+
+.. code-block:: none
+
+ sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
+ sudo dd if=u-boot.itb of=/dev/sda seek=2082
+
+Booting
+-------
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample boot log from HiFive Unleashed board
+-------------------------------------------
+
+.. code-block:: none
+
+ U-Boot SPL 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530)
+ Trying to boot from MMC1
+
+
+ U-Boot 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530)
+
+ CPU: rv64imafdc
+ Model: SiFive HiFive Unleashed A00
+ DRAM: 8 GiB
+ MMC: spi@10050000:mmc@0: 0
+ In: serial@10010000
+ Out: serial@10010000
+ Err: serial@10010000
+ Net: eth0: ethernet@10090000
+ Hit any key to stop autoboot: 0
+ => version
+ U-Boot 2020.04-rc2-00109-g63efc7e07e-dirty (Apr 30 2020 - 13:52:36 +0530)
+
+ riscv64-unknown-linux-gnu-gcc (crosstool-NG 1.24.0.37-3f461da) 9.2.0
+ GNU ld (crosstool-NG 1.24.0.37-3f461da) 2.32
+ => mmc info
+ Device: spi@10050000:mmc@0
+ Manufacturer ID: 3
+ OEM: 5344
+ Name: SC16G
+ Bus Speed: 20000000
+ Mode: SD Legacy
+ Rd Block Len: 512
+ SD version 2.0
+ High Capacity: Yes
+ Capacity: 14.8 GiB
+ Bus Width: 1-bit
+ Erase Group Size: 512 Bytes
+ => mmc part
+
+ Partition Map for MMC device 0 -- Partition Type: EFI
+
+ Part Start LBA End LBA Name
+ Attributes
+ Type GUID
+ Partition GUID
+ 1 0x00000022 0x00000821 "loader1"
+ attrs: 0x0000000000000000
+ type: 5b193300-fc78-40cd-8002-e86c45580b47
+ guid: 66e2b5d2-74db-4df8-ad6f-694b3617f87f
+ 2 0x00000822 0x00002821 "loader2"
+ attrs: 0x0000000000000000
+ type: 2e54b353-1271-4842-806f-e436d6af6985
+ guid: 8befaeaf-bca0-435d-b002-e201f37c0a2f
+ 3 0x00002822 0x01dacbde "rootfs"
+ attrs: 0x0000000000000000
+ type: 0fc63daf-8483-4772-8e79-3d69d8477de4
+ type: linux
+ guid: 9faa81b6-39b1-4418-af5e-89c48f29c20d
.. code-block:: bash
$ export CROSS_COMPILE=arm-linux-gnueabi-
- $ export ARCH=arm
$ make colibri_imx7_emmc_defconfig # For NAND: colibri_imx7_defconfig
$ make
No dm conversion yet::
drivers/spi/fsl_espi.c
- drivers/spi/lpc32xx_ssp.c
- drivers/spi/sh_spi.c
drivers/spi/soft_spi_legacy.c
* Status: In progress
b. Configure and build U-Boot with verified boot enabled:
- export ARCH=arm
export UBOOT=/path/to/u-boot
cd $UBOOT
# You can add -j10 if you have 10 CPUs to make it faster
config BOOTCOUNT_EXT
bool "Boot counter on EXT filesystem"
+ depends on FS_EXT4
+ select EXT4_WRITE
help
Add support for maintaining boot count in a file on an EXT
filesystem.
#define PRCI_COREPLLCFG0_LOCK_SHIFT 31
#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
+/* COREPLLCFG1 */
+#define PRCI_COREPLLCFG1_OFFSET 0x8
+#define PRCI_COREPLLCFG1_CKE_SHIFT 31
+#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
+
/* DDRPLLCFG0 */
#define PRCI_DDRPLLCFG0_OFFSET 0xc
#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
/* DDRPLLCFG1 */
#define PRCI_DDRPLLCFG1_OFFSET 0x10
-#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
+#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
/* GEMGXLPLLCFG0 */
/* GEMGXLPLLCFG1 */
#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
-#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
+#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
/* CORECLKSEL */
(0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
/* CLKMUXSTATUSREG */
-#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
+#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
(0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
+/* PROCMONCFG */
+#define PRCI_PROCMONCFG_OFFSET 0xF0
+#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24
+#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \
+ (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT)
+
/*
* Private structures
*/
* @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
* @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
* @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
+ * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
+ * @release_reset: fn ptr to code to release clock reset
*
* @enable_bypass and @disable_bypass are used for WRPLL instances
* that contain a separate external glitchless clock mux downstream
void (*enable_bypass)(struct __prci_data *pd);
void (*disable_bypass)(struct __prci_data *pd);
u8 cfg0_offs;
+ u8 cfg1_offs;
+ void (*release_reset)(struct __prci_data *pd);
};
struct __prci_clock;
unsigned long *parent_rate);
unsigned long (*recalc_rate)(struct __prci_clock *pc,
unsigned long parent_rate);
+ int (*enable_clk)(struct __prci_clock *pc, bool enable);
};
/**
}
/**
- * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI
+ * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
* @pd: PRCI context
* @pwd: PRCI WRPLL metadata
*
* Context: Any context. Caller must prevent the records pointed to by
* @pd and @pwd from changing during execution.
*/
-static void __prci_wrpll_read_cfg(struct __prci_data *pd,
- struct __prci_wrpll_data *pwd)
+static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd)
{
__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
}
/**
- * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI
+ * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
* @pd: PRCI context
* @pwd: PRCI WRPLL metadata
* @c: WRPLL configuration record to write
* Context: Any context. Caller must prevent the records pointed to by
* @pd and @pwd from changing during execution.
*/
-static void __prci_wrpll_write_cfg(struct __prci_data *pd,
- struct __prci_wrpll_data *pwd,
- struct wrpll_cfg *c)
+static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+ struct wrpll_cfg *c)
{
__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
memcpy(&pwd->c, c, sizeof(*c));
}
+/**
+ * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
+ * into the PRCI
+ * @pd: PRCI context
+ * @pwd: PRCI WRPLL metadata
+ * @enable: Clock enable or disable value
+ */
+static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+ u32 enable)
+{
+ __prci_writel(enable, pwd->cfg1_offs, pd);
+}
+
/* Core clock mux control */
/**
if (pwd->enable_bypass)
pwd->enable_bypass(pd);
- __prci_wrpll_write_cfg(pd, pwd, &pwd->c);
+ __prci_wrpll_write_cfg0(pd, pwd, &pwd->c);
udelay(wrpll_calc_max_lock_us(&pwd->c));
return 0;
}
+static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable)
+{
+ struct __prci_wrpll_data *pwd = pc->pwd;
+ struct __prci_data *pd = pc->pd;
+
+ if (enable) {
+ __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
+
+ if (pwd->release_reset)
+ pwd->release_reset(pd);
+ } else {
+ u32 r;
+
+ r = __prci_readl(pd, pwd->cfg1_offs);
+ r &= ~PRCI_COREPLLCFG1_CKE_MASK;
+
+ __prci_wrpll_write_cfg1(pd, pwd, r);
+ }
+
+ return 0;
+}
+
static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
.set_rate = sifive_fu540_prci_wrpll_set_rate,
.round_rate = sifive_fu540_prci_wrpll_round_rate,
.recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
-};
-
-static const struct __prci_clock_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
- .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
+ .enable_clk = sifive_fu540_prci_clock_enable,
};
/* TLCLKSEL clock integration */
.recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
};
+/**
+ * __prci_ddr_release_reset() - Release DDR reset
+ * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg
+ *
+ */
+static void __prci_ddr_release_reset(struct __prci_data *pd)
+{
+ u32 v;
+
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK;
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ /* HACK to get the '1 full controller clock cycle'. */
+ asm volatile ("fence");
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= (PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK |
+ PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK |
+ PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK);
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ /* HACK to get the '1 full controller clock cycle'. */
+ asm volatile ("fence");
+
+ /*
+ * These take like 16 cycles to actually propagate. We can't go sending
+ * stuff before they come out of reset. So wait.
+ */
+ for (int i = 0; i < 256; i++)
+ asm volatile ("nop");
+}
+
+/**
+ * __prci_ethernet_release_reset() - Release ethernet reset
+ * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
+ *
+ */
+static void __prci_ethernet_release_reset(struct __prci_data *pd)
+{
+ u32 v;
+
+ /* Release GEMGXL reset */
+ v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET);
+ v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK;
+ __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd);
+
+ /* Procmon => core clock */
+ __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
+ pd);
+}
+
/*
* PRCI integration data for each WRPLL instance
*/
static struct __prci_wrpll_data __prci_corepll_data = {
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
.enable_bypass = __prci_coreclksel_use_hfclk,
.disable_bypass = __prci_coreclksel_use_corepll,
};
static struct __prci_wrpll_data __prci_ddrpll_data = {
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
+ .release_reset = __prci_ddr_release_reset,
};
static struct __prci_wrpll_data __prci_gemgxlpll_data = {
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
+ .release_reset = __prci_ethernet_release_reset,
};
/*
[PRCI_CLK_DDRPLL] = {
.name = "ddrpll",
.parent_name = "hfclk",
- .ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
+ .ops = &sifive_fu540_prci_wrpll_clk_ops,
.pwd = &__prci_ddrpll_data,
},
[PRCI_CLK_GEMGXLPLL] = {
return rate;
}
+static int sifive_fu540_prci_enable(struct clk *clk)
+{
+ struct __prci_clock *pc;
+ int ret = 0;
+
+ if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
+ return -ENXIO;
+
+ pc = &__prci_init_clocks[clk->id];
+ if (!pc->pd)
+ return -ENXIO;
+
+ if (pc->ops->enable_clk)
+ ret = pc->ops->enable_clk(pc, 1);
+
+ return ret;
+}
+
+static int sifive_fu540_prci_disable(struct clk *clk)
+{
+ struct __prci_clock *pc;
+ int ret = 0;
+
+ if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
+ return -ENXIO;
+
+ pc = &__prci_init_clocks[clk->id];
+ if (!pc->pd)
+ return -ENXIO;
+
+ if (pc->ops->enable_clk)
+ ret = pc->ops->enable_clk(pc, 0);
+
+ return ret;
+}
+
static int sifive_fu540_prci_probe(struct udevice *dev)
{
int i, err;
pc = &__prci_init_clocks[i];
pc->pd = pd;
if (pc->pwd)
- __prci_wrpll_read_cfg(pd, pc->pwd);
+ __prci_wrpll_read_cfg0(pd, pc->pwd);
}
return 0;
static struct clk_ops sifive_fu540_prci_ops = {
.set_rate = sifive_fu540_prci_set_rate,
.get_rate = sifive_fu540_prci_get_rate,
+ .enable = sifive_fu540_prci_enable,
+ .disable = sifive_fu540_prci_disable,
};
static const struct udevice_id sifive_fu540_prci_ids[] = {
input and update LEDs if the keyboard has them.
config SPL_DM_KEYBOARD
- bool "Enable driver model keyboard support"
+ bool "Enable driver model keyboard support for SPL"
depends on SPL_DM
help
This adds a uclass for keyboards and implements keyboard support
input and update LEDs if the keyboard has them.
config TPL_DM_KEYBOARD
- bool "Enable driver model keyboard support"
+ bool "Enable driver model keyboard support for TPL"
depends on TPL_DM
help
This adds a uclass for keyboards and implements keyboard support
addressing and a length or through child-nodes that are generated
based on the e-fuse map retrieved from the DTS.
+config SIFIVE_OTP
+ bool "SiFive eMemory OTP driver"
+ depends on MISC
+ help
+ Enable support for reading and writing the eMemory OTP on the
+ SiFive SoCs.
+
config VEXPRESS_CONFIG
bool "Enable support for Arm Versatile Express config bus"
depends on MISC
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
+obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
obj-$(CONFIG_STM32MP_FUSE) += stm32mp_fuse.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
+ * One-Time-Programmable (OTP) memory used within the SiFive FU540.
+ * It is documented in the FU540 manual here:
+ * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
+ *
+ * Copyright (C) 2018 Philipp Hug <philipp@hug.cx>
+ * Copyright (C) 2018 Joey Hewitt <joey@joeyhewitt.com>
+ *
+ * Copyright (C) 2020 SiFive, Inc
+ */
+
+/*
+ * The FU540 stores 4096x32 bit (16KiB) values.
+ * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
+ * Right now first 1KiB is used to store only serial number.
+ */
+
+#include <common.h>
+#include <dm/device.h>
+#include <dm/read.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <misc.h>
+
+#define BYTES_PER_FUSE 4
+
+#define PA_RESET_VAL 0x00
+#define PAS_RESET_VAL 0x00
+#define PAIO_RESET_VAL 0x00
+#define PDIN_RESET_VAL 0x00
+#define PTM_RESET_VAL 0x00
+
+#define PCLK_ENABLE_VAL BIT(0)
+#define PCLK_DISABLE_VAL 0x00
+
+#define PWE_WRITE_ENABLE BIT(0)
+#define PWE_WRITE_DISABLE 0x00
+
+#define PTM_FUSE_PROGRAM_VAL BIT(1)
+
+#define PCE_ENABLE_INPUT BIT(0)
+#define PCE_DISABLE_INPUT 0x00
+
+#define PPROG_ENABLE_INPUT BIT(0)
+#define PPROG_DISABLE_INPUT 0x00
+
+#define PTRIM_ENABLE_INPUT BIT(0)
+#define PTRIM_DISABLE_INPUT 0x00
+
+#define PDSTB_DEEP_STANDBY_ENABLE BIT(0)
+#define PDSTB_DEEP_STANDBY_DISABLE 0x00
+
+/* Tpw - Program Pulse width delay */
+#define TPW_DELAY 20
+
+/* Tpwi - Program Pulse interval delay */
+#define TPWI_DELAY 5
+
+/* Tasp - Program address setup delay */
+#define TASP_DELAY 1
+
+/* Tcd - read data access delay */
+#define TCD_DELAY 40
+
+/* Tkl - clok pulse low delay */
+#define TKL_DELAY 10
+
+/* Tms - PTM mode setup delay */
+#define TMS_DELAY 1
+
+struct sifive_otp_regs {
+ u32 pa; /* Address input */
+ u32 paio; /* Program address input */
+ u32 pas; /* Program redundancy cell selection input */
+ u32 pce; /* OTP Macro enable input */
+ u32 pclk; /* Clock input */
+ u32 pdin; /* Write data input */
+ u32 pdout; /* Read data output */
+ u32 pdstb; /* Deep standby mode enable input (active low) */
+ u32 pprog; /* Program mode enable input */
+ u32 ptc; /* Test column enable input */
+ u32 ptm; /* Test mode enable input */
+ u32 ptm_rep;/* Repair function test mode enable input */
+ u32 ptr; /* Test row enable input */
+ u32 ptrim; /* Repair function enable input */
+ u32 pwe; /* Write enable input (defines program cycle) */
+};
+
+struct sifive_otp_platdata {
+ struct sifive_otp_regs __iomem *regs;
+ u32 total_fuses;
+};
+
+/*
+ * offset and size are assumed aligned to the size of the fuses (32-bit).
+ */
+static int sifive_otp_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
+
+ /* Check if offset and size are multiple of BYTES_PER_FUSE */
+ if ((size % BYTES_PER_FUSE) || (offset % BYTES_PER_FUSE)) {
+ printf("%s: size and offset must be multiple of 4.\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ int fuseidx = offset / BYTES_PER_FUSE;
+ int fusecount = size / BYTES_PER_FUSE;
+
+ /* check bounds */
+ if (offset < 0 || size < 0)
+ return -EINVAL;
+ if (fuseidx >= plat->total_fuses)
+ return -EINVAL;
+ if ((fuseidx + fusecount) > plat->total_fuses)
+ return -EINVAL;
+
+ u32 fusebuf[fusecount];
+
+ /* init OTP */
+ writel(PDSTB_DEEP_STANDBY_ENABLE, ®s->pdstb);
+ writel(PTRIM_ENABLE_INPUT, ®s->ptrim);
+ writel(PCE_ENABLE_INPUT, ®s->pce);
+
+ /* read all requested fuses */
+ for (unsigned int i = 0; i < fusecount; i++, fuseidx++) {
+ writel(fuseidx, ®s->pa);
+
+ /* cycle clock to read */
+ writel(PCLK_ENABLE_VAL, ®s->pclk);
+ ndelay(TCD_DELAY * 1000);
+ writel(PCLK_DISABLE_VAL, ®s->pclk);
+ ndelay(TKL_DELAY * 1000);
+
+ /* read the value */
+ fusebuf[i] = readl(®s->pdout);
+ }
+
+ /* shut down */
+ writel(PCE_DISABLE_INPUT, ®s->pce);
+ writel(PTRIM_DISABLE_INPUT, ®s->ptrim);
+ writel(PDSTB_DEEP_STANDBY_DISABLE, ®s->pdstb);
+
+ /* copy out */
+ memcpy(buf, fusebuf, size);
+
+ return size;
+}
+
+/*
+ * Caution:
+ * OTP can be written only once, so use carefully.
+ *
+ * offset and size are assumed aligned to the size of the fuses (32-bit).
+ */
+static int sifive_otp_write(struct udevice *dev, int offset,
+ const void *buf, int size)
+{
+ struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
+
+ /* Check if offset and size are multiple of BYTES_PER_FUSE */
+ if ((size % BYTES_PER_FUSE) || (offset % BYTES_PER_FUSE)) {
+ printf("%s: size and offset must be multiple of 4.\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ int fuseidx = offset / BYTES_PER_FUSE;
+ int fusecount = size / BYTES_PER_FUSE;
+ u32 *write_buf = (u32 *)buf;
+ u32 write_data;
+ int i, pas, bit;
+
+ /* check bounds */
+ if (offset < 0 || size < 0)
+ return -EINVAL;
+ if (fuseidx >= plat->total_fuses)
+ return -EINVAL;
+ if ((fuseidx + fusecount) > plat->total_fuses)
+ return -EINVAL;
+
+ /* init OTP */
+ writel(PDSTB_DEEP_STANDBY_ENABLE, ®s->pdstb);
+ writel(PTRIM_ENABLE_INPUT, ®s->ptrim);
+
+ /* reset registers */
+ writel(PCLK_DISABLE_VAL, ®s->pclk);
+ writel(PA_RESET_VAL, ®s->pa);
+ writel(PAS_RESET_VAL, ®s->pas);
+ writel(PAIO_RESET_VAL, ®s->paio);
+ writel(PDIN_RESET_VAL, ®s->pdin);
+ writel(PWE_WRITE_DISABLE, ®s->pwe);
+ writel(PTM_FUSE_PROGRAM_VAL, ®s->ptm);
+ ndelay(TMS_DELAY * 1000);
+
+ writel(PCE_ENABLE_INPUT, ®s->pce);
+ writel(PPROG_ENABLE_INPUT, ®s->pprog);
+
+ /* write all requested fuses */
+ for (i = 0; i < fusecount; i++, fuseidx++) {
+ writel(fuseidx, ®s->pa);
+ write_data = *(write_buf++);
+
+ for (pas = 0; pas < 2; pas++) {
+ writel(pas, ®s->pas);
+
+ for (bit = 0; bit < 32; bit++) {
+ writel(bit, ®s->paio);
+ writel(((write_data >> bit) & 1),
+ ®s->pdin);
+ ndelay(TASP_DELAY * 1000);
+
+ writel(PWE_WRITE_ENABLE, ®s->pwe);
+ udelay(TPW_DELAY);
+ writel(PWE_WRITE_DISABLE, ®s->pwe);
+ udelay(TPWI_DELAY);
+ }
+ }
+
+ writel(PAS_RESET_VAL, ®s->pas);
+ }
+
+ /* shut down */
+ writel(PWE_WRITE_DISABLE, ®s->pwe);
+ writel(PPROG_DISABLE_INPUT, ®s->pprog);
+ writel(PCE_DISABLE_INPUT, ®s->pce);
+ writel(PTM_RESET_VAL, ®s->ptm);
+
+ writel(PTRIM_DISABLE_INPUT, ®s->ptrim);
+ writel(PDSTB_DEEP_STANDBY_DISABLE, ®s->pdstb);
+
+ return size;
+}
+
+static int sifive_otp_ofdata_to_platdata(struct udevice *dev)
+{
+ struct sifive_otp_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ plat->regs = dev_read_addr_ptr(dev);
+
+ ret = dev_read_u32(dev, "fuse-count", &plat->total_fuses);
+ if (ret < 0) {
+ pr_err("\"fuse-count\" not found\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct misc_ops sifive_otp_ops = {
+ .read = sifive_otp_read,
+ .write = sifive_otp_write,
+};
+
+static const struct udevice_id sifive_otp_ids[] = {
+ { .compatible = "sifive,fu540-c000-otp" },
+ {}
+};
+
+U_BOOT_DRIVER(sifive_otp) = {
+ .name = "sifive_otp",
+ .id = UCLASS_MISC,
+ .of_match = sifive_otp_ids,
+ .ofdata_to_platdata = sifive_otp_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct sifive_otp_platdata),
+ .ops = &sifive_otp_ops,
+};
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+static SPINAND_OP_VARIANTS(write_cache_x4_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_x4_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+/**
+ * Backward compatibility for 1st generation Serial NAND devices
+ * which don't support Quad Program Load operation.
+ */
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD(false, 0, NULL, 0));
-static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section,
+static int tx58cxgxsxraix_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section > 0)
return 0;
}
-static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section,
+static int tx58cxgxsxraix_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section > 0)
return 0;
}
-static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = {
- .ecc = tc58cxgxsx_ooblayout_ecc,
- .rfree = tc58cxgxsx_ooblayout_free,
+static const struct mtd_ooblayout_ops tx58cxgxsxraix_ooblayout = {
+ .ecc = tx58cxgxsxraix_ooblayout_ecc,
+ .rfree = tx58cxgxsxraix_ooblayout_free,
};
-static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand,
+static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
struct nand_device *nand = spinand_to_nand(spinand);
}
static const struct spinand_info toshiba_spinand_table[] = {
- /* 3.3V 1Gb */
- SPINAND_INFO("TC58CVG0S3", 0xC2,
+ /* 3.3V 1Gb (1st generation) */
+ SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2,
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
- SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- tc58cxgxsx_ecc_get_status)),
- /* 3.3V 2Gb */
- SPINAND_INFO("TC58CVG1S3", 0xCB,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 3.3V 2Gb (1st generation) */
+ SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB,
NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
- SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- tc58cxgxsx_ecc_get_status)),
- /* 3.3V 4Gb */
- SPINAND_INFO("TC58CVG2S0", 0xCD,
- NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
- NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- 0,
- SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- tc58cxgxsx_ecc_get_status)),
- /* 3.3V 4Gb */
- SPINAND_INFO("TC58CVG2S0", 0xED,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 3.3V 4Gb (1st generation) */
+ SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD,
NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
- SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- tc58cxgxsx_ecc_get_status)),
- /* 1.8V 1Gb */
- SPINAND_INFO("TC58CYG0S3", 0xB2,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 1.8V 1Gb (1st generation) */
+ SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2,
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
- SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- tc58cxgxsx_ecc_get_status)),
- /* 1.8V 2Gb */
- SPINAND_INFO("TC58CYG1S3", 0xBB,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 1.8V 2Gb (1st generation) */
+ SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB,
NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
- SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- tc58cxgxsx_ecc_get_status)),
- /* 1.8V 4Gb */
- SPINAND_INFO("TC58CYG2S0", 0xBD,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 1.8V 4Gb (1st generation) */
+ SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD,
NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
- SPINAND_ECCINFO(&tc58cxgxsx_ooblayout,
- tc58cxgxsx_ecc_get_status)),
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+
+ /*
+ * 2nd generation serial nand has HOLD_D which is equivalent to
+ * QE_BIT.
+ */
+ /* 3.3V 1Gb (2nd generation) */
+ SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2,
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_x4_variants,
+ &update_cache_x4_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 3.3V 2Gb (2nd generation) */
+ SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB,
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_x4_variants,
+ &update_cache_x4_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 3.3V 4Gb (2nd generation) */
+ SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED,
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_x4_variants,
+ &update_cache_x4_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 3.3V 8Gb (2nd generation) */
+ SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4,
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_x4_variants,
+ &update_cache_x4_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 1.8V 1Gb (2nd generation) */
+ SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2,
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_x4_variants,
+ &update_cache_x4_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 1.8V 2Gb (2nd generation) */
+ SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB,
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_x4_variants,
+ &update_cache_x4_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 1.8V 4Gb (2nd generation) */
+ SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD,
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_x4_variants,
+ &update_cache_x4_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+ /* 1.8V 8Gb (2nd generation) */
+ SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4,
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_x4_variants,
+ &update_cache_x4_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
};
static int toshiba_spinand_detect(struct spinand_device *spinand)
return log_ret(sf_get_ops(dev)->erase(dev, offset, len));
}
-int spl_flash_get_sw_write_prot(struct udevice *dev)
-{
- struct dm_spi_flash_ops *ops = sf_get_ops(dev);
-
- if (!ops->get_sw_write_prot)
- return -ENOSYS;
- return log_ret(ops->get_sw_write_prot(dev));
-}
-
/*
* TODO(sjg@chromium.org): This is an old-style function. We should remove
* it when all SPI flash drivers use dm
#define JEDEC_MFR(info) ((info)->id[0])
#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
-/* Get software write-protect value (BP bits) */
-int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
-
-
#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
int spi_flash_mtd_register(struct spi_flash *flash);
void spi_flash_mtd_unregister(void);
+#else
+static inline int spi_flash_mtd_register(struct spi_flash *flash)
+{
+ return 0;
+}
+
+static inline void spi_flash_mtd_unregister(void)
+{
+}
#endif
+
#endif /* _SF_INTERNAL_H_ */
if (ret)
goto err_read_id;
-#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
- ret = spi_flash_mtd_register(flash);
-#endif
+ if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
+ ret = spi_flash_mtd_register(flash);
err_read_id:
spi_release_bus(spi);
void spi_flash_free(struct spi_flash *flash)
{
-#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
- spi_flash_mtd_unregister();
-#endif
+ if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
+ spi_flash_mtd_unregister();
+
spi_free_slave(flash->spi);
free(flash);
}
return mtd->_erase(mtd, &instr);
}
-static int spi_flash_std_get_sw_write_prot(struct udevice *dev)
-{
- struct spi_flash *flash = dev_get_uclass_priv(dev);
-
- return spi_flash_cmd_get_sw_write_prot(flash);
-}
-
int spi_flash_std_probe(struct udevice *dev)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
- struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
struct spi_flash *flash;
flash = dev_get_uclass_priv(dev);
flash->dev = dev;
flash->spi = slave;
- debug("%s: slave=%p, cs=%d\n", __func__, slave, plat->cs);
return spi_flash_probe_slave(flash);
}
static int spi_flash_std_remove(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
- spi_flash_mtd_unregister();
-#endif
+ if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
+ spi_flash_mtd_unregister();
+
return 0;
}
.read = spi_flash_std_read,
.write = spi_flash_std_write,
.erase = spi_flash_std_erase,
- .get_sw_write_prot = spi_flash_std_get_sw_write_prot,
};
static const struct udevice_id spi_flash_std_ids[] = {
size_t page_offset, page_remain, i;
ssize_t ret;
+#ifdef CONFIG_SPI_FLASH_SST
+ /* sst nor chips use AAI word program */
+ if (nor->info->flags & SST_WRITE)
+ return sst_write(mtd, to, len, retlen, buf);
+#endif
+
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
if (!len)
mtd->size = params.size;
mtd->_erase = spi_nor_erase;
mtd->_read = spi_nor_read;
+ mtd->_write = spi_nor_write;
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
/* NOR protection support for STmicro/Micron chips and similar */
nor->flash_unlock = sst26_unlock;
nor->flash_is_locked = sst26_is_locked;
}
-
- /* sst nor chips use AAI word program */
- if (info->flags & SST_WRITE)
- mtd->_write = sst_write;
- else
#endif
- mtd->_write = spi_nor_write;
if (info->flags & USE_FSR)
nor->flags |= SNOR_F_USE_FSR;
return 0;
}
-
-/* U-Boot specific functions, need to extend MTD to support these */
-int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
-{
- int sr = read_sr(nor);
-
- if (sr < 0)
- return sr;
-
- return (sr >> 2) & 7;
-}
return 0;
}
-
-/* U-Boot specific functions, need to extend MTD to support these */
-int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
-{
- return -ENOTSUPP;
-}
H3_EMAC,
A64_EMAC,
R40_GMAC,
+ H6_EMAC,
};
struct emac_dma_desc {
if (priv->variant == R40_GMAC) {
/* Select RGMII for R40 */
reg = readl(priv->sysctl_reg + 0x164);
- reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
- CCM_GMAC_CTRL_GPIT_RGMII |
- CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
+ reg |= SC_ETCS_INT_GMII |
+ SC_EPIT |
+ (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
writel(reg, priv->sysctl_reg + 0x164);
return 0;
reg = readl(priv->sysctl_reg + 0x30);
- if (priv->variant == H3_EMAC) {
+ if (priv->variant == H3_EMAC || priv->variant == H6_EMAC) {
ret = sun8i_emac_set_syscon_ephy(priv, ®);
if (ret)
return ret;
}
reg &= ~(SC_ETCS_MASK | SC_EPIT);
- if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
+ if (priv->variant == H3_EMAC ||
+ priv->variant == A64_EMAC ||
+ priv->variant == H6_EMAC)
reg &= ~SC_RMII_EN;
switch (priv->interface) {
break;
case PHY_INTERFACE_MODE_RMII:
if (priv->variant == H3_EMAC ||
- priv->variant == A64_EMAC) {
+ priv->variant == A64_EMAC ||
+ priv->variant == H6_EMAC) {
reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
break;
}
if (priv->variant == H3_EMAC)
sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
- else if (priv->variant == R40_GMAC)
+ else if (priv->variant == R40_GMAC || priv->variant == H6_EMAC)
sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
else
sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
.data = (uintptr_t)A83T_EMAC },
{.compatible = "allwinner,sun8i-r40-gmac",
.data = (uintptr_t)R40_GMAC },
+ {.compatible = "allwinner,sun50i-h6-emac",
+ .data = (uintptr_t)H6_EMAC },
{ }
};
return ret;
}
- if (data->cfg->type == sun8i_a83t_phy) {
+ if (data->cfg->type == sun8i_a83t_phy ||
+ data->cfg->type == sun50i_h6_phy) {
if (phy->id == 0) {
val = readl(data->base + data->cfg->phyctl_offset);
val |= PHY_CTL_VBUSVLDEXT;
int ret;
if (phy->id == 0) {
- if (data->cfg->type == sun8i_a83t_phy) {
+ if (data->cfg->type == sun8i_a83t_phy ||
+ data->cfg->type == sun50i_h6_phy) {
void __iomem *phyctl = data->base +
data->cfg->phyctl_offset;
This driver is for the sdram memory interface with the SEMC.
source "drivers/ram/rockchip/Kconfig"
+source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
+
+obj-$(CONFIG_RAM_SIFIVE) += sifive/
--- /dev/null
+config RAM_SIFIVE
+ bool "Ram drivers support for SiFive SoCs"
+ depends on RAM && RISCV
+ default y
+ help
+ This enables support for ram drivers of SiFive SoCs.
+
+config SIFIVE_FU540_DDR
+ bool "SiFive FU540 DDR driver"
+ depends on RAM_SIFIVE
+ default y if TARGET_SIFIVE_FU540
+ help
+ This enables DDR support for the platforms based on SiFive FU540 SoC.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020 SiFive, Inc
+#
+
+obj-$(CONFIG_SIFIVE_FU540_DDR) += fu540_ddr.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * (C) Copyright 2020 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <wait_bit.h>
+#include <linux/bitops.h>
+
+#define DENALI_CTL_0 0
+#define DENALI_CTL_21 21
+#define DENALI_CTL_120 120
+#define DENALI_CTL_132 132
+#define DENALI_CTL_136 136
+#define DENALI_CTL_170 170
+#define DENALI_CTL_181 181
+#define DENALI_CTL_182 182
+#define DENALI_CTL_184 184
+#define DENALI_CTL_208 208
+#define DENALI_CTL_209 209
+#define DENALI_CTL_210 210
+#define DENALI_CTL_212 212
+#define DENALI_CTL_214 214
+#define DENALI_CTL_216 216
+#define DENALI_CTL_224 224
+#define DENALI_CTL_225 225
+#define DENALI_CTL_260 260
+
+#define DENALI_PHY_1152 1152
+#define DENALI_PHY_1214 1214
+
+#define PAYLOAD_DEST 0x80000000
+#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL)
+
+#define DRAM_CLASS_OFFSET 8
+#define DRAM_CLASS_DDR4 0xA
+#define OPTIMAL_RMODW_EN_OFFSET 0
+#define DISABLE_RD_INTERLEAVE_OFFSET 16
+#define OUT_OF_RANGE_OFFSET 1
+#define MULTIPLE_OUT_OF_RANGE_OFFSET 2
+#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
+#define MC_INIT_COMPLETE_OFFSET 8
+#define LEVELING_OPERATION_COMPLETED_OFFSET 22
+#define DFI_PHY_WRLELV_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_MODE_OFFSET 24
+#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
+#define VREF_EN_OFFSET 24
+#define PORT_ADDR_PROTECTION_EN_OFFSET 0
+#define AXI0_ADDRESS_RANGE_ENABLE 8
+#define AXI0_RANGE_PROT_BITS_0_OFFSET 24
+#define RDLVL_EN_OFFSET 16
+#define RDLVL_GATE_EN_OFFSET 24
+#define WRLVL_EN_OFFSET 0
+
+#define PHY_RX_CAL_DQ0_0_OFFSET 0
+#define PHY_RX_CAL_DQ1_0_OFFSET 16
+
+struct fu540_ddrctl {
+ volatile u32 denali_ctl[265];
+};
+
+struct fu540_ddrphy {
+ volatile u32 denali_phy[1215];
+};
+
+/**
+ * struct fu540_ddr_info
+ *
+ * @dev : pointer for the device
+ * @info : UCLASS RAM information
+ * @ctl : DDR controller base address
+ * @phy : DDR PHY base address
+ * @ctrl : DDR control base address
+ * @physical_filter_ctrl : DDR physical filter control base address
+ */
+struct fu540_ddr_info {
+ struct udevice *dev;
+ struct ram_info info;
+ struct fu540_ddrctl *ctl;
+ struct fu540_ddrphy *phy;
+ struct clk ddr_clk;
+ u32 *physical_filter_ctrl;
+};
+
+#if defined(CONFIG_SPL_BUILD)
+struct fu540_ddr_params {
+ struct fu540_ddrctl pctl_regs;
+ struct fu540_ddrphy phy_regs;
+};
+
+struct sifive_dmc_plat {
+ struct fu540_ddr_params ddr_params;
+};
+
+/*
+ * TODO : It can be possible to use common sdram_copy_to_reg() API
+ * n: Unit bytes
+ */
+static void sdram_copy_to_reg(volatile u32 *dest,
+ volatile u32 *src, u32 n)
+{
+ int i;
+
+ for (i = 0; i < n / sizeof(u32); i++) {
+ writel(*src, dest);
+ src++;
+ dest++;
+ }
+}
+
+static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
+{
+ u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
+
+ writel(0x0, DENALI_CTL_209 + ctl);
+ writel(end_addr_16kblocks, DENALI_CTL_210 + ctl);
+ writel(0x0, DENALI_CTL_212 + ctl);
+ writel(0x0, DENALI_CTL_214 + ctl);
+ writel(0x0, DENALI_CTL_216 + ctl);
+ setbits_le32(DENALI_CTL_224 + ctl,
+ 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
+ writel(0xFFFFFFFF, DENALI_CTL_225 + ctl);
+ setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE);
+ setbits_le32(DENALI_CTL_208 + ctl,
+ 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
+}
+
+static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
+ u64 ddr_end)
+{
+ volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
+
+ setbits_le32(DENALI_CTL_0 + ctl, 0x1);
+
+ wait_for_bit_le32((void *)ctl + DENALI_CTL_132,
+ BIT(MC_INIT_COMPLETE_OFFSET), false, 100, false);
+
+ /* Disable the BusBlocker in front of the controller AXI slave ports */
+ filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2);
+}
+
+static void fu540_ddr_check_errata(u32 regbase, u32 updownreg)
+{
+ u64 fails = 0;
+ u32 dq = 0;
+ u32 down, up;
+ u8 failc0, failc1;
+ u32 phy_rx_cal_dqn_0_offset;
+
+ for (u32 bit = 0; bit < 2; bit++) {
+ if (bit == 0) {
+ phy_rx_cal_dqn_0_offset =
+ PHY_RX_CAL_DQ0_0_OFFSET;
+ } else {
+ phy_rx_cal_dqn_0_offset =
+ PHY_RX_CAL_DQ1_0_OFFSET;
+ }
+
+ down = (updownreg >>
+ phy_rx_cal_dqn_0_offset) & 0x3F;
+ up = (updownreg >>
+ (phy_rx_cal_dqn_0_offset + 6)) &
+ 0x3F;
+
+ failc0 = ((down == 0) && (up == 0x3F));
+ failc1 = ((up == 0) && (down == 0x3F));
+
+ /* print error message on failure */
+ if (failc0 || failc1) {
+ if (fails == 0)
+ printf("DDR error in fixing up\n");
+
+ fails |= (1 << dq);
+
+ char slicelsc = '0';
+ char slicemsc = '0';
+
+ slicelsc += (dq % 10);
+ slicemsc += (dq / 10);
+ printf("S ");
+ printf("%c", slicemsc);
+ printf("%c", slicelsc);
+
+ if (failc0)
+ printf("U");
+ else
+ printf("D");
+
+ printf("\n");
+ }
+ dq++;
+ }
+}
+
+static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
+{
+ u32 slicebase = 0;
+
+ /* check errata condition */
+ for (u32 slice = 0; slice < 8; slice++) {
+ u32 regbase = slicebase + 34;
+
+ for (u32 reg = 0; reg < 4; reg++) {
+ u32 updownreg = readl(regbase + reg + ddrphyreg);
+
+ fu540_ddr_check_errata(regbase, updownreg);
+ }
+ slicebase += 128;
+ }
+
+ return(0);
+}
+
+static u32 fu540_ddr_get_dram_class(volatile u32 *ctl)
+{
+ u32 reg = readl(DENALI_CTL_0 + ctl);
+
+ return ((reg >> DRAM_CLASS_OFFSET) & 0xF);
+}
+
+static int fu540_ddr_setup(struct udevice *dev)
+{
+ struct fu540_ddr_info *priv = dev_get_priv(dev);
+ struct sifive_dmc_plat *plat = dev_get_platdata(dev);
+ struct fu540_ddr_params *params = &plat->ddr_params;
+ volatile u32 *denali_ctl = priv->ctl->denali_ctl;
+ volatile u32 *denali_phy = priv->phy->denali_phy;
+ const u64 ddr_size = DDR_MEM_SIZE;
+ const u64 ddr_end = PAYLOAD_DEST + ddr_size;
+ int ret, i;
+ u32 physet;
+
+ ret = dev_read_u32_array(dev, "sifive,ddr-params",
+ (u32 *)&plat->ddr_params,
+ sizeof(plat->ddr_params) / sizeof(u32));
+ if (ret) {
+ printf("%s: Cannot read sifive,ddr-params %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ sdram_copy_to_reg(priv->ctl->denali_ctl,
+ params->pctl_regs.denali_ctl,
+ sizeof(struct fu540_ddrctl));
+
+ /* phy reset */
+ for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) {
+ physet = params->phy_regs.denali_phy[i];
+ priv->phy->denali_phy[i] = physet;
+ }
+
+ for (i = 0; i < DENALI_PHY_1152; i++) {
+ physet = params->phy_regs.denali_phy[i];
+ priv->phy->denali_phy[i] = physet;
+ }
+
+ /* Disable read interleave DENALI_CTL_120 */
+ setbits_le32(DENALI_CTL_120 + denali_ctl,
+ 1 << DISABLE_RD_INTERLEAVE_OFFSET);
+
+ /* Disable optimal read/modify/write logic DENALI_CTL_21 */
+ clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 << OPTIMAL_RMODW_EN_OFFSET);
+
+ /* Enable write Leveling DENALI_CTL_170 */
+ setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET)
+ | (1 << DFI_PHY_WRLELV_MODE_OFFSET));
+
+ /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */
+ setbits_le32(DENALI_CTL_181 + denali_ctl,
+ 1 << DFI_PHY_RDLVL_MODE_OFFSET);
+ setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET);
+
+ /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */
+ setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_GATE_EN_OFFSET);
+ setbits_le32(DENALI_CTL_182 + denali_ctl,
+ 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
+
+ if (fu540_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) {
+ /* Enable vref training DENALI_CTL_184 */
+ setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET);
+ }
+
+ /* Mask off leveling completion interrupt DENALI_CTL_136 */
+ setbits_le32(DENALI_CTL_136 + denali_ctl,
+ 1 << LEVELING_OPERATION_COMPLETED_OFFSET);
+
+ /* Mask off MC init complete interrupt DENALI_CTL_136 */
+ setbits_le32(DENALI_CTL_136 + denali_ctl, 1 << MC_INIT_COMPLETE_OFFSET);
+
+ /* Mask off out of range interrupts DENALI_CTL_136 */
+ setbits_le32(DENALI_CTL_136 + denali_ctl, (1 << OUT_OF_RANGE_OFFSET)
+ | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
+
+ /* set up range protection */
+ fu540_ddr_setup_range_protection(denali_ctl, DDR_MEM_SIZE);
+
+ /* Mask off port command error interrupt DENALI_CTL_136 */
+ setbits_le32(DENALI_CTL_136 + denali_ctl,
+ 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET);
+
+ fu540_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
+
+ fu540_ddr_phy_fixup(denali_phy);
+
+ /* check size */
+ priv->info.size = get_ram_size((long *)priv->info.base,
+ DDR_MEM_SIZE);
+
+ debug("%s : %lx\n", __func__, priv->info.size);
+
+ /* check memory access for all memory */
+ if (priv->info.size != DDR_MEM_SIZE) {
+ printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
+ priv->info.size, DDR_MEM_SIZE);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
+
+static int fu540_ddr_probe(struct udevice *dev)
+{
+ struct fu540_ddr_info *priv = dev_get_priv(dev);
+
+#if defined(CONFIG_SPL_BUILD)
+ struct regmap *map;
+ int ret;
+ u32 clock = 0;
+
+ debug("FU540 DDR probe\n");
+ priv->dev = dev;
+
+ ret = regmap_init_mem(dev_ofnode(dev), &map);
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
+ if (ret) {
+ debug("clk get failed %d\n", ret);
+ return ret;
+ }
+
+ ret = dev_read_u32(dev, "clock-frequency", &clock);
+ if (ret) {
+ debug("clock-frequency not found in dt %d\n", ret);
+ return ret;
+ } else {
+ ret = clk_set_rate(&priv->ddr_clk, clock);
+ if (ret < 0) {
+ debug("Could not set DDR clock\n");
+ return ret;
+ }
+ }
+
+ ret = clk_enable(&priv->ddr_clk);
+ priv->ctl = regmap_get_range(map, 0);
+ priv->phy = regmap_get_range(map, 1);
+ priv->physical_filter_ctrl = regmap_get_range(map, 2);
+
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+
+ priv->info.size = 0;
+ return fu540_ddr_setup(dev);
+#else
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.size = DDR_MEM_SIZE;
+#endif
+ return 0;
+}
+
+static int fu540_ddr_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct fu540_ddr_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops fu540_ddr_ops = {
+ .get_info = fu540_ddr_get_info,
+};
+
+static const struct udevice_id fu540_ddr_ids[] = {
+ { .compatible = "sifive,fu540-c000-ddr" },
+ { }
+};
+
+U_BOOT_DRIVER(fu540_ddr) = {
+ .name = "fu540_ddr",
+ .id = UCLASS_RAM,
+ .of_match = fu540_ddr_ids,
+ .ops = &fu540_ddr_ops,
+ .probe = fu540_ddr_probe,
+ .priv_auto_alloc_size = sizeof(struct fu540_ddr_info),
+#if defined(CONFIG_SPL_BUILD)
+ .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat),
+#endif
+};
config DEBUG_UART_ALTERA_JTAGUART
bool "Altera JTAG UART"
+ depends on ALTERA_JTAG_UART
help
Select this to enable a debug UART using the altera_jtag_uart driver.
You will need to provide parameters to make this work. The driver will
config DEBUG_UART_ALTERA_UART
bool "Altera UART"
+ depends on ALTERA_UART
help
Select this to enable a debug UART using the altera_uart driver.
You will need to provide parameters to make this work. The driver will
config DEBUG_UART_ATMEL
bool "Atmel USART"
+ depends on ATMEL_USART
help
Select this to enable a debug UART using the atmel usart driver. You
will need to provide parameters to make this work. The driver will
config DEBUG_UART_NS16550
bool "ns16550"
+ depends on SYS_NS16550
help
Select this to enable a debug UART using the ns16550 driver. You
will need to provide parameters to make this work. The driver will
config DEBUG_UART_S5P
bool "Samsung S5P"
+ depends on ARCH_EXYNOS || ARCH_S5PC1XX
help
Select this to enable a debug UART using the serial_s5p driver. You
will need to provide parameters to make this work. The driver will
config DEBUG_UART_UARTLITE
bool "Xilinx Uartlite"
+ depends on XILINX_UARTLITE
help
Select this to enable a debug UART using the serial_uartlite driver.
You will need to provide parameters to make this work. The driver will
config DEBUG_UART_ARM_DCC
bool "ARM DCC"
+ depends on ARM_DCC
help
Select this to enable a debug UART using the ARM JTAG DCC port.
The DCC port can be used for very early debugging and doesn't require
config DEBUG_MVEBU_A3700_UART
bool "Marvell Armada 3700"
+ depends on MVEBU_A3700_UART
help
Select this to enable a debug UART using the serial_mvebu driver. You
will need to provide parameters to make this work. The driver will
config DEBUG_UART_ZYNQ
bool "Xilinx Zynq"
+ depends on ZYNQ_SERIAL
help
Select this to enable a debug UART using the serial_zynq driver. You
will need to provide parameters to make this work. The driver will
config DEBUG_UART_PL010
bool "pl010"
+ depends on PL01X_SERIAL
help
Select this to enable a debug UART using the pl01x driver with the
PL010 UART type. You will need to provide parameters to make this
config DEBUG_UART_PL011
bool "pl011"
+ depends on PL011_SERIAL
help
Select this to enable a debug UART using the pl01x driver with the
PL011 UART type. You will need to provide parameters to make this
config DEBUG_UART_SIFIVE
bool "SiFive UART"
+ depends on PL01X_SERIAL
help
Select this to enable a debug UART using the serial_sifive driver. You
will need to provide parameters to make this work. The driver will
config DEBUG_UART_OMAP
bool "OMAP uart"
+ depends on OMAP_SERIAL
help
Select this to enable a debug UART using the omap ns16550 driver.
You will need to provide parameters to make this work. The driver
Select this to enable support for ARC UART now typically
only used in Synopsys DesignWare ARC simulators like nSIM.
+config ARM_DCC
+ bool "ARM Debug Communication Channel (DCC) as UART support"
+ depends on ARM
+ help
+ Select this to enable using the ARM DCC as a form of UART.
+
config ATMEL_USART
bool "Atmel USART support"
help
this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
use this driver.
+config FSL_QSPI
+ bool "Freescale QSPI driver"
+ imply SPI_FLASH_BAR
+ help
+ Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ Freescale IP core.
+
config ICH_SPI
bool "Intel ICH SPI driver"
help
help
Enable support for SPI on the MPC8XXX PowerPC SoCs.
+config MSCC_BB_SPI
+ bool "MSCC bitbang SPI driver"
+ depends on SOC_VCOREIII
+ help
+ Enable MSCC bitbang SPI driver. This driver can be used on
+ MSCC SOCs.
+
config MT7621_SPI
bool "MediaTek MT7621 SPI driver"
depends on SOC_MT7628
Enable Soft SPI driver. This driver is to use GPIO simulate
the SPI protocol.
-config MSCC_BB_SPI
- bool "MSCC bitbang SPI driver"
- depends on SOC_VCOREIII
- help
- Enable MSCC bitbang SPI driver. This driver can be used on
- MSCC SOCs.
-
-config CF_SPI
- bool "ColdFire SPI driver"
- help
- Enable the ColdFire SPI driver. This driver can be used on
- some m68k SoCs.
-
config FSL_ESPI
bool "Freescale eSPI driver"
imply SPI_FLASH_BAR
access the SPI interface and SPI NOR flash on platforms embedding
this Freescale eSPI IP core.
-config FSL_QSPI
- bool "Freescale QSPI driver"
- imply SPI_FLASH_BAR
- help
- Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
- used to access the SPI NOR flash on platforms embedding this
- Freescale IP core.
-
config DAVINCI_SPI
bool "Davinci & Keystone SPI driver"
depends on ARCH_DAVINCI || ARCH_KEYSTONE
help
Enable the Davinci SPI driver
-config SH_SPI
- bool "SuperH SPI driver"
- depends on DEPRECATED
- help
- Enable the SuperH SPI controller driver. This driver can be used
- on various SuperH SoCs, such as SH7757.
-
config SH_QSPI
bool "Renesas Quad SPI driver"
help
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
-obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
obj-$(CONFIG_STM32_SPI) += stm32_spi.o
return 0;
}
-void spi_init(void)
-{
-}
-
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
{
}
#endif
-void spi_init(void)
-{
-}
-
void spi_cs_activate(struct spi_slave *slave)
{
_spi_cs_activate(spireg);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * SH SPI driver
- *
- * Copyright (C) 2011-2012 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <console.h>
-#include <malloc.h>
-#include <spi.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-#include "sh_spi.h"
-
-static void sh_spi_write(unsigned long data, unsigned long *reg)
-{
- writel(data, reg);
-}
-
-static unsigned long sh_spi_read(unsigned long *reg)
-{
- return readl(reg);
-}
-
-static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
-{
- unsigned long tmp;
-
- tmp = sh_spi_read(reg);
- tmp |= val;
- sh_spi_write(tmp, reg);
-}
-
-static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
-{
- unsigned long tmp;
-
- tmp = sh_spi_read(reg);
- tmp &= ~val;
- sh_spi_write(tmp, reg);
-}
-
-static void clear_fifo(struct sh_spi *ss)
-{
- sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
- sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
-}
-
-static int recvbuf_wait(struct sh_spi *ss)
-{
- while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
- if (ctrlc())
- return 1;
- udelay(10);
- }
- return 0;
-}
-
-static int write_fifo_empty_wait(struct sh_spi *ss)
-{
- while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
- if (ctrlc())
- return 1;
- udelay(10);
- }
- return 0;
-}
-
-static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
-{
- unsigned long val = 0;
-
- if (cs & 0x01)
- val |= SH_SPI_SSS0;
- if (cs & 0x02)
- val |= SH_SPI_SSS1;
-
- sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
- sh_spi_set_bit(val, &ss->regs->cr4);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct sh_spi *ss;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- ss = spi_alloc_slave(struct sh_spi, bus, cs);
- if (!ss)
- return NULL;
-
- ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
-
- /* SPI sycle stop */
- sh_spi_write(0xfe, &ss->regs->cr1);
- /* CR1 init */
- sh_spi_write(0x00, &ss->regs->cr1);
- /* CR3 init */
- sh_spi_write(0x00, &ss->regs->cr3);
- sh_spi_set_cs(ss, cs);
-
- clear_fifo(ss);
-
- /* 1/8 clock */
- sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
- udelay(10);
-
- return &ss->slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct sh_spi *spi = to_sh_spi(slave);
-
- free(spi);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- struct sh_spi *ss = to_sh_spi(slave);
-
- sh_spi_write(sh_spi_read(&ss->regs->cr1) &
- ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
-}
-
-static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
- unsigned int len, unsigned long flags)
-{
- int i, cur_len, ret = 0;
- int remain = (int)len;
-
- if (len >= SH_SPI_FIFO_SIZE)
- sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
-
- while (remain > 0) {
- cur_len = (remain < SH_SPI_FIFO_SIZE) ?
- remain : SH_SPI_FIFO_SIZE;
- for (i = 0; i < cur_len &&
- !(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
- !(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
- i++)
- sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
-
- cur_len = i;
-
- if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
- /* Abort the transaction */
- flags |= SPI_XFER_END;
- sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
- ret = 1;
- break;
- }
-
- remain -= cur_len;
- tx_data += cur_len;
-
- if (remain > 0)
- write_fifo_empty_wait(ss);
- }
-
- if (flags & SPI_XFER_END) {
- sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
- sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
- udelay(100);
- write_fifo_empty_wait(ss);
- }
-
- return ret;
-}
-
-static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
- unsigned int len, unsigned long flags)
-{
- int i;
-
- if (len > SH_SPI_MAX_BYTE)
- sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
- else
- sh_spi_write(len, &ss->regs->cr3);
-
- sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
- sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
-
- for (i = 0; i < len; i++) {
- if (recvbuf_wait(ss))
- return 0;
-
- rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
- }
- sh_spi_write(0, &ss->regs->cr3);
-
- return 0;
-}
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
-{
- struct sh_spi *ss = to_sh_spi(slave);
- const unsigned char *tx_data = dout;
- unsigned char *rx_data = din;
- unsigned int len = bitlen / 8;
- int ret = 0;
-
- if (flags & SPI_XFER_BEGIN)
- sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
- &ss->regs->cr1);
-
- if (tx_data)
- ret = sh_spi_send(ss, tx_data, len, flags);
-
- if (ret == 0 && rx_data)
- ret = sh_spi_receive(ss, rx_data, len, flags);
-
- if (flags & SPI_XFER_END) {
- sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
- udelay(100);
-
- sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
- &ss->regs->cr1);
- clear_fifo(ss);
- }
-
- return ret;
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- if (!bus && cs < SH_SPI_NUM_CS)
- return 1;
- else
- return 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * SH SPI driver
- *
- * Copyright (C) 2011 Renesas Solutions Corp.
- */
-
-#ifndef __SH_SPI_H__
-#define __SH_SPI_H__
-
-#include <spi.h>
-
-struct sh_spi_regs {
- unsigned long tbr_rbr;
- unsigned long resv1;
- unsigned long cr1;
- unsigned long resv2;
- unsigned long cr2;
- unsigned long resv3;
- unsigned long cr3;
- unsigned long resv4;
- unsigned long cr4;
-};
-
-/* CR1 */
-#define SH_SPI_TBE 0x80
-#define SH_SPI_TBF 0x40
-#define SH_SPI_RBE 0x20
-#define SH_SPI_RBF 0x10
-#define SH_SPI_PFONRD 0x08
-#define SH_SPI_SSDB 0x04
-#define SH_SPI_SSD 0x02
-#define SH_SPI_SSA 0x01
-
-/* CR2 */
-#define SH_SPI_RSTF 0x80
-#define SH_SPI_LOOPBK 0x40
-#define SH_SPI_CPOL 0x20
-#define SH_SPI_CPHA 0x10
-#define SH_SPI_L1M0 0x08
-
-/* CR3 */
-#define SH_SPI_MAX_BYTE 0xFF
-
-/* CR4 */
-#define SH_SPI_TBEI 0x80
-#define SH_SPI_TBFI 0x40
-#define SH_SPI_RBEI 0x20
-#define SH_SPI_RBFI 0x10
-#define SH_SPI_SSS1 0x08
-#define SH_SPI_WPABRT 0x04
-#define SH_SPI_SSS0 0x01
-
-#define SH_SPI_FIFO_SIZE 32
-#define SH_SPI_NUM_CS 4
-
-struct sh_spi {
- struct spi_slave slave;
- struct sh_spi_regs *regs;
-};
-
-static inline struct sh_spi *to_sh_spi(struct spi_slave *slave)
-{
- return container_of(slave, struct sh_spi, slave);
-}
-
-#endif
help
Enable driver model for USB. The USB interface is then implemented
by the USB uclass. Multiple USB controllers of different types
- (XHCI, EHCI) can be attached and used. The 'usb' command works as
- normal. OCHI is not supported at present.
+ (XHCI, EHCI, OHCI) can be attached and used. The 'usb' command works
+ as normal.
Much of the code is shared but with this option enabled the USB
uclass takes care of device enumeration. USB devices can be
* e.g. PCI controllers need this
*/
+#include <asm/cache.h>
#include <asm/io.h>
#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
QEMU based targets.
config VIRTIO_RNG
- bool "virtio rng driver"
- depends on VIRTIO
- help
- This is the virtual random number generator driver. It can be used
- with Qemu based targets.
+ bool "virtio rng driver"
+ depends on DM_RNG
+ depends on VIRTIO
+ default y
+ help
+ This is the virtual random number generator driver. It can be used
+ with QEMU based targets.
endmenu
env_flash = dev_get_uclass_priv(new);
#else
+ if (env_flash)
+ spi_flash_free(env_flash);
+ env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
if (!env_flash) {
- env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
- CONFIG_ENV_SPI_CS,
- CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
- if (!env_flash) {
- env_set_default("spi_flash_probe() failed", 0);
- return -EIO;
- }
+ env_set_default("spi_flash_probe() failed", 0);
+ return -EIO;
}
#endif
return 0;
*/
#undef CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
. = DEFINED(env_offset) ? env_offset : .; \
env/embedded.o(.text*);
-/*
- * Command line configuration.
- */
-
#ifdef CONFIG_IDE
/* ATA */
# define CONFIG_IDE_RESET 1
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
/*
* Miscellaneous configurable options
*/
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
/*
* Miscellaneous configurable options
*/
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
/*
* Miscellaneous configurable options
*/
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#ifdef CONFIG_MMC
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#ifdef CONFIG_MMC
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#define CONFIG_WATCHDOG /* watchdog enabled */
#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-/*
- * Command line configuration.
- */
-
/*
* USB
*/
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-/*
- * Command line configuration.
- */
-
/*
* Miscellaneous configurable options
*/
#include <configs/ti_am335x_common.h>
/* settings we don;t want on this board */
-#undef CONFIG_CMD_SPI
-
-#define CONFIG_CMD_CACHE
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
DFU_ALT_INFO_RAM \
DFU_ALT_INFO_QSPI
#else
-#undef CONFIG_CMD_BOOTD
#ifdef CONFIG_SPL_DFU
#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
#define DFUARGS \
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 32
-#define CONFIG_CMD_TIME
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#define CONFIG_ENV_OVERWRITE
/* Command definition */
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FLASH
#undef CONFIG_IPADDR
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_SYS_MMC_ENV_PART 1
#endif
-#define CONFIG_CMD_TIME
-
#endif /* __CONFIG_H */
*/
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
-/*
- * Commands configuration
- */
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-common.h"
/*
#error No card type defined!
#endif
-/* Command line configuration */
/*
* CONFIG_RAM defines if u-boot is loaded via BDM (or started from
* a different bootloader that has already performed RAM setup) or
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID 0/* ignored in arm */
-/*
- * Command line configuration.
- */
-
/*
* Network Driver Setting
*/
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 0
-#define CONFIG_CMD_GPT
-
#endif /* __CONFIG_H */
/*
* Command configuration.
*/
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2
/*
* Flash configuration.
* Filesystem configuration.
*/
#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT4
-#define CONFIG_FS_EXT4
-#define CONFIG_CMD_FS_GENERIC
/*
* Environment configuration.
* Set fdtaddr to prior stage-provided DTB in board_late_init, when
* writeable environment is available.
*/
-#define CONFIG_BOARD_LATE_INIT
#endif /* __BCMSTB_H */
#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
-#undef CONFIG_CMD_SF
-#undef CONFIG_CMD_SPI
#endif
/* Board Clock */
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
#define CONFIG_SYS_RTC_BUS_NUM 0x01
#define CONFIG_SYS_I2C_RTC_ADDR 0x32
#define CONFIG_BOARD_EARLY_INIT_F
/* Commands */
-#define CONFIG_CMD_READ
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_CRC32
#undef CONFIG_BOOTM_NETBSD
/* ENET Config */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OVERWRITE
-/* Command line configuration. */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-#define CONFIG_BOARD_LATE_INIT
-
/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM
#define CONFIG_PCA953X
-#define CONFIG_CMD_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-/*
- * Commands configuration
- */
-
/*
* SDIO/MMC Card Configuration
*/
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#ifdef CONFIG_MCFFEC
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_ENV_OVERWRITE
/* Command definition */
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FLASH
#undef CONFIG_IPADDR
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_SYS_MMC_ENV_PART 1
#endif
-#define CONFIG_CMD_TIME
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
-/*
- * Command line configuration.
- */
-
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#ifndef CONFIG_TRAILBLAZER
#define CONFIG_CUSTOMER_BOARD_SUPPORT
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_BOARD_LATE_INIT
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
*/
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
-/*
- * Commands configuration
- */
-
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
-/*
- * Commands configuration
- */
-
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-/*
- * Commands configuration
- */
-
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
-#define CONFIG_BZIP2
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
#include "mx6_common.h"
/* Falcon Mode */
-#define CONFIG_CMD_SPL
#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
-#define CONFIG_CMD_SPL_WRITE_SIZE (44 * SZ_1K)
/* Falcon Mode - MMC support */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x3F00
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-/*
- * Commands configuration
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-common.h"
/* Remove or override few declarations from mv-common.h */
#endif
#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_CMD_BOOTD
#ifdef CONFIG_SPL_DFU
#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
#define DFUARGS \
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG
-/*
- * Commands configuration
- */
-
-/*
- * mv-plug-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-plug-common.h"
/*
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
-/*
- * Commands configuration
- */
-#define CONFIG_CMD_EXT2
-
-/*
- * mv-plug-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-plug-common.h"
/*
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-/*
- * Commands configuration
- */
-
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#define CONFIG_MCFTMR
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
-/*
- * Commands configuration
- */
/*
* Network
#define CONFIG_HIDE_LOGO_VERSION
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
-#define CONFIG_CMD_BMP
#define CONFIG_IMX6_PWM_PER_CLK 66000000
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-/*
- * Commands configuration
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-common.h"
/*
*/
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000)
-/*
- * Commands configuration
- */
-
/* Network configuration */
#ifdef CONFIG_CMD_NET
#define CONFIG_ARMADA100_FEC
/*
* Standard filesystems
*/
-#define CONFIG_BZIP2
/*
* mv-plug-common.h should be defined after CMD configs since it used them
#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c
/* Various command support */
-#define CONFIG_CMD_UNZIP /* gzwrite */
/* Ethernet support */
#define CONFIG_FEC_MXC
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-/*
- * Commands configuration
- */
-
/*
* SDIO/MMC Card Configuration
*/
#define CONFIG_CALXEDA_XGMAC
-/*
- * Command line configuration.
- */
-
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_RESET_TO_RETRY
#define CONFIG_HIKEY_GPIO
-/* Command line configuration */
-
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-/*
- * Command line configuration.
- */
-
/*
* Miscellaneous configurable options
*/
/*
* Callback configuration
*/
-#define CONFIG_BOARD_LATE_INIT
#endif /* _CONFIG_HSDK_H_ */
/*
* Callback configuration
*/
-#define CONFIG_BOARD_LATE_INIT
#endif /* _CONFIG_HSDK_H_ */
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-/*
- * Compression configuration
- */
-#define CONFIG_BZIP2
-
-/*
- * Commands configuration
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-common.h"
/*
*/
#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT
-/*
- * Compression configuration
- */
-#define CONFIG_BZIP2
-
-/*
- * Commands configuration
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-common.h"
/*
#ifdef CONFIG_SPL_OS_BOOT
# define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
# define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-# define CONFIG_CMD_SPL
# define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
-# define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
/* MMC support: args@1MB kernel@2MB */
# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
/* Falcon */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_CMD_SPL
#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
-#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
/* MMC support: args@1MB kernel@2MB */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
#define CONFIG_REMAKE_ELF
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
-#undef CONFIG_CMD_IMLS
-
-#undef CONFIG_CMD_CRC32
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_MXC_GPIO
-#define CONFIG_CMD_FUSE
-
/* I2C Configs */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_BOARD_EARLY_INIT_F
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
-#undef CONFIG_CMD_IMLS
-
-#undef CONFIG_CMD_CRC32
-
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_MXC_GPIO
-#define CONFIG_CMD_FUSE
-
/* I2C Configs */
#define CONFIG_SYS_I2C_SPEED 100000
/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
-#undef CONFIG_CMD_IMLS
-
-#undef CONFIG_CMD_CRC32
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* FUSE command */
-#define CONFIG_CMD_FUSE
/* Boot M4 */
#define M4_BOOT_ENV \
/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
-#undef CONFIG_CMD_IMLS
-
-#undef CONFIG_CMD_CRC32
-
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#ifndef CONFIG_DM_PCA953X
#define CONFIG_PCA953X
-#define CONFIG_CMD_PCA953X
-#define CONFIG_CMD_PCA953X_INFO
#endif
/* Networking */
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
#define CONFIG_BOOTCOMMAND ""
/* Flash settings */
#define CONFIG_SMC91111_BASE 0xC8000000
#undef CONFIG_SMC91111_EXT_PHY
-/*
- * Command line configuration.
- */
#define CONFIG_BOOTCOMMAND "tftpboot ; bootm"
#define CONFIG_SERVERIP 192.168.1.100
#define CONFIG_IPADDR 192.168.1.104
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
-#define CONFIG_CMD_MEMINFO
/* MMC */
#ifdef CONFIG_MMC
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_CMD_MEMINFO
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-#define CONFIG_CMD_MEMINFO
#ifndef CONFIG_SPL_BUILD
#undef BOOT_TARGET_DEVICES
#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd"
#endif
-#define CONFIG_CMD_MEMINFO
-
#endif /* __LS1012ARDB_H__ */
#define SYS_SDRAM_SIZE_512 0x20000000
#define SYS_SDRAM_SIZE_1024 0x40000000
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-#define CONFIG_CMD_MEMINFO
/* ENV */
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\
"env exists secureboot && esbc_halt;"
#endif
-#define CONFIG_CMD_MEMINFO
#include <asm/fsl_secure_boot.h>
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
-#define CONFIG_CMD_MEMINFO
/*
* QIXIS Definitions
#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_MEMINFO
-
#include <asm/fsl_secure_boot.h>
#endif /* __LS1012AQDS_H__ */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
-#define CONFIG_CMD_MEMINFO
/*
* I2C IO expander
#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_MEMINFO
-
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
/*
* I2C
*/
-#define CONFIG_CMD_I2C
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
-#define CONFIG_CMD_SF
#define CONFIG_DM_SPI_FLASH
#endif
#define CONFIG_PCI_SCAN_SHOW
#endif
-#define CONFIG_CMD_MII
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_PEN_ADDR_BIG_ENDIAN
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MEMINFO
-
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_LS102XA_STREAM_ID
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
-#ifndef CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT2
-#endif
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
#endif
/* SATA */
-#ifndef CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT2
-#endif
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
#endif
#endif
-/* Command line configuration */
-
/* MMC */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
-#define CONFIG_CMD_SPL
#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500
/* SATA */
#ifndef SPL_NO_SATA
-#ifndef CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT2
-#endif
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 2
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#endif
-/* Command line configuration */
-
/* MMC */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
*/
#define CPU_RELEASE_ADDR secondary_boot_func
-#ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
-#endif
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
#if defined(CONFIG_FSL_MC_ENET)
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
-/* Command line configuration */
-#define CONFIG_CMD_CACHE
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_QIXIS_I2C_ACCESS
#define SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#else
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#endif
#endif
-#define CONFIG_CMD_MEMINFO
-
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_QIXIS_I2C_ACCESS
#endif
#define SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_CMD_MEMINFO
-
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
-/* Command line configuration */
-
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_KIRKWOOD_GPIO
-/*
- * Commands configuration
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-common.h"
/* loading initramfs images without uimage header */
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-/*
- * Commands configuration
- */
-
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
/*
* Miscellaneous configurable options
*/
/* Fuse API support */
#define CONFIG_FSL_IIM
-#define CONFIG_CMD_FUSE
/* Ethernet Configs */
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-#define CONFIG_BOARD_LATE_INIT
#define CONFIG_REVISION_TAG
/* USB Configs */
/* FLASH and environment organization */
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_CMD_FUSE
#define CONFIG_FSL_IIM
#define CONFIG_BCH
#include "mx6_common.h"
#include "imx6_spl.h"
-#undef CONFIG_MMC
-#undef CONFIG_SPL_MMC_SUPPORT
-#undef CONFIG_GENERIC_MMC
-#undef CONFIG_CMD_FUSE
-
#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
#define CONFIG_MXC_UART
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#define CONFIG_CMD_CACHE
-#endif
-
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif /* __CONFIG_H */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#define CONFIG_CMD_CACHE
-#endif
-
#endif /* __CONFIG_H */
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
-/*
- * Commands configuration
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-common.h"
/*
#define CONFIG_KW88F6702 1 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-/* compression configuration */
-#define CONFIG_BZIP2
-
-/* commands configuration */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-common.h"
/* environment variables configuration */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-/*
- * Commands configuration
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-common.h"
/*
#define MACH_TYPE_PDU001 5075
#define CONFIG_MACH_TYPE MACH_TYPE_PDU001
-#define CONFIG_BOARD_LATE_INIT
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 0 */
#define CONFIG_SYS_I2C_SPEED 100000
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_NAND
/* Enable NAND support */
-#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#endif
/* DMA stuff, needed for GPMI/MXS NAND support */
#define CONFIG_REMAKE_ELF
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_LATE_INIT
-
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
-#undef CONFIG_CMD_IMLS
-
-#undef CONFIG_CMD_CRC32
/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_MXC_GPIO
-#define CONFIG_CMD_FUSE
-
/* I2C Configs */
#define CONFIG_SYS_I2C_SPEED 100000
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
/* SDRAM */
#define PHYS_SDRAM_1 ATMEL_BASE_CS1 /* on DDRSDRC1 */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-/*
- * Commands configuration
- */
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-common.h"
/*
BOOTENV
-/* Command line configuration */
#define CONFIG_SYS_MMC_ENV_DEV 0
/* Monitor Command Prompt */
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_NE2000_BASE 0xb4000300
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
#define CONFIG_LOADS_ECHO /* echo on for serial download */
-/*
- * Command line configuration.
- */
-
/*
* Miscellaneous configurable options
*/
#include <configs/rk3399_common.h>
-#if defined(CONFIG_ENV_IS_IN_MMC)
-# define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
-
#define SDRAM_BANK_SIZE (2UL << 30)
#endif
#include <configs/rk3399_common.h>
-#define CONFIG_SYS_MMC_ENV_DEV 0
-
#define SDRAM_BANK_SIZE (2UL << 30)
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SKIP_LOWLEVEL_INIT
/* Config CACHE */
-#define CONFIG_CMD_CACHE
#define CONFIG_SYS_FULL_VA
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 1
-/* #define CONFIG_CMD_EXT2 EXT2 Support */
-
#if 0
/* Ethernet config */
-#define CONFIG_CMD_MII
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
/* NAND flash */
-#undef CONFIG_CMD_NAND
/* SPI flash */
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
/* NAND flash */
-#undef CONFIG_CMD_NAND
/* SPI flash */
#define CONFIG_SF_DEFAULT_SPEED 66000000
#ifdef FTRACE
#define CONFIG_TRACE
-#define CONFIG_CMD_TRACE
#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
#define CONFIG_TRACE_EARLY_SIZE (16 << 20)
#define CONFIG_TRACE_EARLY
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
-/*
- * Commands configuration
- */
-
-/*
- * Standard filesystems
- */
-#define CONFIG_BZIP2
-
-/*
- * mv-plug-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
#include "mv-plug-common.h"
/*
#include <linux/sizes.h>
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE 0x00100000
+#define CONFIG_SPL_BSS_START_ADDR 0x85000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x84000000
+
+#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif
+
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
/* Environment options */
+#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
+#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47"
+#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985"
+#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4"
+
+#define PARTS_DEFAULT \
+ "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \
+ "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \
+ "name=system,size=-,bootable,type=${type_guid_gpt_system};"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"scriptaddr=0x88100000\0" \
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
+ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
+ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
+ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
+ "partitions=" PARTS_DEFAULT "\0" \
BOOTENV
#define CONFIG_PREBOOT \
"setenv fdt_addr ${fdtcontroladdr};" \
"fdt addr ${fdtcontroladdr};"
+#endif
#endif /* __CONFIG_H */
/* U-Boot memory settings */
#define CONFIG_SYS_MALLOC_LEN (1 << 20)
-/* Command line configuration */
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_CACHE
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_FSL_USDHC_NUM 1
#endif /* CONFIG_FSL_USDHC */
-#define CONFIG_CMD_READ
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"console=ttymxc0\0" \
BOOTENV
/* Extra Commands */
-#define CONFIG_CMD_ASKENV
#define CONFIG_SETUP_MEMORY_TAGS
"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
"bootm 0x08044000 - 0x08042000\0"
-/*
- * Command line configuration.
- */
-
#endif /* __CONFIG_H */
"ramdisk_addr_r=0x00438000\0" \
BOOTENV
-/*
- * Command line configuration.
- */
-
#endif /* __CONFIG_H */
"ramdisk_addr_r=0x00438000\0" \
BOOTENV
-/*
- * Command line configuration.
- */
-
#endif /* __CONFIG_H */
"ramdisk_addr_r=0xC0438000\0" \
BOOTENV
-/*
- * Command line configuration.
- */
-#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DISPLAY_BOARDINFO
/* For SPL */
"ramdisk_addr_r=0xD0438000\0" \
BOOTENV
-/*
- * Command line configuration.
- */
-#define CONFIG_BOARD_LATE_INIT
-
#endif /* __CONFIG_H */
"ramdisk_addr_r=0xD0438000\0" \
BOOTENV
-/*
- * Command line configuration.
- */
-#define CONFIG_BOARD_LATE_INIT
-
#endif /* __CONFIG_H */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-/*
- * Command line configuration.
- */
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-/*
- * Command line configuration.
- */
-
/*
* Miscellaneous configurable options
*/
#define ETH0_BASE_ADDRESS 0xFE100000
#define ETH1_BASE_ADDRESS 0xFE110000
-/*
- * Command line configuration
- */
-
/*
* Environment configuration
*/
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
-#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
/* Environment settings */
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-/*
- * Commands configuration
- */
-
/*
* The debugging version enables USB support via defconfig.
* This version should also enable all other non-production
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#define CONFIG_CMD_ASKENV
-
#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-/* sspi command isn't useful */
-#undef CONFIG_CMD_SPI
-
-/* No useful gpio */
-#undef CONFIG_ZYNQ_GPIO
-#undef CONFIG_CMD_GPIO
-
/* No falcon support */
#undef CONFIG_SPL_OS_BOOT
#undef CONFIG_SPL_FPGA_SUPPORT
* Diagnostics
*/
-#define CONFIG_CMD_MII
-
#endif /* __CONFIG_H */
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
/*
* Miscellaneous configurable options
*/
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
#define CONFIG_SYS_RTC_BUS_NUM 0x01
#define CONFIG_SYS_I2C_RTC_ADDR 0x32
/* Falcon Mode */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
-#define CONFIG_CMD_SPL
#define CONFIG_SYS_SPL_ARGS_ADDR 0x0ffe5000
-#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
/* Falcon Mode - MMC support: args@16MB kernel@17MB */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8000 /* 16MB */
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
#define CONFIG_RBTREE
-#define CONFIG_LZO
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
-/*
- * Commands configuration
- */
-#define CONFIG_CMD_PCI
-
/* NAND */
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* NAND */
#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_LZO
-#define CONFIG_CMD_MTDPARTS
#define CONFIG_SYS_MALLOC_LEN (4 << 20)
#define CONFIG_LMB
-#undef CONFIG_ZLIB
-#undef CONFIG_GZIP
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
/* SATA AHCI storage */
*/
#define CONFIG_SYS_NS16550_PORT_MAPPED
-/*-----------------------------------------------------------------------
- * Command line configuration.
- */
-
#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND \
"ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
#endif
/* Serial setup */
-#define CONFIG_ARM_DCC
#define CONFIG_CPU_ARMV8
#define CONFIG_SYS_BAUDRATE_TABLE \
/* Undef unneeded configs */
#undef CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_ZLIB
-#undef CONFIG_GZIP
-#undef CONFIG_CMD_ENV
/* BOOTP options */
#undef CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000)
/* Serial setup */
-#define CONFIG_ARM_DCC
#define CONFIG_CPU_ARMV8
#define CONFIG_SYS_BAUDRATE_TABLE \
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU)
-# undef CONFIG_CMD_BOOTD
# define CONFIG_SPL_ENV_SUPPORT
# define CONFIG_SPL_HASH_SUPPORT
# define CONFIG_ENV_MAX_ENTRIES 10
#undef CONFIG_BOOTCOMMAND
#undef CONFIG_EXTRA_ENV_SETTINGS
#undef CONFIG_SYS_MALLOC_LEN
-#undef CONFIG_ZLIB
-#undef CONFIG_GZIP
-#undef CONFIG_CMD_ENV
#undef CONFIG_SYS_INIT_SP_ADDR
/* BOOTP options */
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-/*
- * Command line configuration.
- */
-
-/*
- * Additional command
- */
-
/*
* USB
*/
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-#define CONFIG_ARM_DCC
-
/* Ethernet driver */
#if defined(CONFIG_ZYNQ_GEM)
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/* Undef unneeded configs */
#undef CONFIG_EXTRA_ENV_SETTINGS
-#undef CONFIG_ZLIB
-#undef CONFIG_GZIP
#undef CONFIG_SYS_CBSIZE
const u8 *optional_data;
};
-void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data);
+efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data,
+ efi_uintn_t *size);
unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data);
efi_status_t efi_bootmgr_load(efi_handle_t *handle);
#ifndef _LINUX_DMA_MAPPING_H
#define _LINUX_DMA_MAPPING_H
+#include <asm/cache.h>
#include <linux/dma-direction.h>
#include <linux/types.h>
#include <asm/dma-mapping.h>
int (*write)(struct udevice *dev, u32 offset, size_t len,
const void *buf);
int (*erase)(struct udevice *dev, u32 offset, size_t len);
- /**
- * get_sw_write_prot() - Check state of software write-protect feature
- *
- * SPI flash chips can lock a region of the flash defined by a
- * 'protected area'. This function checks if this protected area is
- * defined.
- *
- * @dev: SPI flash device
- * @return 0 if no region is write-protected, 1 if a region is
- * write-protected, -ENOSYS if the driver does not implement this,
- * other -ve value on error
- */
- int (*get_sw_write_prot)(struct udevice *dev);
};
/* Access the serial operations for a device */
*/
int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len);
-/**
- * spl_flash_get_sw_write_prot() - Check state of software write-protect feature
- *
- * SPI flash chips can lock a region of the flash defined by a
- * 'protected area'. This function checks if this protected area is
- * defined.
- *
- * @dev: SPI flash device
- * @return 0 if no region is write-protected, 1 if a region is
- * write-protected, -ENOSYS if the driver does not implement this,
- * other -ve value on error
- */
-int spl_flash_get_sw_write_prot(struct udevice *dev);
-
/**
* spi_flash_std_probe() - Probe a SPI flash device
*
bool "Pseudo-random library support"
config LIB_HW_RAND
- bool "HW Engine for random libray support"
+ bool "HW Engine for random library support"
endchoice
config SPL_LZ4
bool "Enable LZ4 decompression support in SPL"
help
- This enables support for tge LZ4 decompression algorithm in SPL. LZ4
+ This enables support for the LZ4 decompression algorithm in SPL. LZ4
is a lossless data compression algorithm that is focused on
fast compression and decompression speed. It belongs to the LZ77
family of byte-oriented compression schemes.
config SPL_LZMA
bool "Enable LZMA decompression support for SPL build"
help
- This enables support for LZMA compression altorithm for SPL boot.
+ This enables support for LZMA compression algorithm for SPL boot.
config SPL_LZO
bool "Enable LZO decompression support in SPL"
endif
endif
obj-$(CONFIG_USB_TTY) += circbuf.o
-obj-y += crc7.o
obj-y += crc8.o
obj-y += crc16.o
obj-$(CONFIG_ERRNO_STR) += errno_str.o
obj-y += display_options.o
CFLAGS_display_options.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"')
obj-$(CONFIG_BCH) += bch.o
+obj-$(CONFIG_MMC_SPI) += crc7.o
obj-y += crc32.o
obj-$(CONFIG_CRC32C) += crc32c.o
obj-y += ctype.o
*
* @lo: pointer to target
* @data: serialized data
+ * @size: size of the load option, on return size of the optional data
+ * Return: status code
*/
-void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data)
+efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data,
+ efi_uintn_t *size)
{
+ efi_uintn_t len;
+
+ len = sizeof(u32);
+ if (*size < len + 2 * sizeof(u16))
+ return EFI_INVALID_PARAMETER;
lo->attributes = get_unaligned_le32(data);
- data += sizeof(u32);
+ data += len;
+ *size -= len;
+ len = sizeof(u16);
lo->file_path_length = get_unaligned_le16(data);
- data += sizeof(u16);
+ data += len;
+ *size -= len;
- /* FIXME */
lo->label = (u16 *)data;
- data += (u16_strlen(lo->label) + 1) * sizeof(u16);
-
- /* FIXME */
+ len = u16_strnlen(lo->label, *size / sizeof(u16) - 1);
+ if (lo->label[len])
+ return EFI_INVALID_PARAMETER;
+ len = (len + 1) * sizeof(u16);
+ if (*size < len)
+ return EFI_INVALID_PARAMETER;
+ data += len;
+ *size -= len;
+
+ len = lo->file_path_length;
+ if (*size < len)
+ return EFI_INVALID_PARAMETER;
lo->file_path = (struct efi_device_path *)data;
- data += lo->file_path_length;
+ /*
+ * TODO: validate device path. There should be an end node within
+ * the indicated file_path_length.
+ */
+ data += len;
+ *size -= len;
lo->optional_data = data;
+
+ return EFI_SUCCESS;
}
/**
if (!load_option)
return EFI_LOAD_ERROR;
- efi_deserialize_load_option(&lo, load_option);
+ ret = efi_deserialize_load_option(&lo, load_option, &size);
+ if (ret != EFI_SUCCESS) {
+ log_warning("Invalid load option for %ls\n", varname);
+ goto error;
+ }
if (lo.attributes & LOAD_OPTION_ACTIVE) {
u32 attributes;
* restriction so we need to manually swap its and our view of that register on
* EFI callback entry/exit.
*/
-static volatile void *efi_gd, *app_gd;
+static volatile gd_t *efi_gd, *app_gd;
#endif
/* 1 if inside U-Boot code, 0 if inside EFI payload code */
#ifdef CONFIG_ARM
assert(efi_gd);
app_gd = gd;
- gd = efi_gd;
+ set_gd(efi_gd);
#endif
return ret;
}
{
int ret = --entry_count == 0;
#ifdef CONFIG_ARM
- gd = app_gd;
+ set_gd(app_gd);
#endif
return ret;
}
/* Only restore if we're already in EFI context */
if (!efi_gd)
return;
- gd = efi_gd;
+ set_gd(efi_gd);
#endif
}
* otherwise __efi_entry_check() will put the wrong value into
* app_gd.
*/
- gd = app_gd;
+ set_gd(app_gd);
#endif
/*
* To get ready to call EFI_EXIT below we have to execute the
return 0;
}
-/*
+/**
* Receive and parse a reply from the terminal.
*
* @n: array of return values
* @num: number of return values expected
* @end_char: character indicating end of terminal message
- * @return: non-zero indicates error
+ * Return: non-zero indicates error
*/
static int term_read_reply(int *n, int num, char end_char)
{
return 0;
}
+/**
+ * efi_cout_output_string() - write Unicode string to console
+ *
+ * This function implements the OutputString service of the simple text output
+ * protocol. See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @this: simple text output protocol
+ * @string: u16 string
+ * Return: status code
+ */
static efi_status_t EFIAPI efi_cout_output_string(
struct efi_simple_text_output_protocol *this,
const efi_string_t string)
return EFI_EXIT(ret);
}
+/**
+ * efi_cout_test_string() - test writing Unicode string to console
+ *
+ * This function implements the TestString service of the simple text output
+ * protocol. See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * As in OutputString we simply convert UTF-16 to UTF-8 there are no unsupported
+ * code points and we can always return EFI_SUCCESS.
+ *
+ * @this: simple text output protocol
+ * @string: u16 string
+ * Return: status code
+ */
static efi_status_t EFIAPI efi_cout_test_string(
struct efi_simple_text_output_protocol *this,
const efi_string_t string)
return EFI_EXIT(EFI_SUCCESS);
}
+/**
+ * cout_mode_matches() - check if mode has given terminal size
+ *
+ * @mode: text mode
+ * @rows: number of rows
+ * @cols: number of columns
+ * Return: true if number of rows and columns matches the mode and
+ * the mode is present
+ */
static bool cout_mode_matches(struct cout_mode *mode, int rows, int cols)
{
if (!mode->present)
/**
* query_console_serial() - query console size
*
+ * When using a serial console or the net console we can only devise the
+ * terminal size by querying the terminal using ECMA-48 control sequences.
+ *
* @rows: pointer to return number of rows
* @cols: pointer to return number of columns
* Returns: 0 on success
return ret;
}
-/*
- * Update the mode table.
+/**
+ * query_console_size() - update the mode table.
*
* By default the only mode available is 80x25. If the console has at least 50
* lines, enable mode 80x50. If we can query the console size and it is neither
}
}
+
+/**
+ * efi_cout_query_mode() - get terminal size for a text mode
+ *
+ * This function implements the QueryMode service of the simple text output
+ * protocol. See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @this: simple text output protocol
+ * @mode_number: mode number to retrieve information on
+ * @columns: number of columns
+ * @rows: number of rows
+ * Return: status code
+ */
static efi_status_t EFIAPI efi_cout_query_mode(
struct efi_simple_text_output_protocol *this,
unsigned long mode_number, unsigned long *columns,
{ 37, 47 }, /* 7: light gray, map to white */
};
-/* See EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.SetAttribute(). */
+/**
+ * efi_cout_set_attribute() - set fore- and background color
+ *
+ * This function implements the SetAttribute service of the simple text output
+ * protocol. See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @this: simple text output protocol
+ * @attribute: foreground color - bits 0-3, background color - bits 4-6
+ * Return: status code
+ */
static efi_status_t EFIAPI efi_cout_set_attribute(
struct efi_simple_text_output_protocol *this,
unsigned long attribute)
/**
* efi_cout_clear_screen() - clear screen
*
- * This function implements the ClearScreen service of the
- * EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL. See the Unified Extensible Firmware
- * Interface (UEFI) specification for details.
+ * This function implements the ClearScreen service of the simple text output
+ * protocol. See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
*
* @this: pointer to the protocol instance
* Return: status code
return EFI_EXIT(EFI_SUCCESS);
}
+/**
+ * efi_cout_clear_set_mode() - set text model
+ *
+ * This function implements the SetMode service of the simple text output
+ * protocol. See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @this: pointer to the protocol instance
+ * @mode_number: number of the text mode to set
+ * Return: status code
+ */
static efi_status_t EFIAPI efi_cout_set_mode(
struct efi_simple_text_output_protocol *this,
unsigned long mode_number)
return EFI_EXIT(EFI_SUCCESS);
}
+/**
+ * efi_cout_reset() - reset the terminal
+ *
+ * This function implements the Reset service of the simple text output
+ * protocol. See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @this: pointer to the protocol instance
+ * @extended_verification: if set an extended verification may be executed
+ * Return: status code
+ */
static efi_status_t EFIAPI efi_cout_reset(
struct efi_simple_text_output_protocol *this,
char extended_verification)
return EFI_EXIT(EFI_SUCCESS);
}
+/**
+ * efi_cout_set_cursor_position() - reset the terminal
+ *
+ * This function implements the SetCursorPosition service of the simple text
+ * output protocol. See the Unified Extensible Firmware Interface (UEFI)
+ * specification for details.
+ *
+ * @this: pointer to the protocol instance
+ * @column: column to move to
+ * @row: row to move to
+ * Return: status code
+ */
static efi_status_t EFIAPI efi_cout_set_cursor_position(
struct efi_simple_text_output_protocol *this,
unsigned long column, unsigned long row)
return EFI_EXIT(ret);
}
+/**
+ * efi_cout_enable_cursor() - enable the cursor
+ *
+ * This function implements the EnableCursor service of the simple text output
+ * protocol. See the Unified Extensible Firmware Interface (UEFI) specification
+ * for details.
+ *
+ * @this: pointer to the protocol instance
+ * @enable: if true enable, if false disable the cursor
+ * Return: status code
+ */
static efi_status_t EFIAPI efi_cout_enable_cursor(
struct efi_simple_text_output_protocol *this,
bool enable)
* This gets called when we have already parsed CSI.
*
* @key_state: receives the state of the shift, alt, control, and logo keys
- * @return: the unmodified code
+ * Return: the unmodified code
*/
static int analyze_modifiers(struct efi_key_state *key_state)
{
#ifdef CONFIG_EFI_SECURE_BOOT
/**
- * cmp_pe_section - compare two sections
- * @arg1: Pointer to pointer to first section
- * @arg2: Pointer to pointer to second section
+ * cmp_pe_section() - compare virtual addresses of two PE image sections
+ * @arg1: pointer to pointer to first section header
+ * @arg2: pointer to pointer to second section header
*
- * Compare two sections in PE image.
+ * Compare the virtual addresses of two sections of an portable executable.
+ * The arguments are defined as const void * to allow usage with qsort().
*
- * Return: -1, 0, 1 respectively if arg1 < arg2, arg1 == arg2 or
- * arg1 > arg2
+ * Return: -1 if the virtual address of arg1 is less than that of arg2,
+ * 0 if the virtual addresses are equal, 1 if the virtual address
+ * of arg1 is greater than that of arg2.
*/
static int cmp_pe_section(const void *arg1, const void *arg2)
{
}
/**
- * efi_image_parse - parse a PE image
+ * efi_image_parse() - parse a PE image
* @efi: Pointer to image
* @len: Size of @efi
* @regp: Pointer to a list of regions
}
/**
- * efi_image_unsigned_authenticate - authenticate unsigned image with
+ * efi_image_unsigned_authenticate() - authenticate unsigned image with
* SHA256 hash
* @regs: List of regions to be verified
*
}
/**
- * efi_image_authenticate - verify a signature of signed image
+ * efi_image_authenticate() - verify a signature of signed image
* @efi: Pointer to image
* @efi_size: Size of @efi
*
goto err;
}
- /* assume sizeof(IMAGE_NT_HEADERS32) <= sizeof(IMAGE_NT_HEADERS64) */
- if (efi_size < dos->e_lfanew + sizeof(IMAGE_NT_HEADERS32)) {
+ /*
+ * Check if the image section header fits into the file. Knowing that at
+ * least one section header follows we only need to check for the length
+ * of the 64bit header which is longer than the 32bit header.
+ */
+ if (efi_size < dos->e_lfanew + sizeof(IMAGE_NT_HEADERS64)) {
printf("%s: Invalid offset for Extended Header\n", __func__);
ret = EFI_LOAD_ERROR;
goto err;
}
nt = (void *) ((char *)efi + dos->e_lfanew);
- if ((nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR64_MAGIC) &&
- (efi_size < dos->e_lfanew + sizeof(IMAGE_NT_HEADERS64))) {
- printf("%s: Invalid offset for Extended Header\n", __func__);
- ret = EFI_LOAD_ERROR;
- goto err;
- }
-
if (nt->Signature != IMAGE_NT_SIGNATURE) {
printf("%s: Invalid NT Signature\n", __func__);
ret = EFI_LOAD_ERROR;
const efi_guid_t efi_guid_cert_rsa2048 = EFI_CERT_RSA2048_GUID;
const efi_guid_t efi_guid_cert_x509 = EFI_CERT_X509_GUID;
const efi_guid_t efi_guid_cert_x509_sha256 = EFI_CERT_X509_SHA256_GUID;
+const efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
#ifdef CONFIG_EFI_SECURE_BOOT
EFI_MODE_DEPLOYED,
};
-const efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
static bool efi_secure_boot;
static int efi_secure_mode;
static u8 efi_vendor_keys;
{
int i = 1;
char *p = start;
+ if (!*str)
+ str = "Unknown";
for (;;) {
if (!*p) {
my @ignore = ();
my $help = 0;
my $configuration_file = ".checkpatch.conf";
-my $max_line_length = 80;
+my $max_line_length = 100;
my $ignore_perl_version = 0;
my $minimum_perl_version = 5.10.0;
my $min_conf_desc_length = 4;
my $codespellfile = "/usr/share/codespell/dictionary.txt";
my $conststructsfile = "$D/const_structs.checkpatch";
my $typedefsfile = "";
+my $u_boot = 0;
my $color = "auto";
-my $allow_c99_comments = 1; # Can be overridden by --ignore C99_COMMENT_TOLERANCE
-# git output parsing needs US English output, so first set backtick child process LANGUAGE
-my $git_command ='export LANGUAGE=en_US.UTF-8; git';
+my $allow_c99_comments = 1;
sub help {
my ($exitcode) = @_;
--types TYPE(,TYPE2...) show only these comma separated message types
--ignore TYPE(,TYPE2...) ignore various comma separated message types
--show-types show the specific message type in the output
- --max-line-length=n set the maximum line length, if exceeded, warn
+ --max-line-length=n set the maximum line length, (default $max_line_length)
+ if exceeded, warn on patches
+ requires --strict for use with --file
--min-conf-desc-length=n set the min description length, if shorter, warn
--root=PATH PATH to the kernel tree root
--no-summary suppress the per-file summary
--typedefsfile Read additional types from this file
--color[=WHEN] Use colors 'always', 'never', or only when output
is a terminal ('auto'). Default is 'auto'.
+ --u-boot Run additional checks for U-Boot
-h, --help, --version display this help and exit
When FILE is - read standard input.
'codespell!' => \$codespell,
'codespellfile=s' => \$codespellfile,
'typedefsfile=s' => \$typedefsfile,
+ 'u-boot' => \$u_boot,
'color=s' => \$color,
'no-color' => \$color, #keep old behaviors of -nocolor
'nocolor' => \$color, #keep old behaviors of -nocolor
seq_vprintf|seq_printf|seq_puts
)};
-our $allocFunctions = qr{(?x:
- (?:(?:devm_)?
- (?:kv|k|v)[czm]alloc(?:_node|_array)? |
- kstrdup(?:_const)? |
- kmemdup(?:_nul)?) |
- (?:\w+)?alloc_skb(?:ip_align)? |
- # dev_alloc_skb/netdev_alloc_skb, et al
- dma_alloc_coherent
-)};
-
our $signature_tags = qr{(?xi:
Signed-off-by:|
- Co-developed-by:|
Acked-by:|
Tested-by:|
Reviewed-by:|
}
$mode_perms_search = "(?:${mode_perms_search})";
-our %deprecated_apis = (
- "synchronize_rcu_bh" => "synchronize_rcu",
- "synchronize_rcu_bh_expedited" => "synchronize_rcu_expedited",
- "call_rcu_bh" => "call_rcu",
- "rcu_barrier_bh" => "rcu_barrier",
- "synchronize_sched" => "synchronize_rcu",
- "synchronize_sched_expedited" => "synchronize_rcu_expedited",
- "call_rcu_sched" => "call_rcu",
- "rcu_barrier_sched" => "rcu_barrier",
- "get_state_synchronize_sched" => "get_state_synchronize_rcu",
- "cond_synchronize_sched" => "cond_synchronize_rcu",
-);
-
-#Create a search pattern for all these strings to speed up a loop below
-our $deprecated_apis_search = "";
-foreach my $entry (keys %deprecated_apis) {
- $deprecated_apis_search .= '|' if ($deprecated_apis_search ne "");
- $deprecated_apis_search .= $entry;
-}
-$deprecated_apis_search = "(?:${deprecated_apis_search})";
-
our $mode_perms_world_writable = qr{
S_IWUGO |
S_IWOTH |
$camelcase_seeded = 1;
if (-e ".git") {
- my $git_last_include_commit = `${git_command} log --no-merges --pretty=format:"%h%n" -1 -- include`;
+ my $git_last_include_commit = `git log --no-merges --pretty=format:"%h%n" -1 -- include`;
chomp $git_last_include_commit;
$camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit";
} else {
}
if (-e ".git") {
- $files = `${git_command} ls-files "include/*.h"`;
+ $files = `git ls-files "include/*.h"`;
@include_files = split('\n', $files);
}
return ($id, $desc) if ((which("git") eq "") || !(-e ".git"));
- my $output = `${git_command} log --no-color --format='%H %s' -1 $commit 2>&1`;
+ my $output = `git log --no-color --format='%H %s' -1 $commit 2>&1`;
$output =~ s/^\s*//gm;
my @lines = split("\n", $output);
return ($id, $desc) if ($#lines < 0);
- if ($lines[0] =~ /^error: short SHA1 $commit is ambiguous/) {
+ if ($lines[0] =~ /^error: short SHA1 $commit is ambiguous\./) {
# Maybe one day convert this block of bash into something that returns
# all matching commit ids, but it's very slow...
#
} else {
$git_range = "-1 $commit_expr";
}
- my $lines = `${git_command} log --no-color --no-merges --pretty=format:'%H %s' $git_range`;
+ my $lines = `git log --no-color --no-merges --pretty=format:'%H %s' $git_range`;
foreach my $line (split(/\n/, $lines)) {
$line =~ /^([0-9a-fA-F]{40,40}) (.*)$/;
next if (!defined($1) || !defined($2));
}
my $vname;
-$allow_c99_comments = !defined $ignore_type{"C99_COMMENT_TOLERANCE"};
for my $filename (@ARGV) {
my $FILE;
if ($git) {
return length(expand_tabs(substr($line, 0, $last_openparen))) + 1;
}
+# Checks specific to U-Boot
+sub u_boot_line {
+ my ($realfile, $line, $herecurr) = @_;
+
+ # ask for a test if a new uclass ID is added
+ if ($realfile =~ /uclass-id.h/ && $line =~ /^\+/) {
+ WARN("NEW_UCLASS",
+ "Possible new uclass - make sure to add a sandbox driver, plus a test in test/dm/<name>.c\n" . $herecurr);
+ }
+
+ # try to get people to use the livetree API
+ if ($line =~ /^\+.*fdtdec_/) {
+ WARN("LIVETREE",
+ "Use the livetree API (dev_read_...)\n" . $herecurr);
+ }
+
+ # add tests for new commands
+ if ($line =~ /^\+.*do_($Ident)\(struct cmd_tbl.*/) {
+ WARN("CMD_TEST",
+ "Possible new command - make sure you add a test\n" . $herecurr);
+ }
+
+ # use if instead of #if
+ if ($line =~ /^\+#if.*CONFIG.*/) {
+ WARN("PREFER_IF",
+ "Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where possible\n" . $herecurr);
+ }
+
+ # use defconfig to manage CONFIG_CMD options
+ if ($line =~ /\+\s*#\s*(define|undef)\s+(CONFIG_CMD\w*)\b/) {
+ ERROR("DEFINE_CONFIG_CMD",
+ "All commands are managed by Kconfig\n" . $herecurr);
+ }
+}
+
sub process {
my $filename = shift;
} else {
$signatures{$sig_nospace} = 1;
}
-
-# Check Co-developed-by: immediately followed by Signed-off-by: with same name and email
- if ($sign_off =~ /^co-developed-by:$/i) {
- if ($email eq $author) {
- WARN("BAD_SIGN_OFF",
- "Co-developed-by: should not be used to attribute nominal patch author '$author'\n" . "$here\n" . $rawline);
- }
- if (!defined $lines[$linenr]) {
- WARN("BAD_SIGN_OFF",
- "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline);
- } elsif ($rawlines[$linenr] !~ /^\s*signed-off-by:\s*(.*)/i) {
- WARN("BAD_SIGN_OFF",
- "Co-developed-by: must be immediately followed by Signed-off-by:\n" . "$here\n" . $rawline . "\n" .$rawlines[$linenr]);
- } elsif ($1 ne $email) {
- WARN("BAD_SIGN_OFF",
- "Co-developed-by and Signed-off-by: name/email do not match \n" . "$here\n" . $rawline . "\n" .$rawlines[$linenr]);
- }
- }
}
# Check email subject for common tools that don't need to be mentioned
($line =~ /^\s*(?:WARNING:|BUG:)/ ||
$line =~ /^\s*\[\s*\d+\.\d{6,6}\s*\]/ ||
# timestamp
- $line =~ /^\s*\[\<[0-9a-fA-F]{8,}\>\]/) ||
- $line =~ /^(?:\s+\w+:\s+[0-9a-fA-F]+){3,3}/ ||
- $line =~ /^\s*\#\d+\s*\[[0-9a-fA-F]+\]\s*\w+ at [0-9a-fA-F]+/) {
- # stack dump address styles
+ $line =~ /^\s*\[\<[0-9a-fA-F]{8,}\>\]/)) {
+ # stack dump address
$commit_log_possible_stack_dump = 1;
}
}
}
-# check for invalid commit id
- if ($in_commit_log && $line =~ /(^fixes:|\bcommit)\s+([0-9a-f]{6,40})\b/i) {
- my $id;
- my $description;
- ($id, $description) = git_commit_info($2, undef, undef);
- if (!defined($id)) {
- WARN("UNKNOWN_COMMIT_ID",
- "Unknown commit id '$2', maybe rebased or not pulled?\n" . $herecurr);
- }
- }
-
# ignore non-hunk lines and lines being removed
next if (!$hunk_line || $line =~ /^-/);
my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g;
my $dt_path = $root . "/Documentation/devicetree/bindings/";
- my $vp_file = $dt_path . "vendor-prefixes.yaml";
+ my $vp_file = $dt_path . "vendor-prefixes.txt";
foreach my $compat (@compats) {
my $compat2 = $compat;
next if $compat !~ /^([a-zA-Z0-9\-]+)\,/;
my $vendor = $1;
- `grep -Eq "\\"\\^\Q$vendor\E,\\.\\*\\":" $vp_file`;
+ `grep -Eq "^$vendor\\b" $vp_file`;
if ( $? >> 8 ) {
WARN("UNDOCUMENTED_DT_STRING",
"DT compatible string vendor \"$vendor\" appears un-documented -- check $vp_file\n" . $herecurr);
$comment = '..';
}
-# check SPDX comment style for .[chsS] files
- if ($realfile =~ /\.[chsS]$/ &&
- $rawline =~ /SPDX-License-Identifier:/ &&
- $rawline !~ m@^\+\s*\Q$comment\E\s*@) {
- WARN("SPDX_LICENSE_TAG",
- "Improper SPDX comment style for '$realfile', please use '$comment' instead\n" . $herecurr);
- }
-
if ($comment !~ /^$/ &&
- $rawline !~ m@^\+\Q$comment\E SPDX-License-Identifier: @) {
- WARN("SPDX_LICENSE_TAG",
- "Missing or malformed SPDX-License-Identifier tag in line $checklicenseline\n" . $herecurr);
+ $rawline !~ /^\+\Q$comment\E SPDX-License-Identifier: /) {
+ WARN("SPDX_LICENSE_TAG",
+ "Missing or malformed SPDX-License-Identifier tag in line $checklicenseline\n" . $herecurr);
} elsif ($rawline =~ /(SPDX-License-Identifier: .*)/) {
- my $spdx_license = $1;
- if (!is_SPDX_License_valid($spdx_license)) {
- WARN("SPDX_LICENSE_TAG",
- "'$spdx_license' is not supported in LICENSES/...\n" . $herecurr);
- }
+ my $spdx_license = $1;
+ if (!is_SPDX_License_valid($spdx_license)) {
+ WARN("SPDX_LICENSE_TAG",
+ "'$spdx_license' is not supported in LICENSES/...\n" . $herecurr);
+ }
}
}
}
# check we are in a valid source file if not then ignore this hunk
next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/);
-# check for using SPDX-License-Identifier on the wrong line number
- if ($realline != $checklicenseline &&
- $rawline =~ /\bSPDX-License-Identifier:/ &&
- substr($line, @-, @+ - @-) eq "$;" x (@+ - @-)) {
- WARN("SPDX_LICENSE_TAG",
- "Misplaced SPDX-License-Identifier tag - use line $checklicenseline instead\n" . $herecurr);
- }
-
# line length limit (with some exclusions)
#
# There are a few types of lines that may extend beyond $max_line_length:
if ($msg_type ne "" &&
(show_type("LONG_LINE") || show_type($msg_type))) {
- WARN($msg_type,
- "line over $max_line_length characters\n" . $herecurr);
+ my $msg_level = \&WARN;
+ $msg_level = \&CHK if ($file);
+ &{$msg_level}($msg_type,
+ "line length of $length exceeds $max_line_length columns\n" . $herecurr);
}
}
"adding a line without newline at end of file\n" . $herecurr);
}
+ if ($u_boot) {
+ u_boot_line($realfile, $line, $herecurr);
+ }
+
# check we are in a valid source file C or perl if not then ignore this hunk
next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/);
WARN("STATIC_CONST_CHAR_ARRAY",
"static const char * array should probably be static const char * const\n" .
$herecurr);
- }
-
-# check for initialized const char arrays that should be static const
- if ($line =~ /^\+\s*const\s+(char|unsigned\s+char|_*u8|(?:[us]_)?int8_t)\s+\w+\s*\[\s*(?:\w+\s*)?\]\s*=\s*"/) {
- if (WARN("STATIC_CONST_CHAR_ARRAY",
- "const array should probably be static const\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/(^.\s*)const\b/${1}static const/;
- }
- }
+ }
# check for static char foo[] = "bar" declarations.
if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) {
WARN("STATIC_CONST_CHAR_ARRAY",
"static char array declaration should probably be static const char\n" .
$herecurr);
- }
+ }
# check for const <foo> const where <foo> is not a pointer or array type
if ($sline =~ /\bconst\s+($BasicType)\s+const\b/) {
# closing brace should have a space following it when it has anything
# on the line
- if ($line =~ /}(?!(?:,|;|\)|\}))\S/) {
+ if ($line =~ /}(?!(?:,|;|\)))\S/) {
if (ERROR("SPACING",
"space required after that close brace '}'\n" . $herecurr) &&
$fix) {
while ($line =~ m{($Constant|$Lval)}g) {
my $var = $1;
+#gcc binary extension
+ if ($var =~ /^$Binary$/) {
+ if (WARN("GCC_BINARY_CONSTANT",
+ "Avoid gcc v4.3+ binary constant extension: <$var>\n" . $herecurr) &&
+ $fix) {
+ my $hexval = sprintf("0x%x", oct($var));
+ $fixed[$fixlinenr] =~
+ s/\b$var\b/$hexval/;
+ }
+ }
+
#CamelCase
if ($var !~ /^$Constant$/ &&
$var =~ /[A-Z][a-z]|[a-z][A-Z]/ &&
next if ($arg =~ /\.\.\./);
next if ($arg =~ /^type$/i);
my $tmp_stmt = $define_stmt;
- $tmp_stmt =~ s/\b(sizeof|typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g;
+ $tmp_stmt =~ s/\b(typeof|__typeof__|__builtin\w+|typecheck\s*\(\s*$Type\s*,|\#+)\s*\(*\s*$arg\s*\)*\b//g;
$tmp_stmt =~ s/\#+\s*$arg\b//g;
$tmp_stmt =~ s/\b$arg\s*\#\#//g;
my $use_cnt = () = $tmp_stmt =~ /\b$arg\b/g;
my ($s, $c) = ctx_statement_block($linenr - 3, $realcnt, 0);
# print("line: <$line>\nprevline: <$prevline>\ns: <$s>\nc: <$c>\n\n\n");
- if ($s =~ /(?:^|\n)[ \+]\s*(?:$Type\s*)?\Q$testval\E\s*=\s*(?:\([^\)]*\)\s*)?\s*$allocFunctions\s*\(/ &&
- $s !~ /\b__GFP_NOWARN\b/ ) {
+ if ($s =~ /(?:^|\n)[ \+]\s*(?:$Type\s*)?\Q$testval\E\s*=\s*(?:\([^\)]*\)\s*)?\s*(?:devm_)?(?:[kv][czm]alloc(?:_node|_array)?\b|kstrdup|kmemdup|(?:dev_)?alloc_skb)/) {
WARN("OOM_MESSAGE",
"Possible unnecessary 'out of memory' message\n" . $hereprev);
}
# ignore udelay's < 10, however
if (! ($delay < 10) ) {
CHK("USLEEP_RANGE",
- "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst\n" . $herecurr);
+ "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $herecurr);
}
if ($delay > 2000) {
WARN("LONG_UDELAY",
if ($line =~ /\bmsleep\s*\((\d+)\);/) {
if ($1 < 20) {
WARN("MSLEEP",
- "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst\n" . $herecurr);
+ "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $herecurr);
}
}
"__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr);
}
-# Check for __attribute__ section, prefer __section
- if ($realfile !~ m@\binclude/uapi/@ &&
- $line =~ /\b__attribute__\s*\(\s*\(.*_*section_*\s*\(\s*("[^"]*")/) {
- my $old = substr($rawline, $-[1], $+[1] - $-[1]);
- my $new = substr($old, 1, -1);
- if (WARN("PREFER_SECTION",
- "__section($new) is preferred over __attribute__((section($old)))\n" . $herecurr) &&
- $fix) {
- $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*_*section_*\s*\(\s*\Q$old\E\s*\)\s*\)\s*\)/__section($new)/;
- }
- }
-
# Check for __attribute__ format(printf, prefer __printf
if ($realfile !~ m@\binclude/uapi/@ &&
$line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) {
while ($fmt =~ /(\%[\*\d\.]*p(\w))/g) {
$specifier = $1;
$extension = $2;
- if ($extension !~ /[SsBKRraEhMmIiUDdgVCbGNOxt]/) {
+ if ($extension !~ /[SsBKRraEhMmIiUDdgVCbGNOx]/) {
$bad_specifier = $specifier;
last;
}
my $max = $7;
if ($min eq $max) {
WARN("USLEEP_RANGE",
- "usleep_range should not use min == max args; see Documentation/timers/timers-howto.rst\n" . "$here\n$stat\n");
+ "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
} elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ &&
$min > $max) {
WARN("USLEEP_RANGE",
- "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.rst\n" . "$here\n$stat\n");
+ "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n");
}
}
}
}
-# check for pointless casting of alloc functions
- if ($line =~ /\*\s*\)\s*$allocFunctions\b/) {
+# check for pointless casting of kmalloc return
+ if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) {
WARN("UNNECESSARY_CASTS",
"unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr);
}
# alloc style
# p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...)
if ($perl_version_ok &&
- $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*((?:kv|k|v)[mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) {
+ $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*([kv][mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) {
CHK("ALLOC_SIZEOF_STRUCT",
"Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr);
}
}
}
+# check for bool bitfields
+ if ($sline =~ /^.\s+bool\s*$Ident\s*:\s*\d+\s*;/) {
+ WARN("BOOL_BITFIELD",
+ "Avoid using bool as bitfield. Prefer bool bitfields as unsigned int or u<8|16|32>\n" . $herecurr);
+ }
+
+# check for bool use in .h files
+ if ($realfile =~ /\.h$/ &&
+ $sline =~ /^.\s+bool\s*$Ident\s*(?::\s*d+\s*)?;/) {
+ CHK("BOOL_MEMBER",
+ "Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384\n" . $herecurr);
+ }
+
# check for semaphores initialized locked
if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) {
WARN("CONSIDER_COMPLETION",
"please use device_initcall() or more appropriate function instead of __initcall() (see include/linux/init.h)\n" . $herecurr);
}
-# check for spin_is_locked(), suggest lockdep instead
- if ($line =~ /\bspin_is_locked\(/) {
- WARN("USE_LOCKDEP",
- "Where possible, use lockdep_assert_held instead of assertions based on spin_is_locked\n" . $herecurr);
- }
-
-# check for deprecated apis
- if ($line =~ /\b($deprecated_apis_search)\b\s*\(/) {
- my $deprecated_api = $1;
- my $new_api = $deprecated_apis{$deprecated_api};
- WARN("DEPRECATED_API",
- "Deprecated use of '$deprecated_api', prefer '$new_api' instead\n" . $herecurr);
- }
-
# check for various structs that are normally const (ops, kgdb, device_tree)
# and avoid what seem like struct definitions 'struct foo {'
if ($line !~ /\bconst\b/ &&
"Using $1 should generally have parentheses around the comparison\n" . $herecurr);
}
-# nested likely/unlikely calls
- if ($line =~ /\b(?:(?:un)?likely)\s*\(\s*!?\s*(IS_ERR(?:_OR_NULL|_VALUE)?|WARN)/) {
- WARN("LIKELY_MISUSE",
- "nested (un)?likely() calls, $1 already uses unlikely() internally\n" . $herecurr);
- }
-
# whine mightly about in_atomic
if ($line =~ /\bin_atomic\s*\(/) {
if ($realfile =~ m@^drivers/@) {
"unknown module license " . $extracted_string . "\n" . $herecurr);
}
}
-
-# check for sysctl duplicate constants
- if ($line =~ /\.extra[12]\s*=\s*&(zero|one|int_max)\b/) {
- WARN("DUPLICATED_SYSCTL_CONST",
- "duplicated sysctl range checking value '$1', consider using the shared one in include/linux/sysctl.h\n" . $herecurr);
- }
}
# If we have no input at all, then there is nothing to report on
CONFIG_ARMV7_SECURE_RESERVE_SIZE
CONFIG_ARMV8_SWITCH_TO_EL1
CONFIG_ARM_ARCH_CP15_ERRATA
-CONFIG_ARM_DCC
CONFIG_ARM_FREQ
CONFIG_ARM_GIC_BASE_ADDRESS
CONFIG_ARM_PL180_MMCI_BASE
/* Simple test of sandbox SPI flash */
static int dm_test_spi_flash(struct unit_test_state *uts)
{
- struct udevice *dev, *emul;
+ struct udevice *dev;
int full_size = 0x200000;
int size = 0x10000;
u8 *src, *dst;
ut_assertok(spi_flash_read_dm(dev, 0, size, dst));
ut_asserteq_mem(src, dst, size);
- /* Try the write-protect stuff */
- ut_assertok(uclass_first_device_err(UCLASS_SPI_EMUL, &emul));
- ut_asserteq(0, spl_flash_get_sw_write_prot(dev));
- sandbox_sf_set_block_protect(emul, 1);
- ut_asserteq(1, spl_flash_get_sw_write_prot(dev));
- sandbox_sf_set_block_protect(emul, 0);
- ut_asserteq(0, spl_flash_get_sw_write_prot(dev));
-
/* Check mapping */
ut_assertok(dm_spi_get_mmap(dev, &map_base, &map_size, &offset));
ut_asserteq(0x1000, map_base);
o_opt = ''
cmds = (
['make', o_opt, '-s', board_type + '_defconfig'],
- ['make', o_opt, '-s', '-j8'],
+ ['make', o_opt, '-s', '-j{}'.format(os.cpu_count())],
)
name = 'make'
lseek(fd, blockstart + block_seek, SEEK_SET);
rc = read(fd, buf + processed, readlen);
- if (rc != readlen) {
+ if (rc == -1) {
fprintf(stderr, "Read error on %s: %s\n",
DEVNAME(dev), strerror(errno));
return -1;
}
+ if (rc != readlen) {
+ fprintf(stderr, "Read error on %s: "
+ "Attempted to read %d bytes but got %d\n",
+ DEVNAME(dev), readlen, rc);
+ return -1;
+ }
#ifdef DEBUG
fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
rc, (unsigned long long)blockstart + block_seek,
if (size < 0)
return -1;
- /* Add space for properties */
+ /* Add space for properties and hash node */
total_size += size + 300;
}
str[len] = '\0';
}
+/**
+ * add_crc_node() - Add a hash node to request a CRC checksum for an image
+ *
+ * @fdt: Device tree to add to (in sequential-write mode)
+ */
+static void add_crc_node(void *fdt)
+{
+ fdt_begin_node(fdt, "hash-1");
+ fdt_property_string(fdt, FIT_ALGO_PROP, "crc32");
+ fdt_end_node(fdt);
+}
+
/**
* fit_write_images() - Write out a list of images to the FIT
*
ret = fdt_property_file(params, fdt, FIT_DATA_PROP, params->datafile);
if (ret)
return ret;
+ add_crc_node(fdt);
fdt_end_node(fdt);
/* Now the device tree files if available */
genimg_get_arch_short_name(params->arch));
fdt_property_string(fdt, FIT_COMP_PROP,
genimg_get_comp_short_name(IH_COMP_NONE));
+ add_crc_node(fdt);
fdt_end_node(fdt);
}
params->fit_ramdisk);
if (ret)
return ret;
-
+ add_crc_node(fdt);
fdt_end_node(fdt);
}
projects / oweals / u-boot.git / commitdiff