drivers/clk/imx/clk-imx8mn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 NXP
   4  * Peng Fan <peng.fan@nxp.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <dt-bindings/clock/imx8mn-clock.h>
  14
  15 #include "clk.h"
  16
  17 #define PLL_1416X_RATE(_rate, _m, _p, _s)               \
  18         {                                               \
  19                 .rate   =       (_rate),                \
  20                 .mdiv   =       (_m),                   \
  21                 .pdiv   =       (_p),                   \
  22                 .sdiv   =       (_s),                   \
  23         }
  24
  25 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k)           \
  26         {                                               \
  27                 .rate   =       (_rate),                \
  28                 .mdiv   =       (_m),                   \
  29                 .pdiv   =       (_p),                   \
  30                 .sdiv   =       (_s),                   \
  31                 .kdiv   =       (_k),                   \
  32         }
  33
  34 static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
  35         PLL_1416X_RATE(1800000000U, 225, 3, 0),
  36         PLL_1416X_RATE(1600000000U, 200, 3, 0),
  37         PLL_1416X_RATE(1200000000U, 300, 3, 1),
  38         PLL_1416X_RATE(1000000000U, 250, 3, 1),
  39         PLL_1416X_RATE(800000000U,  200, 3, 1),
  40         PLL_1416X_RATE(750000000U,  250, 2, 2),
  41         PLL_1416X_RATE(700000000U,  350, 3, 2),
  42         PLL_1416X_RATE(600000000U,  300, 3, 2),
  43 };
  44
  45 static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
  46         PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  47 };
  48
  49 static struct imx_pll14xx_clk imx8mn_dram_pll __initdata = {
  50                 .type = PLL_1443X,
  51                 .rate_table = imx8mn_drampll_tbl,
  52                 .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
  53 };
  54
  55 static struct imx_pll14xx_clk imx8mn_arm_pll __initdata = {
  56                 .type = PLL_1416X,
  57                 .rate_table = imx8mn_pll1416x_tbl,
  58                 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
  59 };
  60
  61 static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
  62                 .type = PLL_1416X,
  63                 .rate_table = imx8mn_pll1416x_tbl,
  64                 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
  65 };
  66
  67 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
  68 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
  69 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
  70 static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
  71 static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
  72 static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
  73
  74 static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
  75                                         "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
  76
  77 static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
  78                                         "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
  79
  80 static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
  81                                              "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
  82
  83 static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
  84                                                "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
  85
  86 static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  87                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  88
  89 static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  90                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  91
  92 static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  93                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  94
  95 static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  96                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  97
  98 static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  99                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
 100
 101 static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
 102                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
 103
 104 static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
 105                                          "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
 106
 107 static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
 108                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
 109
 110 static ulong imx8mn_clk_get_rate(struct clk *clk)
 111 {
 112         struct clk *c;
 113         int ret;
 114
 115         debug("%s(#%lu)\n", __func__, clk->id);
 116
 117         ret = clk_get_by_id(clk->id, &c);
 118         if (ret)
 119                 return ret;
 120
 121         return clk_get_rate(c);
 122 }
 123
 124 static ulong imx8mn_clk_set_rate(struct clk *clk, unsigned long rate)
 125 {
 126         struct clk *c;
 127         int ret;
 128
 129         debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
 130
 131         ret = clk_get_by_id(clk->id, &c);
 132         if (ret)
 133                 return ret;
 134
 135         return clk_set_rate(c, rate);
 136 }
 137
 138 static int __imx8mn_clk_enable(struct clk *clk, bool enable)
 139 {
 140         struct clk *c;
 141         int ret;
 142
 143         debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
 144
 145         ret = clk_get_by_id(clk->id, &c);
 146         if (ret)
 147                 return ret;
 148
 149         if (enable)
 150                 ret = clk_enable(c);
 151         else
 152                 ret = clk_disable(c);
 153
 154         return ret;
 155 }
 156
 157 static int imx8mn_clk_disable(struct clk *clk)
 158 {
 159         return __imx8mn_clk_enable(clk, 0);
 160 }
 161
 162 static int imx8mn_clk_enable(struct clk *clk)
 163 {
 164         return __imx8mn_clk_enable(clk, 1);
 165 }
 166
 167 static struct clk_ops imx8mn_clk_ops = {
 168         .set_rate = imx8mn_clk_set_rate,
 169         .get_rate = imx8mn_clk_get_rate,
 170         .enable = imx8mn_clk_enable,
 171         .disable = imx8mn_clk_disable,
 172 };
 173
 174 static int imx8mn_clk_probe(struct udevice *dev)
 175 {
 176         void __iomem *base;
 177
 178         base = (void *)ANATOP_BASE_ADDR;
 179
 180         clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
 181                imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
 182                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 183         clk_dm(IMX8MN_ARM_PLL_REF_SEL,
 184                imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
 185                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 186         clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
 187                imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
 188                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 189         clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
 190                imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
 191                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 192         clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
 193                imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
 194                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 195
 196         clk_dm(IMX8MN_DRAM_PLL,
 197                imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
 198                                base + 0x50, &imx8mn_dram_pll));
 199         clk_dm(IMX8MN_ARM_PLL,
 200                imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
 201                                base + 0x84, &imx8mn_arm_pll));
 202         clk_dm(IMX8MN_SYS_PLL1,
 203                imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
 204                                base + 0x94, &imx8mn_sys_pll));
 205         clk_dm(IMX8MN_SYS_PLL2,
 206                imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
 207                                base + 0x104, &imx8mn_sys_pll));
 208         clk_dm(IMX8MN_SYS_PLL3,
 209                imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
 210                                base + 0x114, &imx8mn_sys_pll));
 211
 212         /* PLL bypass out */
 213         clk_dm(IMX8MN_DRAM_PLL_BYPASS,
 214                imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
 215                                  dram_pll_bypass_sels,
 216                                  ARRAY_SIZE(dram_pll_bypass_sels),
 217                                  CLK_SET_RATE_PARENT));
 218         clk_dm(IMX8MN_ARM_PLL_BYPASS,
 219                imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
 220                                  arm_pll_bypass_sels,
 221                                  ARRAY_SIZE(arm_pll_bypass_sels),
 222                                  CLK_SET_RATE_PARENT));
 223         clk_dm(IMX8MN_SYS_PLL1_BYPASS,
 224                imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
 225                                  sys_pll1_bypass_sels,
 226                                  ARRAY_SIZE(sys_pll1_bypass_sels),
 227                                  CLK_SET_RATE_PARENT));
 228         clk_dm(IMX8MN_SYS_PLL2_BYPASS,
 229                imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
 230                                  sys_pll2_bypass_sels,
 231                                  ARRAY_SIZE(sys_pll2_bypass_sels),
 232                                  CLK_SET_RATE_PARENT));
 233         clk_dm(IMX8MN_SYS_PLL3_BYPASS,
 234                imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
 235                                  sys_pll3_bypass_sels,
 236                                  ARRAY_SIZE(sys_pll3_bypass_sels),
 237                                  CLK_SET_RATE_PARENT));
 238
 239         /* PLL out gate */
 240         clk_dm(IMX8MN_DRAM_PLL_OUT,
 241                imx_clk_gate("dram_pll_out", "dram_pll_bypass",
 242                             base + 0x50, 13));
 243         clk_dm(IMX8MN_ARM_PLL_OUT,
 244                imx_clk_gate("arm_pll_out", "arm_pll_bypass",
 245                             base + 0x84, 11));
 246         clk_dm(IMX8MN_SYS_PLL1_OUT,
 247                imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
 248                             base + 0x94, 11));
 249         clk_dm(IMX8MN_SYS_PLL2_OUT,
 250                imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
 251                             base + 0x104, 11));
 252         clk_dm(IMX8MN_SYS_PLL3_OUT,
 253                imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
 254                             base + 0x114, 11));
 255
 256         /* SYS PLL fixed output */
 257         clk_dm(IMX8MN_SYS_PLL1_40M,
 258                imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
 259         clk_dm(IMX8MN_SYS_PLL1_80M,
 260                imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
 261         clk_dm(IMX8MN_SYS_PLL1_100M,
 262                imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
 263         clk_dm(IMX8MN_SYS_PLL1_133M,
 264                imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
 265         clk_dm(IMX8MN_SYS_PLL1_160M,
 266                imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
 267         clk_dm(IMX8MN_SYS_PLL1_200M,
 268                imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
 269         clk_dm(IMX8MN_SYS_PLL1_266M,
 270                imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
 271         clk_dm(IMX8MN_SYS_PLL1_400M,
 272                imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
 273         clk_dm(IMX8MN_SYS_PLL1_800M,
 274                imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
 275
 276         clk_dm(IMX8MN_SYS_PLL2_50M,
 277                imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
 278         clk_dm(IMX8MN_SYS_PLL2_100M,
 279                imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
 280         clk_dm(IMX8MN_SYS_PLL2_125M,
 281                imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
 282         clk_dm(IMX8MN_SYS_PLL2_166M,
 283                imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
 284         clk_dm(IMX8MN_SYS_PLL2_200M,
 285                imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
 286         clk_dm(IMX8MN_SYS_PLL2_250M,
 287                imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
 288         clk_dm(IMX8MN_SYS_PLL2_333M,
 289                imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
 290         clk_dm(IMX8MN_SYS_PLL2_500M,
 291                imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
 292         clk_dm(IMX8MN_SYS_PLL2_1000M,
 293                imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
 294
 295         base = dev_read_addr_ptr(dev);
 296         if (!base)
 297                 return -EINVAL;
 298
 299         clk_dm(IMX8MN_CLK_A53_SRC,
 300                imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
 301                             imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
 302         clk_dm(IMX8MN_CLK_A53_CG,
 303                imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 304         clk_dm(IMX8MN_CLK_A53_DIV,
 305                imx_clk_divider2("arm_a53_div", "arm_a53_cg",
 306                                 base + 0x8000, 0, 3));
 307
 308         clk_dm(IMX8MN_CLK_AHB,
 309                imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
 310                                             base + 0x9000));
 311         clk_dm(IMX8MN_CLK_IPG_ROOT,
 312                imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
 313
 314         clk_dm(IMX8MN_CLK_ENET_AXI,
 315                imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
 316                                    base + 0x8880));
 317         clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
 318                imx8m_clk_composite_critical("nand_usdhc_bus",
 319                                             imx8mn_nand_usdhc_sels,
 320                                             base + 0x8900));
 321
 322         /* IP */
 323         clk_dm(IMX8MN_CLK_USDHC1,
 324                imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
 325                                    base + 0xac00));
 326         clk_dm(IMX8MN_CLK_USDHC2,
 327                imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
 328                                    base + 0xac80));
 329         clk_dm(IMX8MN_CLK_I2C1,
 330                imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
 331         clk_dm(IMX8MN_CLK_I2C2,
 332                imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
 333         clk_dm(IMX8MN_CLK_I2C3,
 334                imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
 335         clk_dm(IMX8MN_CLK_I2C4,
 336                imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
 337         clk_dm(IMX8MN_CLK_WDOG,
 338                imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
 339         clk_dm(IMX8MN_CLK_USDHC3,
 340                imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
 341                                    base + 0xbc80));
 342
 343         clk_dm(IMX8MN_CLK_I2C1_ROOT,
 344                imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
 345         clk_dm(IMX8MN_CLK_I2C2_ROOT,
 346                imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
 347         clk_dm(IMX8MN_CLK_I2C3_ROOT,
 348                imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
 349         clk_dm(IMX8MN_CLK_I2C4_ROOT,
 350                imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 351         clk_dm(IMX8MN_CLK_OCOTP_ROOT,
 352                imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
 353         clk_dm(IMX8MN_CLK_USDHC1_ROOT,
 354                imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 355         clk_dm(IMX8MN_CLK_USDHC2_ROOT,
 356                imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 357         clk_dm(IMX8MN_CLK_WDOG1_ROOT,
 358                imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
 359         clk_dm(IMX8MN_CLK_WDOG2_ROOT,
 360                imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
 361         clk_dm(IMX8MN_CLK_WDOG3_ROOT,
 362                imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
 363         clk_dm(IMX8MN_CLK_USDHC3_ROOT,
 364                imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 365
 366 #ifdef CONFIG_SPL_BUILD
 367         struct clk *clkp, *clkp1;
 368
 369         clk_get_by_id(IMX8MN_CLK_WDOG1_ROOT, &clkp);
 370         clk_enable(clkp);
 371         clk_get_by_id(IMX8MN_CLK_WDOG2_ROOT, &clkp);
 372         clk_enable(clkp);
 373         clk_get_by_id(IMX8MN_CLK_WDOG3_ROOT, &clkp);
 374         clk_enable(clkp);
 375
 376         /* Configure SYS_PLL3 to 600MHz */
 377         clk_get_by_id(IMX8MN_SYS_PLL3, &clkp);
 378         clk_set_rate(clkp, 600000000UL);
 379         clk_enable(clkp);
 380
 381         /* Configure ARM to sys_pll2_500m */
 382         clk_get_by_id(IMX8MN_CLK_A53_SRC, &clkp);
 383         clk_get_by_id(IMX8MN_SYS_PLL2_OUT, &clkp1);
 384         clk_enable(clkp1);
 385         clk_get_by_id(IMX8MN_SYS_PLL2_500M, &clkp1);
 386         clk_set_parent(clkp, clkp1);
 387
 388         /* Configure ARM PLL to 1.2GHz */
 389         clk_get_by_id(IMX8MN_ARM_PLL, &clkp1);
 390         clk_set_rate(clkp1, 1200000000UL);
 391         clk_get_by_id(IMX8MN_ARM_PLL_OUT, &clkp1);
 392         clk_enable(clkp1);
 393         clk_set_parent(clkp, clkp1);
 394
 395         /* Configure DIV to 1.2GHz */
 396         clk_get_by_id(IMX8MN_CLK_A53_DIV, &clkp1);
 397         clk_set_rate(clkp1, 1200000000UL);
 398 #endif
 399
 400         return 0;
 401 }
 402
 403 static const struct udevice_id imx8mn_clk_ids[] = {
 404         { .compatible = "fsl,imx8mn-ccm" },
 405         { },
 406 };
 407
 408 U_BOOT_DRIVER(imx8mn_clk) = {
 409         .name = "clk_imx8mn",
 410         .id = UCLASS_CLK,
 411         .of_match = imx8mn_clk_ids,
 412         .ops = &imx8mn_clk_ops,
 413         .probe = imx8mn_clk_probe,
 414         .flags = DM_FLAG_PRE_RELOC,
 415 };