drivers/clk/imx/clk-imx8mn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 NXP
   4  * Peng Fan <peng.fan@nxp.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <log.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <dt-bindings/clock/imx8mn-clock.h>
  15
  16 #include "clk.h"
  17
  18 #define PLL_1416X_RATE(_rate, _m, _p, _s)               \
  19         {                                               \
  20                 .rate   =       (_rate),                \
  21                 .mdiv   =       (_m),                   \
  22                 .pdiv   =       (_p),                   \
  23                 .sdiv   =       (_s),                   \
  24         }
  25
  26 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k)           \
  27         {                                               \
  28                 .rate   =       (_rate),                \
  29                 .mdiv   =       (_m),                   \
  30                 .pdiv   =       (_p),                   \
  31                 .sdiv   =       (_s),                   \
  32                 .kdiv   =       (_k),                   \
  33         }
  34
  35 static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
  36         PLL_1416X_RATE(1800000000U, 225, 3, 0),
  37         PLL_1416X_RATE(1600000000U, 200, 3, 0),
  38         PLL_1416X_RATE(1200000000U, 300, 3, 1),
  39         PLL_1416X_RATE(1000000000U, 250, 3, 1),
  40         PLL_1416X_RATE(800000000U,  200, 3, 1),
  41         PLL_1416X_RATE(750000000U,  250, 2, 2),
  42         PLL_1416X_RATE(700000000U,  350, 3, 2),
  43         PLL_1416X_RATE(600000000U,  300, 3, 2),
  44 };
  45
  46 static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
  47         PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  48 };
  49
  50 static struct imx_pll14xx_clk imx8mn_dram_pll __initdata = {
  51                 .type = PLL_1443X,
  52                 .rate_table = imx8mn_drampll_tbl,
  53                 .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
  54 };
  55
  56 static struct imx_pll14xx_clk imx8mn_arm_pll __initdata = {
  57                 .type = PLL_1416X,
  58                 .rate_table = imx8mn_pll1416x_tbl,
  59                 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
  60 };
  61
  62 static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
  63                 .type = PLL_1416X,
  64                 .rate_table = imx8mn_pll1416x_tbl,
  65                 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
  66 };
  67
  68 static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
  69 static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
  70 static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
  71 static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
  72 static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
  73 static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
  74
  75 static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
  76                                         "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
  77
  78 static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
  79                                         "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
  80
  81 static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
  82                                              "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
  83
  84 static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
  85                                                "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
  86
  87 static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  88                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  89
  90 static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  91                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  92
  93 static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  94                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  95
  96 static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  97                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  98
  99 static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
 100                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
 101
 102 static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
 103                                          "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
 104
 105 static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
 106                                          "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
 107
 108 static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
 109                                            "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
 110
 111 static ulong imx8mn_clk_get_rate(struct clk *clk)
 112 {
 113         struct clk *c;
 114         int ret;
 115
 116         debug("%s(#%lu)\n", __func__, clk->id);
 117
 118         ret = clk_get_by_id(clk->id, &c);
 119         if (ret)
 120                 return ret;
 121
 122         return clk_get_rate(c);
 123 }
 124
 125 static ulong imx8mn_clk_set_rate(struct clk *clk, unsigned long rate)
 126 {
 127         struct clk *c;
 128         int ret;
 129
 130         debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
 131
 132         ret = clk_get_by_id(clk->id, &c);
 133         if (ret)
 134                 return ret;
 135
 136         return clk_set_rate(c, rate);
 137 }
 138
 139 static int __imx8mn_clk_enable(struct clk *clk, bool enable)
 140 {
 141         struct clk *c;
 142         int ret;
 143
 144         debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
 145
 146         ret = clk_get_by_id(clk->id, &c);
 147         if (ret)
 148                 return ret;
 149
 150         if (enable)
 151                 ret = clk_enable(c);
 152         else
 153                 ret = clk_disable(c);
 154
 155         return ret;
 156 }
 157
 158 static int imx8mn_clk_disable(struct clk *clk)
 159 {
 160         return __imx8mn_clk_enable(clk, 0);
 161 }
 162
 163 static int imx8mn_clk_enable(struct clk *clk)
 164 {
 165         return __imx8mn_clk_enable(clk, 1);
 166 }
 167
 168 static struct clk_ops imx8mn_clk_ops = {
 169         .set_rate = imx8mn_clk_set_rate,
 170         .get_rate = imx8mn_clk_get_rate,
 171         .enable = imx8mn_clk_enable,
 172         .disable = imx8mn_clk_disable,
 173 };
 174
 175 static int imx8mn_clk_probe(struct udevice *dev)
 176 {
 177         void __iomem *base;
 178
 179         base = (void *)ANATOP_BASE_ADDR;
 180
 181         clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
 182                imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
 183                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 184         clk_dm(IMX8MN_ARM_PLL_REF_SEL,
 185                imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
 186                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 187         clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
 188                imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
 189                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 190         clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
 191                imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
 192                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 193         clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
 194                imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
 195                            pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 196
 197         clk_dm(IMX8MN_DRAM_PLL,
 198                imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
 199                                base + 0x50, &imx8mn_dram_pll));
 200         clk_dm(IMX8MN_ARM_PLL,
 201                imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
 202                                base + 0x84, &imx8mn_arm_pll));
 203         clk_dm(IMX8MN_SYS_PLL1,
 204                imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
 205                                base + 0x94, &imx8mn_sys_pll));
 206         clk_dm(IMX8MN_SYS_PLL2,
 207                imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
 208                                base + 0x104, &imx8mn_sys_pll));
 209         clk_dm(IMX8MN_SYS_PLL3,
 210                imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
 211                                base + 0x114, &imx8mn_sys_pll));
 212
 213         /* PLL bypass out */
 214         clk_dm(IMX8MN_DRAM_PLL_BYPASS,
 215                imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
 216                                  dram_pll_bypass_sels,
 217                                  ARRAY_SIZE(dram_pll_bypass_sels),
 218                                  CLK_SET_RATE_PARENT));
 219         clk_dm(IMX8MN_ARM_PLL_BYPASS,
 220                imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
 221                                  arm_pll_bypass_sels,
 222                                  ARRAY_SIZE(arm_pll_bypass_sels),
 223                                  CLK_SET_RATE_PARENT));
 224         clk_dm(IMX8MN_SYS_PLL1_BYPASS,
 225                imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
 226                                  sys_pll1_bypass_sels,
 227                                  ARRAY_SIZE(sys_pll1_bypass_sels),
 228                                  CLK_SET_RATE_PARENT));
 229         clk_dm(IMX8MN_SYS_PLL2_BYPASS,
 230                imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
 231                                  sys_pll2_bypass_sels,
 232                                  ARRAY_SIZE(sys_pll2_bypass_sels),
 233                                  CLK_SET_RATE_PARENT));
 234         clk_dm(IMX8MN_SYS_PLL3_BYPASS,
 235                imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
 236                                  sys_pll3_bypass_sels,
 237                                  ARRAY_SIZE(sys_pll3_bypass_sels),
 238                                  CLK_SET_RATE_PARENT));
 239
 240         /* PLL out gate */
 241         clk_dm(IMX8MN_DRAM_PLL_OUT,
 242                imx_clk_gate("dram_pll_out", "dram_pll_bypass",
 243                             base + 0x50, 13));
 244         clk_dm(IMX8MN_ARM_PLL_OUT,
 245                imx_clk_gate("arm_pll_out", "arm_pll_bypass",
 246                             base + 0x84, 11));
 247         clk_dm(IMX8MN_SYS_PLL1_OUT,
 248                imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
 249                             base + 0x94, 11));
 250         clk_dm(IMX8MN_SYS_PLL2_OUT,
 251                imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
 252                             base + 0x104, 11));
 253         clk_dm(IMX8MN_SYS_PLL3_OUT,
 254                imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
 255                             base + 0x114, 11));
 256
 257         /* SYS PLL fixed output */
 258         clk_dm(IMX8MN_SYS_PLL1_40M,
 259                imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
 260         clk_dm(IMX8MN_SYS_PLL1_80M,
 261                imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
 262         clk_dm(IMX8MN_SYS_PLL1_100M,
 263                imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
 264         clk_dm(IMX8MN_SYS_PLL1_133M,
 265                imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
 266         clk_dm(IMX8MN_SYS_PLL1_160M,
 267                imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
 268         clk_dm(IMX8MN_SYS_PLL1_200M,
 269                imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
 270         clk_dm(IMX8MN_SYS_PLL1_266M,
 271                imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
 272         clk_dm(IMX8MN_SYS_PLL1_400M,
 273                imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
 274         clk_dm(IMX8MN_SYS_PLL1_800M,
 275                imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
 276
 277         clk_dm(IMX8MN_SYS_PLL2_50M,
 278                imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
 279         clk_dm(IMX8MN_SYS_PLL2_100M,
 280                imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
 281         clk_dm(IMX8MN_SYS_PLL2_125M,
 282                imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
 283         clk_dm(IMX8MN_SYS_PLL2_166M,
 284                imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
 285         clk_dm(IMX8MN_SYS_PLL2_200M,
 286                imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
 287         clk_dm(IMX8MN_SYS_PLL2_250M,
 288                imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
 289         clk_dm(IMX8MN_SYS_PLL2_333M,
 290                imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
 291         clk_dm(IMX8MN_SYS_PLL2_500M,
 292                imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
 293         clk_dm(IMX8MN_SYS_PLL2_1000M,
 294                imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
 295
 296         base = dev_read_addr_ptr(dev);
 297         if (!base)
 298                 return -EINVAL;
 299
 300         clk_dm(IMX8MN_CLK_A53_SRC,
 301                imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
 302                             imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
 303         clk_dm(IMX8MN_CLK_A53_CG,
 304                imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 305         clk_dm(IMX8MN_CLK_A53_DIV,
 306                imx_clk_divider2("arm_a53_div", "arm_a53_cg",
 307                                 base + 0x8000, 0, 3));
 308
 309         clk_dm(IMX8MN_CLK_AHB,
 310                imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
 311                                             base + 0x9000));
 312         clk_dm(IMX8MN_CLK_IPG_ROOT,
 313                imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
 314
 315         clk_dm(IMX8MN_CLK_ENET_AXI,
 316                imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
 317                                    base + 0x8880));
 318         clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
 319                imx8m_clk_composite_critical("nand_usdhc_bus",
 320                                             imx8mn_nand_usdhc_sels,
 321                                             base + 0x8900));
 322
 323         /* IP */
 324         clk_dm(IMX8MN_CLK_USDHC1,
 325                imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
 326                                    base + 0xac00));
 327         clk_dm(IMX8MN_CLK_USDHC2,
 328                imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
 329                                    base + 0xac80));
 330         clk_dm(IMX8MN_CLK_I2C1,
 331                imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
 332         clk_dm(IMX8MN_CLK_I2C2,
 333                imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
 334         clk_dm(IMX8MN_CLK_I2C3,
 335                imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
 336         clk_dm(IMX8MN_CLK_I2C4,
 337                imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
 338         clk_dm(IMX8MN_CLK_WDOG,
 339                imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
 340         clk_dm(IMX8MN_CLK_USDHC3,
 341                imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
 342                                    base + 0xbc80));
 343
 344         clk_dm(IMX8MN_CLK_I2C1_ROOT,
 345                imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
 346         clk_dm(IMX8MN_CLK_I2C2_ROOT,
 347                imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
 348         clk_dm(IMX8MN_CLK_I2C3_ROOT,
 349                imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
 350         clk_dm(IMX8MN_CLK_I2C4_ROOT,
 351                imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 352         clk_dm(IMX8MN_CLK_OCOTP_ROOT,
 353                imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
 354         clk_dm(IMX8MN_CLK_USDHC1_ROOT,
 355                imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 356         clk_dm(IMX8MN_CLK_USDHC2_ROOT,
 357                imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 358         clk_dm(IMX8MN_CLK_WDOG1_ROOT,
 359                imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
 360         clk_dm(IMX8MN_CLK_WDOG2_ROOT,
 361                imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
 362         clk_dm(IMX8MN_CLK_WDOG3_ROOT,
 363                imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
 364         clk_dm(IMX8MN_CLK_USDHC3_ROOT,
 365                imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 366
 367 #ifdef CONFIG_SPL_BUILD
 368         struct clk *clkp, *clkp1;
 369
 370         clk_get_by_id(IMX8MN_CLK_WDOG1_ROOT, &clkp);
 371         clk_enable(clkp);
 372         clk_get_by_id(IMX8MN_CLK_WDOG2_ROOT, &clkp);
 373         clk_enable(clkp);
 374         clk_get_by_id(IMX8MN_CLK_WDOG3_ROOT, &clkp);
 375         clk_enable(clkp);
 376
 377         /* Configure SYS_PLL3 to 600MHz */
 378         clk_get_by_id(IMX8MN_SYS_PLL3, &clkp);
 379         clk_set_rate(clkp, 600000000UL);
 380         clk_enable(clkp);
 381
 382         /* Configure ARM to sys_pll2_500m */
 383         clk_get_by_id(IMX8MN_CLK_A53_SRC, &clkp);
 384         clk_get_by_id(IMX8MN_SYS_PLL2_OUT, &clkp1);
 385         clk_enable(clkp1);
 386         clk_get_by_id(IMX8MN_SYS_PLL2_500M, &clkp1);
 387         clk_set_parent(clkp, clkp1);
 388
 389         /* Configure ARM PLL to 1.2GHz */
 390         clk_get_by_id(IMX8MN_ARM_PLL, &clkp1);
 391         clk_set_rate(clkp1, 1200000000UL);
 392         clk_get_by_id(IMX8MN_ARM_PLL_OUT, &clkp1);
 393         clk_enable(clkp1);
 394         clk_set_parent(clkp, clkp1);
 395
 396         /* Configure DIV to 1.2GHz */
 397         clk_get_by_id(IMX8MN_CLK_A53_DIV, &clkp1);
 398         clk_set_rate(clkp1, 1200000000UL);
 399 #endif
 400
 401         return 0;
 402 }
 403
 404 static const struct udevice_id imx8mn_clk_ids[] = {
 405         { .compatible = "fsl,imx8mn-ccm" },
 406         { },
 407 };
 408
 409 U_BOOT_DRIVER(imx8mn_clk) = {
 410         .name = "clk_imx8mn",
 411         .id = UCLASS_CLK,
 412         .of_match = imx8mn_clk_ids,
 413         .ops = &imx8mn_clk_ops,
 414         .probe = imx8mn_clk_probe,
 415         .flags = DM_FLAG_PRE_RELOC,
 416 };