drivers/cache/cache-v5l2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Andes Technology Corporation
   4  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cache.h>
  10 #include <dm.h>
  11 #include <hang.h>
  12 #include <asm/io.h>
  13 #include <dm/ofnode.h>
  14
  15 struct l2cache {
  16         volatile u64    configure;
  17         volatile u64    control;
  18         volatile u64    hpm0;
  19         volatile u64    hpm1;
  20         volatile u64    hpm2;
  21         volatile u64    hpm3;
  22         volatile u64    error_status;
  23         volatile u64    ecc_error;
  24         volatile u64    cctl_command0;
  25         volatile u64    cctl_access_line0;
  26         volatile u64    cctl_command1;
  27         volatile u64    cctl_access_line1;
  28         volatile u64    cctl_command2;
  29         volatile u64    cctl_access_line2;
  30         volatile u64    cctl_command3;
  31         volatile u64    cctl_access_line4;
  32         volatile u64    cctl_status;
  33 };
  34
  35 /* Control Register */
  36 #define L2_ENABLE       0x1
  37 /* prefetch */
  38 #define IPREPETCH_OFF   3
  39 #define DPREPETCH_OFF   5
  40 #define IPREPETCH_MSK   (3 << IPREPETCH_OFF)
  41 #define DPREPETCH_MSK   (3 << DPREPETCH_OFF)
  42 /* tag ram */
  43 #define TRAMOCTL_OFF    8
  44 #define TRAMICTL_OFF    10
  45 #define TRAMOCTL_MSK    (3 << TRAMOCTL_OFF)
  46 #define TRAMICTL_MSK    BIT(TRAMICTL_OFF)
  47 /* data ram */
  48 #define DRAMOCTL_OFF    11
  49 #define DRAMICTL_OFF    13
  50 #define DRAMOCTL_MSK    (3 << DRAMOCTL_OFF)
  51 #define DRAMICTL_MSK    BIT(DRAMICTL_OFF)
  52
  53 /* CCTL Command Register */
  54 #define CCTL_CMD_REG(base, hart)        ((ulong)(base) + 0x40 + (hart) * 0x10)
  55 #define L2_WBINVAL_ALL  0x12
  56
  57 /* CCTL Status Register */
  58 #define CCTL_STATUS_MSK(hart)           (0xf << ((hart) * 4))
  59 #define CCTL_STATUS_IDLE(hart)          (0 << ((hart) * 4))
  60 #define CCTL_STATUS_PROCESS(hart)       (1 << ((hart) * 4))
  61 #define CCTL_STATUS_ILLEGAL(hart)       (2 << ((hart) * 4))
  62
  63 DECLARE_GLOBAL_DATA_PTR;
  64
  65 struct v5l2_plat {
  66         struct l2cache  *regs;
  67         u32             iprefetch;
  68         u32             dprefetch;
  69         u32             tram_ctl[2];
  70         u32             dram_ctl[2];
  71 };
  72
  73 static int v5l2_enable(struct udevice *dev)
  74 {
  75         struct v5l2_plat *plat = dev_get_platdata(dev);
  76         volatile struct l2cache *regs = plat->regs;
  77
  78         if (regs)
  79                 setbits_le32(&regs->control, L2_ENABLE);
  80
  81         return 0;
  82 }
  83
  84 static int v5l2_disable(struct udevice *dev)
  85 {
  86         struct v5l2_plat *plat = dev_get_platdata(dev);
  87         volatile struct l2cache *regs = plat->regs;
  88         u8 hart = gd->arch.boot_hart;
  89         void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
  90
  91         if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
  92                 writel(L2_WBINVAL_ALL, cctlcmd);
  93
  94                 while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) {
  95                         if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
  96                                 printf("L2 flush illegal! hanging...");
  97                                 hang();
  98                         }
  99                 }
 100                 clrbits_le32(&regs->control, L2_ENABLE);
 101         }
 102
 103         return 0;
 104 }
 105
 106 static int v5l2_ofdata_to_platdata(struct udevice *dev)
 107 {
 108         struct v5l2_plat *plat = dev_get_platdata(dev);
 109         struct l2cache *regs;
 110
 111         regs = (struct l2cache *)dev_read_addr(dev);
 112         plat->regs = regs;
 113
 114         plat->iprefetch = -EINVAL;
 115         plat->dprefetch = -EINVAL;
 116         plat->tram_ctl[0] = -EINVAL;
 117         plat->dram_ctl[0] = -EINVAL;
 118
 119         /* Instruction and data fetch prefetch depth */
 120         dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
 121         dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
 122
 123         /* Set tag RAM and data RAM setup and output cycle */
 124         dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
 125         dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
 126
 127         return 0;
 128 }
 129
 130 static int v5l2_probe(struct udevice *dev)
 131 {
 132         struct v5l2_plat *plat = dev_get_platdata(dev);
 133         struct l2cache *regs = plat->regs;
 134         u32 ctl_val;
 135
 136         ctl_val = readl(&regs->control);
 137
 138         if (!(ctl_val & L2_ENABLE))
 139                 ctl_val |= L2_ENABLE;
 140
 141         if (plat->iprefetch != -EINVAL) {
 142                 ctl_val &= ~(IPREPETCH_MSK);
 143                 ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
 144         }
 145
 146         if (plat->dprefetch != -EINVAL) {
 147                 ctl_val &= ~(DPREPETCH_MSK);
 148                 ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
 149         }
 150
 151         if (plat->tram_ctl[0] != -EINVAL) {
 152                 ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
 153                 ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
 154                 ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
 155         }
 156
 157         if (plat->dram_ctl[0] != -EINVAL) {
 158                 ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
 159                 ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
 160                 ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
 161         }
 162
 163         writel(ctl_val, &regs->control);
 164
 165         return 0;
 166 }
 167
 168 static const struct udevice_id v5l2_cache_ids[] = {
 169         { .compatible = "v5l2cache" },
 170         {}
 171 };
 172
 173 static const struct cache_ops v5l2_cache_ops = {
 174         .enable         = v5l2_enable,
 175         .disable        = v5l2_disable,
 176 };
 177
 178 U_BOOT_DRIVER(v5l2_cache) = {
 179         .name   = "v5l2_cache",
 180         .id     = UCLASS_CACHE,
 181         .of_match = v5l2_cache_ids,
 182         .ofdata_to_platdata = v5l2_ofdata_to_platdata,
 183         .probe  = v5l2_probe,
 184         .platdata_auto_alloc_size = sizeof(struct v5l2_plat),
 185         .ops = &v5l2_cache_ops,
 186         .flags  = DM_FLAG_PRE_RELOC,
 187 };