cache: l2x0: Fix write to incorrect shared-override bit

The existing code write bit-0 for shared attribute override enable bit.
It should be bit-22 based on cache controller specification [1].

[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246f/DDI0246F_l2c310_r3p2_trm.pdf

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
index 67c752d076f2c03e9cd9d7db9f032243714a7860..226824c2832eda7e632c2a057cc9343b9c1f6a52 100644 (file)
--- a/drivers/cache/cache-l2x0.c
+++ b/drivers/cache/cache-l2x0.c
@@ -33,8 +33,8 @@ static void l2c310_of_parse_and_init(struct udevice *dev)
                        saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
        }
 
-       saved_reg |= dev_read_bool(dev, "arm,shared-override");
-       writel(saved_reg, &regs->pl310_aux_ctrl);
+       if (dev_read_bool(dev, "arm,shared-override"))
+               saved_reg |= L310_SHARED_ATT_OVERRIDE_ENABLE;
 
        saved_reg = readl(&regs->pl310_tag_latency_ctrl);
        if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))