board/beacon/imx8mm/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <common.h>
   4 #include <cpu_func.h>
   5 #include <hang.h>
   6 #include <spl.h>
   7 #include <asm/io.h>
   8 #include <asm/mach-imx/iomux-v3.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx8mm_pins.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/mach-imx/boot_mode.h>
  13 #include <asm/arch/ddr.h>
  14
  15 #include <dm/uclass.h>
  16 #include <dm/device.h>
  17 #include <dm/uclass-internal.h>
  18 #include <dm/device-internal.h>
  19
  20 #include <power/pmic.h>
  21 #include <power/bd71837.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 int spl_board_boot_device(enum boot_device boot_dev_spl)
  26 {
  27         switch (boot_dev_spl) {
  28         case SD2_BOOT:
  29         case MMC2_BOOT:
  30                 return BOOT_DEVICE_MMC1;
  31         case SD3_BOOT:
  32         case MMC3_BOOT:
  33                 return BOOT_DEVICE_MMC2;
  34         default:
  35                 return BOOT_DEVICE_NONE;
  36         }
  37 }
  38
  39 static void spl_dram_init(void)
  40 {
  41         ddr_init(&dram_timing);
  42 }
  43
  44 void spl_board_init(void)
  45 {
  46         debug("Normal Boot\n");
  47 }
  48
  49 #ifdef CONFIG_SPL_LOAD_FIT
  50 int board_fit_config_name_match(const char *name)
  51 {
  52         /* Just empty function now - can't decide what to choose */
  53         debug("%s: %s\n", __func__, name);
  54
  55         return 0;
  56 }
  57 #endif
  58
  59 #define UART_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  60 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  61
  62 static iomux_v3_cfg_t const uart_pads[] = {
  63         IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  64         IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  65 };
  66
  67 static iomux_v3_cfg_t const wdog_pads[] = {
  68         IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  69 };
  70
  71 int board_early_init_f(void)
  72 {
  73         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  74
  75         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  76
  77         set_wdog_reset(wdog);
  78
  79         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  80
  81         return 0;
  82 }
  83
  84 static int power_init_board(void)
  85 {
  86         struct udevice *dev;
  87         int ret;
  88
  89         ret = pmic_get("pmic@4b", &dev);
  90         if (ret == -ENODEV) {
  91                 puts("No pmic\n");
  92                 return 0;
  93         }
  94         if (ret != 0)
  95                 return ret;
  96
  97         /* decrease RESET key long push time from the default 10s to 10ms */
  98         pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
  99
 100         /* unlock the PMIC regs */
 101         pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
 102
 103         /* increase VDD_SOC to typical value 0.85v before first DRAM access */
 104         pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
 105
 106         /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
 107         pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
 108
 109         /* lock the PMIC regs */
 110         pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
 111
 112         return 0;
 113 }
 114
 115 void board_init_f(ulong dummy)
 116 {
 117         struct udevice *dev;
 118         int ret;
 119
 120         arch_cpu_init();
 121
 122         init_uart_clk(1);
 123
 124         board_early_init_f();
 125
 126         timer_init();
 127
 128         preloader_console_init();
 129
 130         /* Clear the BSS. */
 131         memset(__bss_start, 0, __bss_end - __bss_start);
 132
 133         ret = spl_early_init();
 134         if (ret) {
 135                 debug("spl_early_init() failed: %d\n", ret);
 136                 hang();
 137         }
 138
 139         ret = uclass_get_device_by_name(UCLASS_CLK,
 140                                         "clock-controller@30380000",
 141                                         &dev);
 142         if (ret < 0) {
 143                 printf("Failed to find clock node. Check device tree\n");
 144                 hang();
 145         }
 146
 147         enable_tzc380();
 148
 149         power_init_board();
 150
 151         /* DDR initialization */
 152         spl_dram_init();
 153
 154         board_init_r(NULL, 0);
 155 }