imx: Add support for i.MX8MM Beacon EmbeddedWorks devkit.
authorAdam Ford <aford173@gmail.com>
Sun, 3 May 2020 13:11:33 +0000 (08:11 -0500)
committerStefano Babic <sbabic@denx.de>
Sun, 10 May 2020 18:55:20 +0000 (20:55 +0200)
Beacon EmbeddedWorks, formerly known as Logic PD, is releasing
a devkit based on the i.MX8M Mini SoC consisting of baseboard +
SOM.

It supports eMMC on the SOM, microSD on the baseboard, various
GPIO, the PINCTRL, and UART.

Signed-off-by: Adam Ford <aford173@gmail.com>
15 files changed:
arch/arm/dts/Makefile
arch/arm/dts/imx8mm-beacon-baseboard.dtsi [new file with mode: 0644]
arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi [new file with mode: 0644]
arch/arm/dts/imx8mm-beacon-kit.dts [new file with mode: 0644]
arch/arm/dts/imx8mm-beacon-som.dtsi [new file with mode: 0644]
arch/arm/mach-imx/imx8m/Kconfig
board/beacon/imx8mm/Kconfig [new file with mode: 0644]
board/beacon/imx8mm/MAINTAINERS [new file with mode: 0644]
board/beacon/imx8mm/Makefile [new file with mode: 0644]
board/beacon/imx8mm/README [new file with mode: 0644]
board/beacon/imx8mm/imx8mm_beacon.c [new file with mode: 0644]
board/beacon/imx8mm/lpddr4_timing.c [new file with mode: 0644]
board/beacon/imx8mm/spl.c [new file with mode: 0644]
configs/imx8mm_beacon_defconfig [new file with mode: 0644]
include/configs/imx8mm_beacon.h [new file with mode: 0644]

index 121597756eaef7f077229df5e322bf9452d67243..1325134bd418bf3c3245e0d4a98f2c7d35c973d9 100644 (file)
@@ -736,6 +736,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
        imx8mm-verdin.dtb \
        imx8mn-ddr4-evk.dtb \
        imx8mq-evk.dtb \
+       imx8mm-beacon-kit.dtb \
        imx8mq-phanbell.dtb \
        imx8mp-evk.dtb \
        imx8mq-pico-pi.dtb
diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
new file mode 100644 (file)
index 0000000..baa5f99
--- /dev/null
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/ {
+       leds {
+               compatible = "gpio-leds";
+
+               led0 {
+                       label = "gen_led0";
+                       gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
+                       default-state = "none";
+               };
+
+               led1 {
+                       label = "gen_led1";
+                       gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
+                       default-state = "none";
+               };
+
+               led2 {
+                       label = "gen_led2";
+                       gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
+                       default-state = "none";
+               };
+
+               led3 {
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_led3>;
+                       label = "heartbeat";
+                       gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
+       };
+
+       reg_audio: regulator-audio {
+               compatible = "regulator-fixed";
+               regulator-name = "3v3_aud";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       reg_usdhc2_vmmc: regulator-usdhc2 {
+               compatible = "regulator-fixed";
+               regulator-name = "VSD_3V3";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       sound {
+               compatible = "fsl,imx-audio-wm8962";
+               model = "wm8962-audio";
+               audio-cpu = <&sai3>;
+               audio-codec = <&wm8962>;
+               audio-routing =
+                       "Headphone Jack", "HPOUTL",
+                       "Headphone Jack", "HPOUTR",
+                       "Ext Spk", "SPKOUTL",
+                       "Ext Spk", "SPKOUTR",
+                       "AMIC", "MICBIAS",
+                       "IN3R", "AMIC";
+       };
+};
+
+&ecspi2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_espi2>;
+       cs-gpios = <&gpio5 9 0>;
+       status = "okay";
+
+       eeprom@0 {
+               compatible = "microchip,at25160bn", "atmel,at25";
+               reg = <0>;
+               spi-max-frequency = <5000000>;
+               spi-cpha;
+               spi-cpol;
+               pagesize = <32>;
+               size = <2048>;
+               address-width = <16>;
+       };
+};
+
+&i2c2 {
+       clock-frequency = <400000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+};
+
+&i2c4 {
+       clock-frequency = <400000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c4>;
+       status = "okay";
+
+       wm8962: audio-codec@1a {
+               compatible = "wlf,wm8962";
+               reg = <0x1a>;
+               clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
+               clock-names = "xclk";
+               DCVDD-supply = <&reg_audio>;
+               DBVDD-supply = <&reg_audio>;
+               AVDD-supply = <&reg_audio>;
+               CPVDD-supply = <&reg_audio>;
+               MICVDD-supply = <&reg_audio>;
+               PLLVDD-supply = <&reg_audio>;
+               SPKVDD1-supply = <&reg_audio>;
+               SPKVDD2-supply = <&reg_audio>;
+               gpio-cfg = <
+                       0x0000 /* 0:Default */
+                       0x0000 /* 1:Default */
+                       0x0000 /* 2:FN_DMICCLK */
+                       0x0000 /* 3:Default */
+                       0x0000 /* 4:FN_DMICCDAT */
+                       0x0000 /* 5:Default */
+               >;
+       };
+
+       pca6416_0: gpio@20 {
+               compatible = "nxp,pcal6416";
+               reg = <0x20>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_pcal6414>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&gpio4>;
+               interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pca6416_1: gpio@21 {
+               compatible = "nxp,pcal6416";
+               reg = <0x21>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&gpio4>;
+               interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+       };
+};
+
+&sai3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_sai3>;
+       assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
+       assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+       assigned-clock-rates = <24576000>;
+       fsl,sai-mclk-direction-output;
+       status = "okay";
+};
+
+&snvs_pwrkey {
+       status = "okay";
+};
+
+&uart2 { /* console */
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart2>;
+       status = "okay";
+};
+
+&uart3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart3>;
+       assigned-clocks = <&clk IMX8MM_CLK_UART3>;
+       assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+       status = "okay";
+};
+
+&usdhc2 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+       bus-width = <4>;
+       vmmc-supply = <&reg_usdhc2_vmmc>;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl_espi2: espi2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK            0x82
+                       MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI            0x82
+                       MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO            0x82
+                       MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x41
+               >;
+       };
+
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
+                       MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
+               >;
+       };
+
+       pinctrl_i2c4: i2c4grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL          0x400001c3
+                       MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA          0x400001c3
+               >;
+       };
+
+       pinctrl_led3: led3grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28       0x41
+               >;
+       };
+
+       pinctrl_pcal6414: pcal6414-gpio {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27               0x19
+               >;
+       };
+
+       pinctrl_sai3: sai3grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
+                       MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
+                       MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
+                       MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
+                       MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
+               >;
+       };
+
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
+                       MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
+               >;
+       };
+
+       pinctrl_uart3: uart3grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX   0x40
+                       MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX   0x40
+               >;
+       };
+
+       pinctrl_usdhc2_gpio: usdhc2grpgpio {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B       0x41
+                       MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
+               >;
+       };
+
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+
+       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+
+       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+};
diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
new file mode 100644 (file)
index 0000000..fc1aebb
--- /dev/null
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/ {
+       wdt-reboot {
+               compatible = "wdt-reboot";
+               wdt = <&wdog1>;
+               u-boot,dm-spl;
+       };
+};
+
+&{/soc@0} {
+       u-boot,dm-pre-reloc;
+       u-boot,dm-spl;
+};
+
+&aips1 {
+       u-boot,dm-spl;
+       u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+       u-boot,dm-spl;
+};
+
+&aips3 {
+       u-boot,dm-spl;
+};
+
+&clk {
+       u-boot,dm-spl;
+       u-boot,dm-pre-reloc;
+       /delete-property/ assigned-clocks;
+       /delete-property/ assigned-clock-parents;
+       /delete-property/ assigned-clock-rates;
+};
+
+&fec1 {
+       phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
+
+&gpio1 {
+       u-boot,dm-spl;
+};
+
+&gpio2 {
+       u-boot,dm-spl;
+};
+
+&gpio3 {
+       u-boot,dm-spl;
+};
+
+&gpio4 {
+       u-boot,dm-spl;
+};
+
+&gpio5 {
+       u-boot,dm-spl;
+};
+
+&iomuxc {
+       u-boot,dm-spl;
+};
+
+&osc_24m {
+       u-boot,dm-spl;
+       u-boot,dm-pre-reloc;
+};
+
+&pca6416_0 {
+       compatible = "ti,tca6416";
+};
+
+&pca6416_1 {
+       compatible = "ti,tca6416";
+};
+
+&pinctrl_i2c1 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+       u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+       u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+       u-boot,dm-spl;
+};
+
+&uart2 {
+       u-boot,dm-spl;
+};
+
+&usdhc2 {
+       u-boot,dm-spl;
+};
+
+&usdhc3 {
+       u-boot,dm-spl;
+};
+
+&i2c1 {
+       u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+       u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+       u-boot,dm-spl;
+};
+
+&wdog1 {
+       u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-beacon-kit.dts b/arch/arm/dts/imx8mm-beacon-kit.dts
new file mode 100644 (file)
index 0000000..74a7b0c
--- /dev/null
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+#include "imx8mm-beacon-som.dtsi"
+#include "imx8mm-beacon-baseboard.dtsi"
+
+/ {
+       model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit";
+       compatible = "beacon,imx8mm-beacon-kit", "fsl,imx8mm";
+
+       chosen {
+               stdout-path = &uart2;
+       };
+};
diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi
new file mode 100644 (file)
index 0000000..801bd02
--- /dev/null
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+/ {
+       usdhc1_pwrseq: usdhc1_pwrseq {
+               compatible = "mmc-pwrseq-simple";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_usdhc1_gpio>;
+               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+               clocks = <&osc_32k>;
+               clock-names = "ext_clock";
+               post-power-on-delay-ms = <80>;
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0x0 0x40000000 0 0x80000000>;
+       };
+};
+
+&A53_0 {
+       cpu-supply = <&buck2_reg>;
+};
+
+&fec1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fec1>;
+       phy-mode = "rgmii-id";
+       phy-handle = <&ethphy0>;
+       fsl,magic-packet;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <0>;
+               };
+       };
+};
+
+&i2c1 {
+       clock-frequency = <400000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c1>;
+       status = "okay";
+
+       pmic@4b {
+               compatible = "rohm,bd71847";
+               reg = <0x4b>;
+               pinctrl-0 = <&pinctrl_pmic>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <3 GPIO_ACTIVE_LOW>;
+               rohm,reset-snvs-powered;
+
+               regulators {
+                       buck1_reg: BUCK1 {
+                               regulator-name = "buck1";
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <1300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <1250>;
+                       };
+
+                       buck2_reg: BUCK2 {
+                               regulator-name = "buck2";
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <1300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                               regulator-ramp-delay = <1250>;
+                               rohm,dvs-run-voltage = <1000000>;
+                               rohm,dvs-idle-voltage = <900000>;
+                       };
+
+                       buck3_reg: BUCK3 {
+                               // BUCK5 in datasheet
+                               regulator-name = "buck3";
+                               regulator-min-microvolt = <700000>;
+                               regulator-max-microvolt = <1350000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       buck4_reg: BUCK4 {
+                               // BUCK6 in datasheet
+                               regulator-name = "buck4";
+                               regulator-min-microvolt = <3000000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       buck5_reg: BUCK5 {
+                               // BUCK7 in datasheet
+                               regulator-name = "buck5";
+                               regulator-min-microvolt = <1605000>;
+                               regulator-max-microvolt = <1995000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       buck6_reg: BUCK6 {
+                               // BUCK8 in datasheet
+                               regulator-name = "buck6";
+                               regulator-min-microvolt = <800000>;
+                               regulator-max-microvolt = <1400000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       ldo1_reg: LDO1 {
+                               regulator-name = "ldo1";
+                               regulator-min-microvolt = <3000000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       ldo2_reg: LDO2 {
+                               regulator-name = "ldo2";
+                               regulator-min-microvolt = <900000>;
+                               regulator-max-microvolt = <900000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       ldo3_reg: LDO3 {
+                               regulator-name = "ldo3";
+                               regulator-min-microvolt = <1800000>;
+                               regulator-max-microvolt = <3300000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       ldo4_reg: LDO4 {
+                               regulator-name = "ldo4";
+                               regulator-min-microvolt = <900000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+
+                       ldo6_reg: LDO6 {
+                               regulator-name = "ldo6";
+                               regulator-min-microvolt = <900000>;
+                               regulator-max-microvolt = <1800000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+               };
+       };
+};
+
+&i2c3 {
+       clock-frequency = <400000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c3>;
+       status = "okay";
+
+       eeprom@50 {
+               compatible = "microchip, at24c64d", "atmel,24c64";
+               pagesize = <32>;
+               read-only;      /* Manufacturing EEPROM programmed at factory */
+               reg = <0x50>;
+       };
+
+       rtc@51 {
+               compatible = "nxp,pcf85263";
+               reg = <0x51>;
+       };
+};
+
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart1>;
+       assigned-clocks = <&clk IMX8MM_CLK_UART1>;
+       assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+       uart-has-rtscts;
+       status = "okay";
+
+       bluetooth {
+               compatible = "brcm,bcm43438-bt";
+               shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+               host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+               device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+               clocks = <&osc_32k>;
+               clock-names = "extclk";
+       };
+};
+
+&usdhc1 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc1>;
+       bus-width = <4>;
+       non-removable;
+       cap-power-off-card;
+       pm-ignore-notify;
+       keep-power-in-suspend;
+       mmc-pwrseq = <&usdhc1_pwrseq>;
+       status = "okay";
+
+       brcmf: bcrmf@1 {
+               reg = <1>;
+               compatible = "brcm,bcm4329-fmac";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_wlan>;
+               interrupt-parent = <&gpio2>;
+               interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "host-wake";
+       };
+};
+
+&usdhc3 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       bus-width = <8>;
+       non-removable;
+       status = "okay";
+};
+
+&wdog1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_wdog>;
+       fsl,ext-reset-output;
+       status = "okay";
+};
+
+&iomuxc {
+               pinctrl_fec1: fec1grp {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_ENET_MDC_ENET1_MDC         0x3
+                               MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
+                               MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
+                               MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
+                               MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
+                               MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
+                               MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
+                               MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
+                               MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
+                               MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
+                               MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
+                               MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
+                               MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
+                               MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
+                               MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
+                       >;
+               };
+
+               pinctrl_i2c1: i2c1grp {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
+                               MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
+                       >;
+               };
+
+               pinctrl_i2c3: i2c3grp {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
+                               MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
+                       >;
+               };
+
+               pinctrl_pmic: pmicirq {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x41
+                       >;
+               };
+
+               pinctrl_uart1: uart1grp {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
+                               MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
+                               MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
+                               MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
+                               MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6        0x19
+                               MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7        0x19
+                               MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x19
+                               MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x141
+                       >;
+               };
+
+               pinctrl_usdhc1_gpio: usdhc1grpgpio {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x41
+                       >;
+               };
+
+               pinctrl_usdhc1: usdhc1grp {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
+                               MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
+                               MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
+                               MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
+                               MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
+                               MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
+                       >;
+               };
+
+               pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
+                               MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
+                               MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
+                               MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
+                               MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
+                               MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
+                       >;
+               };
+
+               pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
+                               MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
+                               MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
+                               MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
+                               MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
+                               MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
+                       >;
+               };
+
+               pinctrl_usdhc3: usdhc3grp {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
+                               MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
+                               MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
+                               MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
+                               MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
+                               MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
+                               MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
+                               MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
+                               MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
+                               MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
+                               MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
+                       >;
+               };
+
+               pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
+                               MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
+                               MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
+                               MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
+                               MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
+                               MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
+                               MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
+                               MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
+                               MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
+                               MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
+                               MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
+                       >;
+               };
+
+               pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
+                               MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
+                               MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
+                               MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
+                               MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
+                               MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
+                               MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
+                               MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
+                               MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
+                               MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
+                               MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
+                       >;
+               };
+
+               pinctrl_wdog: wdoggrp {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
+                       >;
+               };
+
+               pinctrl_wlan: wlangrp {
+                       fsl,pins = <
+                               MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                0x111
+                       >;
+               };
+};
index 7d1fe758e66096548a490fc2d83ed01c157db44b..7771fc88afebcf9b901f95773bb2da24e8ac28da 100644 (file)
@@ -66,6 +66,12 @@ config TARGET_VERDIN_IMX8MM
        select SUPPORT_SPL
        select IMX8M_LPDDR4
 
+config TARGET_IMX8MM_BEACON
+       bool "imx8mm Beacon Embedded devkit"
+       select IMX8MM
+       select SUPPORT_SPL
+       select IMX8M_LPDDR4
+
 endchoice
 
 source "board/freescale/imx8mq_evk/Kconfig"
@@ -75,5 +81,6 @@ source "board/freescale/imx8mp_evk/Kconfig"
 source "board/google/imx8mq_phanbell/Kconfig"
 source "board/technexion/pico-imx8mq/Kconfig"
 source "board/toradex/verdin-imx8mm/Kconfig"
+source "board/beacon/imx8mm/Kconfig"
 
 endif
diff --git a/board/beacon/imx8mm/Kconfig b/board/beacon/imx8mm/Kconfig
new file mode 100644 (file)
index 0000000..df3125e
--- /dev/null
@@ -0,0 +1,14 @@
+if TARGET_IMX8MM_BEACON
+
+config SYS_BOARD
+       default "imx8mm"
+
+config SYS_VENDOR
+       default "beacon"
+
+config SYS_CONFIG_NAME
+       default "imx8mm_beacon"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/beacon/imx8mm/MAINTAINERS b/board/beacon/imx8mm/MAINTAINERS
new file mode 100644 (file)
index 0000000..e887db2
--- /dev/null
@@ -0,0 +1,7 @@
+i.MX8MM Beacon EmbeddedWorks Devkit
+
+M:     Adam Ford <aford173@gmail.com>
+S:     Maintained
+F:     board/beacon/imx8mm/
+F:     include/configs/imx8mm_beacon.h
+F:     configs/imx8mm_beacon_defconfig
diff --git a/board/beacon/imx8mm/Makefile b/board/beacon/imx8mm/Makefile
new file mode 100644 (file)
index 0000000..7d3bd31
--- /dev/null
@@ -0,0 +1,13 @@
+#
+# Copyright 2020 Compass Electronics Group, LLC
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mm_beacon.o
+obj-y += ../../freescale/common/
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += lpddr4_timing.o
+endif
diff --git a/board/beacon/imx8mm/README b/board/beacon/imx8mm/README
new file mode 100644 (file)
index 0000000..4223fbd
--- /dev/null
@@ -0,0 +1,37 @@
+U-Boot for the Beacon EmbeddedWorks Devkit
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+Note: $(srctree) is U-Boot source directory
+
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ git checkout imx_4.19.35_1.0.0
+$ make PLAT=imx8mm bl31 ARCH=arm CROSS_COMPILE=aarch64-linux-gnu-
+$ cp build/imx8mm/release/bl31.bin $(srctree)
+
+Get the DDR firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.5.bin
+$ chmod +x firmware-imx-8.5.bin
+$ ./firmware-imx-8.5
+$ cp firmware-imx-8.5/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+
+Build U-Boot
+============
+$ make imx8mm_beacon_defconfig
+$ make flash.bin ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000
+
+Burn U-Boot to microSD Card
+===========================
+$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
+
+Boot
+====
+Set Boot switch to SD boot
diff --git a/board/beacon/imx8mm/imx8mm_beacon.c b/board/beacon/imx8mm/imx8mm_beacon.c
new file mode 100644 (file)
index 0000000..e82e8b7
--- /dev/null
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+       /* rom_pointer[1] contains the size of TEE occupies */
+       if (rom_pointer[1])
+               gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+       else
+               gd->ram_size = PHYS_SDRAM_SIZE;
+
+       return 0;
+}
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+static int setup_fec(void)
+{
+       struct iomuxc_gpr_base_regs *gpr =
+               (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+       /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+       clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+       return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+       /* enable rgmii rxc skew and phy mode select to RGMII copper */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+       return 0;
+}
+#endif
+
+int board_init(void)
+{
+       if (IS_ENABLED(CONFIG_FEC_MXC))
+               setup_fec();
+
+       return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+       return devno;
+}
diff --git a/board/beacon/imx8mm/lpddr4_timing.c b/board/beacon/imx8mm/lpddr4_timing.c
new file mode 100644 (file)
index 0000000..8e48b9d
--- /dev/null
@@ -0,0 +1,1980 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+       /* Start to config, default 3200mbps */
+       { DDRC_DBG1(0), 0x00000001 },
+       { DDRC_PWRCTL(0), 0x00000001 },
+       { DDRC_MSTR(0), 0xa1080020 },
+       { DDRC_RFSHTMG(0), 0x005b00d2 },
+       { DDRC_INIT0(0), 0xC003061B },
+       { DDRC_INIT1(0), 0x009D0000 },
+       { DDRC_INIT3(0), 0x00D4002D },
+       { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+       { DDRC_INIT6(0), 0x0066004a },
+       { DDRC_INIT7(0), 0x0006004a },
+
+       { DDRC_DRAMTMG0(0), 0x1A201B22 },
+       { DDRC_DRAMTMG1(0), 0x00060633 },
+       { DDRC_DRAMTMG3(0), 0x00C0C000 },
+       { DDRC_DRAMTMG4(0), 0x0F04080F },
+       { DDRC_DRAMTMG5(0), 0x02040C0C },
+       { DDRC_DRAMTMG6(0), 0x01010007 },
+       { DDRC_DRAMTMG7(0), 0x00000401 },
+       { DDRC_DRAMTMG12(0), 0x00020600 },
+       { DDRC_DRAMTMG13(0), 0x0C100002 },
+       { DDRC_DRAMTMG14(0), 0x000000E6 },
+       { DDRC_DRAMTMG17(0), 0x00A00050 },
+
+       { DDRC_ZQCTL0(0), 0x03200018 },
+       { DDRC_ZQCTL1(0), 0x028061A8 },
+       { DDRC_ZQCTL2(0), 0x00000000 },
+
+       { DDRC_DFITMG0(0), 0x0497820A },
+       { DDRC_DFITMG2(0), 0x0000170A },
+       { DDRC_DRAMTMG2(0), 0x070E171a },
+       { DDRC_DBICTL(0), 0x00000001 },
+
+       { DDRC_DFITMG1(0), 0x00080303 },
+       { DDRC_DFIUPD0(0), 0xE0400018 },
+       { DDRC_DFIUPD1(0), 0x00DF00E4 },
+       { DDRC_DFIUPD2(0), 0x80000000 },
+       { DDRC_DFIMISC(0), 0x00000011 },
+
+       { DDRC_DFIPHYMSTR(0), 0x00000000 },
+       { DDRC_RANKCTL(0), 0x00000c99 },
+
+       /* address mapping */
+       { DDRC_ADDRMAP0(0), 0x0000001f },
+       { DDRC_ADDRMAP1(0), 0x00080808 },
+       { DDRC_ADDRMAP2(0), 0x00000000 },
+       { DDRC_ADDRMAP3(0), 0x00000000 },
+       { DDRC_ADDRMAP4(0), 0x00001f1f },
+       { DDRC_ADDRMAP5(0), 0x07070707 },
+       { DDRC_ADDRMAP6(0), 0x07070707 },
+       { DDRC_ADDRMAP7(0), 0x00000f0f },
+
+       /* performance setting */
+       { DDRC_SCHED(0), 0x29001701 },
+       { DDRC_SCHED1(0), 0x0000002c },
+       { DDRC_PERFHPR1(0), 0x04000030 },
+       { DDRC_PERFLPR1(0), 0x900093e7 },
+       { DDRC_PERFWR1(0), 0x20005574 },
+       { DDRC_PCCFG(0), 0x00000111 },
+       { DDRC_PCFGW_0(0), 0x000072ff },
+       { DDRC_PCFGQOS0_0(0), 0x02100e07 },
+       { DDRC_PCFGQOS1_0(0), 0x00620096 },
+       { DDRC_PCFGWQOS0_0(0), 0x01100e07 },
+       { DDRC_PCFGWQOS1_0(0), 0x00c8012c },
+
+       /* frequency P1&P2 */
+       /* Frequency 1: 400mbps */
+       { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
+       { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
+       { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
+       { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
+       { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
+       { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
+       { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
+       { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
+       { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
+       { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+       { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
+       { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
+       { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
+       { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
+       { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
+       { DDRC_FREQ1_INIT3(0), 0x00840000 },
+       { DDRC_FREQ1_INIT4(0), 0x00310000 },
+       { DDRC_FREQ1_INIT6(0), 0x0066004a },
+       { DDRC_FREQ1_INIT7(0), 0x0006004a },
+
+       /* Frequency 2: 100mbps */
+       { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
+       { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
+       { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
+       { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
+       { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
+       { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
+       { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
+       { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
+       { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
+       { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
+       { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
+       { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+       { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
+       { DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
+       { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
+       { DDRC_FREQ2_INIT3(0), 0x00840000 },
+       { DDRC_FREQ2_INIT4(0), 0x00310008 },
+       { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+       { DDRC_FREQ2_INIT6(0), 0x0066004a },
+       { DDRC_FREQ2_INIT7(0), 0x0006004a },
+
+       /* boot start point */
+       { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+       { 0x1005f, 0x1ff },
+       { 0x1015f, 0x1ff },
+       { 0x1105f, 0x1ff },
+       { 0x1115f, 0x1ff },
+       { 0x1205f, 0x1ff },
+       { 0x1215f, 0x1ff },
+       { 0x1305f, 0x1ff },
+       { 0x1315f, 0x1ff },
+
+       { 0x11005f, 0x1ff },
+       { 0x11015f, 0x1ff },
+       { 0x11105f, 0x1ff },
+       { 0x11115f, 0x1ff },
+       { 0x11205f, 0x1ff },
+       { 0x11215f, 0x1ff },
+       { 0x11305f, 0x1ff },
+       { 0x11315f, 0x1ff },
+
+       { 0x21005f, 0x1ff },
+       { 0x21015f, 0x1ff },
+       { 0x21105f, 0x1ff },
+       { 0x21115f, 0x1ff },
+       { 0x21205f, 0x1ff },
+       { 0x21215f, 0x1ff },
+       { 0x21305f, 0x1ff },
+       { 0x21315f, 0x1ff },
+
+       { 0x55, 0x1ff },
+       { 0x1055, 0x1ff },
+       { 0x2055, 0x1ff },
+       { 0x3055, 0x1ff },
+       { 0x4055, 0x1ff },
+       { 0x5055, 0x1ff },
+       { 0x6055, 0x1ff },
+       { 0x7055, 0x1ff },
+       { 0x8055, 0x1ff },
+       { 0x9055, 0x1ff },
+
+       { 0x200c5, 0x19 },
+       { 0x1200c5, 0x7 },
+       { 0x2200c5, 0x7 },
+
+       { 0x2002e, 0x2 },
+       { 0x12002e, 0x2 },
+       { 0x22002e, 0x2 },
+
+       { 0x90204, 0x0 },
+       { 0x190204, 0x0 },
+       { 0x290204, 0x0 },
+
+       { 0x20024, 0xab },
+       { 0x2003a, 0x0 },
+
+       { 0x120024, 0xab },
+       { 0x2003a, 0x0 },
+
+       { 0x220024, 0xab },
+       { 0x2003a, 0x0 },
+
+       { 0x20056, 0x3 },
+       { 0x120056, 0xa },
+       { 0x220056, 0xa },
+
+       { 0x1004d, 0xe00 },
+       { 0x1014d, 0xe00 },
+       { 0x1104d, 0xe00 },
+       { 0x1114d, 0xe00 },
+       { 0x1204d, 0xe00 },
+       { 0x1214d, 0xe00 },
+       { 0x1304d, 0xe00 },
+       { 0x1314d, 0xe00 },
+
+       { 0x11004d, 0xe00 },
+       { 0x11014d, 0xe00 },
+       { 0x11104d, 0xe00 },
+       { 0x11114d, 0xe00 },
+       { 0x11204d, 0xe00 },
+       { 0x11214d, 0xe00 },
+       { 0x11304d, 0xe00 },
+       { 0x11314d, 0xe00 },
+
+       { 0x21004d, 0xe00 },
+       { 0x21014d, 0xe00 },
+       { 0x21104d, 0xe00 },
+       { 0x21114d, 0xe00 },
+       { 0x21204d, 0xe00 },
+       { 0x21214d, 0xe00 },
+       { 0x21304d, 0xe00 },
+       { 0x21314d, 0xe00 },
+
+       { 0x10049, 0xfbe },
+       { 0x10149, 0xfbe },
+       { 0x11049, 0xfbe },
+       { 0x11149, 0xfbe },
+       { 0x12049, 0xfbe },
+       { 0x12149, 0xfbe },
+       { 0x13049, 0xfbe },
+       { 0x13149, 0xfbe },
+
+       { 0x110049, 0xfbe },
+       { 0x110149, 0xfbe },
+       { 0x111049, 0xfbe },
+       { 0x111149, 0xfbe },
+       { 0x112049, 0xfbe },
+       { 0x112149, 0xfbe },
+       { 0x113049, 0xfbe },
+       { 0x113149, 0xfbe },
+
+       { 0x210049, 0xfbe },
+       { 0x210149, 0xfbe },
+       { 0x211049, 0xfbe },
+       { 0x211149, 0xfbe },
+       { 0x212049, 0xfbe },
+       { 0x212149, 0xfbe },
+       { 0x213049, 0xfbe },
+       { 0x213149, 0xfbe },
+
+       { 0x43, 0x63 },
+       { 0x1043, 0x63 },
+       { 0x2043, 0x63 },
+       { 0x3043, 0x63 },
+       { 0x4043, 0x63 },
+       { 0x5043, 0x63 },
+       { 0x6043, 0x63 },
+       { 0x7043, 0x63 },
+       { 0x8043, 0x63 },
+       { 0x9043, 0x63 },
+
+       { 0x20018, 0x3 },
+       { 0x20075, 0x4 },
+       { 0x20050, 0x0 },
+       { 0x20008, 0x2ee },
+       { 0x120008, 0x64 },
+       { 0x220008, 0x19 },
+       { 0x20088, 0x9 },
+
+       { 0x200b2, 0x1d4 },
+       { 0x10043, 0x5a1 },
+       { 0x10143, 0x5a1 },
+       { 0x11043, 0x5a1 },
+       { 0x11143, 0x5a1 },
+       { 0x12043, 0x5a1 },
+       { 0x12143, 0x5a1 },
+       { 0x13043, 0x5a1 },
+       { 0x13143, 0x5a1 },
+
+       { 0x1200b2, 0xdc },
+       { 0x110043, 0x5a1 },
+       { 0x110143, 0x5a1 },
+       { 0x111043, 0x5a1 },
+       { 0x111143, 0x5a1 },
+       { 0x112043, 0x5a1 },
+       { 0x112143, 0x5a1 },
+       { 0x113043, 0x5a1 },
+       { 0x113143, 0x5a1 },
+
+       { 0x2200b2, 0xdc },
+       { 0x210043, 0x5a1 },
+       { 0x210143, 0x5a1 },
+       { 0x211043, 0x5a1 },
+       { 0x211143, 0x5a1 },
+       { 0x212043, 0x5a1 },
+       { 0x212143, 0x5a1 },
+       { 0x213043, 0x5a1 },
+       { 0x213143, 0x5a1 },
+
+       { 0x200fa, 0x1 },
+       { 0x1200fa, 0x1 },
+       { 0x2200fa, 0x1 },
+
+       { 0x20019, 0x1 },
+       { 0x120019, 0x1 },
+       { 0x220019, 0x1 },
+
+       { 0x200f0, 0x660 },
+       { 0x200f1, 0x0 },
+       { 0x200f2, 0x4444 },
+       { 0x200f3, 0x8888 },
+       { 0x200f4, 0x5665 },
+       { 0x200f5, 0x0 },
+       { 0x200f6, 0x0 },
+       { 0x200f7, 0xf000 },
+
+       { 0x20025, 0x0 },
+       { 0x2002d, LPDDR4_PHY_DMIPinPresent },
+       { 0x12002d, LPDDR4_PHY_DMIPinPresent },
+       { 0x22002d, LPDDR4_PHY_DMIPinPresent },
+       { 0x200c7, 0x21 },
+       { 0x200ca, 0x24 },
+       { 0x1200c7, 0x21 },
+       { 0x1200ca, 0x24 },
+       { 0x2200c7, 0x21 },
+       { 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+       { 0x200b2, 0x0 },
+       { 0x1200b2, 0x0 },
+       { 0x2200b2, 0x0 },
+       { 0x200cb, 0x0 },
+       { 0x10043, 0x0 },
+       { 0x110043, 0x0 },
+       { 0x210043, 0x0 },
+       { 0x10143, 0x0 },
+       { 0x110143, 0x0 },
+       { 0x210143, 0x0 },
+       { 0x11043, 0x0 },
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+       { 0x113c1, 0x0 },
+       { 0x1113c1, 0x0 },
+       { 0x2113c1, 0x0 },
+       { 0x114c1, 0x0 },
+       { 0x1114c1, 0x0 },
+       { 0x2114c1, 0x0 },
+       { 0x115c1, 0x0 },
+       { 0x1115c1, 0x0 },
+       { 0x2115c1, 0x0 },
+       { 0x116c1, 0x0 },
+       { 0x1116c1, 0x0 },
+       { 0x2116c1, 0x0 },
+       { 0x117c1, 0x0 },
+       { 0x1117c1, 0x0 },
+       { 0x2117c1, 0x0 },
+       { 0x118c1, 0x0 },
+       { 0x1118c1, 0x0 },
+       { 0x2118c1, 0x0 },
+       { 0x120c1, 0x0 },
+       { 0x1120c1, 0x0 },
+       { 0x2120c1, 0x0 },
+       { 0x121c1, 0x0 },
+       { 0x1121c1, 0x0 },
+       { 0x2121c1, 0x0 },
+       { 0x122c1, 0x0 },
+       { 0x1122c1, 0x0 },
+       { 0x2122c1, 0x0 },
+       { 0x123c1, 0x0 },
+       { 0x1123c1, 0x0 },
+       { 0x2123c1, 0x0 },
+       { 0x124c1, 0x0 },
+       { 0x1124c1, 0x0 },
+       { 0x2124c1, 0x0 },
+       { 0x125c1, 0x0 },
+       { 0x1125c1, 0x0 },
+       { 0x2125c1, 0x0 },
+       { 0x126c1, 0x0 },
+       { 0x1126c1, 0x0 },
+       { 0x2126c1, 0x0 },
+       { 0x127c1, 0x0 },
+       { 0x1127c1, 0x0 },
+       { 0x2127c1, 0x0 },
+       { 0x128c1, 0x0 },
+       { 0x1128c1, 0x0 },
+       { 0x2128c1, 0x0 },
+       { 0x130c1, 0x0 },
+       { 0x1130c1, 0x0 },
+       { 0x2130c1, 0x0 },
+       { 0x131c1, 0x0 },
+       { 0x1131c1, 0x0 },
+       { 0x2131c1, 0x0 },
+       { 0x132c1, 0x0 },
+       { 0x1132c1, 0x0 },
+       { 0x2132c1, 0x0 },
+       { 0x133c1, 0x0 },
+       { 0x1133c1, 0x0 },
+       { 0x2133c1, 0x0 },
+       { 0x134c1, 0x0 },
+       { 0x1134c1, 0x0 },
+       { 0x2134c1, 0x0 },
+       { 0x135c1, 0x0 },
+       { 0x1135c1, 0x0 },
+       { 0x2135c1, 0x0 },
+       { 0x136c1, 0x0 },
+       { 0x1136c1, 0x0 },
+       { 0x2136c1, 0x0 },
+       { 0x137c1, 0x0 },
+       { 0x1137c1, 0x0 },
+       { 0x2137c1, 0x0 },
+       { 0x138c1, 0x0 },
+       { 0x1138c1, 0x0 },
+       { 0x2138c1, 0x0 },
+       { 0x10020, 0x0 },
+       { 0x110020, 0x0 },
+       { 0x210020, 0x0 },
+       { 0x11020, 0x0 },
+       { 0x111020, 0x0 },
+       { 0x211020, 0x0 },
+       { 0x12020, 0x0 },
+       { 0x112020, 0x0 },
+       { 0x212020, 0x0 },
+       { 0x13020, 0x0 },
+       { 0x113020, 0x0 },
+       { 0x213020, 0x0 },
+       { 0x20072, 0x0 },
+       { 0x20073, 0x0 },
+       { 0x20074, 0x0 },
+       { 0x100aa, 0x0 },
+       { 0x110aa, 0x0 },
+       { 0x120aa, 0x0 },
+       { 0x130aa, 0x0 },
+       { 0x20010, 0x0 },
+       { 0x120010, 0x0 },
+       { 0x220010, 0x0 },
+       { 0x20011, 0x0 },
+       { 0x120011, 0x0 },
+       { 0x220011, 0x0 },
+       { 0x100ae, 0x0 },
+       { 0x1100ae, 0x0 },
+       { 0x2100ae, 0x0 },
+       { 0x100af, 0x0 },
+       { 0x1100af, 0x0 },
+       { 0x2100af, 0x0 },
+       { 0x110ae, 0x0 },
+       { 0x1110ae, 0x0 },
+       { 0x2110ae, 0x0 },
+       { 0x110af, 0x0 },
+       { 0x1110af, 0x0 },
+       { 0x2110af, 0x0 },
+       { 0x120ae, 0x0 },
+       { 0x1120ae, 0x0 },
+       { 0x2120ae, 0x0 },
+       { 0x120af, 0x0 },
+       { 0x1120af, 0x0 },
+       { 0x2120af, 0x0 },
+       { 0x130ae, 0x0 },
+       { 0x1130ae, 0x0 },
+       { 0x2130ae, 0x0 },
+       { 0x130af, 0x0 },
+       { 0x1130af, 0x0 },
+       { 0x2130af, 0x0 },
+       { 0x20020, 0x0 },
+       { 0x120020, 0x0 },
+       { 0x220020, 0x0 },
+       { 0x100a0, 0x0 },
+       { 0x100a1, 0x0 },
+       { 0x100a2, 0x0 },
+       { 0x100a3, 0x0 },
+       { 0x100a4, 0x0 },
+       { 0x100a5, 0x0 },
+       { 0x100a6, 0x0 },
+       { 0x100a7, 0x0 },
+       { 0x110a0, 0x0 },
+       { 0x110a1, 0x0 },
+       { 0x110a2, 0x0 },
+       { 0x110a3, 0x0 },
+       { 0x110a4, 0x0 },
+       { 0x110a5, 0x0 },
+       { 0x110a6, 0x0 },
+       { 0x110a7, 0x0 },
+       { 0x120a0, 0x0 },
+       { 0x120a1, 0x0 },
+       { 0x120a2, 0x0 },
+       { 0x120a3, 0x0 },
+       { 0x120a4, 0x0 },
+       { 0x120a5, 0x0 },
+       { 0x120a6, 0x0 },
+       { 0x120a7, 0x0 },
+       { 0x130a0, 0x0 },
+       { 0x130a1, 0x0 },
+       { 0x130a2, 0x0 },
+       { 0x130a3, 0x0 },
+       { 0x130a4, 0x0 },
+       { 0x130a5, 0x0 },
+       { 0x130a6, 0x0 },
+       { 0x130a7, 0x0 },
+       { 0x2007c, 0x0 },
+       { 0x12007c, 0x0 },
+       { 0x22007c, 0x0 },
+       { 0x2007d, 0x0 },
+       { 0x12007d, 0x0 },
+       { 0x22007d, 0x0 },
+       { 0x400fd, 0x0 },
+       { 0x400c0, 0x0 },
+       { 0x90201, 0x0 },
+       { 0x190201, 0x0 },
+       { 0x290201, 0x0 },
+       { 0x90202, 0x0 },
+       { 0x190202, 0x0 },
+       { 0x290202, 0x0 },
+       { 0x90203, 0x0 },
+       { 0x190203, 0x0 },
+       { 0x290203, 0x0 },
+       { 0x90204, 0x0 },
+       { 0x190204, 0x0 },
+       { 0x290204, 0x0 },
+       { 0x90205, 0x0 },
+       { 0x190205, 0x0 },
+       { 0x290205, 0x0 },
+       { 0x90206, 0x0 },
+       { 0x190206, 0x0 },
+       { 0x290206, 0x0 },
+       { 0x90207, 0x0 },
+       { 0x190207, 0x0 },
+       { 0x290207, 0x0 },
+       { 0x90208, 0x0 },
+       { 0x190208, 0x0 },
+       { 0x290208, 0x0 },
+       { 0x10062, 0x0 },
+       { 0x10162, 0x0 },
+       { 0x10262, 0x0 },
+       { 0x10362, 0x0 },
+       { 0x10462, 0x0 },
+       { 0x10562, 0x0 },
+       { 0x10662, 0x0 },
+       { 0x10762, 0x0 },
+       { 0x10862, 0x0 },
+       { 0x11062, 0x0 },
+       { 0x11162, 0x0 },
+       { 0x11262, 0x0 },
+       { 0x11362, 0x0 },
+       { 0x11462, 0x0 },
+       { 0x11562, 0x0 },
+       { 0x11662, 0x0 },
+       { 0x11762, 0x0 },
+       { 0x11862, 0x0 },
+       { 0x12062, 0x0 },
+       { 0x12162, 0x0 },
+       { 0x12262, 0x0 },
+       { 0x12362, 0x0 },
+       { 0x12462, 0x0 },
+       { 0x12562, 0x0 },
+       { 0x12662, 0x0 },
+       { 0x12762, 0x0 },
+       { 0x12862, 0x0 },
+       { 0x13062, 0x0 },
+       { 0x13162, 0x0 },
+       { 0x13262, 0x0 },
+       { 0x13362, 0x0 },
+       { 0x13462, 0x0 },
+       { 0x13562, 0x0 },
+       { 0x13662, 0x0 },
+       { 0x13762, 0x0 },
+       { 0x13862, 0x0 },
+       { 0x20077, 0x0 },
+       { 0x10001, 0x0 },
+       { 0x11001, 0x0 },
+       { 0x12001, 0x0 },
+       { 0x13001, 0x0 },
+       { 0x10040, 0x0 },
+       { 0x10140, 0x0 },
+       { 0x10240, 0x0 },
+       { 0x10340, 0x0 },
+       { 0x10440, 0x0 },
+       { 0x10540, 0x0 },
+       { 0x10640, 0x0 },
+       { 0x10740, 0x0 },
+       { 0x10840, 0x0 },
+       { 0x10030, 0x0 },
+       { 0x10130, 0x0 },
+       { 0x10230, 0x0 },
+       { 0x10330, 0x0 },
+       { 0x10430, 0x0 },
+       { 0x10530, 0x0 },
+       { 0x10630, 0x0 },
+       { 0x10730, 0x0 },
+       { 0x10830, 0x0 },
+       { 0x11040, 0x0 },
+       { 0x11140, 0x0 },
+       { 0x11240, 0x0 },
+       { 0x11340, 0x0 },
+       { 0x11440, 0x0 },
+       { 0x11540, 0x0 },
+       { 0x11640, 0x0 },
+       { 0x11740, 0x0 },
+       { 0x11840, 0x0 },
+       { 0x11030, 0x0 },
+       { 0x11130, 0x0 },
+       { 0x11230, 0x0 },
+       { 0x11330, 0x0 },
+       { 0x11430, 0x0 },
+       { 0x11530, 0x0 },
+       { 0x11630, 0x0 },
+       { 0x11730, 0x0 },
+       { 0x11830, 0x0 },
+       { 0x12040, 0x0 },
+       { 0x12140, 0x0 },
+       { 0x12240, 0x0 },
+       { 0x12340, 0x0 },
+       { 0x12440, 0x0 },
+       { 0x12540, 0x0 },
+       { 0x12640, 0x0 },
+       { 0x12740, 0x0 },
+       { 0x12840, 0x0 },
+       { 0x12030, 0x0 },
+       { 0x12130, 0x0 },
+       { 0x12230, 0x0 },
+       { 0x12330, 0x0 },
+       { 0x12430, 0x0 },
+       { 0x12530, 0x0 },
+       { 0x12630, 0x0 },
+       { 0x12730, 0x0 },
+       { 0x12830, 0x0 },
+       { 0x13040, 0x0 },
+       { 0x13140, 0x0 },
+       { 0x13240, 0x0 },
+       { 0x13340, 0x0 },
+       { 0x13440, 0x0 },
+       { 0x13540, 0x0 },
+       { 0x13640, 0x0 },
+       { 0x13740, 0x0 },
+       { 0x13840, 0x0 },
+       { 0x13030, 0x0 },
+       { 0x13130, 0x0 },
+       { 0x13230, 0x0 },
+       { 0x13330, 0x0 },
+       { 0x13430, 0x0 },
+       { 0x13530, 0x0 },
+       { 0x13630, 0x0 },
+       { 0x13730, 0x0 },
+       { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54000, 0x0 },
+       { 0x54001, 0x0 },
+       { 0x54002, 0x0 },
+       { 0x54003, 0xbb8 },
+       { 0x54004, 0x2 },
+       { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+       { 0x54006, LPDDR4_PHY_VREF_VALUE },
+       { 0x54007, 0x0 },
+       { 0x54008, 0x131f },
+       { 0x54009, 0xc8 },
+       { 0x5400a, 0x0 },
+       { 0x5400b, 0x2 },
+       { 0x5400c, 0x0 },
+       { 0x5400d, 0x0 },
+       { 0x5400e, 0x0 },
+       { 0x5400f, 0x0 },
+       { 0x54010, 0x0 },
+       { 0x54011, 0x0 },
+       { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+       { 0x54013, 0x0 },
+       { 0x54014, 0x0 },
+       { 0x54015, 0x0 },
+       { 0x54016, 0x0 },
+       { 0x54017, 0x0 },
+       { 0x54018, 0x0 },
+       { 0x54019, 0x2dd4 },
+       { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+       { 0x5401b, 0x4d66 },
+       { 0x5401c, 0x4d08 },
+       { 0x5401d, 0x0 },
+       { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+       { 0x5401f, 0x2dd4 },
+       { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+       { 0x54021, 0x4d66 },
+       { 0x54022, 0x4d08 },
+       { 0x54023, 0x0 },
+       { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+       { 0x54025, 0x0 },
+       { 0x54026, 0x0 },
+       { 0x54027, 0x0 },
+       { 0x54028, 0x0 },
+       { 0x54029, 0x0 },
+       { 0x5402a, 0x0 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, LPDDR4_CS },
+       { 0x5402d, 0x0 },
+       { 0x5402e, 0x0 },
+       { 0x5402f, 0x0 },
+       { 0x54030, 0x0 },
+       { 0x54031, 0x0 },
+       { 0x54032, 0xd400 },
+       { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x84d },
+       { 0x54036, 0x4d },
+       { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+       { 0x54038, 0xd400 },
+       { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x84d },
+       { 0x5403c, 0x4d },
+       { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+       { 0x5403e, 0x0 },
+       { 0x5403f, 0x0 },
+       { 0x54040, 0x0 },
+       { 0x54041, 0x0 },
+       { 0x54042, 0x0 },
+       { 0x54043, 0x0 },
+       { 0x54044, 0x0 },
+       { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54000, 0x0 },
+       { 0x54001, 0x0 },
+       { 0x54002, 0x101 },
+       { 0x54003, 0x190 },
+       { 0x54004, 0x2 },
+       { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */
+       { 0x54006, LPDDR4_PHY_VREF_VALUE },
+       { 0x54007, 0x0 },
+       { 0x54008, 0x121f },
+       { 0x54009, 0xc8 },
+       { 0x5400a, 0x0 },
+       { 0x5400b, 0x2 },
+       { 0x5400c, 0x0 },
+       { 0x5400d, 0x0 },
+       { 0x5400e, 0x0 },
+       { 0x5400f, 0x0 },
+       { 0x54010, 0x0 },
+       { 0x54011, 0x0 },
+       { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+       { 0x54013, 0x0 },
+       { 0x54014, 0x0 },
+       { 0x54015, 0x0 },
+       { 0x54016, 0x0 },
+       { 0x54017, 0x0 },
+       { 0x54018, 0x0 },
+       { 0x54019, 0x84 },
+       { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+       { 0x5401b, 0x4d66 },
+       { 0x5401c, 0x4d08 },
+       { 0x5401d, 0x0 },
+       { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+       { 0x5401f, 0x84 },
+       { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+       { 0x54021, 0x4d66 },
+       { 0x54022, 0x4d08 },
+       { 0x54023, 0x0 },
+       { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+       { 0x54025, 0x0 },
+       { 0x54026, 0x0 },
+       { 0x54027, 0x0 },
+       { 0x54028, 0x0 },
+       { 0x54029, 0x0 },
+       { 0x5402a, 0x0 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, LPDDR4_CS },
+       { 0x5402d, 0x0 },
+       { 0x5402e, 0x0 },
+       { 0x5402f, 0x0 },
+       { 0x54030, 0x0 },
+       { 0x54031, 0x0 },
+       { 0x54032, 0x8400 },
+       { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x84d },
+       { 0x54036, 0x4d },
+       { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+       { 0x54038, 0x8400 },
+       { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x84d },
+       { 0x5403c, 0x4d },
+       { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+       { 0x5403e, 0x0 },
+       { 0x5403f, 0x0 },
+       { 0x54040, 0x0 },
+       { 0x54041, 0x0 },
+       { 0x54042, 0x0 },
+       { 0x54043, 0x0 },
+       { 0x54044, 0x0 },
+       { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54000, 0x0 },
+       { 0x54001, 0x0 },
+       { 0x54002, 0x102 },
+       { 0x54003, 0x64 },
+       { 0x54004, 0x2 },
+       { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+       { 0x54006, LPDDR4_PHY_VREF_VALUE },
+       { 0x54007, 0x0 },
+       { 0x54008, 0x121f },
+       { 0x54009, 0xc8 },
+       { 0x5400a, 0x0 },
+       { 0x5400b, 0x2 },
+       { 0x5400c, 0x0 },
+       { 0x5400d, 0x0 },
+       { 0x5400e, 0x0 },
+       { 0x5400f, 0x0 },
+       { 0x54010, 0x0 },
+       { 0x54011, 0x0 },
+       { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+       { 0x54013, 0x0 },
+       { 0x54014, 0x0 },
+       { 0x54015, 0x0 },
+       { 0x54016, 0x0 },
+       { 0x54017, 0x0 },
+       { 0x54018, 0x0 },
+       { 0x54019, 0x84 },
+       { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+       { 0x5401b, 0x4d66 },
+       { 0x5401c, 0x4d08 },
+       { 0x5401d, 0x0 },
+       { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+       { 0x5401f, 0x84 },
+       { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+       { 0x54021, 0x4d66 },
+       { 0x54022, 0x4d08 },
+       { 0x54023, 0x0 },
+       { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+       { 0x54025, 0x0 },
+       { 0x54026, 0x0 },
+       { 0x54027, 0x0 },
+       { 0x54028, 0x0 },
+       { 0x54029, 0x0 },
+       { 0x5402a, 0x0 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, LPDDR4_CS },
+       { 0x5402d, 0x0 },
+       { 0x5402e, 0x0 },
+       { 0x5402f, 0x0 },
+       { 0x54030, 0x0 },
+       { 0x54031, 0x0 },
+       { 0x54032, 0x8400 },
+       { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x84d },
+       { 0x54036, 0x4d },
+       { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+       { 0x54038, 0x8400 },
+       { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x84d },
+       { 0x5403c, 0x4d },
+       { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+       { 0x5403e, 0x0 },
+       { 0x5403f, 0x0 },
+       { 0x54040, 0x0 },
+       { 0x54041, 0x0 },
+       { 0x54042, 0x0 },
+       { 0x54043, 0x0 },
+       { 0x54044, 0x0 },
+       { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+       { 0xd0000, 0x0 },
+       { 0x54000, 0x0 },
+       { 0x54001, 0x0 },
+       { 0x54002, 0x0 },
+       { 0x54003, 0xbb8 },
+       { 0x54004, 0x2 },
+       { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+       { 0x54006, LPDDR4_PHY_VREF_VALUE },
+       { 0x54007, 0x0 },
+       { 0x54008, 0x61 },
+       { 0x54009, 0xc8 },
+       { 0x5400a, 0x0 },
+       { 0x5400b, 0x2 },
+       { 0x5400c, 0x0 },
+       { 0x5400d, 0x0 },
+       { 0x5400e, 0x0 },
+       { 0x5400f, 0x100 },
+       { 0x54010, 0x1f7f },
+       { 0x54011, 0x0 },
+       { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+       { 0x54013, 0x0 },
+       { 0x54014, 0x0 },
+       { 0x54015, 0x0 },
+       { 0x54016, 0x0 },
+       { 0x54017, 0x0 },
+       { 0x54018, 0x0 },
+       { 0x54019, 0x2dd4 },
+       { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+       { 0x5401b, 0x4d66 },
+       { 0x5401c, 0x4d08 },
+       { 0x5401d, 0x0 },
+       { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+       { 0x5401f, 0x2dd4 },
+       { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+       { 0x54021, 0x4d66 },
+       { 0x54022, 0x4d08 },
+       { 0x54023, 0x0 },
+       { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+       { 0x54025, 0x0 },
+       { 0x54026, 0x0 },
+       { 0x54027, 0x0 },
+       { 0x54028, 0x0 },
+       { 0x54029, 0x0 },
+       { 0x5402a, 0x0 },
+       { 0x5402b, 0x1000 },
+       { 0x5402c, LPDDR4_CS },
+       { 0x5402d, 0x0 },
+       { 0x5402e, 0x0 },
+       { 0x5402f, 0x0 },
+       { 0x54030, 0x0 },
+       { 0x54031, 0x0 },
+       { 0x54032, 0xd400 },
+       { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+       { 0x54034, 0x6600 },
+       { 0x54035, 0x84d },
+       { 0x54036, 0x4d },
+       { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+       { 0x54038, 0xd400 },
+       { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+       { 0x5403a, 0x6600 },
+       { 0x5403b, 0x84d },
+       { 0x5403c, 0x4d },
+       { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+       { 0x5403e, 0x0 },
+       { 0x5403f, 0x0 },
+       { 0x54040, 0x0 },
+       { 0x54041, 0x0 },
+       { 0x54042, 0x0 },
+       { 0x54043, 0x0 },
+       { 0x54044, 0x0 },
+       { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+       { 0xd0000, 0x0 },
+       { 0x90000, 0x10 },
+       { 0x90001, 0x400 },
+       { 0x90002, 0x10e },
+       { 0x90003, 0x0 },
+       { 0x90004, 0x0 },
+       { 0x90005, 0x8 },
+       { 0x90029, 0xb },
+       { 0x9002a, 0x480 },
+       { 0x9002b, 0x109 },
+       { 0x9002c, 0x8 },
+       { 0x9002d, 0x448 },
+       { 0x9002e, 0x139 },
+       { 0x9002f, 0x8 },
+       { 0x90030, 0x478 },
+       { 0x90031, 0x109 },
+       { 0x90032, 0x0 },
+       { 0x90033, 0xe8 },
+       { 0x90034, 0x109 },
+       { 0x90035, 0x2 },
+       { 0x90036, 0x10 },
+       { 0x90037, 0x139 },
+       { 0x90038, 0xf },
+       { 0x90039, 0x7c0 },
+       { 0x9003a, 0x139 },
+       { 0x9003b, 0x44 },
+       { 0x9003c, 0x630 },
+       { 0x9003d, 0x159 },
+       { 0x9003e, 0x14f },
+       { 0x9003f, 0x630 },
+       { 0x90040, 0x159 },
+       { 0x90041, 0x47 },
+       { 0x90042, 0x630 },
+       { 0x90043, 0x149 },
+       { 0x90044, 0x4f },
+       { 0x90045, 0x630 },
+       { 0x90046, 0x179 },
+       { 0x90047, 0x8 },
+       { 0x90048, 0xe0 },
+       { 0x90049, 0x109 },
+       { 0x9004a, 0x0 },
+       { 0x9004b, 0x7c8 },
+       { 0x9004c, 0x109 },
+       { 0x9004d, 0x0 },
+       { 0x9004e, 0x1 },
+       { 0x9004f, 0x8 },
+       { 0x90050, 0x0 },
+       { 0x90051, 0x45a },
+       { 0x90052, 0x9 },
+       { 0x90053, 0x0 },
+       { 0x90054, 0x448 },
+       { 0x90055, 0x109 },
+       { 0x90056, 0x40 },
+       { 0x90057, 0x630 },
+       { 0x90058, 0x179 },
+       { 0x90059, 0x1 },
+       { 0x9005a, 0x618 },
+       { 0x9005b, 0x109 },
+       { 0x9005c, 0x40c0 },
+       { 0x9005d, 0x630 },
+       { 0x9005e, 0x149 },
+       { 0x9005f, 0x8 },
+       { 0x90060, 0x4 },
+       { 0x90061, 0x48 },
+       { 0x90062, 0x4040 },
+       { 0x90063, 0x630 },
+       { 0x90064, 0x149 },
+       { 0x90065, 0x0 },
+       { 0x90066, 0x4 },
+       { 0x90067, 0x48 },
+       { 0x90068, 0x40 },
+       { 0x90069, 0x630 },
+       { 0x9006a, 0x149 },
+       { 0x9006b, 0x10 },
+       { 0x9006c, 0x4 },
+       { 0x9006d, 0x18 },
+       { 0x9006e, 0x0 },
+       { 0x9006f, 0x4 },
+       { 0x90070, 0x78 },
+       { 0x90071, 0x549 },
+       { 0x90072, 0x630 },
+       { 0x90073, 0x159 },
+       { 0x90074, 0xd49 },
+       { 0x90075, 0x630 },
+       { 0x90076, 0x159 },
+       { 0x90077, 0x94a },
+       { 0x90078, 0x630 },
+       { 0x90079, 0x159 },
+       { 0x9007a, 0x441 },
+       { 0x9007b, 0x630 },
+       { 0x9007c, 0x149 },
+       { 0x9007d, 0x42 },
+       { 0x9007e, 0x630 },
+       { 0x9007f, 0x149 },
+       { 0x90080, 0x1 },
+       { 0x90081, 0x630 },
+       { 0x90082, 0x149 },
+       { 0x90083, 0x0 },
+       { 0x90084, 0xe0 },
+       { 0x90085, 0x109 },
+       { 0x90086, 0xa },
+       { 0x90087, 0x10 },
+       { 0x90088, 0x109 },
+       { 0x90089, 0x9 },
+       { 0x9008a, 0x3c0 },
+       { 0x9008b, 0x149 },
+       { 0x9008c, 0x9 },
+       { 0x9008d, 0x3c0 },
+       { 0x9008e, 0x159 },
+       { 0x9008f, 0x18 },
+       { 0x90090, 0x10 },
+       { 0x90091, 0x109 },
+       { 0x90092, 0x0 },
+       { 0x90093, 0x3c0 },
+       { 0x90094, 0x109 },
+       { 0x90095, 0x18 },
+       { 0x90096, 0x4 },
+       { 0x90097, 0x48 },
+       { 0x90098, 0x18 },
+       { 0x90099, 0x4 },
+       { 0x9009a, 0x58 },
+       { 0x9009b, 0xa },
+       { 0x9009c, 0x10 },
+       { 0x9009d, 0x109 },
+       { 0x9009e, 0x2 },
+       { 0x9009f, 0x10 },
+       { 0x900a0, 0x109 },
+       { 0x900a1, 0x5 },
+       { 0x900a2, 0x7c0 },
+       { 0x900a3, 0x109 },
+       { 0x900a4, 0x10 },
+       { 0x900a5, 0x10 },
+       { 0x900a6, 0x109 },
+       { 0x40000, 0x811 },
+       { 0x40020, 0x880 },
+       { 0x40040, 0x0 },
+       { 0x40060, 0x0 },
+       { 0x40001, 0x4008 },
+       { 0x40021, 0x83 },
+       { 0x40041, 0x4f },
+       { 0x40061, 0x0 },
+       { 0x40002, 0x4040 },
+       { 0x40022, 0x83 },
+       { 0x40042, 0x51 },
+       { 0x40062, 0x0 },
+       { 0x40003, 0x811 },
+       { 0x40023, 0x880 },
+       { 0x40043, 0x0 },
+       { 0x40063, 0x0 },
+       { 0x40004, 0x720 },
+       { 0x40024, 0xf },
+       { 0x40044, 0x1740 },
+       { 0x40064, 0x0 },
+       { 0x40005, 0x16 },
+       { 0x40025, 0x83 },
+       { 0x40045, 0x4b },
+       { 0x40065, 0x0 },
+       { 0x40006, 0x716 },
+       { 0x40026, 0xf },
+       { 0x40046, 0x2001 },
+       { 0x40066, 0x0 },
+       { 0x40007, 0x716 },
+       { 0x40027, 0xf },
+       { 0x40047, 0x2800 },
+       { 0x40067, 0x0 },
+       { 0x40008, 0x716 },
+       { 0x40028, 0xf },
+       { 0x40048, 0xf00 },
+       { 0x40068, 0x0 },
+       { 0x40009, 0x720 },
+       { 0x40029, 0xf },
+       { 0x40049, 0x1400 },
+       { 0x40069, 0x0 },
+       { 0x4000a, 0xe08 },
+       { 0x4002a, 0xc15 },
+       { 0x4004a, 0x0 },
+       { 0x4006a, 0x0 },
+       { 0x4000b, 0x623 },
+       { 0x4002b, 0x15 },
+       { 0x4004b, 0x0 },
+       { 0x4006b, 0x0 },
+       { 0x4000c, 0x4028 },
+       { 0x4002c, 0x80 },
+       { 0x4004c, 0x0 },
+       { 0x4006c, 0x0 },
+       { 0x4000d, 0xe08 },
+       { 0x4002d, 0xc1a },
+       { 0x4004d, 0x0 },
+       { 0x4006d, 0x0 },
+       { 0x4000e, 0x623 },
+       { 0x4002e, 0x1a },
+       { 0x4004e, 0x0 },
+       { 0x4006e, 0x0 },
+       { 0x4000f, 0x4040 },
+       { 0x4002f, 0x80 },
+       { 0x4004f, 0x0 },
+       { 0x4006f, 0x0 },
+       { 0x40010, 0x2604 },
+       { 0x40030, 0x15 },
+       { 0x40050, 0x0 },
+       { 0x40070, 0x0 },
+       { 0x40011, 0x708 },
+       { 0x40031, 0x5 },
+       { 0x40051, 0x0 },
+       { 0x40071, 0x2002 },
+       { 0x40012, 0x8 },
+       { 0x40032, 0x80 },
+       { 0x40052, 0x0 },
+       { 0x40072, 0x0 },
+       { 0x40013, 0x2604 },
+       { 0x40033, 0x1a },
+       { 0x40053, 0x0 },
+       { 0x40073, 0x0 },
+       { 0x40014, 0x708 },
+       { 0x40034, 0xa },
+       { 0x40054, 0x0 },
+       { 0x40074, 0x2002 },
+       { 0x40015, 0x4040 },
+       { 0x40035, 0x80 },
+       { 0x40055, 0x0 },
+       { 0x40075, 0x0 },
+       { 0x40016, 0x60a },
+       { 0x40036, 0x15 },
+       { 0x40056, 0x1200 },
+       { 0x40076, 0x0 },
+       { 0x40017, 0x61a },
+       { 0x40037, 0x15 },
+       { 0x40057, 0x1300 },
+       { 0x40077, 0x0 },
+       { 0x40018, 0x60a },
+       { 0x40038, 0x1a },
+       { 0x40058, 0x1200 },
+       { 0x40078, 0x0 },
+       { 0x40019, 0x642 },
+       { 0x40039, 0x1a },
+       { 0x40059, 0x1300 },
+       { 0x40079, 0x0 },
+       { 0x4001a, 0x4808 },
+       { 0x4003a, 0x880 },
+       { 0x4005a, 0x0 },
+       { 0x4007a, 0x0 },
+       { 0x900a7, 0x0 },
+       { 0x900a8, 0x790 },
+       { 0x900a9, 0x11a },
+       { 0x900aa, 0x8 },
+       { 0x900ab, 0x7aa },
+       { 0x900ac, 0x2a },
+       { 0x900ad, 0x10 },
+       { 0x900ae, 0x7b2 },
+       { 0x900af, 0x2a },
+       { 0x900b0, 0x0 },
+       { 0x900b1, 0x7c8 },
+       { 0x900b2, 0x109 },
+       { 0x900b3, 0x10 },
+       { 0x900b4, 0x2a8 },
+       { 0x900b5, 0x129 },
+       { 0x900b6, 0x8 },
+       { 0x900b7, 0x370 },
+       { 0x900b8, 0x129 },
+       { 0x900b9, 0xa },
+       { 0x900ba, 0x3c8 },
+       { 0x900bb, 0x1a9 },
+       { 0x900bc, 0xc },
+       { 0x900bd, 0x408 },
+       { 0x900be, 0x199 },
+       { 0x900bf, 0x14 },
+       { 0x900c0, 0x790 },
+       { 0x900c1, 0x11a },
+       { 0x900c2, 0x8 },
+       { 0x900c3, 0x4 },
+       { 0x900c4, 0x18 },
+       { 0x900c5, 0xe },
+       { 0x900c6, 0x408 },
+       { 0x900c7, 0x199 },
+       { 0x900c8, 0x8 },
+       { 0x900c9, 0x8568 },
+       { 0x900ca, 0x108 },
+       { 0x900cb, 0x18 },
+       { 0x900cc, 0x790 },
+       { 0x900cd, 0x16a },
+       { 0x900ce, 0x8 },
+       { 0x900cf, 0x1d8 },
+       { 0x900d0, 0x169 },
+       { 0x900d1, 0x10 },
+       { 0x900d2, 0x8558 },
+       { 0x900d3, 0x168 },
+       { 0x900d4, 0x70 },
+       { 0x900d5, 0x788 },
+       { 0x900d6, 0x16a },
+       { 0x900d7, 0x1ff8 },
+       { 0x900d8, 0x85a8 },
+       { 0x900d9, 0x1e8 },
+       { 0x900da, 0x50 },
+       { 0x900db, 0x798 },
+       { 0x900dc, 0x16a },
+       { 0x900dd, 0x60 },
+       { 0x900de, 0x7a0 },
+       { 0x900df, 0x16a },
+       { 0x900e0, 0x8 },
+       { 0x900e1, 0x8310 },
+       { 0x900e2, 0x168 },
+       { 0x900e3, 0x8 },
+       { 0x900e4, 0xa310 },
+       { 0x900e5, 0x168 },
+       { 0x900e6, 0xa },
+       { 0x900e7, 0x408 },
+       { 0x900e8, 0x169 },
+       { 0x900e9, 0x6e },
+       { 0x900ea, 0x0 },
+       { 0x900eb, 0x68 },
+       { 0x900ec, 0x0 },
+       { 0x900ed, 0x408 },
+       { 0x900ee, 0x169 },
+       { 0x900ef, 0x0 },
+       { 0x900f0, 0x8310 },
+       { 0x900f1, 0x168 },
+       { 0x900f2, 0x0 },
+       { 0x900f3, 0xa310 },
+       { 0x900f4, 0x168 },
+       { 0x900f5, 0x1ff8 },
+       { 0x900f6, 0x85a8 },
+       { 0x900f7, 0x1e8 },
+       { 0x900f8, 0x68 },
+       { 0x900f9, 0x798 },
+       { 0x900fa, 0x16a },
+       { 0x900fb, 0x78 },
+       { 0x900fc, 0x7a0 },
+       { 0x900fd, 0x16a },
+       { 0x900fe, 0x68 },
+       { 0x900ff, 0x790 },
+       { 0x90100, 0x16a },
+       { 0x90101, 0x8 },
+       { 0x90102, 0x8b10 },
+       { 0x90103, 0x168 },
+       { 0x90104, 0x8 },
+       { 0x90105, 0xab10 },
+       { 0x90106, 0x168 },
+       { 0x90107, 0xa },
+       { 0x90108, 0x408 },
+       { 0x90109, 0x169 },
+       { 0x9010a, 0x58 },
+       { 0x9010b, 0x0 },
+       { 0x9010c, 0x68 },
+       { 0x9010d, 0x0 },
+       { 0x9010e, 0x408 },
+       { 0x9010f, 0x169 },
+       { 0x90110, 0x0 },
+       { 0x90111, 0x8b10 },
+       { 0x90112, 0x168 },
+       { 0x90113, 0x0 },
+       { 0x90114, 0xab10 },
+       { 0x90115, 0x168 },
+       { 0x90116, 0x0 },
+       { 0x90117, 0x1d8 },
+       { 0x90118, 0x169 },
+       { 0x90119, 0x80 },
+       { 0x9011a, 0x790 },
+       { 0x9011b, 0x16a },
+       { 0x9011c, 0x18 },
+       { 0x9011d, 0x7aa },
+       { 0x9011e, 0x6a },
+       { 0x9011f, 0xa },
+       { 0x90120, 0x0 },
+       { 0x90121, 0x1e9 },
+       { 0x90122, 0x8 },
+       { 0x90123, 0x8080 },
+       { 0x90124, 0x108 },
+       { 0x90125, 0xf },
+       { 0x90126, 0x408 },
+       { 0x90127, 0x169 },
+       { 0x90128, 0xc },
+       { 0x90129, 0x0 },
+       { 0x9012a, 0x68 },
+       { 0x9012b, 0x9 },
+       { 0x9012c, 0x0 },
+       { 0x9012d, 0x1a9 },
+       { 0x9012e, 0x0 },
+       { 0x9012f, 0x408 },
+       { 0x90130, 0x169 },
+       { 0x90131, 0x0 },
+       { 0x90132, 0x8080 },
+       { 0x90133, 0x108 },
+       { 0x90134, 0x8 },
+       { 0x90135, 0x7aa },
+       { 0x90136, 0x6a },
+       { 0x90137, 0x0 },
+       { 0x90138, 0x8568 },
+       { 0x90139, 0x108 },
+       { 0x9013a, 0xb7 },
+       { 0x9013b, 0x790 },
+       { 0x9013c, 0x16a },
+       { 0x9013d, 0x1f },
+       { 0x9013e, 0x0 },
+       { 0x9013f, 0x68 },
+       { 0x90140, 0x8 },
+       { 0x90141, 0x8558 },
+       { 0x90142, 0x168 },
+       { 0x90143, 0xf },
+       { 0x90144, 0x408 },
+       { 0x90145, 0x169 },
+       { 0x90146, 0xc },
+       { 0x90147, 0x0 },
+       { 0x90148, 0x68 },
+       { 0x90149, 0x0 },
+       { 0x9014a, 0x408 },
+       { 0x9014b, 0x169 },
+       { 0x9014c, 0x0 },
+       { 0x9014d, 0x8558 },
+       { 0x9014e, 0x168 },
+       { 0x9014f, 0x8 },
+       { 0x90150, 0x3c8 },
+       { 0x90151, 0x1a9 },
+       { 0x90152, 0x3 },
+       { 0x90153, 0x370 },
+       { 0x90154, 0x129 },
+       { 0x90155, 0x20 },
+       { 0x90156, 0x2aa },
+       { 0x90157, 0x9 },
+       { 0x90158, 0x0 },
+       { 0x90159, 0x400 },
+       { 0x9015a, 0x10e },
+       { 0x9015b, 0x8 },
+       { 0x9015c, 0xe8 },
+       { 0x9015d, 0x109 },
+       { 0x9015e, 0x0 },
+       { 0x9015f, 0x8140 },
+       { 0x90160, 0x10c },
+       { 0x90161, 0x10 },
+       { 0x90162, 0x8138 },
+       { 0x90163, 0x10c },
+       { 0x90164, 0x8 },
+       { 0x90165, 0x7c8 },
+       { 0x90166, 0x101 },
+       { 0x90167, 0x8 },
+       { 0x90168, 0x0 },
+       { 0x90169, 0x8 },
+       { 0x9016a, 0x8 },
+       { 0x9016b, 0x448 },
+       { 0x9016c, 0x109 },
+       { 0x9016d, 0xf },
+       { 0x9016e, 0x7c0 },
+       { 0x9016f, 0x109 },
+       { 0x90170, 0x0 },
+       { 0x90171, 0xe8 },
+       { 0x90172, 0x109 },
+       { 0x90173, 0x47 },
+       { 0x90174, 0x630 },
+       { 0x90175, 0x109 },
+       { 0x90176, 0x8 },
+       { 0x90177, 0x618 },
+       { 0x90178, 0x109 },
+       { 0x90179, 0x8 },
+       { 0x9017a, 0xe0 },
+       { 0x9017b, 0x109 },
+       { 0x9017c, 0x0 },
+       { 0x9017d, 0x7c8 },
+       { 0x9017e, 0x109 },
+       { 0x9017f, 0x8 },
+       { 0x90180, 0x8140 },
+       { 0x90181, 0x10c },
+       { 0x90182, 0x0 },
+       { 0x90183, 0x1 },
+       { 0x90184, 0x8 },
+       { 0x90185, 0x8 },
+       { 0x90186, 0x4 },
+       { 0x90187, 0x8 },
+       { 0x90188, 0x8 },
+       { 0x90189, 0x7c8 },
+       { 0x9018a, 0x101 },
+       { 0x90006, 0x0 },
+       { 0x90007, 0x0 },
+       { 0x90008, 0x8 },
+       { 0x90009, 0x0 },
+       { 0x9000a, 0x0 },
+       { 0x9000b, 0x0 },
+       { 0xd00e7, 0x400 },
+       { 0x90017, 0x0 },
+       { 0x9001f, 0x2a },
+       { 0x90026, 0x6a },
+       { 0x400d0, 0x0 },
+       { 0x400d1, 0x101 },
+       { 0x400d2, 0x105 },
+       { 0x400d3, 0x107 },
+       { 0x400d4, 0x10f },
+       { 0x400d5, 0x202 },
+       { 0x400d6, 0x20a },
+       { 0x400d7, 0x20b },
+       { 0x2003a, 0x2 },
+       { 0x2000b, 0x5d },
+       { 0x2000c, 0xbb },
+       { 0x2000d, 0x753 },
+       { 0x2000e, 0x2c },
+       { 0x12000b, 0xc },
+       { 0x12000c, 0x19 },
+       { 0x12000d, 0xfa },
+       { 0x12000e, 0x10 },
+       { 0x22000b, 0x3 },
+       { 0x22000c, 0x6 },
+       { 0x22000d, 0x3e },
+       { 0x22000e, 0x10 },
+       { 0x9000c, 0x0 },
+       { 0x9000d, 0x173 },
+       { 0x9000e, 0x60 },
+       { 0x9000f, 0x6110 },
+       { 0x90010, 0x2152 },
+       { 0x90011, 0xdfbd },
+       { 0x90012, 0x60 },
+       { 0x90013, 0x6152 },
+       { 0x20010, 0x5a },
+       { 0x20011, 0x3 },
+       { 0x40080, 0xe0 },
+       { 0x40081, 0x12 },
+       { 0x40082, 0xe0 },
+       { 0x40083, 0x12 },
+       { 0x40084, 0xe0 },
+       { 0x40085, 0x12 },
+       { 0x140080, 0xe0 },
+       { 0x140081, 0x12 },
+       { 0x140082, 0xe0 },
+       { 0x140083, 0x12 },
+       { 0x140084, 0xe0 },
+       { 0x140085, 0x12 },
+       { 0x240080, 0xe0 },
+       { 0x240081, 0x12 },
+       { 0x240082, 0xe0 },
+       { 0x240083, 0x12 },
+       { 0x240084, 0xe0 },
+       { 0x240085, 0x12 },
+       { 0x400fd, 0xf },
+       { 0x10011, 0x1 },
+       { 0x10012, 0x1 },
+       { 0x10013, 0x180 },
+       { 0x10018, 0x1 },
+       { 0x10002, 0x6209 },
+       { 0x100b2, 0x1 },
+       { 0x101b4, 0x1 },
+       { 0x102b4, 0x1 },
+       { 0x103b4, 0x1 },
+       { 0x104b4, 0x1 },
+       { 0x105b4, 0x1 },
+       { 0x106b4, 0x1 },
+       { 0x107b4, 0x1 },
+       { 0x108b4, 0x1 },
+       { 0x11011, 0x1 },
+       { 0x11012, 0x1 },
+       { 0x11013, 0x180 },
+       { 0x11018, 0x1 },
+       { 0x11002, 0x6209 },
+       { 0x110b2, 0x1 },
+       { 0x111b4, 0x1 },
+       { 0x112b4, 0x1 },
+       { 0x113b4, 0x1 },
+       { 0x114b4, 0x1 },
+       { 0x115b4, 0x1 },
+       { 0x116b4, 0x1 },
+       { 0x117b4, 0x1 },
+       { 0x118b4, 0x1 },
+       { 0x12011, 0x1 },
+       { 0x12012, 0x1 },
+       { 0x12013, 0x180 },
+       { 0x12018, 0x1 },
+       { 0x12002, 0x6209 },
+       { 0x120b2, 0x1 },
+       { 0x121b4, 0x1 },
+       { 0x122b4, 0x1 },
+       { 0x123b4, 0x1 },
+       { 0x124b4, 0x1 },
+       { 0x125b4, 0x1 },
+       { 0x126b4, 0x1 },
+       { 0x127b4, 0x1 },
+       { 0x128b4, 0x1 },
+       { 0x13011, 0x1 },
+       { 0x13012, 0x1 },
+       { 0x13013, 0x180 },
+       { 0x13018, 0x1 },
+       { 0x13002, 0x6209 },
+       { 0x130b2, 0x1 },
+       { 0x131b4, 0x1 },
+       { 0x132b4, 0x1 },
+       { 0x133b4, 0x1 },
+       { 0x134b4, 0x1 },
+       { 0x135b4, 0x1 },
+       { 0x136b4, 0x1 },
+       { 0x137b4, 0x1 },
+       { 0x138b4, 0x1 },
+       { 0x2003a, 0x2 },
+       { 0xc0080, 0x2 },
+       { 0xd0000, 0x1 },
+};
+
+struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+       {
+               /* P0 3000mts 1D */
+               .drate = 3000,
+               .fw_type = FW_1D_IMAGE,
+               .fsp_cfg = lpddr4_fsp0_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+       },
+       {
+               /* P0 3000mts 2D */
+               .drate = 3000,
+               .fw_type = FW_2D_IMAGE,
+               .fsp_cfg = lpddr4_fsp0_2d_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+       },
+       {
+               /* P1 400mts 1D */
+               .drate = 400,
+               .fw_type = FW_1D_IMAGE,
+               .fsp_cfg = lpddr4_fsp1_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+       },
+       {
+               /* P1 100mts 1D */
+               .drate = 100,
+               .fw_type = FW_1D_IMAGE,
+               .fsp_cfg = lpddr4_fsp2_cfg,
+               .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+       },
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing = {
+       .ddrc_cfg = lpddr4_ddrc_cfg,
+       .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+       .ddrphy_cfg = lpddr4_ddrphy_cfg,
+       .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+       .fsp_msg = lpddr4_dram_fsp_msg,
+       .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+       .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+       .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+       .ddrphy_pie = lpddr4_phy_pie,
+       .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+};
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
new file mode 100644 (file)
index 0000000..35be2e8
--- /dev/null
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/pmic.h>
+#include <power/bd71837.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+       switch (boot_dev_spl) {
+       case SD2_BOOT:
+       case MMC2_BOOT:
+               return BOOT_DEVICE_MMC1;
+       case SD3_BOOT:
+       case MMC3_BOOT:
+               return BOOT_DEVICE_MMC2;
+       default:
+               return BOOT_DEVICE_NONE;
+       }
+}
+
+static void spl_dram_init(void)
+{
+       ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+       debug("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+       /* Just empty function now - can't decide what to choose */
+       debug("%s: %s\n", __func__, name);
+
+       return 0;
+}
+#endif
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+       IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+       IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+       IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+       struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+       imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+       set_wdog_reset(wdog);
+
+       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+       return 0;
+}
+
+static int power_init_board(void)
+{
+       struct udevice *dev;
+       int ret;
+
+       ret = pmic_get("pmic@4b", &dev);
+       if (ret == -ENODEV) {
+               puts("No pmic\n");
+               return 0;
+       }
+       if (ret != 0)
+               return ret;
+
+       /* decrease RESET key long push time from the default 10s to 10ms */
+       pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+
+       /* unlock the PMIC regs */
+       pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+
+       /* increase VDD_SOC to typical value 0.85v before first DRAM access */
+       pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+       /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+       pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+       /* lock the PMIC regs */
+       pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+
+       return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+       struct udevice *dev;
+       int ret;
+
+       arch_cpu_init();
+
+       init_uart_clk(1);
+
+       board_early_init_f();
+
+       timer_init();
+
+       preloader_console_init();
+
+       /* Clear the BSS. */
+       memset(__bss_start, 0, __bss_end - __bss_start);
+
+       ret = spl_early_init();
+       if (ret) {
+               debug("spl_early_init() failed: %d\n", ret);
+               hang();
+       }
+
+       ret = uclass_get_device_by_name(UCLASS_CLK,
+                                       "clock-controller@30380000",
+                                       &dev);
+       if (ret < 0) {
+               printf("Failed to find clock node. Check device tree\n");
+               hang();
+       }
+
+       enable_tzc380();
+
+       power_init_board();
+
+       /* DDR initialization */
+       spl_dram_init();
+
+       board_init_r(NULL, 0);
+}
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
new file mode 100644 (file)
index 0000000..b935d72
--- /dev/null
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_IMX8MM_BEACON=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_BD71837=y
+CONFIG_SPL_DM_REGULATOR_BD71837=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CONS_INDEX=2
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_MEM=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+# CONFIG_WATCHDOG is not set
+CONFIG_IMX_WATCHDOG=y
diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
new file mode 100644 (file)
index 0000000..21102d3
--- /dev/null
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+#ifndef __IMX8MM_BEACON_H
+#define __IMX8MM_BEACON_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE                SZ_8K
+#endif
+
+#define CONFIG_SPL_MAX_SIZE            (148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR        0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
+#define CONFIG_SYS_UBOOT_BASE  \
+       (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK               0x920000
+#define CONFIG_SPL_BSS_START_ADDR      0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE        SZ_8K   /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     SZ_512K /* 512 KB */
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR           0x930000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS              \
+       "script=boot.scr\0" \
+       "image=Image\0" \
+       "console=ttymxc1,115200\0" \
+       "fdt_addr=0x43000000\0"                 \
+       "fdt_high=0xffffffffffffffff\0"         \
+       "boot_fit=try\0" \
+       "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+       "initrd_addr=0x43800000\0"              \
+       "initrd_high=0xffffffffffffffff\0" \
+       "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+       "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+       "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+       "mmcautodetect=yes\0" \
+       "mmcargs=setenv bootargs console=${console},${baudrate}" \
+       " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \
+       "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
+       " ${script};\0" \
+       "bootscript=echo Running bootscript from mmc ...; " \
+               "source\0" \
+       "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run finduuid; " \
+               "run mmcargs; " \
+               "if run loadfdt; then " \
+                       "booti ${loadaddr} - ${fdt_addr}; " \
+               "else " \
+                       "echo WARN: Cannot load the DT; " \
+               "fi; " \
+       "netargs=setenv bootargs console=${console} " \
+               "root=/dev/nfs " \
+               "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+       "netboot=echo Booting from net ...; " \
+               "run netargs;  " \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "${get_cmd} ${loadaddr} ${image}; " \
+               "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+                       "bootm ${loadaddr}; " \
+               "else " \
+                       "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+                               "booti ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "echo WARN: Cannot load the DT; " \
+                       "fi; " \
+               "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+          "mmc dev ${mmcdev}; if mmc rescan; then " \
+                  "if run loadbootscript; then " \
+                          "run bootscript; " \
+                  "else " \
+                          "if run loadimage; then " \
+                                  "run mmcboot; " \
+                          "else run netboot; " \
+                          "fi; " \
+                  "fi; " \
+          "fi;"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR                        0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MMC_ENV_DEV 1   /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          SZ_32M
+
+#define CONFIG_SYS_SDRAM_BASE          0x40000000
+#define PHYS_SDRAM                     0x40000000
+#define PHYS_SDRAM_SIZE                0x80000000 /* 2GB DDR */
+
+#define CONFIG_SYS_MEMTEST_START       PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_MXC_UART_BASE           UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* USDHC */
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_MMC_IMG_LOAD_PART   1
+
+/* I2C */
+#define CONFIG_SYS_I2C_SPEED           100000
+
+/* FEC*/
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define FEC_QUIRK_ENET_MAC
+#define IMX_FEC_BASE                   0x30BE0000
+
+#endif