arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016-2018 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <log.h>
  10 #include <asm/io.h>
  11 #include <linux/delay.h>
  12 #include <linux/errno.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/soc.h>
  15 #include <fsl-mc/ldpaa_wriop.h>
  16
  17 #ifdef CONFIG_SYS_FSL_SRDS_1
  18 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  19 #endif
  20 #ifdef CONFIG_SYS_FSL_SRDS_2
  21 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  22 #endif
  23 #ifdef CONFIG_SYS_NXP_SRDS_3
  24 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
  25 #endif
  26
  27 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  28 #ifdef CONFIG_ARCH_LX2160A
  29 int xfi_dpmac[XFI14 + 1];
  30 int sgmii_dpmac[SGMII18 + 1];
  31 int a25gaui_dpmac[_25GE10 + 1];
  32 int xlaui_dpmac[_40GE2 + 1];
  33 int caui2_dpmac[_50GE2 + 1];
  34 int caui4_dpmac[_100GE2 + 1];
  35 #else
  36 int xfi_dpmac[XFI8 + 1];
  37 int sgmii_dpmac[SGMII16 + 1];
  38 #endif
  39 #endif
  40
  41 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  42 {
  43         return;
  44 }
  45
  46 /*
  47  *The return value of this func is the serdes protocol used.
  48  *Typically this function is called number of times depending
  49  *upon the number of serdes blocks in the Silicon.
  50  *Zero is used to denote that no serdes was enabled,
  51  *this is the case when golden RCW was used where DPAA2 bring was
  52  *intentionally removed to achieve boot to prompt
  53 */
  54
  55 __weak int serdes_get_number(int serdes, int cfg)
  56 {
  57         return cfg;
  58 }
  59
  60 int is_serdes_configured(enum srds_prtcl device)
  61 {
  62         int ret = 0;
  63
  64 #ifdef CONFIG_SYS_FSL_SRDS_1
  65         if (!serdes1_prtcl_map[NONE])
  66                 fsl_serdes_init();
  67
  68         ret |= serdes1_prtcl_map[device];
  69 #endif
  70 #ifdef CONFIG_SYS_FSL_SRDS_2
  71         if (!serdes2_prtcl_map[NONE])
  72                 fsl_serdes_init();
  73
  74         ret |= serdes2_prtcl_map[device];
  75 #endif
  76 #ifdef CONFIG_SYS_NXP_SRDS_3
  77         if (!serdes3_prtcl_map[NONE])
  78                 fsl_serdes_init();
  79
  80         ret |= serdes3_prtcl_map[device];
  81 #endif
  82
  83         return !!ret;
  84 }
  85
  86 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  87 {
  88         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  89         u32 cfg = 0;
  90         int i;
  91
  92         switch (sd) {
  93 #ifdef CONFIG_SYS_FSL_SRDS_1
  94         case FSL_SRDS_1:
  95                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  96                 cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  97                 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  98                 break;
  99 #endif
 100 #ifdef CONFIG_SYS_FSL_SRDS_2
 101         case FSL_SRDS_2:
 102                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
 103                 cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
 104                 cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
 105                 break;
 106 #endif
 107 #ifdef CONFIG_SYS_NXP_SRDS_3
 108         case NXP_SRDS_3:
 109                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
 110                 cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
 111                 cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
 112                 break;
 113 #endif
 114         default:
 115                 printf("invalid SerDes%d\n", sd);
 116                 break;
 117         }
 118
 119         cfg = serdes_get_number(sd, cfg);
 120
 121         /* Is serdes enabled at all? */
 122         if (cfg == 0)
 123                 return -ENODEV;
 124
 125         for (i = 0; i < SRDS_MAX_LANES; i++) {
 126                 if (serdes_get_prtcl(sd, cfg, i) == device)
 127                         return i;
 128         }
 129
 130         return -ENODEV;
 131 }
 132
 133 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 134                  u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 135 {
 136         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 137         u32 cfg;
 138         int lane;
 139
 140         if (serdes_prtcl_map[NONE])
 141                 return;
 142
 143         memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 144
 145         cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 146         cfg >>= sd_prctl_shift;
 147
 148         cfg = serdes_get_number(sd, cfg);
 149         printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 150
 151         if (!is_serdes_prtcl_valid(sd, cfg))
 152                 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
 153
 154         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 155                 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
 156                 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
 157                         debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
 158                 else {
 159                         serdes_prtcl_map[lane_prtcl] = 1;
 160 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 161 #ifdef CONFIG_ARCH_LX2160A
 162                         if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
 163                                 wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
 164                                                  (int)lane_prtcl);
 165
 166                         if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
 167                                 wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
 168                                                  (int)lane_prtcl);
 169
 170                         if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
 171                                 wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
 172                                                  (int)lane_prtcl);
 173
 174                         if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
 175                                 wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
 176                                                  (int)lane_prtcl);
 177
 178                         if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
 179                                 wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
 180                                                  (int)lane_prtcl);
 181
 182                         if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
 183                                 wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
 184                                                  (int)lane_prtcl);
 185
 186 #else
 187                         switch (lane_prtcl) {
 188                         case QSGMII_A:
 189                         case QSGMII_B:
 190                         case QSGMII_C:
 191                         case QSGMII_D:
 192                                 wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
 193                                 break;
 194                         default:
 195                                 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
 196                                         wriop_init_dpmac(sd,
 197                                                          xfi_dpmac[lane_prtcl],
 198                                                          (int)lane_prtcl);
 199
 200                                  if (lane_prtcl >= SGMII1 &&
 201                                      lane_prtcl <= SGMII16)
 202                                         wriop_init_dpmac(sd, sgmii_dpmac[
 203                                                          lane_prtcl],
 204                                                          (int)lane_prtcl);
 205                                 break;
 206                         }
 207 #endif
 208 #endif
 209                 }
 210         }
 211
 212         /* Set the first element to indicate serdes has been initialized */
 213         serdes_prtcl_map[NONE] = 1;
 214 }
 215
 216 __weak int get_serdes_volt(void)
 217 {
 218         return -1;
 219 }
 220
 221 __weak int set_serdes_volt(int svdd)
 222 {
 223         return -1;
 224 }
 225
 226 #define LNAGCR0_RT_RSTB         0x00600000
 227
 228 #define RSTCTL_RESET_MASK       0x000000E0
 229
 230 #define RSTCTL_RSTREQ           0x80000000
 231 #define RSTCTL_RST_DONE         0x40000000
 232 #define RSTCTL_RSTERR           0x20000000
 233
 234 #define RSTCTL_SDEN             0x00000020
 235 #define RSTCTL_SDRST_B          0x00000040
 236 #define RSTCTL_PLLRST_B         0x00000080
 237
 238 #define TCALCR_CALRST_B         0x08000000
 239
 240 struct serdes_prctl_info {
 241         u32 id;
 242         u32 mask;
 243         u32 shift;
 244 };
 245
 246 struct serdes_prctl_info srds_prctl_info[] = {
 247 #ifdef CONFIG_SYS_FSL_SRDS_1
 248         {.id = 1,
 249          .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 250          .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
 251         },
 252
 253 #endif
 254 #ifdef CONFIG_SYS_FSL_SRDS_2
 255         {.id = 2,
 256          .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 257          .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
 258         },
 259 #endif
 260 #ifdef CONFIG_SYS_NXP_SRDS_3
 261         {.id = 3,
 262          .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 263          .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
 264         },
 265 #endif
 266         {} /* NULL ENTRY */
 267 };
 268
 269 static int get_serdes_prctl_info_idx(u32 serdes_id)
 270 {
 271         int pos = 0;
 272         struct serdes_prctl_info *srds_info;
 273
 274         /* loop until NULL ENTRY defined by .id=0 */
 275         for (srds_info = srds_prctl_info; srds_info->id != 0;
 276              srds_info++, pos++) {
 277                 if (srds_info->id == serdes_id)
 278                         return pos;
 279         }
 280
 281         return -1;
 282 }
 283
 284 static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
 285                                    struct ccsr_serdes __iomem *serdes_base,
 286                                    bool cmplt)
 287 {
 288         int i, pos;
 289         u32 cfg_tmp;
 290
 291         pos = get_serdes_prctl_info_idx(serdes_id);
 292         if (pos == -1) {
 293                 printf("invalid serdes_id %d\n", serdes_id);
 294                 return;
 295         }
 296
 297         cfg_tmp = cfg & srds_prctl_info[pos].mask;
 298         cfg_tmp >>= srds_prctl_info[pos].shift;
 299
 300         for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
 301                 if (cmplt)
 302                         setbits_le32(&serdes_base->lane[i].gcr0,
 303                                      LNAGCR0_RT_RSTB);
 304                 else
 305                         clrbits_le32(&serdes_base->lane[i].gcr0,
 306                                      LNAGCR0_RT_RSTB);
 307         }
 308 }
 309
 310 static void do_pll_reset(u32 cfg,
 311                          struct ccsr_serdes __iomem *serdes_base)
 312 {
 313         int i;
 314
 315         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 316                 clrbits_le32(&serdes_base->bank[i].rstctl,
 317                              RSTCTL_RESET_MASK);
 318                 udelay(1);
 319
 320                 setbits_le32(&serdes_base->bank[i].rstctl,
 321                              RSTCTL_RSTREQ);
 322         }
 323         udelay(1);
 324 }
 325
 326 static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
 327 {
 328         clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 329         clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 330 }
 331
 332 static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
 333                                     struct ccsr_serdes __iomem *serdes_base)
 334 {
 335         if (!(cfg == 0x3 && i == 1)) {
 336                 udelay(1);
 337                 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 338                 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 339         }
 340         udelay(1);
 341 }
 342
 343 static void do_pll_reset_done(u32 cfg,
 344                               struct ccsr_serdes __iomem *serdes_base)
 345 {
 346         int i;
 347         u32 reg = 0;
 348
 349         for (i = 0; i < 2; i++) {
 350                 reg = in_le32(&serdes_base->bank[i].pllcr0);
 351                 if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
 352                         setbits_le32(&serdes_base->bank[i].rstctl,
 353                                      RSTCTL_RST_DONE);
 354                 }
 355         }
 356 }
 357
 358 static void do_serdes_enable(u32 cfg,
 359                              struct ccsr_serdes __iomem *serdes_base)
 360 {
 361         int i;
 362
 363         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 364                 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
 365                 udelay(1);
 366
 367                 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
 368                 udelay(1);
 369                 /* Take the Rx/Tx calibration out of reset */
 370                 do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
 371         }
 372 }
 373
 374 static void do_pll_lock(u32 cfg,
 375                         struct ccsr_serdes __iomem *serdes_base)
 376 {
 377         int i;
 378         u32 reg = 0;
 379
 380         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 381                 /* if the PLL is not locked, set RST_ERR */
 382                 reg = in_le32(&serdes_base->bank[i].pllcr0);
 383                 if (!((reg >> 23) & 0x1)) {
 384                         setbits_le32(&serdes_base->bank[i].rstctl,
 385                                      RSTCTL_RSTERR);
 386                 } else {
 387                         udelay(1);
 388                         setbits_le32(&serdes_base->bank[i].rstctl,
 389                                      RSTCTL_SDRST_B);
 390                         udelay(1);
 391                 }
 392         }
 393 }
 394
 395 int setup_serdes_volt(u32 svdd)
 396 {
 397         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 398         struct ccsr_serdes __iomem *serdes1_base =
 399                         (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
 400         u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
 401 #ifdef CONFIG_SYS_FSL_SRDS_2
 402         struct ccsr_serdes __iomem *serdes2_base =
 403                         (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
 404         u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
 405 #endif
 406 #ifdef CONFIG_SYS_NXP_SRDS_3
 407         struct ccsr_serdes __iomem *serdes3_base =
 408                         (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
 409         u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
 410 #endif
 411         u32 cfg_tmp;
 412         int svdd_cur, svdd_tar;
 413         int ret = 1;
 414
 415         /* Only support switch SVDD to 900mV */
 416         if (svdd != 900)
 417                 return -EINVAL;
 418
 419         /* Scale up to the LTC resolution is 1/4096V */
 420         svdd = (svdd * 4096) / 1000;
 421
 422         svdd_tar = svdd;
 423         svdd_cur = get_serdes_volt();
 424         if (svdd_cur < 0)
 425                 return -EINVAL;
 426
 427         debug("%s: current SVDD: %x; target SVDD: %x\n",
 428               __func__, svdd_cur, svdd_tar);
 429         if (svdd_cur == svdd_tar)
 430                 return 0;
 431
 432         /* Put the all enabled lanes in reset */
 433 #ifdef CONFIG_SYS_FSL_SRDS_1
 434         do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
 435 #endif
 436
 437 #ifdef CONFIG_SYS_FSL_SRDS_2
 438         do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
 439 #endif
 440 #ifdef CONFIG_SYS_NXP_SRDS_3
 441         do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
 442 #endif
 443
 444         /* Put the all enabled PLL in reset */
 445 #ifdef CONFIG_SYS_FSL_SRDS_1
 446         cfg_tmp = cfg_rcwsrds1 & 0x3;
 447         do_pll_reset(cfg_tmp, serdes1_base);
 448 #endif
 449
 450 #ifdef CONFIG_SYS_FSL_SRDS_2
 451         cfg_tmp = cfg_rcwsrds1 & 0xC;
 452         cfg_tmp >>= 2;
 453         do_pll_reset(cfg_tmp, serdes2_base);
 454 #endif
 455
 456 #ifdef CONFIG_SYS_NXP_SRDS_3
 457         cfg_tmp = cfg_rcwsrds3 & 0x30;
 458         cfg_tmp >>= 4;
 459         do_pll_reset(cfg_tmp, serdes3_base);
 460 #endif
 461
 462         /* Put the Rx/Tx calibration into reset */
 463 #ifdef CONFIG_SYS_FSL_SRDS_1
 464         do_rx_tx_cal_reset(serdes1_base);
 465 #endif
 466
 467 #ifdef CONFIG_SYS_FSL_SRDS_2
 468         do_rx_tx_cal_reset(serdes2_base);
 469 #endif
 470
 471 #ifdef CONFIG_SYS_NXP_SRDS_3
 472         do_rx_tx_cal_reset(serdes3_base);
 473 #endif
 474
 475         ret = set_serdes_volt(svdd);
 476         if (ret < 0) {
 477                 printf("could not change SVDD\n");
 478                 ret = -1;
 479         }
 480
 481         /* For each PLL that’s not disabled via RCW enable the SERDES */
 482 #ifdef CONFIG_SYS_FSL_SRDS_1
 483         cfg_tmp = cfg_rcwsrds1 & 0x3;
 484         do_serdes_enable(cfg_tmp, serdes1_base);
 485 #endif
 486 #ifdef CONFIG_SYS_FSL_SRDS_2
 487         cfg_tmp = cfg_rcwsrds1 & 0xC;
 488         cfg_tmp >>= 2;
 489         do_serdes_enable(cfg_tmp, serdes2_base);
 490 #endif
 491 #ifdef CONFIG_SYS_NXP_SRDS_3
 492         cfg_tmp = cfg_rcwsrds3 & 0x30;
 493         cfg_tmp >>= 4;
 494         do_serdes_enable(cfg_tmp, serdes3_base);
 495 #endif
 496
 497         /* Wait for at at least 625us, ensure the PLLs being reset are locked */
 498         udelay(800);
 499
 500 #ifdef CONFIG_SYS_FSL_SRDS_1
 501         cfg_tmp = cfg_rcwsrds1 & 0x3;
 502         do_pll_lock(cfg_tmp, serdes1_base);
 503 #endif
 504
 505 #ifdef CONFIG_SYS_FSL_SRDS_2
 506         cfg_tmp = cfg_rcwsrds1 & 0xC;
 507         cfg_tmp >>= 2;
 508         do_pll_lock(cfg_tmp, serdes2_base);
 509 #endif
 510
 511 #ifdef CONFIG_SYS_NXP_SRDS_3
 512         cfg_tmp = cfg_rcwsrds3 & 0x30;
 513         cfg_tmp >>= 4;
 514         do_pll_lock(cfg_tmp, serdes3_base);
 515 #endif
 516
 517         /* Take the all enabled lanes out of reset */
 518 #ifdef CONFIG_SYS_FSL_SRDS_1
 519         do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
 520 #endif
 521 #ifdef CONFIG_SYS_FSL_SRDS_2
 522         do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
 523 #endif
 524
 525 #ifdef CONFIG_SYS_NXP_SRDS_3
 526         do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
 527 #endif
 528
 529         /* For each PLL being reset, and achieved PLL lock set RST_DONE */
 530 #ifdef CONFIG_SYS_FSL_SRDS_1
 531         cfg_tmp = cfg_rcwsrds1 & 0x3;
 532         do_pll_reset_done(cfg_tmp, serdes1_base);
 533 #endif
 534 #ifdef CONFIG_SYS_FSL_SRDS_2
 535         cfg_tmp = cfg_rcwsrds1 & 0xC;
 536         cfg_tmp >>= 2;
 537         do_pll_reset_done(cfg_tmp, serdes2_base);
 538 #endif
 539
 540 #ifdef CONFIG_SYS_NXP_SRDS_3
 541         cfg_tmp = cfg_rcwsrds3 & 0x30;
 542         cfg_tmp >>= 4;
 543         do_pll_reset_done(cfg_tmp, serdes3_base);
 544 #endif
 545
 546         return ret;
 547 }
 548
 549 void fsl_serdes_init(void)
 550 {
 551 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 552         int i , j;
 553
 554 #ifdef CONFIG_ARCH_LX2160A
 555         for (i = XFI1, j = 1; i <= XFI14; i++, j++)
 556                 xfi_dpmac[i] = j;
 557
 558         for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
 559                 sgmii_dpmac[i] = j;
 560
 561         for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
 562                 a25gaui_dpmac[i] = j;
 563
 564         for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
 565                 xlaui_dpmac[i] = j;
 566
 567         for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
 568                 caui2_dpmac[i] = j;
 569
 570         for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
 571                 caui4_dpmac[i] = j;
 572 #else
 573         for (i = XFI1, j = 1; i <= XFI8; i++, j++)
 574                 xfi_dpmac[i] = j;
 575
 576         for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
 577                 sgmii_dpmac[i] = j;
 578 #endif
 579 #endif
 580
 581 #ifdef CONFIG_SYS_FSL_SRDS_1
 582         serdes_init(FSL_SRDS_1,
 583                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
 584                     FSL_CHASSIS3_SRDS1_REGSR,
 585                     FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 586                     FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
 587                     serdes1_prtcl_map);
 588 #endif
 589 #ifdef CONFIG_SYS_FSL_SRDS_2
 590         serdes_init(FSL_SRDS_2,
 591                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
 592                     FSL_CHASSIS3_SRDS2_REGSR,
 593                     FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 594                     FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
 595                     serdes2_prtcl_map);
 596 #endif
 597 #ifdef CONFIG_SYS_NXP_SRDS_3
 598         serdes_init(NXP_SRDS_3,
 599                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
 600                     FSL_CHASSIS3_SRDS3_REGSR,
 601                     FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 602                     FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
 603                     serdes3_prtcl_map);
 604 #endif
 605 }
 606
 607 int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
 608 {
 609         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 610         char scfg[16], snum[16];
 611         int cfgr = 0;
 612         u32 cfg;
 613
 614         cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 615         cfg >>= sd_prctl_shift;
 616         cfg = serdes_get_number(sd, cfg);
 617
 618 #if defined(SRDS_BITS_PER_LANE)
 619         /*
 620          * reverse lanes, lane 0 should be printed first so it must be moved to
 621          * high order bits.
 622          * For example bb58 should read 85bb, lane 0 being protocol 8.
 623          * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
 624          * independent per-lane protocol configuration, at this time LS1028A and
 625          * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
 626          * lanes as a single value.
 627          */
 628         for (int i = 0; i < SRDS_MAX_LANES; i++) {
 629                 int tmp;
 630
 631                 tmp = cfg >> (i * SRDS_BITS_PER_LANE);
 632                 tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
 633                 tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
 634                 cfgr |= tmp;
 635         }
 636 #endif /* SRDS_BITS_PER_LANE */
 637
 638         snprintf(snum, 16, "serdes%d", sd);
 639         snprintf(scfg, 16, "%x", cfgr);
 640         env_set(snum, scfg);
 641
 642         return 0;
 643 }
 644
 645 int serdes_misc_init(void)
 646 {
 647 #ifdef CONFIG_SYS_FSL_SRDS_1
 648         serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
 649                        FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 650                        FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
 651 #endif
 652 #ifdef CONFIG_SYS_FSL_SRDS_2
 653         serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
 654                        FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 655                        FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
 656 #endif
 657 #ifdef CONFIG_SYS_NXP_SRDS_3
 658         serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
 659                        FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 660                        FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
 661 #endif
 662
 663         return 0;
 664 }