arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016-2018 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <log.h>
  10 #include <asm/io.h>
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/errno.h>
  14 #include <asm/arch/fsl_serdes.h>
  15 #include <asm/arch/soc.h>
  16 #include <fsl-mc/ldpaa_wriop.h>
  17
  18 #ifdef CONFIG_SYS_FSL_SRDS_1
  19 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  20 #endif
  21 #ifdef CONFIG_SYS_FSL_SRDS_2
  22 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  23 #endif
  24 #ifdef CONFIG_SYS_NXP_SRDS_3
  25 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
  26 #endif
  27
  28 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  29 #ifdef CONFIG_ARCH_LX2160A
  30 int xfi_dpmac[XFI14 + 1];
  31 int sgmii_dpmac[SGMII18 + 1];
  32 int a25gaui_dpmac[_25GE10 + 1];
  33 int xlaui_dpmac[_40GE2 + 1];
  34 int caui2_dpmac[_50GE2 + 1];
  35 int caui4_dpmac[_100GE2 + 1];
  36 #else
  37 int xfi_dpmac[XFI8 + 1];
  38 int sgmii_dpmac[SGMII16 + 1];
  39 #endif
  40 #endif
  41
  42 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  43 {
  44         return;
  45 }
  46
  47 /*
  48  *The return value of this func is the serdes protocol used.
  49  *Typically this function is called number of times depending
  50  *upon the number of serdes blocks in the Silicon.
  51  *Zero is used to denote that no serdes was enabled,
  52  *this is the case when golden RCW was used where DPAA2 bring was
  53  *intentionally removed to achieve boot to prompt
  54 */
  55
  56 __weak int serdes_get_number(int serdes, int cfg)
  57 {
  58         return cfg;
  59 }
  60
  61 int is_serdes_configured(enum srds_prtcl device)
  62 {
  63         int ret = 0;
  64
  65 #ifdef CONFIG_SYS_FSL_SRDS_1
  66         if (!serdes1_prtcl_map[NONE])
  67                 fsl_serdes_init();
  68
  69         ret |= serdes1_prtcl_map[device];
  70 #endif
  71 #ifdef CONFIG_SYS_FSL_SRDS_2
  72         if (!serdes2_prtcl_map[NONE])
  73                 fsl_serdes_init();
  74
  75         ret |= serdes2_prtcl_map[device];
  76 #endif
  77 #ifdef CONFIG_SYS_NXP_SRDS_3
  78         if (!serdes3_prtcl_map[NONE])
  79                 fsl_serdes_init();
  80
  81         ret |= serdes3_prtcl_map[device];
  82 #endif
  83
  84         return !!ret;
  85 }
  86
  87 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  88 {
  89         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  90         u32 cfg = 0;
  91         int i;
  92
  93         switch (sd) {
  94 #ifdef CONFIG_SYS_FSL_SRDS_1
  95         case FSL_SRDS_1:
  96                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  97                 cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  98                 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  99                 break;
 100 #endif
 101 #ifdef CONFIG_SYS_FSL_SRDS_2
 102         case FSL_SRDS_2:
 103                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
 104                 cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
 105                 cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
 106                 break;
 107 #endif
 108 #ifdef CONFIG_SYS_NXP_SRDS_3
 109         case NXP_SRDS_3:
 110                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
 111                 cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
 112                 cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
 113                 break;
 114 #endif
 115         default:
 116                 printf("invalid SerDes%d\n", sd);
 117                 break;
 118         }
 119
 120         cfg = serdes_get_number(sd, cfg);
 121
 122         /* Is serdes enabled at all? */
 123         if (cfg == 0)
 124                 return -ENODEV;
 125
 126         for (i = 0; i < SRDS_MAX_LANES; i++) {
 127                 if (serdes_get_prtcl(sd, cfg, i) == device)
 128                         return i;
 129         }
 130
 131         return -ENODEV;
 132 }
 133
 134 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 135                  u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 136 {
 137         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 138         u32 cfg;
 139         int lane;
 140
 141         if (serdes_prtcl_map[NONE])
 142                 return;
 143
 144         memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 145
 146         cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 147         cfg >>= sd_prctl_shift;
 148
 149         cfg = serdes_get_number(sd, cfg);
 150         printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 151
 152         if (!is_serdes_prtcl_valid(sd, cfg))
 153                 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
 154
 155         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 156                 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
 157                 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
 158                         debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
 159                 else {
 160                         serdes_prtcl_map[lane_prtcl] = 1;
 161 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 162 #ifdef CONFIG_ARCH_LX2160A
 163                         if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
 164                                 wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
 165                                                  (int)lane_prtcl);
 166
 167                         if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
 168                                 wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
 169                                                  (int)lane_prtcl);
 170
 171                         if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
 172                                 wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
 173                                                  (int)lane_prtcl);
 174
 175                         if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
 176                                 wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
 177                                                  (int)lane_prtcl);
 178
 179                         if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
 180                                 wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
 181                                                  (int)lane_prtcl);
 182
 183                         if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
 184                                 wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
 185                                                  (int)lane_prtcl);
 186
 187 #else
 188                         switch (lane_prtcl) {
 189                         case QSGMII_A:
 190                         case QSGMII_B:
 191                         case QSGMII_C:
 192                         case QSGMII_D:
 193                                 wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
 194                                 break;
 195                         default:
 196                                 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
 197                                         wriop_init_dpmac(sd,
 198                                                          xfi_dpmac[lane_prtcl],
 199                                                          (int)lane_prtcl);
 200
 201                                  if (lane_prtcl >= SGMII1 &&
 202                                      lane_prtcl <= SGMII16)
 203                                         wriop_init_dpmac(sd, sgmii_dpmac[
 204                                                          lane_prtcl],
 205                                                          (int)lane_prtcl);
 206                                 break;
 207                         }
 208 #endif
 209 #endif
 210                 }
 211         }
 212
 213         /* Set the first element to indicate serdes has been initialized */
 214         serdes_prtcl_map[NONE] = 1;
 215 }
 216
 217 __weak int get_serdes_volt(void)
 218 {
 219         return -1;
 220 }
 221
 222 __weak int set_serdes_volt(int svdd)
 223 {
 224         return -1;
 225 }
 226
 227 #define LNAGCR0_RT_RSTB         0x00600000
 228
 229 #define RSTCTL_RESET_MASK       0x000000E0
 230
 231 #define RSTCTL_RSTREQ           0x80000000
 232 #define RSTCTL_RST_DONE         0x40000000
 233 #define RSTCTL_RSTERR           0x20000000
 234
 235 #define RSTCTL_SDEN             0x00000020
 236 #define RSTCTL_SDRST_B          0x00000040
 237 #define RSTCTL_PLLRST_B         0x00000080
 238
 239 #define TCALCR_CALRST_B         0x08000000
 240
 241 struct serdes_prctl_info {
 242         u32 id;
 243         u32 mask;
 244         u32 shift;
 245 };
 246
 247 struct serdes_prctl_info srds_prctl_info[] = {
 248 #ifdef CONFIG_SYS_FSL_SRDS_1
 249         {.id = 1,
 250          .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 251          .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
 252         },
 253
 254 #endif
 255 #ifdef CONFIG_SYS_FSL_SRDS_2
 256         {.id = 2,
 257          .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 258          .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
 259         },
 260 #endif
 261 #ifdef CONFIG_SYS_NXP_SRDS_3
 262         {.id = 3,
 263          .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 264          .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
 265         },
 266 #endif
 267         {} /* NULL ENTRY */
 268 };
 269
 270 static int get_serdes_prctl_info_idx(u32 serdes_id)
 271 {
 272         int pos = 0;
 273         struct serdes_prctl_info *srds_info;
 274
 275         /* loop until NULL ENTRY defined by .id=0 */
 276         for (srds_info = srds_prctl_info; srds_info->id != 0;
 277              srds_info++, pos++) {
 278                 if (srds_info->id == serdes_id)
 279                         return pos;
 280         }
 281
 282         return -1;
 283 }
 284
 285 static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
 286                                    struct ccsr_serdes __iomem *serdes_base,
 287                                    bool cmplt)
 288 {
 289         int i, pos;
 290         u32 cfg_tmp;
 291
 292         pos = get_serdes_prctl_info_idx(serdes_id);
 293         if (pos == -1) {
 294                 printf("invalid serdes_id %d\n", serdes_id);
 295                 return;
 296         }
 297
 298         cfg_tmp = cfg & srds_prctl_info[pos].mask;
 299         cfg_tmp >>= srds_prctl_info[pos].shift;
 300
 301         for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
 302                 if (cmplt)
 303                         setbits_le32(&serdes_base->lane[i].gcr0,
 304                                      LNAGCR0_RT_RSTB);
 305                 else
 306                         clrbits_le32(&serdes_base->lane[i].gcr0,
 307                                      LNAGCR0_RT_RSTB);
 308         }
 309 }
 310
 311 static void do_pll_reset(u32 cfg,
 312                          struct ccsr_serdes __iomem *serdes_base)
 313 {
 314         int i;
 315
 316         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 317                 clrbits_le32(&serdes_base->bank[i].rstctl,
 318                              RSTCTL_RESET_MASK);
 319                 udelay(1);
 320
 321                 setbits_le32(&serdes_base->bank[i].rstctl,
 322                              RSTCTL_RSTREQ);
 323         }
 324         udelay(1);
 325 }
 326
 327 static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
 328 {
 329         clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 330         clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 331 }
 332
 333 static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
 334                                     struct ccsr_serdes __iomem *serdes_base)
 335 {
 336         if (!(cfg == 0x3 && i == 1)) {
 337                 udelay(1);
 338                 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 339                 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 340         }
 341         udelay(1);
 342 }
 343
 344 static void do_pll_reset_done(u32 cfg,
 345                               struct ccsr_serdes __iomem *serdes_base)
 346 {
 347         int i;
 348         u32 reg = 0;
 349
 350         for (i = 0; i < 2; i++) {
 351                 reg = in_le32(&serdes_base->bank[i].pllcr0);
 352                 if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
 353                         setbits_le32(&serdes_base->bank[i].rstctl,
 354                                      RSTCTL_RST_DONE);
 355                 }
 356         }
 357 }
 358
 359 static void do_serdes_enable(u32 cfg,
 360                              struct ccsr_serdes __iomem *serdes_base)
 361 {
 362         int i;
 363
 364         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 365                 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
 366                 udelay(1);
 367
 368                 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
 369                 udelay(1);
 370                 /* Take the Rx/Tx calibration out of reset */
 371                 do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
 372         }
 373 }
 374
 375 static void do_pll_lock(u32 cfg,
 376                         struct ccsr_serdes __iomem *serdes_base)
 377 {
 378         int i;
 379         u32 reg = 0;
 380
 381         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 382                 /* if the PLL is not locked, set RST_ERR */
 383                 reg = in_le32(&serdes_base->bank[i].pllcr0);
 384                 if (!((reg >> 23) & 0x1)) {
 385                         setbits_le32(&serdes_base->bank[i].rstctl,
 386                                      RSTCTL_RSTERR);
 387                 } else {
 388                         udelay(1);
 389                         setbits_le32(&serdes_base->bank[i].rstctl,
 390                                      RSTCTL_SDRST_B);
 391                         udelay(1);
 392                 }
 393         }
 394 }
 395
 396 int setup_serdes_volt(u32 svdd)
 397 {
 398         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 399         struct ccsr_serdes __iomem *serdes1_base =
 400                         (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
 401         u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
 402 #ifdef CONFIG_SYS_FSL_SRDS_2
 403         struct ccsr_serdes __iomem *serdes2_base =
 404                         (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
 405         u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
 406 #endif
 407 #ifdef CONFIG_SYS_NXP_SRDS_3
 408         struct ccsr_serdes __iomem *serdes3_base =
 409                         (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
 410         u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
 411 #endif
 412         u32 cfg_tmp;
 413         int svdd_cur, svdd_tar;
 414         int ret = 1;
 415
 416         /* Only support switch SVDD to 900mV */
 417         if (svdd != 900)
 418                 return -EINVAL;
 419
 420         /* Scale up to the LTC resolution is 1/4096V */
 421         svdd = (svdd * 4096) / 1000;
 422
 423         svdd_tar = svdd;
 424         svdd_cur = get_serdes_volt();
 425         if (svdd_cur < 0)
 426                 return -EINVAL;
 427
 428         debug("%s: current SVDD: %x; target SVDD: %x\n",
 429               __func__, svdd_cur, svdd_tar);
 430         if (svdd_cur == svdd_tar)
 431                 return 0;
 432
 433         /* Put the all enabled lanes in reset */
 434 #ifdef CONFIG_SYS_FSL_SRDS_1
 435         do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
 436 #endif
 437
 438 #ifdef CONFIG_SYS_FSL_SRDS_2
 439         do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
 440 #endif
 441 #ifdef CONFIG_SYS_NXP_SRDS_3
 442         do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
 443 #endif
 444
 445         /* Put the all enabled PLL in reset */
 446 #ifdef CONFIG_SYS_FSL_SRDS_1
 447         cfg_tmp = cfg_rcwsrds1 & 0x3;
 448         do_pll_reset(cfg_tmp, serdes1_base);
 449 #endif
 450
 451 #ifdef CONFIG_SYS_FSL_SRDS_2
 452         cfg_tmp = cfg_rcwsrds1 & 0xC;
 453         cfg_tmp >>= 2;
 454         do_pll_reset(cfg_tmp, serdes2_base);
 455 #endif
 456
 457 #ifdef CONFIG_SYS_NXP_SRDS_3
 458         cfg_tmp = cfg_rcwsrds3 & 0x30;
 459         cfg_tmp >>= 4;
 460         do_pll_reset(cfg_tmp, serdes3_base);
 461 #endif
 462
 463         /* Put the Rx/Tx calibration into reset */
 464 #ifdef CONFIG_SYS_FSL_SRDS_1
 465         do_rx_tx_cal_reset(serdes1_base);
 466 #endif
 467
 468 #ifdef CONFIG_SYS_FSL_SRDS_2
 469         do_rx_tx_cal_reset(serdes2_base);
 470 #endif
 471
 472 #ifdef CONFIG_SYS_NXP_SRDS_3
 473         do_rx_tx_cal_reset(serdes3_base);
 474 #endif
 475
 476         ret = set_serdes_volt(svdd);
 477         if (ret < 0) {
 478                 printf("could not change SVDD\n");
 479                 ret = -1;
 480         }
 481
 482         /* For each PLL that’s not disabled via RCW enable the SERDES */
 483 #ifdef CONFIG_SYS_FSL_SRDS_1
 484         cfg_tmp = cfg_rcwsrds1 & 0x3;
 485         do_serdes_enable(cfg_tmp, serdes1_base);
 486 #endif
 487 #ifdef CONFIG_SYS_FSL_SRDS_2
 488         cfg_tmp = cfg_rcwsrds1 & 0xC;
 489         cfg_tmp >>= 2;
 490         do_serdes_enable(cfg_tmp, serdes2_base);
 491 #endif
 492 #ifdef CONFIG_SYS_NXP_SRDS_3
 493         cfg_tmp = cfg_rcwsrds3 & 0x30;
 494         cfg_tmp >>= 4;
 495         do_serdes_enable(cfg_tmp, serdes3_base);
 496 #endif
 497
 498         /* Wait for at at least 625us, ensure the PLLs being reset are locked */
 499         udelay(800);
 500
 501 #ifdef CONFIG_SYS_FSL_SRDS_1
 502         cfg_tmp = cfg_rcwsrds1 & 0x3;
 503         do_pll_lock(cfg_tmp, serdes1_base);
 504 #endif
 505
 506 #ifdef CONFIG_SYS_FSL_SRDS_2
 507         cfg_tmp = cfg_rcwsrds1 & 0xC;
 508         cfg_tmp >>= 2;
 509         do_pll_lock(cfg_tmp, serdes2_base);
 510 #endif
 511
 512 #ifdef CONFIG_SYS_NXP_SRDS_3
 513         cfg_tmp = cfg_rcwsrds3 & 0x30;
 514         cfg_tmp >>= 4;
 515         do_pll_lock(cfg_tmp, serdes3_base);
 516 #endif
 517
 518         /* Take the all enabled lanes out of reset */
 519 #ifdef CONFIG_SYS_FSL_SRDS_1
 520         do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
 521 #endif
 522 #ifdef CONFIG_SYS_FSL_SRDS_2
 523         do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
 524 #endif
 525
 526 #ifdef CONFIG_SYS_NXP_SRDS_3
 527         do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
 528 #endif
 529
 530         /* For each PLL being reset, and achieved PLL lock set RST_DONE */
 531 #ifdef CONFIG_SYS_FSL_SRDS_1
 532         cfg_tmp = cfg_rcwsrds1 & 0x3;
 533         do_pll_reset_done(cfg_tmp, serdes1_base);
 534 #endif
 535 #ifdef CONFIG_SYS_FSL_SRDS_2
 536         cfg_tmp = cfg_rcwsrds1 & 0xC;
 537         cfg_tmp >>= 2;
 538         do_pll_reset_done(cfg_tmp, serdes2_base);
 539 #endif
 540
 541 #ifdef CONFIG_SYS_NXP_SRDS_3
 542         cfg_tmp = cfg_rcwsrds3 & 0x30;
 543         cfg_tmp >>= 4;
 544         do_pll_reset_done(cfg_tmp, serdes3_base);
 545 #endif
 546
 547         return ret;
 548 }
 549
 550 void fsl_serdes_init(void)
 551 {
 552 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 553         int i , j;
 554
 555 #ifdef CONFIG_ARCH_LX2160A
 556         for (i = XFI1, j = 1; i <= XFI14; i++, j++)
 557                 xfi_dpmac[i] = j;
 558
 559         for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
 560                 sgmii_dpmac[i] = j;
 561
 562         for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
 563                 a25gaui_dpmac[i] = j;
 564
 565         for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
 566                 xlaui_dpmac[i] = j;
 567
 568         for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
 569                 caui2_dpmac[i] = j;
 570
 571         for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
 572                 caui4_dpmac[i] = j;
 573 #else
 574         for (i = XFI1, j = 1; i <= XFI8; i++, j++)
 575                 xfi_dpmac[i] = j;
 576
 577         for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
 578                 sgmii_dpmac[i] = j;
 579 #endif
 580 #endif
 581
 582 #ifdef CONFIG_SYS_FSL_SRDS_1
 583         serdes_init(FSL_SRDS_1,
 584                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
 585                     FSL_CHASSIS3_SRDS1_REGSR,
 586                     FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 587                     FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
 588                     serdes1_prtcl_map);
 589 #endif
 590 #ifdef CONFIG_SYS_FSL_SRDS_2
 591         serdes_init(FSL_SRDS_2,
 592                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
 593                     FSL_CHASSIS3_SRDS2_REGSR,
 594                     FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 595                     FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
 596                     serdes2_prtcl_map);
 597 #endif
 598 #ifdef CONFIG_SYS_NXP_SRDS_3
 599         serdes_init(NXP_SRDS_3,
 600                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
 601                     FSL_CHASSIS3_SRDS3_REGSR,
 602                     FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 603                     FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
 604                     serdes3_prtcl_map);
 605 #endif
 606 }
 607
 608 int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
 609 {
 610         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 611         char scfg[16], snum[16];
 612         int cfgr = 0;
 613         u32 cfg;
 614
 615         cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 616         cfg >>= sd_prctl_shift;
 617         cfg = serdes_get_number(sd, cfg);
 618
 619 #if defined(SRDS_BITS_PER_LANE)
 620         /*
 621          * reverse lanes, lane 0 should be printed first so it must be moved to
 622          * high order bits.
 623          * For example bb58 should read 85bb, lane 0 being protocol 8.
 624          * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
 625          * independent per-lane protocol configuration, at this time LS1028A and
 626          * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
 627          * lanes as a single value.
 628          */
 629         for (int i = 0; i < SRDS_MAX_LANES; i++) {
 630                 int tmp;
 631
 632                 tmp = cfg >> (i * SRDS_BITS_PER_LANE);
 633                 tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
 634                 tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
 635                 cfgr |= tmp;
 636         }
 637 #endif /* SRDS_BITS_PER_LANE */
 638
 639         snprintf(snum, 16, "serdes%d", sd);
 640         snprintf(scfg, 16, "%x", cfgr);
 641         env_set(snum, scfg);
 642
 643         return 0;
 644 }
 645
 646 int serdes_misc_init(void)
 647 {
 648 #ifdef CONFIG_SYS_FSL_SRDS_1
 649         serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
 650                        FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 651                        FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
 652 #endif
 653 #ifdef CONFIG_SYS_FSL_SRDS_2
 654         serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
 655                        FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 656                        FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
 657 #endif
 658 #ifdef CONFIG_SYS_NXP_SRDS_3
 659         serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
 660                        FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 661                        FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
 662 #endif
 663
 664         return 0;
 665 }