arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016-2018 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <asm/io.h>
  10 #include <linux/errno.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #include <asm/arch/soc.h>
  13 #include <fsl-mc/ldpaa_wriop.h>
  14
  15 #ifdef CONFIG_SYS_FSL_SRDS_1
  16 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  17 #endif
  18 #ifdef CONFIG_SYS_FSL_SRDS_2
  19 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  20 #endif
  21 #ifdef CONFIG_SYS_NXP_SRDS_3
  22 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
  23 #endif
  24
  25 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  26 #ifdef CONFIG_ARCH_LX2160A
  27 int xfi_dpmac[XFI14 + 1];
  28 int sgmii_dpmac[SGMII18 + 1];
  29 int a25gaui_dpmac[_25GE10 + 1];
  30 int xlaui_dpmac[_40GE2 + 1];
  31 int caui2_dpmac[_50GE2 + 1];
  32 int caui4_dpmac[_100GE2 + 1];
  33 #else
  34 int xfi_dpmac[XFI8 + 1];
  35 int sgmii_dpmac[SGMII16 + 1];
  36 #endif
  37 #endif
  38
  39 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  40 {
  41         return;
  42 }
  43
  44 /*
  45  *The return value of this func is the serdes protocol used.
  46  *Typically this function is called number of times depending
  47  *upon the number of serdes blocks in the Silicon.
  48  *Zero is used to denote that no serdes was enabled,
  49  *this is the case when golden RCW was used where DPAA2 bring was
  50  *intentionally removed to achieve boot to prompt
  51 */
  52
  53 __weak int serdes_get_number(int serdes, int cfg)
  54 {
  55         return cfg;
  56 }
  57
  58 int is_serdes_configured(enum srds_prtcl device)
  59 {
  60         int ret = 0;
  61
  62 #ifdef CONFIG_SYS_FSL_SRDS_1
  63         if (!serdes1_prtcl_map[NONE])
  64                 fsl_serdes_init();
  65
  66         ret |= serdes1_prtcl_map[device];
  67 #endif
  68 #ifdef CONFIG_SYS_FSL_SRDS_2
  69         if (!serdes2_prtcl_map[NONE])
  70                 fsl_serdes_init();
  71
  72         ret |= serdes2_prtcl_map[device];
  73 #endif
  74 #ifdef CONFIG_SYS_NXP_SRDS_3
  75         if (!serdes3_prtcl_map[NONE])
  76                 fsl_serdes_init();
  77
  78         ret |= serdes3_prtcl_map[device];
  79 #endif
  80
  81         return !!ret;
  82 }
  83
  84 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  85 {
  86         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  87         u32 cfg = 0;
  88         int i;
  89
  90         switch (sd) {
  91 #ifdef CONFIG_SYS_FSL_SRDS_1
  92         case FSL_SRDS_1:
  93                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  94                 cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  95                 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  96                 break;
  97 #endif
  98 #ifdef CONFIG_SYS_FSL_SRDS_2
  99         case FSL_SRDS_2:
 100                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
 101                 cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
 102                 cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
 103                 break;
 104 #endif
 105 #ifdef CONFIG_SYS_NXP_SRDS_3
 106         case NXP_SRDS_3:
 107                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
 108                 cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
 109                 cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
 110                 break;
 111 #endif
 112         default:
 113                 printf("invalid SerDes%d\n", sd);
 114                 break;
 115         }
 116
 117         cfg = serdes_get_number(sd, cfg);
 118
 119         /* Is serdes enabled at all? */
 120         if (cfg == 0)
 121                 return -ENODEV;
 122
 123         for (i = 0; i < SRDS_MAX_LANES; i++) {
 124                 if (serdes_get_prtcl(sd, cfg, i) == device)
 125                         return i;
 126         }
 127
 128         return -ENODEV;
 129 }
 130
 131 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 132                  u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 133 {
 134         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 135         u32 cfg;
 136         int lane;
 137
 138         if (serdes_prtcl_map[NONE])
 139                 return;
 140
 141         memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 142
 143         cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 144         cfg >>= sd_prctl_shift;
 145
 146         cfg = serdes_get_number(sd, cfg);
 147         printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 148
 149         if (!is_serdes_prtcl_valid(sd, cfg))
 150                 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
 151
 152         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 153                 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
 154                 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
 155                         debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
 156                 else {
 157                         serdes_prtcl_map[lane_prtcl] = 1;
 158 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 159 #ifdef CONFIG_ARCH_LX2160A
 160                         if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
 161                                 wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
 162                                                  (int)lane_prtcl);
 163
 164                         if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
 165                                 wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
 166                                                  (int)lane_prtcl);
 167
 168                         if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
 169                                 wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
 170                                                  (int)lane_prtcl);
 171
 172                         if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
 173                                 wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
 174                                                  (int)lane_prtcl);
 175
 176                         if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
 177                                 wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
 178                                                  (int)lane_prtcl);
 179
 180                         if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
 181                                 wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
 182                                                  (int)lane_prtcl);
 183
 184 #else
 185                         switch (lane_prtcl) {
 186                         case QSGMII_A:
 187                         case QSGMII_B:
 188                         case QSGMII_C:
 189                         case QSGMII_D:
 190                                 wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
 191                                 break;
 192                         default:
 193                                 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
 194                                         wriop_init_dpmac(sd,
 195                                                          xfi_dpmac[lane_prtcl],
 196                                                          (int)lane_prtcl);
 197
 198                                  if (lane_prtcl >= SGMII1 &&
 199                                      lane_prtcl <= SGMII16)
 200                                         wriop_init_dpmac(sd, sgmii_dpmac[
 201                                                          lane_prtcl],
 202                                                          (int)lane_prtcl);
 203                                 break;
 204                         }
 205 #endif
 206 #endif
 207                 }
 208         }
 209
 210         /* Set the first element to indicate serdes has been initialized */
 211         serdes_prtcl_map[NONE] = 1;
 212 }
 213
 214 __weak int get_serdes_volt(void)
 215 {
 216         return -1;
 217 }
 218
 219 __weak int set_serdes_volt(int svdd)
 220 {
 221         return -1;
 222 }
 223
 224 #define LNAGCR0_RT_RSTB         0x00600000
 225
 226 #define RSTCTL_RESET_MASK       0x000000E0
 227
 228 #define RSTCTL_RSTREQ           0x80000000
 229 #define RSTCTL_RST_DONE         0x40000000
 230 #define RSTCTL_RSTERR           0x20000000
 231
 232 #define RSTCTL_SDEN             0x00000020
 233 #define RSTCTL_SDRST_B          0x00000040
 234 #define RSTCTL_PLLRST_B         0x00000080
 235
 236 #define TCALCR_CALRST_B         0x08000000
 237
 238 struct serdes_prctl_info {
 239         u32 id;
 240         u32 mask;
 241         u32 shift;
 242 };
 243
 244 struct serdes_prctl_info srds_prctl_info[] = {
 245 #ifdef CONFIG_SYS_FSL_SRDS_1
 246         {.id = 1,
 247          .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 248          .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
 249         },
 250
 251 #endif
 252 #ifdef CONFIG_SYS_FSL_SRDS_2
 253         {.id = 2,
 254          .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 255          .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
 256         },
 257 #endif
 258 #ifdef CONFIG_SYS_NXP_SRDS_3
 259         {.id = 3,
 260          .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 261          .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
 262         },
 263 #endif
 264         {} /* NULL ENTRY */
 265 };
 266
 267 static int get_serdes_prctl_info_idx(u32 serdes_id)
 268 {
 269         int pos = 0;
 270         struct serdes_prctl_info *srds_info;
 271
 272         /* loop until NULL ENTRY defined by .id=0 */
 273         for (srds_info = srds_prctl_info; srds_info->id != 0;
 274              srds_info++, pos++) {
 275                 if (srds_info->id == serdes_id)
 276                         return pos;
 277         }
 278
 279         return -1;
 280 }
 281
 282 static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
 283                                    struct ccsr_serdes __iomem *serdes_base,
 284                                    bool cmplt)
 285 {
 286         int i, pos;
 287         u32 cfg_tmp;
 288
 289         pos = get_serdes_prctl_info_idx(serdes_id);
 290         if (pos == -1) {
 291                 printf("invalid serdes_id %d\n", serdes_id);
 292                 return;
 293         }
 294
 295         cfg_tmp = cfg & srds_prctl_info[pos].mask;
 296         cfg_tmp >>= srds_prctl_info[pos].shift;
 297
 298         for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
 299                 if (cmplt)
 300                         setbits_le32(&serdes_base->lane[i].gcr0,
 301                                      LNAGCR0_RT_RSTB);
 302                 else
 303                         clrbits_le32(&serdes_base->lane[i].gcr0,
 304                                      LNAGCR0_RT_RSTB);
 305         }
 306 }
 307
 308 static void do_pll_reset(u32 cfg,
 309                          struct ccsr_serdes __iomem *serdes_base)
 310 {
 311         int i;
 312
 313         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 314                 clrbits_le32(&serdes_base->bank[i].rstctl,
 315                              RSTCTL_RESET_MASK);
 316                 udelay(1);
 317
 318                 setbits_le32(&serdes_base->bank[i].rstctl,
 319                              RSTCTL_RSTREQ);
 320         }
 321         udelay(1);
 322 }
 323
 324 static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
 325 {
 326         clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 327         clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 328 }
 329
 330 static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
 331                                     struct ccsr_serdes __iomem *serdes_base)
 332 {
 333         if (!(cfg == 0x3 && i == 1)) {
 334                 udelay(1);
 335                 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 336                 setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
 337         }
 338         udelay(1);
 339 }
 340
 341 static void do_pll_reset_done(u32 cfg,
 342                               struct ccsr_serdes __iomem *serdes_base)
 343 {
 344         int i;
 345         u32 reg = 0;
 346
 347         for (i = 0; i < 2; i++) {
 348                 reg = in_le32(&serdes_base->bank[i].pllcr0);
 349                 if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
 350                         setbits_le32(&serdes_base->bank[i].rstctl,
 351                                      RSTCTL_RST_DONE);
 352                 }
 353         }
 354 }
 355
 356 static void do_serdes_enable(u32 cfg,
 357                              struct ccsr_serdes __iomem *serdes_base)
 358 {
 359         int i;
 360
 361         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 362                 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
 363                 udelay(1);
 364
 365                 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
 366                 udelay(1);
 367                 /* Take the Rx/Tx calibration out of reset */
 368                 do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
 369         }
 370 }
 371
 372 static void do_pll_lock(u32 cfg,
 373                         struct ccsr_serdes __iomem *serdes_base)
 374 {
 375         int i;
 376         u32 reg = 0;
 377
 378         for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
 379                 /* if the PLL is not locked, set RST_ERR */
 380                 reg = in_le32(&serdes_base->bank[i].pllcr0);
 381                 if (!((reg >> 23) & 0x1)) {
 382                         setbits_le32(&serdes_base->bank[i].rstctl,
 383                                      RSTCTL_RSTERR);
 384                 } else {
 385                         udelay(1);
 386                         setbits_le32(&serdes_base->bank[i].rstctl,
 387                                      RSTCTL_SDRST_B);
 388                         udelay(1);
 389                 }
 390         }
 391 }
 392
 393 int setup_serdes_volt(u32 svdd)
 394 {
 395         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 396         struct ccsr_serdes __iomem *serdes1_base =
 397                         (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
 398         u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
 399 #ifdef CONFIG_SYS_FSL_SRDS_2
 400         struct ccsr_serdes __iomem *serdes2_base =
 401                         (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
 402         u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
 403 #endif
 404 #ifdef CONFIG_SYS_NXP_SRDS_3
 405         struct ccsr_serdes __iomem *serdes3_base =
 406                         (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
 407         u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
 408 #endif
 409         u32 cfg_tmp;
 410         int svdd_cur, svdd_tar;
 411         int ret = 1;
 412
 413         /* Only support switch SVDD to 900mV */
 414         if (svdd != 900)
 415                 return -EINVAL;
 416
 417         /* Scale up to the LTC resolution is 1/4096V */
 418         svdd = (svdd * 4096) / 1000;
 419
 420         svdd_tar = svdd;
 421         svdd_cur = get_serdes_volt();
 422         if (svdd_cur < 0)
 423                 return -EINVAL;
 424
 425         debug("%s: current SVDD: %x; target SVDD: %x\n",
 426               __func__, svdd_cur, svdd_tar);
 427         if (svdd_cur == svdd_tar)
 428                 return 0;
 429
 430         /* Put the all enabled lanes in reset */
 431 #ifdef CONFIG_SYS_FSL_SRDS_1
 432         do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
 433 #endif
 434
 435 #ifdef CONFIG_SYS_FSL_SRDS_2
 436         do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
 437 #endif
 438 #ifdef CONFIG_SYS_NXP_SRDS_3
 439         do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
 440 #endif
 441
 442         /* Put the all enabled PLL in reset */
 443 #ifdef CONFIG_SYS_FSL_SRDS_1
 444         cfg_tmp = cfg_rcwsrds1 & 0x3;
 445         do_pll_reset(cfg_tmp, serdes1_base);
 446 #endif
 447
 448 #ifdef CONFIG_SYS_FSL_SRDS_2
 449         cfg_tmp = cfg_rcwsrds1 & 0xC;
 450         cfg_tmp >>= 2;
 451         do_pll_reset(cfg_tmp, serdes2_base);
 452 #endif
 453
 454 #ifdef CONFIG_SYS_NXP_SRDS_3
 455         cfg_tmp = cfg_rcwsrds3 & 0x30;
 456         cfg_tmp >>= 4;
 457         do_pll_reset(cfg_tmp, serdes3_base);
 458 #endif
 459
 460         /* Put the Rx/Tx calibration into reset */
 461 #ifdef CONFIG_SYS_FSL_SRDS_1
 462         do_rx_tx_cal_reset(serdes1_base);
 463 #endif
 464
 465 #ifdef CONFIG_SYS_FSL_SRDS_2
 466         do_rx_tx_cal_reset(serdes2_base);
 467 #endif
 468
 469 #ifdef CONFIG_SYS_NXP_SRDS_3
 470         do_rx_tx_cal_reset(serdes3_base);
 471 #endif
 472
 473         ret = set_serdes_volt(svdd);
 474         if (ret < 0) {
 475                 printf("could not change SVDD\n");
 476                 ret = -1;
 477         }
 478
 479         /* For each PLL that’s not disabled via RCW enable the SERDES */
 480 #ifdef CONFIG_SYS_FSL_SRDS_1
 481         cfg_tmp = cfg_rcwsrds1 & 0x3;
 482         do_serdes_enable(cfg_tmp, serdes1_base);
 483 #endif
 484 #ifdef CONFIG_SYS_FSL_SRDS_2
 485         cfg_tmp = cfg_rcwsrds1 & 0xC;
 486         cfg_tmp >>= 2;
 487         do_serdes_enable(cfg_tmp, serdes2_base);
 488 #endif
 489 #ifdef CONFIG_SYS_NXP_SRDS_3
 490         cfg_tmp = cfg_rcwsrds3 & 0x30;
 491         cfg_tmp >>= 4;
 492         do_serdes_enable(cfg_tmp, serdes3_base);
 493 #endif
 494
 495         /* Wait for at at least 625us, ensure the PLLs being reset are locked */
 496         udelay(800);
 497
 498 #ifdef CONFIG_SYS_FSL_SRDS_1
 499         cfg_tmp = cfg_rcwsrds1 & 0x3;
 500         do_pll_lock(cfg_tmp, serdes1_base);
 501 #endif
 502
 503 #ifdef CONFIG_SYS_FSL_SRDS_2
 504         cfg_tmp = cfg_rcwsrds1 & 0xC;
 505         cfg_tmp >>= 2;
 506         do_pll_lock(cfg_tmp, serdes2_base);
 507 #endif
 508
 509 #ifdef CONFIG_SYS_NXP_SRDS_3
 510         cfg_tmp = cfg_rcwsrds3 & 0x30;
 511         cfg_tmp >>= 4;
 512         do_pll_lock(cfg_tmp, serdes3_base);
 513 #endif
 514
 515         /* Take the all enabled lanes out of reset */
 516 #ifdef CONFIG_SYS_FSL_SRDS_1
 517         do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
 518 #endif
 519 #ifdef CONFIG_SYS_FSL_SRDS_2
 520         do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
 521 #endif
 522
 523 #ifdef CONFIG_SYS_NXP_SRDS_3
 524         do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
 525 #endif
 526
 527         /* For each PLL being reset, and achieved PLL lock set RST_DONE */
 528 #ifdef CONFIG_SYS_FSL_SRDS_1
 529         cfg_tmp = cfg_rcwsrds1 & 0x3;
 530         do_pll_reset_done(cfg_tmp, serdes1_base);
 531 #endif
 532 #ifdef CONFIG_SYS_FSL_SRDS_2
 533         cfg_tmp = cfg_rcwsrds1 & 0xC;
 534         cfg_tmp >>= 2;
 535         do_pll_reset_done(cfg_tmp, serdes2_base);
 536 #endif
 537
 538 #ifdef CONFIG_SYS_NXP_SRDS_3
 539         cfg_tmp = cfg_rcwsrds3 & 0x30;
 540         cfg_tmp >>= 4;
 541         do_pll_reset_done(cfg_tmp, serdes3_base);
 542 #endif
 543
 544         return ret;
 545 }
 546
 547 void fsl_serdes_init(void)
 548 {
 549 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 550         int i , j;
 551
 552 #ifdef CONFIG_ARCH_LX2160A
 553         for (i = XFI1, j = 1; i <= XFI14; i++, j++)
 554                 xfi_dpmac[i] = j;
 555
 556         for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
 557                 sgmii_dpmac[i] = j;
 558
 559         for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
 560                 a25gaui_dpmac[i] = j;
 561
 562         for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
 563                 xlaui_dpmac[i] = j;
 564
 565         for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
 566                 caui2_dpmac[i] = j;
 567
 568         for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
 569                 caui4_dpmac[i] = j;
 570 #else
 571         for (i = XFI1, j = 1; i <= XFI8; i++, j++)
 572                 xfi_dpmac[i] = j;
 573
 574         for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
 575                 sgmii_dpmac[i] = j;
 576 #endif
 577 #endif
 578
 579 #ifdef CONFIG_SYS_FSL_SRDS_1
 580         serdes_init(FSL_SRDS_1,
 581                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
 582                     FSL_CHASSIS3_SRDS1_REGSR,
 583                     FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 584                     FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
 585                     serdes1_prtcl_map);
 586 #endif
 587 #ifdef CONFIG_SYS_FSL_SRDS_2
 588         serdes_init(FSL_SRDS_2,
 589                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
 590                     FSL_CHASSIS3_SRDS2_REGSR,
 591                     FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 592                     FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
 593                     serdes2_prtcl_map);
 594 #endif
 595 #ifdef CONFIG_SYS_NXP_SRDS_3
 596         serdes_init(NXP_SRDS_3,
 597                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
 598                     FSL_CHASSIS3_SRDS3_REGSR,
 599                     FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 600                     FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
 601                     serdes3_prtcl_map);
 602 #endif
 603 }
 604
 605 int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
 606 {
 607         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 608         char scfg[16], snum[16];
 609         int cfgr = 0;
 610         u32 cfg;
 611
 612         cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 613         cfg >>= sd_prctl_shift;
 614         cfg = serdes_get_number(sd, cfg);
 615
 616 #if defined(SRDS_BITS_PER_LANE)
 617         /*
 618          * reverse lanes, lane 0 should be printed first so it must be moved to
 619          * high order bits.
 620          * For example bb58 should read 85bb, lane 0 being protocol 8.
 621          * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
 622          * independent per-lane protocol configuration, at this time LS1028A and
 623          * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
 624          * lanes as a single value.
 625          */
 626         for (int i = 0; i < SRDS_MAX_LANES; i++) {
 627                 int tmp;
 628
 629                 tmp = cfg >> (i * SRDS_BITS_PER_LANE);
 630                 tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
 631                 tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
 632                 cfgr |= tmp;
 633         }
 634 #endif /* SRDS_BITS_PER_LANE */
 635
 636         snprintf(snum, 16, "serdes%d", sd);
 637         snprintf(scfg, 16, "%x", cfgr);
 638         env_set(snum, scfg);
 639
 640         return 0;
 641 }
 642
 643 int serdes_misc_init(void)
 644 {
 645 #ifdef CONFIG_SYS_FSL_SRDS_1
 646         serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
 647                        FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 648                        FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
 649 #endif
 650 #ifdef CONFIG_SYS_FSL_SRDS_2
 651         serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
 652                        FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 653                        FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
 654 #endif
 655 #ifdef CONFIG_SYS_NXP_SRDS_3
 656         serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
 657                        FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 658                        FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
 659 #endif
 660
 661         return 0;
 662 }