better a_sc inline asm constraint on aarch64 and arm

"Q" input constraint was used for the written object, instead of "=Q"
output constraint.  this should not cause problems because "memory"
is on the clobber list, but "=Q" better documents the intent and more
consistent with the actual asm code.

this changes the generated code, because different registers are used,
but other than the register names nothing should change.

diff --git a/arch/aarch64/atomic_arch.h b/arch/aarch64/atomic_arch.h
index 6b4f1a4d659fef383047d573c3050cce560e234c..af93d879d2adbe4d900fb8a48d776de8c30513b6 100644 (file)
--- a/arch/aarch64/atomic_arch.h
+++ b/arch/aarch64/atomic_arch.h
@@ -10,7 +10,7 @@ static inline int a_ll(volatile int *p)
 static inline int a_sc(volatile int *p, int v)
 {
        int r;
-       __asm__ __volatile__ ("stlxr %w0,%w1,%2" : "=&r"(r) : "r"(v), "Q"(*p) : "memory");
+       __asm__ __volatile__ ("stlxr %w0,%w2,%1" : "=&r"(r), "=Q"(*p) : "r"(v) : "memory");
        return !r;
 }
 
@@ -44,7 +44,7 @@ static inline void *a_ll_p(volatile void *p)
 static inline int a_sc_p(volatile int *p, void *v)
 {
        int r;
-       __asm__ __volatile__ ("stlxr %w0,%1,%2" : "=&r"(r) : "r"(v), "Q"(*(void *volatile *)p) : "memory");
+       __asm__ __volatile__ ("stlxr %w0,%2,%1" : "=&r"(r), "=Q"(*(void *volatile *)p) : "r"(v) : "memory");
        return !r;
 }
 

diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h
index 21db6b229aaae099c596c2c08fb24387ab4c4b02..706fa1f22ce7021b759ae879ae7e9d9665e64888 100644 (file)
--- a/arch/arm/atomic_arch.h
+++ b/arch/arm/atomic_arch.h
@@ -16,7 +16,7 @@ static inline int a_ll(volatile int *p)
 static inline int a_sc(volatile int *p, int v)
 {
        int r;
-       __asm__ __volatile__ ("strex %0,%1,%2" : "=&r"(r) : "r"(v), "Q"(*p) : "memory");
+       __asm__ __volatile__ ("strex %0,%2,%1" : "=&r"(r), "=Q"(*p) : "r"(v) : "memory");
        return !r;
 }