1 # 0x00 ZM_MAIN_CTRL_OFFSET
3 * BIT6 - 1 = HighSpeed is set (read only?)
7 * BIT2 - 1 = enable global Int
9 * BIT0 - 1 = set Remote Wake Up;
11 # 0x01 ZM_DEVICE_ADDRESS_OFFSET
12 * BIT7 - usb config? (r/w)
22 * BIT0 - 1 ?? used on usb 2.0 init
24 # 0x08 ZM_PHY_TEST_SELECT_OFFSET
34 # 0x0A ZM_VDR_SPECIFIC_MODE_OFFSET
36 # 0x0B ZM_CX_CONFIG_STATUS_OFFSET
39 * BIT5 - indicator that frame was transmitted.
41 * BIT3 - set to drom the fram?
42 * BIT2 - set CX_STL to stall Endpoint0 & will also clear FIFO0
44 * BIT0 - set CX_DONE to indicate the transmistion of control frame
46 # 0x0C ZM_EP0_DATA1_OFFSET
47 # 0x0D ZM_EP0_DATA2_OFFSET
48 # 0x0C ZM_EP0_DATA_OFFSET
49 * Write 32bit data to fifo
51 # 0x11 ZM_INTR_MASK_BYTE_0_OFFSET
52 # 0x12 ZM_INTR_MASK_BYTE_1_OFFSET
55 # 0x13 ZM_INTR_MASK_BYTE_2_OFFSET
58 # 0x14 ZM_INTR_MASK_BYTE_3_OFFSET
61 # 0x15 ZM_INTR_MASK_BYTE_4_OFFSET
63 #define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
64 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
65 #define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
66 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0xc0)
68 # 0x16 ZM_INTR_MASK_BYTE_5_OFFSET
71 # 0x17 ZM_INTR_MASK_BYTE_6_OFFSET
74 #define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
75 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
76 #define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
77 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)
79 # 0x18 ZM_INTR_MASK_BYTE_7_OFFSET
81 # 0x20 ZM_INTR_GROUP_OFFSET
82 # 0x21 ZM_INTR_SOURCE_0_OFFSET
83 # 0x22 ZM_INTR_SOURCE_1_OFFSET
84 # 0x23 ZM_INTR_SOURCE_2_OFFSET
85 # 0x24 ZM_INTR_SOURCE_3_OFFSET
86 # 0x25 ZM_INTR_SOURCE_4_OFFSET
87 # 0x26 ZM_INTR_SOURCE_5_OFFSET
88 # 0x27 ZM_INTR_SOURCE_6_OFFSET
89 # 0x28 ZM_INTR_SOURCE_7_OFFSET
91 # 0x3F ZM_EP_IN_MAX_SIZE_HIGH_OFFSET
92 # 0x3E ZM_EP_IN_MAX_SIZE_LOW_OFFSET
94 # 0x5F ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET
95 # 0x5E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET
97 # 0xAE ZM_EP3_BYTE_COUNT_HIGH_OFFSET
99 comments: after sending data from target to host, set BIT3
100 # 0xBE ZM_EP3_BYTE_COUNT_LOW_OFFSET
101 # 0xAF ZM_EP4_BYTE_COUNT_HIGH_OFFSET
102 BIT4 - 1 - reset fifo; 0 - disable reset?
103 comments: probably compatible with ZM_EP3_BYTE_COUNT_HIGH_OFFSET
104 # 0xBF ZM_EP4_BYTE_COUNT_LOW_OFFSET
105 size of data in fifo buffer
107 # 0xF8 ZM_EP3_DATA_OFFSET
108 # 0xFC ZM_EP4_DATA_OFFSET
110 # 0x108 ZM_SOC_USB_MODE_CTRL_OFFSET
111 BIT10 - 1 - enable MP (EP6) downstream stream mode
112 BIT9 - 1 - enable MP (EP6) downstream DMA mode
113 BIT8 - 1 - enable HP (EP5) downstream DMA mode
114 BIT7 - 1 - enable HP (EP5) downstream stream mode
115 BIT6 - 1 - enable LP downstream stream mode
116 BIT5 - define the host dma buffer size - 4096(00) 8192 (01) 16384(10) 32768(11) bytes
118 BIT3 - 0 - enable upstream stream mode: 1 - enable upstream packed mode;
119 BIT2 - 0 - Set into 64 byte mode (full speed) 1 - Set into 512 byte mode (usb highspeed)
120 BIT1 - 0 - disable upstream dma mode; 1 - enable upstream dma mode
121 BIT0 - 0 - disable LP down stream dma mode; 1 - eanble LP down stream dma mode
123 ryan: 04/01: bit0 could disable lpdn dma, which is good at debugging while async_fifo have problem, we could disable this and check the fifo_rcv_size to see if we have correct at fifo or not
124 LP - lo priotiry; MP - middle priority; HP - High priority;
127 # 0x110 ZM_SOC_USB_MAX_AGGREGATE_OFFSET
128 set stream mode packet buffer critirea
129 0x0 = disable stream mode or 1 packet. So 0x9 is 10 packets?
130 # 0x114 ZM_SOC_USB_TIME_CTRL_OFFSET
131 set stream mode timeout critirea. the unit is 32 USB (30Mhz) clock cycles.