1 Assumptions made on source code:
2 * looks like USB block is [FUSB200](http://www.faraday-tech.com/techDocument/FUSB200_ProductBrief_v1_2.pdf).
3 * According to docs FUSB200 has 15 endpoints, but according to the source 10.
5 # 0x00 ZM_MAIN_CTRL_OFFSET
7 * BIT6 - 1 = HighSpeed is set (read only?)
11 * BIT2 - 1 = enable global Int
13 * BIT0 - 1 = set Remote Wake Up;
15 # 0x01 ZM_DEVICE_ADDRESS_OFFSET
16 * BIT7 - usb config? (r/w)
26 * BIT0 - 1 ?? set on usb 2.0 init
28 # 0x08 ZM_PHY_TEST_SELECT_OFFSET
32 * BIT4 - TEST_PKY - Test packed.
38 According to FUSB200 doc:
39 DM(D-) DP(D+) Description
44 0: Control PHY to turn off 1.5K Ohm pull-up resistor
45 1: Control PHY to turn on 1.5K Ohm pull-up resistor
46 If TEST_PKY is set, the test packet must be filled into FIFO by DMA first.
49 # 0x0A ZM_VDR_SPECIFIC_MODE_OFFSET
51 # 0x0B ZM_CX_CONFIG_STATUS_OFFSET
54 * BIT5 - indicator that frame was transmitted.
56 * BIT3 - set to drom the fram?
57 * BIT2 - set CX_STL to stall Endpoint0 & will also clear FIFO0
59 * BIT0 - set CX_DONE to indicate the transmistion of control frame
61 # 0x0C ZM_EP0_DATA_OFFSET
62 * Write 32bit data to fifo
64 # 0x11 ZM_INTR_MASK_BYTE_0_OFFSET
65 Theoretically INTR_MASK_BYTE should control INTR_SOURCE. Is it correct?
67 # 0x12 ZM_INTR_MASK_BYTE_1_OFFSET
70 # 0x13 ZM_INTR_MASK_BYTE_2_OFFSET
73 # 0x14 ZM_INTR_MASK_BYTE_3_OFFSET
76 # 0x15 ZM_INTR_MASK_BYTE_4_OFFSET
78 #define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
79 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
80 #define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
81 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0xc0)
83 # 0x16 ZM_INTR_MASK_BYTE_5_OFFSET
86 # 0x17 ZM_INTR_MASK_BYTE_6_OFFSET
89 #define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
90 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
91 #define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
92 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)
94 # 0x18 ZM_INTR_MASK_BYTE_7_OFFSET
96 # 0x20 ZM_INTR_GROUP_OFFSET
100 * BIT4 - group INTR 4
101 * BIT3 - group INTR 3
102 * BIT2 - group INTR 2
103 * BIT1 - group INTR 1
104 * BIT0 - group INTR 0
105 These bits indicate if fallowing groups got some interrupt.
107 # 0x21 ZM_INTR_SOURCE_0_OFFSET
108 * BIT7 - abort interrupt? should be cleared first?
111 * BIT4 - ep0 CMD_FAIL
113 * BIT2 - USB EP0 OUT/rx interrupt
114 * BIT1 - USB EP0 IN/tx interrupt
117 # 0x22 ZM_INTR_SOURCE_1_OFFSET
118 # 0x23 ZM_INTR_SOURCE_2_OFFSET
119 # 0x24 ZM_INTR_SOURCE_3_OFFSET
120 # 0x25 ZM_INTR_SOURCE_4_OFFSET
121 * BIT7 - End of data.
122 * BIT6 - vUsb_Reg_Out(). Pending data in fifo for EP4. We need to read it out.
123 Comments: we can read only 64bytes per time. If pending data is less then 64bytes or it is end of packet, then BIT6 and BIT7 will be set. If not, then only BIT6 is set.
125 # 0x26 ZM_INTR_SOURCE_5_OFFSET
126 these endpoints are handled by DMA
128 # 0x27 ZM_INTR_SOURCE_6_OFFSET
129 * BIT6 - vUsb_Status_In()?
131 # 0x28 ZM_INTR_SOURCE_7_OFFSET
138 * BIT1 - USB reset interrupt.
142 code use: ZM_FUSB_BASE+0x30+(EPn-1)
143 (0x0F | FIFOn << 4) = OUT
146 for FIFOn see mUsbFIFOMap registers.
148 Current configuration:
150 * 0x30 0x0f <- EP1 = OUT + Start FIFO0
151 * 0x31 0xf2 <- EP2 = IN + Start FIFO2
152 * 0x32 0xfe <- EP3 = IN + Start FIFO14
153 * 0x33 0xff <- EP4 = OUT + Start FIFO15
175 # 0x39 mUsbEPMap EP10
176 # 0x3a mUsbEPMap EP11
177 # 0x3b mUsbEPMap EP12
178 # 0x3c mUsbEPMap EP13
179 # 0x3d mUsbEPMap EP14
180 # 0x3e mUsbEPMap EP15
182 # 0x3E ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP0
183 * BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_IN_MAX_SIZE_LOW_OFFSET + ZM_EP_IN_MAX_SIZE_HIGH_OFFSET)
185 # 0x3F ZM_EP_IN_MAX_SIZE_HIGH_OFFSET EP0
189 * BIT4 - mUsbEPinRsTgSet
190 * BIT3 - mUsbEPinStallSet
191 * BIT0 - BIT2; High size regs
192 These offset + 2 Byte step for each endpoint.
193 For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
196 # 0x40 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP1
197 # 0x42 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP2
198 # 0x44 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP3
199 # 0x46 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP4
200 # 0x48 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP5
201 # 0x4A ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP6
202 # 0x4C ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP7
203 # 0x4E ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP8
204 # 0x50 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP9
205 # 0x52 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP10
206 # 0x54 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP11
207 # 0x56 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP12
208 # 0x58 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP13
209 # 0x5A ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP14
210 # 0x5C ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP15
212 # 0x5E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP0
213 * BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_OUT_MAX_SIZE_LOW_OFFSET + ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET)
215 # 0x5F ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET EP0
219 * BIT4 - mUsbEPoutRsTgSet
220 * BIT3 - mUsbEPoutStallSet
221 * BIT0 - BIT2; High size regs
223 These offset + 2 Byte step for each endpoint.
224 For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
226 # 0x60 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP1
227 # 0x62 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP2
228 # 0x64 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP3
229 # 0x66 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP4
230 # 0x68 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP5
231 # 0x6A ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP6
232 # 0x6C ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP7
233 # 0x6E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP8
234 # 0x70 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP9
235 # 0x72 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP10
236 # 0x74 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP11
237 # 0x76 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP12
238 # 0x78 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP13
239 # 0x7A ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP14
240 # 0x7C ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP15
242 # 0x80 mUsbFIFOMap FIFO0
246 * BIT4 - Direction: 0 - OUT; 1 - IN.
247 * BIT0 - BIT3: assigned EP number.
250 * 0x80 0x01 - EP1 OUT
251 * 0x81 0x01 - EP1 OUT
267 # 0x81 mUsbFIFOMap FIFO1
268 # 0x82 mUsbFIFOMap FIFO2
269 # 0x83 mUsbFIFOMap FIFO3
270 # 0x84 mUsbFIFOMap FIFO4
271 # 0x85 mUsbFIFOMap FIFO5
272 # 0x86 mUsbFIFOMap FIFO6
273 # 0x87 mUsbFIFOMap FIFO7
274 # 0x88 mUsbFIFOMap FIFO8
275 # 0x89 mUsbFIFOMap FIFO9
276 # 0x8a mUsbFIFOMap FIFO10
277 # 0x8b mUsbFIFOMap FIFO11
278 # 0x8c mUsbFIFOMap FIFO12
279 # 0x8d mUsbFIFOMap FIFO13
280 # 0x8e mUsbFIFOMap FIFO14
281 # 0x8f mUsbFIFOMap FIFO15
283 # 0x90 mUsbFIFOConfig FIFO0
284 * BIT7 - If EPn use more then one FIFO, then this bit should be on the first
287 * BIT4 - Block size: 0 - 64/512; 1 - 128/1024. It depends on initial FIFO size.
288 * BIT2 - BIT3; number of FIFO blocks or better to say extra blocks? 0 - no more blocks; 1 - one block; 2 - two blocks.
289 * BIT0 - BIT1; EP type: 0x1 - Iso; 0x2 - Bulk, 0x3 - Intr;
308 # 0x91 mUsbFIFOConfig FIFO1
309 # 0x92 mUsbFIFOConfig FIFO2
310 # 0x93 mUsbFIFOConfig FIFO3
311 # 0x94 mUsbFIFOConfig FIFO4
312 # 0x95 mUsbFIFOConfig FIFO5
313 # 0x96 mUsbFIFOConfig FIFO6
314 # 0x97 mUsbFIFOConfig FIFO7
315 # 0x98 mUsbFIFOConfig FIFO8
316 # 0x99 mUsbFIFOConfig FIFO9
317 # 0x9a mUsbFIFOConfig FIFO10
318 # 0x9b mUsbFIFOConfig FIFO11
319 # 0x9c mUsbFIFOConfig FIFO12
320 # 0x9d mUsbFIFOConfig FIFO13
321 # 0x9e mUsbFIFOConfig FIFO14
322 # 0x9f mUsbFIFOConfig FIFO15
324 # 0xAE ZM_EP3_BYTE_COUNT_HIGH_OFFSET
326 comments: after sending data from target to host, set BIT3
328 # 0xAF ZM_EP4_BYTE_COUNT_HIGH_OFFSET
329 BIT4 - 1 - reset fifo; 0 - disable reset?
330 comments: probably compatible with ZM_EP3_BYTE_COUNT_HIGH_OFFSET.
331 **These name reg do not fit to pattern!!!** Compare with 0x3e, 0x3f and 0x5e, 0x5f.
332 If we have 0x3e, 0x3f and 0x5e, 0x5f, why do we need this register?
334 # 0xBE ZM_EP3_BYTE_COUNT_LOW_OFFSET
335 size of data in fifo buffer? never used?
337 # 0xBF ZM_EP4_BYTE_COUNT_LOW_OFFSET
338 size of data in fifo buffer. Maximum size of EP4 should be 64 Bytes. If reported value is bigger, then buffer is defiantly corrupt.
340 # 0xF8 ZM_EP3_DATA_OFFSET
343 # 0xFC ZM_EP4_DATA_OFFSET
346 # 0x100 ZM_CBUS_FIFO_SIZE_REG
347 0x1 - 1 Byte, 0x3 - 2 Byte, 0x7 - 3 Byte; 0xf - 4 Byte.
349 **we miss 7 bytes here**
351 # 0x108 ZM_SOC_USB_MODE_CTRL_OFFSET
352 BIT10 - 1 - enable MP (EP6) downstream stream mode
353 BIT9 - 1 - enable MP (EP6) downstream DMA mode
354 BIT8 - 1 - enable HP (EP5) downstream DMA mode
355 BIT7 - 1 - enable HP (EP5) downstream stream mode
356 BIT6 - 1 - enable LP downstream stream mode
357 BIT5 - define the host dma buffer size - 4096(00) 8192 (01) 16384(10) 32768(11) bytes
359 BIT3 - 0 - enable upstream stream mode: 1 - enable upstream packed mode;
360 BIT2 - 0 - Set into 64 byte mode (full speed) 1 - Set into 512 byte mode (usb highspeed)
361 BIT1 - 0 - disable upstream dma mode; 1 - enable upstream dma mode
362 BIT0 - 0 - disable LP down stream dma mode; 1 - eanble LP down stream dma mode
364 ryan: 04/01: bit0 could disable lpdn dma, which is good at debugging while async_fifo have problem, we could disable this and check the fifo_rcv_size to see if we have correct at fifo or not
365 LP - lo priotiry; MP - middle priority; HP - High priority;
368 # 0x110 ZM_SOC_USB_MAX_AGGREGATE_OFFSET
369 set stream mode packet buffer critirea
370 0x0 = disable stream mode or 1 packet. So 0x9 is 10 packets?
371 # 0x114 ZM_SOC_USB_TIME_CTRL_OFFSET
372 set stream mode timeout critirea. the unit is 32 USB (30Mhz) clock cycles.
374 # 0x1f0 ZM_CBUS_CTRL_REG