1 Assumptions made on source code:
2 * looks like USB block is Faraday [FUSB200](http://www.faraday-tech.com/techDocument/FUSB200_ProductBrief_v1_2.pdf).
3 * We have 15 Endpoints and 15 FIFO buffers.
4 * **FIFO0 - FIFO13, 512 Byte each. FIFO14 - FIFO15 - 64 Byte each.**
5 * location of usb descriptor target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_table.c
7 # EP layout vs software/reg layout
9 * EP 1 OUT; Bulk; = LP (Low priority downstream); RX0;
10 * EP 2 IN; Bulk; = US (upstream)
12 * EP 4 OUT; Interrupt;
13 * EP 5 OUT; Bulk; = HP (High priority downstream); RX1;
14 * EP 6 OUT; Bulk; = MP (Medium priority downstream); RX2;
17 # 0x00 ZM_MAIN_CTRL_OFFSET
18 * BIT7 - Forced to be Full-Speed Mod?
19 * BIT6 - 1 = HighSpeed is set (read only?)
21 * BIT4 - Chip Software Rese
22 * BIT3 - Enter Suspend Mode
23 * BIT2 - Enable global Int
24 * BIT1 - Half speed mode for FPGA test
25 * BIT0 - Enable remote wake-up;
27 # 0x01 ZM_DEVICE_ADDRESS_OFFSET
28 * BIT7 - SET_CONFIGURATION has been executed
38 * BIT6 - Do not generate SOF
39 * BIT5 - Enter Test Mode
40 * BIT4 - Do not toggle sequence
41 * BIT3 - Do not append CRC
42 * BIT2 - Clear External Side Address
43 * BIT1 - EP0 loopback test
44 * BIT0 - 1 ?? set on usb 2.0 init. Clear FIFO
46 # 0x08 ZM_PHY_TEST_SELECT_OFFSET
50 * BIT4 - TEST_PKY - Test packed.
51 * BIT3 - TEST_SE0_NAK. High-Speed quiescent state.
52 * BIT2 - TEST_K, High-Speed K state
53 * BIT1 - TEST_J, High-Speed J state
54 * BIT0 - Enable soft-detachment
56 According to FUSB200 doc:
57 DM(D-) DP(D+) Description
62 0: Control PHY to turn off 1.5K Ohm pull-up resistor
63 1: Control PHY to turn on 1.5K Ohm pull-up resistor
64 If TEST_PKY is set, the test packet must be filled into FIFO by DMA first.
67 # 0x0A ZM_VDR_SPECIFIC_MODE_OFFSET
69 # 0x0B ZM_CX_CONFIG_STATUS_OFFSET
72 * BIT5 - CX FIFO empty
74 * BIT3 - CX FIFO clear
75 * BIT2 - set CX_STL, CX data stalled
76 * BIT1 - Test packet data transfer finished
77 * BIT0 - set CX_DONE, CX data transfer finished
79 # 0x0C ZM_EP0_DATA_OFFSET
80 * Write 32bit data to fifo
82 # 0x11 ZM_INTR_MASK_BYTE_0_OFFSET
83 Theoretically INTR_MASK_BYTE should control INTR_SOURCE. Is it correct?
85 # 0x12 ZM_INTR_MASK_BYTE_1_OFFSET
88 # 0x13 ZM_INTR_MASK_BYTE_2_OFFSET
91 # 0x14 ZM_INTR_MASK_BYTE_3_OFFSET
94 # 0x15 ZM_INTR_MASK_BYTE_4_OFFSET
96 #define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
97 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f)
98 #define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \
99 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0xc0)
101 # 0x16 ZM_INTR_MASK_BYTE_5_OFFSET
104 # 0x17 ZM_INTR_MASK_BYTE_6_OFFSET
107 #define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
108 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf)
109 #define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \
110 USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0)
112 # 0x18 ZM_INTR_MASK_BYTE_7_OFFSET
114 # 0x20 ZM_INTR_GROUP_OFFSET
115 * BIT7 - group INTR 7
116 * BIT6 - group INTR 6
117 * BIT5 - group INTR 5
118 * BIT4 - group INTR 4
119 * BIT3 - group INTR 3
120 * BIT2 - group INTR 2
121 * BIT1 - group INTR 1
122 * BIT0 - group INTR 0
123 These bits indicate if fallowing groups got some interrupt.
125 # 0x21 ZM_INTR_SOURCE_0_OFFSET
126 * BIT7 - abort interrupt? should be cleared first?
128 * BIT5 - (abort int on fotg210, may be here too?)
129 * BIT4 - ep0 CMD_FAIL (error)
131 * BIT2 - EP0-OUT packet
132 * BIT1 - EP0-IN packet
133 * BIT0 - EP0-SETUP packet
135 # 0x22 - 0x25 ZM_INTR_SOURCE_1_OFFSET (FIFOx OUT)
137 * BIT1 - FIFO0 OUT - short packet
138 * BIT0 - FIFO0 OUT - data
140 ### 0x25 ZM_INTR_SOURCE_4_OFFSET
141 * BIT7 - FIFO15 OUT - short packet.
142 * BIT6 - FIFO15 OUT - vUsb_Reg_Out(). Pending data in fifo for EP4. We need to read it out.
147 # 0x26 - 0x27 ZM_INTR_SOURCE_5_OFFSET (FIFOx IN)
151 ### 0x27 ZM_INTR_SOURCE_6_OFFSET
152 * BIT6 - FIFO14 IN - vUsb_Status_In()
154 # 0x28 ZM_INTR_SOURCE_7_OFFSET
155 * BIT11 - device wake up
156 * BIT10 - device idle
158 * BIT8 - DMA finnished
159 * BIT7 - RX0BTYE_INT - Zero-Length-Packet Rx
160 * BIT6 - TX0BTYE_INT - Zero-Length-Packet Tx
161 * BIT5 - ISO seq abort
162 * BIT4 - ISO seq error
165 * BIT1 - USB reset interrupt.
167 comment: not matching layout with fotg210.. some thing wrong?
170 code use: ZM_FUSB_BASE+0x30+(EPn-1)
171 (0x0F | FIFOn << 4) = OUT
173 **probably incorrect interpretation. It should be FUSB_REG_IDLE_CNT
174 set suspend delay in ms**
176 for FIFOn see mUsbFIFOMap registers.
178 Current configuration:
180 * 0x30 0x0f <- EP1 = OUT + Start FIFO0
181 * 0x31 0xf2 <- EP2 = IN + Start FIFO2
182 * 0x32 0xfe <- EP3 = IN + Start FIFO14
183 * 0x33 0xff <- EP4 = OUT + Start FIFO15
204 # 0x39 mUsbEPMap EP10
205 # 0x3a mUsbEPMap EP11
206 # 0x3b mUsbEPMap EP12
207 # 0x3c mUsbEPMap EP13
208 # 0x3d mUsbEPMap EP14
210 # 0x3E ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP0
211 * BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_IN_MAX_SIZE_LOW_OFFSET + ZM_EP_IN_MAX_SIZE_HIGH_OFFSET)
213 Current configuration:
232 # 0x3F ZM_EP_IN_MAX_SIZE_HIGH_OFFSET EP0
236 * BIT4 - mUsbEPinRsTgSet
237 * BIT3 - mUsbEPinStallSet
238 * BIT0 - BIT2; High size regs
239 These offset + 2 Byte step for each endpoint.
240 For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
259 # 0x40 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP1
260 # 0x42 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP2
261 # 0x44 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP3
262 # 0x46 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP4
263 # 0x48 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP5
264 # 0x4A ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP6
265 # 0x4C ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP7
266 # 0x4E ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP8
267 # 0x50 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP9
268 # 0x52 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP10
269 # 0x54 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP11
270 # 0x56 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP12
271 # 0x58 ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP13
272 # 0x5A ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP14
273 # 0x5C ZM_EP_IN_MAX_SIZE_LOW_OFFSET EP15
275 # 0x5E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP0
276 * BIT0 - BIT7; low size regs. Max size 0x7ff (ZM_EP_OUT_MAX_SIZE_LOW_OFFSET + ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET)
278 # 0x5F ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET EP0
282 * BIT4 - mUsbEPoutRsTgSet
283 * BIT3 - mUsbEPoutStallSet
284 * BIT0 - BIT2; High size regs
286 These offset + 2 Byte step for each endpoint.
287 For example EP0 = +0x00; EP1 = +0x02; or offset+(EPn << 1). In these address space will fit 15 endpoints.
289 # 0x60 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP1
290 # 0x62 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP2
291 # 0x64 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP3
292 # 0x66 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP4
293 # 0x68 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP5
294 # 0x6A ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP6
295 # 0x6C ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP7
296 # 0x6E ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP8
297 # 0x70 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP9
298 # 0x72 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP10
299 # 0x74 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP11
300 # 0x76 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP12
301 # 0x78 ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP13
302 # 0x7A ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP14
303 # 0x7C ZM_EP_OUT_MAX_SIZE_LOW_OFFSET EP15
305 # 0x80 mUsbFIFOMap FIFO0
309 * BIT4 - Direction: 0 - OUT; 1 - IN.
310 * BIT0 - BIT3: assigned EP number.
313 * 0x80 0x01 - EP1 OUT
314 * 0x81 0x01 - EP1 OUT
330 # 0x81 mUsbFIFOMap FIFO1
331 # 0x82 mUsbFIFOMap FIFO2
332 # 0x83 mUsbFIFOMap FIFO3
333 # 0x84 mUsbFIFOMap FIFO4
334 # 0x85 mUsbFIFOMap FIFO5
335 # 0x86 mUsbFIFOMap FIFO6
336 # 0x87 mUsbFIFOMap FIFO7
337 # 0x88 mUsbFIFOMap FIFO8
338 # 0x89 mUsbFIFOMap FIFO9
339 # 0x8a mUsbFIFOMap FIFO10
340 # 0x8b mUsbFIFOMap FIFO11
341 # 0x8c mUsbFIFOMap FIFO12
342 # 0x8d mUsbFIFOMap FIFO13
343 # 0x8e mUsbFIFOMap FIFO14
344 # 0x8f mUsbFIFOMap FIFO15
346 # 0x90 mUsbFIFOConfig FIFO0
347 * BIT7 - If EPn use more then one FIFO, then this bit should be on the first
350 * BIT4 - Block size: 0 - 64/512; 1 - 128/1024. It depends on initial FIFO size.
351 * BIT2 - BIT3; number of FIFO blocks or better to say extra blocks? 0 - no more blocks; 1 - one block; 2 - two blocks.
352 * BIT0 - BIT1; EP type: 0x1 - Iso; 0x2 - Bulk, 0x3 - Intr;
354 * 0x90 0x86 <- FIFO0: Bulk | + one block (0x91) | size 512
371 # 0x91 mUsbFIFOConfig FIFO1
372 # 0x92 mUsbFIFOConfig FIFO2
373 # 0x93 mUsbFIFOConfig FIFO3
374 # 0x94 mUsbFIFOConfig FIFO4
375 # 0x95 mUsbFIFOConfig FIFO5
376 # 0x96 mUsbFIFOConfig FIFO6
377 # 0x97 mUsbFIFOConfig FIFO7
378 # 0x98 mUsbFIFOConfig FIFO8
379 # 0x99 mUsbFIFOConfig FIFO9
380 # 0x9a mUsbFIFOConfig FIFO10
381 # 0x9b mUsbFIFOConfig FIFO11
382 # 0x9c mUsbFIFOConfig FIFO12
383 # 0x9d mUsbFIFOConfig FIFO13
384 # 0x9e mUsbFIFOConfig FIFO14
385 # 0x9f mUsbFIFOConfig FIFO15
387 # 0xa0 FUSB_REG_FIFO0_INS
388 * BIT0 - BIT2 - high offset of byte count in fifo.
390 # 0xa1 FUSB_REG_FIFO1_INS
391 # 0xa2 FUSB_REG_FIFO2_INS
392 # 0xa3 FUSB_REG_FIFO3_INS
393 # 0xa4 FUSB_REG_FIFO4_INS
394 # 0xa5 FUSB_REG_FIFO5_INS
395 # 0xa6 FUSB_REG_FIFO6_INS
396 # 0xa7 FUSB_REG_FIFO7_INS
397 # 0xa8 FUSB_REG_FIFO8_INS
398 # 0xa9 FUSB_REG_FIFO9_INS
399 # 0xaa FUSB_REG_FIFO10_INS
400 # 0xab FUSB_REG_FIFO11_INS
401 # 0xac FUSB_REG_FIFO12_INS
402 # 0xad FUSB_REG_FIFO13_INS
403 # 0xae FUSB_REG_FIFO14_INS
404 or known as ZM_EP3_BYTE_COUNT_HIGH_OFFSET
406 comments: after sending data from target to host, set BIT3
408 # 0xaf FUSB_REG_FIFO15_INS
409 or known ZM_EP4_BYTE_COUNT_HIGH_OFFSET
410 BIT4 - 1 - reset fifo; 0 - disable reset?
411 comments: probably compatible with ZM_EP3_BYTE_COUNT_HIGH_OFFSET.
412 **These name reg do not fit to pattern!!!** Compare with 0x3e, 0x3f and 0x5e, 0x5f.
413 If we have 0x3e, 0x3f and 0x5e, 0x5f, why do we need this register?
415 # 0xb0 FUSB_REG_FIFO0_BCNT
416 # 0xb1 FUSB_REG_FIFO1_BCNT
417 # 0xb2 FUSB_REG_FIFO2_BCNT
418 # 0xb3 FUSB_REG_FIFO3_BCNT
419 # 0xb4 FUSB_REG_FIFO4_BCNT
420 # 0xb5 FUSB_REG_FIFO5_BCNT
421 # 0xb6 FUSB_REG_FIFO6_BCNT
422 # 0xb7 FUSB_REG_FIFO7_BCNT
423 # 0xb8 FUSB_REG_FIFO8_BCNT
424 # 0xb9 FUSB_REG_FIFO9_BCNT
425 # 0xba FUSB_REG_FIFO10_BCNT
426 # 0xbb FUSB_REG_FIFO11_BCNT
427 # 0xbc FUSB_REG_FIFO12_BCNT
428 # 0xbd FUSB_REG_FIFO13_BCNT
429 # 0xbe FUSB_REG_FIFO14_BCNT
430 or known as ZM_EP3_BYTE_COUNT_LOW_OFFSET
431 size of data in fifo buffer? never used?
433 # 0xbf FUSB_REG_FIFO15_BCNT
434 or known as ZM_EP4_BYTE_COUNT_LOW_OFFSET
435 size of data in fifo buffer. Maximum size of EP4 should be 64 Bytes. If reported value is bigger, then buffer is defiantly corrupt.
437 # 0xc0 FIFO0 DATA OFFSET?
438 or known as FUSB_REG_FIFO0_DP
440 # 0xc4 FIFO1 DATA OFFSET?
441 # 0xc8 FIFO2 DATA OFFSET?
442 # 0xcc FIFO3 DATA OFFSET?
443 # 0xd0 FIFO4 DATA OFFSET?
444 # 0xd4 FIFO5 DATA OFFSET?
445 # 0xd8 FIFO6 DATA OFFSET?
446 # 0xdc FIFO7 DATA OFFSET?
447 # 0xe0 FIFO8 DATA OFFSET?
448 # 0xe4 FIFO9 DATA OFFSET?
449 # 0xe8 FIFO10 DATA OFFSET?
450 # 0xec FIFO11 DATA OFFSET?
451 # 0xf0 FIFO12 DATA OFFSET?
452 # 0xf4 FIFO13 DATA OFFSET?
453 # 0xf8 FIFO14 DATA OFFSET?
454 # 0xfc FIFO15 DATA OFFSET?
456 # 0xF8 ZM_EP3_DATA_OFFSET
457 32bit data. Probably FIFO14 offset.. not EP
459 # 0xFC ZM_EP4_DATA_OFFSET
460 32bit data. Probably FIFO15 offset.. not EP
462 # 0x100 ZM_CBUS_FIFO_SIZE_REG
463 0x1 - 1 Byte, 0x3 - 2 Byte, 0x7 - 3 Byte; 0xf - 4 Byte.
465 **we miss 7 bytes here**
467 # 0x108 ZM_SOC_USB_MODE_CTRL_OFFSET
468 BIT10 - 1 - enable MP (EP6) downstream stream mode
469 BIT9 - 1 - enable MP (EP6) downstream DMA mode
470 BIT8 - 1 - enable HP (EP5) downstream DMA mode
471 BIT7 - 1 - enable HP (EP5) downstream stream mode
472 BIT6 - 1 - enable LP downstream stream mode
473 BIT5 - define the host dma buffer size - 4096(00) 8192 (01) 16384(10) 32768(11) bytes
475 BIT3 - 0 - enable upstream stream mode: 1 - enable upstream packed mode;
476 BIT2 - 0 - Set into 64 byte mode (full speed) 1 - Set into 512 byte mode (usb highspeed)
477 BIT1 - 0 - disable upstream dma mode; 1 - enable upstream dma mode
478 BIT0 - 0 - disable LP down stream dma mode; 1 - eanble LP down stream dma mode
480 ryan: 04/01: bit0 could disable lpdn dma, which is good at debugging while async_fifo have problem, we could disable this and check the fifo_rcv_size to see if we have correct at fifo or not
481 LP - lo priotiry; MP - middle priority; HP - High priority;
484 # 0x110 ZM_SOC_USB_MAX_AGGREGATE_OFFSET
485 set stream mode packet buffer critirea
486 0x0 = disable stream mode or 1 packet. So 0x9 is 10 packets?
487 # 0x114 ZM_SOC_USB_TIME_CTRL_OFFSET
488 set stream mode timeout critirea. the unit is 32 USB (30Mhz) clock cycles.
490 # 0x118 ZM_SOC_USB_DMA_RESET_OFFSET
491 BIT0 - reset usb dma.
493 # 0x1f0 ZM_CBUS_CTRL_REG