u-boot/include/configs/db12x.h

   1 /*
   2  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   3  *
   4  * This file contains the configuration parameters
   5  * for Qualcomm Atheros AR934x based devices
   6  *
   7  * Reference designs: AP123, MI124, DB120
   8  *
   9  * SPDX-License-Identifier: GPL-2.0
  10  */
  11
  12 #ifndef _DB12X_H
  13 #define _DB12X_H
  14
  15 #include <config.h>
  16 #include <configs/qca9k_common.h>
  17 #include <soc/soc_common.h>
  18
  19 /*
  20  * ==================
  21  * GPIO configuration
  22  * ==================
  23  */
  24 #if defined(CONFIG_FOR_ENGENIUS_ENS202EXT)
  25
  26         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0  | GPIO14 | GPIO16 |\
  27                                                 GPIO17 | GPIO18
  28
  29 #elif defined(CONFIG_FOR_GLINET_GL_AR300)
  30
  31         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13 | GPIO14
  32
  33 #elif defined(CONFIG_FOR_TPLINK_MR3420_V2)
  34
  35         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13 |\
  36                                                 GPIO14 | GPIO15 | GPIO18 |\
  37                                                 GPIO19 | GPIO20 | GPIO21
  38         #define CONFIG_QCA_GPIO_MASK_IN         GPIO16
  39         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO4
  40
  41 #elif defined(CONFIG_FOR_TPLINK_WA801ND_V2) ||\
  42       defined(CONFIG_FOR_TPLINK_WA830RE_V2)
  43
  44         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13 | GPIO14 | GPIO15 |\
  45                                                 GPIO18
  46         #define CONFIG_QCA_GPIO_MASK_IN         GPIO16
  47
  48 #elif defined(CONFIG_FOR_TPLINK_WDR3500_V1)
  49
  50         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO13 | GPIO14 |\
  51                                                 GPIO15 | GPIO18 | GPIO19 |\
  52                                                 GPIO20 | GPIO21 | GPIO22
  53         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
  54         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO12
  55
  56 #elif defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
  57       defined(CONFIG_FOR_TPLINK_WDR43X0_V1)
  58
  59         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13 |\
  60                                                 GPIO14 | GPIO15
  61         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
  62         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO21 | GPIO22
  63
  64 #elif defined(CONFIG_FOR_TPLINK_WR1041N_V2)
  65
  66         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13
  67
  68 #elif defined(CONFIG_FOR_TPLINK_WR841N_V8)
  69
  70         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO12 | GPIO13 | GPIO14 |\
  71                                                 GPIO15 | GPIO18 | GPIO19 |\
  72                                                 GPIO20 | GPIO21
  73         #define CONFIG_QCA_GPIO_MASK_IN         GPIO16
  74
  75 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
  76
  77         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0 | GPIO1  | GPIO2  |\
  78                                                 GPIO3 | GPIO13 | GPIO19 |\
  79                                                 GPIO20
  80
  81 #endif
  82
  83 /*
  84  * ================
  85  * Default bootargs
  86  * ================
  87  */
  88 #if defined(CONFIG_FOR_ENGENIUS_ENS202EXT)
  89
  90         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:04 "\
  91                                 "rootfstype=squashfs init=/etc/preinit "\
  92                                 "mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),320k(custom),1536k(kernel),12096k(rootfs),2048k(failsafe),64k(art)ro"
  93
  94 #elif defined(CONFIG_FOR_GLINET_GL_AR300)
  95
  96         #define CONFIG_BOOTARGS "console=ttyATH0,115200 root=31:02 "\
  97                                 "rootfstype=squashfs init=/sbin/init "\
  98                                 "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(art)ro"
  99
 100 #elif defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\
 101       defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
 102       defined(CONFIG_FOR_TPLINK_WDR43X0_V1)
 103
 104         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 105                                 "rootfstype=squashfs init=/sbin/init "\
 106                                 "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(art)"
 107
 108 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
 109
 110         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 111                                 "rootfstype=squashfs,jffs2 init=/sbin/init "\
 112                                 "mtdparts=ath-nor0:64k(u-boot),64k(u-boot-env),6528k(rootfs),1408K(uImage)"\
 113                                 ",7936k@0x20000(firmware),64k(NVRAM),64k(ART),8128k@0x00000(firmware2)"
 114
 115 #else
 116
 117         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 118                                 "rootfstype=squashfs init=/sbin/init "\
 119                                 "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 120
 121 #endif
 122
 123 /*
 124  * =============================
 125  * Load address and boot command
 126  * =============================
 127  */
 128 #if defined(CONFIG_FOR_ENGENIUS_ENS202EXT)
 129
 130         #define CFG_LOAD_ADDR           0x9F0A0000
 131
 132 #elif defined(CONFIG_FOR_GLINET_GL_AR300)
 133
 134         #define CFG_LOAD_ADDR           0x9F050000
 135
 136 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
 137
 138         #define CFG_LOAD_ADDR           0x9F680000
 139
 140 #else
 141
 142         #define CFG_LOAD_ADDR           0x9F020000
 143
 144 #endif
 145
 146 #define CONFIG_BOOTCOMMAND      "bootm " MK_STR(CFG_LOAD_ADDR)
 147
 148 /*
 149  * =========================
 150  * Environment configuration
 151  * =========================
 152  */
 153 #if defined(CONFIG_FOR_ENGENIUS_ENS202EXT)
 154
 155         #define CFG_ENV_ADDR            0x9F040000
 156         #define CFG_ENV_SIZE            0x10000
 157         #define CFG_ENV_SECT_SIZE       0x10000
 158
 159 #elif defined(CONFIG_FOR_GLINET_GL_AR300)
 160
 161         #define CFG_ENV_ADDR            0x9F040000
 162         #define CFG_ENV_SIZE            0xFC00
 163         #define CFG_ENV_SECT_SIZE       0x10000
 164
 165 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
 166
 167         #define CFG_ENV_ADDR            0x9F020000
 168         #define CFG_ENV_SIZE            0xFC00
 169         #define CFG_ENV_SECT_SIZE       0x10000
 170
 171 #else
 172
 173         #define CFG_ENV_ADDR            0x9F01EC00
 174         #define CFG_ENV_SIZE            0x1000
 175         #define CFG_ENV_SECT_SIZE       0x10000
 176
 177 #endif
 178
 179 /*
 180  * ===========================
 181  * List of available baudrates
 182  * ===========================
 183  */
 184 #define CFG_BAUDRATE_TABLE      \
 185                 { 600,    1200,   2400,    4800,    9600,    14400, \
 186                   19200,  28800,  38400,   56000,   57600,   115200 }
 187
 188 /*
 189  * ==================================================
 190  * MAC address/es, model and WPS pin offsets in FLASH
 191  * ==================================================
 192  */
 193 #if defined(CONFIG_FOR_GLINET_GL_AR300) ||\
 194     defined(CONFIG_FOR_YUNCORE_CPE870)
 195
 196         #define OFFSET_MAC_DATA_BLOCK           0xFF0000
 197         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 198         #define OFFSET_MAC_ADDRESS              0x000000
 199
 200 #else
 201
 202         #define OFFSET_MAC_DATA_BLOCK           0x010000
 203         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 204         #define OFFSET_MAC_ADDRESS              0x00FC00
 205         #define OFFSET_ROUTER_MODEL             0x00FD00
 206         #define OFFSET_PIN_NUMBER               0x00FE00
 207
 208 #endif
 209
 210 /*
 211  * =========================
 212  * Custom changes per device
 213  * =========================
 214  */
 215
 216 /*
 217  * YunCore CPE870 is limited to 64 KB only,
 218  * disable some commands
 219  */
 220 #if defined(CONFIG_FOR_YUNCORE_CPE870)
 221
 222         #undef CONFIG_CMD_DHCP
 223         #undef CONFIG_CMD_IMI
 224         #undef CONFIG_CMD_LOADB
 225         #undef CONFIG_CMD_MAC
 226         #undef CONFIG_CMD_SNTP
 227         #undef CONFIG_UPG_SCRIPTS_FW
 228         #undef CONFIG_UPG_SCRIPTS_UBOOT
 229
 230 #endif
 231
 232 /*
 233  * ===========================
 234  * HTTP recovery configuration
 235  * ===========================
 236  */
 237 #if defined(CONFIG_FOR_YUNCORE_CPE870)
 238
 239         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_FLASH_BASE + 0x20000
 240
 241 #else
 242
 243         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_LOAD_ADDR
 244
 245 #endif
 246
 247 /* Firmware size limit */
 248 #if defined(CONFIG_FOR_ENGENIUS_ENS202EXT)
 249
 250         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (2752 * 1024)
 251
 252 #elif defined(CONFIG_FOR_GLINET_GL_AR300)
 253
 254         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
 255
 256 #elif defined(CONFIG_FOR_YUNCORE_CPE870)
 257
 258         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (256 * 1024)
 259
 260 #else
 261
 262         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 263
 264 #endif
 265
 266 /*
 267  * ========================
 268  * PLL/Clocks configuration
 269  * ========================
 270  */
 271 #define CONFIG_QCA_PLL  QCA_PLL_PRESET_550_400_200
 272
 273 #if defined(CONFIG_FOR_GLINET_GL_AR300)
 274
 275         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x40000
 276         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 277
 278 #elif defined(CONFIG_FOR_TPLINK_MR3420_V2)  ||\
 279       defined(CONFIG_FOR_TPLINK_WA801ND_V2) ||\
 280       defined(CONFIG_FOR_TPLINK_WA830RE_V2) ||\
 281       defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\
 282       defined(CONFIG_FOR_TPLINK_WDR3600_V1) ||\
 283       defined(CONFIG_FOR_TPLINK_WDR43X0_V1) ||\
 284       defined(CONFIG_FOR_TPLINK_WR1041N_V2) ||\
 285       defined(CONFIG_FOR_TPLINK_WR841N_V8)  ||\
 286       defined(CONFIG_FOR_YUNCORE_CPE870)
 287
 288         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x10000
 289         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 290
 291 #endif
 292
 293 /*
 294  * ==================================
 295  * For upgrade scripts in environment
 296  * ==================================
 297  */
 298 #if !defined(CONFIG_FOR_ENGENIUS_ENS202EXT) &&\
 299     !defined(CONFIG_FOR_GLINET_GL_AR300)    &&\
 300     !defined(CONFIG_FOR_YUNCORE_CPE870)
 301
 302         #define CONFIG_UPG_UBOOT_SIZE_BACKUP_HEX        0x20000
 303
 304 #endif
 305
 306 #if defined(CONFIG_FOR_YUNCORE_CPE870)
 307
 308         #define CONFIG_UPG_SCRIPTS_FW_ADDR_HEX  0x9F020000
 309
 310 #endif
 311
 312 /*
 313  * ===================
 314  * Other configuration
 315  * ===================
 316  */
 317
 318 /* Cache lock for stack */
 319 #define CONFIG_INIT_SRAM_SP_OFFSET      0xbd007000
 320
 321 #endif /* _DB12X_H */