u-boot/include/configs/ap143.h

   1 /*
   2  * This file contains the configuration parameters for the DB12x (AR9344) board.
   3  */
   4
   5 #ifndef _AP143_CONFIG_H
   6 #define _AP143_CONFIG_H
   7
   8 #include <config.h>
   9 #include <soc/soc_common.h>
  10
  11 /*
  12  * GPIO configuration
  13  */
  14 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
  15         defined(CONFIG_FOR_TPLINK_WR802N)
  16         /* LEDs */
  17         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             GPIO13
  18
  19         /* Outputs, inputs */
  20         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  21         #define CONFIG_QCA_GPIO_MASK_INPUTS                             GPIO12
  22
  23         /* Initial states */
  24         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  25
  26 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9)
  27         /* LEDs */
  28         #define CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO             (GPIO3 | GPIO4  | GPIO11 | GPIO13 |\
  29                                                                                                         GPIO14 | GPIO15 | GPIO16)
  30
  31         /* Outputs, inputs */
  32         #define CONFIG_QCA_GPIO_MASK_OUTPUTS                    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  33         #define CONFIG_QCA_GPIO_MASK_INPUTS                             (GPIO12 | GPIO17)
  34
  35         /* Initial states */
  36         #define CONFIG_QCA_GPIO_MASK_OUTPUTS_INIT_HI    CONFIG_QCA_GPIO_MASK_LEDS_ACTIVE_LO
  37
  38 #endif
  39
  40 /*
  41  * Miscellaneous configurable options
  42  */
  43 #ifndef CONFIG_BOOTDELAY
  44         #define CONFIG_BOOTDELAY        1
  45 #endif
  46
  47 #define CFG_LONGHELP
  48
  49 #define CONFIG_BAUDRATE                         115200
  50 #define CFG_BAUDRATE_TABLE                      { 600,    1200,   2400,    4800,    9600,    14400, \
  51                                                                           19200,  28800,  38400,   56000,   57600,   115200 }
  52
  53 #define CFG_ALT_MEMTEST
  54 #define CFG_HUSH_PARSER
  55 #define CFG_LONGHELP                                                                                                            /* undef to save memory      */
  56 #define CFG_PROMPT                      "uboot> "                                                                               /* Monitor Command Prompt    */
  57 #define CFG_PROMPT_HUSH_PS2     "> "
  58 #define CFG_CBSIZE                      1024                                                                                    /* Console I/O Buffer Size   */
  59 #define CFG_PBSIZE                      (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)                              /* Print Buffer Size, was: def + 16 */
  60 #define CFG_MAXARGS                     16                                                                                              /* max number of command */
  61 #define CFG_MALLOC_LEN          512*1024                                                                                /* def: 128*1024 */
  62 #define CFG_BOOTPARAMS_LEN      512*1024                                                                                /* def: 128 */
  63 #define CFG_SDRAM_BASE          0x80000000                                                                              /* Cached addr */
  64 #define CFG_MEMTEST_START       (CFG_SDRAM_BASE + 0x200000)                                             /* RAM test start = CFG_SDRAM_BASE + 2 MB */
  65 #define CFG_MEMTEST_END         (CFG_SDRAM_BASE + bd->bi_memsize - 0x200001)    /* RAM test end   = CFG_SDRAM_BASE + RAM size - 2 MB - 1 Byte */
  66 #define CFG_RX_ETH_BUFFER   16
  67
  68 #if defined(CONFIG_SILENT_CONSOLE)
  69         #define SILENT_ENV_VARIABLE     "silent=1\0"
  70 #else
  71         #define SILENT_ENV_VARIABLE     ""
  72 #endif
  73
  74 #define CFG_DCACHE_SIZE         32768
  75 #define CFG_ICACHE_SIZE         65536
  76 #define CFG_CACHELINE_SIZE      32
  77
  78 /*
  79  * FLASH and environment organization
  80  */
  81 #define CFG_MAX_FLASH_BANKS                     1
  82 #define CFG_MAX_FLASH_SECT                      4096    // 4 KB sectors in 16 MB flash
  83 #define CFG_FLASH_SECTOR_SIZE           64 * 1024
  84
  85 /*
  86  * We boot from this flash
  87  */
  88 #define CFG_FLASH_BASE                                  0x9F000000
  89 #ifdef COMPRESSED_UBOOT
  90         #define BOOTSTRAP_TEXT_BASE                     CFG_FLASH_BASE
  91         #define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE
  92 #endif
  93
  94 /*
  95  * The following #defines are needed to get flash environment right
  96  */
  97 #define CFG_MONITOR_BASE        TEXT_BASE
  98 #define CFG_MONITOR_LEN         (192 << 10)
  99
 100 /*
 101  * Default bootargs
 102  */
 103 #undef CONFIG_BOOTARGS
 104 #if defined(CONFIG_FOR_TPLINK_WR820N_CN)
 105         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)"
 106 #elif defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
 107           defined(CONFIG_FOR_TPLINK_WR802N)
 108         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 109 #endif
 110
 111 /*
 112  * Other env default values
 113  */
 114 #undef CONFIG_BOOTFILE
 115 #define CONFIG_BOOTFILE                 "firmware.bin"
 116
 117 #undef CONFIG_LOADADDR
 118 #define CONFIG_LOADADDR                 0x80800000
 119
 120 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 121         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 122         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 123         #define CFG_LOAD_ADDR                    0x9F020000
 124         #define UPDATE_SCRIPT_FW_ADDR   "0x9F020000"
 125         #define CONFIG_BOOTCOMMAND              "bootm 0x9F020000"
 126 #endif
 127
 128 #define CONFIG_IPADDR                   192.168.1.1
 129 #define CONFIG_SERVERIP                 192.168.1.2
 130
 131 /*
 132  * PLL/Clocks configuration
 133  */
 134 #ifdef CFG_HZ
 135         #undef  CFG_HZ
 136 #endif
 137 #define CFG_HZ  bd->bi_cfg_hz
 138
 139 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 140         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 141         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 142         #define CONFIG_QCA_PLL          QCA_PLL_PRESET_550_400_200
 143 #endif
 144
 145 /*
 146  * For PLL/clocks recovery use reset button by default
 147  */
 148 #ifdef CONFIG_GPIO_RESET_BTN
 149         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN         CONFIG_GPIO_RESET_BTN
 150 #endif
 151
 152 #ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW
 153         #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW      1
 154 #endif
 155
 156 /*
 157  * Address and size of Primary Environment Sector
 158  */
 159 #define CFG_ENV_IS_IN_FLASH     1
 160 #undef  CFG_ENV_IS_NOWHERE
 161
 162 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 163         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 164         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 165         #define CFG_ENV_ADDR            0x9F01EC00
 166         #define CFG_ENV_SIZE            0x1000
 167         #define CFG_ENV_SECT_SIZE       0x10000
 168 #endif
 169
 170 /*
 171  * Available commands
 172  */
 173 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 174         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 175         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 176         #define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
 177                                                          CFG_CMD_DHCP   | \
 178                                                          CFG_CMD_PING   | \
 179                                                          CFG_CMD_FLASH  | \
 180                                                          CFG_CMD_NET    | \
 181                                                          CFG_CMD_RUN    | \
 182                                                          CFG_CMD_DATE   | \
 183                                                          CFG_CMD_SNTP   | \
 184                                                          CFG_CMD_ECHO   | \
 185                                                          CFG_CMD_BOOTD  | \
 186                                                          CFG_CMD_ITEST  | \
 187                                                          CFG_CMD_ENV    | \
 188                                                          CFG_CMD_LOADB)
 189 #endif
 190
 191 // Enable NetConsole and custom NetConsole port
 192 #define CONFIG_NETCONSOLE
 193 #define CONFIG_NETCONSOLE_PORT  6666
 194
 195 /*
 196  * Web Failsafe configuration
 197  */
 198 #define WEBFAILSAFE_UPLOAD_RAM_ADDRESS                          CONFIG_LOADADDR
 199 #define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS                        CFG_FLASH_BASE
 200
 201 // Firmware partition offset
 202 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 203         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 204         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 205         #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS               WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
 206 #endif
 207
 208 // U-Boot partition size
 209 #define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES          (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
 210
 211 // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
 212 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 213         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 214         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 215         #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES                       "0x1EC00"
 216         #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES        "0x20000"
 217 #endif
 218
 219 // ART partition size
 220 #define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES            (64 * 1024)
 221
 222 // max. firmware size <= (FLASH_SIZE -  WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
 223 // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
 224 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 225         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 226         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 227         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 228 #endif
 229
 230 // progress state info
 231 #define WEBFAILSAFE_PROGRESS_START                              0
 232 #define WEBFAILSAFE_PROGRESS_TIMEOUT                    1
 233 #define WEBFAILSAFE_PROGRESS_UPLOAD_READY               2
 234 #define WEBFAILSAFE_PROGRESS_UPGRADE_READY              3
 235 #define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED             4
 236
 237 // update type
 238 #define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE               0
 239 #define WEBFAILSAFE_UPGRADE_TYPE_UBOOT                  1
 240 #define WEBFAILSAFE_UPGRADE_TYPE_ART                    2
 241
 242 /*-----------------------------------------------------------------------*/
 243
 244 /*
 245  * Additional environment variables for simple upgrades
 246  */
 247 #define CONFIG_EXTRA_ENV_SETTINGS       "uboot_addr=0x9F000000\0" \
 248                                                                         "uboot_name=uboot.bin\0" \
 249                                                                         "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \
 250                                                                         "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \
 251                                                                         "uboot_upg=" \
 252                                                                                 "if ping $serverip; then " \
 253                                                                                         "mw.b $loadaddr 0xFF $uboot_backup_size && " \
 254                                                                                         "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \
 255                                                                                         "tftp $loadaddr $uboot_name && " \
 256                                                                                         "if itest.l $filesize <= $uboot_size; then " \
 257                                                                                                 "erase $uboot_addr +$uboot_backup_size && " \
 258                                                                                                 "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \
 259                                                                                                 "echo OK!; " \
 260                                                                                         "else " \
 261                                                                                                 "echo ERROR! Wrong file size!; " \
 262                                                                                         "fi; " \
 263                                                                                 "else " \
 264                                                                                         "echo ERROR! Server not reachable!; " \
 265                                                                                 "fi\0" \
 266                                                                         SILENT_ENV_VARIABLE
 267
 268 /*
 269  * Cache lock for stack
 270  */
 271 #define CFG_INIT_SP_OFFSET                      0x1000
 272 #define CONFIG_INIT_SRAM_SP_OFFSET      0xbd001800
 273
 274 /* For Merlin, both PCI, PCI-E interfaces are valid */
 275 #define ATH_ART_PCICFG_OFFSET           12
 276 /* use eth1(LAN) as the net interface */
 277 #define CONFIG_AG7240_SPEPHY
 278 #define CONFIG_NET_MULTI
 279 #define CONFIG_PCI 1
 280 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 281         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 282         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 283         #define WLANCAL                                 0x9fff1000
 284         #define BOARDCAL                                0x9fff0000
 285 #endif
 286 #define CFG_MII0_RMII                           1
 287 #define CFG_BOOTM_LEN                           (16 << 20) /* 16 MB */
 288
 289 #undef DEBUG
 290
 291 /* MAC address, model and PIN number offsets in FLASH */
 292 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 293         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 294         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 295         #define OFFSET_MAC_DATA_BLOCK                   0x010000
 296         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 297         #define OFFSET_MAC_ADDRESS                              0x00FC00
 298         #define OFFSET_ROUTER_MODEL                             0x00FD00
 299         #define OFFSET_PIN_NUMBER                               0x00FE00
 300 #endif
 301
 302 /*
 303  * PLL and clocks configurations from FLASH
 304  */
 305 #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
 306         defined(CONFIG_FOR_TPLINK_WR802N)    ||\
 307         defined(CONFIG_FOR_TPLINK_WR841N_V9)
 308         /*
 309          * All TP-Link routers have a lot of unused space
 310          * in FLASH, in second 64 KiB block.
 311          * We will store there PLL and CLOCK
 312          * registers configuration.
 313          */
 314         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x00010000
 315         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE              0x00010000
 316
 317 #endif
 318
 319 #if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET)
 320         /* Use last 32 bytes */
 321         #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET    (CFG_FLASH_BASE + \
 322                                                                                                          CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \
 323                                                                                                          0x0000FFE0)
 324 #endif
 325
 326 #include <cmd_confdefs.h>
 327
 328 #endif  /* __AP143_CONFIG_H */