u-boot/include/configs/ap143.h

   1 /*
   2  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   3  *
   4  * This file contains the configuration parameters
   5  * for Qualcomm Atheros QCA953x based devices
   6  *
   7  * Reference designs: AP143
   8  *
   9  * SPDX-License-Identifier: GPL-2.0
  10  */
  11
  12 #ifndef _AP143_H
  13 #define _AP143_H
  14
  15 #include <config.h>
  16 #include <configs/qca9k_common.h>
  17 #include <soc/soc_common.h>
  18
  19 /*
  20  * ==================
  21  * GPIO configuration
  22  * ==================
  23  */
  24 #if defined(CONFIG_FOR_COMFAST_CF_E314N)
  25
  26         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO4  | GPIO11 | GPIO14 |\
  27                                                 GPIO15 | GPIO16
  28         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0 | GPIO2 | GPIO3
  29
  30 #elif defined(CONFIG_FOR_COMFAST_CF_E320N_V2)
  31
  32         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0 | GPIO2 | GPIO3
  33         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11 | GPIO12 | GPIO14 |\
  34                                                 GPIO16
  35
  36 #elif defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
  37       defined(CONFIG_FOR_COMFAST_CF_E530N)
  38
  39         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11
  40
  41 #elif defined(CONFIG_FOR_GLINET_GL_AR750)
  42
  43         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13 | GPIO14
  44         #define CONFIG_QCA_GPIO_MASK_IN         GPIO0 | GPIO16 | GPIO17
  45         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO2
  46         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L GPIO12
  47
  48 #elif defined(CONFIG_FOR_P2W_CPE505N)
  49
  50         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO4  | GPIO11 | GPIO12 |\
  51                                                 GPIO14 | GPIO15
  52
  53 #elif defined(CONFIG_FOR_P2W_R602N)
  54
  55         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO4  | GPIO11 | GPIO12 |\
  56                                                 GPIO14 | GPIO15 | GPIO16
  57
  58 #elif defined(CONFIG_FOR_TPLINK_MR22U_V1)
  59
  60         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13
  61         #define CONFIG_QCA_GPIO_MASK_IN         GPIO14 | GPIO16
  62         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO11
  63
  64 #elif defined(CONFIG_FOR_TPLINK_MR3420_V3)
  65
  66         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO1  | GPIO3  | GPIO4  |\
  67                                                 GPIO11 | GPIO13 | GPIO14 |\
  68                                                 GPIO15 | GPIO16
  69         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
  70
  71 #elif defined(CONFIG_FOR_TPLINK_MR6400_V1V2)
  72
  73         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0  | GPIO1 | GPIO3 |\
  74                                                 GPIO11 | GPIO16
  75         #define CONFIG_QCA_GPIO_MASK_IN         GPIO14
  76         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO4 | GPIO13
  77
  78 #elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
  79
  80         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0  | GPIO1 | GPIO2  |\
  81                                                 GPIO3  | GPIO4 | GPIO12 |\
  82                                                 GPIO13 | GPIO14
  83         #define CONFIG_QCA_GPIO_MASK_IN         GPIO16
  84         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO15
  85
  86 #elif defined(CONFIG_FOR_TPLINK_WR802N_V1) ||\
  87       defined(CONFIG_FOR_TPLINK_WR820N_V1_CN)
  88
  89         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13
  90
  91 #elif defined(CONFIG_FOR_TPLINK_WR810N_V1) ||\
  92       defined(CONFIG_FOR_TPLINK_WR810N_V2)
  93
  94         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13
  95         #define CONFIG_QCA_GPIO_MASK_IN         GPIO0 | GPIO1
  96
  97         #if defined(CONFIG_FOR_TPLINK_WR810N_V1)
  98                 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO11
  99         #endif
 100
 101 #elif defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
 102       defined(CONFIG_FOR_TPLINK_WR841N_V9)
 103
 104         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO3  | GPIO4  | GPIO11 |\
 105                                                 GPIO13 | GPIO14 | GPIO15 |\
 106                                                 GPIO16
 107         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
 108
 109 #elif defined(CONFIG_FOR_TPLINK_WR841N_V11)
 110
 111         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO1  | GPIO2  | GPIO3  |\
 112                                                 GPIO4  | GPIO11 | GPIO13 |\
 113                                                 GPIO14 | GPIO15 | GPIO16
 114         #define CONFIG_QCA_GPIO_MASK_IN         GPIO17
 115
 116 #elif defined(CONFIG_FOR_TPLINK_WR842N_V3)
 117
 118         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO2  | GPIO3  | GPIO4  |\
 119                                                 GPIO11 | GPIO12 | GPIO13 |\
 120                                                 GPIO14 | GPIO15 | GPIO16 |\
 121                                                 GPIO17
 122         #define CONFIG_QCA_GPIO_MASK_IN         GPIO0
 123
 124 #elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
 125
 126         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO4 | GPIO15
 127         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0 | GPIO11 | GPIO12
 128         #define CONFIG_QCA_GPIO_MASK_IN         GPIO2 | GPIO14 | GPIO17
 129         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO1 | GPIO13
 130
 131 #elif defined(CONFIG_FOR_WALLYS_DR531)
 132
 133         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO11 | GPIO12 | GPIO13 |\
 134                                                 GPIO14 | GPIO15 | GPIO16
 135
 136 #elif defined(CONFIG_FOR_YUNCORE_AP90Q)
 137
 138         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO4 | GPIO12 | GPIO16
 139
 140 #elif defined(CONFIG_FOR_YUNCORE_CPE830)
 141
 142         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0 | GPIO1 | GPIO2  |\
 143                                                 GPIO3 | GPIO4 | GPIO12 |\
 144                                                 GPIO16
 145
 146 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 147
 148         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO4  | GPIO11 | GPIO12 |\
 149                                                 GPIO13 | GPIO14 | GPIO15 |\
 150                                                 GPIO16
 151
 152 #endif
 153
 154 /*
 155  * ================
 156  * Default bootargs
 157  * ================
 158  */
 159 #if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
 160     defined(CONFIG_FOR_COMFAST_CF_E320N_V2)
 161
 162         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:03 "\
 163                                 "rootfstype=jffs2 init=/sbin/init "\
 164                                 "mtdparts=ath-nor0:64k(u-boot),64k(art),1536k(uImage),14656k(rootfs),64k(mib0)"
 165
 166 #elif defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
 167       defined(CONFIG_FOR_COMFAST_CF_E530N)
 168
 169         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:03 "\
 170                                 "rootfstype=jffs2 init=/sbin/init "\
 171                                 "mtdparts=ath-nor0:64k(u-boot),64k(art),1536k(uImage),6464k(rootfs),64k(mib0)"
 172
 173 #elif defined(CONFIG_FOR_GLINET_GL_AR750)
 174
 175         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:03 "\
 176                                 "rootfstype=squashfs init=/sbin/init "\
 177                                 "mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),64k(art)ro,16000k(firmware)"
 178
 179 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
 180       defined(CONFIG_FOR_P2W_R602N)      ||\
 181       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 182       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 183       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 184
 185         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 186                                 "rootfstype=squashfs init=/sbin/init "\
 187                                 "mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),14528k(rootfs),1472k(kernel),64k(art),16000k(firmware)"
 188
 189 #elif defined(CONFIG_FOR_TPLINK_MR22U_V1)    ||\
 190       defined(CONFIG_FOR_TPLINK_MR6400_V1V2) ||\
 191       defined(CONFIG_FOR_TPLINK_WR810N_V1)   ||\
 192       defined(CONFIG_FOR_TPLINK_WR810N_V2)
 193
 194         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 195                                 "rootfstype=squashfs init=/sbin/init "\
 196                                 "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(art)"
 197
 198 #elif defined(CONFIG_FOR_TPLINK_MR3420_V3)  ||\
 199       defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
 200       defined(CONFIG_FOR_TPLINK_WR802N_V1)  ||\
 201       defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
 202       defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
 203       defined(CONFIG_FOR_TPLINK_WR841N_V9)
 204
 205         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 206                                 "rootfstype=squashfs init=/sbin/init "\
 207                                 "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 208
 209 #elif defined(CONFIG_FOR_TPLINK_WR820N_V1_CN)
 210
 211         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 212                                 "rootfstype=squashfs init=/sbin/init "\
 213                                 "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(art)"
 214
 215 #elif defined(CONFIG_FOR_TPLINK_WR842N_V3) ||\
 216       defined(CONFIG_FOR_TPLINK_WR902AC_V1)
 217
 218         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 219                                 "rootfstype=jffs2 init=/sbin/init "\
 220                                 "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)"
 221
 222 #elif defined(CONFIG_FOR_WALLYS_DR531)
 223
 224         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 225                                 "rootfstype=jffs2 init=/sbin/init "\
 226                                 "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)"
 227
 228 #endif
 229
 230 /*
 231  * =============================
 232  * Load address and boot command
 233  * =============================
 234  */
 235 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 236     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 237     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 238     defined(CONFIG_FOR_COMFAST_CF_E530N)    ||\
 239     defined(CONFIG_FOR_TPLINK_MR22U_V1)     ||\
 240     defined(CONFIG_FOR_TPLINK_MR3420_V3)    ||\
 241     defined(CONFIG_FOR_TPLINK_MR6400_V1V2)  ||\
 242     defined(CONFIG_FOR_TPLINK_WA850RE_V2)   ||\
 243     defined(CONFIG_FOR_TPLINK_WR802N_V1)    ||\
 244     defined(CONFIG_FOR_TPLINK_WR810N_V1)    ||\
 245     defined(CONFIG_FOR_TPLINK_WR810N_V2)    ||\
 246     defined(CONFIG_FOR_TPLINK_WR820N_V1_CN) ||\
 247     defined(CONFIG_FOR_TPLINK_WR841N_V10)   ||\
 248     defined(CONFIG_FOR_TPLINK_WR841N_V11)   ||\
 249     defined(CONFIG_FOR_TPLINK_WR841N_V9)    ||\
 250     defined(CONFIG_FOR_TPLINK_WR842N_V3)    ||\
 251     defined(CONFIG_FOR_TPLINK_WR902AC_V1)
 252
 253         #define CFG_LOAD_ADDR   0x9F020000
 254
 255 #elif defined(CONFIG_FOR_GLINET_GL_AR750)
 256
 257         #define CFG_LOAD_ADDR   0x9F060000
 258
 259 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
 260       defined(CONFIG_FOR_P2W_R602N)      ||\
 261       defined(CONFIG_FOR_WALLYS_DR531)   ||\
 262       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 263       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 264       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 265
 266         #define CFG_LOAD_ADDR   0x9F050000
 267
 268 #endif
 269
 270 #if defined(CONFIG_FOR_P2W_CPE505N)    ||\
 271     defined(CONFIG_FOR_P2W_R602N)      ||\
 272     defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 273     defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 274     defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 275
 276         #define CONFIG_BOOTCOMMAND      "bootm 0x9F050000 || bootm 0x9FE80000"
 277
 278 #else
 279
 280         #define CONFIG_BOOTCOMMAND      "bootm " MK_STR(CFG_LOAD_ADDR)
 281
 282 #endif
 283
 284 /*
 285  * =========================
 286  * Environment configuration
 287  * =========================
 288  */
 289 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 290     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 291     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 292     defined(CONFIG_FOR_COMFAST_CF_E530N)
 293
 294         #define CFG_ENV_ADDR            0x9F018000
 295         #define CFG_ENV_SIZE            0x7C00
 296         #define CFG_ENV_SECT_SIZE       0x10000
 297
 298 #elif defined(CONFIG_FOR_GLINET_GL_AR750)
 299
 300         #define CFG_ENV_ADDR            0x9F040000
 301         #define CFG_ENV_SIZE            0x10000
 302         #define CFG_ENV_SECT_SIZE       0x10000
 303
 304 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
 305       defined(CONFIG_FOR_P2W_R602N)      ||\
 306       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 307       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 308       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 309
 310         #define CFG_ENV_ADDR            0x9F040000
 311         #define CFG_ENV_SIZE            0xFC00
 312         #define CFG_ENV_SECT_SIZE       0x10000
 313
 314 #elif defined(CONFIG_FOR_TPLINK_MR22U_V1)     ||\
 315       defined(CONFIG_FOR_TPLINK_MR3420_V3)    ||\
 316       defined(CONFIG_FOR_TPLINK_MR6400_V1V2)  ||\
 317       defined(CONFIG_FOR_TPLINK_WA850RE_V2)   ||\
 318       defined(CONFIG_FOR_TPLINK_WR802N_V1)    ||\
 319       defined(CONFIG_FOR_TPLINK_WR810N_V1)    ||\
 320       defined(CONFIG_FOR_TPLINK_WR810N_V2)    ||\
 321       defined(CONFIG_FOR_TPLINK_WR820N_V1_CN) ||\
 322       defined(CONFIG_FOR_TPLINK_WR841N_V10)   ||\
 323       defined(CONFIG_FOR_TPLINK_WR841N_V11)   ||\
 324       defined(CONFIG_FOR_TPLINK_WR841N_V9)    ||\
 325       defined(CONFIG_FOR_TPLINK_WR842N_V3)    ||\
 326       defined(CONFIG_FOR_TPLINK_WR902AC_V1)
 327
 328         #define CFG_ENV_ADDR            0x9F01EC00
 329         #define CFG_ENV_SIZE            0x1000
 330         #define CFG_ENV_SECT_SIZE       0x10000
 331
 332 #elif defined(CONFIG_FOR_WALLYS_DR531)
 333
 334         #define CFG_ENV_ADDR            0x9F030000
 335         #define CFG_ENV_SIZE            0xF800
 336         #define CFG_ENV_SECT_SIZE       0x10000
 337
 338 #endif
 339
 340 /*
 341  * ===========================
 342  * List of available baudrates
 343  * ===========================
 344  */
 345 #define CFG_BAUDRATE_TABLE      \
 346                 { 600,    1200,   2400,    4800,    9600,    14400, \
 347                   19200,  28800,  38400,   56000,   57600,   115200 }
 348
 349 /*
 350  * ==================================================
 351  * MAC address/es, model and WPS pin offsets in FLASH
 352  * ==================================================
 353  */
 354 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 355     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 356     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 357     defined(CONFIG_FOR_COMFAST_CF_E530N)
 358
 359         #define OFFSET_MAC_DATA_BLOCK           0x10000
 360         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x10000
 361         #define OFFSET_MAC_ADDRESS              0x00000
 362
 363 #elif defined(CONFIG_FOR_GLINET_GL_AR750)
 364
 365         #define OFFSET_MAC_DATA_BLOCK           0x50000
 366         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x10000
 367         #define OFFSET_MAC_ADDRESS              0x00000
 368
 369 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
 370       defined(CONFIG_FOR_P2W_R602N)      ||\
 371       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 372       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 373       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 374
 375         #define OFFSET_MAC_DATA_BLOCK           0xFF0000
 376         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 377         #define OFFSET_MAC_ADDRESS              0x000000
 378
 379 #elif defined(CONFIG_FOR_TPLINK_MR22U_V1)     ||\
 380       defined(CONFIG_FOR_TPLINK_MR3420_V3)    ||\
 381       defined(CONFIG_FOR_TPLINK_MR6400_V1V2)  ||\
 382       defined(CONFIG_FOR_TPLINK_WR802N_V1)    ||\
 383       defined(CONFIG_FOR_TPLINK_WR810N_V1)    ||\
 384       defined(CONFIG_FOR_TPLINK_WR810N_V2)    ||\
 385       defined(CONFIG_FOR_TPLINK_WR820N_V1_CN) ||\
 386       defined(CONFIG_FOR_TPLINK_WR841N_V10)   ||\
 387       defined(CONFIG_FOR_TPLINK_WR841N_V11)   ||\
 388       defined(CONFIG_FOR_TPLINK_WR841N_V9)    ||\
 389       defined(CONFIG_FOR_TPLINK_WR842N_V3)
 390
 391         #define OFFSET_MAC_DATA_BLOCK           0x010000
 392         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 393         #define OFFSET_MAC_ADDRESS              0x00FC00
 394         #define OFFSET_ROUTER_MODEL             0x00FD00
 395         #define OFFSET_PIN_NUMBER               0x00FE00
 396
 397 #elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
 398
 399         #define OFFSET_MAC_DATA_BLOCK           0x3c0000
 400         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 401         #define OFFSET_MAC_ADDRESS              0x000008
 402
 403 #elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
 404
 405         #define OFFSET_MAC_DATA_BLOCK           0x750000
 406         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 407         #define OFFSET_MAC_ADDRESS              0x000008
 408
 409 #elif defined(CONFIG_FOR_WALLYS_DR531)
 410
 411         #define OFFSET_MAC_DATA_BLOCK           0x030000
 412         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 413         #define OFFSET_MAC_ADDRESS              0x00F810
 414
 415 #endif
 416
 417 /*
 418  * =========================
 419  * Custom changes per device
 420  * =========================
 421  */
 422
 423 /*
 424  * Comfast CF-E520N and E320Nv2 are limited to 64 KB only,
 425  * disable some commands
 426  */
 427 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 428     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 429     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 430     defined(CONFIG_FOR_COMFAST_CF_E530N)
 431
 432         #undef CONFIG_CMD_DHCP
 433         #undef CONFIG_CMD_LOADB
 434         #undef CONFIG_CMD_SNTP
 435         #undef CONFIG_UPG_SCRIPTS_UBOOT
 436
 437 #endif
 438
 439 /*
 440  * ===========================
 441  * HTTP recovery configuration
 442  * ===========================
 443  */
 444 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_LOAD_ADDR
 445
 446 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 447     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 448     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 449     defined(CONFIG_FOR_COMFAST_CF_E530N)
 450
 451         #define WEBFAILSAFE_UPLOAD_ART_ADDRESS  (CFG_FLASH_BASE + 0x10000)
 452
 453 #elif defined(CONFIG_FOR_GLINET_GL_AR750)
 454
 455         #define WEBFAILSAFE_UPLOAD_ART_ADDRESS  (CFG_FLASH_BASE + 0x50000)
 456
 457 #endif
 458
 459 /* Firmware size limit */
 460 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 461     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 462     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 463     defined(CONFIG_FOR_COMFAST_CF_E530N)    ||\
 464     defined(CONFIG_FOR_TPLINK_MR22U_V1)     ||\
 465     defined(CONFIG_FOR_TPLINK_MR3420_V3)    ||\
 466     defined(CONFIG_FOR_TPLINK_MR6400_V1V2)  ||\
 467     defined(CONFIG_FOR_TPLINK_WR802N_V1)    ||\
 468     defined(CONFIG_FOR_TPLINK_WR810N_V1)    ||\
 469     defined(CONFIG_FOR_TPLINK_WR810N_V2)    ||\
 470     defined(CONFIG_FOR_TPLINK_WR820N_V1_CN) ||\
 471     defined(CONFIG_FOR_TPLINK_WR841N_V10)   ||\
 472     defined(CONFIG_FOR_TPLINK_WR841N_V11)   ||\
 473     defined(CONFIG_FOR_TPLINK_WR841N_V9)    ||\
 474     defined(CONFIG_FOR_TPLINK_WR842N_V3)
 475
 476         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 477
 478 #elif defined(CONFIG_FOR_GLINET_GL_AR750) ||\
 479       defined(CONFIG_FOR_P2W_CPE505N)     ||\
 480       defined(CONFIG_FOR_P2W_R602N)       ||\
 481       defined(CONFIG_FOR_WALLYS_DR531)    ||\
 482       defined(CONFIG_FOR_YUNCORE_AP90Q)   ||\
 483       defined(CONFIG_FOR_YUNCORE_CPE830)  ||\
 484       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 485
 486         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
 487
 488 #elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
 489
 490         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (448 * 1024)
 491
 492 #elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
 493
 494         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (832 * 1024)
 495
 496 #endif
 497
 498 /*
 499  * ========================
 500  * PLL/Clocks configuration
 501  * ========================
 502  */
 503 #if defined(CONFIG_FOR_TPLINK_MR22U_V1)     ||\
 504     defined(CONFIG_FOR_TPLINK_WA850RE_V2)   ||\
 505     defined(CONFIG_FOR_TPLINK_WR802N_V1)    ||\
 506     defined(CONFIG_FOR_TPLINK_WR820N_V1_CN) ||\
 507     defined(CONFIG_FOR_TPLINK_WR841N_V9)
 508
 509         #define CONFIG_QCA_PLL  QCA_PLL_PRESET_550_400_200
 510
 511 #else
 512
 513         #define CONFIG_QCA_PLL  QCA_PLL_PRESET_650_400_200
 514
 515 #endif
 516
 517 #if defined(CONFIG_FOR_COMFAST_CF_E314N)    ||\
 518     defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
 519     defined(CONFIG_FOR_COMFAST_CF_E520N)    ||\
 520     defined(CONFIG_FOR_COMFAST_CF_E530N)    ||\
 521     defined(CONFIG_FOR_TPLINK_MR22U_V1)     ||\
 522     defined(CONFIG_FOR_TPLINK_MR3420_V3)    ||\
 523     defined(CONFIG_FOR_TPLINK_MR6400_V1V2)  ||\
 524     defined(CONFIG_FOR_TPLINK_WA850RE_V2)   ||\
 525     defined(CONFIG_FOR_TPLINK_WR802N_V1)    ||\
 526     defined(CONFIG_FOR_TPLINK_WR810N_V1)    ||\
 527     defined(CONFIG_FOR_TPLINK_WR810N_V2)    ||\
 528     defined(CONFIG_FOR_TPLINK_WR820N_V1_CN) ||\
 529     defined(CONFIG_FOR_TPLINK_WR841N_V10)   ||\
 530     defined(CONFIG_FOR_TPLINK_WR841N_V11)   ||\
 531     defined(CONFIG_FOR_TPLINK_WR841N_V9)    ||\
 532     defined(CONFIG_FOR_TPLINK_WR842N_V3)    ||\
 533     defined(CONFIG_FOR_TPLINK_WR902AC_V1)
 534
 535         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x10000
 536         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 537
 538 #elif defined(CONFIG_FOR_GLINET_GL_AR750)
 539
 540         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x50000
 541         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 542
 543 #elif defined(CONFIG_FOR_P2W_CPE505N)    ||\
 544       defined(CONFIG_FOR_P2W_R602N)      ||\
 545       defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 546       defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 547       defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 548
 549         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x40000
 550         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 551
 552 #elif defined(CONFIG_FOR_WALLYS_DR531)
 553
 554         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x30000
 555         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 556
 557 #endif
 558
 559 /*
 560  * ==================================
 561  * For upgrade scripts in environment
 562  * ==================================
 563  */
 564 #if !defined(CONFIG_FOR_COMFAST_CF_E314N)    &&\
 565     !defined(CONFIG_FOR_COMFAST_CF_E320N_V2) &&\
 566     !defined(CONFIG_FOR_COMFAST_CF_E520N)    &&\
 567     !defined(CONFIG_FOR_COMFAST_CF_E530N)    &&\
 568     !defined(CONFIG_FOR_GLINET_GL_AR750)     &&\
 569     !defined(CONFIG_FOR_P2W_CPE505N)         &&\
 570     !defined(CONFIG_FOR_P2W_R602N)           &&\
 571     !defined(CONFIG_FOR_WALLYS_DR531)        &&\
 572     !defined(CONFIG_FOR_YUNCORE_AP90Q)       &&\
 573     !defined(CONFIG_FOR_YUNCORE_CPE830)      &&\
 574     !defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 575
 576         #define CONFIG_UPG_UBOOT_SIZE_BACKUP_HEX        0x20000
 577
 578 #endif
 579
 580 #if defined(CONFIG_FOR_P2W_CPE505N)    ||\
 581     defined(CONFIG_FOR_P2W_R602N)      ||\
 582     defined(CONFIG_FOR_YUNCORE_AP90Q)  ||\
 583     defined(CONFIG_FOR_YUNCORE_CPE830) ||\
 584     defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
 585
 586         #define CONFIG_UPG_SCRIPTS_FW_ADDR_HEX  0x9F050000
 587
 588 #endif
 589
 590 /*
 591  * ===================
 592  * Other configuration
 593  * ===================
 594  */
 595
 596 /* Cache lock for stack */
 597 #define CONFIG_INIT_SRAM_SP_OFFSET      0xbd001800
 598
 599 #endif /* _AP143_H */