u-boot/include/configs/ap121.h

   1 /*
   2  * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
   3  *
   4  * This file contains the configuration parameters
   5  * for Qualcomm Atheros AR933x based devices
   6  *
   7  * Reference designs: AP121
   8  *
   9  * SPDX-License-Identifier: GPL-2.0
  10  */
  11
  12 #ifndef _AP121_H
  13 #define _AP121_H
  14
  15 #include <config.h>
  16 #include <configs/qca9k_common.h>
  17 #include <soc/soc_common.h>
  18
  19 /*
  20  * ==================
  21  * GPIO configuration
  22  * ==================
  23  */
  24 #if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
  25
  26         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO13 | GPIO14
  27         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO0
  28         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
  29                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
  30         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  31         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  32         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  33
  34 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
  35
  36         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO26 | GPIO27
  37         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  38         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  39         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  40
  41 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
  42       defined(CONFIG_FOR_MESH_POTATO_V2)
  43
  44         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0 | GPIO28
  45         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13 | GPIO17
  46         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
  47                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
  48         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  49         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  50         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  51
  52 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
  53
  54         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO13 | GPIO15 | GPIO17 |\
  55                                                 GPIO27
  56         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
  57         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  58         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
  59
  60 #elif defined(CONFIG_FOR_GL_INET)
  61
  62         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0 | GPIO13
  63         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_H
  64         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  65         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  66
  67 #elif defined(CONFIG_FOR_TPLINK_MR10U_V1)
  68
  69         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO27
  70         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO18 |\
  71                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  72         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
  73         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO18 |\
  74                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  75
  76 #elif defined(CONFIG_FOR_TPLINK_MR13U_V1)
  77
  78         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO27
  79         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO18 |\
  80                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
  81         #define CONFIG_QCA_GPIO_MASK_IN         GPIO6 | GPIO7 | GPIO11
  82         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO18
  83         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  84
  85 #elif defined(CONFIG_FOR_TPLINK_MR3020_V1)
  86
  87         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0
  88         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO17 | GPIO26 | GPIO27
  89         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO8 |\
  90                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
  91                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
  92         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11 | GPIO18 | GPIO20
  93         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
  94                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
  95         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
  96
  97 #elif defined(CONFIG_FOR_TPLINK_MR3040_V1V2)
  98
  99         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO17 | GPIO26 | GPIO27
 100         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO18 |\
 101                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 102         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
 103         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO18 |\
 104                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 105         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
 106
 107 #elif defined(CONFIG_FOR_TPLINK_MR3220_V2)
 108
 109         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0  | GPIO1  | GPIO13 |\
 110                                                 GPIO14 | GPIO15 | GPIO16 |\
 111                                                 GPIO26
 112         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO17 | GPIO27
 113         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO8 |\
 114                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
 115                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
 116         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
 117         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
 118                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 119         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
 120
 121 #elif defined(CONFIG_FOR_TPLINK_WR703N_V1) ||\
 122       defined(CONFIG_FOR_TPLINK_WR710N_V1)
 123
 124         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO27
 125         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO8 |\
 126                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 127         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
 128         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
 129                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 130
 131 #elif defined(CONFIG_FOR_TPLINK_WR720N_V3)
 132
 133         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO27
 134         #define CONFIG_QCA_GPIO_MASK_OUT        GPIO8 |\
 135                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 136         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11 | GPIO18 | GPIO20
 137         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\
 138                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_L
 139
 140 #elif defined(CONFIG_FOR_TPLINK_WR740N_V4)
 141
 142         #define CONFIG_QCA_GPIO_MASK_LED_ACT_H  GPIO0  | GPIO1  | GPIO13 |\
 143                                                 GPIO14 | GPIO15 | GPIO16
 144         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO17 | GPIO27
 145         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L |\
 146                                                 CONFIG_QCA_GPIO_MASK_LED_ACT_H
 147         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11 | GPIO26
 148         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 149         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
 150
 151 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 152
 153         #define CONFIG_QCA_GPIO_MASK_LED_ACT_L  GPIO27
 154         #define CONFIG_QCA_GPIO_MASK_OUT        CONFIG_QCA_GPIO_MASK_LED_ACT_L
 155         #define CONFIG_QCA_GPIO_MASK_IN         GPIO11
 156         #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
 157
 158 #endif
 159
 160 /*
 161  * ================
 162  * Default bootargs
 163  * ================
 164  */
 165 #if defined(CONFIG_FOR_GL_INET)            ||\
 166     defined(CONFIG_FOR_TPLINK_MR10U_V1)    ||\
 167     defined(CONFIG_FOR_TPLINK_MR13U_V1)    ||\
 168     defined(CONFIG_FOR_TPLINK_MR3020_V1)   ||\
 169     defined(CONFIG_FOR_TPLINK_MR3040_V1V2) ||\
 170     defined(CONFIG_FOR_TPLINK_MR3220_V2)   ||\
 171     defined(CONFIG_FOR_TPLINK_WR703N_V1)   ||\
 172     defined(CONFIG_FOR_TPLINK_WR720N_V3)   ||\
 173     defined(CONFIG_FOR_TPLINK_WR740N_V4)
 174
 175         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 176                                 "rootfstype=squashfs init=/sbin/init "\
 177                                 "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 178
 179 #elif defined(CONFIG_FOR_TPLINK_WR710N_V1)
 180
 181         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 182                                 "rootfstype=squashfs init=/sbin/init "\
 183                                 "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(art)"
 184
 185 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
 186
 187         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:06 "\
 188                                 "rootfstype=squashfs init=/sbin/init "\
 189                                 "mtdparts=ar7240-nor0:64k(u-boot),64k(ART),64k(mac),64k(nvram),256k(language),1024k(uImage),6656k(rootfs)"
 190
 191 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 192
 193         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 194                                 "rootfstype=squashfs init=/sbin/init "\
 195                                 "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
 196
 197 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 198
 199         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 200                                 "rootfstype=squashfs init=/sbin/init "\
 201                                 "mtdparts=ar7240-nor0:128k(u-boot),64k(u-boot-env),16128k(firmware),64k(art)"
 202
 203 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 204
 205         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 206                                 "rootfstype=squashfs init=/sbin/init "\
 207                                 "mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(art)"
 208
 209 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
 210       defined(CONFIG_FOR_MESH_POTATO_V2)
 211
 212         #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
 213                                 "rootfstype=squashfs init=/sbin/init "\
 214                                 "mtdparts=ar7240-nor0:192k(u-boot),64k(u-boot-env),16064k(firmware),64k(art)"
 215
 216 #endif
 217
 218 /*
 219  * =============================
 220  * Load address and boot command
 221  * =============================
 222  */
 223 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 224         #define CFG_LOAD_ADDR   0x9F080000
 225 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 226         #define CFG_LOAD_ADDR   0x9F050000
 227 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
 228       defined(CONFIG_FOR_MESH_POTATO_V2)
 229         #define CFG_LOAD_ADDR   0x9F040000
 230 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 231         #define CFG_LOAD_ADDR   0x9F030000
 232 #else
 233         #define CFG_LOAD_ADDR   0x9F020000
 234 #endif
 235
 236 #define CONFIG_BOOTCOMMAND      "bootm " MK_STR(CFG_LOAD_ADDR)
 237
 238 /*
 239  * =========================
 240  * Environment configuration
 241  * =========================
 242  */
 243 #if defined(CONFIG_FOR_DRAGINO_V2) ||\
 244     defined(CONFIG_FOR_MESH_POTATO_V2)
 245         #define CFG_ENV_ADDR            0x9F030000
 246         #define CFG_ENV_SIZE            0x8000
 247         #define CFG_ENV_SECT_SIZE       0x10000
 248 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 249         #define CFG_ENV_ADDR            0x9F040000
 250         #define CFG_ENV_SIZE            0x8000
 251         #define CFG_ENV_SECT_SIZE       0x10000
 252 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 253         #define CFG_ENV_ADDR            0x9F020000
 254         #define CFG_ENV_SIZE            0x8000
 255         #define CFG_ENV_SECT_SIZE       0x10000
 256 #else
 257         #define CFG_ENV_ADDR            0x9F01EC00
 258         #define CFG_ENV_SIZE            0x1000
 259         #define CFG_ENV_SECT_SIZE       0x10000
 260 #endif
 261
 262 /*
 263  * ===========================
 264  * List of available baudrates
 265  * ===========================
 266  */
 267 #define CFG_BAUDRATE_TABLE      \
 268                 { 600,    1200,   2400,    4800,    9600,    14400,  \
 269                   19200,  28800,  38400,   56000,   57600,   115200, \
 270                   128000, 153600, 230400,  250000,  256000,  460800, \
 271                   576000, 921600, 1000000, 1152000, 1500000, 2000000 }
 272
 273 /*
 274  * ==================================================
 275  * MAC address/es, model and WPS pin offsets in FLASH
 276  * ==================================================
 277  */
 278 #if defined(CONFIG_FOR_DRAGINO_V2)     ||\
 279     defined(CONFIG_FOR_MESH_POTATO_V2) ||\
 280     defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 281         #define OFFSET_MAC_DATA_BLOCK           0xFF0000
 282         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 283         #define OFFSET_MAC_ADDRESS              0x000000
 284         #define OFFSET_MAC_ADDRESS2             0x000006
 285 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 286         #define OFFSET_MAC_DATA_BLOCK           0x010000
 287         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 288         #define OFFSET_MAC_ADDRESS              0x00FC00
 289 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 290         #define OFFSET_MAC_DATA_BLOCK           0xFF0000
 291         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 292         #define OFFSET_MAC_ADDRESS              0x000000
 293 #elif defined(CONFIG_FOR_DLINK_DIR505_A1)
 294         /*
 295          * DIR-505 has two MAC addresses inside dedicated MAC partition
 296          * They are stored in plain text...
 297          * TODO: read/write MAC stored as plain text
 298          * #define OFFSET_MAC_DATA_BLOCK        0x02000
 299          * #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
 300          * #define OFFSET_MAC_ADDRESS           0x000004
 301          * #define OFFSET_MAC_ADDRESS2          0x000016
 302          */
 303 #else
 304         #define OFFSET_MAC_DATA_BLOCK           0x010000
 305         #define OFFSET_MAC_DATA_BLOCK_LENGTH    0x010000
 306         #define OFFSET_MAC_ADDRESS              0x00FC00
 307 #endif
 308
 309 #if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) &&\
 310     !defined(CONFIG_FOR_DLINK_DIR505_A1)     &&\
 311     !defined(CONFIG_FOR_GS_OOLITE_V1_DEV)    &&\
 312     !defined(CONFIG_FOR_DRAGINO_V2)          &&\
 313     !defined(CONFIG_FOR_MESH_POTATO_V2)      &&\
 314     !defined(CONFIG_FOR_GL_INET)             &&\
 315     !defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 316         #define OFFSET_ROUTER_MODEL     0xFD00
 317 #endif
 318
 319 #if defined(CONFIG_FOR_TPLINK_MR3020_V1) ||\
 320     defined(CONFIG_FOR_TPLINK_WR740N_V4) ||\
 321     defined(CONFIG_FOR_TPLINK_MR3220_V2) ||\
 322     defined(CONFIG_FOR_TPLINK_WR710N_V1)
 323         #define OFFSET_PIN_NUMBER       0xFE00
 324 #endif
 325
 326 /*
 327  * =========================
 328  * Custom changes per device
 329  * =========================
 330  */
 331
 332 /* Dragino 2 uses different IP addresses */
 333 #if defined(CONFIG_FOR_DRAGINO_V2)
 334         #undef  CONFIG_IPADDR
 335         #define CONFIG_IPADDR   192.168.255.1
 336
 337         #undef  CONFIG_SERVERIP
 338         #define CONFIG_SERVERIP 192.168.255.2
 339 #endif
 340
 341 /* Dragino 2 and Black Swift boards use different prompts */
 342 #if defined(CONFIG_FOR_DRAGINO_V2) ||\
 343     defined(CONFIG_FOR_MESH_POTATO_V2)
 344         #undef  CFG_PROMPT
 345         #define CFG_PROMPT      "dr_boot> "
 346 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 347         #undef  CFG_PROMPT
 348         #define CFG_PROMPT      "BSB> "
 349 #endif
 350
 351 /*
 352  * ===========================
 353  * HTTP recovery configuration
 354  * ===========================
 355  */
 356 #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS       CFG_LOAD_ADDR
 357
 358 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 359         #define WEBFAILSAFE_UPLOAD_ART_ADDRESS  (CFG_FLASH_BASE + 0x10000)
 360 #endif
 361
 362 /* Firmware size limit */
 363 #if defined(CONFIG_FOR_DLINK_DIR505_A1)
 364         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (512 * 1024)
 365 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 366         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (384 * 1024)
 367 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
 368       defined(CONFIG_FOR_MESH_POTATO_V2)
 369         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (320 * 1024)
 370 #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV)
 371         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 372 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 373         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (256 * 1024)
 374 #else
 375         #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES        (192 * 1024)
 376 #endif
 377
 378
 379 /*
 380  * ========================
 381  * PLL/Clocks configuration
 382  * ========================
 383  */
 384 #define CONFIG_QCA_PLL  QCA_PLL_PRESET_400_400_200
 385
 386 #if defined(CONFIG_FOR_DLINK_DIR505_A1) ||\
 387     defined(CONFIG_FOR_BLACK_SWIFT_BOARD)
 388
 389         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x20000
 390         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 391
 392 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2)
 393
 394         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x40000
 395         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 396
 397 #elif defined(CONFIG_FOR_DRAGINO_V2) ||\
 398       defined(CONFIG_FOR_MESH_POTATO_V2)
 399
 400         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x30000
 401         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 402
 403 #else
 404
 405         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET    0x10000
 406         #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE      0x10000
 407
 408 #endif
 409
 410 #endif /* _AP121_H */