2 * Common functions for QC/A WiSoCs based boards support
4 * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
7 * Linux/arch/mips/ath79/setup.c
9 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/mipsregs.h>
16 #include <asm/addrspace.h>
17 #include <soc/qca_soc_common.h>
19 #define ALIGN_SIZE "8"
21 DECLARE_GLOBAL_DATA_PTR;
23 static u32 mac_is_not_valid = 0;
26 * Put QCA SOC name, version and revision in buffer
28 void qca_soc_name_rev(char *buf)
37 /* Get revision ID value */
38 id = qca_soc_reg_read(QCA_RST_REVISION_ID_REG);
40 major = id & QCA_RST_REVISION_ID_MAJOR_MASK;
41 rev = id & QCA_RST_REVISION_ID_REV_MASK;
44 #if (SOC_TYPE & QCA_AR933X_SOC)
45 case QCA_RST_REVISION_ID_MAJOR_AR9330_VAL:
46 sprintf(buf, "AR9330 rev. %d", rev);
48 case QCA_RST_REVISION_ID_MAJOR_AR9331_VAL:
49 sprintf(buf, "AR9331 rev. %d", rev);
52 #if (SOC_TYPE & QCA_AR934X_SOC)
53 case QCA_RST_REVISION_ID_MAJOR_AR9341_VAL:
54 sprintf(buf, "AR9341 rev. %d", rev);
56 case QCA_RST_REVISION_ID_MAJOR_AR9344_VAL:
57 sprintf(buf, "AR9344 rev. %d", rev);
60 #if (SOC_TYPE & QCA_QCA953X_SOC)
61 case QCA_RST_REVISION_ID_MAJOR_QCA953X_VAL:
62 sprintf(buf, "QCA953x ver. 1 rev. %d", rev);
64 case QCA_RST_REVISION_ID_MAJOR_QCA953X_V2_VAL:
65 sprintf(buf, "QCA953x ver. 2 rev. %d", rev);
68 #if (SOC_TYPE & QCA_QCA955X_SOC)
69 case QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL:
70 sprintf(buf, "QCA9558 rev. %d", rev);
74 sprintf(buf, "Unknown");
80 * Returns last reset reason:
81 * 1 -> reset by watchdog
88 reg = qca_soc_reg_read(QCA_RST_WATCHDOG_TIMER_CTRL_REG);
89 if (reg & QCA_RST_WATCHDOG_TIMER_CTRL_LAST_MASK)
96 * Prints available information about the board
98 void print_board_info(void)
100 u32 ahb_clk, cpu_clk, ddr_clk, spi_clk, ref_clk;
101 #if defined(CONFIG_PCI)
108 /* Show warning if last reboot was caused by SOC watchdog */
109 if (last_reset_wdt())
110 printf_wrn("reset caused by watchdog!\n\n");
113 printf("%" ALIGN_SIZE "s %s\n",
114 "BOARD:", MK_STR(CONFIG_BOARD_CUSTOM_STRING));
116 /* SOC name, version and revision */
117 qca_soc_name_rev(buffer);
118 printf("%" ALIGN_SIZE "s %s\n", "SOC:", buffer);
122 printf("%" ALIGN_SIZE "s %s\n", "CPU:", buffer);
124 /* RAM size and type */
125 printf("%" ALIGN_SIZE "s ", "RAM:");
126 print_size(bd->bi_memsize, "");
128 switch (qca_dram_type()) {
129 case RAM_MEMORY_TYPE_SDR:
132 case RAM_MEMORY_TYPE_DDR1:
135 case RAM_MEMORY_TYPE_DDR2:
142 /* DDR interface width */
143 printf("%d-bit ", qca_dram_ddr_width());
145 /* tCL-tRCD-tRP-tRAS latency */
146 printf("CL%d-%d-%d-%d\n", qca_dram_cas_lat(),
149 qca_dram_tras_lat());
151 /* SPI NOR FLASH sizes and types */
152 printf("%" ALIGN_SIZE "s ", "FLASH:");
154 for (bank = 0; bank < CFG_MAX_FLASH_BANKS; bank++) {
155 if (flash_info[bank].size == 0)
159 printf("%" ALIGN_SIZE "s ", " ");
161 print_size(flash_info[bank].size, "");
163 if (flash_info[bank].manuf_name != NULL)
164 printf(" %s", flash_info[bank].manuf_name);
166 if (flash_info[bank].model_name != NULL)
167 printf(" %s", flash_info[bank].model_name);
172 /* PCIE device/s info */
173 #if defined(CONFIG_PCI)
174 printf("%" ALIGN_SIZE "s ", "PCIe:");
176 #if (SOC_TYPE & QCA_AR934X_SOC) |\
177 (SOC_TYPE & QCA_QCA955X_SOC)
178 if (!qca_pcie0_in_ep_mode()) {
179 if (qca_pcie_dev_info(0, &vid, &did))
180 printf("%04X:%04X", vid, did);
186 #elif (SOC_TYPE & QCA_QCA953X_SOC)
187 if (qca_pcie_dev_info(0, &vid, &did))
188 printf("%04X:%04X", vid, did);
193 #if (SOC_TYPE & QCA_QCA956X_SOC)
194 if (qca_pcie_dev_info(1, &vid, &did))
195 printf("%04X:%04X", vid, did);
198 #elif (SOC_TYPE & QCA_QCA955X_SOC)
199 if (qca_pcie_dev_info(1, &vid, &did))
200 printf(", %04X:%04X", vid, did);
209 printf("%" ALIGN_SIZE "s %02X:%02X:%02X:%02X:%02X:%02X", "MAC:",
210 bd->bi_enetaddr[0],bd->bi_enetaddr[1], bd->bi_enetaddr[2],
211 bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
213 if (mac_is_not_valid)
219 printf("%" ALIGN_SIZE "s CPU/RAM/AHB/SPI/REF\n", "CLOCKS:");
221 qca_sys_clocks(&cpu_clk, &ddr_clk, &ahb_clk, &spi_clk, &ref_clk);
222 cpu_clk = cpu_clk / 1000000;
223 ddr_clk = ddr_clk / 1000000;
224 ahb_clk = ahb_clk / 1000000;
225 spi_clk = spi_clk / 1000000;
226 ref_clk = ref_clk / 1000000;
228 printf("%" ALIGN_SIZE "s %3d/%3d/%3d/%3d/%3d MHz\n",
229 " ", cpu_clk, ddr_clk, ahb_clk, spi_clk, ref_clk);
235 * Reads MAC address if available or uses fixed one
237 void macaddr_init(u8 *mac_addr)
240 u8 fixed_mac[6] = {0x00, 0x03, 0x7F, 0x09, 0x0B, 0xAD};
242 #if defined(OFFSET_MAC_ADDRESS)
243 memcpy(buffer, (void *)(CFG_FLASH_BASE
244 + OFFSET_MAC_DATA_BLOCK + OFFSET_MAC_ADDRESS), 6);
247 * Check first LSBit (I/G bit) and second LSBit (U/L bit) in MSByte of vendor part
248 * both of them should be 0:
249 * I/G bit == 0 -> Individual MAC address (unicast address)
250 * U/L bit == 0 -> Burned-In-Address (BIA) MAC address
252 if (CHECK_BIT((buffer[0] & 0xFF), 0) != 0 ||
253 CHECK_BIT((buffer[0] & 0xFF), 1) != 0) {
254 memcpy(buffer, fixed_mac, 6);
255 mac_is_not_valid = 1;
258 memcpy(buffer, fixed_mac, 6);
259 mac_is_not_valid = 1;
262 memcpy(mac_addr, buffer, 6);
266 * Returns "reset button" status:
267 * 1 -> button is pressed
268 * 0 -> button is not pressed
270 int reset_button_status(void)
272 #ifdef CONFIG_GPIO_RESET_BTN
275 gpio = qca_soc_reg_read(QCA_GPIO_IN_REG);
277 if (gpio & (1 << CONFIG_GPIO_RESET_BTN)) {
278 #if defined(CONFIG_GPIO_RESET_BTN_ACTIVE_LOW)
284 #if defined(CONFIG_GPIO_RESET_BTN_ACTIVE_LOW)
296 * Returns main CPU clock in Hz
298 u32 main_cpu_clk(void)
302 qca_sys_clocks(&cpu_clk, NULL, NULL, NULL, NULL);
308 * Calls full chip reset
310 void full_reset(void)
312 qca_full_chip_reset();