arm: socfpga: Switch to filtered QTS files
authorMarek Vasut <marex@denx.de>
Mon, 10 Aug 2015 19:21:07 +0000 (21:21 +0200)
committerMarek Vasut <marex@denx.de>
Sun, 23 Aug 2015 09:56:20 +0000 (11:56 +0200)
Signed-off-by: Marek Vasut <marex@denx.de>
23 files changed:
arch/arm/mach-socfpga/wrap_iocsr_config.c
arch/arm/mach-socfpga/wrap_pinmux_config.c
arch/arm/mach-socfpga/wrap_sdram_config.c
board/altera/arria5-socdk/qts/iocsr_config.c [deleted file]
board/altera/arria5-socdk/qts/iocsr_config.h
board/altera/arria5-socdk/qts/pinmux_config.c [deleted file]
board/altera/arria5-socdk/qts/pinmux_config.h
board/altera/arria5-socdk/qts/pll_config.h
board/altera/arria5-socdk/qts/sdram_config.h
board/altera/arria5-socdk/qts/sequencer_auto.h [deleted file]
board/altera/arria5-socdk/qts/sequencer_auto_ac_init.h [deleted file]
board/altera/arria5-socdk/qts/sequencer_auto_inst_init.h [deleted file]
board/altera/arria5-socdk/qts/sequencer_defines.h [deleted file]
board/altera/cyclone5-socdk/qts/iocsr_config.c [deleted file]
board/altera/cyclone5-socdk/qts/iocsr_config.h
board/altera/cyclone5-socdk/qts/pinmux_config.c [deleted file]
board/altera/cyclone5-socdk/qts/pinmux_config.h
board/altera/cyclone5-socdk/qts/pll_config.h
board/altera/cyclone5-socdk/qts/sdram_config.h
board/altera/cyclone5-socdk/qts/sequencer_auto.h [deleted file]
board/altera/cyclone5-socdk/qts/sequencer_auto_ac_init.h [deleted file]
board/altera/cyclone5-socdk/qts/sequencer_auto_inst_init.h [deleted file]
board/altera/cyclone5-socdk/qts/sequencer_defines.h [deleted file]

index 31b54260dfde70439c41ac3bdceb0e733c1ea718..5e3f0573555c605817e14abe4fed3abed2f22adb 100644 (file)
@@ -7,10 +7,9 @@
 #include <common.h>
 #include <errno.h>
 #include <asm/arch/clock_manager.h>
-/*
- * Yes, dear reader, we're including a C file here, this is no mistake :-)
- */
-#include <qts/iocsr_config.c>
+
+/* Board-specific header. */
+#include <qts/iocsr_config.h>
 
 int iocsr_get_config_table(const unsigned int chain_id,
                           const unsigned long **table,
index 688f1e4aca17aa9ecce7c7e24e6f80406fd8b88e..bcb77814430db5238799de5a1f50cd0746d8b441 100644 (file)
@@ -6,26 +6,9 @@
 
 #include <common.h>
 #include <errno.h>
-/*
- * Yes, dear reader, we're including a C file here, this is no mistake.
- * But this time around, we do even more perverse hacking here to be
- * compatible with QTS headers and obtain reasonably nice results too.
- *
- * First, we define _PRELOADER_PINMUX_CONFIG_H_, which will neutralise
- * the pinmux_config.h inclusion in pinmux_config.c . Since we are
- * probing everything from DT, we do NOT want those macros from the
- * pinmux_config.h to ooze into our build system, anywhere, ever. So
- * we nip it at the bud.
- *
- * Next, pinmux_config.c needs CONFIG_HPS_PINMUX_NUM and uses it to
- * specify sized array explicitly. Instead, we want to use ARRAY_SIZE
- * to figure out the size of the array, so define this macro as an
- * empty one, so that the preprocessor optimizes things such that the
- * arrays are not sized by default.
- */
-#define _PRELOADER_PINMUX_CONFIG_H_
-#define CONFIG_HPS_PINMUX_NUM
-#include <qts/pinmux_config.c>
+
+/* Board-specific header. */
+#include <qts/pinmux_config.h>
 
 void sysmgr_get_pinmux_table(const unsigned long **table,
                             unsigned int *table_len)
index 72ce565751d67567ff006f1bdeb62dc3a8775b96..31cc7dee4e1f2b70fe9f3af156fc2df5158646a3 100644 (file)
@@ -7,13 +7,9 @@
 #include <common.h>
 #include <errno.h>
 #include <asm/arch/sdram.h>
-/* QTS output file. */
-#include <qts/sdram_config.h>
 
-#include <qts/sequencer_auto_ac_init.h>
-#include <qts/sequencer_auto_inst_init.h>
-#include <qts/sequencer_auto.h>
-#include <qts/sequencer_defines.h>
+/* Board-specific header. */
+#include <qts/sdram_config.h>
 
 static const struct socfpga_sdram_config sdram_config = {
        .ctrl_cfg =
diff --git a/board/altera/arria5-socdk/qts/iocsr_config.c b/board/altera/arria5-socdk/qts/iocsr_config.c
deleted file mode 100644 (file)
index f588eda..0000000
+++ /dev/null
@@ -1,693 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2014. All rights reserved
- *
- * SPDX-License-Identifier:    BSD-3-Clause
- */
-
-/* This file is generated by Preloader Generator */
-
-#include "iocsr_config.h"
-
-const unsigned long iocsr_scan_chain0_table[((
-       CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00008000,
-       0x00060180,
-       0x18060000,
-       0x18000060,
-       0x00018060,
-       0x06018060,
-       0x00004000,
-       0x0C0300C0,
-       0x0C030000,
-       0x00000030,
-       0x00000000,
-       0x00000000,
-       0x00002000,
-       0x00000000,
-       0x00000000,
-       0x06000000,
-       0x00006018,
-       0x01806018,
-       0x00001000,
-       0x0000C030,
-       0x04000000,
-       0x03000000,
-       0x0000300C,
-       0x00000000,
-       0x00000800,
-       0x00006018,
-       0x01806000,
-       0x01800000,
-       0x00000006,
-       0x00001806,
-       0x00000400,
-       0x0000300C,
-       0x00C03000,
-       0x00C00000,
-       0x00000003,
-       0x00000C03,
-       0x00000200,
-};
-
-const unsigned long iocsr_scan_chain1_table[((
-       CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
-       0x00100000,
-       0x300C0000,
-       0x300000C0,
-       0x000000C0,
-       0x000300C0,
-       0x00008000,
-       0x00060180,
-       0x18060000,
-       0x18000000,
-       0x00000060,
-       0x00018060,
-       0x00004000,
-       0x000300C0,
-       0x10000000,
-       0x0C000000,
-       0x00000030,
-       0x0000C030,
-       0x00002000,
-       0x06018060,
-       0x06018000,
-       0x01FE0000,
-       0xF8000000,
-       0x00000007,
-       0x00001000,
-       0x0000C030,
-       0x0300C000,
-       0x03000000,
-       0x0000300C,
-       0x0000300C,
-       0x00000800,
-       0x00006018,
-       0x01806000,
-       0x01800000,
-       0x00000006,
-       0x00002000,
-       0x00000400,
-       0x0000300C,
-       0x01000000,
-       0x00000000,
-       0x00000004,
-       0x00000C03,
-       0x00000200,
-       0x00001806,
-       0x00800000,
-       0x00000000,
-       0x00000002,
-       0x00000800,
-       0x00000100,
-       0x00001000,
-       0x00400000,
-       0xC0300000,
-       0x00000000,
-       0x00000400,
-       0x00000080,
-};
-
-const unsigned long iocsr_scan_chain2_table[((
-       CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
-       0x00100000,
-       0x40000000,
-       0x00000000,
-       0x00000100,
-       0x00040000,
-       0x00008000,
-       0x18060180,
-       0x20000000,
-       0x00000000,
-       0x00000080,
-       0x00020000,
-       0x00004000,
-       0x00040000,
-       0x10000000,
-       0x00000000,
-       0x00000000,
-       0x00010000,
-       0x00002000,
-       0x10038060,
-       0x00000000,
-       0x00000000,
-       0x00000020,
-       0x01806018,
-       0x00001000,
-       0x00010000,
-       0x04000000,
-       0x03000000,
-       0x0000801C,
-       0x00004000,
-       0x00000800,
-       0x01806018,
-       0x02000000,
-       0x00000000,
-       0x00000008,
-       0x00002000,
-       0x00000400,
-       0x00C0300C,
-       0x00C03000,
-       0x00C00003,
-       0x00000C03,
-       0x00300C03,
-       0x00000200,
-       0x00601806,
-       0x80601800,
-       0x80600001,
-       0x80000601,
-       0x00180601,
-       0x00000100,
-};
-
-const unsigned long iocsr_scan_chain3_table[((
-       CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
-       0x2C820D80,
-       0x082000FF,
-       0x0A804001,
-       0x07900000,
-       0x08020000,
-       0x00100000,
-       0x0A800000,
-       0x07900000,
-       0x08020000,
-       0x00100000,
-       0xC8800000,
-       0x00003001,
-       0x00C00722,
-       0x00000000,
-       0x00000021,
-       0x82000004,
-       0x05400000,
-       0x03C80000,
-       0x04010000,
-       0x00080000,
-       0x05400000,
-       0x03C80000,
-       0x05400000,
-       0x03C80000,
-       0xE4400000,
-       0x00001800,
-       0x00600391,
-       0x800E4400,
-       0x00000001,
-       0x40000002,
-       0x02A00000,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x72200000,
-       0x80000C00,
-       0x003001C8,
-       0xC0072200,
-       0x1C880000,
-       0x20000300,
-       0x00040000,
-       0x50670000,
-       0x00000050,
-       0x24590000,
-       0x00001000,
-       0xA0000034,
-       0x0D000001,
-       0x906808A2,
-       0xA2834024,
-       0x05141A00,
-       0x808A20D0,
-       0x34024906,
-       0x01A00A28,
-       0xA20D0000,
-       0x24906808,
-       0x00A28340,
-       0xD000001A,
-       0x06808A20,
-       0x10040000,
-       0x00200000,
-       0x10040000,
-       0x00200000,
-       0x15000000,
-       0x0F200000,
-       0x15000000,
-       0x0F200000,
-       0x01FE0000,
-       0x00000000,
-       0x01800E44,
-       0x00391000,
-       0x007F8006,
-       0x00000000,
-       0x0A800001,
-       0x07900000,
-       0x0A800000,
-       0x07900000,
-       0x0A800000,
-       0x07900000,
-       0x08020000,
-       0x00100000,
-       0xC8800000,
-       0x00003001,
-       0x00C00722,
-       0x00000FF0,
-       0x72200000,
-       0x80000C00,
-       0x05400000,
-       0x02480000,
-       0x04000000,
-       0x00080000,
-       0x05400000,
-       0x03C80000,
-       0x05400000,
-       0x03C80000,
-       0x6A1C0000,
-       0x00001800,
-       0x00600391,
-       0x800E4400,
-       0x1A870001,
-       0x40000600,
-       0x02A00040,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x72200000,
-       0x80000C00,
-       0x003001C8,
-       0xC0072200,
-       0x1C880000,
-       0x20000300,
-       0x00040000,
-       0x50670000,
-       0x00000050,
-       0x24590000,
-       0x00001000,
-       0xA0000034,
-       0x0D000001,
-       0x906808A2,
-       0xA2834024,
-       0x05141A00,
-       0x808A20D0,
-       0x34024906,
-       0x01A00040,
-       0xA20D0002,
-       0x24906808,
-       0x00A28340,
-       0xD005141A,
-       0x06808A20,
-       0x10040000,
-       0x00200000,
-       0x10040000,
-       0x00200000,
-       0x15000000,
-       0x0F200000,
-       0x15000000,
-       0x0F200000,
-       0x01FE0000,
-       0x00000000,
-       0x01800E44,
-       0x00391000,
-       0x007F8006,
-       0x00000000,
-       0x99300001,
-       0x34343400,
-       0xAA0D4000,
-       0x01C3A810,
-       0xAA0D4000,
-       0x01C3A808,
-       0xAA0D4000,
-       0x01C3A810,
-       0x00040100,
-       0x00000800,
-       0x00000000,
-       0x00001208,
-       0x00482000,
-       0x01000000,
-       0x00000000,
-       0x00410482,
-       0x0006A000,
-       0x0001B400,
-       0x00020000,
-       0x00000400,
-       0x0002A000,
-       0x0001E400,
-       0x5506A000,
-       0x00E1D404,
-       0x00000000,
-       0xC880090C,
-       0x00003001,
-       0x90400000,
-       0x00000000,
-       0x2020C243,
-       0x2A835000,
-       0x0070EA04,
-       0x2A835000,
-       0x0070EA02,
-       0x2A835000,
-       0x0070EA04,
-       0x00010040,
-       0x00000200,
-       0x00000000,
-       0x00000482,
-       0x00120800,
-       0x00002000,
-       0x80000000,
-       0x00104120,
-       0x00000200,
-       0xAC055F80,
-       0xFFFFFFFF,
-       0x14F3690D,
-       0x1A041414,
-       0x00D00000,
-       0x14864000,
-       0x59647A05,
-       0xBA28A3D8,
-       0xF511451E,
-       0x0341D348,
-       0x821A0000,
-       0x0000D000,
-       0x04510680,
-       0xD859647A,
-       0x1EBA28A3,
-       0x48F51145,
-       0x000341D3,
-       0x00080200,
-       0x00001000,
-       0x00080200,
-       0x00001000,
-       0x000A8000,
-       0x00075000,
-       0x541A8000,
-       0x03875011,
-       0x10000000,
-       0x00000000,
-       0x0080C000,
-       0x41000000,
-       0x00003FC2,
-       0x00820000,
-       0xAA0D4000,
-       0x01C3A810,
-       0xAA0D4000,
-       0x01C3A808,
-       0xAA0D4000,
-       0x01C3A810,
-       0x00040100,
-       0x00000800,
-       0x00000000,
-       0x00001208,
-       0x00482000,
-       0x00008000,
-       0x00000000,
-       0x00410482,
-       0x0006A000,
-       0x0001B400,
-       0x00020000,
-       0x00000400,
-       0x00020080,
-       0x00000400,
-       0x5506A000,
-       0x00E1D404,
-       0x00000000,
-       0x0000090C,
-       0x00000010,
-       0x90400000,
-       0x00000000,
-       0x2020C243,
-       0x2A835000,
-       0x0070EA04,
-       0x2A835000,
-       0x0070EA02,
-       0x2A835000,
-       0x0070EA04,
-       0x00015000,
-       0x0000F200,
-       0x00000000,
-       0x00000482,
-       0x00120800,
-       0x00600391,
-       0x80000000,
-       0x00104120,
-       0x00000200,
-       0xAC055F80,
-       0xFFFFFFFF,
-       0x14F3690D,
-       0x1A041414,
-       0x00D00000,
-       0x14864000,
-       0x59647A05,
-       0xBA28A3D8,
-       0xF511451E,
-       0x8341D348,
-       0x821A0124,
-       0x0000D000,
-       0x00000680,
-       0xD859647A,
-       0x1EBA28A3,
-       0x48F51145,
-       0x000341D3,
-       0x00080200,
-       0x00001000,
-       0x00080200,
-       0x00001000,
-       0x000A8000,
-       0x00075000,
-       0x541A8000,
-       0x03875011,
-       0x10000000,
-       0x00000000,
-       0x0080C000,
-       0x41000000,
-       0x04000002,
-       0x00820000,
-       0xAA0D4000,
-       0x01C3A810,
-       0xAA0D4000,
-       0x01C3A808,
-       0xAA0D4000,
-       0x01C3A810,
-       0x00040100,
-       0x00000800,
-       0x00000000,
-       0x00001208,
-       0x00482000,
-       0x00008000,
-       0x00000000,
-       0x00410482,
-       0x0006A000,
-       0x0001B400,
-       0x00020000,
-       0x00000400,
-       0x0002A000,
-       0x0001E400,
-       0x5506A000,
-       0x00E1D404,
-       0x00000000,
-       0xC880090C,
-       0x00003001,
-       0x90400000,
-       0x00000000,
-       0x2020C243,
-       0x2A835000,
-       0x0070EA04,
-       0x2A835000,
-       0x0070EA02,
-       0x2A835000,
-       0x0070EA04,
-       0x00010040,
-       0x00000200,
-       0x00000000,
-       0x00000482,
-       0x00120800,
-       0x00002000,
-       0x80000000,
-       0x00104120,
-       0x00000200,
-       0xAC055F80,
-       0xFFFFFFFF,
-       0x14F3690D,
-       0x1A041414,
-       0x00D00000,
-       0x14864000,
-       0x59647A05,
-       0xBA28A3D8,
-       0xF511451E,
-       0x0341D348,
-       0x821A0000,
-       0x0000D000,
-       0x00000680,
-       0xD859647A,
-       0x1EBA28A3,
-       0x48F51145,
-       0x000341D3,
-       0x00080200,
-       0x00001000,
-       0x00080200,
-       0x00001000,
-       0x000A8000,
-       0x00075000,
-       0x541A8000,
-       0x03875011,
-       0x10000000,
-       0x00000000,
-       0x0080C000,
-       0x41000000,
-       0x04000002,
-       0x00820000,
-       0xAA0D4000,
-       0x01C3A810,
-       0xAA0D4000,
-       0x01C3A808,
-       0xAA0D4000,
-       0x01C3A810,
-       0x00040100,
-       0x00000800,
-       0x00000000,
-       0x00001208,
-       0x00482000,
-       0x00008000,
-       0x00000000,
-       0x00410482,
-       0x0006A000,
-       0x0001B400,
-       0x00020000,
-       0x00000400,
-       0x00020080,
-       0x00000400,
-       0x5506A000,
-       0x00E1D404,
-       0x00000000,
-       0x0000090C,
-       0x00000010,
-       0x90400000,
-       0x00000000,
-       0x2020C243,
-       0x2A835000,
-       0x0070EA04,
-       0x2A835000,
-       0x0070EA02,
-       0x2A835000,
-       0x0070EA04,
-       0x00010040,
-       0x00000200,
-       0x00000000,
-       0x00000482,
-       0x00120800,
-       0x00400000,
-       0x80000000,
-       0x00104120,
-       0x00000200,
-       0xAC055F80,
-       0xFFFFFFFF,
-       0x14F1690D,
-       0x1A041414,
-       0x00D00000,
-       0x14864000,
-       0x59647A05,
-       0xBA28A3D8,
-       0xF511451E,
-       0x0341D348,
-       0x821A0000,
-       0x0000D000,
-       0x00000680,
-       0xD859647A,
-       0x1EBA28A3,
-       0x48F51145,
-       0x000341D3,
-       0x00080200,
-       0x00001000,
-       0x00080200,
-       0x00001000,
-       0x000A8000,
-       0x00075000,
-       0x541A8000,
-       0x03875011,
-       0x10000000,
-       0x00000000,
-       0x0080C000,
-       0x41000000,
-       0x04000002,
-       0x00820000,
-       0x00481800,
-       0x001A1A1A,
-       0x085506A0,
-       0x0000E1D4,
-       0x045506A0,
-       0x0000E1D4,
-       0x085506A0,
-       0x8000E1D4,
-       0x00000200,
-       0x00000004,
-       0x04000000,
-       0x00000009,
-       0x00002410,
-       0x00000040,
-       0x41000000,
-       0x00002082,
-       0x00000350,
-       0x000000DA,
-       0x00000100,
-       0x40000002,
-       0x00000100,
-       0x00000002,
-       0x022A8350,
-       0x000070EA,
-       0x86000000,
-       0x08000004,
-       0x00000000,
-       0x00482000,
-       0x21800000,
-       0x00101061,
-       0x021541A8,
-       0x00003875,
-       0x011541A8,
-       0x00003875,
-       0x021541A8,
-       0x20003875,
-       0x00000080,
-       0x00000001,
-       0x41000000,
-       0x00000002,
-       0x00FF0904,
-       0x00000000,
-       0x90400000,
-       0x00000820,
-       0xC0000001,
-       0xFFD602AF,
-       0x86FFFFFF,
-       0x0A0A78B4,
-       0x000D020A,
-       0x00006800,
-       0x028A4320,
-       0xEC2CB23D,
-       0x8F5D1451,
-       0xA47A88A2,
-       0x0001A0E9,
-       0x00410D00,
-       0x40000068,
-       0x3D000003,
-       0x51EC2CB2,
-       0xA28F5D14,
-       0xE9A47A88,
-       0x000001A0,
-       0x00000401,
-       0x00000008,
-       0x00000401,
-       0x00000008,
-       0x00000540,
-       0x000003A8,
-       0x08AA0D40,
-       0x8001C3A8,
-       0x0000007F,
-       0x00000000,
-       0x00004060,
-       0xE1208000,
-       0x0000001F,
-       0x00004100,
-};
index 857f19c9e768bd3bbe8b3858f106a5a26d7ea5fe..e2bb4bb92e054d5eed6cf77d304a374647b718c0 100644 (file)
 /*
- * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ * Altera SoCFPGA IOCSR configuration
  *
- * SPDX-License-Identifier:    BSD-3-Clause
+ * SPDX-License-Identifier:    BSD-3-Clause
  */
 
-/* This file is generated by Preloader Generator */
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
 
-#ifndef _PRELOADER_IOCSR_CONFIG_H_
-#define _PRELOADER_IOCSR_CONFIG_H_
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     1337
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     1528
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     (1337)
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     (1719)
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     (1528)
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     (16766)
+const unsigned long iocsr_scan_chain0_table[] = {
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00008000,
+       0x00060180,
+       0x18060000,
+       0x18000060,
+       0x00018060,
+       0x06018060,
+       0x00004000,
+       0x0C0300C0,
+       0x0C030000,
+       0x00000030,
+       0x00000000,
+       0x00000000,
+       0x00002000,
+       0x00000000,
+       0x00000000,
+       0x06000000,
+       0x00006018,
+       0x01806018,
+       0x00001000,
+       0x0000C030,
+       0x04000000,
+       0x03000000,
+       0x0000300C,
+       0x00000000,
+       0x00000800,
+       0x00006018,
+       0x01806000,
+       0x01800000,
+       0x00000006,
+       0x00001806,
+       0x00000400,
+       0x0000300C,
+       0x00C03000,
+       0x00C00000,
+       0x00000003,
+       0x00000C03,
+       0x00000200,
+};
 
-#endif /*_PRELOADER_IOCSR_CONFIG_H_*/
+const unsigned long iocsr_scan_chain1_table[] = {
+       0x00100000,
+       0x300C0000,
+       0x300000C0,
+       0x000000C0,
+       0x000300C0,
+       0x00008000,
+       0x00060180,
+       0x18060000,
+       0x18000000,
+       0x00000060,
+       0x00018060,
+       0x00004000,
+       0x000300C0,
+       0x10000000,
+       0x0C000000,
+       0x00000030,
+       0x0000C030,
+       0x00002000,
+       0x06018060,
+       0x06018000,
+       0x01FE0000,
+       0xF8000000,
+       0x00000007,
+       0x00001000,
+       0x0000C030,
+       0x0300C000,
+       0x03000000,
+       0x0000300C,
+       0x0000300C,
+       0x00000800,
+       0x00006018,
+       0x01806000,
+       0x01800000,
+       0x00000006,
+       0x00002000,
+       0x00000400,
+       0x0000300C,
+       0x01000000,
+       0x00000000,
+       0x00000004,
+       0x00000C03,
+       0x00000200,
+       0x00001806,
+       0x00800000,
+       0x00000000,
+       0x00000002,
+       0x00000800,
+       0x00000100,
+       0x00001000,
+       0x00400000,
+       0xC0300000,
+       0x00000000,
+       0x00000400,
+       0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+       0x00100000,
+       0x40000000,
+       0x00000000,
+       0x00000100,
+       0x00040000,
+       0x00008000,
+       0x18060180,
+       0x20000000,
+       0x00000000,
+       0x00000080,
+       0x00020000,
+       0x00004000,
+       0x00040000,
+       0x10000000,
+       0x00000000,
+       0x00000000,
+       0x00010000,
+       0x00002000,
+       0x10038060,
+       0x00000000,
+       0x00000000,
+       0x00000020,
+       0x01806018,
+       0x00001000,
+       0x00010000,
+       0x04000000,
+       0x03000000,
+       0x0000801C,
+       0x00004000,
+       0x00000800,
+       0x01806018,
+       0x02000000,
+       0x00000000,
+       0x00000008,
+       0x00002000,
+       0x00000400,
+       0x00C0300C,
+       0x00C03000,
+       0x00C00003,
+       0x00000C03,
+       0x00300C03,
+       0x00000200,
+       0x00601806,
+       0x80601800,
+       0x80600001,
+       0x80000601,
+       0x00180601,
+       0x00000100,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+       0x2C820D80,
+       0x082000FF,
+       0x0A804001,
+       0x07900000,
+       0x08020000,
+       0x00100000,
+       0x0A800000,
+       0x07900000,
+       0x08020000,
+       0x00100000,
+       0xC8800000,
+       0x00003001,
+       0x00C00722,
+       0x00000000,
+       0x00000021,
+       0x82000004,
+       0x05400000,
+       0x03C80000,
+       0x04010000,
+       0x00080000,
+       0x05400000,
+       0x03C80000,
+       0x05400000,
+       0x03C80000,
+       0xE4400000,
+       0x00001800,
+       0x00600391,
+       0x800E4400,
+       0x00000001,
+       0x40000002,
+       0x02A00000,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x72200000,
+       0x80000C00,
+       0x003001C8,
+       0xC0072200,
+       0x1C880000,
+       0x20000300,
+       0x00040000,
+       0x50670000,
+       0x00000050,
+       0x24590000,
+       0x00001000,
+       0xA0000034,
+       0x0D000001,
+       0x906808A2,
+       0xA2834024,
+       0x05141A00,
+       0x808A20D0,
+       0x34024906,
+       0x01A00A28,
+       0xA20D0000,
+       0x24906808,
+       0x00A28340,
+       0xD000001A,
+       0x06808A20,
+       0x10040000,
+       0x00200000,
+       0x10040000,
+       0x00200000,
+       0x15000000,
+       0x0F200000,
+       0x15000000,
+       0x0F200000,
+       0x01FE0000,
+       0x00000000,
+       0x01800E44,
+       0x00391000,
+       0x007F8006,
+       0x00000000,
+       0x0A800001,
+       0x07900000,
+       0x0A800000,
+       0x07900000,
+       0x0A800000,
+       0x07900000,
+       0x08020000,
+       0x00100000,
+       0xC8800000,
+       0x00003001,
+       0x00C00722,
+       0x00000FF0,
+       0x72200000,
+       0x80000C00,
+       0x05400000,
+       0x02480000,
+       0x04000000,
+       0x00080000,
+       0x05400000,
+       0x03C80000,
+       0x05400000,
+       0x03C80000,
+       0x6A1C0000,
+       0x00001800,
+       0x00600391,
+       0x800E4400,
+       0x1A870001,
+       0x40000600,
+       0x02A00040,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x72200000,
+       0x80000C00,
+       0x003001C8,
+       0xC0072200,
+       0x1C880000,
+       0x20000300,
+       0x00040000,
+       0x50670000,
+       0x00000050,
+       0x24590000,
+       0x00001000,
+       0xA0000034,
+       0x0D000001,
+       0x906808A2,
+       0xA2834024,
+       0x05141A00,
+       0x808A20D0,
+       0x34024906,
+       0x01A00040,
+       0xA20D0002,
+       0x24906808,
+       0x00A28340,
+       0xD005141A,
+       0x06808A20,
+       0x10040000,
+       0x00200000,
+       0x10040000,
+       0x00200000,
+       0x15000000,
+       0x0F200000,
+       0x15000000,
+       0x0F200000,
+       0x01FE0000,
+       0x00000000,
+       0x01800E44,
+       0x00391000,
+       0x007F8006,
+       0x00000000,
+       0x99300001,
+       0x34343400,
+       0xAA0D4000,
+       0x01C3A810,
+       0xAA0D4000,
+       0x01C3A808,
+       0xAA0D4000,
+       0x01C3A810,
+       0x00040100,
+       0x00000800,
+       0x00000000,
+       0x00001208,
+       0x00482000,
+       0x01000000,
+       0x00000000,
+       0x00410482,
+       0x0006A000,
+       0x0001B400,
+       0x00020000,
+       0x00000400,
+       0x0002A000,
+       0x0001E400,
+       0x5506A000,
+       0x00E1D404,
+       0x00000000,
+       0xC880090C,
+       0x00003001,
+       0x90400000,
+       0x00000000,
+       0x2020C243,
+       0x2A835000,
+       0x0070EA04,
+       0x2A835000,
+       0x0070EA02,
+       0x2A835000,
+       0x0070EA04,
+       0x00010040,
+       0x00000200,
+       0x00000000,
+       0x00000482,
+       0x00120800,
+       0x00002000,
+       0x80000000,
+       0x00104120,
+       0x00000200,
+       0xAC055F80,
+       0xFFFFFFFF,
+       0x14F3690D,
+       0x1A041414,
+       0x00D00000,
+       0x14864000,
+       0x59647A05,
+       0xBA28A3D8,
+       0xF511451E,
+       0x0341D348,
+       0x821A0000,
+       0x0000D000,
+       0x04510680,
+       0xD859647A,
+       0x1EBA28A3,
+       0x48F51145,
+       0x000341D3,
+       0x00080200,
+       0x00001000,
+       0x00080200,
+       0x00001000,
+       0x000A8000,
+       0x00075000,
+       0x541A8000,
+       0x03875011,
+       0x10000000,
+       0x00000000,
+       0x0080C000,
+       0x41000000,
+       0x00003FC2,
+       0x00820000,
+       0xAA0D4000,
+       0x01C3A810,
+       0xAA0D4000,
+       0x01C3A808,
+       0xAA0D4000,
+       0x01C3A810,
+       0x00040100,
+       0x00000800,
+       0x00000000,
+       0x00001208,
+       0x00482000,
+       0x00008000,
+       0x00000000,
+       0x00410482,
+       0x0006A000,
+       0x0001B400,
+       0x00020000,
+       0x00000400,
+       0x00020080,
+       0x00000400,
+       0x5506A000,
+       0x00E1D404,
+       0x00000000,
+       0x0000090C,
+       0x00000010,
+       0x90400000,
+       0x00000000,
+       0x2020C243,
+       0x2A835000,
+       0x0070EA04,
+       0x2A835000,
+       0x0070EA02,
+       0x2A835000,
+       0x0070EA04,
+       0x00015000,
+       0x0000F200,
+       0x00000000,
+       0x00000482,
+       0x00120800,
+       0x00600391,
+       0x80000000,
+       0x00104120,
+       0x00000200,
+       0xAC055F80,
+       0xFFFFFFFF,
+       0x14F3690D,
+       0x1A041414,
+       0x00D00000,
+       0x14864000,
+       0x59647A05,
+       0xBA28A3D8,
+       0xF511451E,
+       0x8341D348,
+       0x821A0124,
+       0x0000D000,
+       0x00000680,
+       0xD859647A,
+       0x1EBA28A3,
+       0x48F51145,
+       0x000341D3,
+       0x00080200,
+       0x00001000,
+       0x00080200,
+       0x00001000,
+       0x000A8000,
+       0x00075000,
+       0x541A8000,
+       0x03875011,
+       0x10000000,
+       0x00000000,
+       0x0080C000,
+       0x41000000,
+       0x04000002,
+       0x00820000,
+       0xAA0D4000,
+       0x01C3A810,
+       0xAA0D4000,
+       0x01C3A808,
+       0xAA0D4000,
+       0x01C3A810,
+       0x00040100,
+       0x00000800,
+       0x00000000,
+       0x00001208,
+       0x00482000,
+       0x00008000,
+       0x00000000,
+       0x00410482,
+       0x0006A000,
+       0x0001B400,
+       0x00020000,
+       0x00000400,
+       0x0002A000,
+       0x0001E400,
+       0x5506A000,
+       0x00E1D404,
+       0x00000000,
+       0xC880090C,
+       0x00003001,
+       0x90400000,
+       0x00000000,
+       0x2020C243,
+       0x2A835000,
+       0x0070EA04,
+       0x2A835000,
+       0x0070EA02,
+       0x2A835000,
+       0x0070EA04,
+       0x00010040,
+       0x00000200,
+       0x00000000,
+       0x00000482,
+       0x00120800,
+       0x00002000,
+       0x80000000,
+       0x00104120,
+       0x00000200,
+       0xAC055F80,
+       0xFFFFFFFF,
+       0x14F3690D,
+       0x1A041414,
+       0x00D00000,
+       0x14864000,
+       0x59647A05,
+       0xBA28A3D8,
+       0xF511451E,
+       0x0341D348,
+       0x821A0000,
+       0x0000D000,
+       0x00000680,
+       0xD859647A,
+       0x1EBA28A3,
+       0x48F51145,
+       0x000341D3,
+       0x00080200,
+       0x00001000,
+       0x00080200,
+       0x00001000,
+       0x000A8000,
+       0x00075000,
+       0x541A8000,
+       0x03875011,
+       0x10000000,
+       0x00000000,
+       0x0080C000,
+       0x41000000,
+       0x04000002,
+       0x00820000,
+       0xAA0D4000,
+       0x01C3A810,
+       0xAA0D4000,
+       0x01C3A808,
+       0xAA0D4000,
+       0x01C3A810,
+       0x00040100,
+       0x00000800,
+       0x00000000,
+       0x00001208,
+       0x00482000,
+       0x00008000,
+       0x00000000,
+       0x00410482,
+       0x0006A000,
+       0x0001B400,
+       0x00020000,
+       0x00000400,
+       0x00020080,
+       0x00000400,
+       0x5506A000,
+       0x00E1D404,
+       0x00000000,
+       0x0000090C,
+       0x00000010,
+       0x90400000,
+       0x00000000,
+       0x2020C243,
+       0x2A835000,
+       0x0070EA04,
+       0x2A835000,
+       0x0070EA02,
+       0x2A835000,
+       0x0070EA04,
+       0x00010040,
+       0x00000200,
+       0x00000000,
+       0x00000482,
+       0x00120800,
+       0x00400000,
+       0x80000000,
+       0x00104120,
+       0x00000200,
+       0xAC055F80,
+       0xFFFFFFFF,
+       0x14F1690D,
+       0x1A041414,
+       0x00D00000,
+       0x14864000,
+       0x59647A05,
+       0xBA28A3D8,
+       0xF511451E,
+       0x0341D348,
+       0x821A0000,
+       0x0000D000,
+       0x00000680,
+       0xD859647A,
+       0x1EBA28A3,
+       0x48F51145,
+       0x000341D3,
+       0x00080200,
+       0x00001000,
+       0x00080200,
+       0x00001000,
+       0x000A8000,
+       0x00075000,
+       0x541A8000,
+       0x03875011,
+       0x10000000,
+       0x00000000,
+       0x0080C000,
+       0x41000000,
+       0x04000002,
+       0x00820000,
+       0x00481800,
+       0x001A1A1A,
+       0x085506A0,
+       0x0000E1D4,
+       0x045506A0,
+       0x0000E1D4,
+       0x085506A0,
+       0x8000E1D4,
+       0x00000200,
+       0x00000004,
+       0x04000000,
+       0x00000009,
+       0x00002410,
+       0x00000040,
+       0x41000000,
+       0x00002082,
+       0x00000350,
+       0x000000DA,
+       0x00000100,
+       0x40000002,
+       0x00000100,
+       0x00000002,
+       0x022A8350,
+       0x000070EA,
+       0x86000000,
+       0x08000004,
+       0x00000000,
+       0x00482000,
+       0x21800000,
+       0x00101061,
+       0x021541A8,
+       0x00003875,
+       0x011541A8,
+       0x00003875,
+       0x021541A8,
+       0x20003875,
+       0x00000080,
+       0x00000001,
+       0x41000000,
+       0x00000002,
+       0x00FF0904,
+       0x00000000,
+       0x90400000,
+       0x00000820,
+       0xC0000001,
+       0xFFD602AF,
+       0x86FFFFFF,
+       0x0A0A78B4,
+       0x000D020A,
+       0x00006800,
+       0x028A4320,
+       0xEC2CB23D,
+       0x8F5D1451,
+       0xA47A88A2,
+       0x0001A0E9,
+       0x00410D00,
+       0x40000068,
+       0x3D000003,
+       0x51EC2CB2,
+       0xA28F5D14,
+       0xE9A47A88,
+       0x000001A0,
+       0x00000401,
+       0x00000008,
+       0x00000401,
+       0x00000008,
+       0x00000540,
+       0x000003A8,
+       0x08AA0D40,
+       0x8001C3A8,
+       0x0000007F,
+       0x00000000,
+       0x00004060,
+       0xE1208000,
+       0x0000001F,
+       0x00004100,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/altera/arria5-socdk/qts/pinmux_config.c b/board/altera/arria5-socdk/qts/pinmux_config.c
deleted file mode 100644 (file)
index bf987f9..0000000
+++ /dev/null
@@ -1,214 +0,0 @@
-/* This file is generated by Preloader Generator */
-
-#include "pinmux_config.h"
-
-/* pin mux configuration data */
-unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
-       0, /* EMACIO0 */
-       2, /* EMACIO1 */
-       2, /* EMACIO2 */
-       2, /* EMACIO3 */
-       2, /* EMACIO4 */
-       2, /* EMACIO5 */
-       2, /* EMACIO6 */
-       2, /* EMACIO7 */
-       2, /* EMACIO8 */
-       0, /* EMACIO9 */
-       2, /* EMACIO10 */
-       2, /* EMACIO11 */
-       2, /* EMACIO12 */
-       2, /* EMACIO13 */
-       3, /* EMACIO14 */
-       3, /* EMACIO15 */
-       3, /* EMACIO16 */
-       3, /* EMACIO17 */
-       3, /* EMACIO18 */
-       3, /* EMACIO19 */
-       3, /* FLASHIO0 */
-       0, /* FLASHIO1 */
-       3, /* FLASHIO2 */
-       3, /* FLASHIO3 */
-       0, /* FLASHIO4 */
-       0, /* FLASHIO5 */
-       0, /* FLASHIO6 */
-       0, /* FLASHIO7 */
-       0, /* FLASHIO8 */
-       3, /* FLASHIO9 */
-       3, /* FLASHIO10 */
-       3, /* FLASHIO11 */
-       3, /* GENERALIO0 */
-       3, /* GENERALIO1 */
-       3, /* GENERALIO2 */
-       3, /* GENERALIO3 */
-       3, /* GENERALIO4 */
-       3, /* GENERALIO5 */
-       3, /* GENERALIO6 */
-       3, /* GENERALIO7 */
-       3, /* GENERALIO8 */
-       0, /* GENERALIO9 */
-       0, /* GENERALIO10 */
-       0, /* GENERALIO11 */
-       0, /* GENERALIO12 */
-       0, /* GENERALIO13 */
-       0, /* GENERALIO14 */
-       3, /* GENERALIO15 */
-       3, /* GENERALIO16 */
-       2, /* GENERALIO17 */
-       2, /* GENERALIO18 */
-       0, /* GENERALIO19 */
-       0, /* GENERALIO20 */
-       0, /* GENERALIO21 */
-       0, /* GENERALIO22 */
-       3, /* GENERALIO23 */
-       3, /* GENERALIO24 */
-       0, /* GENERALIO25 */
-       0, /* GENERALIO26 */
-       0, /* GENERALIO27 */
-       0, /* GENERALIO28 */
-       0, /* GENERALIO29 */
-       0, /* GENERALIO30 */
-       0, /* GENERALIO31 */
-       0, /* MIXED1IO0 */
-       0, /* MIXED1IO1 */
-       0, /* MIXED1IO2 */
-       0, /* MIXED1IO3 */
-       0, /* MIXED1IO4 */
-       0, /* MIXED1IO5 */
-       0, /* MIXED1IO6 */
-       0, /* MIXED1IO7 */
-       0, /* MIXED1IO8 */
-       0, /* MIXED1IO9 */
-       0, /* MIXED1IO10 */
-       0, /* MIXED1IO11 */
-       0, /* MIXED1IO12 */
-       0, /* MIXED1IO13 */
-       0, /* MIXED1IO14 */
-       3, /* MIXED1IO15 */
-       3, /* MIXED1IO16 */
-       3, /* MIXED1IO17 */
-       3, /* MIXED1IO18 */
-       3, /* MIXED1IO19 */
-       3, /* MIXED1IO20 */
-       0, /* MIXED1IO21 */
-       3, /* MIXED2IO0 */
-       3, /* MIXED2IO1 */
-       3, /* MIXED2IO2 */
-       3, /* MIXED2IO3 */
-       3, /* MIXED2IO4 */
-       3, /* MIXED2IO5 */
-       3, /* MIXED2IO6 */
-       3, /* MIXED2IO7 */
-       0, /* GPLINMUX48 */
-       0, /* GPLINMUX49 */
-       0, /* GPLINMUX50 */
-       0, /* GPLINMUX51 */
-       0, /* GPLINMUX52 */
-       0, /* GPLINMUX53 */
-       0, /* GPLINMUX54 */
-       0, /* GPLINMUX55 */
-       0, /* GPLINMUX56 */
-       0, /* GPLINMUX57 */
-       0, /* GPLINMUX58 */
-       0, /* GPLINMUX59 */
-       0, /* GPLINMUX60 */
-       0, /* GPLINMUX61 */
-       0, /* GPLINMUX62 */
-       0, /* GPLINMUX63 */
-       0, /* GPLINMUX64 */
-       0, /* GPLINMUX65 */
-       0, /* GPLINMUX66 */
-       0, /* GPLINMUX67 */
-       0, /* GPLINMUX68 */
-       0, /* GPLINMUX69 */
-       0, /* GPLINMUX70 */
-       1, /* GPLMUX0 */
-       1, /* GPLMUX1 */
-       1, /* GPLMUX2 */
-       1, /* GPLMUX3 */
-       1, /* GPLMUX4 */
-       1, /* GPLMUX5 */
-       1, /* GPLMUX6 */
-       1, /* GPLMUX7 */
-       1, /* GPLMUX8 */
-       1, /* GPLMUX9 */
-       1, /* GPLMUX10 */
-       1, /* GPLMUX11 */
-       1, /* GPLMUX12 */
-       1, /* GPLMUX13 */
-       1, /* GPLMUX14 */
-       1, /* GPLMUX15 */
-       1, /* GPLMUX16 */
-       1, /* GPLMUX17 */
-       1, /* GPLMUX18 */
-       1, /* GPLMUX19 */
-       1, /* GPLMUX20 */
-       1, /* GPLMUX21 */
-       1, /* GPLMUX22 */
-       1, /* GPLMUX23 */
-       1, /* GPLMUX24 */
-       1, /* GPLMUX25 */
-       1, /* GPLMUX26 */
-       1, /* GPLMUX27 */
-       1, /* GPLMUX28 */
-       1, /* GPLMUX29 */
-       1, /* GPLMUX30 */
-       1, /* GPLMUX31 */
-       1, /* GPLMUX32 */
-       1, /* GPLMUX33 */
-       1, /* GPLMUX34 */
-       1, /* GPLMUX35 */
-       1, /* GPLMUX36 */
-       1, /* GPLMUX37 */
-       1, /* GPLMUX38 */
-       1, /* GPLMUX39 */
-       1, /* GPLMUX40 */
-       1, /* GPLMUX41 */
-       1, /* GPLMUX42 */
-       1, /* GPLMUX43 */
-       1, /* GPLMUX44 */
-       1, /* GPLMUX45 */
-       1, /* GPLMUX46 */
-       1, /* GPLMUX47 */
-       1, /* GPLMUX48 */
-       1, /* GPLMUX49 */
-       1, /* GPLMUX50 */
-       1, /* GPLMUX51 */
-       1, /* GPLMUX52 */
-       1, /* GPLMUX53 */
-       1, /* GPLMUX54 */
-       1, /* GPLMUX55 */
-       1, /* GPLMUX56 */
-       1, /* GPLMUX57 */
-       1, /* GPLMUX58 */
-       1, /* GPLMUX59 */
-       1, /* GPLMUX60 */
-       1, /* GPLMUX61 */
-       1, /* GPLMUX62 */
-       1, /* GPLMUX63 */
-       1, /* GPLMUX64 */
-       1, /* GPLMUX65 */
-       1, /* GPLMUX66 */
-       1, /* GPLMUX67 */
-       1, /* GPLMUX68 */
-       1, /* GPLMUX69 */
-       1, /* GPLMUX70 */
-       0, /* NANDUSEFPGA */
-       0, /* UART0USEFPGA */
-       0, /* RGMII1USEFPGA */
-       0, /* SPIS0USEFPGA */
-       0, /* CAN0USEFPGA */
-       0, /* I2C0USEFPGA */
-       0, /* SDMMCUSEFPGA */
-       0, /* QSPIUSEFPGA */
-       0, /* SPIS1USEFPGA */
-       0, /* RGMII0USEFPGA */
-       0, /* UART1USEFPGA */
-       0, /* CAN1USEFPGA */
-       0, /* USB1USEFPGA */
-       0, /* I2C3USEFPGA */
-       0, /* I2C2USEFPGA */
-       0, /* I2C1USEFPGA */
-       0, /* SPIM1USEFPGA */
-       0, /* USB0USEFPGA */
-       0 /* SPIM0USEFPGA */
-};
index 21fabb0b2b42d322b5db0933f18c1c9996de1860..5a714a37831262f190ff87ed43fcd73a2f75ea59 100644 (file)
-/* This file is generated by Preloader Generator */
-
-#ifndef _PRELOADER_PINMUX_CONFIG_H_
-#define _PRELOADER_PINMUX_CONFIG_H_
-
 /*
- * State of enabling for which IP connected out through the muxing.
- * Value 1 mean the IP connection is muxed out
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
  */
-#define CONFIG_HPS_EMAC0               (1)
-#define CONFIG_HPS_EMAC1               (0)
-#define CONFIG_HPS_USB0                        (0)
-#define CONFIG_HPS_USB1                        (1)
-#define CONFIG_HPS_NAND                        (0)
-#define CONFIG_HPS_SDMMC               (1)
-#define CONFIG_HPS_QSPI                        (0)
-#define CONFIG_HPS_UART0               (1)
-#define CONFIG_HPS_UART1               (0)
-#define CONFIG_HPS_TRACE               (0)
-#define CONFIG_HPS_I2C0                        (1)
-#define CONFIG_HPS_I2C1                        (0)
-#define CONFIG_HPS_I2C2                        (0)
-#define CONFIG_HPS_I2C3                        (0)
-#define CONFIG_HPS_SPIM0               (0)
-#define CONFIG_HPS_SPIM1               (0)
-#define CONFIG_HPS_SPIS0               (0)
-#define CONFIG_HPS_SPIS1               (0)
-#define CONFIG_HPS_CAN0                        (1)
-#define CONFIG_HPS_CAN1                        (0)
-
-/* IP attribute value (which affected by pin muxing configuration) */
-#define CONFIG_HPS_SDMMC_BUSWIDTH      (8)
-
-/* 1 if the pins are connected out */
-#define CONFIG_HPS_QSPI_CS0            (0)
-#define CONFIG_HPS_QSPI_CS1            (0)
-#define CONFIG_HPS_QSPI_CS2            (0)
-#define CONFIG_HPS_QSPI_CS3            (0)
-
-/* UART */
-/* 1 means the pin is mux out or available */
-#define CONFIG_HPS_UART0_TX            (1)
-#define CONFIG_HPS_UART0_RX            (1)
-#define CONFIG_HPS_UART0_CTS           (0)
-#define CONFIG_HPS_UART0_RTS           (0)
-#define CONFIG_HPS_UART1_TX            (0)
-#define CONFIG_HPS_UART1_RX            (0)
-#define CONFIG_HPS_UART1_CTS           (0)
-#define CONFIG_HPS_UART1_RTS           (0)
 
-/* Pin mux data */
-#define CONFIG_HPS_PINMUX_NUM          (207)
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
 
-#endif /* _PRELOADER_PINMUX_CONFIG_H_ */
+unsigned long sys_mgr_init_table[] = {
+       0, /* EMACIO0 */
+       2, /* EMACIO1 */
+       2, /* EMACIO2 */
+       2, /* EMACIO3 */
+       2, /* EMACIO4 */
+       2, /* EMACIO5 */
+       2, /* EMACIO6 */
+       2, /* EMACIO7 */
+       2, /* EMACIO8 */
+       0, /* EMACIO9 */
+       2, /* EMACIO10 */
+       2, /* EMACIO11 */
+       2, /* EMACIO12 */
+       2, /* EMACIO13 */
+       3, /* EMACIO14 */
+       3, /* EMACIO15 */
+       3, /* EMACIO16 */
+       3, /* EMACIO17 */
+       3, /* EMACIO18 */
+       3, /* EMACIO19 */
+       3, /* FLASHIO0 */
+       0, /* FLASHIO1 */
+       3, /* FLASHIO2 */
+       3, /* FLASHIO3 */
+       0, /* FLASHIO4 */
+       0, /* FLASHIO5 */
+       0, /* FLASHIO6 */
+       0, /* FLASHIO7 */
+       0, /* FLASHIO8 */
+       3, /* FLASHIO9 */
+       3, /* FLASHIO10 */
+       3, /* FLASHIO11 */
+       3, /* GENERALIO0 */
+       3, /* GENERALIO1 */
+       3, /* GENERALIO2 */
+       3, /* GENERALIO3 */
+       3, /* GENERALIO4 */
+       3, /* GENERALIO5 */
+       3, /* GENERALIO6 */
+       3, /* GENERALIO7 */
+       3, /* GENERALIO8 */
+       0, /* GENERALIO9 */
+       0, /* GENERALIO10 */
+       0, /* GENERALIO11 */
+       0, /* GENERALIO12 */
+       0, /* GENERALIO13 */
+       0, /* GENERALIO14 */
+       3, /* GENERALIO15 */
+       3, /* GENERALIO16 */
+       2, /* GENERALIO17 */
+       2, /* GENERALIO18 */
+       0, /* GENERALIO19 */
+       0, /* GENERALIO20 */
+       0, /* GENERALIO21 */
+       0, /* GENERALIO22 */
+       3, /* GENERALIO23 */
+       3, /* GENERALIO24 */
+       0, /* GENERALIO25 */
+       0, /* GENERALIO26 */
+       0, /* GENERALIO27 */
+       0, /* GENERALIO28 */
+       0, /* GENERALIO29 */
+       0, /* GENERALIO30 */
+       0, /* GENERALIO31 */
+       0, /* MIXED1IO0 */
+       0, /* MIXED1IO1 */
+       0, /* MIXED1IO2 */
+       0, /* MIXED1IO3 */
+       0, /* MIXED1IO4 */
+       0, /* MIXED1IO5 */
+       0, /* MIXED1IO6 */
+       0, /* MIXED1IO7 */
+       0, /* MIXED1IO8 */
+       0, /* MIXED1IO9 */
+       0, /* MIXED1IO10 */
+       0, /* MIXED1IO11 */
+       0, /* MIXED1IO12 */
+       0, /* MIXED1IO13 */
+       0, /* MIXED1IO14 */
+       3, /* MIXED1IO15 */
+       3, /* MIXED1IO16 */
+       3, /* MIXED1IO17 */
+       3, /* MIXED1IO18 */
+       3, /* MIXED1IO19 */
+       3, /* MIXED1IO20 */
+       0, /* MIXED1IO21 */
+       3, /* MIXED2IO0 */
+       3, /* MIXED2IO1 */
+       3, /* MIXED2IO2 */
+       3, /* MIXED2IO3 */
+       3, /* MIXED2IO4 */
+       3, /* MIXED2IO5 */
+       3, /* MIXED2IO6 */
+       3, /* MIXED2IO7 */
+       0, /* GPLINMUX48 */
+       0, /* GPLINMUX49 */
+       0, /* GPLINMUX50 */
+       0, /* GPLINMUX51 */
+       0, /* GPLINMUX52 */
+       0, /* GPLINMUX53 */
+       0, /* GPLINMUX54 */
+       0, /* GPLINMUX55 */
+       0, /* GPLINMUX56 */
+       0, /* GPLINMUX57 */
+       0, /* GPLINMUX58 */
+       0, /* GPLINMUX59 */
+       0, /* GPLINMUX60 */
+       0, /* GPLINMUX61 */
+       0, /* GPLINMUX62 */
+       0, /* GPLINMUX63 */
+       0, /* GPLINMUX64 */
+       0, /* GPLINMUX65 */
+       0, /* GPLINMUX66 */
+       0, /* GPLINMUX67 */
+       0, /* GPLINMUX68 */
+       0, /* GPLINMUX69 */
+       0, /* GPLINMUX70 */
+       1, /* GPLMUX0 */
+       1, /* GPLMUX1 */
+       1, /* GPLMUX2 */
+       1, /* GPLMUX3 */
+       1, /* GPLMUX4 */
+       1, /* GPLMUX5 */
+       1, /* GPLMUX6 */
+       1, /* GPLMUX7 */
+       1, /* GPLMUX8 */
+       1, /* GPLMUX9 */
+       1, /* GPLMUX10 */
+       1, /* GPLMUX11 */
+       1, /* GPLMUX12 */
+       1, /* GPLMUX13 */
+       1, /* GPLMUX14 */
+       1, /* GPLMUX15 */
+       1, /* GPLMUX16 */
+       1, /* GPLMUX17 */
+       1, /* GPLMUX18 */
+       1, /* GPLMUX19 */
+       1, /* GPLMUX20 */
+       1, /* GPLMUX21 */
+       1, /* GPLMUX22 */
+       1, /* GPLMUX23 */
+       1, /* GPLMUX24 */
+       1, /* GPLMUX25 */
+       1, /* GPLMUX26 */
+       1, /* GPLMUX27 */
+       1, /* GPLMUX28 */
+       1, /* GPLMUX29 */
+       1, /* GPLMUX30 */
+       1, /* GPLMUX31 */
+       1, /* GPLMUX32 */
+       1, /* GPLMUX33 */
+       1, /* GPLMUX34 */
+       1, /* GPLMUX35 */
+       1, /* GPLMUX36 */
+       1, /* GPLMUX37 */
+       1, /* GPLMUX38 */
+       1, /* GPLMUX39 */
+       1, /* GPLMUX40 */
+       1, /* GPLMUX41 */
+       1, /* GPLMUX42 */
+       1, /* GPLMUX43 */
+       1, /* GPLMUX44 */
+       1, /* GPLMUX45 */
+       1, /* GPLMUX46 */
+       1, /* GPLMUX47 */
+       1, /* GPLMUX48 */
+       1, /* GPLMUX49 */
+       1, /* GPLMUX50 */
+       1, /* GPLMUX51 */
+       1, /* GPLMUX52 */
+       1, /* GPLMUX53 */
+       1, /* GPLMUX54 */
+       1, /* GPLMUX55 */
+       1, /* GPLMUX56 */
+       1, /* GPLMUX57 */
+       1, /* GPLMUX58 */
+       1, /* GPLMUX59 */
+       1, /* GPLMUX60 */
+       1, /* GPLMUX61 */
+       1, /* GPLMUX62 */
+       1, /* GPLMUX63 */
+       1, /* GPLMUX64 */
+       1, /* GPLMUX65 */
+       1, /* GPLMUX66 */
+       1, /* GPLMUX67 */
+       1, /* GPLMUX68 */
+       1, /* GPLMUX69 */
+       1, /* GPLMUX70 */
+       0, /* NANDUSEFPGA */
+       0, /* UART0USEFPGA */
+       0, /* RGMII1USEFPGA */
+       0, /* SPIS0USEFPGA */
+       0, /* CAN0USEFPGA */
+       0, /* I2C0USEFPGA */
+       0, /* SDMMCUSEFPGA */
+       0, /* QSPIUSEFPGA */
+       0, /* SPIS1USEFPGA */
+       0, /* RGMII0USEFPGA */
+       0, /* UART1USEFPGA */
+       0, /* CAN1USEFPGA */
+       0, /* USB1USEFPGA */
+       0, /* I2C3USEFPGA */
+       0, /* I2C2USEFPGA */
+       0, /* I2C1USEFPGA */
+       0, /* SPIM1USEFPGA */
+       0, /* USB0USEFPGA */
+       0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
index 7cd25df61456981a8cbff272dcaf00a75f0c982f..3d621ed9c15f42ff351c8c724c40a66792ead7f8 100644 (file)
 /*
- * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ * Altera SoCFPGA Clock and PLL configuration
  *
- * SPDX-License-Identifier:    BSD-3-Clause
+ * SPDX-License-Identifier:    BSD-3-Clause
  */
 
-/* This file is generated by Preloader Generator */
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
 
-#ifndef _PRELOADER_PLL_CONFIG_H_
-#define _PRELOADER_PLL_CONFIG_H_
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
 
-/* PLL configuration data */
-/* Main PLL */
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM                        (0)
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER                        (63)
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT               (0)
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT              (0)
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT             (0)
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT          (511)
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT     (511)
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT       (15)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK          (1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK          (1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK          (1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK          (1)
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK          (0)
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK            (1)
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK                (0)
-/*
- * To tell where is the clock source:
- * 0 = MAINPLL
- * 1 = PERIPHPLL
- */
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP               (1)
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP               (1)
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-/* Peripheral PLL */
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM                 (1)
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER                 (79)
-/*
- * To tell where is the VCOs source:
- * 0 = EOSC1
- * 1 = EOSC2
- * 2 = F2S
- */
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC                  (0)
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT              (3)
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT              (511)
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT            (511)
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT       (4)
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT            (4)
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT           (511)
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK                        (0)
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK               (4)
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK               (1)
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK               (1)
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK         (6249)
-/*
- * To tell where is the clock source:
- * 0 = F2S_PERIPH_REF_CLK
- * 1 = MAIN_CLK
- * 2 = PERIPH_CLK
- */
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC                 (2)
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND                  (2)
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI                  (1)
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
 
-/* SDRAM PLL */
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM                 (2)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER                 (79)
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-/*
- * To tell where is the VCOs source:
- * 0 = EOSC1
- * 1 = EOSC2
- * 2 = F2S
- */
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC                  (0)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT             (1)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE           (0)
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT           (0)
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE         (0)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT              (1)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE            (4)
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT           (5)
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE         (0)
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 100000000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
 
-/* Info for driver */
-#define CONFIG_HPS_CLK_OSC1_HZ                 (25000000)
-#define CONFIG_HPS_CLK_OSC2_HZ                 (25000000)
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ          0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ          0
-#define CONFIG_HPS_CLK_MAINVCO_HZ              (1600000000)
-#define CONFIG_HPS_CLK_PERVCO_HZ               (1000000000)
-#define CONFIG_HPS_CLK_SDRVCO_HZ               (666666666)
-#define CONFIG_HPS_CLK_EMAC0_HZ                        (250000000)
-#define CONFIG_HPS_CLK_EMAC1_HZ                        (250000000)
-#define CONFIG_HPS_CLK_USBCLK_HZ               (200000000)
-#define CONFIG_HPS_CLK_NAND_HZ                 (50000000)
-#define CONFIG_HPS_CLK_SDMMC_HZ                        (200000000)
-#define CONFIG_HPS_CLK_QSPI_HZ                 (400000000)
-#define CONFIG_HPS_CLK_SPIM_HZ                 (200000000)
-#define CONFIG_HPS_CLK_CAN0_HZ                 (100000000)
-#define CONFIG_HPS_CLK_CAN1_HZ                 (100000000)
-#define CONFIG_HPS_CLK_GPIODB_HZ               (32000)
-#define CONFIG_HPS_CLK_L4_MP_HZ                        (100000000)
-#define CONFIG_HPS_CLK_L4_SP_HZ                        (100000000)
 
-#endif /* _PRELOADER_PLL_CONFIG_H_ */
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
index 2e26ae5bd855a318d7bbf4c86e9e05c70241355b..e9fe60fc026dc052b0c9c2805c7cfe25b198f188 100644 (file)
 /*
- * Copyright Altera Corporation (C) 2012-2015
+ * Altera SoCFPGA SDRAM configuration
  *
- * SPDX-License-Identifier:    BSD-3-Clause
+ * SPDX-License-Identifier:    BSD-3-Clause
  */
 
-/* This file is autogenerated from tools provided by Altera.*/
-#ifndef __SDRAM_CONFIG_H
-#define __SDRAM_CONFIG_H
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
 
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             40
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        19
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        139
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            4160
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            4160
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              8
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              8
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        19
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 26
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
 #define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0        0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32       0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64       0x0101
 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
 #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
 #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
 #define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
-0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
-0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
-0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED      0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED     0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED   0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0
 
-#endif /*#ifndef__SDRAM_CONFIG_H*/
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1        0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1  0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2  0x10
+#define RW_MGR_ACTIVATE_1      0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE        0x48
+#define RW_MGR_GUARANTEED_READ 0x4B
+#define RW_MGR_GUARANTEED_READ_CONT    0x53
+#define RW_MGR_GUARANTEED_WRITE        0x17
+#define RW_MGR_GUARANTEED_WRITE_WAIT0  0x1A
+#define RW_MGR_GUARANTEED_WRITE_WAIT1  0x1E
+#define RW_MGR_GUARANTEED_WRITE_WAIT2  0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT3  0x1C
+#define RW_MGR_IDLE    0x00
+#define RW_MGR_IDLE_LOOP1      0x7A
+#define RW_MGR_IDLE_LOOP2      0x79
+#define RW_MGR_INIT_RESET_0_CKE_0      0x6E
+#define RW_MGR_INIT_RESET_1_CKE_0      0x73
+#define RW_MGR_LFSR_WR_RD_BANK_0       0x21
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA  0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS   0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP   0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT  0x31
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1  0x20
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0    0x35
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA       0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS        0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP        0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT       0x45
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1       0x34
+#define RW_MGR_MRS0_DLL_RESET  0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR     0x08
+#define RW_MGR_MRS0_USER       0x07
+#define RW_MGR_MRS0_USER_MIRR  0x0C
+#define RW_MGR_MRS1    0x03
+#define RW_MGR_MRS1_MIRR       0x09
+#define RW_MGR_MRS2    0x04
+#define RW_MGR_MRS2_MIRR       0x0A
+#define RW_MGR_MRS3    0x05
+#define RW_MGR_MRS3_MIRR       0x0B
+#define RW_MGR_PRECHARGE_ALL   0x12
+#define RW_MGR_READ_B2B        0x58
+#define RW_MGR_READ_B2B_WAIT1  0x60
+#define RW_MGR_READ_B2B_WAIT2  0x6A
+#define RW_MGR_REFRESH_ALL     0x14
+#define RW_MGR_RETURN  0x01
+#define RW_MGR_SGLE_READ       0x7C
+#define RW_MGR_ZQCL    0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET     8
+#define CALIB_VFIFO_OFFSET     6
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP        25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP   234
+#define IO_DLL_CHAIN_LENGTH    8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX    15
+#define IO_DQS_EN_DELAY_OFFSET 16
+#define IO_DQS_EN_PHASE_MAX    7
+#define IO_DQS_IN_DELAY_MAX    31
+#define IO_DQS_IN_RESERVE      4
+#define IO_DQS_OUT_RESERVE     6
+#define IO_IO_IN_DELAY_MAX     31
+#define IO_IO_OUT1_DELAY_MAX   31
+#define IO_IO_OUT2_DELAY_MAX   0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH        5
+#define READ_VALID_FIFO_SIZE   16
+#define REG_FILE_INIT_SEQ_SIGNATURE    0x5555048c
+#define RW_MGR_MEM_ADDRESS_MIRRORING   0
+#define RW_MGR_MEM_DATA_MASK_WIDTH     5
+#define RW_MGR_MEM_DATA_WIDTH  40
+#define RW_MGR_MEM_DQ_PER_READ_DQS     8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS    8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH   5
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH  5
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM       1
+#define RW_MGR_MEM_NUMBER_OF_RANKS     1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS        1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH        5
+#define TINIT_CNTR0_VAL        132
+#define TINIT_CNTR1_VAL        32
+#define TINIT_CNTR2_VAL        32
+#define TRESET_CNTR0_VAL       132
+#define TRESET_CNTR1_VAL       99
+#define TRESET_CNTR2_VAL       10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] ={
+       0x20700000,
+       0x20780000,
+       0x10080831,
+       0x10080930,
+       0x10090004,
+       0x100a0008,
+       0x100b0000,
+       0x10380400,
+       0x10080849,
+       0x100808c8,
+       0x100a0004,
+       0x10090010,
+       0x100b0000,
+       0x30780000,
+       0x38780000,
+       0x30780000,
+       0x10680000,
+       0x106b0000,
+       0x10280400,
+       0x10480000,
+       0x1c980000,
+       0x1c9b0000,
+       0x1c980008,
+       0x1c9b0008,
+       0x38f80000,
+       0x3cf80000,
+       0x38780000,
+       0x18180000,
+       0x18980000,
+       0x13580000,
+       0x135b0000,
+       0x13580008,
+       0x135b0008,
+       0x33780000,
+       0x10580008,
+       0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] ={
+       0x80000,
+       0x80680,
+       0x8180,
+       0x8200,
+       0x8280,
+       0x8300,
+       0x8380,
+       0x8100,
+       0x8480,
+       0x8500,
+       0x8580,
+       0x8600,
+       0x8400,
+       0x800,
+       0x8680,
+       0x880,
+       0xa680,
+       0x80680,
+       0x900,
+       0x80680,
+       0x980,
+       0x8680,
+       0x80680,
+       0xb68,
+       0xcce8,
+       0xae8,
+       0x8ce8,
+       0xb88,
+       0xec88,
+       0xa08,
+       0xac88,
+       0x80680,
+       0xce00,
+       0xcd80,
+       0xe700,
+       0xc00,
+       0x20ce0,
+       0x20ce0,
+       0x20ce0,
+       0x20ce0,
+       0xd00,
+       0x680,
+       0x680,
+       0x680,
+       0x680,
+       0x60e80,
+       0x61080,
+       0x61080,
+       0x61080,
+       0xa680,
+       0x8680,
+       0x80680,
+       0xce00,
+       0xcd80,
+       0xe700,
+       0xc00,
+       0x30ce0,
+       0x30ce0,
+       0x30ce0,
+       0x30ce0,
+       0xd00,
+       0x680,
+       0x680,
+       0x680,
+       0x680,
+       0x70e80,
+       0x71080,
+       0x71080,
+       0x71080,
+       0xa680,
+       0x8680,
+       0x80680,
+       0x1158,
+       0x6d8,
+       0x80680,
+       0x1168,
+       0x7e8,
+       0x7e8,
+       0x87e8,
+       0x40fe8,
+       0x410e8,
+       0x410e8,
+       0x410e8,
+       0x1168,
+       0x7e8,
+       0x7e8,
+       0xa7e8,
+       0x80680,
+       0x40e88,
+       0x41088,
+       0x41088,
+       0x41088,
+       0x40f68,
+       0x410e8,
+       0x410e8,
+       0x410e8,
+       0xa680,
+       0x40fe8,
+       0x410e8,
+       0x410e8,
+       0x410e8,
+       0x41008,
+       0x41088,
+       0x41088,
+       0x41088,
+       0x1100,
+       0xc680,
+       0x8680,
+       0xe680,
+       0x80680,
+       0x0,
+       0x8000,
+       0xa000,
+       0xc000,
+       0x80000,
+       0x80,
+       0x8080,
+       0xa080,
+       0xc080,
+       0x80080,
+       0x9180,
+       0x8680,
+       0xa680,
+       0x80680,
+       0x40f08,
+       0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/altera/arria5-socdk/qts/sequencer_auto.h b/board/altera/arria5-socdk/qts/sequencer_auto.h
deleted file mode 100644 (file)
index df1c224..0000000
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier:    BSD-3-Clause
- */
-
-
-#define RW_MGR_READ_B2B_WAIT2 0x6A
-#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
-#define RW_MGR_REFRESH_ALL 0x14
-#define RW_MGR_ZQCL 0x06
-#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
-#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
-#define RW_MGR_ACTIVATE_0_AND_1 0x0D
-#define RW_MGR_MRS2_MIRR 0x0A
-#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
-#define RW_MGR_ACTIVATE_1 0x0F
-#define RW_MGR_MRS2 0x04
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
-#define RW_MGR_MRS1 0x03
-#define RW_MGR_IDLE_LOOP1 0x7A
-#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
-#define RW_MGR_MRS3 0x05
-#define RW_MGR_IDLE_LOOP2 0x79
-#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
-#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
-#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
-#define RW_MGR_RDIMM_CMD 0x78
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
-#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
-#define RW_MGR_GUARANTEED_READ_CONT 0x53
-#define RW_MGR_MRS3_MIRR 0x0B
-#define RW_MGR_IDLE 0x00
-#define RW_MGR_READ_B2B 0x58
-#define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
-#define RW_MGR_GUARANTEED_WRITE 0x17
-#define RW_MGR_PRECHARGE_ALL 0x12
-#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
-#define RW_MGR_SGLE_READ 0x7C
-#define RW_MGR_MRS0_USER_MIRR 0x0C
-#define RW_MGR_RETURN 0x01
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
-#define RW_MGR_MRS0_USER 0x07
-#define RW_MGR_GUARANTEED_READ 0x4B
-#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
-#define RW_MGR_INIT_RESET_1_CKE_0 0x73
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
-#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
-#define RW_MGR_MRS0_DLL_RESET 0x02
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
-#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
-#define RW_MGR_CLEAR_DQS_ENABLE 0x48
-#define RW_MGR_MRS1_MIRR 0x09
-#define RW_MGR_READ_B2B_WAIT1 0x60
-#define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
-#define RW_MGR_CONTENT_REFRESH_ALL 0x000980
-#define RW_MGR_CONTENT_ZQCL 0x008380
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
-#define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
-#define RW_MGR_CONTENT_MRS2_MIRR 0x008580
-#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
-#define RW_MGR_CONTENT_ACTIVATE_1 0x000880
-#define RW_MGR_CONTENT_MRS2 0x008280
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
-#define RW_MGR_CONTENT_MRS1 0x008200
-#define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
-#define RW_MGR_CONTENT_MRS3 0x008300
-#define RW_MGR_CONTENT_IDLE_LOOP2 0x008680
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
-#define RW_MGR_CONTENT_RDIMM_CMD 0x009180
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
-#define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
-#define RW_MGR_CONTENT_MRS3_MIRR 0x008600
-#define RW_MGR_CONTENT_IDLE 0x080000
-#define RW_MGR_CONTENT_READ_B2B 0x040E88
-#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
-#define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
-#define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
-#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
-#define RW_MGR_CONTENT_SGLE_READ 0x040F08
-#define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
-#define RW_MGR_CONTENT_RETURN 0x080680
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
-#define RW_MGR_CONTENT_MRS0_USER 0x008100
-#define RW_MGR_CONTENT_GUARANTEED_READ 0x001168
-#define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
-#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
-#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
-#define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
-#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
-#define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
-#define RW_MGR_CONTENT_MRS1_MIRR 0x008500
-#define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
-
diff --git a/board/altera/arria5-socdk/qts/sequencer_auto_ac_init.h b/board/altera/arria5-socdk/qts/sequencer_auto_ac_init.h
deleted file mode 100644 (file)
index 1c9d8f3..0000000
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier:    BSD-3-Clause
- */
-
-const uint32_t ac_rom_init[] = {
-/* The if..else... is not required if generated by tools */
-       0x20700000,
-       0x20780000,
-       0x10080831,
-       0x10080930,
-       0x10090004,
-       0x100a0008,
-       0x100b0000,
-       0x10380400,
-       0x10080849,
-       0x100808c8,
-       0x100a0004,
-       0x10090010,
-       0x100b0000,
-       0x30780000,
-       0x38780000,
-       0x30780000,
-       0x10680000,
-       0x106b0000,
-       0x10280400,
-       0x10480000,
-       0x1c980000,
-       0x1c9b0000,
-       0x1c980008,
-       0x1c9b0008,
-       0x38f80000,
-       0x3cf80000,
-       0x38780000,
-       0x18180000,
-       0x18980000,
-       0x13580000,
-       0x135b0000,
-       0x13580008,
-       0x135b0008,
-       0x33780000,
-       0x10580008,
-       0x10780000
-};
diff --git a/board/altera/arria5-socdk/qts/sequencer_auto_inst_init.h b/board/altera/arria5-socdk/qts/sequencer_auto_inst_init.h
deleted file mode 100644 (file)
index c8dbeab..0000000
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier:    BSD-3-Clause
- */
-
-/* The if..else... is not required if generated by tools */
-const u32 inst_rom_init[] = {
-       0x80000,
-       0x80680,
-       0x8180,
-       0x8200,
-       0x8280,
-       0x8300,
-       0x8380,
-       0x8100,
-       0x8480,
-       0x8500,
-       0x8580,
-       0x8600,
-       0x8400,
-       0x800,
-       0x8680,
-       0x880,
-       0xa680,
-       0x80680,
-       0x900,
-       0x80680,
-       0x980,
-       0x8680,
-       0x80680,
-       0xb68,
-       0xcce8,
-       0xae8,
-       0x8ce8,
-       0xb88,
-       0xec88,
-       0xa08,
-       0xac88,
-       0x80680,
-       0xce00,
-       0xcd80,
-       0xe700,
-       0xc00,
-       0x20ce0,
-       0x20ce0,
-       0x20ce0,
-       0x20ce0,
-       0xd00,
-       0x680,
-       0x680,
-       0x680,
-       0x680,
-       0x60e80,
-       0x61080,
-       0x61080,
-       0x61080,
-       0xa680,
-       0x8680,
-       0x80680,
-       0xce00,
-       0xcd80,
-       0xe700,
-       0xc00,
-       0x30ce0,
-       0x30ce0,
-       0x30ce0,
-       0x30ce0,
-       0xd00,
-       0x680,
-       0x680,
-       0x680,
-       0x680,
-       0x70e80,
-       0x71080,
-       0x71080,
-       0x71080,
-       0xa680,
-       0x8680,
-       0x80680,
-       0x1158,
-       0x6d8,
-       0x80680,
-       0x1168,
-       0x7e8,
-       0x7e8,
-       0x87e8,
-       0x40fe8,
-       0x410e8,
-       0x410e8,
-       0x410e8,
-       0x1168,
-       0x7e8,
-       0x7e8,
-       0xa7e8,
-       0x80680,
-       0x40e88,
-       0x41088,
-       0x41088,
-       0x41088,
-       0x40f68,
-       0x410e8,
-       0x410e8,
-       0x410e8,
-       0xa680,
-       0x40fe8,
-       0x410e8,
-       0x410e8,
-       0x410e8,
-       0x41008,
-       0x41088,
-       0x41088,
-       0x41088,
-       0x1100,
-       0xc680,
-       0x8680,
-       0xe680,
-       0x80680,
-       0x0,
-       0x8000,
-       0xa000,
-       0xc000,
-       0x80000,
-       0x80,
-       0x8080,
-       0xa080,
-       0xc080,
-       0x80080,
-       0x9180,
-       0x8680,
-       0xa680,
-       0x80680,
-       0x40f08,
-       0x80680
-};
diff --git a/board/altera/arria5-socdk/qts/sequencer_defines.h b/board/altera/arria5-socdk/qts/sequencer_defines.h
deleted file mode 100644 (file)
index 6e41175..0000000
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier:    BSD-3-Clause
- */
-
-#ifndef _SEQUENCER_DEFINES_H_
-#define _SEQUENCER_DEFINES_H_
-
-#define AC_ROM_MR1_MIRR 0000000000100
-#define AC_ROM_MR1_OCD_ENABLE
-#define AC_ROM_MR2_MIRR 0000000010000
-#define AC_ROM_MR3_MIRR 0000000000000
-#define AC_ROM_MR0_CALIB
-#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000
-#define AC_ROM_MR0_DLL_RESET 0100100110000
-#define AC_ROM_MR0_MIRR 0100001001001
-#define AC_ROM_MR0 0100000110001
-#define AC_ROM_MR1 0000000000100
-#define AC_ROM_MR2 0000000001000
-#define AC_ROM_MR3 0000000000000
-#define AFI_CLK_FREQ 534
-#define AFI_RATE_RATIO 1
-#define AVL_CLK_FREQ 67
-#define BFM_MODE 0
-#define BURST2 0
-#define CALIB_LFIFO_OFFSET 8
-#define CALIB_VFIFO_OFFSET 6
-#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
-#define ENABLE_SUPER_QUICK_CALIBRATION 0
-#define GUARANTEED_READ_BRINGUP_TEST 0
-#define HARD_PHY 1
-#define HARD_VFIFO 1
-#define HPS_HW 1
-#define HR_DDIO_OUT_HAS_THREE_REGS 0
-#define IO_DELAY_PER_DCHAIN_TAP 25
-#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
-#define IO_DELAY_PER_OPA_TAP 234
-#define IO_DLL_CHAIN_LENGTH 8
-#define IO_DM_OUT_RESERVE 0
-#define IO_DQDQS_OUT_PHASE_MAX 0
-#define IO_DQS_EN_DELAY_MAX 15
-#define IO_DQS_EN_DELAY_OFFSET 16
-#define IO_DQS_EN_PHASE_MAX 7
-#define IO_DQS_IN_DELAY_MAX 31
-#define IO_DQS_IN_RESERVE 4
-#define IO_DQS_OUT_RESERVE 6
-#define IO_DQ_OUT_RESERVE 0
-#define IO_IO_IN_DELAY_MAX 31
-#define IO_IO_OUT1_DELAY_MAX 31
-#define IO_IO_OUT2_DELAY_MAX 0
-#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
-#define MARGIN_VARIATION_TEST 0
-#define MAX_LATENCY_COUNT_WIDTH 5
-#define MEM_ADDR_WIDTH 13
-#define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
-#define RW_MGR_MEM_ADDRESS_MIRRORING 0
-#define RW_MGR_MEM_ADDRESS_WIDTH 15
-#define RW_MGR_MEM_BANK_WIDTH 3
-#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
-#define RW_MGR_MEM_CLK_EN_WIDTH 1
-#define RW_MGR_MEM_CONTROL_WIDTH 1
-#define RW_MGR_MEM_DATA_MASK_WIDTH 5
-#define RW_MGR_MEM_DATA_WIDTH 40
-#define RW_MGR_MEM_DQ_PER_READ_DQS 8
-#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
-#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
-#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
-#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
-#define RW_MGR_MEM_NUMBER_OF_RANKS 1
-#define RW_MGR_MEM_ODT_WIDTH 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
-#define RW_MGR_MR0_BL 1
-#define RW_MGR_MR0_CAS_LATENCY 3
-#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
-#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
-#define SKEW_CALIBRATION 0
-#define TINIT_CNTR1_VAL 32
-#define TINIT_CNTR2_VAL 32
-#define TINIT_CNTR0_VAL 132
-#define TRESET_CNTR1_VAL 99
-#define TRESET_CNTR2_VAL 10
-#define TRESET_CNTR0_VAL 132
-
-#endif /* _SEQUENCER_DEFINES_H_ */
diff --git a/board/altera/cyclone5-socdk/qts/iocsr_config.c b/board/altera/cyclone5-socdk/qts/iocsr_config.c
deleted file mode 100644 (file)
index a2d238c..0000000
+++ /dev/null
@@ -1,657 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2014. All rights reserved
- *
- * SPDX-License-Identifier:    BSD-3-Clause
- */
-
-/* This file is generated by Preloader Generator */
-
-#include "iocsr_config.h"
-
-const unsigned long iocsr_scan_chain0_table[((
-       CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
-       0x00000000,
-       0x00000000,
-       0x0FF00000,
-       0xC0000000,
-       0x0000003F,
-       0x00008000,
-       0x00020080,
-       0x08020000,
-       0x08000000,
-       0x00018020,
-       0x00000000,
-       0x00004000,
-       0x00010040,
-       0x04010000,
-       0x04000000,
-       0x00000010,
-       0x00004010,
-       0x00002000,
-       0x00020000,
-       0x02008000,
-       0x02000000,
-       0x00000008,
-       0x00002008,
-       0x00001000,
-};
-
-const unsigned long iocsr_scan_chain1_table[((
-       CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
-       0x000C0300,
-       0x10040000,
-       0x100000C0,
-       0x00000040,
-       0x00010040,
-       0x00008000,
-       0x00080000,
-       0x18060000,
-       0x18000000,
-       0x00000060,
-       0x00018060,
-       0x00004000,
-       0x00010040,
-       0x10000000,
-       0x04000000,
-       0x00000010,
-       0x00004010,
-       0x00002000,
-       0x06008020,
-       0x02008000,
-       0x01FE0000,
-       0xF8000000,
-       0x00000007,
-       0x00001000,
-       0x00004010,
-       0x01004000,
-       0x01000000,
-       0x00003004,
-       0x00001004,
-       0x00000800,
-       0x00000000,
-       0x00000000,
-       0x00800000,
-       0x00000002,
-       0x00002000,
-       0x00000400,
-       0x00000000,
-       0x00401000,
-       0x00000003,
-       0x00000000,
-       0x00000000,
-       0x00000200,
-       0x00600802,
-       0x00000000,
-       0x80200000,
-       0x80000600,
-       0x00000200,
-       0x00000100,
-       0x00300401,
-       0xC0100400,
-       0x40100000,
-       0x40000300,
-       0x000C0100,
-       0x00000080,
-};
-
-const unsigned long iocsr_scan_chain2_table[((
-       CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
-       0x80040100,
-       0x00000000,
-       0x0FF00000,
-       0x00000000,
-       0x0C010040,
-       0x00008000,
-       0x18020080,
-       0x00000000,
-       0x08000000,
-       0x00040020,
-       0x06018060,
-       0x00004000,
-       0x0C010040,
-       0x04010000,
-       0x00000030,
-       0x00000000,
-       0x03004010,
-       0x00002000,
-       0x06008020,
-       0x02008000,
-       0x02000018,
-       0x00006008,
-       0x01802008,
-       0x00001000,
-       0x03004010,
-       0x01004000,
-       0x0100000C,
-       0x00003004,
-       0x00C01004,
-       0x00000800,
-};
-
-const unsigned long iocsr_scan_chain3_table[((
-       CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
-       0x2C420D80,
-       0x082000FF,
-       0x0A804001,
-       0x07900000,
-       0x08020000,
-       0x00100000,
-       0x0A800000,
-       0x07900000,
-       0x08020000,
-       0x00100000,
-       0xC8800000,
-       0x00003001,
-       0x00C00722,
-       0x00000000,
-       0x00000021,
-       0x82000004,
-       0x05400000,
-       0x03C80000,
-       0x04010000,
-       0x00080000,
-       0x05400000,
-       0x03C80000,
-       0x05400000,
-       0x03C80000,
-       0xE4400000,
-       0x00001800,
-       0x00600391,
-       0x800E4400,
-       0x00000001,
-       0x40000002,
-       0x02A00000,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x72200000,
-       0x80000C00,
-       0x003001C8,
-       0xC0072200,
-       0x1C880000,
-       0x20000300,
-       0x00040000,
-       0x50670000,
-       0x00000070,
-       0x24590000,
-       0x00001000,
-       0xA0000034,
-       0x0D000001,
-       0x906808A2,
-       0xA2834024,
-       0x05141A00,
-       0x808A20D0,
-       0x34024906,
-       0x01A00A28,
-       0xA20D0000,
-       0x24906808,
-       0x00A28340,
-       0xD000001A,
-       0x06808A20,
-       0x10040000,
-       0x00200000,
-       0x10040000,
-       0x00200000,
-       0x15000000,
-       0x0F200000,
-       0x15000000,
-       0x0F200000,
-       0x01FE0000,
-       0x00000000,
-       0x01800E44,
-       0x00391000,
-       0x007F8006,
-       0x00000000,
-       0x0A800001,
-       0x07900000,
-       0x0A800000,
-       0x07900000,
-       0x0A800000,
-       0x07900000,
-       0x08020000,
-       0x00100000,
-       0xC8800000,
-       0x00003001,
-       0x00C00722,
-       0x00000FF0,
-       0x72200000,
-       0x80000C00,
-       0x05400000,
-       0x02480000,
-       0x04000000,
-       0x00080000,
-       0x05400000,
-       0x03C80000,
-       0x05400000,
-       0x03C80000,
-       0x6A1C0000,
-       0x00001800,
-       0x00600391,
-       0x800E4400,
-       0x1A870001,
-       0x40000600,
-       0x02A00040,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x02A00000,
-       0x01E40000,
-       0x72200000,
-       0x80000C00,
-       0x003001C8,
-       0xC0072200,
-       0x1C880000,
-       0x20000300,
-       0x00040000,
-       0x50670000,
-       0x00000070,
-       0x24590000,
-       0x00001000,
-       0xA0000034,
-       0x0D000001,
-       0x906808A2,
-       0xA2834024,
-       0x05141A00,
-       0x808A20D0,
-       0x34024906,
-       0x01A00040,
-       0xA20D0002,
-       0x24906808,
-       0x00A28340,
-       0xD005141A,
-       0x06808A20,
-       0x10040000,
-       0x00200000,
-       0x10040000,
-       0x00200000,
-       0x15000000,
-       0x0F200000,
-       0x15000000,
-       0x0F200000,
-       0x01FE0000,
-       0x00000000,
-       0x01800E44,
-       0x00391000,
-       0x007F8006,
-       0x00000000,
-       0x99300001,
-       0x34343400,
-       0xAA0D4000,
-       0x01C3A810,
-       0xAA0D4000,
-       0x01C3A808,
-       0xAA0D4000,
-       0x01C3A810,
-       0x00040100,
-       0x00000800,
-       0x00000000,
-       0x00001208,
-       0x00482000,
-       0x000001C1,
-       0x00000000,
-       0x00410482,
-       0x0006A000,
-       0x0001B400,
-       0x00020000,
-       0x00000400,
-       0x0002A000,
-       0x0001E400,
-       0x5506A000,
-       0x00E1D404,
-       0x00000000,
-       0xC880090C,
-       0x00003001,
-       0x90400000,
-       0x00000000,
-       0x2020C243,
-       0x2A835000,
-       0x0070EA04,
-       0x2A835000,
-       0x0070EA02,
-       0x2A835000,
-       0x0070EA04,
-       0x00010040,
-       0x00000200,
-       0x00000000,
-       0x00000482,
-       0x00120800,
-       0x00002000,
-       0x80000000,
-       0x00104120,
-       0x00000200,
-       0xAC255F80,
-       0xF1C71C71,
-       0x14F3690D,
-       0x1A041414,
-       0x00D00000,
-       0x14864000,
-       0x59647A05,
-       0xBA28A3D8,
-       0xF511451E,
-       0x0341D348,
-       0x821A0000,
-       0x0000D000,
-       0x04510680,
-       0xD859647A,
-       0x1EBA28A3,
-       0x48F51145,
-       0x000341D3,
-       0x00080200,
-       0x00001000,
-       0x00080200,
-       0x00001000,
-       0x000A8000,
-       0x00075000,
-       0x541A8000,
-       0x03875011,
-       0x10000000,
-       0x00000000,
-       0x0080C000,
-       0x41000000,
-       0x00003FC2,
-       0x00820000,
-       0xAA0D4000,
-       0x01C3A810,
-       0xAA0D4000,
-       0x01C3A808,
-       0xAA0D4000,
-       0x01C3A810,
-       0x00040100,
-       0x00000800,
-       0x00000000,
-       0x00001208,
-       0x00482000,
-       0x00008000,
-       0x00000000,
-       0x00410482,
-       0x0006A000,
-       0x0001B400,
-       0x00020000,
-       0x00000400,
-       0x00020080,
-       0x00000400,
-       0x5506A000,
-       0x00E1D404,
-       0x00000000,
-       0x0000090C,
-       0x00000010,
-       0x90400000,
-       0x00000000,
-       0x2020C243,
-       0x2A835000,
-       0x0070EA04,
-       0x2A835000,
-       0x0070EA02,
-       0x2A835000,
-       0x0070EA04,
-       0x00015000,
-       0x0000F200,
-       0x00000000,
-       0x00000482,
-       0x00120800,
-       0x00600391,
-       0x80000000,
-       0x00104120,
-       0x00000200,
-       0xAC255F80,
-       0xF1C71C71,
-       0x14F3690D,
-       0x1A041414,
-       0x00D00000,
-       0x14864000,
-       0x59647A05,
-       0xBA28A3D8,
-       0xF511451E,
-       0x8341D348,
-       0x821A0124,
-       0x0000D000,
-       0x00000680,
-       0xD859647A,
-       0x1EBA28A3,
-       0x48F51145,
-       0x000341D3,
-       0x00080200,
-       0x00001000,
-       0x00080200,
-       0x00001000,
-       0x000A8000,
-       0x00075000,
-       0x541A8000,
-       0x03875011,
-       0x10000000,
-       0x00000000,
-       0x0080C000,
-       0x41000000,
-       0x04000002,
-       0x00820000,
-       0xAA0D4000,
-       0x01C3A810,
-       0xAA0D4000,
-       0x01C3A808,
-       0xAA0D4000,
-       0x01C3A810,
-       0x00040100,
-       0x00000800,
-       0x00000000,
-       0x00001208,
-       0x00482000,
-       0x00008000,
-       0x00000000,
-       0x00410482,
-       0x0006A000,
-       0x0001B400,
-       0x00020000,
-       0x00000400,
-       0x0002A000,
-       0x0001E400,
-       0x5506A000,
-       0x00E1D404,
-       0x00000000,
-       0xC880090C,
-       0x00003001,
-       0x90400000,
-       0x00000000,
-       0x2020C243,
-       0x2A835000,
-       0x0070EA04,
-       0x2A835000,
-       0x0070EA02,
-       0x2A835000,
-       0x0070EA04,
-       0x00010040,
-       0x00000200,
-       0x00000000,
-       0x00000482,
-       0x00120800,
-       0x00002000,
-       0x80000000,
-       0x00104120,
-       0x00000200,
-       0xAC255F80,
-       0xF1C71C71,
-       0x14F3690D,
-       0x1A041414,
-       0x00D00000,
-       0x14864000,
-       0x59647A05,
-       0xBA28A3D8,
-       0xF511451E,
-       0x0341D348,
-       0x821A0000,
-       0x0000D000,
-       0x00000680,
-       0xD859647A,
-       0x1EBA28A3,
-       0x48F51145,
-       0x000341D3,
-       0x00080200,
-       0x00001000,
-       0x00080200,
-       0x00001000,
-       0x000A8000,
-       0x00075000,
-       0x541A8000,
-       0x03875011,
-       0x10000000,
-       0x00000000,
-       0x0080C000,
-       0x41000000,
-       0x04000002,
-       0x00820000,
-       0xAA0D4000,
-       0x01C3A810,
-       0xAA0D4000,
-       0x01C3A808,
-       0xAA0D4000,
-       0x01C3A810,
-       0x00040100,
-       0x00000800,
-       0x00000000,
-       0x00001208,
-       0x00482000,
-       0x00008000,
-       0x00000000,
-       0x00410482,
-       0x0006A000,
-       0x0001B400,
-       0x00020000,
-       0x00000400,
-       0x00020080,
-       0x00000400,
-       0x5506A000,
-       0x00E1D404,
-       0x00000000,
-       0x0000090C,
-       0x00000010,
-       0x90400000,
-       0x00000000,
-       0x2020C243,
-       0x2A835000,
-       0x0070EA04,
-       0x2A835000,
-       0x0070EA02,
-       0x2A835000,
-       0x0070EA04,
-       0x00010040,
-       0x00000200,
-       0x00000000,
-       0x00000482,
-       0x40120800,
-       0x00000070,
-       0x80000000,
-       0x00104120,
-       0x00000200,
-       0xAC255F80,
-       0xF1C71C71,
-       0x14F1690D,
-       0x1A041414,
-       0x00D00000,
-       0x14864000,
-       0x59647A05,
-       0xBA28A3D8,
-       0xF511451E,
-       0x0341D348,
-       0x821A0000,
-       0x0000D000,
-       0x00000680,
-       0xD859647A,
-       0x1EBA28A3,
-       0x48F51145,
-       0x000341D3,
-       0x00080200,
-       0x00001000,
-       0x00080200,
-       0x00001000,
-       0x000A8000,
-       0x00075000,
-       0x541A8000,
-       0x03875011,
-       0x10000000,
-       0x00000000,
-       0x0080C000,
-       0x41000000,
-       0x04000002,
-       0x00820000,
-       0x00489800,
-       0x001A1A1A,
-       0x085506A0,
-       0x0000E1D4,
-       0x045506A0,
-       0x0000E1D4,
-       0x085506A0,
-       0x8000E1D4,
-       0x00000200,
-       0x00000004,
-       0x04000000,
-       0x00000009,
-       0x00002410,
-       0x00000040,
-       0x41000000,
-       0x00002082,
-       0x00000350,
-       0x000000DA,
-       0x00000100,
-       0x40000002,
-       0x00000100,
-       0x00000002,
-       0x022A8350,
-       0x000070EA,
-       0x86000000,
-       0x08000004,
-       0x00000000,
-       0x00482000,
-       0x21800000,
-       0x00101061,
-       0x021541A8,
-       0x00003875,
-       0x011541A8,
-       0x00003875,
-       0x021541A8,
-       0x20003875,
-       0x00000080,
-       0x00000001,
-       0x41000000,
-       0x00000002,
-       0x00FF0904,
-       0x00000000,
-       0x90400000,
-       0x00000820,
-       0xC0000001,
-       0x38D612AF,
-       0x86F8E38E,
-       0x0A0A78B4,
-       0x000D020A,
-       0x00006800,
-       0x028A4320,
-       0xEC2CB23D,
-       0x8F5D1451,
-       0xA47A88A2,
-       0x0001A0E9,
-       0x00410D00,
-       0x40000068,
-       0x3D000003,
-       0x51EC2CB2,
-       0xA28F5D14,
-       0xE9A47A88,
-       0x000001A0,
-       0x00000401,
-       0x00000008,
-       0x00000401,
-       0x00000008,
-       0x00000540,
-       0x000003A8,
-       0x08AA0D40,
-       0x8001C3A8,
-       0x0000007F,
-       0x00000000,
-       0x00004060,
-       0xE1208000,
-       0x0000001F,
-       0x00004100,
-};
index 4a7ed46221d5d1ae3385766eff46d992b18f8e7e..49a4feef31c9509469a1bcfc584d54162b94eb7d 100644 (file)
 /*
- * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ * Altera SoCFPGA IOCSR configuration
  *
- * SPDX-License-Identifier:    BSD-3-Clause
+ * SPDX-License-Identifier:    BSD-3-Clause
  */
 
-/* This file is generated by Preloader Generator */
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
 
-#ifndef _PRELOADER_IOCSR_CONFIG_H_
-#define _PRELOADER_IOCSR_CONFIG_H_
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     16766
 
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH     (764)
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH     (1719)
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH     (955)
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH     (16766)
+const unsigned long iocsr_scan_chain0_table[] = {
+       0x00000000,
+       0x00000000,
+       0x0FF00000,
+       0xC0000000,
+       0x0000003F,
+       0x00008000,
+       0x00020080,
+       0x08020000,
+       0x08000000,
+       0x00018020,
+       0x00000000,
+       0x00004000,
+       0x00010040,
+       0x04010000,
+       0x04000000,
+       0x00000010,
+       0x00004010,
+       0x00002000,
+       0x00020000,
+       0x02008000,
+       0x02000000,
+       0x00000008,
+       0x00002008,
+       0x00001000,
+};
 
-#endif /*_PRELOADER_IOCSR_CONFIG_H_*/
+const unsigned long iocsr_scan_chain1_table[] = {
+       0x000C0300,
+       0x10040000,
+       0x100000C0,
+       0x00000040,
+       0x00010040,
+       0x00008000,
+       0x00080000,
+       0x18060000,
+       0x18000000,
+       0x00000060,
+       0x00018060,
+       0x00004000,
+       0x00010040,
+       0x10000000,
+       0x04000000,
+       0x00000010,
+       0x00004010,
+       0x00002000,
+       0x06008020,
+       0x02008000,
+       0x01FE0000,
+       0xF8000000,
+       0x00000007,
+       0x00001000,
+       0x00004010,
+       0x01004000,
+       0x01000000,
+       0x00003004,
+       0x00001004,
+       0x00000800,
+       0x00000000,
+       0x00000000,
+       0x00800000,
+       0x00000002,
+       0x00002000,
+       0x00000400,
+       0x00000000,
+       0x00401000,
+       0x00000003,
+       0x00000000,
+       0x00000000,
+       0x00000200,
+       0x00600802,
+       0x00000000,
+       0x80200000,
+       0x80000600,
+       0x00000200,
+       0x00000100,
+       0x00300401,
+       0xC0100400,
+       0x40100000,
+       0x40000300,
+       0x000C0100,
+       0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+       0x80040100,
+       0x00000000,
+       0x0FF00000,
+       0x00000000,
+       0x0C010040,
+       0x00008000,
+       0x18020080,
+       0x00000000,
+       0x08000000,
+       0x00040020,
+       0x06018060,
+       0x00004000,
+       0x0C010040,
+       0x04010000,
+       0x00000030,
+       0x00000000,
+       0x03004010,
+       0x00002000,
+       0x06008020,
+       0x02008000,
+       0x02000018,
+       0x00006008,
+       0x01802008,
+       0x00001000,
+       0x03004010,
+       0x01004000,
+       0x0100000C,
+       0x00003004,
+       0x00C01004,
+       0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+       0x2C420D80,
+       0x082000FF,
+       0x0A804001,
+       0x07900000,
+       0x08020000,
+       0x00100000,
+       0x0A800000,
+       0x07900000,
+       0x08020000,
+       0x00100000,
+       0xC8800000,
+       0x00003001,
+       0x00C00722,
+       0x00000000,
+       0x00000021,
+       0x82000004,
+       0x05400000,
+       0x03C80000,
+       0x04010000,
+       0x00080000,
+       0x05400000,
+       0x03C80000,
+       0x05400000,
+       0x03C80000,
+       0xE4400000,
+       0x00001800,
+       0x00600391,
+       0x800E4400,
+       0x00000001,
+       0x40000002,
+       0x02A00000,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x72200000,
+       0x80000C00,
+       0x003001C8,
+       0xC0072200,
+       0x1C880000,
+       0x20000300,
+       0x00040000,
+       0x50670000,
+       0x00000070,
+       0x24590000,
+       0x00001000,
+       0xA0000034,
+       0x0D000001,
+       0x906808A2,
+       0xA2834024,
+       0x05141A00,
+       0x808A20D0,
+       0x34024906,
+       0x01A00A28,
+       0xA20D0000,
+       0x24906808,
+       0x00A28340,
+       0xD000001A,
+       0x06808A20,
+       0x10040000,
+       0x00200000,
+       0x10040000,
+       0x00200000,
+       0x15000000,
+       0x0F200000,
+       0x15000000,
+       0x0F200000,
+       0x01FE0000,
+       0x00000000,
+       0x01800E44,
+       0x00391000,
+       0x007F8006,
+       0x00000000,
+       0x0A800001,
+       0x07900000,
+       0x0A800000,
+       0x07900000,
+       0x0A800000,
+       0x07900000,
+       0x08020000,
+       0x00100000,
+       0xC8800000,
+       0x00003001,
+       0x00C00722,
+       0x00000FF0,
+       0x72200000,
+       0x80000C00,
+       0x05400000,
+       0x02480000,
+       0x04000000,
+       0x00080000,
+       0x05400000,
+       0x03C80000,
+       0x05400000,
+       0x03C80000,
+       0x6A1C0000,
+       0x00001800,
+       0x00600391,
+       0x800E4400,
+       0x1A870001,
+       0x40000600,
+       0x02A00040,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x02A00000,
+       0x01E40000,
+       0x72200000,
+       0x80000C00,
+       0x003001C8,
+       0xC0072200,
+       0x1C880000,
+       0x20000300,
+       0x00040000,
+       0x50670000,
+       0x00000070,
+       0x24590000,
+       0x00001000,
+       0xA0000034,
+       0x0D000001,
+       0x906808A2,
+       0xA2834024,
+       0x05141A00,
+       0x808A20D0,
+       0x34024906,
+       0x01A00040,
+       0xA20D0002,
+       0x24906808,
+       0x00A28340,
+       0xD005141A,
+       0x06808A20,
+       0x10040000,
+       0x00200000,
+       0x10040000,
+       0x00200000,
+       0x15000000,
+       0x0F200000,
+       0x15000000,
+       0x0F200000,
+       0x01FE0000,
+       0x00000000,
+       0x01800E44,
+       0x00391000,
+       0x007F8006,
+       0x00000000,
+       0x99300001,
+       0x34343400,
+       0xAA0D4000,
+       0x01C3A810,
+       0xAA0D4000,
+       0x01C3A808,
+       0xAA0D4000,
+       0x01C3A810,
+       0x00040100,
+       0x00000800,
+       0x00000000,
+       0x00001208,
+       0x00482000,
+       0x000001C1,
+       0x00000000,
+       0x00410482,
+       0x0006A000,
+       0x0001B400,
+       0x00020000,
+       0x00000400,
+       0x0002A000,
+       0x0001E400,
+       0x5506A000,
+       0x00E1D404,
+       0x00000000,
+       0xC880090C,
+       0x00003001,
+       0x90400000,
+       0x00000000,
+       0x2020C243,
+       0x2A835000,
+       0x0070EA04,
+       0x2A835000,
+       0x0070EA02,
+       0x2A835000,
+       0x0070EA04,
+       0x00010040,
+       0x00000200,
+       0x00000000,
+       0x00000482,
+       0x00120800,
+       0x00002000,
+       0x80000000,
+       0x00104120,
+       0x00000200,
+       0xAC255F80,
+       0xF1C71C71,
+       0x14F3690D,
+       0x1A041414,
+       0x00D00000,
+       0x14864000,
+       0x59647A05,
+       0xBA28A3D8,
+       0xF511451E,
+       0x0341D348,
+       0x821A0000,
+       0x0000D000,
+       0x04510680,
+       0xD859647A,
+       0x1EBA28A3,
+       0x48F51145,
+       0x000341D3,
+       0x00080200,
+       0x00001000,
+       0x00080200,
+       0x00001000,
+       0x000A8000,
+       0x00075000,
+       0x541A8000,
+       0x03875011,
+       0x10000000,
+       0x00000000,
+       0x0080C000,
+       0x41000000,
+       0x00003FC2,
+       0x00820000,
+       0xAA0D4000,
+       0x01C3A810,
+       0xAA0D4000,
+       0x01C3A808,
+       0xAA0D4000,
+       0x01C3A810,
+       0x00040100,
+       0x00000800,
+       0x00000000,
+       0x00001208,
+       0x00482000,
+       0x00008000,
+       0x00000000,
+       0x00410482,
+       0x0006A000,
+       0x0001B400,
+       0x00020000,
+       0x00000400,
+       0x00020080,
+       0x00000400,
+       0x5506A000,
+       0x00E1D404,
+       0x00000000,
+       0x0000090C,
+       0x00000010,
+       0x90400000,
+       0x00000000,
+       0x2020C243,
+       0x2A835000,
+       0x0070EA04,
+       0x2A835000,
+       0x0070EA02,
+       0x2A835000,
+       0x0070EA04,
+       0x00015000,
+       0x0000F200,
+       0x00000000,
+       0x00000482,
+       0x00120800,
+       0x00600391,
+       0x80000000,
+       0x00104120,
+       0x00000200,
+       0xAC255F80,
+       0xF1C71C71,
+       0x14F3690D,
+       0x1A041414,
+       0x00D00000,
+       0x14864000,
+       0x59647A05,
+       0xBA28A3D8,
+       0xF511451E,
+       0x8341D348,
+       0x821A0124,
+       0x0000D000,
+       0x00000680,
+       0xD859647A,
+       0x1EBA28A3,
+       0x48F51145,
+       0x000341D3,
+       0x00080200,
+       0x00001000,
+       0x00080200,
+       0x00001000,
+       0x000A8000,
+       0x00075000,
+       0x541A8000,
+       0x03875011,
+       0x10000000,
+       0x00000000,
+       0x0080C000,
+       0x41000000,
+       0x04000002,
+       0x00820000,
+       0xAA0D4000,
+       0x01C3A810,
+       0xAA0D4000,
+       0x01C3A808,
+       0xAA0D4000,
+       0x01C3A810,
+       0x00040100,
+       0x00000800,
+       0x00000000,
+       0x00001208,
+       0x00482000,
+       0x00008000,
+       0x00000000,
+       0x00410482,
+       0x0006A000,
+       0x0001B400,
+       0x00020000,
+       0x00000400,
+       0x0002A000,
+       0x0001E400,
+       0x5506A000,
+       0x00E1D404,
+       0x00000000,
+       0xC880090C,
+       0x00003001,
+       0x90400000,
+       0x00000000,
+       0x2020C243,
+       0x2A835000,
+       0x0070EA04,
+       0x2A835000,
+       0x0070EA02,
+       0x2A835000,
+       0x0070EA04,
+       0x00010040,
+       0x00000200,
+       0x00000000,
+       0x00000482,
+       0x00120800,
+       0x00002000,
+       0x80000000,
+       0x00104120,
+       0x00000200,
+       0xAC255F80,
+       0xF1C71C71,
+       0x14F3690D,
+       0x1A041414,
+       0x00D00000,
+       0x14864000,
+       0x59647A05,
+       0xBA28A3D8,
+       0xF511451E,
+       0x0341D348,
+       0x821A0000,
+       0x0000D000,
+       0x00000680,
+       0xD859647A,
+       0x1EBA28A3,
+       0x48F51145,
+       0x000341D3,
+       0x00080200,
+       0x00001000,
+       0x00080200,
+       0x00001000,
+       0x000A8000,
+       0x00075000,
+       0x541A8000,
+       0x03875011,
+       0x10000000,
+       0x00000000,
+       0x0080C000,
+       0x41000000,
+       0x04000002,
+       0x00820000,
+       0xAA0D4000,
+       0x01C3A810,
+       0xAA0D4000,
+       0x01C3A808,
+       0xAA0D4000,
+       0x01C3A810,
+       0x00040100,
+       0x00000800,
+       0x00000000,
+       0x00001208,
+       0x00482000,
+       0x00008000,
+       0x00000000,
+       0x00410482,
+       0x0006A000,
+       0x0001B400,
+       0x00020000,
+       0x00000400,
+       0x00020080,
+       0x00000400,
+       0x5506A000,
+       0x00E1D404,
+       0x00000000,
+       0x0000090C,
+       0x00000010,
+       0x90400000,
+       0x00000000,
+       0x2020C243,
+       0x2A835000,
+       0x0070EA04,
+       0x2A835000,
+       0x0070EA02,
+       0x2A835000,
+       0x0070EA04,
+       0x00010040,
+       0x00000200,
+       0x00000000,
+       0x00000482,
+       0x40120800,
+       0x00000070,
+       0x80000000,
+       0x00104120,
+       0x00000200,
+       0xAC255F80,
+       0xF1C71C71,
+       0x14F1690D,
+       0x1A041414,
+       0x00D00000,
+       0x14864000,
+       0x59647A05,
+       0xBA28A3D8,
+       0xF511451E,
+       0x0341D348,
+       0x821A0000,
+       0x0000D000,
+       0x00000680,
+       0xD859647A,
+       0x1EBA28A3,
+       0x48F51145,
+       0x000341D3,
+       0x00080200,
+       0x00001000,
+       0x00080200,
+       0x00001000,
+       0x000A8000,
+       0x00075000,
+       0x541A8000,
+       0x03875011,
+       0x10000000,
+       0x00000000,
+       0x0080C000,
+       0x41000000,
+       0x04000002,
+       0x00820000,
+       0x00489800,
+       0x001A1A1A,
+       0x085506A0,
+       0x0000E1D4,
+       0x045506A0,
+       0x0000E1D4,
+       0x085506A0,
+       0x8000E1D4,
+       0x00000200,
+       0x00000004,
+       0x04000000,
+       0x00000009,
+       0x00002410,
+       0x00000040,
+       0x41000000,
+       0x00002082,
+       0x00000350,
+       0x000000DA,
+       0x00000100,
+       0x40000002,
+       0x00000100,
+       0x00000002,
+       0x022A8350,
+       0x000070EA,
+       0x86000000,
+       0x08000004,
+       0x00000000,
+       0x00482000,
+       0x21800000,
+       0x00101061,
+       0x021541A8,
+       0x00003875,
+       0x011541A8,
+       0x00003875,
+       0x021541A8,
+       0x20003875,
+       0x00000080,
+       0x00000001,
+       0x41000000,
+       0x00000002,
+       0x00FF0904,
+       0x00000000,
+       0x90400000,
+       0x00000820,
+       0xC0000001,
+       0x38D612AF,
+       0x86F8E38E,
+       0x0A0A78B4,
+       0x000D020A,
+       0x00006800,
+       0x028A4320,
+       0xEC2CB23D,
+       0x8F5D1451,
+       0xA47A88A2,
+       0x0001A0E9,
+       0x00410D00,
+       0x40000068,
+       0x3D000003,
+       0x51EC2CB2,
+       0xA28F5D14,
+       0xE9A47A88,
+       0x000001A0,
+       0x00000401,
+       0x00000008,
+       0x00000401,
+       0x00000008,
+       0x00000540,
+       0x000003A8,
+       0x08AA0D40,
+       0x8001C3A8,
+       0x0000007F,
+       0x00000000,
+       0x00004060,
+       0xE1208000,
+       0x0000001F,
+       0x00004100,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.c b/board/altera/cyclone5-socdk/qts/pinmux_config.c
deleted file mode 100644 (file)
index cb58689..0000000
+++ /dev/null
@@ -1,214 +0,0 @@
-/* This file is generated by Preloader Generator */
-
-#include "pinmux_config.h"
-
-/* pin mux configuration data */
-unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
-       3, /* EMACIO0 */
-       3, /* EMACIO1 */
-       3, /* EMACIO2 */
-       3, /* EMACIO3 */
-       3, /* EMACIO4 */
-       3, /* EMACIO5 */
-       3, /* EMACIO6 */
-       3, /* EMACIO7 */
-       3, /* EMACIO8 */
-       3, /* EMACIO9 */
-       3, /* EMACIO10 */
-       3, /* EMACIO11 */
-       3, /* EMACIO12 */
-       3, /* EMACIO13 */
-       0, /* EMACIO14 */
-       0, /* EMACIO15 */
-       0, /* EMACIO16 */
-       0, /* EMACIO17 */
-       0, /* EMACIO18 */
-       0, /* EMACIO19 */
-       3, /* FLASHIO0 */
-       0, /* FLASHIO1 */
-       3, /* FLASHIO2 */
-       3, /* FLASHIO3 */
-       3, /* FLASHIO4 */
-       3, /* FLASHIO5 */
-       3, /* FLASHIO6 */
-       3, /* FLASHIO7 */
-       0, /* FLASHIO8 */
-       3, /* FLASHIO9 */
-       3, /* FLASHIO10 */
-       3, /* FLASHIO11 */
-       0, /* GENERALIO0 */
-       1, /* GENERALIO1 */
-       1, /* GENERALIO2 */
-       0, /* GENERALIO3 */
-       0, /* GENERALIO4 */
-       1, /* GENERALIO5 */
-       1, /* GENERALIO6 */
-       1, /* GENERALIO7 */
-       1, /* GENERALIO8 */
-       0, /* GENERALIO9 */
-       0, /* GENERALIO10 */
-       0, /* GENERALIO11 */
-       0, /* GENERALIO12 */
-       2, /* GENERALIO13 */
-       2, /* GENERALIO14 */
-       0, /* GENERALIO15 */
-       0, /* GENERALIO16 */
-       2, /* GENERALIO17 */
-       2, /* GENERALIO18 */
-       0, /* GENERALIO19 */
-       0, /* GENERALIO20 */
-       0, /* GENERALIO21 */
-       0, /* GENERALIO22 */
-       0, /* GENERALIO23 */
-       0, /* GENERALIO24 */
-       0, /* GENERALIO25 */
-       0, /* GENERALIO26 */
-       0, /* GENERALIO27 */
-       0, /* GENERALIO28 */
-       0, /* GENERALIO29 */
-       0, /* GENERALIO30 */
-       0, /* GENERALIO31 */
-       0, /* MIXED1IO0 */
-       1, /* MIXED1IO1 */
-       1, /* MIXED1IO2 */
-       1, /* MIXED1IO3 */
-       1, /* MIXED1IO4 */
-       0, /* MIXED1IO5 */
-       0, /* MIXED1IO6 */
-       0, /* MIXED1IO7 */
-       1, /* MIXED1IO8 */
-       1, /* MIXED1IO9 */
-       1, /* MIXED1IO10 */
-       1, /* MIXED1IO11 */
-       0, /* MIXED1IO12 */
-       0, /* MIXED1IO13 */
-       0, /* MIXED1IO14 */
-       1, /* MIXED1IO15 */
-       1, /* MIXED1IO16 */
-       1, /* MIXED1IO17 */
-       1, /* MIXED1IO18 */
-       0, /* MIXED1IO19 */
-       0, /* MIXED1IO20 */
-       0, /* MIXED1IO21 */
-       0, /* MIXED2IO0 */
-       0, /* MIXED2IO1 */
-       0, /* MIXED2IO2 */
-       0, /* MIXED2IO3 */
-       0, /* MIXED2IO4 */
-       0, /* MIXED2IO5 */
-       0, /* MIXED2IO6 */
-       0, /* MIXED2IO7 */
-       0, /* GPLINMUX48 */
-       0, /* GPLINMUX49 */
-       0, /* GPLINMUX50 */
-       0, /* GPLINMUX51 */
-       0, /* GPLINMUX52 */
-       0, /* GPLINMUX53 */
-       0, /* GPLINMUX54 */
-       0, /* GPLINMUX55 */
-       0, /* GPLINMUX56 */
-       0, /* GPLINMUX57 */
-       0, /* GPLINMUX58 */
-       0, /* GPLINMUX59 */
-       0, /* GPLINMUX60 */
-       0, /* GPLINMUX61 */
-       0, /* GPLINMUX62 */
-       0, /* GPLINMUX63 */
-       0, /* GPLINMUX64 */
-       0, /* GPLINMUX65 */
-       0, /* GPLINMUX66 */
-       0, /* GPLINMUX67 */
-       0, /* GPLINMUX68 */
-       0, /* GPLINMUX69 */
-       0, /* GPLINMUX70 */
-       1, /* GPLMUX0 */
-       1, /* GPLMUX1 */
-       1, /* GPLMUX2 */
-       1, /* GPLMUX3 */
-       1, /* GPLMUX4 */
-       1, /* GPLMUX5 */
-       1, /* GPLMUX6 */
-       1, /* GPLMUX7 */
-       1, /* GPLMUX8 */
-       1, /* GPLMUX9 */
-       1, /* GPLMUX10 */
-       1, /* GPLMUX11 */
-       1, /* GPLMUX12 */
-       1, /* GPLMUX13 */
-       1, /* GPLMUX14 */
-       1, /* GPLMUX15 */
-       1, /* GPLMUX16 */
-       1, /* GPLMUX17 */
-       1, /* GPLMUX18 */
-       1, /* GPLMUX19 */
-       1, /* GPLMUX20 */
-       1, /* GPLMUX21 */
-       1, /* GPLMUX22 */
-       1, /* GPLMUX23 */
-       1, /* GPLMUX24 */
-       1, /* GPLMUX25 */
-       1, /* GPLMUX26 */
-       1, /* GPLMUX27 */
-       1, /* GPLMUX28 */
-       1, /* GPLMUX29 */
-       1, /* GPLMUX30 */
-       1, /* GPLMUX31 */
-       1, /* GPLMUX32 */
-       1, /* GPLMUX33 */
-       1, /* GPLMUX34 */
-       1, /* GPLMUX35 */
-       1, /* GPLMUX36 */
-       1, /* GPLMUX37 */
-       1, /* GPLMUX38 */
-       1, /* GPLMUX39 */
-       1, /* GPLMUX40 */
-       1, /* GPLMUX41 */
-       1, /* GPLMUX42 */
-       1, /* GPLMUX43 */
-       1, /* GPLMUX44 */
-       1, /* GPLMUX45 */
-       1, /* GPLMUX46 */
-       1, /* GPLMUX47 */
-       1, /* GPLMUX48 */
-       1, /* GPLMUX49 */
-       1, /* GPLMUX50 */
-       1, /* GPLMUX51 */
-       1, /* GPLMUX52 */
-       1, /* GPLMUX53 */
-       1, /* GPLMUX54 */
-       1, /* GPLMUX55 */
-       1, /* GPLMUX56 */
-       1, /* GPLMUX57 */
-       1, /* GPLMUX58 */
-       1, /* GPLMUX59 */
-       1, /* GPLMUX60 */
-       1, /* GPLMUX61 */
-       1, /* GPLMUX62 */
-       1, /* GPLMUX63 */
-       1, /* GPLMUX64 */
-       1, /* GPLMUX65 */
-       1, /* GPLMUX66 */
-       1, /* GPLMUX67 */
-       1, /* GPLMUX68 */
-       1, /* GPLMUX69 */
-       1, /* GPLMUX70 */
-       0, /* NANDUSEFPGA */
-       0, /* UART0USEFPGA */
-       0, /* RGMII1USEFPGA */
-       0, /* SPIS0USEFPGA */
-       0, /* CAN0USEFPGA */
-       0, /* I2C0USEFPGA */
-       0, /* SDMMCUSEFPGA */
-       0, /* QSPIUSEFPGA */
-       0, /* SPIS1USEFPGA */
-       0, /* RGMII0USEFPGA */
-       0, /* UART1USEFPGA */
-       0, /* CAN1USEFPGA */
-       0, /* USB1USEFPGA */
-       0, /* I2C3USEFPGA */
-       0, /* I2C2USEFPGA */
-       0, /* I2C1USEFPGA */
-       0, /* SPIM1USEFPGA */
-       0, /* USB0USEFPGA */
-       0 /* SPIM0USEFPGA */
-};
index 21fabb0b2b42d322b5db0933f18c1c9996de1860..aa282e1705356dc634b3591368e0a3c4c5d57de9 100644 (file)
-/* This file is generated by Preloader Generator */
-
-#ifndef _PRELOADER_PINMUX_CONFIG_H_
-#define _PRELOADER_PINMUX_CONFIG_H_
-
 /*
- * State of enabling for which IP connected out through the muxing.
- * Value 1 mean the IP connection is muxed out
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier:    BSD-3-Clause
  */
-#define CONFIG_HPS_EMAC0               (1)
-#define CONFIG_HPS_EMAC1               (0)
-#define CONFIG_HPS_USB0                        (0)
-#define CONFIG_HPS_USB1                        (1)
-#define CONFIG_HPS_NAND                        (0)
-#define CONFIG_HPS_SDMMC               (1)
-#define CONFIG_HPS_QSPI                        (0)
-#define CONFIG_HPS_UART0               (1)
-#define CONFIG_HPS_UART1               (0)
-#define CONFIG_HPS_TRACE               (0)
-#define CONFIG_HPS_I2C0                        (1)
-#define CONFIG_HPS_I2C1                        (0)
-#define CONFIG_HPS_I2C2                        (0)
-#define CONFIG_HPS_I2C3                        (0)
-#define CONFIG_HPS_SPIM0               (0)
-#define CONFIG_HPS_SPIM1               (0)
-#define CONFIG_HPS_SPIS0               (0)
-#define CONFIG_HPS_SPIS1               (0)
-#define CONFIG_HPS_CAN0                        (1)
-#define CONFIG_HPS_CAN1                        (0)
-
-/* IP attribute value (which affected by pin muxing configuration) */
-#define CONFIG_HPS_SDMMC_BUSWIDTH      (8)
-
-/* 1 if the pins are connected out */
-#define CONFIG_HPS_QSPI_CS0            (0)
-#define CONFIG_HPS_QSPI_CS1            (0)
-#define CONFIG_HPS_QSPI_CS2            (0)
-#define CONFIG_HPS_QSPI_CS3            (0)
-
-/* UART */
-/* 1 means the pin is mux out or available */
-#define CONFIG_HPS_UART0_TX            (1)
-#define CONFIG_HPS_UART0_RX            (1)
-#define CONFIG_HPS_UART0_CTS           (0)
-#define CONFIG_HPS_UART0_RTS           (0)
-#define CONFIG_HPS_UART1_TX            (0)
-#define CONFIG_HPS_UART1_RX            (0)
-#define CONFIG_HPS_UART1_CTS           (0)
-#define CONFIG_HPS_UART1_RTS           (0)
 
-/* Pin mux data */
-#define CONFIG_HPS_PINMUX_NUM          (207)
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
 
-#endif /* _PRELOADER_PINMUX_CONFIG_H_ */
+unsigned long sys_mgr_init_table[] = {
+       3, /* EMACIO0 */
+       3, /* EMACIO1 */
+       3, /* EMACIO2 */
+       3, /* EMACIO3 */
+       3, /* EMACIO4 */
+       3, /* EMACIO5 */
+       3, /* EMACIO6 */
+       3, /* EMACIO7 */
+       3, /* EMACIO8 */
+       3, /* EMACIO9 */
+       3, /* EMACIO10 */
+       3, /* EMACIO11 */
+       3, /* EMACIO12 */
+       3, /* EMACIO13 */
+       0, /* EMACIO14 */
+       0, /* EMACIO15 */
+       0, /* EMACIO16 */
+       0, /* EMACIO17 */
+       0, /* EMACIO18 */
+       0, /* EMACIO19 */
+       3, /* FLASHIO0 */
+       0, /* FLASHIO1 */
+       3, /* FLASHIO2 */
+       3, /* FLASHIO3 */
+       3, /* FLASHIO4 */
+       3, /* FLASHIO5 */
+       3, /* FLASHIO6 */
+       3, /* FLASHIO7 */
+       0, /* FLASHIO8 */
+       3, /* FLASHIO9 */
+       3, /* FLASHIO10 */
+       3, /* FLASHIO11 */
+       0, /* GENERALIO0 */
+       1, /* GENERALIO1 */
+       1, /* GENERALIO2 */
+       0, /* GENERALIO3 */
+       0, /* GENERALIO4 */
+       1, /* GENERALIO5 */
+       1, /* GENERALIO6 */
+       1, /* GENERALIO7 */
+       1, /* GENERALIO8 */
+       0, /* GENERALIO9 */
+       0, /* GENERALIO10 */
+       0, /* GENERALIO11 */
+       0, /* GENERALIO12 */
+       2, /* GENERALIO13 */
+       2, /* GENERALIO14 */
+       0, /* GENERALIO15 */
+       0, /* GENERALIO16 */
+       2, /* GENERALIO17 */
+       2, /* GENERALIO18 */
+       0, /* GENERALIO19 */
+       0, /* GENERALIO20 */
+       0, /* GENERALIO21 */
+       0, /* GENERALIO22 */
+       0, /* GENERALIO23 */
+       0, /* GENERALIO24 */
+       0, /* GENERALIO25 */
+       0, /* GENERALIO26 */
+       0, /* GENERALIO27 */
+       0, /* GENERALIO28 */
+       0, /* GENERALIO29 */
+       0, /* GENERALIO30 */
+       0, /* GENERALIO31 */
+       0, /* MIXED1IO0 */
+       1, /* MIXED1IO1 */
+       1, /* MIXED1IO2 */
+       1, /* MIXED1IO3 */
+       1, /* MIXED1IO4 */
+       0, /* MIXED1IO5 */
+       0, /* MIXED1IO6 */
+       0, /* MIXED1IO7 */
+       1, /* MIXED1IO8 */
+       1, /* MIXED1IO9 */
+       1, /* MIXED1IO10 */
+       1, /* MIXED1IO11 */
+       0, /* MIXED1IO12 */
+       0, /* MIXED1IO13 */
+       0, /* MIXED1IO14 */
+       1, /* MIXED1IO15 */
+       1, /* MIXED1IO16 */
+       1, /* MIXED1IO17 */
+       1, /* MIXED1IO18 */
+       0, /* MIXED1IO19 */
+       0, /* MIXED1IO20 */
+       0, /* MIXED1IO21 */
+       0, /* MIXED2IO0 */
+       0, /* MIXED2IO1 */
+       0, /* MIXED2IO2 */
+       0, /* MIXED2IO3 */
+       0, /* MIXED2IO4 */
+       0, /* MIXED2IO5 */
+       0, /* MIXED2IO6 */
+       0, /* MIXED2IO7 */
+       0, /* GPLINMUX48 */
+       0, /* GPLINMUX49 */
+       0, /* GPLINMUX50 */
+       0, /* GPLINMUX51 */
+       0, /* GPLINMUX52 */
+       0, /* GPLINMUX53 */
+       0, /* GPLINMUX54 */
+       0, /* GPLINMUX55 */
+       0, /* GPLINMUX56 */
+       0, /* GPLINMUX57 */
+       0, /* GPLINMUX58 */
+       0, /* GPLINMUX59 */
+       0, /* GPLINMUX60 */
+       0, /* GPLINMUX61 */
+       0, /* GPLINMUX62 */
+       0, /* GPLINMUX63 */
+       0, /* GPLINMUX64 */
+       0, /* GPLINMUX65 */
+       0, /* GPLINMUX66 */
+       0, /* GPLINMUX67 */
+       0, /* GPLINMUX68 */
+       0, /* GPLINMUX69 */
+       0, /* GPLINMUX70 */
+       1, /* GPLMUX0 */
+       1, /* GPLMUX1 */
+       1, /* GPLMUX2 */
+       1, /* GPLMUX3 */
+       1, /* GPLMUX4 */
+       1, /* GPLMUX5 */
+       1, /* GPLMUX6 */
+       1, /* GPLMUX7 */
+       1, /* GPLMUX8 */
+       1, /* GPLMUX9 */
+       1, /* GPLMUX10 */
+       1, /* GPLMUX11 */
+       1, /* GPLMUX12 */
+       1, /* GPLMUX13 */
+       1, /* GPLMUX14 */
+       1, /* GPLMUX15 */
+       1, /* GPLMUX16 */
+       1, /* GPLMUX17 */
+       1, /* GPLMUX18 */
+       1, /* GPLMUX19 */
+       1, /* GPLMUX20 */
+       1, /* GPLMUX21 */
+       1, /* GPLMUX22 */
+       1, /* GPLMUX23 */
+       1, /* GPLMUX24 */
+       1, /* GPLMUX25 */
+       1, /* GPLMUX26 */
+       1, /* GPLMUX27 */
+       1, /* GPLMUX28 */
+       1, /* GPLMUX29 */
+       1, /* GPLMUX30 */
+       1, /* GPLMUX31 */
+       1, /* GPLMUX32 */
+       1, /* GPLMUX33 */
+       1, /* GPLMUX34 */
+       1, /* GPLMUX35 */
+       1, /* GPLMUX36 */
+       1, /* GPLMUX37 */
+       1, /* GPLMUX38 */
+       1, /* GPLMUX39 */
+       1, /* GPLMUX40 */
+       1, /* GPLMUX41 */
+       1, /* GPLMUX42 */
+       1, /* GPLMUX43 */
+       1, /* GPLMUX44 */
+       1, /* GPLMUX45 */
+       1, /* GPLMUX46 */
+       1, /* GPLMUX47 */
+       1, /* GPLMUX48 */
+       1, /* GPLMUX49 */
+       1, /* GPLMUX50 */
+       1, /* GPLMUX51 */
+       1, /* GPLMUX52 */
+       1, /* GPLMUX53 */
+       1, /* GPLMUX54 */
+       1, /* GPLMUX55 */
+       1, /* GPLMUX56 */
+       1, /* GPLMUX57 */
+       1, /* GPLMUX58 */
+       1, /* GPLMUX59 */
+       1, /* GPLMUX60 */
+       1, /* GPLMUX61 */
+       1, /* GPLMUX62 */
+       1, /* GPLMUX63 */
+       1, /* GPLMUX64 */
+       1, /* GPLMUX65 */
+       1, /* GPLMUX66 */
+       1, /* GPLMUX67 */
+       1, /* GPLMUX68 */
+       1, /* GPLMUX69 */
+       1, /* GPLMUX70 */
+       0, /* NANDUSEFPGA */
+       0, /* UART0USEFPGA */
+       0, /* RGMII1USEFPGA */
+       0, /* SPIS0USEFPGA */
+       0, /* CAN0USEFPGA */
+       0, /* I2C0USEFPGA */
+       0, /* SDMMCUSEFPGA */
+       0, /* QSPIUSEFPGA */
+       0, /* SPIS1USEFPGA */
+       0, /* RGMII0USEFPGA */
+       0, /* UART1USEFPGA */
+       0, /* CAN1USEFPGA */
+       0, /* USB1USEFPGA */
+       0, /* I2C3USEFPGA */
+       0, /* I2C2USEFPGA */
+       0, /* I2C1USEFPGA */
+       0, /* SPIM1USEFPGA */
+       0, /* USB0USEFPGA */
+       0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
index 7cd25df61456981a8cbff272dcaf00a75f0c982f..3d621ed9c15f42ff351c8c724c40a66792ead7f8 100644 (file)
 /*
- * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ * Altera SoCFPGA Clock and PLL configuration
  *
- * SPDX-License-Identifier:    BSD-3-Clause
+ * SPDX-License-Identifier:    BSD-3-Clause
  */
 
-/* This file is generated by Preloader Generator */
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
 
-#ifndef _PRELOADER_PLL_CONFIG_H_
-#define _PRELOADER_PLL_CONFIG_H_
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
 
-/* PLL configuration data */
-/* Main PLL */
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM                        (0)
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER                        (63)
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT               (0)
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT              (0)
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT             (0)
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT          (511)
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT     (511)
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT       (15)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK          (1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK          (1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK          (1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK          (1)
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK          (0)
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK            (1)
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK                (0)
-/*
- * To tell where is the clock source:
- * 0 = MAINPLL
- * 1 = PERIPHPLL
- */
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP               (1)
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP               (1)
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
 
-/* Peripheral PLL */
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM                 (1)
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER                 (79)
-/*
- * To tell where is the VCOs source:
- * 0 = EOSC1
- * 1 = EOSC2
- * 2 = F2S
- */
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC                  (0)
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT              (3)
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT              (511)
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT            (511)
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT       (4)
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT            (4)
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT           (511)
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK                        (0)
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK               (4)
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK               (1)
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK               (1)
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK         (6249)
-/*
- * To tell where is the clock source:
- * 0 = F2S_PERIPH_REF_CLK
- * 1 = MAIN_CLK
- * 2 = PERIPH_CLK
- */
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC                 (2)
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND                  (2)
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI                  (1)
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
 
-/* SDRAM PLL */
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM                 (2)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER                 (79)
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
 
-/*
- * To tell where is the VCOs source:
- * 0 = EOSC1
- * 1 = EOSC2
- * 2 = F2S
- */
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC                  (0)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT             (1)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE           (0)
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT           (0)
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE         (0)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT              (1)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE            (4)
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT           (5)
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE         (0)
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 100000000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
 
-/* Info for driver */
-#define CONFIG_HPS_CLK_OSC1_HZ                 (25000000)
-#define CONFIG_HPS_CLK_OSC2_HZ                 (25000000)
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ          0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ          0
-#define CONFIG_HPS_CLK_MAINVCO_HZ              (1600000000)
-#define CONFIG_HPS_CLK_PERVCO_HZ               (1000000000)
-#define CONFIG_HPS_CLK_SDRVCO_HZ               (666666666)
-#define CONFIG_HPS_CLK_EMAC0_HZ                        (250000000)
-#define CONFIG_HPS_CLK_EMAC1_HZ                        (250000000)
-#define CONFIG_HPS_CLK_USBCLK_HZ               (200000000)
-#define CONFIG_HPS_CLK_NAND_HZ                 (50000000)
-#define CONFIG_HPS_CLK_SDMMC_HZ                        (200000000)
-#define CONFIG_HPS_CLK_QSPI_HZ                 (400000000)
-#define CONFIG_HPS_CLK_SPIM_HZ                 (200000000)
-#define CONFIG_HPS_CLK_CAN0_HZ                 (100000000)
-#define CONFIG_HPS_CLK_CAN1_HZ                 (100000000)
-#define CONFIG_HPS_CLK_GPIODB_HZ               (32000)
-#define CONFIG_HPS_CLK_L4_MP_HZ                        (100000000)
-#define CONFIG_HPS_CLK_L4_SP_HZ                        (100000000)
 
-#endif /* _PRELOADER_PLL_CONFIG_H_ */
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
index 15df808188382d53a0aa688b933ee4e465649345..37c147645285b631238f88eba4b7ce5f98902d34 100644 (file)
 /*
- * Copyright Altera Corporation (C) 2012-2015
+ * Altera SoCFPGA SDRAM configuration
  *
- * SPDX-License-Identifier:    BSD-3-Clause
+ * SPDX-License-Identifier:    BSD-3-Clause
  */
 
-/* This file is autogenerated from tools provided by Altera.*/
-#ifndef __SDRAM_CONFIG_H
-#define __SDRAM_CONFIG_H
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
 
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               1
 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             40
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        14
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            3120
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES       0
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES   8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS               10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK           3
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH             2
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE                        0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
 #define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY         0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0        0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32       0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64       0x0101
 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0   0x21084210
 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32  0x1EF84
 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0    0x2020
 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14   0x0
 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46   0xF800
 #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0               0x200
-
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH           0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP             0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP             0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN               0
 #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP             0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA          0
 #define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP             0x980543
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR             0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0      0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32     0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0       0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4      0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36     0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
-0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
-0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
-0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED      0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED     0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED   0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST                     0
 
-#endif /*#ifndef__SDRAM_CONFIG_H*/
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1        0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1  0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2  0x10
+#define RW_MGR_ACTIVATE_1      0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE        0x48
+#define RW_MGR_GUARANTEED_READ 0x4B
+#define RW_MGR_GUARANTEED_READ_CONT    0x53
+#define RW_MGR_GUARANTEED_WRITE        0x17
+#define RW_MGR_GUARANTEED_WRITE_WAIT0  0x1A
+#define RW_MGR_GUARANTEED_WRITE_WAIT1  0x1E
+#define RW_MGR_GUARANTEED_WRITE_WAIT2  0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT3  0x1C
+#define RW_MGR_IDLE    0x00
+#define RW_MGR_IDLE_LOOP1      0x7C
+#define RW_MGR_IDLE_LOOP2      0x7B
+#define RW_MGR_INIT_RESET_0_CKE_0      0x6E
+#define RW_MGR_INIT_RESET_1_CKE_0      0x73
+#define RW_MGR_LFSR_WR_RD_BANK_0       0x21
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA  0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS   0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP   0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT  0x31
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1  0x20
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0    0x35
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA       0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS        0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP        0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT       0x45
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1       0x34
+#define RW_MGR_MRS0_DLL_RESET  0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR     0x08
+#define RW_MGR_MRS0_USER       0x07
+#define RW_MGR_MRS0_USER_MIRR  0x0C
+#define RW_MGR_MRS1    0x03
+#define RW_MGR_MRS1_MIRR       0x09
+#define RW_MGR_MRS2    0x04
+#define RW_MGR_MRS2_MIRR       0x0A
+#define RW_MGR_MRS3    0x05
+#define RW_MGR_MRS3_MIRR       0x0B
+#define RW_MGR_PRECHARGE_ALL   0x12
+#define RW_MGR_READ_B2B        0x58
+#define RW_MGR_READ_B2B_WAIT1  0x60
+#define RW_MGR_READ_B2B_WAIT2  0x6A
+#define RW_MGR_REFRESH_ALL     0x14
+#define RW_MGR_RETURN  0x01
+#define RW_MGR_SGLE_READ       0x7E
+#define RW_MGR_ZQCL    0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET     7
+#define CALIB_VFIFO_OFFSET     5
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP        25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP   312
+#define IO_DLL_CHAIN_LENGTH    8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX    31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX    7
+#define IO_DQS_IN_DELAY_MAX    31
+#define IO_DQS_IN_RESERVE      4
+#define IO_DQS_OUT_RESERVE     6
+#define IO_IO_IN_DELAY_MAX     31
+#define IO_IO_OUT1_DELAY_MAX   31
+#define IO_IO_OUT2_DELAY_MAX   0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH        5
+#define READ_VALID_FIFO_SIZE   16
+#define REG_FILE_INIT_SEQ_SIGNATURE    0x55550483
+#define RW_MGR_MEM_ADDRESS_MIRRORING   0
+#define RW_MGR_MEM_DATA_MASK_WIDTH     5
+#define RW_MGR_MEM_DATA_WIDTH  40
+#define RW_MGR_MEM_DQ_PER_READ_DQS     8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS    8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH   5
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH  5
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM       1
+#define RW_MGR_MEM_NUMBER_OF_RANKS     1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS        1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH        5
+#define TINIT_CNTR0_VAL        132
+#define TINIT_CNTR1_VAL        32
+#define TINIT_CNTR2_VAL        32
+#define TRESET_CNTR0_VAL       132
+#define TRESET_CNTR1_VAL       99
+#define TRESET_CNTR2_VAL       10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] ={
+       0x20700000,
+       0x20780000,
+       0x10080431,
+       0x10080530,
+       0x10090004,
+       0x100a0008,
+       0x100b0000,
+       0x10380400,
+       0x10080449,
+       0x100804c8,
+       0x100a0004,
+       0x10090010,
+       0x100b0000,
+       0x30780000,
+       0x38780000,
+       0x30780000,
+       0x10680000,
+       0x106b0000,
+       0x10280400,
+       0x10480000,
+       0x1c980000,
+       0x1c9b0000,
+       0x1c980008,
+       0x1c9b0008,
+       0x38f80000,
+       0x3cf80000,
+       0x38780000,
+       0x18180000,
+       0x18980000,
+       0x13580000,
+       0x135b0000,
+       0x13580008,
+       0x135b0008,
+       0x33780000,
+       0x10580008,
+       0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] ={
+       0x80000,
+       0x80680,
+       0x8180,
+       0x8200,
+       0x8280,
+       0x8300,
+       0x8380,
+       0x8100,
+       0x8480,
+       0x8500,
+       0x8580,
+       0x8600,
+       0x8400,
+       0x800,
+       0x8680,
+       0x880,
+       0xa680,
+       0x80680,
+       0x900,
+       0x80680,
+       0x980,
+       0x8680,
+       0x80680,
+       0xb68,
+       0xcce8,
+       0xae8,
+       0x8ce8,
+       0xb88,
+       0xec88,
+       0xa08,
+       0xac88,
+       0x80680,
+       0xce00,
+       0xcd80,
+       0xe700,
+       0xc00,
+       0x20ce0,
+       0x20ce0,
+       0x20ce0,
+       0x20ce0,
+       0xd00,
+       0x680,
+       0x680,
+       0x680,
+       0x680,
+       0x60e80,
+       0x61080,
+       0x61080,
+       0x61080,
+       0xa680,
+       0x8680,
+       0x80680,
+       0xce00,
+       0xcd80,
+       0xe700,
+       0xc00,
+       0x30ce0,
+       0x30ce0,
+       0x30ce0,
+       0x30ce0,
+       0xd00,
+       0x680,
+       0x680,
+       0x680,
+       0x680,
+       0x70e80,
+       0x71080,
+       0x71080,
+       0x71080,
+       0xa680,
+       0x8680,
+       0x80680,
+       0x1158,
+       0x6d8,
+       0x80680,
+       0x1168,
+       0x7e8,
+       0x7e8,
+       0x87e8,
+       0x40fe8,
+       0x410e8,
+       0x410e8,
+       0x410e8,
+       0x1168,
+       0x7e8,
+       0x7e8,
+       0xa7e8,
+       0x80680,
+       0x40e88,
+       0x41088,
+       0x41088,
+       0x41088,
+       0x40f68,
+       0x410e8,
+       0x410e8,
+       0x410e8,
+       0xa680,
+       0x40fe8,
+       0x410e8,
+       0x410e8,
+       0x410e8,
+       0x41008,
+       0x41088,
+       0x41088,
+       0x41088,
+       0x1100,
+       0xc680,
+       0x8680,
+       0xe680,
+       0x80680,
+       0x0,
+       0x0,
+       0xa000,
+       0x8000,
+       0x80000,
+       0x80,
+       0x80,
+       0x80,
+       0x80,
+       0xa080,
+       0x8080,
+       0x80080,
+       0x9180,
+       0x8680,
+       0xa680,
+       0x80680,
+       0x40f08,
+       0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/altera/cyclone5-socdk/qts/sequencer_auto.h b/board/altera/cyclone5-socdk/qts/sequencer_auto.h
deleted file mode 100644 (file)
index d3c2251..0000000
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier:    BSD-3-Clause
- */
-
-
-#define RW_MGR_READ_B2B_WAIT2 0x6A
-#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
-#define RW_MGR_REFRESH_ALL 0x14
-#define RW_MGR_ZQCL 0x06
-#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
-#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
-#define RW_MGR_ACTIVATE_0_AND_1 0x0D
-#define RW_MGR_MRS2_MIRR 0x0A
-#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
-#define RW_MGR_ACTIVATE_1 0x0F
-#define RW_MGR_MRS2 0x04
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
-#define RW_MGR_MRS1 0x03
-#define RW_MGR_IDLE_LOOP1 0x7C
-#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
-#define RW_MGR_MRS3 0x05
-#define RW_MGR_IDLE_LOOP2 0x7B
-#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
-#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
-#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
-#define RW_MGR_RDIMM_CMD 0x7A
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
-#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
-#define RW_MGR_GUARANTEED_READ_CONT 0x53
-#define RW_MGR_MRS3_MIRR 0x0B
-#define RW_MGR_IDLE 0x00
-#define RW_MGR_READ_B2B 0x58
-#define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
-#define RW_MGR_GUARANTEED_WRITE 0x17
-#define RW_MGR_PRECHARGE_ALL 0x12
-#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
-#define RW_MGR_SGLE_READ 0x7E
-#define RW_MGR_MRS0_USER_MIRR 0x0C
-#define RW_MGR_RETURN 0x01
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
-#define RW_MGR_MRS0_USER 0x07
-#define RW_MGR_GUARANTEED_READ 0x4B
-#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
-#define RW_MGR_INIT_RESET_1_CKE_0 0x73
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
-#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
-#define RW_MGR_MRS0_DLL_RESET 0x02
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
-#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
-#define RW_MGR_CLEAR_DQS_ENABLE 0x48
-#define RW_MGR_MRS1_MIRR 0x09
-#define RW_MGR_READ_B2B_WAIT1 0x60
-#define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
-#define RW_MGR_CONTENT_REFRESH_ALL 0x000980
-#define RW_MGR_CONTENT_ZQCL 0x008380
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
-#define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
-#define RW_MGR_CONTENT_MRS2_MIRR 0x008580
-#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
-#define RW_MGR_CONTENT_ACTIVATE_1 0x000880
-#define RW_MGR_CONTENT_MRS2 0x008280
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
-#define RW_MGR_CONTENT_MRS1 0x008200
-#define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
-#define RW_MGR_CONTENT_MRS3 0x008300
-#define RW_MGR_CONTENT_IDLE_LOOP2 0x008680
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
-#define RW_MGR_CONTENT_RDIMM_CMD 0x009180
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
-#define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
-#define RW_MGR_CONTENT_MRS3_MIRR 0x008600
-#define RW_MGR_CONTENT_IDLE 0x080000
-#define RW_MGR_CONTENT_READ_B2B 0x040E88
-#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
-#define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
-#define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
-#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
-#define RW_MGR_CONTENT_SGLE_READ 0x040F08
-#define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
-#define RW_MGR_CONTENT_RETURN 0x080680
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
-#define RW_MGR_CONTENT_MRS0_USER 0x008100
-#define RW_MGR_CONTENT_GUARANTEED_READ 0x001168
-#define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
-#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
-#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
-#define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
-#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
-#define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
-#define RW_MGR_CONTENT_MRS1_MIRR 0x008500
-#define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
-
diff --git a/board/altera/cyclone5-socdk/qts/sequencer_auto_ac_init.h b/board/altera/cyclone5-socdk/qts/sequencer_auto_ac_init.h
deleted file mode 100644 (file)
index 0d26281..0000000
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier:    BSD-3-Clause
- */
-
-const uint32_t ac_rom_init[] = {
-       0x20700000,
-       0x20780000,
-       0x10080431,
-       0x10080530,
-       0x10090004,
-       0x100a0008,
-       0x100b0000,
-       0x10380400,
-       0x10080449,
-       0x100804c8,
-       0x100a0004,
-       0x10090010,
-       0x100b0000,
-       0x30780000,
-       0x38780000,
-       0x30780000,
-       0x10680000,
-       0x106b0000,
-       0x10280400,
-       0x10480000,
-       0x1c980000,
-       0x1c9b0000,
-       0x1c980008,
-       0x1c9b0008,
-       0x38f80000,
-       0x3cf80000,
-       0x38780000,
-       0x18180000,
-       0x18980000,
-       0x13580000,
-       0x135b0000,
-       0x13580008,
-       0x135b0008,
-       0x33780000,
-       0x10580008,
-       0x10780000
-};
diff --git a/board/altera/cyclone5-socdk/qts/sequencer_auto_inst_init.h b/board/altera/cyclone5-socdk/qts/sequencer_auto_inst_init.h
deleted file mode 100644 (file)
index 2b4c78f..0000000
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier:    BSD-3-Clause
- */
-
-const u32 inst_rom_init[] = {
-       0x80000,
-       0x80680,
-       0x8180,
-       0x8200,
-       0x8280,
-       0x8300,
-       0x8380,
-       0x8100,
-       0x8480,
-       0x8500,
-       0x8580,
-       0x8600,
-       0x8400,
-       0x800,
-       0x8680,
-       0x880,
-       0xa680,
-       0x80680,
-       0x900,
-       0x80680,
-       0x980,
-       0x8680,
-       0x80680,
-       0xb68,
-       0xcce8,
-       0xae8,
-       0x8ce8,
-       0xb88,
-       0xec88,
-       0xa08,
-       0xac88,
-       0x80680,
-       0xce00,
-       0xcd80,
-       0xe700,
-       0xc00,
-       0x20ce0,
-       0x20ce0,
-       0x20ce0,
-       0x20ce0,
-       0xd00,
-       0x680,
-       0x680,
-       0x680,
-       0x680,
-       0x60e80,
-       0x61080,
-       0x61080,
-       0x61080,
-       0xa680,
-       0x8680,
-       0x80680,
-       0xce00,
-       0xcd80,
-       0xe700,
-       0xc00,
-       0x30ce0,
-       0x30ce0,
-       0x30ce0,
-       0x30ce0,
-       0xd00,
-       0x680,
-       0x680,
-       0x680,
-       0x680,
-       0x70e80,
-       0x71080,
-       0x71080,
-       0x71080,
-       0xa680,
-       0x8680,
-       0x80680,
-       0x1158,
-       0x6d8,
-       0x80680,
-       0x1168,
-       0x7e8,
-       0x7e8,
-       0x87e8,
-       0x40fe8,
-       0x410e8,
-       0x410e8,
-       0x410e8,
-       0x1168,
-       0x7e8,
-       0x7e8,
-       0xa7e8,
-       0x80680,
-       0x40e88,
-       0x41088,
-       0x41088,
-       0x41088,
-       0x40f68,
-       0x410e8,
-       0x410e8,
-       0x410e8,
-       0xa680,
-       0x40fe8,
-       0x410e8,
-       0x410e8,
-       0x410e8,
-       0x41008,
-       0x41088,
-       0x41088,
-       0x41088,
-       0x1100,
-       0xc680,
-       0x8680,
-       0xe680,
-       0x80680,
-       0x0,
-       0x0,
-       0xa000,
-       0x8000,
-       0x80000,
-       0x80,
-       0x80,
-       0x80,
-       0x80,
-       0xa080,
-       0x8080,
-       0x80080,
-       0x9180,
-       0x8680,
-       0xa680,
-       0x80680,
-       0x40f08,
-       0x80680
-};
diff --git a/board/altera/cyclone5-socdk/qts/sequencer_defines.h b/board/altera/cyclone5-socdk/qts/sequencer_defines.h
deleted file mode 100644 (file)
index 27ace02..0000000
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier:    BSD-3-Clause
- */
-
-#ifndef _SEQUENCER_DEFINES_H_
-#define _SEQUENCER_DEFINES_H_
-
-#define AC_ROM_MR1_MIRR 0000000000100
-#define AC_ROM_MR1_OCD_ENABLE
-#define AC_ROM_MR2_MIRR 0000000010000
-#define AC_ROM_MR3_MIRR 0000000000000
-#define AC_ROM_MR0_CALIB
-#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000
-#define AC_ROM_MR0_DLL_RESET 0010100110000
-#define AC_ROM_MR0_MIRR 0010001001001
-#define AC_ROM_MR0 0010000110001
-#define AC_ROM_MR1 0000000000100
-#define AC_ROM_MR2 0000000001000
-#define AC_ROM_MR3 0000000000000
-#define AFI_CLK_FREQ 401
-#define AFI_RATE_RATIO 1
-#define AVL_CLK_FREQ 67
-#define BFM_MODE 0
-#define BURST2 0
-#define CALIB_LFIFO_OFFSET 7
-#define CALIB_VFIFO_OFFSET 5
-#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
-#define ENABLE_SUPER_QUICK_CALIBRATION 0
-#define GUARANTEED_READ_BRINGUP_TEST 0
-#define HARD_PHY 1
-#define HARD_VFIFO 1
-#define HPS_HW 1
-#define HR_DDIO_OUT_HAS_THREE_REGS 0
-#define IO_DELAY_PER_DCHAIN_TAP 25
-#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
-#define IO_DELAY_PER_OPA_TAP 312
-#define IO_DLL_CHAIN_LENGTH 8
-#define IO_DM_OUT_RESERVE 0
-#define IO_DQDQS_OUT_PHASE_MAX 0
-#define IO_DQS_EN_DELAY_MAX 31
-#define IO_DQS_EN_DELAY_OFFSET 0
-#define IO_DQS_EN_PHASE_MAX 7
-#define IO_DQS_IN_DELAY_MAX 31
-#define IO_DQS_IN_RESERVE 4
-#define IO_DQS_OUT_RESERVE 6
-#define IO_DQ_OUT_RESERVE 0
-#define IO_IO_IN_DELAY_MAX 31
-#define IO_IO_OUT1_DELAY_MAX 31
-#define IO_IO_OUT2_DELAY_MAX 0
-#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
-#define MARGIN_VARIATION_TEST 0
-#define MAX_LATENCY_COUNT_WIDTH 5
-#define MEM_ADDR_WIDTH 13
-#define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483
-#define RW_MGR_MEM_ADDRESS_MIRRORING 0
-#define RW_MGR_MEM_ADDRESS_WIDTH 15
-#define RW_MGR_MEM_BANK_WIDTH 3
-#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
-#define RW_MGR_MEM_CLK_EN_WIDTH 1
-#define RW_MGR_MEM_CONTROL_WIDTH 1
-#define RW_MGR_MEM_DATA_MASK_WIDTH 5
-#define RW_MGR_MEM_DATA_WIDTH 40
-#define RW_MGR_MEM_DQ_PER_READ_DQS 8
-#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
-#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
-#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
-#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
-#define RW_MGR_MEM_NUMBER_OF_RANKS 1
-#define RW_MGR_MEM_ODT_WIDTH 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
-#define RW_MGR_MR0_BL 1
-#define RW_MGR_MR0_CAS_LATENCY 3
-#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
-#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
-#define SKEW_CALIBRATION 0
-#define TINIT_CNTR1_VAL 32
-#define TINIT_CNTR2_VAL 32
-#define TINIT_CNTR0_VAL 132
-#define TRESET_CNTR1_VAL 99
-#define TRESET_CNTR2_VAL 10
-#define TRESET_CNTR0_VAL 132
-
-#endif /* _SEQUENCER_DEFINES_H_ */