arm: socfpga: gen5: combine some init code for SPL and U-Boot
authorSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Mon, 13 Aug 2018 19:34:35 +0000 (21:34 +0200)
committerMarek Vasut <marex@denx.de>
Mon, 13 Aug 2018 20:35:06 +0000 (22:35 +0200)
Some of the code for low level system initialization in SPL's
board_init_f() and U-Boot's arch_early_init_r() is the same,
so let's combine it into a single function called from both.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
arch/arm/mach-socfpga/include/mach/misc.h
arch/arm/mach-socfpga/misc_gen5.c
arch/arm/mach-socfpga/spl_gen5.c

index 7fe77ac8d81b793a798e37494cae175bab30c976..218dd6b6e73512a41b92f331e57e79a678132a51 100644 (file)
@@ -27,6 +27,10 @@ unsigned int shared_uart_com_port(const void *blob);
 unsigned int uart_com_port(const void *blob);
 #endif
 
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
+void socfpga_sdram_remap_zero(void);
+#endif
+
 void do_bridge_reset(int enable);
 
 #endif /* _MISC_H_ */
index 848551c73f8ca64c5701aa0053d4777e2678188a..429c3d6cd590f953b2f30ab5fd4389362f57153e 100644 (file)
@@ -175,6 +175,22 @@ static void socfpga_nic301_slave_ns(void)
        writel(0x1, &nic301_regs->sdrdata);
 }
 
+void socfpga_sdram_remap_zero(void)
+{
+       socfpga_nic301_slave_ns();
+
+       /*
+        * Private components security:
+        * U-Boot : configure private timer, global timer and cpu component
+        * access as non secure for kernel stage (as required by Linux)
+        */
+       setbits_le32(&scu_regs->sacr, 0xfff);
+
+       /* Configure the L2 controller to make SDRAM start at 0 */
+       writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
+       writel(0x1, &pl310->pl310_addr_filter_start);
+}
+
 static u32 iswgrp_handoff[8];
 
 int arch_early_init_r(void)
@@ -195,18 +211,7 @@ int arch_early_init_r(void)
 
        socfpga_bridges_reset(1);
 
-       socfpga_nic301_slave_ns();
-
-       /*
-        * Private components security:
-        * U-Boot : configure private timer, global timer and cpu component
-        * access as non secure for kernel stage (as required by Linux)
-        */
-       setbits_le32(&scu_regs->sacr, 0xfff);
-
-       /* Configure the L2 controller to make SDRAM start at 0 */
-       writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
-       writel(0x1, &pl310->pl310_addr_filter_start);
+       socfpga_sdram_remap_zero();
 
        /* Add device descriptor to FPGA device table */
        socfpga_fpga_add();
index 0e685f6ee5ea5ea38d94f12580f103a0a91e0c6e..be318cc0d9f98cba4307808e5798ceb6c3bfb7d1 100644 (file)
@@ -5,7 +5,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/pl310.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <image.h>
@@ -17,8 +16,6 @@
 #include <asm/arch/misc.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/sdram.h>
-#include <asm/arch/scu.h>
-#include <asm/arch/nic301.h>
 #include <asm/sections.h>
 #include <debug_uart.h>
 #include <fdtdec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
-       (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct scu_registers *scu_regs =
-       (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
-static struct nic301_registers *nic301_regs =
-       (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
 static const struct socfpga_system_manager *sysmgr_regs =
        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
@@ -72,16 +63,6 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
-static void socfpga_nic301_slave_ns(void)
-{
-       writel(0x1, &nic301_regs->lwhps2fpgaregs);
-       writel(0x1, &nic301_regs->hps2fpgaregs);
-       writel(0x1, &nic301_regs->acp);
-       writel(0x1, &nic301_regs->rom);
-       writel(0x1, &nic301_regs->ocram);
-       writel(0x1, &nic301_regs->sdrdata);
-}
-
 void board_init_f(ulong dummy)
 {
        const struct cm_config *cm_default_cfg = cm_get_default_config();
@@ -103,14 +84,7 @@ void board_init_f(ulong dummy)
 
        memset(__bss_start, 0, __bss_end - __bss_start);
 
-       socfpga_nic301_slave_ns();
-
-       /* Configure ARM MPU SNSAC register. */
-       setbits_le32(&scu_regs->sacr, 0xfff);
-
-       /* Remap SDRAM to 0x0 */
-       writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
-       writel(0x1, &pl310->pl310_addr_filter_start);
+       socfpga_sdram_remap_zero();
 
        debug("Freezing all I/O banks\n");
        /* freeze all IO banks */