clk: rk3399: Enable/Disable TCPHY clocks

Enable/Disable TCPHY clock for rk3399 platform.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index ce163aec5a131f764d88454e633c982a84bc8c5c..22c373a623ca96d2bc36aa45a23d61626f31cb4c 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1147,6 +1147,18 @@ static int rk3399_clk_enable(struct clk *clk)
        case HCLK_HOST1_ARB:
                rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
                break;
        case HCLK_HOST1_ARB:
                rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
                break;

+       case SCLK_UPHY0_TCPDPHY_REF:
+               rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
+               break;
+       case SCLK_UPHY0_TCPDCORE:
+               rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
+               break;
+       case SCLK_UPHY1_TCPDPHY_REF:
+               rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
+               break;
+       case SCLK_UPHY1_TCPDCORE:
+               rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
+               break;

        case SCLK_PCIEPHY_REF:
                rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
                break;
        case SCLK_PCIEPHY_REF:
                rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
                break;


@@ -1229,6 +1241,18 @@ static int rk3399_clk_disable(struct clk *clk)
        case HCLK_HOST1_ARB:
                rk_setreg(&priv->cru->clksel_con[20], BIT(8));
                break;
        case HCLK_HOST1_ARB:
                rk_setreg(&priv->cru->clksel_con[20], BIT(8));
                break;

+       case SCLK_UPHY0_TCPDPHY_REF:
+               rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
+               break;
+       case SCLK_UPHY0_TCPDCORE:
+               rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
+               break;
+       case SCLK_UPHY1_TCPDPHY_REF:
+               rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
+               break;
+       case SCLK_UPHY1_TCPDCORE:
+               rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
+               break;

        case SCLK_PCIEPHY_REF:
                rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
                break;
        case SCLK_PCIEPHY_REF:
                rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
                break;