armada-388-gp.dtb \
armada-385-amc.dtb \
armada-7040-db.dtb \
+ armada-7040-db-nand.dtb \
armada-8040-db.dtb \
armada-8040-mcbin.dtb \
armada-xp-gp.dtb \
aliases {
ethernet0 = ð0;
ethernet1 = ð1;
+ i2c0 = &i2c0;
spi1 = &spi1;
};
internal-regs {
i2c@11000 {
+ clock-frequency = <100000>;
+ u-boot,i2c-slave-addr = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
--- /dev/null
+/*
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada 7040 Development board platform
+ * Boot device: NAND, 0xE (SW3)
+ */
+
+#include "armada-7040.dtsi"
+
+/ {
+ model = "Marvell Armada 7040 DB board with NAND";
+ compatible = "marvell,armada7040-db-nand", "marvell,armada7040-db",
+ "marvell,armada7040", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cpm_i2c0;
+ spi0 = &cpm_spi1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&ap_pinctl {
+ /* MPP Bus:
+ * SDIO [0-5]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
+ 0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+
+&cpm_pcie2 {
+ status = "okay";
+};
+
+&cpm_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cpm_pinctl {
+ /* MPP Bus:
+ * AUDIO [0-5]
+ * GBE [6-11]
+ * SS_PWDN [12]
+ * NF_RBn [13]
+ * GPIO [14]
+ * DEV_BUS [15-27]
+ * SATA1 [28]
+ * UART0 [29-30]
+ * MSS_VTT_EN [31]
+ * SMI [32,34]
+ * XSMI [35-36]
+ * I2C [37-38]
+ * RGMII1 [44-55]
+ * SD [56-61]
+ * GPIO [62]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
+ 0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
+ 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x9 0xa
+ 0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
+ 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1
+ 0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
+ 0xe 0xe 0x0>;
+};
+
+&cpm_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpm_spi0_pins>;
+ status = "disabled";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <20000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+&cpm_sata0 {
+ status = "okay";
+};
+
+&cpm_usb3_0 {
+ status = "okay";
+};
+
+&cpm_usb3_1 {
+ status = "okay";
+};
+
+&cpm_comphy {
+ phy0 {
+ phy-type = <PHY_TYPE_SGMII2>;
+ phy-speed = <PHY_SPEED_3_125G>;
+ };
+
+ phy1 {
+ phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-speed = <PHY_SPEED_5G>;
+ };
+
+ phy2 {
+ phy-type = <PHY_TYPE_SGMII0>;
+ phy-speed = <PHY_SPEED_1_25G>;
+ };
+
+ phy3 {
+ phy-type = <PHY_TYPE_SATA1>;
+ phy-speed = <PHY_SPEED_5G>;
+ };
+
+ phy4 {
+ phy-type = <PHY_TYPE_USB3_HOST1>;
+ phy-speed = <PHY_SPEED_5G>;
+ };
+
+ phy5 {
+ phy-type = <PHY_TYPE_PEX2>;
+ phy-speed = <PHY_SPEED_5G>;
+ };
+};
+
+&cpm_nand {
+ status = "okay";
+};
+
+&cpm_utmi0 {
+ status = "okay";
+};
+
+&cpm_utmi1 {
+ status = "okay";
+};
+
+&ap_sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+};
+
+&cpm_sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+};
/*
* Device Tree file for Marvell Armada 7040 Development board platform
+ * Boot device: SPI NOR, 0x32 (SW3)
*/
#include "armada-7040.dtsi"
&cpm_comphy {
phy0 {
- phy-type = <PHY_TYPE_SGMII2>;
+ phy-type = <PHY_TYPE_SGMII1>;
phy-speed = <PHY_SPEED_1_25G>;
};
&cpm_pinctl {
/* MPP Bus:
- * [0-31] = 0xff: Keep default CP0_shared_pins:
- * [11] CLKOUT_MPP_11 (out)
- * [23] LINK_RD_IN_CP2CP (in)
- * [25] CLKOUT_MPP_25 (out)
- * [29] AVS_FB_IN_CP2CP (in)
- * [32,34] SMI
- * [31] GPIO: push button/Wake
- * [35-36] GPIO
- * [37-38] I2C
- * [40-41] SATA[0/1]_PRESENT_ACTIVEn
- * [42-43] XSMI
- * [44-55] RGMII1
- * [56-62] SD
+ * [0-31] = 0xff: Keep default CP0_shared_pins
+ * [11] CLKOUT_MPP_11 (out)
+ * [23] LINK_RD_IN_CP2CP (in)
+ * [25] CLKOUT_MPP_25 (out)
+ * [29] AVS_FB_IN_CP2CP (in)
+ * [32,34] GE_MDIO/MDC
+ * [33] GPIO: GE_INT#/push button/Wake
+ * [35] MSS_GPIO[3]: MSS_PWDN
+ * [36] MSS_GPIO[5]: MSS_VTT_EN
+ * [37-38] I2C0
+ * [39] PTP_CLK
+ * [40-41] SATA[0/1]_PRESENT_ACTIVEn
+ * [42-43] XG_MDC/XG_MDIO (XSMI)
+ * [44-55] RGMII1
+ * [56-62] SD
*/
- /* 0 1 2 3 4 5 6 7 8 9 */
+ /* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
- 0xff 0 7 0 7 0 0 2 2 0
- 0 0 8 8 1 1 1 1 1 1
- 1 1 1 1 1 1 0xe 0xe 0xe 0xe
- 0xe 0xe 0xe >;
+ 0xff 0xff 0x7 0x0 0x7 0xa 0xa 0x2 0x2 0x5
+ 0x9 0x9 0x8 0x8 0x1 0x1 0x1 0x1 0x1 0x1
+ 0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
+ 0xe 0xe 0xe>;
+};
+
+&cpm_comphy {
+ /* Serdes Configuration:
+ * Lane 0: PCIe0 (x1)
+ * Lane 1: SATA0
+ * Lane 2: SFI (10G)
+ * Lane 3: SATA1
+ * Lane 4: USB3_HOST1
+ * Lane 5: PCIe2 (x1)
+ */
+ phy0 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+ phy1 {
+ phy-type = <PHY_TYPE_SATA0>;
+ };
+ phy2 {
+ phy-type = <PHY_TYPE_SFI>;
+ };
+ phy3 {
+ phy-type = <PHY_TYPE_SATA1>;
+ };
+ phy4 {
+ phy-type = <PHY_TYPE_USB3_HOST1>;
+ };
+ phy5 {
+ phy-type = <PHY_TYPE_PEX2>;
+ };
+};
+
+/* CON6 on CP0 expansion */
+&cpm_pcie0 {
+ status = "okay";
+};
+
+&cpm_pcie1 {
+ status = "disabled";
};
/* CON5 on CP0 expansion */
status = "okay";
};
+&cpm_utmi0 {
+ status = "okay";
+};
+
+&cpm_utmi1 {
+ status = "okay";
+};
+
&cps_pinctl {
/* MPP Bus:
- * [0-11] RGMII0
- * [13-16] SPI1
- * [27,31] GE_MDIO/MDC
- * [32-62] = 0xff: Keep default CP1_shared_pins:
+ * [0-11] RGMII0
+ * [13-16] SPI1
+ * [27,31] GE_MDIO/MDC
+ * [28] SATA1_PRESENT_ACTIVEn
+ * [29-30] UART0
+ * [32-62] = 0xff: Keep default CP1_shared_pins
*/
- /* 0 1 2 3 4 5 6 7 8 9 */
+ /* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
- 0x3 0x3 0xff 0x3 0x3 0x3 0x3 0xff 0xff 0xff
- 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff
- 0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
+ 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
+ 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0x9 0xa
+ 0xA 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
- 0xff 0xff 0xff >;
+ 0xff 0xff 0xff>;
+};
+
+&cps_comphy {
+ /* Serdes Configuration:
+ * Lane 0: PCIe0 (x1)
+ * Lane 1: SATA0
+ * Lane 2: SFI (10G)
+ * Lane 3: SATA1
+ * Lane 4: PCIe1 (x1)
+ * Lane 5: PCIe2 (x1)
+ */
+ phy0 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+ phy1 {
+ phy-type = <PHY_TYPE_SATA0>;
+ };
+ phy2 {
+ phy-type = <PHY_TYPE_SFI>;
+ };
+ phy3 {
+ phy-type = <PHY_TYPE_SATA1>;
+ };
+ phy4 {
+ phy-type = <PHY_TYPE_PEX1>;
+ };
+ phy5 {
+ phy-type = <PHY_TYPE_PEX2>;
+ };
+};
+
+/* CON6 on CP1 expansion */
+&cps_pcie0 {
+ status = "okay";
+};
+
+&cps_pcie1 {
+ status = "okay";
};
/* CON5 on CP1 expansion */
status = "okay";
};
-&cpm_comphy {
- /*
- * Serdes Configuration:
- * Lane 0: SGMII2
- * Lane 1: USB3_HOST0
- * Lane 2: KR (10G)
- * Lane 3: SATA1
- * Lane 4: USB3_HOST1
- * Lane 5: PEX2x1
- */
- phy0 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
- };
-
- phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- };
-
- phy2 {
- phy-type = <PHY_TYPE_KR>;
- };
-
- phy3 {
- phy-type = <PHY_TYPE_SATA1>;
- };
-
- phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
- };
-
- phy5 {
- phy-type = <PHY_TYPE_PEX2>;
- };
-};
-
-&cps_comphy {
- /*
- * Serdes Configuration:
- * Lane 0: SGMII2
- * Lane 1: USB3_HOST0
- * Lane 2: KR (10G)
- * Lane 3: SATA1
- * Lane 4: Unconnected
- * Lane 5: PEX2x1
- */
- phy0 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
- };
-
- phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- };
-
- phy2 {
- phy-type = <PHY_TYPE_KR>;
- };
-
- phy3 {
- phy-type = <PHY_TYPE_SATA1>;
- };
-
- phy4 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
- };
-
- phy5 {
- phy-type = <PHY_TYPE_PEX2>;
- };
-};
-
-&cpm_utmi0 {
- status = "okay";
-};
-
-&cpm_utmi1 {
- status = "okay";
-};
-
&cps_utmi0 {
status = "okay";
};
* [54] 2.5G SFP LOS
* [55] Micro SD card detect
* [56-61] Micro SD
- * [62] CP1 KR SFP FAULT
+ * [62] CP1 SFI SFP FAULT
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
* Lane 1: PCIe0 (x4)
* Lane 2: PCIe0 (x4)
* Lane 3: PCIe0 (x4)
- * Lane 4: KR (10G)
+ * Lane 4: SFI (10G)
* Lane 5: SATA1
*/
phy0 {
phy-type = <PHY_TYPE_PEX0>;
};
phy4 {
- phy-type = <PHY_TYPE_KR>;
+ phy-type = <PHY_TYPE_SFI>;
};
phy5 {
phy-type = <PHY_TYPE_SATA1>;
&cps_comphy {
/*
* CP1 Serdes Configuration:
- * Lane 0: SGMII2
+ * Lane 0: SGMII1
* Lane 1: SATA 0
* Lane 2: USB HOST 0
* Lane 3: SATA1
- * Lane 4: KR (10G)
+ * Lane 4: SFI (10G)
* Lane 5: SGMII3
*/
phy0 {
- phy-type = <PHY_TYPE_SGMII2>;
+ phy-type = <PHY_TYPE_SGMII1>;
phy-speed = <PHY_SPEED_1_25G>;
};
phy1 {
phy-type = <PHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <PHY_TYPE_KR>;
+ phy-type = <PHY_TYPE_SFI>;
};
phy5 {
phy-type = <PHY_TYPE_SGMII3>;
reg = <0x580000 0x1000>, /* utmi-unit */
<0x440420 0x4>, /* usb-cfg */
<0x440440 0x4>; /* utmi-cfg */
- utmi-port = <UTMI_PHY_TO_USB_HOST0>;
+ utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
status = "disabled";
};
reg = <0x581000 0x1000>, /* utmi-unit */
<0x440420 0x4>, /* usb-cfg */
<0x440444 0x4>; /* utmi-cfg */
- utmi-port = <UTMI_PHY_TO_USB_HOST1>;
+ utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
status = "disabled";
};
dma-coherent;
status = "disabled";
};
+
+ cpm_nand: nand@720000 {
+ compatible = "marvell,mvebu-pxa3xx-nand";
+ reg = <0x720000 0x100>;
+ #address-cells = <1>;
+
+ clocks = <&cpm_syscon0 1 2>;
+ nand-enable-arbiter;
+ num-cs = <1>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ status = "disabled";
+ };
+
};
cpm_pcie0: pcie@f2600000 {
reg = <0x580000 0x1000>, /* utmi-unit */
<0x440420 0x4>, /* usb-cfg */
<0x440440 0x4>; /* utmi-cfg */
- utmi-port = <UTMI_PHY_TO_USB_HOST0>;
+ utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
status = "disabled";
};
};
&mmc1 {
status = "okay";
};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
spi2 = &spi2;
spi3 = &spi3;
spi4 = &qspi;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
};
memory {
#size-cells = <0>;
status = "disabled";
};
+ i2c0: i2c@2530000 {
+ compatible = "ti,keystone-i2c";
+ reg = <0x02530000 0x400>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2530400 {
+ compatible = "ti,keystone-i2c";
+ reg = <0x02530400 0x400>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2530800 {
+ compatible = "ti,keystone-i2c";
+ reg = <0x02530800 0x400>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
mmc0: mmc@23000000 {
compatible = "ti,omap4-hsmmc";
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
};
chosen {
config TARGET_K2HK_EVM
bool "TI Keystone 2 Kepler/Hawking EVM"
+ imply DM_I2C
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
+ imply DM_I2C
config TARGET_K2L_EVM
bool "TI Keystone 2 Lamar EVM"
+ imply DM_I2C
config TARGET_K2G_EVM
bool "TI Keystone 2 Galileo EVM"
select BOARD_LATE_INIT
select TI_I2C_BOARD_DETECT
+ imply DM_I2C
endchoice
#include <dm.h>
#include <fdtdec.h>
#include <libfdt.h>
+#include <pci.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/cpu.h>
/* Cause the SATA device to do its early init */
uclass_first_device(UCLASS_AHCI, &dev);
+#ifdef CONFIG_DM_PCI
+ /* Trigger PCIe devices detection */
+ pci_init();
+#endif
+
return 0;
}
reg &= ~(1 << RFU_SW_RESET_OFFSET);
writel(reg, RFU_GLOBAL_SW_RST);
}
+
+/*
+ * TODO - implement this functionality using platform
+ * clock driver once it gets available
+ * Return NAND clock in Hz
+ */
+u32 mvebu_get_nand_clock(void)
+{
+ unsigned long NAND_FLASH_CLK_CTRL = 0xF2440700UL;
+ unsigned long NF_CLOCK_SEL_MASK = 0x1;
+ u32 reg;
+
+ reg = readl(NAND_FLASH_CLK_CTRL);
+ if (reg & NF_CLOCK_SEL_MASK)
+ return 400 * 1000000;
+ else
+ return 250 * 1000000;
+}
#include "high_speed_env_spec.h"
#include "sys_env_lib.h"
-#define SERDES_VERION "2.0"
-
u8 selectors_serdes_rev1_map[LAST_SERDES_TYPE][MAX_SERDES_LANES] = {
/* 0 1 2 3 4 5 */
{0x1, 0x1, NA, NA, NA, NA}, /* PEX0 */
*/
struct cfg_seq serdes_seq_db[SERDES_LAST_SEQ];
-#define SERDES_VERION "2.0"
+#define SERDES_VERSION "2.0"
#define ENDED_OK "High speed PHY - Ended Successfully\n"
#define LINK_WAIT_CNTR 100
DEBUG_INIT_FULL_S("\n### ctrl_high_speed_serdes_phy_config ###\n");
DEBUG_INIT_S("High speed PHY - Version: ");
- DEBUG_INIT_S(SERDES_VERION);
+ DEBUG_INIT_S(SERDES_VERSION);
DEBUG_INIT_S("\n");
/* Init serdes sequences DB */
#include "high_speed_env_spec.h"
#include "board_env_spec.h"
-#define SERDES_VERION "2.1.5"
+#define SERDES_VERSION "2.1.5"
#define ENDED_OK "High speed PHY - Ended Successfully\n"
static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG;
if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
(1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
DEBUG_INIT_S("High speed PHY - Version: ");
- DEBUG_INIT_S(SERDES_VERION);
+ DEBUG_INIT_S(SERDES_VERSION);
DEBUG_INIT_S(" - 2nd boot - Skip\n");
return MV_OK;
}
DEBUG_INIT_S("High speed PHY - Version: ");
- DEBUG_INIT_S(SERDES_VERION);
+ DEBUG_INIT_S(SERDES_VERSION);
DEBUG_INIT_S(" (COM-PHY-V20)\n");
/*
*/
#include <common.h>
-#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <common.h>
#include <asm/omap_common.h>
+#include <dm/uclass.h>
#include <i2c.h>
#include "board_detect.h"
+#if defined(CONFIG_DM_I2C_COMPAT)
+/**
+ * ti_i2c_set_alen - Set chip's i2c address length
+ * @bus_addr - I2C bus number
+ * @dev_addr - I2C eeprom id
+ * @alen - I2C address length in bytes
+ *
+ * DM_I2C by default sets the address length to be used to 1. This
+ * function allows this address length to be changed to match the
+ * eeprom used for board detection.
+ */
+int __maybe_unused ti_i2c_set_alen(int bus_addr, int dev_addr, int alen)
+{
+ struct udevice *dev;
+ struct udevice *bus;
+ int rc;
+
+ rc = uclass_get_device_by_seq(UCLASS_I2C, bus_addr, &bus);
+ if (rc)
+ return rc;
+ rc = i2c_get_chip(bus, dev_addr, 1, &dev);
+ if (rc)
+ return rc;
+ rc = i2c_set_chip_offset_len(dev, alen);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+#else
+int __maybe_unused ti_i2c_set_alen(int bus_addr, int dev_addr, int alen)
+{
+ return 0;
+}
+#endif
+
/**
* ti_i2c_eeprom_init - Initialize an i2c bus and probe for a device
* @i2c_bus: i2c bus number to initialize
static int __maybe_unused ti_i2c_eeprom_read(int dev_addr, int offset,
uchar *ep, int epsize)
{
- return i2c_read(dev_addr, offset, 2, ep, epsize);
+ int bus_num, rc, alen;
+
+ bus_num = i2c_get_bus_num();
+
+ alen = 2;
+
+ rc = ti_i2c_set_alen(bus_num, dev_addr, alen);
+ if (rc)
+ return rc;
+
+ return i2c_read(dev_addr, offset, alen, ep, epsize);
}
/**
* Read the header first then only read the other contents.
*/
byte = 2;
+
+ rc = ti_i2c_set_alen(bus_addr, dev_addr, byte);
+ if (rc)
+ return rc;
+
rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4);
if (rc)
return rc;
* 1 byte address (some legacy boards need this..)
*/
byte = 1;
- if (rc)
+ if (rc) {
+ rc = ti_i2c_set_alen(bus_addr, dev_addr, byte);
+ if (rc)
+ return rc;
+
rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read,
4);
+ }
if (rc)
return rc;
}
#ifdef CONFIG_CMD_NAND
static int nand_burn_image(size_t image_size)
{
- int ret, block_size;
- nand_info_t *nand;
+ int ret;
+ uint32_t block_size;
+ struct mtd_info *nand;
int dev = nand_curr_device;
if ((dev < 0) || (dev >= CONFIG_SYS_MAX_NAND_DEVICE) ||
- (!nand_info[dev].name)) {
+ (!nand_info[dev]->name)) {
puts("\nno devices available\n");
return -ENOMEDIUM;
}
- nand = &nand_info[dev];
+ nand = nand_info[dev];
block_size = nand->erasesize;
/* Align U-Boot size to currently used blocksize */
printf("Done!\n");
/* Write the image to flash */
- printf("Writing image:...");
- printf("&image_size = 0x%p\n", (void *)&image_size);
+ printf("Writing %d bytes from 0x%lx to offset 0 ... ",
+ (int)image_size, get_load_addr());
ret = nand_write(nand, 0, &image_size, (void *)get_load_addr());
if (ret)
printf("Error!\n");
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MVEBU_ARMADA_8K=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db-nand"
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_NAND=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_BLOCK_CACHE=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_MVEBU_NAND_BOOT=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_PHYLIB=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_SMBIOS_MANUFACTURER=""
#include <common.h>
#include <i2c.h>
+#include <dm.h>
#include <asm/arch/hardware.h>
#include <asm/arch/i2c_defs.h>
#include <asm/io.h>
#include "davinci_i2c.h"
+#ifdef CONFIG_DM_I2C
+/* Information about i2c controller */
+struct i2c_bus {
+ int id;
+ uint speed;
+ struct i2c_regs *regs;
+};
+#endif
+
#define CHECK_NACK() \
do {\
if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
} \
} while (0)
-static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap);
-
-static int wait_for_bus(struct i2c_adapter *adap)
+static int _wait_for_bus(struct i2c_regs *i2c_base)
{
- struct i2c_regs *i2c_base = davinci_get_base(adap);
int stat, timeout;
REG(&(i2c_base->i2c_stat)) = 0xffff;
return 1;
}
-
-static int poll_i2c_irq(struct i2c_adapter *adap, int mask)
+static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask)
{
- struct i2c_regs *i2c_base = davinci_get_base(adap);
int stat, timeout;
for (timeout = 0; timeout < 10; timeout++) {
return stat | I2C_TIMEOUT;
}
-static void flush_rx(struct i2c_adapter *adap)
+static void _flush_rx(struct i2c_regs *i2c_base)
{
- struct i2c_regs *i2c_base = davinci_get_base(adap);
-
while (1) {
if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
break;
}
}
-static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
+static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base,
+ uint speed)
{
- struct i2c_regs *i2c_base = davinci_get_base(adap);
uint32_t div, psc;
psc = 2;
REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
- adap->speed = speed;
return 0;
}
-static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
+static void _davinci_i2c_init(struct i2c_regs *i2c_base,
+ uint speed, int slaveadd)
{
- struct i2c_regs *i2c_base = davinci_get_base(adap);
-
if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
REG(&(i2c_base->i2c_con)) = 0;
udelay(50000);
}
- davinci_i2c_setspeed(adap, speed);
+ _davinci_i2c_setspeed(i2c_base, speed);
REG(&(i2c_base->i2c_oa)) = slaveadd;
REG(&(i2c_base->i2c_cnt)) = 0;
udelay(1000);
}
-static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
+static int _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip,
+ uint32_t addr, int alen, uint8_t *buf, int len)
{
- struct i2c_regs *i2c_base = davinci_get_base(adap);
- int rc = 1;
-
- if (chip == REG(&(i2c_base->i2c_oa)))
- return rc;
-
- REG(&(i2c_base->i2c_con)) = 0;
- if (wait_for_bus(adap))
- return 1;
-
- /* try to read one byte from current (or only) address */
- REG(&(i2c_base->i2c_cnt)) = 1;
- REG(&(i2c_base->i2c_sa)) = chip;
- REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
- I2C_CON_STP);
- udelay(50000);
-
- if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
- rc = 0;
- flush_rx(adap);
- REG(&(i2c_base->i2c_stat)) = 0xffff;
- } else {
- REG(&(i2c_base->i2c_stat)) = 0xffff;
- REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
- udelay(20000);
- if (wait_for_bus(adap))
- return 1;
- }
-
- flush_rx(adap);
- REG(&(i2c_base->i2c_stat)) = 0xffff;
- REG(&(i2c_base->i2c_cnt)) = 0;
- return rc;
-}
-
-static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
- uint32_t addr, int alen, uint8_t *buf, int len)
-{
- struct i2c_regs *i2c_base = davinci_get_base(adap);
uint32_t tmp;
int i;
return 1;
}
- if (wait_for_bus(adap))
+ if (_wait_for_bus(i2c_base))
return 1;
if (alen != 0) {
REG(&(i2c_base->i2c_sa)) = chip;
REG(&(i2c_base->i2c_con)) = tmp;
- tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
+ tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK();
return 1;
}
- tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
+ tmp = _poll_i2c_irq(i2c_base,
+ I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK();
/* No break, fall through */
return 1;
}
- tmp = poll_i2c_irq(adap, I2C_STAT_XRDY |
- I2C_STAT_NACK | I2C_STAT_ARDY);
+ tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY |
+ I2C_STAT_NACK | I2C_STAT_ARDY);
CHECK_NACK();
REG(&(i2c_base->i2c_con)) = tmp;
for (i = 0; i < len; i++) {
- tmp = poll_i2c_irq(adap, I2C_STAT_RRDY | I2C_STAT_NACK |
+ tmp = _poll_i2c_irq(i2c_base, I2C_STAT_RRDY | I2C_STAT_NACK |
I2C_STAT_ROVR);
CHECK_NACK();
}
}
- tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
+ tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
CHECK_NACK();
return 1;
}
- flush_rx(adap);
+ _flush_rx(i2c_base);
REG(&(i2c_base->i2c_stat)) = 0xffff;
REG(&(i2c_base->i2c_cnt)) = 0;
REG(&(i2c_base->i2c_con)) = 0;
return 0;
}
-static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
- uint32_t addr, int alen, uint8_t *buf, int len)
+static int _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip,
+ uint32_t addr, int alen, uint8_t *buf, int len)
{
- struct i2c_regs *i2c_base = davinci_get_base(adap);
uint32_t tmp;
int i;
return 1;
}
- if (wait_for_bus(adap))
+ if (_wait_for_bus(i2c_base))
return 1;
/* Start address phase */
switch (alen) {
case 2:
/* Send address MSByte */
- tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
+ tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK();
/* No break, fall through */
case 1:
/* Send address LSByte */
- tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
+ tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK();
}
for (i = 0; i < len; i++) {
- tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
+ tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK();
return 1;
}
- tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
+ tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
CHECK_NACK();
return 1;
}
- flush_rx(adap);
+ _flush_rx(i2c_base);
REG(&(i2c_base->i2c_stat)) = 0xffff;
REG(&(i2c_base->i2c_cnt)) = 0;
REG(&(i2c_base->i2c_con)) = 0;
return 0;
}
+static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip)
+{
+ int rc = 1;
+
+ if (chip == REG(&(i2c_base->i2c_oa)))
+ return rc;
+
+ REG(&(i2c_base->i2c_con)) = 0;
+ if (_wait_for_bus(i2c_base))
+ return 1;
+
+ /* try to read one byte from current (or only) address */
+ REG(&(i2c_base->i2c_cnt)) = 1;
+ REG(&(i2c_base->i2c_sa)) = chip;
+ REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
+ I2C_CON_STP);
+ udelay(50000);
+
+ if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
+ rc = 0;
+ _flush_rx(i2c_base);
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
+ } else {
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
+ REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
+ udelay(20000);
+ if (_wait_for_bus(i2c_base))
+ return 1;
+ }
+
+ _flush_rx(i2c_base);
+ REG(&(i2c_base->i2c_stat)) = 0xffff;
+ REG(&(i2c_base->i2c_cnt)) = 0;
+ return rc;
+}
+
+#ifndef CONFIG_DM_I2C
static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
{
switch (adap->hwadapnr) {
return NULL;
}
-U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe,
+static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
+{
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
+ uint ret;
+
+ adap->speed = speed;
+ ret = _davinci_i2c_setspeed(i2c_base, speed);
+
+ return ret;
+}
+
+static void davinci_i2c_init(struct i2c_adapter *adap, int speed,
+ int slaveadd)
+{
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
+
+ adap->speed = speed;
+ _davinci_i2c_init(i2c_base, speed, slaveadd);
+
+ return;
+}
+
+static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
+ uint32_t addr, int alen, uint8_t *buf, int len)
+{
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
+ return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len);
+}
+
+static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
+ uint32_t addr, int alen, uint8_t *buf, int len)
+{
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
+
+ return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len);
+}
+
+static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip)
+{
+ struct i2c_regs *i2c_base = davinci_get_base(adap);
+
+ return _davinci_i2c_probe_chip(i2c_base, chip);
+}
+
+U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip,
davinci_i2c_read, davinci_i2c_write,
davinci_i2c_setspeed,
CONFIG_SYS_DAVINCI_I2C_SPEED,
0)
#if I2C_BUS_MAX >= 2
-U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
davinci_i2c_read, davinci_i2c_write,
davinci_i2c_setspeed,
CONFIG_SYS_DAVINCI_I2C_SPEED1,
#endif
#if I2C_BUS_MAX >= 3
-U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe,
+U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
davinci_i2c_read, davinci_i2c_write,
davinci_i2c_setspeed,
CONFIG_SYS_DAVINCI_I2C_SPEED2,
CONFIG_SYS_DAVINCI_I2C_SLAVE2,
2)
#endif
+
+#else /* CONFIG_DM_I2C */
+
+static int davinci_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct i2c_bus *i2c_bus = dev_get_priv(bus);
+ int ret;
+
+ debug("i2c_xfer: %d messages\n", nmsgs);
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
+ if (msg->flags & I2C_M_RD) {
+ ret = _davinci_i2c_read(i2c_bus->regs, msg->addr,
+ 0, 0, msg->buf, msg->len);
+ } else {
+ ret = _davinci_i2c_write(i2c_bus->regs, msg->addr,
+ 0, 0, msg->buf, msg->len);
+ }
+ if (ret) {
+ debug("i2c_write: error sending\n");
+ return -EREMOTEIO;
+ }
+ }
+
+ return ret;
+}
+
+static int davinci_i2c_set_speed(struct udevice *dev, uint speed)
+{
+ struct i2c_bus *i2c_bus = dev_get_priv(dev);
+
+ i2c_bus->speed = speed;
+ return _davinci_i2c_setspeed(i2c_bus->regs, speed);
+}
+
+static int davinci_i2c_probe(struct udevice *dev)
+{
+ struct i2c_bus *i2c_bus = dev_get_priv(dev);
+
+ i2c_bus->id = dev->seq;
+ i2c_bus->regs = (struct i2c_regs *)dev_get_addr(dev);
+
+ i2c_bus->speed = 100000;
+ _davinci_i2c_init(i2c_bus->regs, i2c_bus->speed, 0);
+
+ return 0;
+}
+
+static int davinci_i2c_probe_chip(struct udevice *bus, uint chip_addr,
+ uint chip_flags)
+{
+ struct i2c_bus *i2c_bus = dev_get_priv(bus);
+
+ return _davinci_i2c_probe_chip(i2c_bus->regs, chip_addr);
+}
+
+static const struct dm_i2c_ops davinci_i2c_ops = {
+ .xfer = davinci_i2c_xfer,
+ .probe_chip = davinci_i2c_probe_chip,
+ .set_bus_speed = davinci_i2c_set_speed,
+};
+
+static const struct udevice_id davinci_i2c_ids[] = {
+ { .compatible = "ti,davinci-i2c"},
+ { .compatible = "ti,keystone-i2c"},
+ { }
+};
+
+U_BOOT_DRIVER(i2c_davinci) = {
+ .name = "i2c_davinci",
+ .id = UCLASS_I2C,
+ .of_match = davinci_i2c_ids,
+ .probe = davinci_i2c_probe,
+ .priv_auto_alloc_size = sizeof(struct i2c_bus),
+ .ops = &davinci_i2c_ops,
+};
+
+#endif /* CONFIG_DM_I2C */
#include <common.h>
#include <malloc.h>
+#include <fdtdec.h>
#include <nand.h>
#include <linux/errno.h>
#include <asm/io.h>
#include "pxa3xx_nand.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define TIMEOUT_DRAIN_FIFO 5 /* in ms */
#define CHIP_DELAY_TIMEOUT 200
#define NAND_STOP_DELAY 40
chip->cmdfunc = nand_cmdfunc;
}
- info->mmio_base = (void __iomem *)MVEBU_NAND_BASE;
-
/* Allocate a buffer to allow flash detection */
info->buf_size = INIT_BUFFER_SIZE;
info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info)
{
struct pxa3xx_nand_platform_data *pdata;
+ const void *blob = gd->fdt_blob;
+ int node = -1;
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return -ENOMEM;
- pdata->enable_arbiter = 1;
- pdata->num_cs = 1;
+ /* Get address decoding nodes from the FDT blob */
+ do {
+ node = fdt_node_offset_by_compatible(blob, node,
+ "marvell,mvebu-pxa3xx-nand");
+ if (node < 0)
+ break;
+
+ /* Bypass disabeld nodes */
+ if (!fdtdec_get_is_enabled(blob, node))
+ continue;
- info->pdata = pdata;
+ /* Get the first enabled NAND controler base address */
+ info->mmio_base =
+ (void __iomem *)fdtdec_get_addr_size_auto_noparent(
+ blob, node, "reg", 0, NULL, true);
- return 0;
+ pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1);
+ if (pdata->num_cs != 1) {
+ error("pxa3xx driver supports single CS only\n");
+ break;
+ }
+
+ if (fdtdec_get_bool(blob, node, "nand-enable-arbiter"))
+ pdata->enable_arbiter = 1;
+
+ if (fdtdec_get_bool(blob, node, "nand-keep-config"))
+ pdata->keep_config = 1;
+
+ /*
+ * ECC parameters.
+ * If these are not set, they will be selected according
+ * to the detected flash type.
+ */
+ /* ECC strength */
+ pdata->ecc_strength = fdtdec_get_int(blob, node,
+ "nand-ecc-strength", 0);
+
+ /* ECC step size */
+ pdata->ecc_step_size = fdtdec_get_int(blob, node,
+ "nand-ecc-step-size", 0);
+
+ info->pdata = pdata;
+
+ /* Currently support only a single NAND controller */
+ return 0;
+
+ } while (node >= 0);
+
+ return -EINVAL;
}
static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
int ret;
info = kzalloc(sizeof(*info) +
- sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
- GFP_KERNEL);
+ sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
+ GFP_KERNEL);
if (!info)
return;
static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
struct mvpp2_bm_pool *bm_pool)
{
+ int i;
+
+ for (i = 0; i < bm_pool->buf_num; i++) {
+ /* Allocate buffer back from the buffer manager */
+ mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
+ }
+
bm_pool->buf_num = 0;
}
return 0;
}
+/*
+ * Empty BM pool and stop its activity before the OS is started
+ */
+static int mvpp2_remove(struct udevice *dev)
+{
+ struct mvpp2_port *port = dev_get_priv(dev);
+ struct mvpp2 *priv = port->priv;
+ int i;
+
+ for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
+ mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
+
+ return 0;
+}
+
static const struct eth_ops mvpp2_ops = {
.start = mvpp2_start,
.send = mvpp2_send,
.name = "mvpp2",
.id = UCLASS_ETH,
.probe = mvpp2_probe,
+ .remove = mvpp2_remove,
.ops = &mvpp2_ops,
.priv_auto_alloc_size = sizeof(struct mvpp2_port),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ACTIVE_DMA,
};
/*
/* Don't register host if link is down */
if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
printf("PCIE-%d: Link down\n", dev->seq);
- return -ENODEV;
+ } else {
+ printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,
+ pcie_dw_get_link_speed(pcie->ctrl_base),
+ pcie_dw_get_link_width(pcie->ctrl_base),
+ hose->first_busno);
}
- printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,
- pcie_dw_get_link_speed(pcie->ctrl_base),
- pcie_dw_get_link_width(pcie->ctrl_base), hose->first_busno);
-
pcie_dw_regions_setup(pcie);
/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
u32 speed;
u32 invert;
bool clk_src;
+ bool end_point;
};
struct chip_serdes_phy_config {
void __iomem *hpipe3_base_addr;
u32 comphy_lanes_count;
u32 comphy_mux_bitcount;
- u32 comphy_index;
+ u32 cp_index;
};
/* Register helper functions */
"SGMII1", "SGMII2", "SGMII3", "QSGMII",
"USB3_HOST0", "USB3_HOST1", "USB3_DEVICE",
"XAUI0", "XAUI1", "XAUI2", "XAUI3",
- "RXAUI0", "RXAUI1", "KR"};
+ "RXAUI0", "RXAUI1", "SFI", "IGNORE"};
if (type < 0 || type > PHY_TYPE_MAX)
return "invalid";
for (lane = 0; lane < chip_cfg->comphy_lanes_count;
lane++, comphy_map_data++) {
- if (comphy_map_data->type == PHY_TYPE_UNCONNECTED)
- continue;
-
if (comphy_map_data->speed == PHY_SPEED_INVALID) {
printf("Comphy-%d: %-13s\n", lane,
get_type_string(comphy_map_data->type));
int subnode;
int lane;
int last_idx = 0;
+ static int current_idx;
/* Save base addresses for later use */
chip_cfg->comphy_base_addr = (void *)dev_get_addr_index(dev, 0);
blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT);
comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode,
"clk-src");
+ comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode,
+ "end_point");
if (comphy_map_data[lane].type == PHY_TYPE_INVALID) {
printf("no phy type for lane %d, setting lane as unconnected\n",
lane + 1);
lane++;
}
- /* Save comphy index for MultiCP devices (A8K) */
- chip_cfg->comphy_index = dev->seq;
+ /* Save CP index for MultiCP devices (A8K) */
+ chip_cfg->cp_index = current_idx++;
/* PHY power UP sequence */
chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data);
/* PHY print SerDes status */
if (of_machine_is_compatible("marvell,armada8040"))
- printf("Comphy chip #%d:\n", chip_cfg->comphy_index);
+ printf("Comphy chip #%d:\n", chip_cfg->cp_index);
comphy_print(chip_cfg, comphy_map_data);
/*
if (of_machine_is_compatible("marvell,armada8040"))
last_idx = 1;
- if (chip_cfg->comphy_index == last_idx) {
+ if (chip_cfg->cp_index == last_idx) {
/* Initialize dedicated PHYs (not muxed SerDes lanes) */
comphy_dedicated_phys_init();
}
* PIPE selector include USB and PCIe options.
* PHY selector include the Ethernet and SATA options, every Ethernet
* option has different options, for example: serdes lane2 had option
- * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, KR)
+ * Eth_port_0 that include (SGMII0, RXAUI0, SFI)
*/
struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */
- {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, /* Lane 1 */
- {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA0, 0x4} } },
+ {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
+ {PHY_TYPE_SATA1, 0x4} } },
+ {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
+ {PHY_TYPE_SATA0, 0x4} } },
{6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
- {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1},
- {PHY_TYPE_KR, 0x1}, {PHY_TYPE_SATA0, 0x4} } },
- {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 3 */
- {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1},
- {PHY_TYPE_KR, 0x1}, {PHY_TYPE_XAUI1, 0x1},
- {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
+ {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1},
+ {PHY_TYPE_SATA0, 0x4} } },
+ {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
+ {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
{7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
- {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1},
- {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } },
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */
- {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1},
- {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
+ {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2},
+ {PHY_TYPE_SGMII1, 0x1} } },
+ {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
+ {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
};
struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
return 0;
}
-static int comphy_pcie_power_up(u32 lane, u32 pcie_width,
- bool clk_src, void __iomem *hpipe_base,
+static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
+ bool is_end_point, void __iomem *hpipe_base,
void __iomem *comphy_base)
{
u32 mask, data, ret = 1;
* and SerDes Lane 0 got PCIe ref-clock #0
*/
debug("PCIe clock = %x\n", pcie_clk);
+ debug("PCIe RC = %d\n", !is_end_point);
debug("PCIe width = %d\n", pcie_width);
/* enable PCIe by4 and by2 */
mask |= HPIPE_MISC_REFCLK_SEL_MASK;
data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
}
+ mask |= HPIPE_MISC_ICP_FORCE_MASK;
+ data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
if (pcie_clk) { /* output */
/* Set reference frequcency select - 0x2 for 25MHz*/
/* Set Maximal PHY Generation Setting(8Gbps) */
mask = HPIPE_INTERFACE_GEN_MAX_MASK;
data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
+ /* Bypass frame detection and sync detection for RX DATA */
+ mask = HPIPE_INTERFACE_DET_BYPASS_MASK;
+ data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
/* Set Link Train Mode (Tx training control pins are used) */
mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
- /* Force DFE resolution (use GEN table value) */
+ /* Use TX/RX training result for DFE */
mask = HPIPE_DFE_RES_FORCE_MASK;
- data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
+ data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
/* Configure initial and final coefficient value for receiver */
- mask = HPIPE_G3_RX_SELMUPI_MASK;
- data = 0x1 << HPIPE_G3_RX_SELMUPI_OFFSET;
+ mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
+ data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G3_RX_SELMUPF_MASK;
- data |= 0x1 << HPIPE_G3_RX_SELMUPF_OFFSET;
+ mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
+ data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
- mask |= HPIPE_G3_SETTING_BIT_MASK;
- data |= 0x0 << HPIPE_G3_SETTING_BIT_OFFSET;
- reg_set(hpipe_addr + HPIPE_G3_SETTINGS_1_REG, data, mask);
+ mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
+ data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
/* Trigger sampler enable pulse */
mask = HPIPE_SMAPLER_MASK;
data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
- data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
+ data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
- /* Set phy in root complex mode */
- mask = HPIPE_CFG_PHY_RC_EP_MASK;
- data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
- reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
+ /* Pattern lock lost timeout disable */
+ mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
+ data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
+
+ /* Configure DFE adaptations */
+ mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK;
+ data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET;
+ mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK;
+ data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET;
+ mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK;
+ data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET;
+ reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
+ mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK;
+ data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET;
+ reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
+
+ /* Genration 2 setting 1*/
+ mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
+ data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
+ mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
+ data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
+ data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
+
+ /* DFE enable */
+ mask = HPIPE_G2_DFE_RES_MASK;
+ data = 0x3 << HPIPE_G2_DFE_RES_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
+
+ /* Configure DFE Resolution */
+ mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK;
+ data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
+
+ /* VDD calibration control */
+ mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
+ data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
+
+ /* Set PLL Charge-pump Current Control */
+ mask = HPIPE_G3_SETTING_5_G3_ICP_MASK;
+ data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
+
+ /* Set lane rqualization remote setting */
+ mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK;
+ data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET;
+ mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK;
+ data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET;
+ mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
+ data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET;
+ reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
+
+ if (!is_end_point) {
+ /* Set phy in root complex mode */
+ mask = HPIPE_CFG_PHY_RC_EP_MASK;
+ data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
+ reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
+ }
debug("stage: Comphy power up\n");
}
static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base, int comphy_index)
+ void __iomem *comphy_base, int cp_index)
{
u32 mask, data, i, ret = 1;
void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
* In order to parse each CPs SATA node, fdt_node_offset_by_compatible
* must be called again (according to the CP id)
*/
- for (i = 0; i < (comphy_index + 1); i++)
+ for (i = 0; i < (cp_index + 1); i++)
sata_node = fdt_node_offset_by_compatible(
gd->fdt_blob, sata_node, "marvell,armada-8k-ahci");
0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
debug("stage: Analog paramters from ETP(HW)\n");
- /*
- * TODO: Set analog paramters from ETP(HW) - for now use the
- * default datas
- */
+ /* Set analog parameters from ETP(HW) */
+ /* G1 settings */
+ mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
+ data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
+ data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
+ data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
+
+ mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
+ data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
+ mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
+ data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
+ mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
+ data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
+ mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK;
+ data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET;
+ mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK;
+ data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
+
+ /* G2 settings */
+ mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
+ data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
+ mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK;
+ data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
+ data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
+ mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK;
+ data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET;
+ mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK;
+ data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
+
+ /* G3 settings */
+ mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
+ data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
+ mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
+ data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
+ mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK;
+ data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET;
+ mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK;
+ data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET;
+ mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK;
+ data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET;
+ mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK;
+ data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET;
+ mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
+ data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
+
+ /* DTL Control */
+ mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK;
+ data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET;
+ mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK;
+ data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET;
+ mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
+ data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
+ mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK;
+ data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET;
+ mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK;
+ data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET;
+ mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK;
+ data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET;
+ mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK;
+ data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
+
+ /* Trigger sampler enable pulse (by toggleing the bit) */
+ mask = HPIPE_SMAPLER_MASK;
+ data = 0x1 << HPIPE_SMAPLER_OFFSET;
+ reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
+ mask = HPIPE_SMAPLER_MASK;
+ data = 0x0 << HPIPE_SMAPLER_OFFSET;
+ reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
+
+ /* VDD Calibration Control 3 */
+ mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
+ data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
+
+ /* DFE Resolution Control */
+ mask = HPIPE_DFE_RES_FORCE_MASK;
+ data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
+
+ /* DFE F3-F5 Coefficient Control */
+ mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
+ data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
+ mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
+ data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
+
+ /* G3 Setting 3 */
+ mask = HPIPE_G3_FFE_CAP_SEL_MASK;
+ data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET;
+ mask |= HPIPE_G3_FFE_RES_SEL_MASK;
+ data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET;
+ mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK;
+ data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET;
+ mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
+ data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
+ mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
+ data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
+
+ /* G3 Setting 4 */
+ mask = HPIPE_G3_DFE_RES_MASK;
+ data = 0x2 << HPIPE_G3_DFE_RES_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
+
+ /* Offset Phase Control */
+ mask = HPIPE_OS_PH_OFFSET_MASK;
+ data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET;
+ mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK;
+ data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
+ mask = HPIPE_OS_PH_VALID_MASK;
+ data = 0x1 << HPIPE_OS_PH_VALID_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
+ mask = HPIPE_OS_PH_VALID_MASK;
+ data = 0x0 << HPIPE_OS_PH_VALID_OFFSET;
+ reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
+
+ /* Set G1 TX amplitude and TX post emphasis value */
+ mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
+ data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
+ mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK;
+ data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET;
+ mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
+ data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
+ mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK;
+ data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
+
+ /* Set G2 TX amplitude and TX post emphasis value */
+ mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK;
+ data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET;
+ mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK;
+ data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET;
+ mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK;
+ data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET;
+ mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK;
+ data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask);
+
+ /* Set G3 TX amplitude and TX post emphasis value */
+ mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK;
+ data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET;
+ mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK;
+ data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET;
+ mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK;
+ data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET;
+ mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK;
+ data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET;
+ mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK;
+ data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET;
+ mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK;
+ data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask);
+
+ /* SERDES External Configuration 2 register */
+ mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK;
+ data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET;
+ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
/* DFE reset sequence */
reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
return ret;
}
-static int comphy_kr_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base)
+static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base,
+ void __iomem *comphy_base, u32 speed)
{
u32 mask, data, ret = 1;
void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
debug("stage: Comphy configuration\n");
/* set reference clock */
mask = HPIPE_MISC_ICP_FORCE_MASK;
- data = 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
+ data = (speed == PHY_SPEED_5_15625G) ?
+ (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) :
+ (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET);
mask |= HPIPE_MISC_REFCLK_SEL_MASK;
data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
+ /* Transmitter/Receiver Speed Divider Force */
+ if (speed == PHY_SPEED_5_15625G) {
+ mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK;
+ data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET;
+ mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK;
+ data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET;
+ mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK;
+ data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET;
+ mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK;
+ data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET;
+ } else {
+ mask = HPIPE_TXDIGCK_DIV_FORCE_MASK;
+ data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET;
+ }
+ reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask);
+
/* Set analog paramters from ETP(HW) */
debug("stage: Analog paramters from ETP(HW)\n");
/* SERDES External Configuration 2 */
data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
/* 0xd-G1_Setting_0 */
- mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
- data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
- mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
- data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
+ if (speed == PHY_SPEED_5_15625G) {
+ mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
+ data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
+ } else {
+ mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
+ data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
+ mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
+ data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
+ }
reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
/* Genration 1 setting 2 (G1_Setting_2) */
mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK;
data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask);
/* 0xE-G1_Setting_1 */
- mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
- data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
+ mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
+ data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
+ if (speed == PHY_SPEED_5_15625G) {
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+ } else {
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
+ data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
+ data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
+ data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
+ data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET;
+ mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
+ data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
+ }
reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
+
/* 0xA-DFE_Reg3 */
mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
/* Genration 1 setting 3 (G1_Setting_3) */
mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK;
data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET;
+ if (speed == PHY_SPEED_5_15625G) {
+ /* Force FFE (Feed Forward Equalization) to 5G */
+ mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
+ data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
+ mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
+ data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
+ mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
+ data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
+ }
reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
+ /* Connfigure RX training timer */
+ mask = HPIPE_RX_TRAIN_TIMER_MASK;
+ data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET;
+ reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
+
+ /* Enable TX train peak to peak hold */
+ mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
+ data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
+ reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
+
+ /* Configure TX preset index */
+ mask = HPIPE_TX_PRESET_INDEX_MASK;
+ data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET;
+ reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask);
+
+ /* Disable pattern lock lost timeout */
+ mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
+ data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
+ reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
+
+ /* Configure TX training pattern and TX training 16bit auto */
+ mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK;
+ data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET;
+ mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK;
+ data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
+
+ /* Configure Training patten number */
+ mask = HPIPE_TRAIN_PAT_NUM_MASK;
+ data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET;
+ reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask);
+
+ /* Configure differencial manchester encoter to ethernet mode */
+ mask = HPIPE_DME_ETHERNET_MODE_MASK;
+ data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_DME_REG, data, mask);
+
+ /* Configure VDD Continuous Calibration */
+ mask = HPIPE_CAL_VDD_CONT_MODE_MASK;
+ data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET;
+ reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask);
+
+ /* Trigger sampler enable pulse (by toggleing the bit) */
+ mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK;
+ data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET;
+ mask |= HPIPE_SMAPLER_MASK;
+ data |= 0x1 << HPIPE_SMAPLER_OFFSET;
+ reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
+ mask = HPIPE_SMAPLER_MASK;
+ data = 0x0 << HPIPE_SMAPLER_OFFSET;
+ reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
+
+ /* Set External RX Regulator Control */
+ mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
+ data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
+ reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
+
debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
/* SERDES External Configuration */
mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
* If UTMI connected to USB Device, configure mux prior to PHY init
* (Device can be connected to UTMI0 or to UTMI1)
*/
- if (utmi_phy_port == UTMI_PHY_TO_USB_DEVICE0) {
+ if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) {
debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n",
utmi_index);
/* USB3 Device UTMI enable */
continue;
}
printf("UTMI PHY %d initialized to ", i);
- if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_TO_USB_DEVICE0)
+ if (cp110_utmi_data[i].utmi_phy_port ==
+ UTMI_PHY_TO_USB3_DEVICE0)
printf("USB Device\n");
else
printf("USB Host%d\n",
}
switch (ptr_comphy_map->type) {
case PHY_TYPE_UNCONNECTED:
+ case PHY_TYPE_IGNORE:
continue;
break;
case PHY_TYPE_PEX0:
case PHY_TYPE_PEX3:
ret = comphy_pcie_power_up(
lane, pcie_width, ptr_comphy_map->clk_src,
+ serdes_map->end_point,
hpipe_base_addr, comphy_base_addr);
break;
case PHY_TYPE_SATA0:
case PHY_TYPE_SATA3:
ret = comphy_sata_power_up(
lane, hpipe_base_addr, comphy_base_addr,
- ptr_chip_cfg->comphy_index);
+ ptr_chip_cfg->cp_index);
break;
case PHY_TYPE_USB3_HOST0:
case PHY_TYPE_USB3_HOST1:
lane, ptr_comphy_map->speed, hpipe_base_addr,
comphy_base_addr);
break;
- case PHY_TYPE_KR:
- ret = comphy_kr_power_up(lane, hpipe_base_addr,
- comphy_base_addr);
+ case PHY_TYPE_SFI:
+ ret = comphy_sfi_power_up(lane, hpipe_base_addr,
+ comphy_base_addr,
+ ptr_comphy_map->speed);
break;
case PHY_TYPE_RXAUI0:
case PHY_TYPE_RXAUI1:
}
if (ret == 0) {
/*
- * If interface wans't initialiuzed, set the lane to
+ * If interface wans't initialized, set the lane to
* PHY_TYPE_UNCONNECTED state.
*/
ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;
#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
(0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
+#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
+#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
+ (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
#define SD_EXTERNAL_STATUS0_REG 0x18
#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
(0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
+#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6
+#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \
+ (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
(0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
+#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11
+#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \
+ (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
#define HPIPE_G1_SET_1_REG 0x038
#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
+#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
+#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
+ (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
+#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8
+#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \
+ (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
(0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
-#define HPIPE_G2_SETTINGS_1_REG 0x040
-
-#define HPIPE_G3_SETTINGS_1_REG 0x048
-#define HPIPE_G3_RX_SELMUPI_OFFSET 0
-#define HPIPE_G3_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET)
-#define HPIPE_G3_RX_SELMUPF_OFFSET 3
-#define HPIPE_G3_RX_SELMUPF_MASK \
- (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET)
-#define HPIPE_G3_SETTING_BIT_OFFSET 13
-#define HPIPE_G3_SETTING_BIT_MASK \
- (0x1 << HPIPE_G3_SETTING_BIT_OFFSET)
+#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11
+#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \
+ (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
+
+#define HPIPE_G2_SET_0_REG 0x3c
+#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1
+#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \
+ (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
+#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6
+#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \
+ (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
+#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7
+#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \
+ (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
+#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11
+#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \
+ (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
+
+#define HPIPE_G2_SET_1_REG 0x040
+#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
+#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
+ (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
+#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3
+#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \
+ (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
+#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
+#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
+ (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
+#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8
+#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \
+ (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
+#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10
+#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \
+ (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
+#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11
+#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \
+ (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
+
+#define HPIPE_G3_SET_0_REG 0x44
+#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1
+#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \
+ (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
+#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6
+#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \
+ (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
+#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7
+#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \
+ (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
+#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11
+#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \
+ (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
+#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
+#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \
+ (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
+#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
+#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \
+ (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
+
+#define HPIPE_G3_SET_1_REG 0x048
+#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
+#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \
+ (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
+#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3
+#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \
+ (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
+#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6
+#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \
+ (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
+#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8
+#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \
+ (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
+#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10
+#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \
+ (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
+#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11
+#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \
+ (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
+#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13
+#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
+ (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
#define HPIPE_LOOPBACK_REG 0x08c
#define HPIPE_LOOPBACK_SEL_OFFSET 1
#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
#define HPIPE_INTERFACE_GEN_MAX_MASK \
(0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
+#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
+#define HPIPE_INTERFACE_DET_BYPASS_MASK \
+ (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
(0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
+#define HPIPE_VDD_CAL_CTRL_REG 0x114
+#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
+#define HPIPE_EXT_SELLV_RXSAMPL_MASK \
+ (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
+
+#define HPIPE_VDD_CAL_0_REG 0x108
+#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
+#define HPIPE_CAL_VDD_CONT_MODE_MASK \
+ (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
+
#define HPIPE_PCIE_REG0 0x120
#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
#define HPIPE_PCIE_IDLE_SYNC_MASK \
#define HPIPE_PWR_CTR_SFT_RST_MASK \
(0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
+#define HPIPE_SPD_DIV_FORCE_REG 0x154
+#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7
+#define HPIPE_TXDIGCK_DIV_FORCE_MASK \
+ (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
+#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8
+#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \
+ (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
+#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10
+#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \
+ (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
+#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13
+#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \
+ (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
+#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15
+#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
+ (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
+
#define HPIPE_PLLINTP_REG1 0x150
#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
+#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
+#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \
+ (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
#define HPIPE_SMAPLER_OFFSET 12
#define HPIPE_SMAPLER_MASK \
(0x1 << HPIPE_SMAPLER_OFFSET)
#define HPIPE_TX_REG1_SLC_EN_MASK \
(0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_REG 0x184
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
+#define HPIPE_PWR_CTR_DTL_REG 0x184
+#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
+#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \
+ (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
+#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
+#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \
+ (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
+#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
+#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
(0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
-
-#define HPIPE_RX_REG3 0x188
+#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
+#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \
+ (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
+#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
+#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \
+ (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
+#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
+#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \
+ (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
+#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
+#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \
+ (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
+
+#define HPIPE_PHASE_CONTROL_REG 0x188
+#define HPIPE_OS_PH_OFFSET_OFFSET 0
+#define HPIPE_OS_PH_OFFSET_MASK \
+ (0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
+#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
+#define HPIPE_OS_PH_OFFSET_FORCE_MASK \
+ (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
+#define HPIPE_OS_PH_VALID_OFFSET 8
+#define HPIPE_OS_PH_VALID_MASK \
+ (0x1 << HPIPE_OS_PH_VALID_OFFSET)
+
+#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
+#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
+#define HPIPE_TRAIN_PAT_NUM_MASK \
+ (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
+
+#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220
+#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12
+#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \
+ (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
+
+#define HPIPE_DME_REG 0x228
+#define HPIPE_DME_ETHERNET_MODE_OFFSET 7
+#define HPIPE_DME_ETHERNET_MODE_MASK \
+ (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
#define HPIPE_PCIE_REG3 0x290
#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
+#define HPIPE_RX_TRAIN_TIMER_OFFSET 0
+#define HPIPE_RX_TRAIN_TIMER_MASK \
+ (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
(0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
(0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
+#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8
+#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \
+ (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
+#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9
+#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
+ (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
+
+#define HPIPE_CDR_CONTROL_REG 0x418
+#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
+#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
+ (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
+#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
+#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
+ (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
+#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
+#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
+ (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
(0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
-#define HPIPE_G1_SETTINGS_3_REG 0x440
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
+#define HPIPE_G1_SETTINGS_3_REG 0x440
+#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
+#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \
+ (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
+#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4
+#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \
+ (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
+#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7
+#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \
+ (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
+#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
+#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
(0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
+#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12
+#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \
+ (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
+#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14
+#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \
+ (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
#define HPIPE_G1_SETTINGS_4_REG 0x444
#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
(0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
#define HPIPE_G2_SETTINGS_3_REG 0x448
-#define HPIPE_G2_SETTINGS_4_REG 0x44C
+
+#define HPIPE_G2_SETTINGS_4_REG 0x44c
+#define HPIPE_G2_DFE_RES_OFFSET 8
+#define HPIPE_G2_DFE_RES_MASK \
+ (0x3 << HPIPE_G2_DFE_RES_OFFSET)
#define HPIPE_G3_SETTING_3_REG 0x450
+#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
+#define HPIPE_G3_FFE_CAP_SEL_MASK \
+ (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
+#define HPIPE_G3_FFE_RES_SEL_OFFSET 4
+#define HPIPE_G3_FFE_RES_SEL_MASK \
+ (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
+#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7
+#define HPIPE_G3_FFE_SETTING_FORCE_MASK \
+ (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
(0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
#define HPIPE_G3_DFE_RES_MASK \
(0x3 << HPIPE_G3_DFE_RES_OFFSET)
+#define HPIPE_TX_PRESET_INDEX_REG 0x468
+#define HPIPE_TX_PRESET_INDEX_OFFSET 0
+#define HPIPE_TX_PRESET_INDEX_MASK \
+ (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
+
+#define HPIPE_DFE_CONTROL_REG 0x470
+#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
+#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \
+ (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
+
#define HPIPE_DFE_CTRL_28_REG 0x49C
#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
(0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
+#define HPIPE_G3_SETTING_5_REG 0x548
+#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
+#define HPIPE_G3_SETTING_5_G3_ICP_MASK \
+ (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
+
#define HPIPE_LANE_CONFIG0_REG 0x600
#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
(0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
+#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
+#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \
+ (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
(0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
#define HPIPE_CFG_UPDATE_POLARITY_MASK \
(0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
+#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
+#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
+#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \
+ (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
+#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
+#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \
+ (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
+#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
+#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \
+ (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
+
#define HPIPE_RST_CLK_CTRL_REG 0x704
#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
for (lane = 0; lane < comphy_max_lanes;
lane++, comphy_map_data++, mux_data++) {
+ /* Don't check ignored COMPHYs */
+ if (comphy_map_data->type == PHY_TYPE_IGNORE)
+ continue;
+
mux_opt = mux_data->mux_values;
for (opt = 0, valid = 0; opt < mux_data->max_lane_values;
opt++, mux_opt++) {
for (lane = 0; lane < comphy_max_lanes;
lane++, comphy_map_data++, mux_data++) {
+ if (comphy_map_data->type == PHY_TYPE_IGNORE)
+ continue;
+
offset = lane * bitcount;
mask = (((1 << bitcount) - 1) << offset);
value = (comphy_mux_get_mux_value(mux_data,
#define CONFIG_CMD_ENV
#define CONFIG_CMD_PCI
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
-
/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_BUS 1
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
/* Environment in SPI NOR flash */
+#ifdef CONFIG_MVEBU_SPI_BOOT
#define CONFIG_ENV_IS_IN_SPI_FLASH
+/* Environment in NAND flash */
+#elif defined(CONFIG_MVEBU_NAND_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#endif
+
#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
/*
* Ethernet Driver configuration
*/
#define PHY_SPEED_3G 3
#define PHY_SPEED_3_125G 4
#define PHY_SPEED_5G 5
-#define PHY_SPEED_6G 6
-#define PHY_SPEED_6_25G 7
-#define PHY_SPEED_10_3125G 8
-#define PHY_SPEED_MAX 9
+#define PHY_SPEED_5_15625G 6
+#define PHY_SPEED_6G 7
+#define PHY_SPEED_6_25G 8
+#define PHY_SPEED_10_3125G 9
+#define PHY_SPEED_MAX 10
#define PHY_SPEED_INVALID 0xff
#define PHY_TYPE_UNCONNECTED 0
#define PHY_TYPE_XAUI3 20
#define PHY_TYPE_RXAUI0 21
#define PHY_TYPE_RXAUI1 22
-#define PHY_TYPE_KR 23
-#define PHY_TYPE_MAX 24
+#define PHY_TYPE_SFI 23
+#define PHY_TYPE_IGNORE 24
+#define PHY_TYPE_MAX 25
#define PHY_TYPE_INVALID 0xff
#define PHY_POLARITY_NO_INVERT 0
#define PHY_POLARITY_ALL_INVERT \
(PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)
-#define UTMI_PHY_TO_USB_HOST0 0
-#define UTMI_PHY_TO_USB_HOST1 1
-#define UTMI_PHY_TO_USB_DEVICE0 2
+#define UTMI_PHY_TO_USB3_HOST0 0
+#define UTMI_PHY_TO_USB3_HOST1 1
+#define UTMI_PHY_TO_USB3_DEVICE0 2
#define UTMI_PHY_INVALID 0xff
#endif /* _COMPHY_DATA_H_ */
projects / oweals / u-boot.git / commitdiff