#
# Top-level generic files
#
+fit-dtb.blob
/MLO*
/SPL*
/System.map
quiet_cmd_copy = COPY $@
cmd_copy = cp $< $@
-ifeq ($(CONFIG_OF_SEPARATE),y)
+ifeq ($(CONFIG_FIT_EMBED),y)
+
+fit-dtb.blob: dts/dt.dtb FORCE
+ $(call if_changed,mkimage)
+
+MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
+ -a 0 -e 0 -E \
+ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null
+
+u-boot-fit-dtb.bin: u-boot-nodtb.bin fit-dtb.blob
+ $(call if_changed,cat)
+
+u-boot.bin: u-boot-fit-dtb.bin FORCE
+ $(call if_changed,copy)
+else ifeq ($(CONFIG_OF_SEPARATE),y)
u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
$(call if_changed,cat)
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
- boot* u-boot* MLO* SPL System.map
+ boot* u-boot* MLO* SPL System.map fit-dtb.blob
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
+config TARGET_POPLAR
+ bool "Support Poplar 96boards Enterprise Edition Platform"
+ select ARM64
+ select DM
+ select OF_CONTROL
+ select DM_SERIAL
+ select DM_USB
+ help
+ Support for Poplar 96boards EE platform. It features a HI3798cv200
+ SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
+ making it capable of running any commercial set-top solution based on
+ Linux or Android.
+
config TARGET_LS1012AQDS
bool "Support ls1012aqds"
select ARCH_LS1012A
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hisilicon/hikey/Kconfig"
+source "board/hisilicon/poplar/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
keystone-k2e-evm.dtb \
- keystone-k2g-evm.dtb
+ keystone-k2g-evm.dtb \
+ keystone-k2g-generic.dtb \
+ keystone-k2g-ice.dtb
dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb
--- /dev/null
+/*
+ * DTS File for HiSilicon Poplar Development Board
+ *
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * Released under the GPLv2 only.
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "hi3798cv200.dtsi"
+
+/ {
+ model = "HiSilicon Poplar Development Board";
+ compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
+
+ aliases {
+ serial0 = &uart0;
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user-led0 {
+ label = "USER-LED0";
+ gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ user-led1 {
+ label = "USER-LED1";
+ gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ user-led2 {
+ label = "USER-LED2";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ };
+
+ user-led3 {
+ label = "USER-LED3";
+ gpios = <&gpio10 6 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "cpu0";
+ default-state = "off";
+ };
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-handle = <ð_phy1>;
+ phy-mode = "rgmii";
+ hisilicon,phy-reset-delays-us = <10000 10000 30000>;
+
+ eth_phy1: phy@3 {
+ reg = <3>;
+ };
+};
+
+&gpio1 {
+ status = "okay";
+ gpio-line-names = "LS-GPIO-E", "",
+ "", "",
+ "", "LS-GPIO-F",
+ "", "LS-GPIO-J";
+};
+
+&gpio2 {
+ status = "okay";
+ gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
+ "LS-GPIO-L", "LS-GPIO-G",
+ "LS-GPIO-K", "",
+ "", "";
+};
+
+&gpio3 {
+ status = "okay";
+ gpio-line-names = "", "",
+ "", "",
+ "LS-GPIO-C", "",
+ "", "LS-GPIO-B";
+};
+
+&gpio4 {
+ status = "okay";
+ gpio-line-names = "", "",
+ "", "",
+ "", "LS-GPIO-D",
+ "", "";
+};
+
+&gpio5 {
+ status = "okay";
+ gpio-line-names = "", "USER-LED-1",
+ "USER-LED-2", "",
+ "", "LS-GPIO-A",
+ "", "";
+};
+
+&gpio6 {
+ status = "okay";
+ gpio-line-names = "", "",
+ "", "USER-LED-0",
+ "", "",
+ "", "";
+};
+
+&gpio10 {
+ status = "okay";
+ gpio-line-names = "", "",
+ "", "",
+ "", "",
+ "USER-LED-3", "";
+};
+
+&i2c0 {
+ status = "okay";
+ label = "LS-I2C0";
+};
+
+&i2c2 {
+ status = "okay";
+ label = "LS-I2C1";
+};
+
+&ir {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ label = "LS-SPI0";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+ label = "LS-UART0";
+};
+/* No optional LS-UART1 on Low Speed Expansion Connector. */
--- /dev/null
+/*
+ * U-Boot addition to:
+ * 1) use platform data for the console
+ * 2) provide support for the generic-ehci USB driver currently not available
+ * in the linux kernel (8/May/2017).
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&soc {
+ usb2: ehci@9890000 {
+ compatible = "generic-ehci";
+ reg = <0x9890000 0x100>;
+ status = "okay";
+ };
+};
+
+&uart0 {
+ status = "disabled";
+};
+
+/{
+ chosen {
+ stdout-path = "";
+ };
+};
+
--- /dev/null
+/*
+ * DTS File for HiSilicon Hi3798cv200 SoC.
+ *
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * Released under the GPLv2 only.
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <dt-bindings/clock/histb-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/ti-syscon.h>
+
+/ {
+ compatible = "hisilicon,hi3798cv200";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
+ <0x0 0xf1002000 0x0 0x100>; /* GICC */
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc: soc@f0000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xf0000000 0x10000000>;
+
+ crg: clock-reset-controller@8a22000 {
+ compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
+ reg = <0x8a22000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+
+ gmacphyrst: reset-controller {
+ compatible = "ti,syscon-reset";
+ #reset-cells = <1>;
+ ti,reset-bits =
+ <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
+ DEASSERT_SET|STATUS_NONE)>,
+ <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
+ DEASSERT_SET|STATUS_NONE)>;
+ };
+ };
+
+ sysctrl: system-controller@8000000 {
+ compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
+ reg = <0x8000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+ };
+
+ uart0: serial@8b00000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x8b00000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysctrl HISTB_UART0_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ uart2: serial@8b02000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x8b02000 0x1000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_UART2_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ i2c0: i2c@8b10000 {
+ compatible = "hisilicon,hix5hd2-i2c";
+ reg = <0x8b10000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <400000>;
+ clocks = <&crg HISTB_I2C0_CLK>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@8b11000 {
+ compatible = "hisilicon,hix5hd2-i2c";
+ reg = <0x8b11000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <400000>;
+ clocks = <&crg HISTB_I2C1_CLK>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@8b12000 {
+ compatible = "hisilicon,hix5hd2-i2c";
+ reg = <0x8b12000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <400000>;
+ clocks = <&crg HISTB_I2C2_CLK>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@8b13000 {
+ compatible = "hisilicon,hix5hd2-i2c";
+ reg = <0x8b13000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <400000>;
+ clocks = <&crg HISTB_I2C3_CLK>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@8b14000 {
+ compatible = "hisilicon,hix5hd2-i2c";
+ reg = <0x8b14000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <400000>;
+ clocks = <&crg HISTB_I2C4_CLK>;
+ status = "disabled";
+ };
+
+ spi0: spi@8b1a000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x8b1a000 0x1000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <1>;
+ cs-gpios = <&gpio7 1 0>;
+ clocks = <&crg HISTB_SPI0_CLK>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ emmc: mmc@9830000 {
+ compatible = "snps,dw-mshc";
+ reg = <0x9830000 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_MMC_CIU_CLK>,
+ <&crg HISTB_MMC_BIU_CLK>;
+ clock-names = "ciu", "biu";
+ };
+
+ gpio0: gpio@8b20000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b20000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio1: gpio@8b21000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b21000 0x1000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio2: gpio@8b22000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b22000 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio3: gpio@8b23000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b23000 0x1000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio4: gpio@8b24000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b24000 0x1000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio5: gpio@8004000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8004000 0x1000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio6: gpio@8b26000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b26000 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio7: gpio@8b27000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b27000 0x1000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio8: gpio@8b28000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b28000 0x1000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio9: gpio@8b29000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b29000 0x1000>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio10: gpio@8b2a000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b2a000 0x1000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio11: gpio@8b2b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b2b000 0x1000>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gpio12: gpio@8b2c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x8b2c000 0x1000>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg HISTB_APB_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ gmac0: ethernet@9840000 {
+ compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
+ reg = <0x9840000 0x1000>,
+ <0x984300c 0x4>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_ETH0_MAC_CLK>,
+ <&crg HISTB_ETH0_MACIF_CLK>;
+ clock-names = "mac_core", "mac_ifc";
+ resets = <&crg 0xcc 8>,
+ <&crg 0xcc 10>,
+ <&gmacphyrst 0>;
+ reset-names = "mac_core", "mac_ifc", "phy";
+ status = "disabled";
+ };
+
+ gmac1: ethernet@9841000 {
+ compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
+ reg = <0x9841000 0x1000>,
+ <0x9843010 0x4>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_ETH1_MAC_CLK>,
+ <&crg HISTB_ETH1_MACIF_CLK>;
+ clock-names = "mac_core", "mac_ifc";
+ resets = <&crg 0xcc 9>,
+ <&crg 0xcc 11>,
+ <&gmacphyrst 1>;
+ reset-names = "mac_core", "mac_ifc", "phy";
+ status = "disabled";
+ };
+
+ ir: ir@8001000 {
+ compatible = "hisilicon,hix5hd2-ir";
+ reg = <0x8001000 0x1000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysctrl HISTB_IR_CLK>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/{
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&i2c1 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/{
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&i2c0 {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c1 {
+ u-boot,dm-pre-reloc;
+};
chosen {
stdout-path = &uart0;
};
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
};
&mdio {
phy-handle = <ðphy0>;
};
+&netcp {
+ status = "okay";
+};
+
&spi1 {
status = "okay";
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/{
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&i2c0 {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c1 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for Generic 66AK2G0X EVM
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "keystone-k2g.dtsi"
+
+/ {
+ compatible = "ti,k2g-generic", "ti,k2g", "ti,keystone";
+ model = "Texas Instruments 66AK2G02 Generic";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/{
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&i2c0 {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c1 {
+ u-boot,dm-pre-reloc;
+};
--- /dev/null
+/*
+ * Device Tree Source for K2G Industrial Communication Engine EVM
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+
+#include "keystone-k2g.dtsi"
+
+/ {
+ compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
+ model = "Texas Instruments K2G Industrial Communication EVM";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
reg = <0x2620110 0x8>;
reg-names = "efuse";
compatible = "ti,netcp-1.0";
+ status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
/* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
/ {
model = "Texas Instruments K2G SoC";
#size-cells = <1>;
interrupt-parent = <&gic>;
+ chosen { };
+
aliases {
serial0 = &uart0;
spi0 = &spi0;
i2c2 = &i2c2;
};
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
u-boot,dm-spl;
};
};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio7 {
+ u-boot,dm-spl;
+};
--- /dev/null
+/*
+ * (C) Copyright 2017 Linaro
+ * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _HI3798cv200_DWMMC_H_
+#define _HI3798cv200_DWMMC_H_
+
+int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
+
+#endif /* _HI3798cv200_DWMMC_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2017 Linaro
+ * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __HI3798cv200_H__
+#define __HI3798cv200_H__
+
+#define REG_BASE_PERI_CTRL 0xF8A20000
+#define REG_BASE_CRG 0xF8A22000
+
+/* DEVICES */
+#define REG_BASE_MCI 0xF9830000
+#define REG_BASE_UART0 0xF8B00000
+
+/* PERI control registers (4KB) */
+ /* USB2 PHY01 configuration register */
+#define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120)
+
+/* PERI CRG registers (4KB) */
+ /* USB2 CTRL0 clock and soft reset */
+#define PERI_CRG46 (REG_BASE_CRG + 0xb8)
+#define USB2_BUS_CKEN (1<<0)
+#define USB2_OHCI48M_CKEN (1<<1)
+#define USB2_OHCI12M_CKEN (1<<2)
+#define USB2_OTG_UTMI_CKEN (1<<3)
+#define USB2_HST_PHY_CKEN (1<<4)
+#define USB2_UTMI0_CKEN (1<<5)
+#define USB2_BUS_SRST_REQ (1<<12)
+#define USB2_UTMI0_SRST_REQ (1<<13)
+#define USB2_HST_PHY_SYST_REQ (1<<16)
+#define USB2_OTG_PHY_SYST_REQ (1<<17)
+#define USB2_CLK48_SEL (1<<20)
+
+ /* USB2 PHY clock and soft reset */
+#define PERI_CRG47 (REG_BASE_CRG + 0xbc)
+#define USB2_PHY01_REF_CKEN (1 << 0)
+#define USB2_PHY2_REF_CKEN (1 << 2)
+#define USB2_PHY01_SRST_REQ (1 << 4)
+#define USB2_PHY2_SRST_REQ (1 << 6)
+#define USB2_PHY01_SRST_TREQ0 (1 << 8)
+#define USB2_PHY01_SRST_TREQ1 (1 << 9)
+#define USB2_PHY2_SRST_TREQ (1 << 10)
+#define USB2_PHY01_REFCLK_SEL (1 << 12)
+#define USB2_PHY2_REFCLK_SEL (1 << 14)
+
+
+#endif
OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
--gap-fill=0
-u-boot-spi.gph: spl/u-boot-spl.gph u-boot-dtb.img FORCE
+u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
$(call if_changed,pad_cat)
ifndef CONFIG_SPL_BUILD
MKIMAGEFLAGS_MLO = -A $(ARCH) -T gpimage -C none \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot
-MLO: u-boot-dtb.bin FORCE
+MLO: u-boot.bin FORCE
$(call if_changed,mkimage)
@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
endif
__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
__raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
__raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
- if (!cpu_is_k2g())
- __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
+ __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
__raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
;
if (cpu_is_k2g()) {
- setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
- clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
- clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
- clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
- clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET,
+ phy_cfg->datx8_2_mask,
+ phy_cfg->datx8_2_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET,
+ phy_cfg->datx8_3_mask,
+ phy_cfg->datx8_3_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET,
+ phy_cfg->datx8_4_mask,
+ phy_cfg->datx8_4_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET,
+ phy_cfg->datx8_5_mask,
+ phy_cfg->datx8_5_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET,
+ phy_cfg->datx8_6_mask,
+ phy_cfg->datx8_6_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET,
+ phy_cfg->datx8_7_mask,
+ phy_cfg->datx8_7_val);
+
+ clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET,
+ phy_cfg->datx8_8_mask,
+ phy_cfg->datx8_8_val);
}
__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
unsigned int zq1cr1;
unsigned int zq2cr1;
unsigned int pir_v1;
+ unsigned int datx8_2_mask;
+ unsigned int datx8_2_val;
+ unsigned int datx8_3_mask;
+ unsigned int datx8_3_val;
+ unsigned int datx8_4_mask;
+ unsigned int datx8_4_val;
+ unsigned int datx8_5_mask;
+ unsigned int datx8_5_val;
+ unsigned int datx8_6_mask;
+ unsigned int datx8_6_val;
+ unsigned int datx8_7_mask;
+ unsigned int datx8_7_val;
+ unsigned int datx8_8_mask;
+ unsigned int datx8_8_val;
unsigned int pir_v2;
};
#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
+#define KS2_DDRPHY_DATX8_2_OFFSET 0x240
+#define KS2_DDRPHY_DATX8_3_OFFSET 0x280
#define KS2_DDRPHY_DATX8_4_OFFSET 0x2C0
#define KS2_DDRPHY_DATX8_5_OFFSET 0x300
#define KS2_DDRPHY_DATX8_6_OFFSET 0x340
#define PDQ_MASK 0x00000070
#define NOSRA_MASK 0x08000000
#define ECC_MASK 0x00000001
+#define DXEN_MASK 0x00000001
/* DDR3 definitions */
#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
}
/*
- * Overwrite the image headers after authentication
- * and decryption. Update size to reflect removal
- * of header.
- */
- memcpy(image, image + KS2_HS_SEC_HEADER_LEN, *p_size);
+ * Overwrite the image headers after authentication
+ * and decryption. Update size to reflect removal
+ * of header.
+ */
*p_size -= KS2_HS_SEC_HEADER_LEN;
+ memcpy(image, image + KS2_HS_SEC_HEADER_LEN, *p_size);
/*
* Output notification of successful authentication to re-assure the
set_uart_mux_conf();
setup_early_clocks();
uart_soft_reset();
+#ifdef CONFIG_SPL_BUILD
+ /*
+ * Save the boot parameters passed from romcode.
+ * We cannot delay the saving further than this,
+ * to prevent overwrites.
+ */
+ save_omap_boot_params();
+#endif
#ifdef CONFIG_DEBUG_UART_OMAP
debug_uart_init();
#endif
void spl_board_init(void)
{
- /*
- * Save the boot parameters passed from romcode.
- * We cannot delay the saving further than this,
- * to prevent overwrites.
- */
- save_omap_boot_params();
-
/* Prepare console output */
preloader_console_init();
do_io_settings();
#endif
setup_early_clocks();
+#ifdef CONFIG_SPL_BUILD
+ /*
+ * Save the boot parameters passed from romcode.
+ * We cannot delay the saving further than this,
+ * to prevent overwrites.
+ */
+ save_omap_boot_params();
+ spl_early_init();
+#endif
do_board_detect();
vcores_init();
#ifdef CONFIG_DEBUG_UART_OMAP
--- /dev/null
+if TARGET_POPLAR
+
+config SYS_BOARD
+ default "poplar"
+
+config SYS_VENDOR
+ default "hisilicon"
+
+config SYS_SOC
+ default "hi3798cv200"
+
+config SYS_CONFIG_NAME
+ default "poplar"
+
+endif
--- /dev/null
+Poplar BOARD
+M: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+S: Maintained
+F: board/hisilicon/poplar
+F: include/configs/poplar.h
+F: configs/poplar_defconfig
--- /dev/null
+#
+# (C) Copyright 2017 Linaro
+# Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-y := poplar.o
--- /dev/null
+================================================================================
+ Board Information
+================================================================================
+
+Developed by HiSilicon, the board features the Hi3798C V200 with an
+integrated quad-core 64-bit ARM Cortex A53 processor and high
+performance Mali T720 GPU, making it capable of running any commercial
+set-top solution based on Linux or Android. Its high performance
+specification also supports a premium user experience with up to H.265
+HEVC decoding of 4K video at 60 frames per second.
+
+SOC Hisilicon Hi3798CV200
+CPU Quad-core ARM Cortex-A53 64 bit
+DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
+USB Two USB 2.0 ports One USB 3.0 ports
+CONSOLE USB-micro port for console support
+ETHERNET 1 GBe Ethernet
+PCIE One PCIe 2.0 interfaces
+JTAG 8-Pin JTAG
+EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot
+DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
+WIFI 802.11AC 2*2 with Bluetooth
+CONNECTORS One connector for Smart Card One connector for TSI
+
+
+================================================================================
+ BUILD INSTRUCTIONS
+================================================================================
+
+Note of warning:
+================
+
+U-boot has a *strong* dependency with the l-loader and the arm trusted firmware
+repositories.
+
+The boot sequence is:
+ l-loader --> arm_trusted_firmware --> u-boot
+
+U-Boot needs to be aware of the BL31 runtime location and size to avoid writing
+over it. Currently, BL31 is being placed below the kernel text offset (check
+poplar.c) but this could change in the future.
+
+The current version of u-boot has been tested with:
+ - https://github.com/Linaro/poplar-l-loader.git
+
+ commit f0988698dcc5c08bd0a8f50aa0457e138a5f438c
+ Author: Alex Elder <elder@linaro.org>
+ Date: Fri Jun 16 08:57:59 2017 -0500
+
+ l-loader: use external memory region definitions
+
+ The ARM Trusted Firmware code now has a header file that collects
+ all the definitions for the memory regions used for its boot stages.
+ Include that file where needed, and use the definitions found therein
+
+ Signed-off-by: Alex Elder <elder@linaro.org>
+
+
+ - https://github.com/Linaro/poplar-arm-trusted-firmware.git
+
+ commit 6ac42dd3be13c99aa8ce29a15073e2f19d935f68
+ Author: Alex Elder <elder@linaro.org>
+ Date: Fri Jun 16 09:24:50 2017 -0500
+
+ poplar: define memory regions in a separate file
+
+ Separate the definitions for memory regions used for the BL stage
+ images and FIP into a new file. The "l-loader" image uses knowledge
+ of the sizes and locations of these memory regions, and it can now
+ include this (external) header to get these definitions, rather than
+ having to make coordinated changes to both code bases.
+
+ The new file has a complete set of definitions (more than may be
+ required by one or the other user). It also includes a summary of
+ how the boot process works, and how it uses these regions.
+
+ It should now be relatively easy to adjust the sizes and locations
+ of these memory regions, or to add to them (e.g. for TEE).
+
+ Signed-off-by: Alex Elder <elder@linaro.org>
+
+
+Compile from source:
+====================
+
+Get all the sources
+
+ > mkdir -p ~/poplar/src ~/poplar/bin
+ > cd ~/poplar/src
+ > git clone https://github.com/Linaro/poplar-l-loader.git l-loader
+ > git clone https://github.com/Linaro/poplar-arm-trusted-firmware.git atf
+ > git clone https://github.com/Linaro/poplar-u-boot.git u-boot
+
+Make sure you are using the correct branch on each one of these repositories.
+The definition of "correct" might change over time (at this moment in time this
+would be the "latest" branch).
+
+Compile U-Boot:
+===============
+
+ Prerequisite:
+ # sudo apt-get install device-tree-compiler
+
+ > cd ~/poplar/src/u-boot
+ > make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig
+ > make CROSS_COMPILE=aarch64-linux-gnu-
+ > cp u-boot.bin ~/poplar/bin
+
+Compile ARM Trusted Firmware (ATF):
+===================================
+
+ > cd ~/poplar/src/atf
+ > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+ SPD=none BL33=~/poplar/bin/u-boot.bin DEBUG=1 PLAT=poplar
+
+Copy resulting binaries
+ > cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/
+ > cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/
+
+Compile l-loader:
+=================
+
+ > cd ~/poplar/src/l-loader
+ > make clean
+ > make CROSS_COMPILE=arm-linux-gnueabi-
+
+ Due to BootROM requiremets, rename l-loader.bin to fastboot.bin:
+ > cp l-loader.bin ~/poplar/bin/fastboot.bin
+
+
+================================================================================
+ FLASH INSTRUCTIONS
+================================================================================
+
+Two methods:
+
+Using USB debrick support:
+ Copy fastboot.bin to a FAT partition on the USB drive and reboot the
+ poplar board while pressing S3(usb_boot).
+
+ The system will execute the new u-boot and boot into a shell which you
+ can then use to write to eMMC.
+
+Using U-BOOT from shell:
+ 1) using AXIS usb ethernet dongle and tftp
+ 2) using FAT formated USB drive
+
+
+1. TFTP (USB ethernet dongle)
+=============================
+
+Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board.
+Copy fastboot.bin to your tftp server.
+In u-boot make sure your network is properly setup.
+
+Then
+
+=> tftp 0x30000000 fastboot.bin
+starting USB...
+USB0: USB EHCI 1.00
+scanning bus 0 for devices... 1 USB Device(s) found
+USB1: USB EHCI 1.00
+scanning bus 1 for devices... 3 USB Device(s) found
+ scanning usb for storage devices... 0 Storage Device(s) found
+ scanning usb for ethernet devices... 1 Ethernet Device(s) found
+Waiting for Ethernet connection... done.
+Using asx0 device
+TFTP from server 192.168.1.4; our IP address is 192.168.1.10
+Filename 'poplar/fastboot.bin'.
+Load address: 0x30000000
+Loading: #################################################################
+ #################################################################
+ ###############################################################
+ 2 MiB/s
+done
+Bytes transferred = 983040 (f0000 hex)
+
+=> mmc write 0x30000000 0 0x780
+
+MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
+=> reset
+
+
+2. USING USB FAT DRIVE
+=======================
+
+Copy fastboot.bin to any partition on a FAT32 formated usb flash drive.
+Enter the uboot prompt
+
+=> fatls usb 0:2
+ 983040 fastboot.bin
+
+1 file(s), 0 dir(s)
+
+=> fatload usb 0:2 0x30000000 fastboot.bin
+reading fastboot.bin
+983040 bytes read in 44 ms (21.3 MiB/s)
+
+=> mmc write 0x30000000 0 0x780
+
+MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
+
+
+================================================================================
+ BOOT TRACE
+================================================================================
+
+Bootrom start
+Boot Media: eMMC
+Decrypt auxiliary code ...OK
+
+lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000
+
+Entry boot auxiliary code
+
+Auxiliary code - v1.00
+DDR code - V1.1.2 20160205
+Build: Mar 24 2016 - 17:09:44
+Reg Version: v134
+Reg Time: 2016/03/18 09:44:55
+Reg Name: hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg
+
+Boot auxiliary code success
+Bootrom success
+
+LOADER: Switched to aarch64 mode
+LOADER: Entering ARM TRUSTED FIRMWARE
+LOADER: CPU0 executes at 0x000ce000
+
+INFO: BL1: 0xe1000 - 0xe7000 [size = 24576]
+NOTICE: Booting Trusted Firmware
+NOTICE: BL1: v1.3(debug):v1.3-372-g1ba9c60
+NOTICE: BL1: Built : 17:51:33, Apr 30 2017
+INFO: BL1: RAM 0xe1000 - 0xe7000
+INFO: BL1: Loading BL2
+INFO: Loading image id=1 at address 0xe9000
+INFO: Image id=1 loaded at address 0xe9000, size = 0x5008
+NOTICE: BL1: Booting BL2
+INFO: Entry point address = 0xe9000
+INFO: SPSR = 0x3c5
+NOTICE: BL2: v1.3(debug):v1.3-372-g1ba9c60
+NOTICE: BL2: Built : 17:51:33, Apr 30 2017
+INFO: BL2: Loading BL31
+INFO: Loading image id=3 at address 0x129000
+INFO: Image id=3 loaded at address 0x129000, size = 0x8038
+INFO: BL2: Loading BL33
+INFO: Loading image id=5 at address 0x37000000
+INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17
+NOTICE: BL1: Booting BL31
+INFO: Entry point address = 0x129000
+INFO: SPSR = 0x3cd
+INFO: Boot bl33 from 0x37000000 for 364311 Bytes
+NOTICE: BL31: v1.3(debug):v1.3-372-g1ba9c60
+NOTICE: BL31: Built : 17:51:33, Apr 30 2017
+INFO: BL31: Initializing runtime services
+INFO: BL31: Preparing for EL3 exit to normal world
+INFO: Entry point address = 0x37000000
+INFO: SPSR = 0x3c9
+
+
+U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar
+
+Model: HiSilicon Poplar Development Board
+BOARD: Hisilicon HI3798cv200 Poplar
+DRAM: 1 GiB
+MMC: Hisilicon DWMMC: 0
+In: serial@f8b00000
+Out: serial@f8b00000
+Err: serial@f8b00000
+Net: Net Initialization Skipped
+No ethernet found.
+
+Hit any key to stop autoboot: 0
+starting USB...
+USB0: USB EHCI 1.00
+scanning bus 0 for devices... 1 USB Device(s) found
+USB1: USB EHCI 1.00
+scanning bus 1 for devices... 4 USB Device(s) found
+ scanning usb for storage devices... 1 Storage Device(s) found
+ scanning usb for ethernet devices... 1 Ethernet Device(s) found
+
+USB device 0:
+ Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade
+ Type: Removable Hard Disk
+ Capacity: 7632.0 MB = 7.4 GB (15630336 x 512)
+... is now current device
+Scanning usb 0:1...
+=>
--- /dev/null
+/*
+ * (C) Copyright 2017 Linaro
+ * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm.h>
+#include <common.h>
+#include <asm/io.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <asm/arch/hi3798cv200.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region poplar_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = poplar_mem_map;
+
+static const struct pl01x_serial_platdata serial_platdata = {
+ .base = REG_BASE_UART0,
+ .type = TYPE_PL010,
+ .clock = 75000000,
+};
+
+U_BOOT_DEVICE(poplar_serial) = {
+ .name = "serial_pl01x",
+ .platdata = &serial_platdata,
+};
+
+int checkboard(void)
+{
+ puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(NULL, 0x80000000);
+
+ return 0;
+}
+
+/*
+ * Some linux kernel versions don't use memory before its load address, so to
+ * be generic we just pretend it isn't there. In previous uboot versions we
+ * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
+ * could persist in memory and be left alone by the kernel.
+ *
+ * That led to a problem when mapping memory in older kernels. That PSCI code
+ * now lies in memory below the kernel load offset; it therefore won't be
+ * touched by the kernel, and by not specially reserving it we avoid the mapping
+ * problem as well.
+ *
+ */
+#define KERNEL_TEXT_OFFSET 0x00080000
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
+ gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
+
+ return 0;
+}
+
+static void usb2_phy_config(void)
+{
+ const u32 config[] = {
+ /* close EOP pre-emphasis. open data pre-emphasis */
+ 0xa1001c,
+ /* Rcomp = 150mW, increase DC level */
+ 0xa00607,
+ /* keep Rcomp working */
+ 0xa10700,
+ /* Icomp = 212mW, increase current drive */
+ 0xa00aab,
+ /* EMI fix: rx_active not stay 1 when error packets received */
+ 0xa11140,
+ /* Comp mode select */
+ 0xa11041,
+ /* adjust eye diagram */
+ 0xa0098c,
+ /* adjust eye diagram */
+ 0xa10a0a,
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(config); i++) {
+ writel(config[i], PERI_CTRL_USB0);
+ clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
+ udelay(20);
+ }
+}
+
+static void usb2_phy_init(void)
+{
+ /* reset usb2 controller bus/utmi/roothub */
+ setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
+ USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
+ udelay(200);
+
+ /* reset usb2 phy por/utmi */
+ setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
+ udelay(200);
+
+ /* open usb2 ref clk */
+ setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
+ udelay(300);
+
+ /* cancel usb2 power on reset */
+ clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
+ udelay(500);
+
+ usb2_phy_config();
+
+ /* cancel usb2 port reset, wait comp circuit stable */
+ clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
+ mdelay(10);
+
+ /* open usb2 controller clk */
+ setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
+ USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
+ USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
+ udelay(200);
+
+ /* cancel usb2 control reset */
+ clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
+ USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
+ udelay(200);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ ret = hi6220_dwmci_add_port(0, REG_BASE_MCI, 8);
+ if (ret)
+ printf("mmc init error (%d)\n", ret);
+
+ return ret;
+}
+
+int board_init(void)
+{
+ usb2_phy_init();
+
+ return 0;
+}
+
return 0;
}
+int __maybe_unused ti_i2c_eeprom_am_set(const char *name, const char *rev)
+{
+ struct ti_common_eeprom *ep;
+
+ if (!name || !rev)
+ return -1;
+
+ ep = TI_EEPROM_DATA;
+ if (ep->header == TI_EEPROM_HEADER_MAGIC)
+ goto already_set;
+
+ /* Set to 0 all fields */
+ memset(ep, 0, sizeof(*ep));
+ strncpy(ep->name, name, TI_EEPROM_HDR_NAME_LEN);
+ strncpy(ep->version, rev, TI_EEPROM_HDR_REV_LEN);
+ /* Some dummy serial number to identify the platform */
+ strncpy(ep->serial, "0000", TI_EEPROM_HDR_SERIAL_LEN);
+ /* Mark it with a valid header */
+ ep->header = TI_EEPROM_HEADER_MAGIC;
+
+already_set:
+ return 0;
+}
+
int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
{
int rc;
}
}
}
+
+bool __maybe_unused board_ti_was_eeprom_read(void)
+{
+ struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+ if (ep->header == TI_EEPROM_HEADER_MAGIC)
+ return true;
+ else
+ return false;
+}
*/
void board_ti_set_ethaddr(int index);
+/**
+ * board_ti_was_eeprom_read() - Check to see if the eeprom contents have been read
+ *
+ * This function is useful to determine if the eeprom has already been read and
+ * its contents have already been loaded into memory. It utiltzes the magic
+ * number that the header value is set to upon successful eeprom read.
+ */
+bool board_ti_was_eeprom_read(void);
+
+/**
+ * ti_i2c_eeprom_am_set() - Setup the eeprom data with predefined values
+ * @name: Name of the board
+ * @rev: Revision of the board
+ *
+ * In some cases such as in RTC-only mode, we are able to skip reading eeprom
+ * and wasting i2c based initialization time by using predefined flags for
+ * detecting what platform we are booting on. For those platforms, provide
+ * a handy function to pre-program information.
+ *
+ * NOTE: many eeprom information such as serial number, mac address etc is not
+ * available.
+ *
+ * Return: 0 if all went fine, else return error.
+ */
+int ti_i2c_eeprom_am_set(const char *name, const char *rev);
+
#endif /* __BOARD_DETECT_H */
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
#if defined(CONFIG_TI_AEMIF)
- aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+ if (!board_is_k2g_ice())
+ aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
#endif
- if (ddr3_size)
- ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
- else
- ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, gd->ram_size >> 30);
+ if (!board_is_k2g_ice()) {
+ if (ddr3_size)
+ ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+ else
+ ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
+ gd->ram_size >> 30);
+ }
return 0;
}
ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
}
#endif /* CONFIG_OF_BOARD_SETUP */
+
+#if defined(CONFIG_DTB_RESELECT)
+int __weak embedded_dtb_select(void)
+{
+ return 0;
+}
+#endif
#define _KS2_BOARD
#include <asm/ti-common/keystone_net.h>
+#include "../common/board_detect.h"
extern struct eth_priv_t eth_priv_cfg[];
+#if defined(CONFIG_TI_I2C_BOARD_DETECT)
+static inline int board_is_k2g_gp(void)
+{
+ return board_ti_is("66AK2GGP");
+}
+static inline int board_is_k2g_ice(void)
+{
+ return board_ti_is("66AK2GIC");
+}
+#else
+static inline int board_is_k2g_gp(void)
+{
+ return false;
+}
+static inline int board_is_k2g_ice(void)
+{
+ return false;
+}
+#endif
+
int get_num_eth_ports(void);
void spl_init_keystone_plls(void);
}
#endif
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "keystone-k2e-evm"))
+ return 0;
+
+ return -1;
+}
+#endif
+
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
#include <asm/ti-common/keystone_net.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/mmc_host_def.h>
+#include <fdtdec.h>
+#include <i2c.h>
#include "mux-k2g.h"
#include "../common/board_detect.h"
+#define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
+
const unsigned int sysclk_array[MAX_SYSCLK] = {
19200000,
24000000,
return -1;
}
- omap_mmc_init(0, 0, 0, -1, -1);
+ if (board_is_k2g_gp())
+ omap_mmc_init(0, 0, 0, -1, -1);
+
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
#endif
-#ifdef CONFIG_BOARD_EARLY_INIT_F
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+ bool eeprom_read = board_ti_was_eeprom_read();
+
+ if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
+ return 0;
+ else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
+ return 0;
+ else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
+ return 0;
+ else
+ return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+static int k2g_alt_board_detect(void)
+{
+ int rc;
+
+ rc = i2c_set_bus_num(1);
+ if (rc)
+ return rc;
+
+ rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
+ if (rc)
+ return rc;
+
+ ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
+
+ return 0;
+}
static void k2g_reset_mux_config(void)
{
setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
}
-int board_early_init_f(void)
+int embedded_dtb_select(void)
{
- init_plls();
+ int rc;
+ rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS);
+ if (rc) {
+ rc = k2g_alt_board_detect();
+ if (rc) {
+ printf("Unable to do board detection\n");
+ return -1;
+ }
+ }
+
+ fdtdec_setup();
k2g_mux_config();
k2g_reset_mux_config();
- /* deassert FLASH_HOLD */
- clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
- BIT(9));
- setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
- BIT(9));
+ if (board_is_k2g_gp()) {
+ /* deassert FLASH_HOLD */
+ clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
+ BIT(9));
+ setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
+ BIT(9));
+ }
return 0;
}
board_ti_set_ethaddr(1);
#endif
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if (board_is_k2g_gp())
+ setenv("board_name", "66AK2GGP\0");
+ else if (board_is_k2g_ice())
+ setenv("board_name", "66AK2GIC\0");
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ init_plls();
+
+ k2g_mux_config();
+
return 0;
}
#endif
}
#endif
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "keystone-k2hk-evm"))
+ return 0;
+
+ return -1;
+}
+#endif
+
#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
}
#endif
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "keystone-k2l-evm"))
+ return 0;
+
+ return -1;
+}
+#endif
+
#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
+#include "board.h"
+/* K2G GP EVM DDR3 Configuration */
struct ddr3_phy_config ddr3phy_800_2g = {
.pllcr = 0x000DC000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.dtpr2 = 0x50022A00ul,
.mr0 = 0x00001430ul,
.mr1 = 0x00000006ul,
- .mr2 = 0x00000018ul,
+ .mr2 = 0x00000000ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F03D09ul,
.zq0cr1 = 0x0001005Dul,
.zq1cr1 = 0x0001005Bul,
.zq2cr1 = 0x0001005Bul,
.pir_v1 = 0x00000033ul,
+ .datx8_2_mask = 0,
+ .datx8_2_val = 0,
+ .datx8_3_mask = 0,
+ .datx8_3_val = 0,
+ .datx8_4_mask = 0,
+ .datx8_4_val = ((1 << 0)),
+ .datx8_5_mask = DXEN_MASK,
+ .datx8_5_val = 0,
+ .datx8_6_mask = DXEN_MASK,
+ .datx8_6_val = 0,
+ .datx8_7_mask = DXEN_MASK,
+ .datx8_7_val = 0,
+ .datx8_8_mask = DXEN_MASK,
+ .datx8_8_val = 0,
.pir_v2 = 0x00000F81ul,
};
.sdrfc = 0x00000C34ul,
};
+/* K2G ICE evm DDR3 Configuration */
+struct ddr3_phy_config ddr3phy_800_512mb = {
+ .pllcr = 0x000DC000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0,
+ .ptr3 = 0x06C30D40ul,
+ .ptr4 = 0x06413880ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x550E6644ul,
+ .dtpr1 = 0x32834200ul,
+ .dtpr2 = 0x50022A00ul,
+ .mr0 = 0x00001430ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000008ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F03D09ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .datx8_2_mask = DXEN_MASK,
+ .datx8_2_val = 0,
+ .datx8_3_mask = DXEN_MASK,
+ .datx8_3_val = 0,
+ .datx8_4_mask = DXEN_MASK,
+ .datx8_4_val = 0,
+ .datx8_5_mask = DXEN_MASK,
+ .datx8_5_val = 0,
+ .datx8_6_mask = DXEN_MASK,
+ .datx8_6_val = 0,
+ .datx8_7_mask = DXEN_MASK,
+ .datx8_7_val = 0,
+ .datx8_8_mask = DXEN_MASK,
+ .datx8_8_val = 0,
+ .pir_v2 = 0x00000F81ul,
+};
+
+struct ddr3_emif_config ddr3_800_512mb = {
+ .sdcfg = 0x62006662ul,
+ .sdtim1 = 0x0A385033ul,
+ .sdtim2 = 0x00001CA5ul,
+ .sdtim3 = 0x21ADFF32ul,
+ .sdtim4 = 0x533F067Ful,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00000C34ul,
+};
+
u32 ddr3_init(void)
{
/* Reset DDR3 PHY after PLL enabled */
ddr3_reset_ddrphy();
- ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
- ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
+ if (board_is_k2g_gp()) {
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
+ } else if (board_is_k2g_ice()) {
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb);
+ }
return 0;
}
#include <asm/io.h>
#include <asm/arch/mux-k2g.h>
#include <asm/arch/hardware.h>
+#include "board.h"
+
+struct pin_cfg k2g_generic_pin_cfg[] = {
+ /* UART0 */
+ { 115, MODE(0) }, /* SOC_UART0_RXD */
+ { 116, MODE(0) }, /* SOC_UART0_TXD */
+
+ /* I2C 0 */
+ { 223, MODE(0) }, /* SOC_I2C0_SCL */
+ { 224, MODE(0) }, /* SOC_I2C0_SDA */
+
+ /* I2C 1 */
+ { 225, MODE(0) }, /* SOC_I2C1_SCL */
+ { 226, MODE(0) }, /* SOC_I2C1_SDA */
+ { MAX_PIN_N, }
+};
struct pin_cfg k2g_evm_pin_cfg[] = {
/* GPMC */
{ MAX_PIN_N, }
};
+struct pin_cfg k2g_ice_evm_pin_cfg[] = {
+ /* MMC 1 */
+ { 63, MODE(0) | PIN_PTD }, /* MMC1_DAT3.MMC1_DAT3 */
+ { 64, MODE(0) | PIN_PTU }, /* MMC1_DAT2.MMC1_DAT2 */
+ { 65, MODE(0) | PIN_PTU }, /* MMC1_DAT1.MMC1_DAT1 */
+ { 66, MODE(0) | PIN_PTD }, /* MMC1_DAT0.MMC1_DAT0 */
+ { 67, MODE(0) | PIN_PTD }, /* MMC1_CLK.MMC1_CLK */
+ { 68, MODE(0) | PIN_PTD }, /* MMC1_CMD.MMC1_CMD */
+ { 69, MODE(3) | PIN_PTU }, /* MMC1_SDCD.GPIO0_69 */
+ { 70, MODE(0) | PIN_PTU }, /* MMC1_SDWP.MMC1_SDWP */
+ { 71, MODE(0) | PIN_PTD }, /* MMC1_POW.MMC1_POW */
+
+ /* I2C 0 */
+ { 223, MODE(0) }, /* SOC_I2C0_SCL */
+ { 224, MODE(0) }, /* SOC_I2C0_SDA */
+ { MAX_PIN_N, }
+};
+
void k2g_mux_config(void)
{
- configure_pin_mux(k2g_evm_pin_cfg);
+ if (!board_ti_was_eeprom_read()) {
+ configure_pin_mux(k2g_generic_pin_cfg);
+ } else if (board_is_k2g_gp()) {
+ configure_pin_mux(k2g_evm_pin_cfg);
+ } else if (board_is_k2g_ice()) {
+ configure_pin_mux(k2g_ice_evm_pin_cfg);
+ } else {
+ puts("Unknown board, cannot configure pinmux.");
+ hang();
+ }
}
endmenu
+config DTB_RESELECT
+ bool "Support swapping dtbs at a later point in boot"
+ depends on FIT_EMBED
+ help
+ It is possible during initial boot you may need to use a generic
+ dtb until you can fully determine the board your running on. This
+ config allows boards to implement a function at a later point
+ during boot to switch to the "correct" dtb.
+
+config FIT_EMBED
+ bool "Support a FIT image embedded in the U-boot image"
+ help
+ This option provides hooks to allow U-boot to parse an
+ appended FIT image and enable board specific code to then select
+ the correct DTB to be used.
+
config DEFAULT_FDT_FILE
string "Default fdt file"
help
obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
+obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o
obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
obj-$(CONFIG_SPL_OF_LIBFDT) += fdt_support.o
ifdef CONFIG_SPL_USB_HOST_SUPPORT
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
obj-$(CONFIG_$(SPL_)FIT) += image-fit.o
+obj-$(CONFIG_FIT_EMBED) += boot_fit.o common_fit.o
obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += image-sig.o
obj-$(CONFIG_IO_TRACE) += iotrace.o
obj-y += memsize.o
#if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo, /* display cpu info (and speed) */
#endif
+#if defined(CONFIG_DTB_RESELECT)
+ embedded_dtb_select,
+#endif
#if defined(CONFIG_DISPLAY_BOARDINFO)
show_board_info,
#endif
--- /dev/null
+/*
+ * (C) Copyright 2017
+ * Texas Instruments, <www.ti.com>
+ *
+ * Franklin S Cooper Jr. <fcooper@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <boot_fit.h>
+#include <common.h>
+#include <errno.h>
+#include <image.h>
+#include <libfdt.h>
+
+int fdt_offset(void *fit)
+{
+ int images, node, fdt_len, fdt_node, fdt_offset;
+ const char *fdt_name;
+
+ node = fit_find_config_node(fit);
+ if (node < 0)
+ return node;
+
+ images = fdt_path_offset(fit, FIT_IMAGES_PATH);
+ if (images < 0) {
+ debug("%s: Cannot find /images node: %d\n", __func__, images);
+ return FDT_ERROR;
+ }
+
+ fdt_name = fdt_getprop(fit, node, FIT_FDT_PROP, &fdt_len);
+ if (!fdt_name) {
+ debug("%s: Cannot find fdt name property: %d\n",
+ __func__, fdt_len);
+ return -EINVAL;
+ }
+
+ fdt_node = fdt_subnode_offset(fit, images, fdt_name);
+ if (fdt_node < 0) {
+ debug("%s: Cannot find fdt node '%s': %d\n",
+ __func__, fdt_name, fdt_node);
+ return -EINVAL;
+ }
+
+ fdt_offset = fdt_getprop_u32(fit, fdt_node, "data-offset");
+
+ if (fdt_offset == FDT_ERROR)
+ return -ENOENT;
+
+ fdt_len = fdt_getprop_u32(fit, fdt_node, "data-size");
+
+ if (fdt_len < 0)
+ return fdt_len;
+
+ return fdt_offset;
+}
+
+void *locate_dtb_in_fit(void *fit)
+{
+ struct image_header *header;
+ int size;
+ int ret;
+
+ size = fdt_totalsize(fit);
+ size = (size + 3) & ~3;
+
+ header = (struct image_header *)fit;
+
+ if (image_get_magic(header) != FDT_MAGIC) {
+ debug("No FIT image appended to U-boot\n");
+ return NULL;
+ }
+
+ ret = fdt_offset(fit);
+
+ if (ret <= 0)
+ return NULL;
+ else
+ return (void *)fit+size+ret;
+}
--- /dev/null
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <image.h>
+#include <libfdt.h>
+#include <spl.h>
+
+ulong fdt_getprop_u32(const void *fdt, int node, const char *prop)
+{
+ const u32 *cell;
+ int len;
+
+ cell = fdt_getprop(fdt, node, prop, &len);
+ if (!cell || len != sizeof(*cell))
+ return FDT_ERROR;
+
+ return fdt32_to_cpu(*cell);
+}
+
+/*
+ * Iterate over all /configurations subnodes and call a platform specific
+ * function to find the matching configuration.
+ * Returns the node offset or a negative error number.
+ */
+int fit_find_config_node(const void *fdt)
+{
+ const char *name;
+ int conf, node, len;
+
+ conf = fdt_path_offset(fdt, FIT_CONFS_PATH);
+ if (conf < 0) {
+ debug("%s: Cannot find /configurations node: %d\n", __func__,
+ conf);
+ return -EINVAL;
+ }
+ for (node = fdt_first_subnode(fdt, conf);
+ node >= 0;
+ node = fdt_next_subnode(fdt, node)) {
+ name = fdt_getprop(fdt, node, "description", &len);
+ if (!name) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("%s: Missing FDT description in DTB\n",
+ __func__);
+#endif
+ return -EINVAL;
+ }
+ if (board_fit_config_name_match(name))
+ continue;
+
+ debug("Selecting config '%s'", name);
+
+ return node;
+ }
+
+ return -ENOENT;
+}
#include <libfdt.h>
#include <spl.h>
-#define FDT_ERROR ((ulong)(-1))
-
-static ulong fdt_getprop_u32(const void *fdt, int node, const char *prop)
-{
- const u32 *cell;
- int len;
-
- cell = fdt_getprop(fdt, node, prop, &len);
- if (!cell || len != sizeof(*cell))
- return FDT_ERROR;
-
- return fdt32_to_cpu(*cell);
-}
-
-/*
- * Iterate over all /configurations subnodes and call a platform specific
- * function to find the matching configuration.
- * Returns the node offset or a negative error number.
- */
-static int spl_fit_find_config_node(const void *fdt)
-{
- const char *name;
- int conf, node, len;
-
- conf = fdt_path_offset(fdt, FIT_CONFS_PATH);
- if (conf < 0) {
- debug("%s: Cannot find /configurations node: %d\n", __func__,
- conf);
- return -EINVAL;
- }
- for (node = fdt_first_subnode(fdt, conf);
- node >= 0;
- node = fdt_next_subnode(fdt, node)) {
- name = fdt_getprop(fdt, node, "description", &len);
- if (!name) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("%s: Missing FDT description in DTB\n",
- __func__);
-#endif
- return -EINVAL;
- }
- if (board_fit_config_name_match(name))
- continue;
-
- debug("Selecting config '%s'", name);
-
- return node;
- }
-
- return -ENOENT;
-}
-
/**
* spl_fit_get_image_node(): By using the matching configuration subnode,
* retrieve the name of an image, specified by a property name and an index
int node, conf_node;
int len, i;
- conf_node = spl_fit_find_config_node(fit);
+ conf_node = fit_find_config_node(fit);
if (conf_node < 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("No matching DT out of these options:\n");
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
+CONFIG_OF_LIST="keystone-k2e-evm"
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
+CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice"
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
+CONFIG_OF_LIST="keystone-k2hk-evm"
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
+CONFIG_DTB_RESELECT=y
+CONFIG_FIT_EMBED=y
+CONFIG_OF_LIST="keystone-k2l-evm"
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_POPLAR=y
+CONFIG_IDENT_STRING="poplar"
+CONFIG_DEFAULT_DEVICE_TREE="hi3798cv200-poplar"
+CONFIG_SYS_PROMPT="poplar# "
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DISPLAY_CPUINFO=n
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_ISO_PARTITION=n
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_K3=y
+CONFIG_PL011_SERIAL=y
+CONFIG_PSCI_RESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_NET=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_DM_GPIO is not set
+CONFIG_LIB_RAND=y
+CONFIG_CMD_UNZIP=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+
static int hi6220_dwmci_core_init(struct dwmci_host *host, int index)
{
- host->name = "HiKey DWMMC";
+ host->name = "Hisilicon DWMMC";
host->dev_index = index;
void stm32_flash_latency_cfg(int latency)
{
/* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
- writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
+ writel(FLASH_ACR_WS(latency) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
| FLASH_ACR_DCEN, &STM32_FLASH->acr);
}
config PIPE3_PHY
bool "Support omap's PIPE3 PHY"
- depends on PHY && ARCH_OMAP2
+ depends on PHY && ARCH_OMAP2PLUS
help
Support for the omap PIPE3 phy for sata
config SPL_PIPE3_PHY
bool "Support omap's PIPE3 PHY in SPL"
- depends on SPL_PHY && ARCH_OMAP2
+ depends on SPL_PHY && ARCH_OMAP2PLUS
help
Support for the omap PIPE3 phy for sata in SPL
return 0;
}
-static int stm32_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
+static int stm32_pinctrl_config(int offset)
{
u32 pin_mux[MAX_PINS_ONE_IP];
- struct fdtdec_phandle_args args;
int rv, len;
- /* Get node pinctrl-0 */
- rv = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(periph),
- "pinctrl-0", 0, 0, 0, &args);
- if (rv)
- return rv;
/*
* check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
* usart1) of pin controller phandle "pinctrl-0"
* */
- fdt_for_each_subnode(args.node, gd->fdt_blob, args.node) {
+ fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
struct stm32_gpio_dsc gpio_dsc;
struct stm32_gpio_ctl gpio_ctl;
int i;
- len = fdtdec_get_int_array_count(gd->fdt_blob, args.node,
+ len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
"pinmux", pin_mux,
ARRAY_SIZE(pin_mux));
- debug("%s: periph->name = %s, no of pinmux entries= %d\n",
- __func__, periph->name, len);
+ debug("%s: no of pinmux entries= %d\n", __func__, len);
if (len < 0)
return -EINVAL;
for (i = 0; i < len; i++) {
struct gpio_desc desc;
debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
- prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), args.node);
+ prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
rv = uclass_get_device_by_seq(UCLASS_GPIO,
gpio_dsc.port, &desc.dev);
if (rv)
return 0;
}
+#if CONFIG_IS_ENABLED(PINCTRL_FULL)
+static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ return stm32_pinctrl_config(dev_of_offset(config));
+}
+#else /* PINCTRL_FULL */
+static int stm32_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ const void *fdt = gd->fdt_blob;
+ const fdt32_t *list;
+ uint32_t phandle;
+ int config_node;
+ int size, i, ret;
+
+ list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
+ if (!list)
+ return -EINVAL;
+
+ debug("%s: periph->name = %s\n", __func__, periph->name);
+
+ size /= sizeof(*list);
+ for (i = 0; i < size; i++) {
+ phandle = fdt32_to_cpu(*list++);
+
+ config_node = fdt_node_offset_by_phandle(fdt, phandle);
+ if (config_node < 0) {
+ error("prop pinctrl-0 index %d invalid phandle\n", i);
+ return -EINVAL;
+ }
+
+ ret = stm32_pinctrl_config(config_node);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif /* PINCTRL_FULL */
+
static struct pinctrl_ops stm32_pinctrl_ops = {
+#if CONFIG_IS_ENABLED(PINCTRL_FULL)
+ .set_state = stm32_pinctrl_set_state,
+#else /* PINCTRL_FULL */
.set_state_simple = stm32_pinctrl_set_state_simple,
+#endif /* PINCTRL_FULL */
};
static const struct udevice_id stm32_pinctrl_ids[] = {
config OF_LIST
string "List of device tree files to include for DT control"
- depends on SPL_LOAD_FIT
+ depends on SPL_LOAD_FIT || FIT_EMBED
default DEFAULT_DEVICE_TREE
help
This option specifies a list of device tree files to use for DT
- control. These will be packaged into a FIT. At run-time, SPL will
- select the correct DT to use by examining the hardware (e.g.
- reading a board ID value). This is a list of device tree files
- (without the directory or .dtb suffix) separated by <space>.
+ control. These will be packaged into a FIT. At run-time, U-boot
+ or SPL will select the correct DT to use by examining the
+ hardware (e.g. reading a board ID value). This is a list of
+ device tree files (without the directory or .dtb suffix)
+ separated by <space>.
config OF_SPL_REMOVE_PROPS
string "List of device tree properties to drop for SPL"
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments
+ * Written by Franklin Cooper Jr. <fcooper@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+int fdt_offset(void *fit);
+void *locate_dtb_in_fit(void *fit);
void pci_init (void);
void pci_init_board(void);
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void);
+#endif
+
int misc_init_f (void);
int misc_init_r (void);
/* Platform type */
#define CONFIG_SOC_K2G
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DEFAULT_MMC_TI_ARGS \
"rd_spec=-\0" \
"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \
- "name_fdt=keystone-k2g-evm.dtb\0" \
+ "findfdt="\
+ "if test $board_name = 66AK2GGP; then " \
+ "setenv name_fdt keystone-k2g-evm.dtb; " \
+ "else if test $board_name = 66AK2GIC; then " \
+ "setenv name_fdt keystone-k2g-ice.dtb; " \
+ "else if test $name_fdt = undefined; then " \
+ "echo WARNING: Could not determine device tree to use;"\
+ "fi;fi;fi;\0" \
"name_mon=skern-k2g.bin\0" \
"name_ubi=k2g-evm-ubifs.ubi\0" \
"name_uboot=u-boot-spi-k2g-evm.gph\0" \
"run envboot; " \
"run set_name_pmmc init_${boot} init_fw_rd_${boot} " \
"get_pmmc_${boot} run_pmmc get_mon_${boot} run_mon " \
- "get_fdt_${boot} get_kern_${boot} run_kern"
+ "findfdt get_fdt_${boot} get_kern_${boot} run_kern"
/* SPL SPI Loader Configuration */
#define CONFIG_SPL_TEXT_BASE 0x0c080000
--- /dev/null
+/*
+ * (C) Copyright 2017 Linaro
+ *
+ * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * Configuration for Poplar 96boards CE. Parts were derived from other ARM
+ * configurations.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _POPLAR_H_
+#define _POPLAR_H_
+
+#include <linux/sizes.h>
+
+/* DRAM banks */
+#define CONFIG_NR_DRAM_BANKS 2
+
+/* SYS */
+#define CONFIG_SYS_BOOTM_LEN 0x1400000
+#define CONFIG_SYS_INIT_SP_ADDR 0x200000
+#define CONFIG_SYS_LOAD_ADDR 0x800000
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+
+/* ATF bl33.bin load address (must match) */
+#define CONFIG_SYS_TEXT_BASE 0x37000000
+
+/* PL010/PL011 */
+#define CONFIG_PL01X_SERIAL
+
+/* USB configuration */
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* SD/MMC */
+#define CONFIG_BOUNCE_BUFFER
+
+/*****************************************************************************
+ * Initial environment variables
+ *****************************************************************************/
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
+ func(DHCP, dhcp, na)
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+#include <config_distro_bootcmd.h>
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loader_mmc_blknum=0x0\0" \
+ "loader_mmc_nblks=0x780\0" \
+ "env_mmc_blknum=0x780\0" \
+ "env_mmc_nblks=0x80\0" \
+ "kernel_addr_r=0x30000000\0" \
+ "pxefile_addr_r=0x32000000\0" \
+ "scriptaddr=0x32000000\0" \
+ "fdt_addr_r=0x32200000\0" \
+ "fdtfile=hisilicon/hi3798cv200-poplar.dtb\0" \
+ "ramdisk_addr_r=0x32400000\0" \
+ BOOTENV
+
+
+/* Command line configuration */
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET (0x780 * 512) /* env_mmc_blknum */
+#define CONFIG_ENV_SIZE 0x10000 /* env_mmc_nblks bytes */
+#define CONFIG_FAT_WRITE
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+
+/* Monitor Command Prompt */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#endif /* _POPLAR_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HISTB_CLOCK_H
+#define __DTS_HISTB_CLOCK_H
+
+/* clocks provided by core CRG */
+#define HISTB_OSC_CLK 0
+#define HISTB_APB_CLK 1
+#define HISTB_AHB_CLK 2
+#define HISTB_UART1_CLK 3
+#define HISTB_UART2_CLK 4
+#define HISTB_UART3_CLK 5
+#define HISTB_I2C0_CLK 6
+#define HISTB_I2C1_CLK 7
+#define HISTB_I2C2_CLK 8
+#define HISTB_I2C3_CLK 9
+#define HISTB_I2C4_CLK 10
+#define HISTB_I2C5_CLK 11
+#define HISTB_SPI0_CLK 12
+#define HISTB_SPI1_CLK 13
+#define HISTB_SPI2_CLK 14
+#define HISTB_SCI_CLK 15
+#define HISTB_FMC_CLK 16
+#define HISTB_MMC_BIU_CLK 17
+#define HISTB_MMC_CIU_CLK 18
+#define HISTB_MMC_DRV_CLK 19
+#define HISTB_MMC_SAMPLE_CLK 20
+#define HISTB_SDIO0_BIU_CLK 21
+#define HISTB_SDIO0_CIU_CLK 22
+#define HISTB_SDIO0_DRV_CLK 23
+#define HISTB_SDIO0_SAMPLE_CLK 24
+#define HISTB_PCIE_AUX_CLK 25
+#define HISTB_PCIE_PIPE_CLK 26
+#define HISTB_PCIE_SYS_CLK 27
+#define HISTB_PCIE_BUS_CLK 28
+#define HISTB_ETH0_MAC_CLK 29
+#define HISTB_ETH0_MACIF_CLK 30
+#define HISTB_ETH1_MAC_CLK 31
+#define HISTB_ETH1_MACIF_CLK 32
+#define HISTB_COMBPHY1_CLK 33
+
+
+/* clocks provided by mcu CRG */
+#define HISTB_MCE_CLK 1
+#define HISTB_IR_CLK 2
+#define HISTB_TIMER01_CLK 3
+#define HISTB_LEDC_CLK 4
+#define HISTB_UART0_CLK 5
+#define HISTB_LSADC_CLK 6
+
+#endif /* __DTS_HISTB_CLOCK_H */
--- /dev/null
+/*
+ * TI Syscon Reset definitions
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__
+#define __DT_BINDINGS_RESET_TI_SYSCON_H__
+
+/*
+ * The reset does not support the feature and corresponding
+ * values are not valid
+ */
+#define ASSERT_NONE (1 << 0)
+#define DEASSERT_NONE (1 << 1)
+#define STATUS_NONE (1 << 2)
+
+/* When set this function is activated by setting(vs clearing) this bit */
+#define ASSERT_SET (1 << 3)
+#define DEASSERT_SET (1 << 4)
+#define STATUS_SET (1 << 5)
+
+/* The following are the inverse of the above and are added for consistency */
+#define ASSERT_CLEAR (0 << 3)
+#define DEASSERT_CLEAR (0 << 4)
+#define STATUS_CLEAR (0 << 5)
+
+#endif
void board_fit_image_post_process(void **p_image, size_t *p_size);
#endif /* CONFIG_SPL_FIT_IMAGE_POST_PROCESS */
+#define FDT_ERROR ((ulong)(-1))
+
+ulong fdt_getprop_u32(const void *fdt, int node, const char *prop);
+int fit_find_config_node(const void *fdt);
+
/**
* Mapping of image types to function handlers to be invoked on the associated
* loaded images
*/
#ifndef USE_HOSTCC
+#include <boot_fit.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
gd->fdt_blob = (ulong *)&_image_binary_end;
else
gd->fdt_blob = (ulong *)&__bss_end;
+
+# elif defined CONFIG_FIT_EMBED
+ gd->fdt_blob = locate_dtb_in_fit(&_end);
+
+ if (gd->fdt_blob == NULL || gd->fdt_blob <= ((void *)&_end)) {
+ puts("Failed to find proper dtb in embedded FIT Image\n");
+ return -1;
+ }
+
# else
/* FDT is at end of image */
gd->fdt_blob = (ulong *)&_end;
projects / oweals / u-boot.git / commitdiff