spl/u-boot-spl-dtb.sfp: spl/u-boot-spl
@:
+spl/boot.bin: spl/u-boot-spl
+ @:
+
tpl/u-boot-tpl.bin: tools prepare
$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
(0-5, cf. cfb_console.c)
VIDEO_FB_ADRS framebuffer address
VIDEO_KBD_INIT_FCT keyboard int fct
- (i.e. i8042_kbd_init())
+ (i.e. rx51_kp_init())
VIDEO_TSTC_FCT test char fct
- (i.e. i8042_tstc)
+ (i.e. rx51_kp_tstc)
VIDEO_GETC_FCT get char fct
- (i.e. i8042_getc)
- CONFIG_CONSOLE_CURSOR cursor drawing on/off
- (requires blink timer
- cf. i8042.c)
- CONFIG_SYS_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c)
- CONFIG_CONSOLE_TIME display time/date info in
- upper right corner
- (requires CONFIG_CMD_DATE)
+ (i.e. rx51_kp_getc)
CONFIG_VIDEO_LOGO display Linux logo in
upper left corner
CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of
a default value of 65536 will be defined.
- Keyboard Support:
- CONFIG_ISA_KEYBOARD
+ See Kconfig help for available keyboard drivers.
- Define this to enable standard (PC-Style) keyboard
- support
-
- CONFIG_I8042_KBD
- Standard PC keyboard driver with US (is default) and
- GERMAN key layout (switch via environment 'keymap=de') support.
- Export function i8042_kbd_init, i8042_tstc and i8042_getc
- for cfb_console. Supports cursor blinking.
+ CONFIG_KEYBOARD
- CONFIG_CROS_EC_KEYB
- Enables a Chrome OS keyboard using the CROS_EC interface.
- This uses CROS_EC to communicate with a second microcontroller
- which provides key scans on request.
+ Define this to enable a custom keyboard support.
+ This simply calls drv_keyboard_init() which must be
+ defined in your board-specific files. This option is deprecated
+ and is only used by novena. For new boards, use driver model
+ instead.
- Video support:
CONFIG_VIDEO
boot. See the documentation file README.video for a
description of this variable.
-
-- Keyboard Support:
- CONFIG_KEYBOARD
-
- Define this to enable a custom keyboard support.
- This simply calls drv_keyboard_init() which must be
- defined in your board-specific files.
- The only board using this so far is RBC823.
-
- LCD Support: CONFIG_LCD
Define this to enable LCD support (for output to LCD
Enables the driver for SPI controller on SuperH. Currently
only SH7757 is supported.
- CONFIG_SPI_X
-
- Enables extended (16-bit) SPI EEPROM addressing.
- (symmetrical to CONFIG_I2C_X)
-
CONFIG_SOFT_SPI
Enables a software (bit-bang) SPI driver rather than
select DM_SERIAL
select DM_SPI
select DM_GPIO
+ select DM_KEYBOARD
config ARCH_S5PC1XX
bool "Samsung S5PC1XX"
set_uart_mux_conf();
setup_clocks_for_console();
uart_soft_reset();
-#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
- /* TODO: This does not work, gd is not available yet */
- gd->baudrate = CONFIG_BAUDRATE;
- serial_init();
- gd->have_console = 1;
-#endif
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
/* Enable RTC32K clock */
rtc32k_enable();
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
+obj-$(CONFIG_MACH_SUN8I_H3) += dram_sun8i_h3.o
obj-y += fel_utils.o
endif
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
clock_set_pll1(408000000);
- writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
-
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+ while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
+ ;
+
+ writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
puts("CPU: Allwinner A23 (SUN8I)\n");
#elif defined CONFIG_MACH_SUN8I_A33
puts("CPU: Allwinner A33 (SUN8I)\n");
+#elif defined CONFIG_MACH_SUN8I_H3
+ puts("CPU: Allwinner H3 (SUN8I)\n");
#elif defined CONFIG_MACH_SUN9I
puts("CPU: Allwinner A80 (SUN9I)\n");
#else
--- /dev/null
+/*
+ * sun8i H3 platform dram controller init
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <linux/kconfig.h>
+
+struct dram_para {
+ u32 read_delays;
+ u32 write_delays;
+ u16 page_size;
+ u8 bus_width;
+ u8 dual_rank;
+ u8 row_bits;
+};
+
+static inline int ns_to_t(int nanoseconds)
+{
+ const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
+
+ return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+
+static u32 bin_to_mgray(int val)
+{
+ static const u8 lookup_table[32] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
+ 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
+ 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
+ 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
+ };
+
+ return lookup_table[clamp(val, 0, 31)];
+}
+
+static int mgray_to_bin(u32 val)
+{
+ static const u8 lookup_table[32] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
+ 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
+ 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
+ 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
+ };
+
+ return lookup_table[val & 0x1f];
+}
+
+static void mctl_phy_init(u32 val)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ writel(val | PIR_INIT, &mctl_ctl->pir);
+ mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
+}
+
+static void mctl_dq_delay(u32 read, u32 write)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ int i, j;
+ u32 val;
+
+ for (i = 0; i < 4; i++) {
+ val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
+ DATX_IOCR_READ_DELAY((read >> (i * 4)) & 0xf);
+
+ for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
+ setbits_le32(&mctl_ctl->datx[i].iocr[j], val);
+ }
+
+ clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
+
+ for (i = 0; i < 4; i++) {
+ val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
+ DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
+
+ setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQS], val);
+ setbits_le32(&mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN], val);
+ }
+
+ setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
+
+ udelay(1);
+}
+
+static void mctl_set_master_priority(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ /* enable bandwidth limit windows and set windows size 1us */
+ writel(0x00010190, &mctl_com->bwcr);
+
+ /* set cpu high priority */
+ writel(0x00000001, &mctl_com->mapr);
+
+ writel(0x0200000d, &mctl_com->mcr[0][0]);
+ writel(0x00800100, &mctl_com->mcr[0][1]);
+ writel(0x06000009, &mctl_com->mcr[1][0]);
+ writel(0x01000400, &mctl_com->mcr[1][1]);
+ writel(0x0200000d, &mctl_com->mcr[2][0]);
+ writel(0x00600100, &mctl_com->mcr[2][1]);
+ writel(0x0100000d, &mctl_com->mcr[3][0]);
+ writel(0x00200080, &mctl_com->mcr[3][1]);
+ writel(0x07000009, &mctl_com->mcr[4][0]);
+ writel(0x01000640, &mctl_com->mcr[4][1]);
+ writel(0x0100000d, &mctl_com->mcr[5][0]);
+ writel(0x00200080, &mctl_com->mcr[5][1]);
+ writel(0x01000009, &mctl_com->mcr[6][0]);
+ writel(0x00400080, &mctl_com->mcr[6][1]);
+ writel(0x0100000d, &mctl_com->mcr[7][0]);
+ writel(0x00400080, &mctl_com->mcr[7][1]);
+ writel(0x0100000d, &mctl_com->mcr[8][0]);
+ writel(0x00400080, &mctl_com->mcr[8][1]);
+ writel(0x04000009, &mctl_com->mcr[9][0]);
+ writel(0x00400100, &mctl_com->mcr[9][1]);
+ writel(0x2000030d, &mctl_com->mcr[10][0]);
+ writel(0x04001800, &mctl_com->mcr[10][1]);
+ writel(0x04000009, &mctl_com->mcr[11][0]);
+ writel(0x00400120, &mctl_com->mcr[11][1]);
+}
+
+static void mctl_set_timing_params(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ u8 tccd = 2;
+ u8 tfaw = ns_to_t(50);
+ u8 trrd = max(ns_to_t(10), 4);
+ u8 trcd = ns_to_t(15);
+ u8 trc = ns_to_t(53);
+ u8 txp = max(ns_to_t(8), 3);
+ u8 twtr = max(ns_to_t(8), 4);
+ u8 trtp = max(ns_to_t(8), 4);
+ u8 twr = max(ns_to_t(15), 3);
+ u8 trp = ns_to_t(15);
+ u8 tras = ns_to_t(38);
+ u16 trefi = ns_to_t(7800) / 32;
+ u16 trfc = ns_to_t(350);
+
+ u8 tmrw = 0;
+ u8 tmrd = 4;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 4;
+ u8 trasmax = 24;
+
+ u8 tcl = 6; /* CL 12 */
+ u8 tcwl = 4; /* CWL 8 */
+ u8 t_rdata_en = 4;
+ u8 wr_latency = 2;
+
+ u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
+ u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
+ u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
+ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
+ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
+
+ /* set mode register */
+ writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
+ writel(0x40, &mctl_ctl->mr[1]);
+ writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
+ writel(0x0, &mctl_ctl->mr[3]);
+
+ /* set DRAM timing */
+ writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
+ DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
+ &mctl_ctl->dramtmg[0]);
+ writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
+ &mctl_ctl->dramtmg[1]);
+ writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
+ DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
+ &mctl_ctl->dramtmg[2]);
+ writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
+ &mctl_ctl->dramtmg[3]);
+ writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
+ DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
+ writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
+ DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
+ &mctl_ctl->dramtmg[5]);
+
+ /* set two rank timing */
+ clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
+ (0x66 << 8) | (0x10 << 0));
+
+ /* set PHY interface timing, write latency and read latency configure */
+ writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
+ (wr_latency << 0), &mctl_ctl->pitmg[0]);
+
+ /* set PHY timing, PTR0-2 use default */
+ writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
+ writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
+
+ /* set refresh timing */
+ writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
+}
+
+static void mctl_zq_calibration(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ int i;
+ u16 zq_val[6];
+ u8 val;
+
+ writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
+
+ for (i = 0; i < 6; i++) {
+ u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
+
+ writel((zq << 20) | (zq << 16) | (zq << 12) |
+ (zq << 8) | (zq << 4) | (zq << 0),
+ &mctl_ctl->zqcr);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
+ writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
+
+ writel(PIR_CLRSR, &mctl_ctl->pir);
+ mctl_phy_init(PIR_ZCAL);
+
+ val = readl(&mctl_ctl->zqdr[0]) >> 24;
+ zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
+ }
+
+ writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
+ writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
+ writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
+}
+
+static void mctl_set_cr(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
+ MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
+ (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
+ MCTL_CR_PAGE_SIZE(para->page_size) |
+ MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
+}
+
+static void mctl_sys_init(struct dram_para *para)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
+ clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
+ udelay(10);
+
+ clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
+ udelay(1000);
+
+ clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
+ clrsetbits_le32(&ccm->dram_clk_cfg,
+ CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK,
+ CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 |
+ CCM_DRAMCLK_CFG_UPD);
+ mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
+
+ setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
+ udelay(10);
+
+ writel(0xc00e, &mctl_ctl->clken);
+ udelay(500);
+}
+
+static int mctl_channel_init(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ unsigned int i;
+
+ mctl_set_cr(para);
+ mctl_set_timing_params(para);
+ mctl_set_master_priority();
+
+ /* setting VTC, default disable all VT */
+ clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
+ clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
+
+ /* increase DFI_PHY_UPD clock */
+ writel(PROTECT_MAGIC, &mctl_com->protect);
+ udelay(100);
+ clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
+ writel(0x0, &mctl_com->protect);
+ udelay(100);
+
+ /* set dramc odt */
+ for (i = 0; i < 4; i++)
+ clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) |
+ (0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
+ (0x3 << 14),
+ IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
+
+ /* AC PDR should always ON */
+ setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
+
+ /* set DQS auto gating PD mode */
+ setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
+
+ /* dx ddr_clk & hdr_clk dynamic mode */
+ clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
+
+ /* dphy & aphy phase select 270 degree */
+ clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
+ (0x1 << 10) | (0x2 << 8));
+
+ /* set half DQ */
+ if (para->bus_width != 32) {
+ writel(0x0, &mctl_ctl->datx[2].gcr);
+ writel(0x0, &mctl_ctl->datx[3].gcr);
+ }
+
+ /* data training configuration */
+ clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
+ (para->dual_rank ? 0x3 : 0x1) << 24);
+
+
+ if (para->read_delays || para->write_delays) {
+ mctl_dq_delay(para->read_delays, para->write_delays);
+ udelay(50);
+ }
+
+ mctl_zq_calibration(para);
+
+ mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST |
+ PIR_DRAMINIT | PIR_QSGATE);
+
+ /* detect ranks and bus width */
+ if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
+ /* only one rank */
+ if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) ||
+ ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) {
+ clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
+ para->dual_rank = 0;
+ }
+
+ /* only half DQ width */
+ if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) ||
+ ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) {
+ writel(0x0, &mctl_ctl->datx[2].gcr);
+ writel(0x0, &mctl_ctl->datx[3].gcr);
+ para->bus_width = 16;
+ }
+
+ mctl_set_cr(para);
+ udelay(20);
+
+ /* re-train */
+ mctl_phy_init(PIR_QSGATE);
+ if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
+ return 1;
+ }
+
+ /* check the dramc status */
+ mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
+
+ /* liuke added for refresh debug */
+ setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
+ udelay(10);
+ clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
+ udelay(10);
+
+ /* set PGCR3, CKE polarity */
+ writel(0x00aa0060, &mctl_ctl->pgcr[3]);
+
+ /* power down zq calibration module for power save */
+ setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
+
+ /* enable master access */
+ writel(0xffffffff, &mctl_com->maer);
+
+ return 0;
+}
+
+static void mctl_auto_detect_dram_size(struct dram_para *para)
+{
+ /* detect row address bits */
+ para->page_size = 512;
+ para->row_bits = 16;
+ mctl_set_cr(para);
+
+ for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
+ if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
+ break;
+
+ /* detect page size */
+ para->page_size = 8192;
+ mctl_set_cr(para);
+
+ for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
+ if (mctl_mem_matches(para->page_size))
+ break;
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ struct dram_para para = {
+ .read_delays = 0x00007979,
+ .write_delays = 0x6aaa0000,
+ .dual_rank = 0,
+ .bus_width = 32,
+ .row_bits = 15,
+ .page_size = 4096,
+ };
+
+ mctl_sys_init(¶);
+ if (mctl_channel_init(¶))
+ return 0;
+
+ if (para.dual_rank)
+ writel(0x00000303, &mctl_ctl->odtmap);
+ else
+ writel(0x00000201, &mctl_ctl->odtmap);
+ udelay(1);
+
+ /* odt delay */
+ writel(0x0c000400, &mctl_ctl->odtcfg);
+
+ /* clear credit value */
+ setbits_le32(&mctl_com->cccr, 1 << 31);
+ udelay(10);
+
+ mctl_auto_detect_dram_size(¶);
+ mctl_set_cr(¶);
+
+ return (1 << (para.row_bits + 3)) * para.page_size *
+ (para.dual_rank ? 2 : 1);
+}
writel(tmp, &rpu_base->rpu1_cfg);
}
+static void write_tcm_boot_trampoline(u32 boot_addr)
+{
+ if (boot_addr) {
+ /*
+ * Boot trampoline is simple ASM code below.
+ *
+ * b over;
+ * label:
+ * .word 0
+ * over: ldr r0, =label
+ * ldr r1, [r0]
+ * bx r1
+ */
+ debug("Write boot trampoline for %x\n", boot_addr);
+ writel(0xea000000, ZYNQMP_TCM_START_ADDRESS);
+ writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4);
+ writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8);
+ writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc);
+ writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10);
+ writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for
+ }
+}
+
int cpu_release(int nr, int argc, char * const argv[])
{
if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
}
u32 boot_addr = simple_strtoul(argv[0], NULL, 16);
+ u32 boot_addr_uniq = 0;
if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR ||
boot_addr == ZYNQMP_R5_HIVEC_ADDR)) {
- printf("Invalid starting address 0x%x\n", boot_addr);
- printf("0 or 0xffff0000 are permitted\n");
- return 1;
+ printf("Using TCM jump trampoline for address 0x%x\n",
+ boot_addr);
+ /* Save boot address for later usage */
+ boot_addr_uniq = boot_addr;
+ /*
+ * R5 needs to start from LOVEC at TCM
+ * OCM will be probably occupied by ATF
+ */
+ boot_addr = ZYNQMP_R5_LOVEC_ADDR;
}
if (!strncmp(argv[1], "lockstep", 8)) {
set_r5_start(boot_addr);
enable_clock_r5();
release_r5_reset(LOCK);
+ write_tcm_boot_trampoline(boot_addr_uniq);
set_r5_halt_mode(RELEASE, LOCK);
} else if (!strncmp(argv[1], "split", 5)) {
printf("R5 split mode\n");
set_r5_halt_mode(HALT, SPLIT);
enable_clock_r5();
release_r5_reset(SPLIT);
+ write_tcm_boot_trampoline(boot_addr_uniq);
set_r5_halt_mode(RELEASE, SPLIT);
} else {
printf("Unsupported mode\n");
sun7i-a20-cubietruck.dtb \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
+ sun7i-a20-lamobo-r1.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-m5.dtb \
sun7i-a20-mk808c.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb
+dtb-$(CONFIG_MACH_SUN8I_H3) += \
+ sun8i-h3-orangepi-pc.dtb \
+ sun8i-h3-orangepi-plus.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ clock-frequency = <24000000>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
+ clock-frequency = <24000000>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
--- /dev/null
+/*
+ * Copyright 2015 Jelle de Jong <jelledejong@powercraft.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Lamobo R1";
+ compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart3;
+ serial2 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_lamobo_r1>;
+
+ green {
+ label = "lamobo_r1:green:usr";
+ gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_power_pin_lamobo_r1>;
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+ };
+};
+
+&ahci_pwr_pin_a {
+ allwinner,pins = "PB3";
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+ operating-points = <
+ /* kHz uV */
+ 960000 1400000
+ 912000 1400000
+ 864000 1350000
+ 720000 1250000
+ 528000 1150000
+ 312000 1100000
+ 144000 1050000
+ >;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ phy-supply = <®_gmac_3v3>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_rx_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc0_cd_pin_lamobo_r1: mmc0_cd_pin@0 {
+ allwinner,pins = "PH10";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ gmac_power_pin_lamobo_r1: gmac_power_pin@0 {
+ allwinner,pins = "PH23";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_lamobo_r1: led_pins@0 {
+ allwinner,pins = "PH24";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+#include "axp209.dtsi"
+
+®_ahci_5v {
+ gpio = <&pio 1 3 0>; /* PB3 */
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb0_vbus {
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_a>,
+ <&spi0_cs0_pins_a>,
+ <&spi0_cs1_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_b>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi PC";
+ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi Plus";
+ compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_usb3_vbus: usb3-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_vbus_pin_a>;
+ regulator-name = "usb3-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&pio {
+ usb3_vbus_pin_a: usb3_vbus_pin@0 {
+ allwinner,pins = "PG11";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+®_usb1_vbus {
+ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PG13";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb3_vbus-supply = <®_usb3_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ /* dummy clock until actually implemented */
+ pll5: pll5_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "pll5";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6", "pll6x2", "pll6d2";
+ };
+
+ pll8: clk@01c20044 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20044 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll8", "pll8x2";
+ };
+
+ cpu: cpu_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb1: ahb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ahb1-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+ clock-output-names = "ahb1";
+ };
+
+ ahb2: ahb2_clk@01c2005c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-h3-ahb2-clk";
+ reg = <0x01c2005c 0x4>;
+ clocks = <&ahb1>, <&pll6 2>;
+ clock-output-names = "ahb2";
+ };
+
+ apb1: apb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ clock-output-names = "apb1";
+ };
+
+ apb2: apb2_clk@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
+ clock-output-names = "apb2";
+ };
+
+ bus_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-h3-bus-gates-clk";
+ reg = <0x01c20060 0x14>;
+ clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
+ clock-names = "ahb1", "ahb2", "apb1", "apb2";
+ clock-indices = <5>, <6>, <8>,
+ <9>, <10>, <13>,
+ <14>, <17>, <18>,
+ <19>, <20>,
+ <21>, <23>,
+ <24>, <25>,
+ <26>, <27>,
+ <28>, <29>,
+ <30>, <31>, <32>,
+ <35>, <36>, <37>,
+ <40>, <41>, <43>,
+ <44>, <52>, <53>,
+ <54>, <64>,
+ <65>, <69>, <72>,
+ <76>, <77>, <78>,
+ <96>, <97>, <98>,
+ <112>, <113>,
+ <114>, <115>, <116>,
+ <128>, <135>;
+ clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0",
+ "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand",
+ "ahb1_sdram", "ahb2_gmac", "ahb1_ts",
+ "ahb1_hstimer", "ahb1_spi0",
+ "ahb1_spi1", "ahb1_otg",
+ "ahb1_otg_ehci0", "ahb1_ehic1",
+ "ahb1_ehic2", "ahb1_ehic3",
+ "ahb1_otg_ohci0", "ahb2_ohic1",
+ "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve",
+ "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint",
+ "ahb1_csi", "ahb1_tve", "ahb1_hdmi",
+ "ahb1_de", "ahb1_gpu", "ahb1_msgbox",
+ "ahb1_spinlock", "apb1_codec",
+ "apb1_spdif", "apb1_pio", "apb1_ths",
+ "apb1_i2s0", "apb1_i2s1", "apb1_i2s2",
+ "apb2_i2c0", "apb2_i2c1", "apb2_i2c2",
+ "apb2_uart0", "apb2_uart1",
+ "apb2_uart2", "apb2_uart3", "apb2_scr",
+ "ahb1_ephy", "ahb1_dbg";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+ };
+
+ usb_clk: clk@01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun8i-h3-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "usb_phy0", "usb_phy1",
+ "usb_phy2", "usb_phy3",
+ "usb_ohci0", "usb_ohci1",
+ "usb_ohci2", "usb_ohci3";
+ };
+
+ mbus_clk: clk@01c2015c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-mbus-clk";
+ reg = <0x01c2015c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5>;
+ clock-output-names = "mbus";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun8i-h3-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 6>;
+ resets = <&bus_rst 6>;
+ #dma-cells = <1>;
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&bus_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&bus_rst 8>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&bus_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&bus_rst 9>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&bus_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&bus_rst 10>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usbphy: phy@01c19400 {
+ compatible = "allwinner,sun8i-h3-usb-phy";
+ reg = <0x01c19400 0x2c>,
+ <0x01c1a800 0x4>,
+ <0x01c1b800 0x4>,
+ <0x01c1c800 0x4>,
+ <0x01c1d800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1",
+ "pmu2",
+ "pmu3";
+ clocks = <&usb_clk 8>,
+ <&usb_clk 9>,
+ <&usb_clk 10>,
+ <&usb_clk 11>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb3_phy";
+ resets = <&usb_clk 0>,
+ <&usb_clk 1>,
+ <&usb_clk 2>,
+ <&usb_clk 3>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset",
+ "usb3_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci1: usb@01c1b000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 25>, <&bus_gates 29>;
+ resets = <&bus_rst 25>, <&bus_rst 29>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@01c1b400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1b400 0x100>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 29>, <&bus_gates 25>,
+ <&usb_clk 17>;
+ resets = <&bus_rst 29>, <&bus_rst 25>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci2: usb@01c1c000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 26>, <&bus_gates 30>;
+ resets = <&bus_rst 26>, <&bus_rst 30>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@01c1c400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 30>, <&bus_gates 26>,
+ <&usb_clk 18>;
+ resets = <&bus_rst 30>, <&bus_rst 26>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci3: usb@01c1d000 {
+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
+ reg = <0x01c1d000 0x100>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 27>, <&bus_gates 31>;
+ resets = <&bus_rst 27>, <&bus_rst 31>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci3: usb@01c1d400 {
+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
+ reg = <0x01c1d400 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 31>, <&bus_gates 27>,
+ <&usb_clk 19>;
+ resets = <&bus_rst 31>, <&bus_rst 27>;
+ phys = <&usbphy 3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun8i-h3-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bus_gates 69>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PA4", "PA5";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin: mmc0_cd_pin@0 {
+ allwinner,pins = "PF6";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc1_pins_a: mmc1@0 {
+ allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ bus_rst: reset@01c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun8i-h3-bus-reset";
+ reg = <0x01c202c0 0x1c>;
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ wdt0: watchdog@01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 112>;
+ resets = <&bus_rst 144>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 113>;
+ resets = <&bus_rst 145>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 114>;
+ resets = <&bus_rst 146>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&bus_gates 115>;
+ resets = <&bus_rst 147>;
+ dmas = <&dma 9>, <&dma 9>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ rtc: rtc@01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
#define NUM_CRYSTAL_FREQ 0x4
+/* EDMA3 Base Address */
+#define EDMA3_BASE 0x49000000
+
#endif /* __AM43XX_HARDWARE_AM43XX_H */
#endif
#if defined(CONFIG_SYS_NS16550_SERIAL)
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
#define CCM_PLL6_CTRL_K_SHIFT 4
#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_LOCK (1 << 28)
#define CCM_MIPI_PLL_CTRL_M_SHIFT 0
#define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)
#define CCM_PLL11_CTRL_UPD (0x1 << 30)
#define CCM_PLL11_CTRL_EN (0x1 << 31)
-#define AHB1_ABP1_DIV_DEFAULT 0x00002020
+#if defined CONFIG_MACH_SUN8I_H3
+#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
+#else
+#define AHB1_ABP1_DIV_DEFAULT 0x00002020 /* AHB1=AXI/4, APB1=AHB1/2 */
+#endif
#define AXI_GATE_OFFSET_DRAM 0
#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0)
#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
+#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20)
+#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20)
+#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20)
#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
#include <asm/arch/dram_sun8i_a23.h>
#elif defined(CONFIG_MACH_SUN8I_A33)
#include <asm/arch/dram_sun8i_a33.h>
+#elif defined(CONFIG_MACH_SUN8I_H3)
+#include <asm/arch/dram_sun8i_h3.h>
#else
#include <asm/arch/dram_sun4i.h>
#endif
--- /dev/null
+/*
+ * sun8i H3 platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_H3_H
+#define _SUNXI_DRAM_SUN8I_H3_H
+
+struct sunxi_mctl_com_reg {
+ u32 cr; /* 0x00 control register */
+ u8 res0[0xc]; /* 0x04 */
+ u32 mcr[16][2]; /* 0x10 */
+ u32 bwcr; /* 0x90 bandwidth control register */
+ u32 maer; /* 0x94 master enable register */
+ u32 mapr; /* 0x98 master priority register */
+ u32 mcgcr; /* 0x9c */
+ u32 cpu_bwcr; /* 0xa0 */
+ u32 gpu_bwcr; /* 0xa4 */
+ u32 ve_bwcr; /* 0xa8 */
+ u32 disp_bwcr; /* 0xac */
+ u32 other_bwcr; /* 0xb0 */
+ u32 total_bwcr; /* 0xb4 */
+ u8 res1[0x8]; /* 0xb8 */
+ u32 swonr; /* 0xc0 */
+ u32 swoffr; /* 0xc4 */
+ u8 res2[0x8]; /* 0xc8 */
+ u32 cccr; /* 0xd0 */
+ u8 res3[0x72c]; /* 0xd4 */
+ u32 protect; /* 0x800 */
+};
+
+#define MCTL_CR_BL8 (0x4 << 20)
+
+#define MCTL_CR_1T (0x1 << 19)
+#define MCTL_CR_2T (0x0 << 19)
+
+#define MCTL_CR_LPDDR3 (0x7 << 16)
+#define MCTL_CR_LPDDR2 (0x6 << 16)
+#define MCTL_CR_DDR3 (0x3 << 16)
+#define MCTL_CR_DDR2 (0x2 << 16)
+
+#define MCTL_CR_SEQUENTIAL (0x1 << 15)
+#define MCTL_CR_INTERLEAVED (0x0 << 15)
+
+#define MCTL_CR_32BIT (0x1 << 12)
+#define MCTL_CR_16BIT (0x0 << 12)
+#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT)
+
+#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
+#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4)
+#define MCTL_CR_EIGHT_BANKS (0x1 << 2)
+#define MCTL_CR_FOUR_BANKS (0x0 << 2)
+#define MCTL_CR_DUAL_RANK (0x1 << 0)
+#define MCTL_CR_SINGLE_RANK (0x0 << 0)
+
+#define PROTECT_MAGIC (0x94be6fa3)
+
+struct sunxi_mctl_ctl_reg {
+ u32 pir; /* 0x00 PHY initialization register */
+ u32 pwrctl; /* 0x04 */
+ u32 mrctrl; /* 0x08 */
+ u32 clken; /* 0x0c */
+ u32 pgsr[2]; /* 0x10 PHY general status registers */
+ u32 statr; /* 0x18 */
+ u8 res1[0x14]; /* 0x1c */
+ u32 mr[4]; /* 0x30 mode registers */
+ u32 pllgcr; /* 0x40 */
+ u32 ptr[5]; /* 0x44 PHY timing registers */
+ u32 dramtmg[9]; /* 0x58 DRAM timing registers */
+ u32 odtcfg; /* 0x7c */
+ u32 pitmg[2]; /* 0x80 PHY interface timing registers */
+ u8 res2[0x4]; /* 0x88 */
+ u32 rfshctl0; /* 0x8c */
+ u32 rfshtmg; /* 0x90 refresh timing */
+ u32 rfshctl1; /* 0x94 */
+ u32 pwrtmg; /* 0x98 */
+ u8 res3[0x20]; /* 0x9c */
+ u32 dqsgmr; /* 0xbc */
+ u32 dtcr; /* 0xc0 */
+ u32 dtar[4]; /* 0xc4 */
+ u32 dtdr[2]; /* 0xd4 */
+ u32 dtmr[2]; /* 0xdc */
+ u32 dtbmr; /* 0xe4 */
+ u32 catr[2]; /* 0xe8 */
+ u32 dtedr[2]; /* 0xf0 */
+ u8 res4[0x8]; /* 0xf8 */
+ u32 pgcr[4]; /* 0x100 PHY general configuration registers */
+ u32 iovcr[2]; /* 0x110 */
+ u32 dqsdr; /* 0x118 */
+ u32 dxccr; /* 0x11c */
+ u32 odtmap; /* 0x120 */
+ u32 zqctl[2]; /* 0x124 */
+ u8 res6[0x14]; /* 0x12c */
+ u32 zqcr; /* 0x140 ZQ control register */
+ u32 zqsr; /* 0x144 ZQ status register */
+ u32 zqdr[3]; /* 0x148 ZQ data registers */
+ u8 res7[0x6c]; /* 0x154 */
+ u32 sched; /* 0x1c0 */
+ u32 perfhpr[2]; /* 0x1c4 */
+ u32 perflpr[2]; /* 0x1cc */
+ u32 perfwr[2]; /* 0x1d4 */
+ u8 res8[0x2c]; /* 0x1dc */
+ u32 aciocr; /* 0x208 */
+ u8 res9[0xf4]; /* 0x20c */
+ struct { /* 0x300 DATX8 modules*/
+ u32 mdlr; /* 0x00 */
+ u32 lcdlr[3]; /* 0x04 */
+ u32 iocr[11]; /* 0x10 IO configuration register */
+ u32 bdlr6; /* 0x3c */
+ u32 gtr; /* 0x40 */
+ u32 gcr; /* 0x44 */
+ u32 gsr[3]; /* 0x48 */
+ u8 res0[0x2c]; /* 0x54 */
+ } datx[4];
+ u8 res10[0x388]; /* 0x500 */
+ u32 upd2; /* 0x888 */
+};
+
+#define PTR3_TDINIT1(x) ((x) << 20)
+#define PTR3_TDINIT0(x) ((x) << 0)
+
+#define PTR4_TDINIT3(x) ((x) << 20)
+#define PTR4_TDINIT2(x) ((x) << 0)
+
+#define DRAMTMG0_TWTP(x) ((x) << 24)
+#define DRAMTMG0_TFAW(x) ((x) << 16)
+#define DRAMTMG0_TRAS_MAX(x) ((x) << 8)
+#define DRAMTMG0_TRAS(x) ((x) << 0)
+
+#define DRAMTMG1_TXP(x) ((x) << 16)
+#define DRAMTMG1_TRTP(x) ((x) << 8)
+#define DRAMTMG1_TRC(x) ((x) << 0)
+
+#define DRAMTMG2_TCWL(x) ((x) << 24)
+#define DRAMTMG2_TCL(x) ((x) << 16)
+#define DRAMTMG2_TRD2WR(x) ((x) << 8)
+#define DRAMTMG2_TWR2RD(x) ((x) << 0)
+
+#define DRAMTMG3_TMRW(x) ((x) << 16)
+#define DRAMTMG3_TMRD(x) ((x) << 12)
+#define DRAMTMG3_TMOD(x) ((x) << 0)
+
+#define DRAMTMG4_TRCD(x) ((x) << 24)
+#define DRAMTMG4_TCCD(x) ((x) << 16)
+#define DRAMTMG4_TRRD(x) ((x) << 8)
+#define DRAMTMG4_TRP(x) ((x) << 0)
+
+#define DRAMTMG5_TCKSRX(x) ((x) << 24)
+#define DRAMTMG5_TCKSRE(x) ((x) << 16)
+#define DRAMTMG5_TCKESR(x) ((x) << 8)
+#define DRAMTMG5_TCKE(x) ((x) << 0)
+
+#define RFSHTMG_TREFI(x) ((x) << 16)
+#define RFSHTMG_TRFC(x) ((x) << 0)
+
+#define PIR_CLRSR (0x1 << 27) /* clear status registers */
+#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */
+#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */
+#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */
+#define PIR_PHYRST (0x1 << 6) /* PHY reset */
+#define PIR_DCAL (0x1 << 5) /* DDL calibration */
+#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */
+#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */
+#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */
+
+#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */
+
+#define ZQCR_PWRDOWN (0x1 << 31) /* ZQ power down */
+
+#define DATX_IOCR_DQ(x) (x) /* DQ0-7 IOCR index */
+#define DATX_IOCR_DM (8) /* DM IOCR index */
+#define DATX_IOCR_DQS (9) /* DQS IOCR index */
+#define DATX_IOCR_DQSN (10) /* DQSN IOCR index */
+
+#define DATX_IOCR_WRITE_DELAY(x) ((x) << 8)
+#define DATX_IOCR_READ_DELAY(x) ((x) << 0)
+
+#endif /* _SUNXI_DRAM_SUN8I_H3_H */
#define SUN7I_GPA_GMAC 5
#define SUN6I_GPA_SDC2 5
#define SUN6I_GPA_SDC3 4
+#define SUN8I_H3_GPA_UART0 2
#define SUN4I_GPB_TWI0 2
#define SUN4I_GPB_TWI1 2
config TARGET_NAS220
bool "BlackArmor NAS220"
+config TARGET_NSA310S
+ bool "Zyxel NSA310S"
+
endchoice
config SYS_SOC
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
source "board/Seagate/nas220/Kconfig"
+source "board/zyxel/nsa310s/Kconfig"
endif
#define CONFIG_PHYLIB
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
+#define CONFIG_ARP_TIMEOUT 200
+#define CONFIG_NET_RETRY_COUNT 50
#endif /* CONFIG_CMD_NET */
/*
config DM_GPIO
default y
-config ROCKCHIP_SERIAL
- default y
-
source "arch/arm/mach-rockchip/rk3288/Kconfig"
endif
select DM_I2C
select DM_SPI
select DM_GPIO
+ select DM_KEYBOARD
choice
prompt "Tegra SoC select"
*/
#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
setup_uarts(uart_ids);
}
+#if CONFIG_IS_ENABLED(DM_SERIAL) && !CONFIG_IS_ENABLED(OF_CONTROL)
+static struct ns16550_platdata ns16550_com1_pdata = {
+ .base = CONFIG_SYS_NS16550_COM1,
+ .reg_shift = 2,
+ .clock = CONFIG_SYS_NS16550_CLK,
+};
+
+U_BOOT_DEVICE(ns16550_com1) = {
+ "ns16550_serial", &ns16550_com1_pdata
+};
+#endif
+
#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
#include <config.h>
#include <common.h>
#include <command.h>
+#include <console.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/mpu.h>
#include <asm-generic/bitops/__ffs.h>
#ifdef __KERNEL__
-/*
- * Function prototypes to keep gcc -Wall happy
- */
-
/*
* The __ functions are not atomic
*/
-extern void set_bit(int nr, volatile void * addr);
-extern void __set_bit(int nr, volatile void * addr);
-
-extern void clear_bit(int nr, volatile void * addr);
-#define __clear_bit(nr, addr) clear_bit(nr, addr)
-#define PLATFORM__CLEAR_BIT
-
-extern void change_bit(int nr, volatile void * addr);
-extern void __change_bit(int nr, volatile void * addr);
-extern int test_and_set_bit(int nr, volatile void * addr);
-extern int __test_and_set_bit(int nr, volatile void * addr);
-extern int test_and_clear_bit(int nr, volatile void * addr);
-extern int __test_and_clear_bit(int nr, volatile void * addr);
-extern int test_and_change_bit(int nr, volatile void * addr);
-extern int __test_and_change_bit(int nr, volatile void * addr);
-extern int __constant_test_bit(int nr, const volatile void * addr);
-extern int __test_bit(int nr, volatile void * addr);
-extern int find_first_zero_bit(void * addr, unsigned size);
-extern int find_next_zero_bit (void * addr, int size, int offset);
-
/*
* ffz = Find First Zero in word. Undefined if no zero exists,
* so code should check against ~0UL first..
*/
-extern __inline__ unsigned long ffz(unsigned long word)
+static inline unsigned long ffz(unsigned long word)
{
unsigned long result = 0;
}
-extern __inline__ void set_bit(int nr, volatile void * addr)
+static inline void set_bit(int nr, volatile void *addr)
{
int * a = (int *) addr;
int mask;
restore_flags(flags);
}
-extern __inline__ void __set_bit(int nr, volatile void * addr)
+static inline void __set_bit(int nr, volatile void *addr)
{
int * a = (int *) addr;
int mask;
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
-extern __inline__ void clear_bit(int nr, volatile void * addr)
+static inline void clear_bit(int nr, volatile void *addr)
{
int * a = (int *) addr;
int mask;
restore_flags(flags);
}
-extern __inline__ void change_bit(int nr, volatile void * addr)
+#define __clear_bit(nr, addr) clear_bit(nr, addr)
+#define PLATFORM__CLEAR_BIT
+
+static inline void change_bit(int nr, volatile void *addr)
{
int mask;
unsigned long flags;
restore_flags(flags);
}
-extern __inline__ void __change_bit(int nr, volatile void * addr)
+static inline void __change_bit(int nr, volatile void *addr)
{
int mask;
unsigned long *ADDR = (unsigned long *) addr;
*ADDR ^= mask;
}
-extern __inline__ int test_and_set_bit(int nr, volatile void * addr)
+static inline int test_and_set_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
return retval;
}
-extern __inline__ int __test_and_set_bit(int nr, volatile void * addr)
+static inline int __test_and_set_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
return retval;
}
-extern __inline__ int test_and_clear_bit(int nr, volatile void * addr)
+static inline int test_and_clear_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
return retval;
}
-extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
return retval;
}
-extern __inline__ int test_and_change_bit(int nr, volatile void * addr)
+static inline int test_and_change_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
return retval;
}
-extern __inline__ int __test_and_change_bit(int nr, volatile void * addr)
+static inline int __test_and_change_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
/*
* This routine doesn't need to be atomic.
*/
-extern __inline__ int __constant_test_bit(int nr, const volatile void * addr)
+static inline int __constant_test_bit(int nr, const volatile void *addr)
{
return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
}
-extern __inline__ int __test_bit(int nr, volatile void * addr)
+static inline int __test_bit(int nr, volatile void *addr)
{
int * a = (int *) addr;
int mask;
#define find_first_zero_bit(addr, size) \
find_next_zero_bit((addr), (size), 0)
-extern __inline__ int find_next_zero_bit (void * addr, int size, int offset)
+static inline int find_next_zero_bit(void *addr, int size, int offset)
{
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
#define hweight8(x) generic_hweight8(x)
-extern __inline__ int ext2_set_bit(int nr, volatile void * addr)
+static inline int ext2_set_bit(int nr, volatile void *addr)
{
int mask, retval;
unsigned long flags;
return retval;
}
-extern __inline__ int ext2_clear_bit(int nr, volatile void * addr)
+static inline int ext2_clear_bit(int nr, volatile void *addr)
{
int mask, retval;
unsigned long flags;
return retval;
}
-extern __inline__ int ext2_test_bit(int nr, const volatile void * addr)
+static inline int ext2_test_bit(int nr, const volatile void *addr)
{
int mask;
const volatile unsigned char *ADDR = (const unsigned char *) addr;
((__typeof__ (*(ptr)))__xchg ((unsigned long)(with), (ptr), sizeof (*(ptr))))
#define tas(ptr) (xchg ((ptr), 1))
-extern inline unsigned long __xchg (unsigned long with,
+static inline unsigned long __xchg(unsigned long with,
__volatile__ void *ptr, int size)
{
unsigned long tmp, flags;
chosen {
bootargs = "debug console=ttyS0,115200";
- stdout-path = &uart_0;
+ stdout-path = &a_16550_uart_0;
};
};
*/
#include <common.h>
+#include <console.h>
#include <malloc.h>
#include <asm/cpm_8260.h>
#include <mpc8260.h>
*/
#include <common.h>
+#include <console.h>
#if defined(CONFIG_HARD_I2C)
*/
#include <common.h>
+#include <console.h>
#ifdef CONFIG_HARD_I2C
/* All PPC boards must swap IDE bytes */
#define CONFIG_IDE_SWAP_IO
+#if defined(CONFIG_DM_SERIAL)
+/*
+ * TODO: Convert this to a clock driver exists that can give us the UART
+ * clock here.
+ */
+#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#endif
+
#endif /* _ASM_CONFIG_H_ */
used on some devices to allow the CPU to communicate with its
peripherals.
+config DM_KEYBOARD
+ default y
+
endmenu
/* delay x useconds */
void __udelay(unsigned long usec)
{
- os_usleep(usec);
+ struct sandbox_state *state = state_get_current();
+
+ if (!state->skip_delays)
+ os_usleep(usec);
}
int cleanup_before_linux(void)
SANDBOX_CMDLINE_OPT_SHORT(terminal, 't', 1,
"Set terminal to raw/cooked mode");
+static int sandbox_cmdline_cb_verbose(struct sandbox_state *state,
+ const char *arg)
+{
+ state->show_test_output = true;
+ return 0;
+}
+SANDBOX_CMDLINE_OPT_SHORT(verbose, 'v', 0, "Show test output");
+
int main(int argc, char *argv[])
{
struct sandbox_state *state;
return state;
}
+void state_set_skip_delays(bool skip_delays)
+{
+ struct sandbox_state *state = state_get_current();
+
+ state->skip_delays = skip_delays;
+}
+
+bool state_get_skip_delays(void)
+{
+ struct sandbox_state *state = state_get_current();
+
+ return state->skip_delays;
+}
+
int state_init(void)
{
state = &main_state;
sides = <4>;
};
+ timer {
+ compatible = "sandbox,timer";
+ };
+
tpm {
compatible = "google,sandbox-tpm";
};
compatible = "sandbox,usb-hub";
#address-cells = <1>;
#size-cells = <0>;
- flash-stick {
+ flash-stick@0 {
reg = <0>;
compatible = "sandbox,usb-flash";
sandbox,filepath = "testflash.bin";
};
+ flash-stick@1 {
+ reg = <1>;
+ compatible = "sandbox,usb-flash";
+ sandbox,filepath = "testflash1.bin";
+ };
+
+ flash-stick@2 {
+ reg = <2>;
+ compatible = "sandbox,usb-flash";
+ sandbox,filepath = "testflash2.bin";
+ };
+
+ keyb@3 {
+ reg = <3>;
+ compatible = "sandbox,usb-keyb";
+ };
+
};
};
};
enum reset_t last_reset; /* Last reset type */
bool reset_allowed[RESET_COUNT]; /* Allowed reset types */
enum state_terminal_raw term_raw; /* Terminal raw/cooked */
+ bool skip_delays; /* Ignore any time delays (for test) */
+ bool show_test_output; /* Don't suppress stdout in tests */
/* Pointer to information for each SPI bus/cs */
struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
*/
int state_setprop(int node, const char *prop_name, const void *data, int size);
+/**
+ * Control skipping of time delays
+ *
+ * Some tests have unnecessay time delays (e.g. USB). Allow these to be
+ * skipped to speed up testing
+ *
+ * @param skip_delays true to skip delays from now on, false to honour delay
+ * requests
+ */
+void state_set_skip_delays(bool skip_delays);
+
+/**
+ * See if delays should be skipped
+ *
+ * @return true if delays should be skipped, false if they should be honoured
+ */
+bool state_get_skip_delays(void);
+
/**
* Initialize the test system state
*/
*/
long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time);
+int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str);
+
#endif
#include <common.h>
#include <command.h>
+#include <console.h>
#include <malloc.h>
#include <stdio_dev.h>
#include <version.h>
#include <common.h>
#include <command.h>
+#include <console.h>
#include <malloc.h>
#include <stdio_dev.h>
#include <config.h>
Intel 8254 timer contains three counters which have fixed uses.
Include this to have U-Boot set up the timer correctly.
+config I8042_KEYB
+ default y
+
+config DM_KEYBOARD
+ default y
+
source "arch/x86/lib/efi/Kconfig"
endmenu
#include <dt-bindings/interrupt-router/intel-irq.h>
/include/ "skeleton.dtsi"
+/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/dts-v1/;
/include/ "skeleton.dtsi"
+/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
stdout-path = "/serial";
};
+ keyboard {
+ intel,duplicate-por;
+ };
+
spd {
compatible = "memory-spd";
#address-cells = <1>;
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
+/include/ "keyboard.dtsi"
/include/ "rtc.dtsi"
/ {
--- /dev/null
+/ {
+ keyboard {
+ compatible = "intel,i8042-keyboard";
+ };
+};
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
+/include/ "keyboard.dtsi"
/include/ "rtc.dtsi"
/ {
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
+/include/ "keyboard.dtsi"
/include/ "rtc.dtsi"
/ {
/ {
serial: serial {
- compatible = "x86-uart";
+ compatible = "ns16550";
reg = <0x3f8 8>;
reg-shift = <0>;
clock-frequency = <1843200>;
*/
#include <common.h>
+#include <console.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
#include <common.h>
#include <cli.h>
#include <command.h>
+#include <console.h>
#include "yucca.h"
#include <i2c.h>
#include <asm/byteorder.h>
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := vexpress64.o pcie.o
+obj-y := vexpress64.o
+obj-$(CONFIG_TARGET_VEXPRESS64_JUNO) += pcie.o
writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
- printf("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
+ debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,
((u64)1) << window_size, trsl_param);
}
void vexpress64_pcie_init(void)
{
-#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
xr3pci_init();
-#endif
}
.platdata = &serial_platdata,
};
+/* This function gets replaced by platforms supporting PCIe.
+ * The replacement function, eg. on Juno, initialises the PCIe bus.
+ */
+__weak void vexpress64_pcie_init(void)
+{
+}
+
int board_init(void)
{
vexpress64_pcie_init();
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#ifdef PHYS_SDRAM_2
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
}
/*
/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
#include <common.h>
+#include <console.h>
#include <watchdog.h>
#include <altera.h>
#include <ACEX1K.h>
*/
#include <common.h>
+#include <console.h>
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
#define FLASH_BANK_SIZE 0x200000
int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom)
{
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
unsigned int bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE);
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
-#endif
if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) {
warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC,
int ret;
unsigned char *p;
int i;
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- unsigned int bus;
-#endif
memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE);
print_buffer(0, &eeprom, 1, sizeof(eeprom), 16);
#endif
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
-#endif
+ eeprom_init(CONFIG_SYS_EEPROM_BUS_NUM);
- /* do page write to the eeprom */
- for (i = 0, p = (unsigned char *)&eeprom;
- i < sizeof(eeprom);
- i += 32, p += 32) {
- ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
- p, min(sizeof(eeprom) - i, 32));
- if (ret)
- break;
- udelay(5000); /* 5ms write cycle timing */
- }
+ ret = eeprom_write(devaddr, 0, (unsigned char *)&eeprom,
+ TRICORDER_EEPROM_SIZE);
+ if (ret)
+ printf("Tricorder: Could not write EEPROM content!\n");
- ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify,
+ ret = eeprom_read(devaddr, 0, (unsigned char *)&eeprom_verify,
TRICORDER_EEPROM_SIZE);
+ if (ret)
+ printf("Tricorder: Could not read EEPROM content!\n");
if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) {
printf("Tricorder: Could not verify EEPROM content!\n");
ret = 1;
}
-#ifdef CONFIG_SYS_EEPROM_BUS_NUM
- i2c_set_bus_num(bus);
-#endif
return ret;
}
{
if (argc == 3) {
ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
- eeprom_init();
+
if (strcmp(argv[1], "read") == 0) {
int rcode;
char *version = argv[4];
char *serial = argv[5];
char *interface = NULL;
- eeprom_init();
if (argc == 7)
interface = argv[6];
#include <common.h>
#include <command.h>
+#include <console.h>
#if !defined(CONFIG_440)
#include <asm/4xx_pci.h>
#endif
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <console.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
*/
#include <common.h>
+#include <console.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
*/
#include <common.h>
#include <command.h>
+#include <console.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/processor.h>
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <console.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/ppc440.h>
*/
#include <common.h>
+#include <console.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
*/
#include <common.h>
+#include <console.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
*/
#include <common.h>
+#include <console.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
*/
#include <common.h>
+#include <console.h>
#include <hwconfig.h>
#include <pci.h>
#include <asm/processor.h>
*/
#include <common.h>
+#include <console.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
*/
#include <common.h>
+#include <console.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
*/
#include <common.h>
+#include <console.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
*/
#include <common.h>
+#include <console.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
*/
#include <common.h>
+#include <console.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
*/
#include <common.h>
+#include <console.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
*/
#include <common.h>
+#include <console.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
*/
#include <common.h>
+#include <console.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
*/
#include <common.h>
+#include <console.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
*/
#include <common.h>
+#include <console.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
#include <common.h>
#include <command.h>
+#include <console.h>
#include <gdsys_fpga.h>
#include <asm/io.h>
#include <common.h>
#include <config.h>
+#include <console.h>
#include <mpc5xxx.h>
#include <pci.h>
};
U_BOOT_DEVICE(igep_uart) = {
- "serial_omap",
+ "ns16550_serial",
&igep_serial
};
debug("%s: Cannot set up input\n", __func__);
return -1;
}
+ input_add_tables(&button_input, false);
button_input.read_keys = novena_gpio_button_read_keys;
error = input_stdio_register(&dev);
};
U_BOOT_DEVICE(sniper_serial) = {
- .name = "serial_omap",
+ .name = "ns16550_serial",
.platdata = &serial_omap_platdata
};
};
U_BOOT_DEVICE(omap3logic_uart) = {
- "serial_omap",
+ "ns16550_serial",
&omap3logic_serial
};
};
U_BOOT_DEVICE(zoom1_uart) = {
- "serial_omap",
+ "ns16550_serial",
&zoom1_serial
};
#include <common.h>
#include <i2c.h>
#include <command.h>
+#include <console.h>
#include <post.h>
#include <serial.h>
#include <malloc.h>
* linux/drivers/char/pc_keyb.c
*/
#include <common.h>
+#include <console.h>
#include <asm/processor.h>
#include <stdio_dev.h>
#include "isa.h"
**********************************************************************************/
#include <common.h>
+#include <console.h>
#include <mpc5xx.h>
#include <stdio_dev.h>
#include <pci_ids.h>
----
CONFIG_RTC_MC146818 MC146818 RTC support
-Keyboard:
----------
-CONFIG_ISA_KEYBOARD Standard (PC-Style) Keyboard support
-
Video:
------
CONFIG_VIDEO_CT69000 Enable Chips & Technologies 69000 Video chip
};
U_BOOT_DEVICE(overo_uart) = {
- "serial_omap",
+ "ns16550_serial",
&overo_serial
};
};
U_BOOT_DEVICE(cairo_uart) = {
- "serial_omap",
+ "ns16550_serial",
&cairo_serial
};
*/
#include <common.h>
+#include <console.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/pci.h>
{
}
+#ifndef CONFIG_TIMER
/* system timer offset in ms */
static unsigned long sandbox_timer_offset;
{
return os_get_nsec() / 1000 + sandbox_timer_offset * 1000;
}
+#endif
int dram_init(void)
{
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+config MACH_SUN8I_H3
+ bool "sun8i (Allwinner H3)"
+ select CPU_V7
+ select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
- default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
+ default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3
config DRAM_CLK
F: include/configs/sun8i.h
F: configs/ga10h_v1_1_defconfig
F: configs/gt90h_v4_defconfig
+F: configs/orangepi_pc_defconfig
+F: configs/orangepi_plus_defconfig
F: configs/q8_a23_tablet_800x480_defconfig
F: configs/q8_a33_tablet_800x480_defconfig
F: configs/q8_a33_tablet_1024x600_defconfig
S: Maintained
F: configs/iNet_86VS_defconfig
+LAMOBO-R1 BOARD
+M: Jelle de Jong <jelledejong@powercraft.nl>
+S: Maintained
+F: configs/Lamobo_R1_defconfig
+
LINKSPRITE-PCDUINO BOARD
M: Zoltan Herpai <wigyori@uid0.hu>
S: Maintained
{UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
{I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
{I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
- {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */
- {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */
- {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */
- {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */
+ {WAKEUP0, (M0 | PULL_UP)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP1, (M0)}, /* Wakeup1.Wakeup1 */
+ {WAKEUP2, (M0)}, /* Wakeup2.Wakeup2 */
+ {WAKEUP3, (M0 | PULL_UP)}, /* Wakeup3.Wakeup3 */
{ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
{RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
{RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */
};
U_BOOT_DEVICE(beagle_uart) = {
- "serial_omap",
+ "ns16550_serial",
&beagle_serial
};
{I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */
{I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */
{WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
- {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */
+ {WAKEUP2, (M14)}, /* Wakeup2.gpio1_2 */
};
#ifdef CONFIG_IODELAY_RECALIBRATION
};
U_BOOT_DEVICE(devkit8000_uart) = {
- "serial_omap",
+ "ns16550_serial",
&devkit8000_serial
};
#include <common.h>
#include <command.h>
+#include <console.h>
#if defined(CONFIG_CMD_BSP)
*/
#include <common.h>
+#include <console.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
*/
#include <common.h>
+#include <console.h>
#include <asm/processor.h>
#include <spd_sdram.h>
#include <i2c.h>
--- /dev/null
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+if TARGET_NSA310S
+
+config SYS_BOARD
+ default "nsa310s"
+
+config SYS_VENDOR
+ default "zyxel"
+
+config SYS_CONFIG_NAME
+ default "nsa310s"
+
+endif
--- /dev/null
+NSA310S BOARD
+M: Gerald Kerma <dreagle@doukki.net>
+M: Tony Dinh <mibodhi@gmail.com>
+M: Luka Perkov <luka.perkov@sartura.hr>
+S: Maintained
+F: board/zyxel/nsa310s/
+F: include/configs/nsa310s.h
+F: configs/nsa310s_defconfig
--- /dev/null
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nsa310s.o
--- /dev/null
+#
+# Copyright (C) 2015
+# Gerald Kerma <dreagle@doukki.net>
+# Tony Dinh <mibodhi@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer to doc/README.kwbimage for more details about how-to
+# configure and create kirkwood boot images.
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+DATA 0xFFD01400 0x43010c30
+DATA 0xFFD01404 0x39543000
+DATA 0xFFD01408 0x22125451
+DATA 0xFFD0140C 0x00000833
+DATA 0xFFD01410 0x0000000C
+DATA 0xFFD01414 0x00000000
+DATA 0xFFD01418 0x00000000
+DATA 0xFFD0141C 0x00000652
+DATA 0xFFD01420 0x00000004
+DATA 0xFFD01424 0x0000F17F
+DATA 0xFFD01428 0x00085520
+DATA 0xFFD0147c 0x00008552
+DATA 0xFFD01504 0x0FFFFFF1
+DATA 0xFFD01508 0x10000000
+DATA 0xFFD0150C 0x00000000
+DATA 0xFFD01514 0x00000000
+DATA 0xFFD0151C 0x00000000
+DATA 0xFFD01494 0x00010000
+DATA 0xFFD01498 0x00000000
+DATA 0xFFD0149C 0x0000E403
+DATA 0xFFD01480 0x00000001
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0x0 0x0
--- /dev/null
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/io.h>
+#include "nsa310s.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
+ NSA310S_OE_LOW, NSA310S_OE_HIGH);
+
+ /* (all LEDs & power off active high) */
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_GPIO,
+ MPP14_GPIO,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+ u16 reg;
+ u16 phyaddr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* read PHY dev address */
+ if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
+ printf("could not read PHY dev address\n");
+ return;
+ }
+
+ /* set RGMII delay */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
+ miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®);
+ reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
+ miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
+
+ /* reset PHY */
+ if (miiphy_reset(name, phyaddr))
+ return;
+
+ /*
+ * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
+ * and has an MCU attached to the LED[2] via tristate interrupt
+ */
+
+ /* switch to LED register page */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
+ /* read out LED polarity register */
+ miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, ®);
+ /* clear 4, set 5 - LED2 low, tri-state */
+ reg &= ~(MV88E1318_LED2_4);
+ reg |= (MV88E1318_LED2_5);
+ /* write back LED polarity register */
+ miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
+ /* jump back to page 0, per the PHY chip documenation. */
+ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
+
+ /* set PHY back to auto-negotiation mode */
+ miiphy_write(name, phyaddr, 0x4, 0x1e1);
+ miiphy_write(name, phyaddr, 0x9, 0x300);
+ /* downshift */
+ miiphy_write(name, phyaddr, 0x10, 0x3860);
+ miiphy_write(name, phyaddr, 0x0, 0x9140);
+}
+#endif /* CONFIG_RESET_PHY_R */
--- /dev/null
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __NSA310S_H
+#define __NSA310S_H
+
+/* low GPIO's */
+#define HDD1_GREEN_LED (1 << 16)
+#define HDD1_RED_LED (1 << 13)
+#define USB_GREEN_LED (1 << 15)
+#define USB_POWER (1 << 21)
+#define SYS_GREEN_LED (1 << 28)
+#define SYS_ORANGE_LED (1 << 29)
+
+#define COPY_GREEN_LED (1 << 22)
+#define COPY_RED_LED (1 << 23)
+
+#define PIN_USB_GREEN_LED 15
+#define PIN_USB_POWER 21
+
+#define NSA310S_OE_LOW (~(0))
+#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
+
+/* high GPIO's */
+#define HDD2_GREEN_LED (1 << 2)
+#define HDD2_POWER (1 << 1)
+
+#define NSA310S_OE_HIGH (~(0))
+#define NSA310S_VAL_HIGH (HDD2_POWER)
+
+/* PHY related */
+#define MV88E1318_PGADR_REG 22
+#define MV88E1318_MAC_CTRL_PG 2
+#define MV88E1318_MAC_CTRL_REG 21
+#define MV88E1318_RGMII_TX_CTRL (1 << 4)
+#define MV88E1318_RGMII_RX_CTRL (1 << 5)
+#define MV88E1318_LED_PG 3
+#define MV88E1318_LED_POL_REG 17
+#define MV88E1318_LED2_4 (1 << 4)
+#define MV88E1318_LED2_5 (1 << 5)
+
+#endif /* __NSA310S_H */
endmenu
endmenu
+
+config CONSOLE_RECORD
+ bool "Console recording"
+ help
+ This provides a way to record console output (and provide console
+ input) through cirular buffers. This is mostly useful for testing.
+ Console output is recorded even when the console is silent.
+ To enable console recording, call console_record_reset_enable()
+ from your code.
+
+config CONSOLE_RECORD_OUT_SIZE
+ hex "Output buffer size"
+ depends on CONSOLE_RECORD
+ default 0x400 if CONSOLE_RECORD
+ help
+ Set the size of the console output buffer. When this fills up, no
+ more data will be recorded until some is removed. The buffer is
+ allocated immediately after the malloc() region is ready.
+
+config CONSOLE_RECORD_IN_SIZE
+ hex "Input buffer size"
+ depends on CONSOLE_RECORD
+ default 0x100 if CONSOLE_RECORD
+ help
+ Set the size of the console input buffer. When this contains data,
+ tstc() and getc() will use this in preference to real device input.
+ The buffer is allocated immediately after the malloc() region is
+ ready.
#include <autoboot.h>
#include <bootretry.h>
#include <cli.h>
+#include <console.h>
#include <fdtdec.h>
#include <menu.h>
#include <post.h>
#include <common.h>
#include <linux/compiler.h>
#include <version.h>
+#include <console.h>
#include <environment.h>
#include <dm.h>
#include <fdtdec.h>
return 0;
}
+static int initf_console_record(void)
+{
+#if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F_LEN)
+ return console_record_init();
+#else
+ return 0;
+#endif
+}
+
static int initf_dm(void)
{
#if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN)
trace_early_init,
#endif
initf_malloc,
+ initf_console_record,
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/* TODO: can this go into arch_cpu_init()? */
probecpu,
x86_fsp_init,
#endif
arch_cpu_init, /* basic arch cpu dependent setup */
- mark_bootstage,
initf_dm,
arch_cpu_init_dm,
+ mark_bootstage, /* need timer, go after init dm */
#if defined(CONFIG_BOARD_EARLY_INIT_F)
board_early_init_f,
#endif
#if defined(CONFIG_CMD_BEDBUG)
#include <bedbug/type.h>
#endif
+#include <console.h>
#ifdef CONFIG_HAS_DATAFLASH
#include <dataflash.h>
#endif
return 0;
}
+static int initr_console_record(void)
+{
+#if defined(CONFIG_CONSOLE_RECORD)
+ return console_record_init();
+#else
+ return 0;
+#endif
+}
+
#ifdef CONFIG_SYS_NONCACHED_MEMORY
static int initr_noncached(void)
{
#endif
initr_barrier,
initr_malloc,
+ initr_console_record,
#ifdef CONFIG_SYS_NONCACHED_MEMORY
initr_noncached,
#endif
#include <common.h>
#include <cli.h>
#include <cli_hush.h>
+#include <console.h>
#include <fdtdec.h>
#include <malloc.h>
#include <malloc.h> /* malloc, free, realloc*/
#include <linux/ctype.h> /* isalpha, isdigit */
#include <common.h> /* readline */
+#include <console.h>
#include <bootretry.h>
#include <cli.h>
#include <cli_hush.h>
#include <common.h>
#include <bootretry.h>
#include <cli.h>
+#include <console.h>
#include <linux/ctype.h>
#define DEBUG_PARSER 0 /* set to 1 to debug */
*/
#include <common.h>
#include <command.h>
+#include <console.h>
#include <asm/io.h>
#define MAX_REGIONS 4
#include <common.h>
#include <cli.h>
#include <command.h>
+#include <console.h>
#include <linux/ctype.h>
#include <net.h>
#include <bedbug/type.h>
#include <cli.h>
#include <config.h>
#include <command.h>
+#include <console.h>
unsigned long get_dcr (unsigned short);
unsigned long set_dcr (unsigned short, unsigned long);
#include <common.h>
#include <watchdog.h>
#include <dfu.h>
+#include <console.h>
#include <g_dnl.h>
#include <usb.h>
#include <net.h>
#include <command.h>
#include <i2c.h>
-extern void eeprom_init (void);
-extern int eeprom_read (unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt);
-extern int eeprom_write (unsigned dev_addr, unsigned offset,
- uchar *buffer, unsigned cnt);
-#if defined(CONFIG_SYS_EEPROM_WREN)
-extern int eeprom_write_enable (unsigned dev_addr, int state);
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED 50000
#endif
-
-#if defined(CONFIG_SYS_EEPROM_X40430)
- /* Maximum number of times to poll for acknowledge after write */
-#define MAX_ACKNOWLEDGE_POLLS 10
+#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 0
#endif
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_EEPROM)
-static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- const char *const fmt =
- "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
-
-#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
- if (argc == 6) {
- ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
- ulong addr = simple_strtoul (argv[3], NULL, 16);
- ulong off = simple_strtoul (argv[4], NULL, 16);
- ulong cnt = simple_strtoul (argv[5], NULL, 16);
-#else
- if (argc == 5) {
- ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
- ulong addr = simple_strtoul (argv[2], NULL, 16);
- ulong off = simple_strtoul (argv[3], NULL, 16);
- ulong cnt = simple_strtoul (argv[4], NULL, 16);
-#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
-
-# if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
- eeprom_init ();
-# endif /* !CONFIG_SPI */
-
- if (strcmp (argv[1], "read") == 0) {
- int rcode;
-
- printf (fmt, dev_addr, argv[1], addr, off, cnt);
-
- rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);
-
- puts ("done\n");
- return rcode;
- } else if (strcmp (argv[1], "write") == 0) {
- int rcode;
-
- printf (fmt, dev_addr, argv[1], addr, off, cnt);
-
- rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
-
- puts ("done\n");
- return rcode;
- }
- }
-
- return CMD_RET_USAGE;
-}
+#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 8
#endif
-/*-----------------------------------------------------------------------
- *
+#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
+#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
+
+/*
* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
*
* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
* 0x00000nxx for EEPROM address selectors and page number at n.
*/
-
#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
-#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 || CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
+#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || \
+ (CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1) || \
+ (CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2)
#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
#endif
#endif
-int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+__weak int eeprom_write_enable(unsigned dev_addr, int state)
{
- unsigned end = offset + cnt;
- unsigned blk_off;
- int rcode = 0;
+ return 0;
+}
- /* Read data until done or would cross a page boundary.
- * We must write the address again when changing pages
- * because the next page may be in a different device.
- */
- while (offset < end) {
- unsigned alen, len;
-#if !defined(CONFIG_SYS_I2C_FRAM)
- unsigned maxlen;
+void eeprom_init(int bus)
+{
+ /* SPI EEPROM */
+#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
+ spi_init_f();
#endif
-#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
- uchar addr[2];
+ /* I2C EEPROM */
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+#if defined(CONFIG_SYS_I2C)
+ if (bus >= 0)
+ i2c_set_bus_num(bus);
+#endif
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+}
- blk_off = offset & 0xFF; /* block offset */
+static int eeprom_addr(unsigned dev_addr, unsigned offset, uchar *addr)
+{
+ unsigned blk_off;
+ int alen;
- addr[0] = offset >> 8; /* block number */
- addr[1] = blk_off; /* block offset */
- alen = 2;
+ blk_off = offset & 0xff; /* block offset */
+#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1
+ addr[0] = offset >> 8; /* block number */
+ addr[1] = blk_off; /* block offset */
+ alen = 2;
#else
- uchar addr[3];
-
- blk_off = offset & 0xFF; /* block offset */
-
- addr[0] = offset >> 16; /* block number */
- addr[1] = offset >> 8; /* upper address octet */
- addr[2] = blk_off; /* lower address octet */
- alen = 3;
-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
-
- addr[0] |= dev_addr; /* insert device address */
+ addr[0] = offset >> 16; /* block number */
+ addr[1] = offset >> 8; /* upper address octet */
+ addr[2] = blk_off; /* lower address octet */
+ alen = 3;
+#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN */
- len = end - offset;
+ addr[0] |= dev_addr; /* insert device address */
- /*
- * For a FRAM device there is no limit on the number of the
- * bytes that can be ccessed with the single read or write
- * operation.
- */
-#if !defined(CONFIG_SYS_I2C_FRAM)
- maxlen = 0x100 - blk_off;
- if (maxlen > I2C_RXTX_LEN)
- maxlen = I2C_RXTX_LEN;
- if (len > maxlen)
- len = maxlen;
-#endif
-
-#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
- spi_read (addr, alen, buffer, len);
-#else
-#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
- i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
-#endif
- if (i2c_read(addr[0], offset, alen - 1, buffer, len))
- rcode = 1;
-#endif
- buffer += len;
- offset += len;
- }
-
- return rcode;
+ return alen;
}
-/*-----------------------------------------------------------------------
- *
- * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
- * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
- *
- * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
- * 0x00000nxx for EEPROM address selectors and page number at n.
- */
-
-int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
+static int eeprom_len(unsigned offset, unsigned end)
{
- unsigned end = offset + cnt;
- unsigned blk_off;
- int rcode = 0;
-
-#if defined(CONFIG_SYS_EEPROM_X40430)
- uchar contr_r_addr[2];
- uchar addr_void[2];
- uchar contr_reg[2];
- uchar ctrl_reg_v;
- int i;
-#endif
+ unsigned len = end - offset;
-#if defined(CONFIG_SYS_EEPROM_WREN)
- eeprom_write_enable (dev_addr,1);
-#endif
- /* Write data until done or would cross a write page boundary.
- * We must write the address again when changing pages
- * because the address counter only increments within a page.
+ /*
+ * For a FRAM device there is no limit on the number of the
+ * bytes that can be ccessed with the single read or write
+ * operation.
*/
-
- while (offset < end) {
- unsigned alen, len;
#if !defined(CONFIG_SYS_I2C_FRAM)
- unsigned maxlen;
-#endif
+ unsigned blk_off = offset & 0xff;
+ unsigned maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
-#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
- uchar addr[2];
+ if (maxlen > I2C_RXTX_LEN)
+ maxlen = I2C_RXTX_LEN;
- blk_off = offset & 0xFF; /* block offset */
-
- addr[0] = offset >> 8; /* block number */
- addr[1] = blk_off; /* block offset */
- alen = 2;
-#else
- uchar addr[3];
+ if (len > maxlen)
+ len = maxlen;
+#endif
- blk_off = offset & 0xFF; /* block offset */
+ return len;
+}
- addr[0] = offset >> 16; /* block number */
- addr[1] = offset >> 8; /* upper address octet */
- addr[2] = blk_off; /* lower address octet */
- alen = 3;
-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
+static int eeprom_rw_block(unsigned offset, uchar *addr, unsigned alen,
+ uchar *buffer, unsigned len, bool read)
+{
+ int ret = 0;
- addr[0] |= dev_addr; /* insert device address */
+ /* SPI */
+#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
+ if (read)
+ spi_read(addr, alen, buffer, len);
+ else
+ spi_write(addr, alen, buffer, len);
+#else /* I2C */
- len = end - offset;
+#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
+ i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+#endif
- /*
- * For a FRAM device there is no limit on the number of the
- * bytes that can be accessed with the single read or write
- * operation.
- */
-#if !defined(CONFIG_SYS_I2C_FRAM)
+ if (read)
+ ret = i2c_read(addr[0], offset, alen - 1, buffer, len);
+ else
+ ret = i2c_write(addr[0], offset, alen - 1, buffer, len);
-#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
+ if (ret)
+ ret = 1;
+#endif
+ return ret;
+}
-#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
-#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
+static int eeprom_rw(unsigned dev_addr, unsigned offset, uchar *buffer,
+ unsigned cnt, bool read)
+{
+ unsigned end = offset + cnt;
+ unsigned alen, len;
+ int rcode = 0;
+ uchar addr[3];
- maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
-#else
- maxlen = 0x100 - blk_off;
-#endif
- if (maxlen > I2C_RXTX_LEN)
- maxlen = I2C_RXTX_LEN;
+ while (offset < end) {
+ alen = eeprom_addr(dev_addr, offset, addr);
- if (len > maxlen)
- len = maxlen;
-#endif
+ len = eeprom_len(offset, end);
-#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
- spi_write (addr, alen, buffer, len);
-#else
-#if defined(CONFIG_SYS_EEPROM_X40430)
- /* Get the value of the control register.
- * Set current address (internal pointer in the x40430)
- * to 0x1ff.
- */
- contr_r_addr[0] = 9;
- contr_r_addr[1] = 0xff;
- addr_void[0] = 0;
- addr_void[1] = addr[1];
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
- contr_r_addr[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
- addr_void[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
-#endif
- contr_reg[0] = 0xff;
- if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
- rcode = 1;
- }
- ctrl_reg_v = contr_reg[0];
-
- /* Are any of the eeprom blocks write protected?
- */
- if (ctrl_reg_v & 0x18) {
- ctrl_reg_v &= ~0x18; /* reset block protect bits */
- ctrl_reg_v |= 0x02; /* set write enable latch */
- ctrl_reg_v &= ~0x04; /* clear RWEL */
-
- /* Set write enable latch.
- */
- contr_reg[0] = 0x02;
- if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
- rcode = 1;
- }
-
- /* Set register write enable latch.
- */
- contr_reg[0] = 0x06;
- if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
- rcode = 1;
- }
-
- /* Modify ctrl register.
- */
- contr_reg[0] = ctrl_reg_v;
- if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
- rcode = 1;
- }
-
- /* The write (above) is an operation on NV memory.
- * These can take some time (~5ms), and the device
- * will not respond to further I2C messages till
- * it's completed the write.
- * So poll device for an I2C acknowledge.
- * When we get one we know we can continue with other
- * operations.
- */
- contr_reg[0] = 0;
- for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
- if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
- break; /* got ack */
-#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
- udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
-#endif
- }
- if (i == MAX_ACKNOWLEDGE_POLLS) {
- puts ("EEPROM poll acknowledge failed\n");
- rcode = 1;
- }
- }
-
- /* Is the write enable latch on?.
- */
- else if (!(ctrl_reg_v & 0x02)) {
- /* Set write enable latch.
- */
- contr_reg[0] = 0x02;
- if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
- rcode = 1;
- }
- }
- /* Write is enabled ... now write eeprom value.
- */
-#endif
-#if defined(CONFIG_SYS_I2C_EEPROM_BUS)
- i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
-#endif
- if (i2c_write(addr[0], offset, alen - 1, buffer, len))
- rcode = 1;
+ rcode = eeprom_rw_block(offset, addr, alen, buffer, len, read);
-#endif
buffer += len;
offset += len;
-#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
- udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
-#endif
+ if (!read)
+ udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
}
-#if defined(CONFIG_SYS_EEPROM_WREN)
- eeprom_write_enable (dev_addr,0);
-#endif
+
return rcode;
}
-#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
-int
-eeprom_probe (unsigned dev_addr, unsigned offset)
+int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
{
- unsigned char chip;
-
- /* Probe the chip address
+ /*
+ * Read data until done or would cross a page boundary.
+ * We must write the address again when changing pages
+ * because the next page may be in a different device.
*/
-#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
- chip = offset >> 8; /* block number */
-#else
- chip = offset >> 16; /* block number */
-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
+ return eeprom_rw(dev_addr, offset, buffer, cnt, 1);
+}
+
+int eeprom_write(unsigned dev_addr, unsigned offset,
+ uchar *buffer, unsigned cnt)
+{
+ int ret;
+
+ eeprom_write_enable(dev_addr, 1);
- chip |= dev_addr; /* insert device address */
+ /*
+ * Write data until done or would cross a write page boundary.
+ * We must write the address again when changing pages
+ * because the address counter only increments within a page.
+ */
+ ret = eeprom_rw(dev_addr, offset, buffer, cnt, 1);
- return (i2c_probe (chip));
+ eeprom_write_enable(dev_addr, 0);
+ return ret;
}
-#endif
-/*-----------------------------------------------------------------------
- * Set default values
- */
-#ifndef CONFIG_SYS_I2C_SPEED
-#define CONFIG_SYS_I2C_SPEED 50000
+static int do_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const char *const fmt =
+ "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
+ char * const *args = &argv[2];
+ int rcode;
+ ulong dev_addr, addr, off, cnt;
+ int bus_addr;
+
+ switch (argc) {
+#ifdef CONFIG_SYS_DEF_EEPROM_ADDR
+ case 5:
+ bus_addr = -1;
+ dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
+ break;
#endif
+ case 6:
+ bus_addr = -1;
+ dev_addr = simple_strtoul(*args++, NULL, 16);
+ break;
+ case 7:
+ bus_addr = simple_strtoul(*args++, NULL, 16);
+ dev_addr = simple_strtoul(*args++, NULL, 16);
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
-void eeprom_init (void)
-{
+ addr = simple_strtoul(*args++, NULL, 16);
+ off = simple_strtoul(*args++, NULL, 16);
+ cnt = simple_strtoul(*args++, NULL, 16);
-#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
- spi_init_f ();
-#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-}
+ eeprom_init(bus_addr);
-/*-----------------------------------------------------------------------
- */
+ if (strcmp(argv[1], "read") == 0) {
+ printf(fmt, dev_addr, argv[1], addr, off, cnt);
+
+ rcode = eeprom_read(dev_addr, off, (uchar *)addr, cnt);
+
+ puts("done\n");
+ return rcode;
+ } else if (strcmp(argv[1], "write") == 0) {
+ printf(fmt, dev_addr, argv[1], addr, off, cnt);
-/***************************************************/
+ rcode = eeprom_write(dev_addr, off, (uchar *)addr, cnt);
-#if defined(CONFIG_CMD_EEPROM)
+ puts("done\n");
+ return rcode;
+ }
+
+ return CMD_RET_USAGE;
+}
-#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
U_BOOT_CMD(
- eeprom, 6, 1, do_eeprom,
+ eeprom, 7, 1, do_eeprom,
"EEPROM sub-system",
- "read devaddr addr off cnt\n"
- "eeprom write devaddr addr off cnt\n"
+ "read <bus> <devaddr> addr off cnt\n"
+ "eeprom write <bus> <devaddr> addr off cnt\n"
" - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
)
-#else /* One EEPROM */
-U_BOOT_CMD(
- eeprom, 5, 1, do_eeprom,
- "EEPROM sub-system",
- "read addr off cnt\n"
- "eeprom write addr off cnt\n"
- " - read/write `cnt' bytes at EEPROM offset `off'"
-)
-#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
-
-#endif
*/
#include <common.h>
#include <command.h>
+#include <console.h>
#include <g_dnl.h>
#include <usb.h>
#include <common.h>
#include <command.h>
+#include <console.h>
#include <gdsys_fpga.h>
#include <common.h>
#include <command.h>
+#include <console.h>
#include <fuse.h>
#include <asm/errno.h>
/*
* cmd_gpt.c -- GPT (GUID Partition Table) handling command
*
+ * Copyright (C) 2015
+ * Lukasz Majewski <l.majewski@majess.pl>
+ *
* Copyright (C) 2012 Samsung Electronics
* author: Lukasz Majewski <l.majewski@samsung.com>
* author: Piotr Wilczek <p.wilczek@samsung.com>
#include <exports.h>
#include <linux/ctype.h>
#include <div64.h>
+#include <memalign.h>
#ifndef CONFIG_PARTITION_UUIDS
#error CONFIG_PARTITION_UUIDS must be enabled for CONFIG_CMD_GPT to be enabled
return new;
}
+/**
+ * found_key(): Found key without value in parameter list (comma separated).
+ *
+ * @param str - pointer to string with key
+ * @param key - pointer to the key to search for
+ *
+ * @return - true on found key
+ */
+static bool found_key(const char *str, const char *key)
+{
+ char *k;
+ char *s, *strcopy;
+ bool result = false;
+
+ strcopy = strdup(str);
+ if (!strcopy)
+ return NULL;
+
+ s = strcopy;
+ while (s) {
+ k = strsep(&s, ",");
+ if (!k)
+ break;
+ if (strcmp(k, key) == 0) {
+ result = true;
+ break;
+ }
+ }
+
+ free(strcopy);
+
+ return result;
+}
+
/**
* set_gpt_info(): Fill partition information from string
* function allocates memory, remember to free!
parts[i].start = lldiv(start_ll, dev_desc->blksz);
free(val);
}
+
+ /* bootable */
+ if (found_key(tok, "bootable"))
+ parts[i].bootable = 1;
}
*parts_count = p_count;
u8 part_count = 0;
disk_partition_t *partitions = NULL;
- if (!str_part)
- return -1;
-
/* fill partitions */
ret = set_gpt_info(blk_dev_desc, str_part,
&str_disk_guid, &partitions, &part_count);
return ret;
}
+static int gpt_verify(block_dev_desc_t *blk_dev_desc, const char *str_part)
+{
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1,
+ blk_dev_desc->blksz);
+ disk_partition_t *partitions = NULL;
+ gpt_entry *gpt_pte = NULL;
+ char *str_disk_guid;
+ u8 part_count = 0;
+ int ret = 0;
+
+ /* fill partitions */
+ ret = set_gpt_info(blk_dev_desc, str_part,
+ &str_disk_guid, &partitions, &part_count);
+ if (ret) {
+ if (ret == -1) {
+ printf("No partition list provided - only basic check\n");
+ ret = gpt_verify_headers(blk_dev_desc, gpt_head,
+ &gpt_pte);
+ goto out;
+ }
+ if (ret == -2)
+ printf("Missing disk guid\n");
+ if ((ret == -3) || (ret == -4))
+ printf("Partition list incomplete\n");
+ return -1;
+ }
+
+ /* Check partition layout with provided pattern */
+ ret = gpt_verify_partitions(blk_dev_desc, partitions, part_count,
+ gpt_head, &gpt_pte);
+ free(str_disk_guid);
+ free(partitions);
+ out:
+ free(gpt_pte);
+ return ret;
+}
+
/**
* do_gpt(): Perform GPT operations
*
int ret = CMD_RET_SUCCESS;
int dev = 0;
char *ep;
- block_dev_desc_t *blk_dev_desc;
+ block_dev_desc_t *blk_dev_desc = NULL;
- if (argc < 5)
+ if (argc < 4 || argc > 5)
return CMD_RET_USAGE;
- /* command: 'write' */
- if ((strcmp(argv[1], "write") == 0) && (argc == 5)) {
- dev = (int)simple_strtoul(argv[3], &ep, 10);
- if (!ep || ep[0] != '\0') {
- printf("'%s' is not a number\n", argv[3]);
- return CMD_RET_USAGE;
- }
- blk_dev_desc = get_dev(argv[2], dev);
- if (!blk_dev_desc) {
- printf("%s: %s dev %d NOT available\n",
- __func__, argv[2], dev);
- return CMD_RET_FAILURE;
- }
-
- puts("Writing GPT: ");
+ dev = (int)simple_strtoul(argv[3], &ep, 10);
+ if (!ep || ep[0] != '\0') {
+ printf("'%s' is not a number\n", argv[3]);
+ return CMD_RET_USAGE;
+ }
+ blk_dev_desc = get_dev(argv[2], dev);
+ if (!blk_dev_desc) {
+ printf("%s: %s dev %d NOT available\n",
+ __func__, argv[2], dev);
+ return CMD_RET_FAILURE;
+ }
+ if ((strcmp(argv[1], "write") == 0) && (argc == 5)) {
+ printf("Writing GPT: ");
ret = gpt_default(blk_dev_desc, argv[4]);
- if (!ret) {
- puts("success!\n");
- return CMD_RET_SUCCESS;
- } else {
- puts("error!\n");
- return CMD_RET_FAILURE;
- }
+ } else if ((strcmp(argv[1], "verify") == 0)) {
+ ret = gpt_verify(blk_dev_desc, argv[4]);
+ printf("Verify GPT: ");
} else {
return CMD_RET_USAGE;
}
- return ret;
+
+ if (ret) {
+ printf("error!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("success!\n");
+ return CMD_RET_SUCCESS;
}
U_BOOT_CMD(gpt, CONFIG_SYS_MAXARGS, 1, do_gpt,
"GUID Partition Table",
"<command> <interface> <dev> <partitions_list>\n"
- " - GUID partition table restoration\n"
- " Restore GPT information on a device connected\n"
+ " - GUID partition table restoration and validity check\n"
+ " Restore or verify GPT information on a device connected\n"
" to interface\n"
+ " Example usage:\n"
+ " gpt write mmc 0 $partitions\n"
+ " gpt verify mmc 0 $partitions\n"
);
#include <bootretry.h>
#include <cli.h>
#include <command.h>
+#include <console.h>
#include <dm.h>
#include <edid.h>
#include <environment.h>
*/
#include <common.h>
#include <command.h>
+#include <console.h>
#include <s_record.h>
#include <net.h>
#include <exports.h>
*/
#include <common.h>
+#include <console.h>
#include <bootretry.h>
#include <cli.h>
#include <command.h>
+#include <console.h>
#ifdef CONFIG_HAS_DATAFLASH
#include <dataflash.h>
#endif
mask = simple_strtoul(argv[5], NULL, 16);
}
+ if (addrhi > 31) {
+ printf("Incorrect PHY address. Range should be 0-31\n");
+ return CMD_RET_USAGE;
+ }
+
/* use current device */
devname = miiphy_get_current_dev();
*/
#include <common.h>
#include <command.h>
+#include <console.h>
static int do_sleep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#include <common.h>
#include <command.h>
+#include <console.h>
#include <mmc.h>
static int curr_device = -1;
#include <common.h>
#include <linux/mtd/mtd.h>
#include <command.h>
+#include <console.h>
#include <watchdog.h>
#include <malloc.h>
#include <asm/byteorder.h>
#include <common.h>
#include <cli.h>
#include <command.h>
+#include <console.h>
#include <environment.h>
#include <search.h>
#include <errno.h>
#include <config.h>
#include <common.h>
#include <command.h>
+#include <console.h>
#include <asm/blackfin.h>
#include <asm/clock.h>
#include <bootretry.h>
#include <cli.h>
#include <command.h>
+#include <console.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#include <common.h>
#include <command.h>
+#include <console.h>
#include <dm.h>
#include <memalign.h>
#include <asm/byteorder.h>
}
/* main routine for the tree command */
-static void usb_show_tree(struct usb_device *dev)
+static void usb_show_subtree(struct usb_device *dev)
{
char preamble[32];
usb_show_tree_graph(dev, &preamble[0]);
}
+void usb_show_tree(void)
+{
+#ifdef CONFIG_DM_USB
+ struct udevice *bus;
+
+ for (uclass_first_device(UCLASS_USB, &bus);
+ bus;
+ uclass_next_device(&bus)) {
+ struct usb_device *udev;
+ struct udevice *dev;
+
+ device_find_first_child(bus, &dev);
+ if (dev && device_active(dev)) {
+ udev = dev_get_parent_priv(dev);
+ usb_show_subtree(udev);
+ }
+ }
+#else
+ struct usb_device *udev;
+ int i;
+
+ for (i = 0; i < USB_MAX_DEVICE; i++) {
+ udev = usb_get_dev_index(i);
+ if (udev == NULL)
+ break;
+ if (udev->parent == NULL)
+ usb_show_subtree(udev);
+ }
+#endif
+}
+
static int usb_test(struct usb_device *dev, int port, char* arg)
{
int mode;
/* Driver model will probe the devices as they are found */
#ifndef CONFIG_DM_USB
-#ifdef CONFIG_USB_STORAGE
+# ifdef CONFIG_USB_STORAGE
/* try to recognize storage devices immediately */
usb_stor_curr_dev = usb_stor_scan(1);
-#endif
-#endif
+# endif
+# ifdef CONFIG_USB_KEYBOARD
+ drv_usb_kbd_init();
+# endif
+#endif /* !CONFIG_DM_USB */
#ifdef CONFIG_USB_HOST_ETHER
# ifdef CONFIG_DM_ETH
# ifndef CONFIG_DM_USB
usb_ether_curr_dev = usb_host_eth_scan(1);
# endif
#endif
-#ifdef CONFIG_USB_KEYBOARD
- drv_usb_kbd_init();
-#endif
}
#ifdef CONFIG_DM_USB
}
if (strncmp(argv[1], "tree", 4) == 0) {
puts("USB device tree:\n");
-#ifdef CONFIG_DM_USB
- struct udevice *bus;
-
- for (uclass_first_device(UCLASS_USB, &bus);
- bus;
- uclass_next_device(&bus)) {
- struct usb_device *udev;
- struct udevice *dev;
-
- device_find_first_child(bus, &dev);
- if (dev && device_active(dev)) {
- udev = dev_get_parent_priv(dev);
- usb_show_tree(udev);
- }
- }
-#else
- for (i = 0; i < USB_MAX_DEVICE; i++) {
- udev = usb_get_dev_index(i);
- if (udev == NULL)
- break;
- if (udev->parent == NULL)
- usb_show_tree(udev);
- }
-#endif
+ usb_show_tree();
return 0;
}
if (strncmp(argv[1], "inf", 3) == 0) {
#include <errno.h>
#include <common.h>
#include <command.h>
+#include <console.h>
#include <g_dnl.h>
#include <part.h>
#include <usb.h>
#include <common.h>
#include <command.h>
+#include <console.h>
#include <linux/ctype.h>
/*
*/
#include <common.h>
+#include <console.h>
#include <debug_uart.h>
#include <stdarg.h>
#include <iomux.h>
if (!gd->have_console)
return 0;
+#ifdef CONFIG_CONSOLE_RECORD
+ if (gd->console_in.start) {
+ int ch;
+
+ ch = membuff_getbyte(&gd->console_in);
+ if (ch != -1)
+ return 1;
+ }
+#endif
if (gd->flags & GD_FLG_DEVINIT) {
/* Get from the standard input */
return fgetc(stdin);
if (!gd->have_console)
return 0;
-
+#ifdef CONFIG_CONSOLE_RECORD
+ if (gd->console_in.start) {
+ if (membuff_peekbyte(&gd->console_in) != -1)
+ return 1;
+ }
+#endif
if (gd->flags & GD_FLG_DEVINIT) {
/* Test the standard input */
return ftstc(stdin);
return;
}
#endif
+#ifdef CONFIG_CONSOLE_RECORD
+ if (gd && (gd->flags & GD_FLG_RECORD) && gd->console_out.start)
+ membuff_putbyte(&gd->console_out, c);
+#endif
#ifdef CONFIG_SILENT_CONSOLE
if (gd->flags & GD_FLG_SILENT)
return;
return;
}
#endif
+#ifdef CONFIG_CONSOLE_RECORD
+ if (gd && (gd->flags & GD_FLG_RECORD) && gd->console_out.start)
+ membuff_put(&gd->console_out, s, strlen(s));
+#endif
#ifdef CONFIG_SILENT_CONSOLE
if (gd->flags & GD_FLG_SILENT)
return;
}
}
-int printf(const char *fmt, ...)
+#ifdef CONFIG_CONSOLE_RECORD
+int console_record_init(void)
{
- va_list args;
- uint i;
- char printbuffer[CONFIG_SYS_PBSIZE];
+ int ret;
- va_start(args, fmt);
+ ret = membuff_new(&gd->console_out, CONFIG_CONSOLE_RECORD_OUT_SIZE);
+ if (ret)
+ return ret;
+ ret = membuff_new(&gd->console_in, CONFIG_CONSOLE_RECORD_IN_SIZE);
- /* For this to work, printbuffer must be larger than
- * anything we ever want to print.
- */
- i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
- va_end(args);
-
- /* Print the string */
- puts(printbuffer);
- return i;
+ return ret;
}
-int vprintf(const char *fmt, va_list args)
+void console_record_reset(void)
{
- uint i;
- char printbuffer[CONFIG_SYS_PBSIZE];
-
-#if defined(CONFIG_PRE_CONSOLE_BUFFER) && !defined(CONFIG_SANDBOX)
- if (!gd->have_console)
- return 0;
-#endif
-
- /* For this to work, printbuffer must be larger than
- * anything we ever want to print.
- */
- i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
+ membuff_purge(&gd->console_out);
+ membuff_purge(&gd->console_in);
+}
- /* Print the string */
- puts(printbuffer);
- return i;
+void console_record_reset_enable(void)
+{
+ console_record_reset();
+ gd->flags |= GD_FLG_RECORD;
}
+#endif
/* test if ctrl-c was pressed */
static int ctrlc_disabled = 0; /* see disable_ctrl() */
uchar rdbuf[64], flags[2];
int i, crc_ok[2] = {0, 0};
- eeprom_init(); /* prepare for EEPROM read/write */
+ eeprom_init(-1); /* prepare for EEPROM read/write */
off_env[0] = CONFIG_ENV_OFFSET;
off_env[1] = CONFIG_ENV_OFFSET_REDUND;
ulong crc, len, new;
uchar rdbuf[64];
- eeprom_init(); /* prepare for EEPROM read/write */
+ eeprom_init(-1); /* prepare for EEPROM read/write */
/* read old CRC */
eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR,
return;
}
- if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)&buf,
- CONFIG_ENV_SIZE)) {
+ if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, buf, CONFIG_ENV_SIZE)) {
printf("\n** Unable to read env from %s:%s **\n",
CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME);
set_default_env(NULL);
{ IH_TYPE_RKIMAGE, "rkimage", "Rockchip Boot Image" },
{ IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" },
{ IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" },
+ { IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" },
{ -1, "", "", },
};
*/
#include <common.h>
+#include <console.h>
#include <serial.h>
#include <malloc.h>
#include <common.h>
#include <autoboot.h>
#include <cli.h>
+#include <console.h>
#include <version.h>
DECLARE_GLOBAL_DATA_PTR;
#include <config.h>
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <stdarg.h>
#include <malloc.h>
#include <i2c.h>
#endif
+#include <dm/device-internal.h>
+
DECLARE_GLOBAL_DATA_PTR;
static struct stdio_dev devs;
int stdio_add_devices(void)
{
+#ifdef CONFIG_DM_KEYBOARD
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ /*
+ * For now we probe all the devices here. At some point this should be
+ * done only when the devices are required - e.g. we have a list of
+ * input devices to start up in the stdin environment variable. That
+ * work probably makes more sense when stdio itself is converted to
+ * driver model.
+ *
+ * TODO(sjg@chromium.org): Convert changing uclass_first_device() etc.
+ * to return the device even on error. Then we could use that here.
+ */
+ ret = uclass_get(UCLASS_KEYBOARD, &uc);
+ if (ret)
+ return ret;
+
+ /* Don't report errors to the caller - assume that they are non-fatal */
+ uclass_foreach_dev(dev, uc) {
+ ret = device_probe(dev);
+ if (ret)
+ printf("Failed to probe keyboard '%s'\n", dev->name);
+ }
+#endif
#ifdef CONFIG_SYS_I2C
i2c_init_all();
#else
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
drv_video_init ();
#endif
-#ifdef CONFIG_KEYBOARD
+#if defined(CONFIG_KEYBOARD) && !defined(CONFIG_DM_KEYBOARD)
drv_keyboard_init ();
#endif
#ifdef CONFIG_LOGBUFFER
#include <asm/unaligned.h>
#include <linux/ctype.h>
#include <asm/byteorder.h>
+#ifdef CONFIG_SANDBOX
+#include <asm/state.h>
+#endif
#include <asm/unaligned.h>
#include <dm/root.h>
unsigned short portstatus, portchange;
int ret;
ulong start = get_timer(0);
+ uint delay = CONFIG_SYS_HZ;
+#ifdef CONFIG_SANDBOX
+ if (state_get_skip_delays())
+ delay = 0;
+#endif
#ifdef CONFIG_DM_USB
debug("\n\nScanning '%s' port %d\n", dev->dev->name, i + 1);
#else
if (portstatus & USB_PORT_STAT_CONNECTION)
break;
- } while (get_timer(start) < CONFIG_SYS_HZ * 1);
+ } while (get_timer(start) < delay);
if (ret < 0)
continue;
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <console.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
}
/* probes the USB device dev for keyboard type. */
-static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum)
+static int usb_kbd_probe_dev(struct usb_device *dev, unsigned int ifnum)
{
struct usb_interface *iface;
struct usb_endpoint_descriptor *ep;
iface = &dev->config.if_desc[ifnum];
- if (iface->desc.bInterfaceClass != 3)
+ if (iface->desc.bInterfaceClass != USB_CLASS_HID)
return 0;
- if (iface->desc.bInterfaceSubClass != 1)
+ if (iface->desc.bInterfaceSubClass != USB_SUB_HID_BOOT)
return 0;
- if (iface->desc.bInterfaceProtocol != 1)
+ if (iface->desc.bInterfaceProtocol != USB_PROT_HID_KEYBOARD)
return 0;
if (iface->desc.bNumEndpoints != 1)
int error;
/* Try probing the keyboard */
- if (usb_kbd_probe(dev, 0) != 1)
+ if (usb_kbd_probe_dev(dev, 0) != 1)
return -ENOENT;
/* Register the keyboard */
return 0;
}
+#ifndef CONFIG_DM_USB
/* Search for keyboard and register it if found. */
int drv_usb_kbd_init(void)
{
int error, i;
debug("%s: Probing for keyboard\n", __func__);
-#ifdef CONFIG_DM_USB
- /*
- * TODO: We should add U_BOOT_USB_DEVICE() declarations to each USB
- * keyboard driver and then most of this file can be removed.
- */
- struct udevice *bus;
- struct uclass *uc;
- int ret;
-
- ret = uclass_get(UCLASS_USB, &uc);
- if (ret)
- return ret;
- uclass_foreach_dev(bus, uc) {
- for (i = 0; i < USB_MAX_DEVICE; i++) {
- struct usb_device *dev;
-
- dev = usb_get_dev_index(bus, i); /* get device */
- debug("i=%d, %p\n", i, dev);
- if (!dev)
- break; /* no more devices available */
-
- error = probe_usb_keyboard(dev);
- if (!error)
- return 1;
- if (error && error != -ENOENT)
- return error;
- } /* for */
- }
-#else
/* Scan all USB Devices */
for (i = 0; i < USB_MAX_DEVICE; i++) {
struct usb_device *dev;
if (error && error != -ENOENT)
return error;
}
-#endif
/* No USB Keyboard found */
return -1;
}
+#endif
/* Deregister the keyboard. */
int usb_kbd_deregister(int force)
return 1;
#endif
}
+
+#ifdef CONFIG_DM_USB
+
+static int usb_kbd_probe(struct udevice *dev)
+{
+ struct usb_device *udev = dev_get_parent_priv(dev);
+ int ret;
+
+ ret = probe_usb_keyboard(udev);
+
+ return ret;
+}
+
+static const struct udevice_id usb_kbd_ids[] = {
+ { .compatible = "usb-keyboard" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_kbd) = {
+ .name = "usb_kbd",
+ .id = UCLASS_KEYBOARD,
+ .of_match = usb_kbd_ids,
+ .probe = usb_kbd_probe,
+};
+
+static const struct usb_device_id kbd_id_table[] = {
+ {
+ .match_flags = USB_DEVICE_ID_MATCH_INT_CLASS |
+ USB_DEVICE_ID_MATCH_INT_SUBCLASS |
+ USB_DEVICE_ID_MATCH_INT_PROTOCOL,
+ .bInterfaceClass = USB_CLASS_HID,
+ .bInterfaceSubClass = USB_SUB_HID_BOOT,
+ .bInterfaceProtocol = USB_PROT_HID_KEYBOARD,
+ },
+ { } /* Terminating entry */
+};
+
+U_BOOT_USB_DEVICE(usb_kbd, kbd_id_table);
+
+#endif
CONFIG_ALTERA_QSPI=y
CONFIG_DM_ETH=y
CONFIG_ALTERA_TSE=y
-CONFIG_ALTERA_UART=y
+CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
CONFIG_ALTERA_TIMER=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_SUNXI_NO_PMIC=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
-CONFIG_USB_MUSB_SUNXI=y
-CONFIG_USB_MUSB_GADGET=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_B4860QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_BSC9132QDS=y
CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_CMD_GPIO=y
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_GPIO=y
CONFIG_NETCONSOLE=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_C29XPCIE=y
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_AXP_DCDC2_VOLT=1300
CONFIG_AXP_ALDO3_VOLT=3300
CONFIG_AXP_ALDO4_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_GADGET=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SPI_CS="PA0"
CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_USB0_VBUS_PIN="PH17"
+CONFIG_USB0_VBUS_DET="PH22"
+CONFIG_USB0_ID_DET="PH19"
CONFIG_VIDEO_VGA=y
CONFIG_GMAC_TX_DELAY=1
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB0_ID_DET="PH19"
-CONFIG_USB0_VBUS_DET="PH22"
-CONFIG_USB0_VBUS_PIN="PH17"
-CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB_MUSB_GADGET=y
# CONFIG_CMD_FLASH is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_FLASH is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=432
+CONFIG_MMC0_CD_PIN="PH10"
+CONFIG_GMAC_TX_DELAY=4
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_TARGET_MIP405=y
CONFIG_SYS_EXTRA_OPTIONS="MIP405T"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_MIP405=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308RDB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8315ERDB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8323ERDB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC832XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC832XEMDS=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8349EMDS=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC837XEMDS=y
CONFIG_SYS_EXTRA_OPTIONS="PCI"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC837XEMDS=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC837XERDB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8536DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8540ADS=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8541CDS=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8541CDS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8544DS=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8548CDS=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8555CDS=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8555CDS=y
CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_MPC8568MDS=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="ATM"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8569MDS=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8572DS=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8610HPCD=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_MPC8641HPCN=y
CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC86xx=y
CONFIG_TARGET_MPC8641HPCN=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
CONFIG_VIDEO_LCD_SSD2828_RESET="PA26"
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_DLDO1_VOLT=3300
CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1010RDB=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020MBG"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SYS_EXTRA_OPTIONS="P1020UTM"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1021RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1022DS=y
CONFIG_SYS_EXTRA_OPTIONS="36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1022DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1023RDB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1024RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P1025RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P1_P2_RDB_PC=y
CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P3041DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P4080DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P4080DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P4080DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5020DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_P5040DS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_4xx=y
CONFIG_TARGET_PIP405=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_AXP_ALDO1_VOLT=3300
CONFIG_AXP_ALDO2_VOLT=1800
CONFIG_AXP_DLDO1_VOLT=3000
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T1040QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T1040QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T1040QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T104XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T208XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T208XRDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T208XQDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240RDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240QDS=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TARGET_T4240RDB=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TQM834X=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_AUTOBOOT_STOP_STR="\x1b"
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_AUTOBOOT_STOP_STR="\x1b"
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_4xx=y
CONFIG_TARGET_VOM405=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_ACADIA=y
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_ADP_AG101P=y
CONFIG_SYS_PROMPT="NDS32 # "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DFU_TFTP=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
+CONFIG_SYS_NS16550=y
CONFIG_RSA=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_NFS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARCHES=y
CONFIG_DEFAULT_DEVICE_TREE="arches"
CONFIG_OF_CONTROL=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CLK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CLK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_BAMBOO=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_LIB_RAND=y
CONFIG_TARGET_BF527_EZKIT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
+# CONFIG_NET_TFTP_VARS is not set
CONFIG_SPI_FLASH=y
-CONFIG_NET_TFTP_VARS=n
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_LIB_RAND=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_BUBINGA=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NET is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_STOP_STR="\x0b"
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_NS16550=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
CONFIG_TPM_TIS_LPC=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
CONFIG_TPM_TIS_LPC=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
CONFIG_DM=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_TPM=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
CONFIG_CMD_TPM=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TPM=y
CONFIG_DM=y
+CONFIG_SYS_NS16550=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TPM=y
CONFIG_DM=y
+CONFIG_SYS_NS16550=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_OF_CONTROL=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_PCH_GBE=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_4xx=y
CONFIG_TARGET_INTIP=y
CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_DLVISION=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SYS_NS16550=y
+CONFIG_TI_QSPI=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_DREAMPLUG=y
+CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_SPI_FLASH=y
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
-CONFIG_CMD_SF=y
CONFIG_CMD_PING=y
-CONFIG_CMD_USB=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SPL=y
CONFIG_SYS_PROMPT="EDMiniV2> "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_DEBUG_EFI_CONSOLE=y
CONFIG_DEBUG_UART_BASE=0
CONFIG_DEBUG_UART_CLOCK=0
-# CONFIG_X86_SERIAL is not set
+CONFIG_ICH_SPI=y
CONFIG_EFI=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TARGET_GDPPC440ETX=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="glacier"
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_GURUPLUG=y
+CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_PING=y
-CONFIG_CMD_USB=y
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_KILAUEA=y
CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA"
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
-CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
-
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
+CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_IB62X0=y
+CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ib62x0 => "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_PING=y
-CONFIG_CMD_USB=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_ICON=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
CONFIG_AUTOBOOT_DELAY_STR="ids"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
CONFIG_SYS_EXTRA_OPTIONS="INTIB"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_IO64=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_KATMAI=y
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_KILAUEA=y
CONFIG_SYS_EXTRA_OPTIONS="KILAUEA"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
CONFIG_MPC83xx=y
CONFIG_TARGET_KM8360=y
CONFIG_SYS_EXTRA_OPTIONS="KMCOGE5NE"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_KM8360=y
CONFIG_SYS_EXTRA_OPTIONS="KMETER1"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_ESPI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="KMOPTI2"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="KMSUPX5"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
-CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
+CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
+CONFIG_SYS_NS16550=y
-CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2"
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
+CONFIG_SYS_EXTRA_OPTIONS="KMTEPR2"
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_SYS_EXTRA_OPTIONS="KMVECT1"
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_NS16550=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_LUAN=y
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_LWMON5=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_MAKALU=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_THERMAL=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_NS16550=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
CONFIG_CMD_GPIO=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_AXP_ALDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_SUNXI_NO_PMIC=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MPC83xx=y
CONFIG_TARGET_MPC8308_P1M=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q"
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_THERMAL=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_THERMAL=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_THERMAL=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_THERMAL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_NEO=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_TARGET_NSA310S=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_PROMPT="nsa310s => "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_USB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65090=y
CONFIG_DM_REGULATOR=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_EXYNOS_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65090=y
CONFIG_DM_REGULATOR=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_EXYNOS_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
CONFIG_LIB_RAND=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP_DLDO1_VOLT=3300
+CONFIG_SYS_NS16550=y
CONFIG_USB_MUSB_HOST=y
# CONFIG_CMD_FLASH is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_AXP152_POWER=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="RAINIER"
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_REDWOOD=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SST=y
CONFIG_DM_THERMAL=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_PCI=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
CONFIG_FIT=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
+CONFIG_CONSOLE_RECORD=y
+CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
CONFIG_REGMAP=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_DM_PCI=y
CONFIG_PCI_SANDBOX=y
CONFIG_SOUND=y
CONFIG_SOUND_SANDBOX=y
CONFIG_SANDBOX_SPI=y
+CONFIG_TIMER=y
+CONFIG_SANDBOX_TIMER=y
CONFIG_TPM_TIS_SANDBOX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EMUL=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL=y
CONFIG_SYS_VSNPRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
CONFIG_TARGET_SBC8349=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_SBC8349=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_SBC8349=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,33"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_TARGET_SBC8548=y
CONFIG_SYS_EXTRA_OPTIONS="PCI,66"
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_SBC8548=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC86xx=y
CONFIG_TARGET_SBC8641D=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA"
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_SEQUOIA=y
CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_SHEEVAPLUG=y
+CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_HUSH_PARSER=y
CONFIG_CMD_DHCP=y
-CONFIG_CMD_NAND=y
CONFIG_CMD_PING=y
-CONFIG_CMD_USB=y
+CONFIG_SYS_NS16550=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
CONFIG_CMD_REGULATOR=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_DM_REGULATOR=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_EXYNOS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_BRIDGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM_I2C_COMPAT=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
+CONFIG_EXYNOS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_BRIDGE=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_PMIC_S5M8767=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_EXYNOS_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_CMD_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_CMD_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_TARGET_SOCRATES=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_MAX77686=y
CONFIG_PMIC_S5M8767=y
CONFIG_I2S_SAMSUNG=y
CONFIG_SOUND_MAX98095=y
CONFIG_SOUND_WM8994=y
+CONFIG_EXYNOS_SPI=y
CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SH_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
-CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_CADENCE_QSPI=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
+CONFIG_SYS_NS16550=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MPC83xx=y
CONFIG_TARGET_SUVD3=y
CONFIG_SYS_EXTRA_OPTIONS="SUVD3"
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_WALNUT=y
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_T3CORP=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SFLASH=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="TUGE1"
+CONFIG_SYS_NS16550=y
CONFIG_MPC83xx=y
CONFIG_TARGET_TUXX1=y
CONFIG_SYS_EXTRA_OPTIONS="TUXX1"
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_VCT_PLATINUM=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_VCT_PREMIUM=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_MPC83xx=y
CONFIG_TARGET_VE8313=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_MPC83xx=y
CONFIG_TARGET_VME8349=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_WALNUT=y
+CONFIG_SYS_NS16550=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
+CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_USE_TINY_PRINTF=y
CONFIG_4xx=y
CONFIG_TARGET_XPEDITE1000=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC86xx=y
CONFIG_TARGET_XPEDITE517X=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE520X=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE537X=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_MPC85xx=y
CONFIG_TARGET_XPEDITE550X=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_YOSEMITE=y
CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE"
+CONFIG_SYS_NS16550=y
CONFIG_4xx=y
CONFIG_TARGET_YOSEMITE=y
CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE"
+CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_YUCCA=y
+CONFIG_SYS_NS16550=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_ZYNQ_SPI=y
CONFIG_ZYNQ_QSPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_ZYNQ_QSPI=y
memset(&gpt_e[i].attributes, 0,
sizeof(gpt_entry_attributes));
+ if (partitions[i].bootable)
+ gpt_e[i].attributes.fields.legacy_bios_bootable = 1;
+
/* partition name */
efiname_len = sizeof(gpt_e[i].partition_name)
/ sizeof(efi_char16_t);
return ret;
}
+static void gpt_convert_efi_name_to_char(char *s, efi_char16_t *es, int n)
+{
+ char *ess = (char *)es;
+ int i, j;
+
+ memset(s, '\0', n);
+
+ for (i = 0, j = 0; j < n; i += 2, j++) {
+ s[j] = ess[i];
+ if (!ess[i])
+ return;
+ }
+}
+
+int gpt_verify_headers(block_dev_desc_t *dev_desc, gpt_header *gpt_head,
+ gpt_entry **gpt_pte)
+{
+ /*
+ * This function validates AND
+ * fills in the GPT header and PTE
+ */
+ if (is_gpt_valid(dev_desc,
+ GPT_PRIMARY_PARTITION_TABLE_LBA,
+ gpt_head, gpt_pte) != 1) {
+ printf("%s: *** ERROR: Invalid GPT ***\n",
+ __func__);
+ return -1;
+ }
+ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
+ gpt_head, gpt_pte) != 1) {
+ printf("%s: *** ERROR: Invalid Backup GPT ***\n",
+ __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+int gpt_verify_partitions(block_dev_desc_t *dev_desc,
+ disk_partition_t *partitions, int parts,
+ gpt_header *gpt_head, gpt_entry **gpt_pte)
+{
+ char efi_str[PARTNAME_SZ + 1];
+ u64 gpt_part_size;
+ gpt_entry *gpt_e;
+ int ret, i;
+
+ ret = gpt_verify_headers(dev_desc, gpt_head, gpt_pte);
+ if (ret)
+ return ret;
+
+ gpt_e = *gpt_pte;
+
+ for (i = 0; i < parts; i++) {
+ if (i == gpt_head->num_partition_entries) {
+ error("More partitions than allowed!\n");
+ return -1;
+ }
+
+ /* Check if GPT and ENV partition names match */
+ gpt_convert_efi_name_to_char(efi_str, gpt_e[i].partition_name,
+ PARTNAME_SZ + 1);
+
+ debug("%s: part: %2d name - GPT: %16s, ENV: %16s ",
+ __func__, i, efi_str, partitions[i].name);
+
+ if (strncmp(efi_str, (char *)partitions[i].name,
+ sizeof(partitions->name))) {
+ error("Partition name: %s does not match %s!\n",
+ efi_str, (char *)partitions[i].name);
+ return -1;
+ }
+
+ /* Check if GPT and ENV sizes match */
+ gpt_part_size = le64_to_cpu(gpt_e[i].ending_lba) -
+ le64_to_cpu(gpt_e[i].starting_lba) + 1;
+ debug("size(LBA) - GPT: %8llu, ENV: %8llu ",
+ gpt_part_size, (u64) partitions[i].size);
+
+ if (le64_to_cpu(gpt_part_size) != partitions[i].size) {
+ error("Partition %s size: %llu does not match %llu!\n",
+ efi_str, gpt_part_size, (u64) partitions[i].size);
+ return -1;
+ }
+
+ /*
+ * Start address is optional - check only if provided
+ * in '$partition' variable
+ */
+ if (!partitions[i].start) {
+ debug("\n");
+ continue;
+ }
+
+ /* Check if GPT and ENV start LBAs match */
+ debug("start LBA - GPT: %8llu, ENV: %8llu\n",
+ le64_to_cpu(gpt_e[i].starting_lba),
+ (u64) partitions[i].start);
+
+ if (le64_to_cpu(gpt_e[i].starting_lba) != partitions[i].start) {
+ error("Partition %s start: %llu does not match %llu!\n",
+ efi_str, le64_to_cpu(gpt_e[i].starting_lba),
+ (u64) partitions[i].start);
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf)
{
gpt_header *gpt_h;
Attribute flags:
Bit 0 - System partition
+ Bit 1 - Hide from EFI
+ Bit 2 - Legacy BIOS bootable
+ Bit 48-63 - Defined and used by the individual partition type
+ For Basic data partition :
Bit 60 - Read-only
Bit 62 - Hidden
Bit 63 - Not mount
The fields 'name' and 'size' are mandatory for every partition.
The field 'start' is optional.
+ If field 'size' of the last partition is 0, the partiton is extended
+ up to the end of the device.
+
The fields 'uuid' and 'uuid_disk' are optional if CONFIG_RANDOM_UUID is
enabled. A random uuid will be used if omitted or they point to an empty/
non-existent environment variable. The environment variable will be set to
the generated UUID.
+ The field 'bootable' is optional, it is used to mark the GPT partition
+ bootable (set attribute flags "Legacy BIOS bootable").
+ "name=u-boot,size=60MiB;name=boot,size=60Mib,bootable;name=rootfs,size=0"
+ It can be used to locate bootable disks with command
+ "part list <interface> <dev> -bootable <varname>",
+ please check out doc/README.distro for use.
+
2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT'
-2. From u-boot prompt type:
+3. From u-boot prompt type:
gpt write mmc 0 $partitions
+Checking (validating) GPT partitions in U-Boot:
+===============================================
+
+Procedure is the same as above. The only change is at point 3.
+
+At u-boot prompt one needs to write:
+ gpt verify mmc 0 [$partitions]
+
+where [$partitions] is an optional parameter.
+
+When it is not provided, only basic checks based on CRC32 calculation for GPT
+header and PTEs are performed.
+When provided, additionally partition data - name, size and starting
+offset (last two in LBA) - are compared with data defined in '$partitions'
+environment variable.
+
+After running this command, return code is set to 0 if no errors found in
+on non-volatile medium stored GPT.
+
+Following line can be used to assess if GPT verification has succeed:
+
+U-BOOT> gpt verify mmc 0 $partitions
+U-BOOT> if test $? = 0; then echo "GPT OK"; else echo "GPT ERR"; fi
+
+
Partition type GUID:
====================
--- /dev/null
+i8042 Keyboard
+
+The Intel i8042 is a keyboard controller used on many x86 PCs.
+
+Required properties:
+- compatible: "intel,i8042-keyboard"
+
+Optional properties:
+- intel,duplicate-por: Indicates that a keyboard reset may result in a
+ duplicate POR byte, which should be ignored.
--- /dev/null
+Sandbox timer
+
+The sandbox timer device is an emulated device which gets time from
+host os.
+
+Required properties:
+ compatible: "sandbox,timer"
--- /dev/null
+How to port a serial driver to driver model
+===========================================
+
+About 16 of 33 serial drivers have been converted as at September 2015. It
+is time for maintainers to start converting over the remaining serial drivers:
+
+ altera_jtag_uart.c
+ altera_uart.c
+ arm_dcc.c
+ lpc32xx_hsuart.c
+ mcfuart.c
+ mxs_auart.c
+ opencores_yanu.c
+ serial_bfin.c
+ serial_imx.c
+ serial_lpuart.c
+ serial_max3100.c
+ serial_pxa.c
+ serial_s3c24x0.c
+ serial_sa1100.c
+ serial_stm32.c
+ serial_xuartlite.c
+ usbtty.c
+
+You should complete this by the end of January 2016.
+
+Here is a suggested approach for converting your serial driver over to driver
+model. Please feel free to update this file with your ideas and suggestions.
+
+- #ifdef out all your own serial driver code (#ifndef CONFIG_DM_SERIAL)
+- Define CONFIG_DM_SERIAL for your board, vendor or architecture
+- If the board does not already use driver model, you need CONFIG_DM also
+- Your board should then build, but will not boot since there will be no serial
+ driver
+- Add the U_BOOT_DRIVER piece at the end (e.g. copy serial_s5p.c for example)
+- Add a private struct for the driver data - avoid using static variables
+- Implement each of the driver methods, perhaps by calling your old methods
+- You may need to adjust the function parameters so that the old and new
+ implementations can share most of the existing code
+- If you convert all existing users of the driver, remove the pre-driver-model
+ code
+
+In terms of patches a conversion series typically has these patches:
+- clean up / prepare the driver for conversion
+- add driver model code
+- convert at least one existing board to use driver model serial
+- (if no boards remain that don't use driver model) remove the old code
+
+This may be a good time to move your board to use device tree also. Mostly
+this involves these steps:
+
+- define CONFIG_OF_CONTROL and CONFIG_OF_SEPARATE
+- add your device tree files to arch/<arch>/dts
+- update the Makefile there
+- Add stdout-path to your /chosen device tree node if it is not already there
+- build and get u-boot-dtb.bin so you can test it
+- Your drivers can now use device tree
+- For device tree in SPL, define CONFIG_SPL_OF_CONTROL
#include <common.h>
#include <command.h>
+#include <console.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/fsl_serdes.h>
#include <dm/uclass-internal.h>
#include <dm/util.h>
-int device_unbind_children(struct udevice *dev)
+/**
+ * device_chld_unbind() - Unbind all device's children from the device
+ *
+ * On error, the function continues to unbind all children, and reports the
+ * first error.
+ *
+ * @dev: The device that is to be stripped of its children
+ * @return 0 on success, -ve on error
+ */
+static int device_chld_unbind(struct udevice *dev)
{
struct udevice *pos, *n;
int ret, saved_ret = 0;
return saved_ret;
}
-int device_remove_children(struct udevice *dev)
+/**
+ * device_chld_remove() - Stop all device's children
+ * @dev: The device whose children are to be removed
+ * @return 0 on success, -ve on error
+ */
+static int device_chld_remove(struct udevice *dev)
{
struct udevice *pos, *n;
int ret;
return ret;
}
- ret = device_unbind_children(dev);
+ ret = device_chld_unbind(dev);
if (ret)
return ret;
if (ret)
return ret;
- ret = device_remove_children(dev);
+ ret = device_chld_remove(dev);
if (ret)
goto err;
entry->unbind += gd->reloc_off;
if (entry->ofdata_to_platdata)
entry->ofdata_to_platdata += gd->reloc_off;
+ if (entry->child_post_bind)
+ entry->child_post_bind += gd->reloc_off;
if (entry->child_pre_probe)
entry->child_pre_probe += gd->reloc_off;
if (entry->child_post_remove)
entry->post_bind += gd->reloc_off;
if (entry->pre_unbind)
entry->pre_unbind += gd->reloc_off;
+ if (entry->pre_probe)
+ entry->pre_probe += gd->reloc_off;
if (entry->post_probe)
entry->post_probe += gd->reloc_off;
if (entry->pre_remove)
entry->pre_remove += gd->reloc_off;
+ if (entry->child_post_bind)
+ entry->child_post_bind += gd->reloc_off;
+ if (entry->child_pre_probe)
+ entry->child_pre_probe += gd->reloc_off;
if (entry->init)
entry->init += gd->reloc_off;
if (entry->destroy)
*/
#include <common.h> /* core U-Boot definitions */
+#include <console.h>
#include <ACEX1K.h> /* ACEX device family */
/* Define FPGA_DEBUG to get debug printf's */
*/
#include <common.h>
+#include <console.h>
#include <virtex2.h>
#if 0
*/
#include <common.h>
+#include <console.h>
#include <asm/io.h>
#include <fs.h>
#include <zynqpl.h>
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
-obj-y += muxes/
+obj-$(CONFIG_I2C_MUX) += muxes/
*/
#include <common.h>
+#include <console.h>
#include <i2c.h>
#include <asm/clock.h>
+config DM_KEYBOARD
+ bool "Enable driver model keyboard support"
+ depends on DM
+ help
+ This adds a uclass for keyboards and implements keyboard support
+ using driver model. The API is implemented by keyboard.h and
+ includes methods to start/stop the device, check for available
+ input and update LEDs if the keyboard has them.
+
config CROS_EC_KEYB
bool "Enable Chrome OS EC keyboard support"
help
Most ARM Chromebooks use an EC to provide access to the keyboard.
Messages are used to request key scans from the EC and these are
then decoded into keys by this driver.
+
+config I8042_KEYB
+ bool "Enable Intel i8042 keyboard support"
+ depends on DM_KEYBOARD
+ help
+ This adds a driver for the i8042 keyboard controller, allowing the
+ keyboard to be used on devices which support this controller. The
+ driver handles English and German keyboards - set the environment
+ variable 'keymap' to "de" to select German. Keyboard repeat is
+ handled by the keyboard itself.
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_I8042_KBD) += i8042.o
+obj-$(CONFIG_DM_KEYBOARD) += keyboard-uclass.o
+
+obj-$(CONFIG_I8042_KEYB) += i8042.o
obj-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o
obj-$(CONFIG_TWL4030_INPUT) += twl4030.o
obj-$(CONFIG_CROS_EC_KEYB) += cros_ec_keyb.o
#include <common.h>
#include <cros_ec.h>
+#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <input.h>
+#include <keyboard.h>
#include <key_matrix.h>
#include <stdio_dev.h>
KBC_REPEAT_DELAY_MS = 240,
};
-static struct keyb {
- struct cros_ec_dev *dev; /* The CROS_EC device */
- struct input_config input; /* The input layer */
+struct cros_ec_keyb_priv {
+ struct input_config *input; /* The input layer */
struct key_matrix matrix; /* The key matrix layer */
int key_rows; /* Number of keyboard rows */
int key_cols; /* Number of keyboard columns */
int ghost_filter; /* 1 to enable ghost filter, else 0 */
- int inited; /* 1 if keyboard is ready */
-} config;
+};
/**
* Check the keyboard controller and return a list of key matrix positions
* for which a key is pressed
*
- * @param config Keyboard config
+ * @param dev Keyboard device
* @param keys List of keys that we have detected
* @param max_count Maximum number of keys to return
* @param samep Set to true if this scan repeats the last, else false
* @return number of pressed keys, 0 for none, -EIO on error
*/
-static int check_for_keys(struct keyb *config,
- struct key_matrix_key *keys, int max_count,
- bool *samep)
+static int check_for_keys(struct udevice *dev, struct key_matrix_key *keys,
+ int max_count, bool *samep)
{
+ struct cros_ec_keyb_priv *priv = dev_get_priv(dev);
struct key_matrix_key *key;
static struct mbkp_keyscan last_scan;
static bool last_scan_valid;
unsigned int row, col, bit, data;
int num_keys;
- if (cros_ec_scan_keyboard(config->dev, &scan)) {
+ if (cros_ec_scan_keyboard(dev->parent, &scan)) {
debug("%s: keyboard scan failed\n", __func__);
return -EIO;
}
last_scan_valid = true;
memcpy(&last_scan, &scan, sizeof(last_scan));
- for (col = num_keys = bit = 0; col < config->matrix.num_cols;
+ for (col = num_keys = bit = 0; col < priv->matrix.num_cols;
col++) {
- for (row = 0; row < config->matrix.num_rows; row++) {
+ for (row = 0; row < priv->matrix.num_rows; row++) {
unsigned int mask = 1 << (bit & 7);
data = scan.data[bit / 8];
return num_keys;
}
-/**
- * Test if keys are available to be read
- *
- * @return 0 if no keys available, 1 if keys are available
- */
-static int kbd_tstc(struct stdio_dev *dev)
-{
- /* Just get input to do this for us */
- return config.inited ? input_tstc(&config.input) : 0;
-}
-
-/**
- * Read a key
- *
- * @return ASCII key code, or 0 if no key, or -1 if error
- */
-static int kbd_getc(struct stdio_dev *dev)
-{
- /* Just get input to do this for us */
- return config.inited ? input_getc(&config.input) : 0;
-}
-
/**
* Check the keyboard, and send any keys that are pressed.
*
*/
int cros_ec_kbc_check(struct input_config *input)
{
+ struct udevice *dev = input->dev;
+ struct cros_ec_keyb_priv *priv = dev_get_priv(dev);
static struct key_matrix_key last_keys[KBC_MAX_KEYS];
static int last_num_keys;
struct key_matrix_key keys[KBC_MAX_KEYS];
* may return 0 before all keys have been read from the EC.
*/
do {
- irq_pending = cros_ec_interrupt_pending(config.dev);
+ irq_pending = cros_ec_interrupt_pending(dev->parent);
if (irq_pending) {
- num_keys = check_for_keys(&config, keys, KBC_MAX_KEYS,
+ num_keys = check_for_keys(dev, keys, KBC_MAX_KEYS,
&same);
if (num_keys < 0)
return 0;
if (num_keys < 0)
return -1;
- num_keycodes = key_matrix_decode(&config.matrix, keys,
+ num_keycodes = key_matrix_decode(&priv->matrix, keys,
num_keys, keycodes, KBC_MAX_KEYS);
sent = input_send_keycodes(input, keycodes, num_keycodes);
* @return 0 if ok, -1 on error
*/
static int cros_ec_keyb_decode_fdt(const void *blob, int node,
- struct keyb *config)
+ struct cros_ec_keyb_priv *config)
{
/*
* Get keyboard rows and columns - at present we are limited to
return 0;
}
-/**
- * Set up the keyboard. This is called by the stdio device handler.
- *
- * We want to do this init when the keyboard is actually used rather than
- * at start-up, since keyboard input may not currently be selected.
- *
- * @return 0 if ok, -1 on error
- */
-static int cros_ec_init_keyboard(struct stdio_dev *dev)
+static int cros_ec_kbd_probe(struct udevice *dev)
{
+ struct cros_ec_keyb_priv *priv = dev_get_priv(dev);
+ struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct stdio_dev *sdev = &uc_priv->sdev;
+ struct input_config *input = &uc_priv->input;
const void *blob = gd->fdt_blob;
- int node;
+ int node = dev->of_offset;
+ int ret;
- config.dev = board_get_cros_ec_dev();
- if (!config.dev) {
- debug("%s: no cros_ec device: cannot init keyboard\n",
- __func__);
+ if (cros_ec_keyb_decode_fdt(blob, node, priv))
return -1;
- }
- node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB);
- if (node < 0) {
- debug("%s: Node not found\n", __func__);
- return -1;
- }
- if (cros_ec_keyb_decode_fdt(blob, node, &config))
- return -1;
- input_set_delays(&config.input, KBC_REPEAT_DELAY_MS,
- KBC_REPEAT_RATE_MS);
- if (key_matrix_init(&config.matrix, config.key_rows,
- config.key_cols, config.ghost_filter)) {
+ input_set_delays(input, KBC_REPEAT_DELAY_MS, KBC_REPEAT_RATE_MS);
+ ret = key_matrix_init(&priv->matrix, priv->key_rows, priv->key_cols,
+ priv->ghost_filter);
+ if (ret) {
debug("%s: cannot init key matrix\n", __func__);
- return -1;
+ return ret;
}
- if (key_matrix_decode_fdt(&config.matrix, gd->fdt_blob, node)) {
+ ret = key_matrix_decode_fdt(&priv->matrix, gd->fdt_blob, node);
+ if (ret) {
debug("%s: Could not decode key matrix from fdt\n", __func__);
- return -1;
+ return ret;
}
- config.inited = 1;
- debug("%s: Matrix keyboard %dx%d ready\n", __func__, config.key_rows,
- config.key_cols);
+ debug("%s: Matrix keyboard %dx%d ready\n", __func__, priv->key_rows,
+ priv->key_cols);
- return 0;
-}
+ priv->input = input;
+ input->dev = dev;
+ input_add_tables(input, false);
+ input->read_keys = cros_ec_kbc_check;
+ strcpy(sdev->name, "cros-ec-keyb");
-int drv_keyboard_init(void)
-{
- struct stdio_dev dev;
+ /* Register the device. cros_ec_init_keyboard() will be called soon */
+ return input_stdio_register(sdev);
+}
- if (input_init(&config.input, 0)) {
- debug("%s: Cannot set up input\n", __func__);
- return -1;
- }
- config.input.read_keys = cros_ec_kbc_check;
+static const struct keyboard_ops cros_ec_kbd_ops = {
+};
- memset(&dev, '\0', sizeof(dev));
- strcpy(dev.name, "cros-ec-keyb");
- dev.flags = DEV_FLAGS_INPUT;
- dev.getc = kbd_getc;
- dev.tstc = kbd_tstc;
- dev.start = cros_ec_init_keyboard;
+static const struct udevice_id cros_ec_kbd_ids[] = {
+ { .compatible = "google,cros-ec-keyb" },
+ { }
+};
- /* Register the device. cros_ec_init_keyboard() will be called soon */
- return input_stdio_register(&dev);
-}
+U_BOOT_DRIVER(cros_ec_kbd) = {
+ .name = "cros_ec_kbd",
+ .id = UCLASS_KEYBOARD,
+ .of_match = cros_ec_kbd_ids,
+ .probe = cros_ec_kbd_probe,
+ .ops = &cros_ec_kbd_ops,
+ .priv_auto_alloc_size = sizeof(struct cros_ec_keyb_priv),
+};
/* i8042.c - Intel 8042 keyboard driver routines */
-/* includes */
-
#include <common.h>
-#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
#include <i8042.h>
+#include <input.h>
+#include <keyboard.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
/* defines */
#define in8(p) inb(p)
#define out8(p, v) outb(v, p)
-#ifdef CONFIG_CONSOLE_CURSOR
-extern void console_cursor(int state);
-static int blink_count = CONFIG_SYS_CONSOLE_BLINK_COUNT;
-static int cursor_state;
-#endif
+enum {
+ QUIRK_DUP_POR = 1 << 0,
+};
/* locals */
-
-static int kbd_input = -1; /* no input yet */
-static int kbd_mapping = KBD_US; /* default US keyboard */
-static int kbd_flags = NORMAL; /* after reset */
-static int kbd_state; /* unshift code */
-
-static unsigned char kbd_fct_map[144] = {
- /* kbd_fct_map table for scan code */
- 0, AS, AS, AS, AS, AS, AS, AS, /* scan 00-07 */
- AS, AS, AS, AS, AS, AS, AS, AS, /* scan 08-0F */
- AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */
- AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */
- AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */
- AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */
- AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */
- AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */
- ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */
- ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */
- 0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */
- AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */
- AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */
- };
-
-static unsigned char kbd_key_map[2][5][144] = {
- { /* US keyboard */
- { /* unshift code */
- 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 00-07 */
- '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 08-0F */
- 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
- 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
- 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
- '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
- 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
- '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
- '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* shift code */
- 0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 00-07 */
- '&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 08-0F */
- 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */
- 'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */
- 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */
- '"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */
- 'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
- '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
- '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* control code */
- 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 00-07 */
- 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 08-0F */
- 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
- 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
- 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
- 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
- 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
- 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
- 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
- },
- { /* non numeric code */
- 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 00-07 */
- '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 08-0F */
- 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
- 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
- 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
- '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
- 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
- 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
- 'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* right alt mode - not used in US keyboard */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 00-07 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 08-0F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10-17 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18-1F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20-27 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28-2F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30-37 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40-47 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
- }
- },
- { /* German keyboard */
- { /* unshift code */
- 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 00-07 */
- '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 08-0F */
- 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
- 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
- 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
- 0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */
- 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
- '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
- '2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* shift code */
- 0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 00-07 */
- '/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 08-0F */
- 'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */
- 'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */
- 'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */
- 0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */
- 'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
- '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
- '2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* control code */
- 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 00-07 */
- 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 08-0F */
- 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
- 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
- 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
- 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
- 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
- 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
- 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
- },
- { /* non numeric code */
- 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 00-07 */
- '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 08-0F */
- 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
- 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
- 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
- 0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */
- 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
- ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
- 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
- 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
- 'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
- 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
- '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
- 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
- },
- { /* right alt mode - is used in German keyboard */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 00-07 */
- '{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 08-0F */
- '@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10-17 */
- 0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18-1F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20-27 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28-2F */
- 0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30-37 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40-47 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50-57 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
- }
- }
- };
+struct i8042_kbd_priv {
+ bool extended; /* true if an extended keycode is expected next */
+ int quirks; /* quirks that we support */
+};
static unsigned char ext_key_map[] = {
0x1c, /* keypad enter */
return kbd_timeout != -1;
}
-static void kbd_led_set(void)
+/**
+ * check_leds() - Check the keyboard LEDs and update them it needed
+ *
+ * @ret: Value to return
+ * @return value of @ret
+ */
+static int i8042_kbd_update_leds(struct udevice *dev, int leds)
{
kbd_input_empty();
out8(I8042_DATA_REG, CMD_SET_KBD_LED);
kbd_input_empty();
- out8(I8042_DATA_REG, (kbd_flags & 0x7));
-}
-
-static void kbd_normal(unsigned char scan_code)
-{
- unsigned char chr;
+ out8(I8042_DATA_REG, leds & 0x7);
- if ((kbd_flags & BRK) == NORMAL) {
- chr = kbd_key_map[kbd_mapping][kbd_state][scan_code];
- if ((chr == 0xff) || (chr == 0x00))
- return;
-
- /* if caps lock convert upper to lower */
- if (((kbd_flags & CAPS) == CAPS) &&
- (chr >= 'a' && chr <= 'z')) {
- chr -= 'a' - 'A';
- }
- kbd_input = chr;
- }
+ return 0;
}
-static void kbd_shift(unsigned char scan_code)
+static int kbd_write(int reg, int value)
{
- if ((kbd_flags & BRK) == BRK) {
- kbd_state = AS;
- kbd_flags &= (~SHIFT);
- } else {
- kbd_state = SH;
- kbd_flags |= SHIFT;
- }
-}
+ if (!kbd_input_empty())
+ return -1;
+ out8(reg, value);
-static void kbd_ctrl(unsigned char scan_code)
-{
- if ((kbd_flags & BRK) == BRK) {
- kbd_state = AS;
- kbd_flags &= (~CTRL);
- } else {
- kbd_state = CN;
- kbd_flags |= CTRL;
- }
+ return 0;
}
-static void kbd_num(unsigned char scan_code)
+static int kbd_read(int reg)
{
- if ((kbd_flags & BRK) == NORMAL) {
- kbd_flags ^= NUM;
- kbd_state = (kbd_flags & NUM) ? AS : NM;
- kbd_led_set();
- }
-}
+ if (!kbd_output_full())
+ return -1;
-static void kbd_alt(unsigned char scan_code)
-{
- if ((kbd_flags & BRK) == BRK) {
- kbd_state = AS;
- kbd_flags &= (~ALT);
- } else {
- kbd_state = AK;
- kbd_flags &= ALT;
- }
+ return in8(reg);
}
-static void kbd_caps(unsigned char scan_code)
+static int kbd_cmd_read(int cmd)
{
- if ((kbd_flags & BRK) == NORMAL) {
- kbd_flags ^= CAPS;
- kbd_led_set();
- }
-}
+ if (kbd_write(I8042_CMD_REG, cmd))
+ return -1;
-static void kbd_scroll(unsigned char scan_code)
-{
- if ((kbd_flags & BRK) == NORMAL) {
- kbd_flags ^= STP;
- kbd_led_set();
- if (kbd_flags & STP)
- kbd_input = 0x13;
- else
- kbd_input = 0x11;
- }
+ return kbd_read(I8042_DATA_REG);
}
-static void kbd_conv_char(unsigned char scan_code)
+static int kbd_cmd_write(int cmd, int data)
{
- if (scan_code == 0xe0) {
- kbd_flags |= EXT;
- return;
- }
-
- /* if high bit of scan_code, set break flag */
- if (scan_code & 0x80)
- kbd_flags |= BRK;
- else
- kbd_flags &= ~BRK;
-
- if ((scan_code == 0xe1) || (kbd_flags & E1)) {
- if (scan_code == 0xe1) {
- kbd_flags ^= BRK; /* reset the break flag */
- kbd_flags ^= E1; /* bitwise EXOR with E1 flag */
- }
- return;
- }
-
- scan_code &= 0x7f;
-
- if (kbd_flags & EXT) {
- int i;
-
- kbd_flags ^= EXT;
- for (i = 0; ext_key_map[i]; i++) {
- if (ext_key_map[i] == scan_code) {
- scan_code = 0x80 + i;
- break;
- }
- }
- /* not found ? */
- if (!ext_key_map[i])
- return;
- }
-
- switch (kbd_fct_map[scan_code]) {
- case AS:
- kbd_normal(scan_code);
- break;
- case SH:
- kbd_shift(scan_code);
- break;
- case CN:
- kbd_ctrl(scan_code);
- break;
- case NM:
- kbd_num(scan_code);
- break;
- case AK:
- kbd_alt(scan_code);
- break;
- case CP:
- kbd_caps(scan_code);
- break;
- case ST:
- kbd_scroll(scan_code);
- break;
- }
+ if (kbd_write(I8042_CMD_REG, cmd))
+ return -1;
- return;
+ return kbd_write(I8042_DATA_REG, data);
}
-static int kbd_reset(void)
+static int kbd_reset(int quirk)
{
- u8 config;
+ int config;
/* controller self test */
- if (kbd_input_empty() == 0)
- return -1;
- out8(I8042_CMD_REG, CMD_SELF_TEST);
- if (kbd_output_full() == 0)
- return -1;
- if (in8(I8042_DATA_REG) != KBC_TEST_OK)
- return -1;
+ if (kbd_cmd_read(CMD_SELF_TEST) != KBC_TEST_OK)
+ goto err;
/* keyboard reset */
- if (kbd_input_empty() == 0)
- return -1;
- out8(I8042_DATA_REG, CMD_RESET_KBD);
- if (kbd_output_full() == 0)
- return -1;
- if (in8(I8042_DATA_REG) != KBD_ACK)
- return -1;
- if (kbd_output_full() == 0)
- return -1;
- if (in8(I8042_DATA_REG) != KBD_POR)
- return -1;
+ if (kbd_write(I8042_DATA_REG, CMD_RESET_KBD) ||
+ kbd_read(I8042_DATA_REG) != KBD_ACK ||
+ kbd_read(I8042_DATA_REG) != KBD_POR)
+ goto err;
/* set AT translation and disable irq */
- if (kbd_input_empty() == 0)
- return -1;
- out8(I8042_CMD_REG, CMD_RD_CONFIG);
- if (kbd_output_full() == 0)
- return -1;
- config = in8(I8042_DATA_REG);
+ config = kbd_cmd_read(CMD_RD_CONFIG);
+ if (config == -1)
+ goto err;
+
+ /* Sometimes get a second byte */
+ else if ((quirk & QUIRK_DUP_POR) && config == KBD_POR)
+ config = kbd_cmd_read(CMD_RD_CONFIG);
+
config |= CONFIG_AT_TRANS;
config &= ~(CONFIG_KIRQ_EN | CONFIG_MIRQ_EN);
- if (kbd_input_empty() == 0)
- return -1;
- out8(I8042_CMD_REG, CMD_WR_CONFIG);
- if (kbd_input_empty() == 0)
- return -1;
- out8(I8042_DATA_REG, config);
+ if (kbd_cmd_write(CMD_WR_CONFIG, config))
+ goto err;
/* enable keyboard */
- if (kbd_input_empty() == 0)
- return -1;
- out8(I8042_CMD_REG, CMD_KBD_EN);
- if (kbd_input_empty() == 0)
- return -1;
+ if (kbd_write(I8042_CMD_REG, CMD_KBD_EN) ||
+ !kbd_input_empty())
+ goto err;
return 0;
+err:
+ debug("%s: Keyboard failure\n", __func__);
+ return -1;
}
static int kbd_controller_present(void)
/*
* Implement a weak default function for boards that optionally
* need to skip the i8042 initialization.
+ *
+ * TODO(sjg@chromium.org): Use device tree for this?
*/
int __weak board_i8042_skip(void)
{
return 0;
}
+static int i8042_kbd_check(struct input_config *input)
+{
+ struct i8042_kbd_priv *priv = dev_get_priv(input->dev);
+
+ if ((in8(I8042_STS_REG) & STATUS_OBF) == 0) {
+ return 0;
+ } else {
+ bool release = false;
+ int scan_code;
+ int i;
+
+ scan_code = in8(I8042_DATA_REG);
+ if (scan_code == 0xfa) {
+ return 0;
+ } else if (scan_code == 0xe0) {
+ priv->extended = true;
+ return 0;
+ }
+ if (scan_code & 0x80) {
+ scan_code &= 0x7f;
+ release = true;
+ }
+ if (priv->extended) {
+ priv->extended = false;
+ for (i = 0; ext_key_map[i]; i++) {
+ if (ext_key_map[i] == scan_code) {
+ scan_code = 0x60 + i;
+ break;
+ }
+ }
+ /* not found ? */
+ if (!ext_key_map[i])
+ return 0;
+ }
+
+ input_add_keycode(input, scan_code, release);
+ return 1;
+ }
+}
+
/* i8042_kbd_init - reset keyboard and init state flags */
-int i8042_kbd_init(void)
+static int i8042_start(struct udevice *dev)
{
+ struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct i8042_kbd_priv *priv = dev_get_priv(dev);
+ struct input_config *input = &uc_priv->input;
int keymap, try;
char *penv;
+ int ret;
if (!kbd_controller_present() || board_i8042_skip()) {
debug("i8042 keyboard controller is not present\n");
- return -1;
+ return -ENOENT;
}
/* Init keyboard device (default US layout) */
keymap = KBD_GER;
}
- for (try = 0; try < KBD_RESET_TRIES; try++) {
- if (kbd_reset() == 0) {
- kbd_mapping = keymap;
- kbd_flags = NORMAL;
- kbd_state = 0;
- kbd_led_set();
-
- return 0;
- }
+ for (try = 0; kbd_reset(priv->quirks) != 0; try++) {
+ if (try >= KBD_RESET_TRIES)
+ return -1;
}
- return -1;
-}
+ ret = input_add_tables(input, keymap == KBD_GER);
+ if (ret)
+ return ret;
-/*
- * i8042_tstc - test if keyboard input is available
- *
- * option: cursor blinking if called in a loop
- */
-int i8042_tstc(struct stdio_dev *dev)
-{
- unsigned char scan_code = 0;
-
-#ifdef CONFIG_CONSOLE_CURSOR
- if (--blink_count == 0) {
- cursor_state ^= 1;
- console_cursor(cursor_state);
- blink_count = CONFIG_SYS_CONSOLE_BLINK_COUNT;
- udelay(10);
- }
-#endif
-
- if ((in8(I8042_STS_REG) & STATUS_OBF) == 0) {
- return 0;
- } else {
- scan_code = in8(I8042_DATA_REG);
- if (scan_code == 0xfa)
- return 0;
-
- kbd_conv_char(scan_code);
-
- if (kbd_input != -1)
- return 1;
- }
+ i8042_kbd_update_leds(dev, NORMAL);
+ debug("%s: started\n", __func__);
return 0;
}
-/*
- * i8042_getc - wait till keyboard input is available
+/**
+ * Set up the i8042 keyboard. This is called by the stdio device handler
*
- * option: turn on/off cursor while waiting
+ * We want to do this init when the keyboard is actually used rather than
+ * at start-up, since keyboard input may not currently be selected.
+ *
+ * Once the keyboard starts there will be a period during which we must
+ * wait for the keyboard to init. We do this only when a key is first
+ * read - see kbd_wait_for_fifo_init().
+ *
+ * @return 0 if ok, -ve on error
*/
-int i8042_getc(struct stdio_dev *dev)
+static int i8042_kbd_probe(struct udevice *dev)
{
- int ret_chr;
- unsigned char scan_code;
-
- while (kbd_input == -1) {
- while ((in8(I8042_STS_REG) & STATUS_OBF) == 0) {
-#ifdef CONFIG_CONSOLE_CURSOR
- if (--blink_count == 0) {
- cursor_state ^= 1;
- console_cursor(cursor_state);
- blink_count = CONFIG_SYS_CONSOLE_BLINK_COUNT;
- }
- udelay(10);
-#endif
- }
- scan_code = in8(I8042_DATA_REG);
- if (scan_code != 0xfa)
- kbd_conv_char(scan_code);
+ struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct i8042_kbd_priv *priv = dev_get_priv(dev);
+ struct stdio_dev *sdev = &uc_priv->sdev;
+ struct input_config *input = &uc_priv->input;
+ int ret;
+
+ if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ "intel,duplicate-por"))
+ priv->quirks |= QUIRK_DUP_POR;
+
+ /* Register the device. i8042_start() will be called soon */
+ input->dev = dev;
+ input->read_keys = i8042_kbd_check;
+ input_allow_repeats(input, true);
+ strcpy(sdev->name, "i8042-kbd");
+ ret = input_stdio_register(sdev);
+ if (ret) {
+ debug("%s: input_stdio_register() failed\n", __func__);
+ return ret;
}
- ret_chr = kbd_input;
- kbd_input = -1;
+ debug("%s: ready\n", __func__);
- return ret_chr;
+ return 0;
}
+
+static const struct keyboard_ops i8042_kbd_ops = {
+ .start = i8042_start,
+ .update_leds = i8042_kbd_update_leds,
+};
+
+static const struct udevice_id i8042_kbd_ids[] = {
+ { .compatible = "intel,i8042-keyboard" },
+ { }
+};
+
+U_BOOT_DRIVER(i8042_kbd) = {
+ .name = "i8042_kbd",
+ .id = UCLASS_KEYBOARD,
+ .of_match = i8042_kbd_ids,
+ .probe = i8042_kbd_probe,
+ .ops = &i8042_kbd_ops,
+ .priv_auto_alloc_size = sizeof(struct i8042_kbd_priv),
+};
*/
#include <common.h>
+#include <console.h>
+#include <dm.h>
+#include <errno.h>
#include <stdio_dev.h>
#include <input.h>
+#ifdef CONFIG_DM_KEYBOARD
+#include <keyboard.h>
+#endif
#include <linux/input.h>
enum {
/* These correspond to the lights on the keyboard */
- FLAG_NUM_LOCK = 1 << 0,
- FLAG_CAPS_LOCK = 1 << 1,
- FLAG_SCROLL_LOCK = 1 << 2,
+ FLAG_SCROLL_LOCK = 1 << 0,
+ FLAG_NUM_LOCK = 1 << 1,
+ FLAG_CAPS_LOCK = 1 << 2,
/* Special flag ORed with key code to indicate release */
KEY_RELEASE = 1 << 15,
'8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
'2', '3', '0', '.', 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x50 - 0x5F */
- '\r', 0xff, 0xff
+ '\r', 0xff, '/', '*',
};
static unsigned char kbd_shift_xlate[] = {
'8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
'2', '3', '0', '.', 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x50 - 0x5F */
- '\r', 0xff, 0xff
+ '\r', 0xff, '/', '*',
};
static unsigned char kbd_ctrl_xlate[] = {
0xff, 0x1b, '1', 0x00, '3', '4', '5', 0x1E,
'7', '8', '9', '0', 0x1F, '=', '\b', '\t', /* 0x00 - 0x0f */
- 0x11, 0x17, 0x05, 0x12, 0x14, 0x18, 0x15, 0x09,
+ 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09,
0x0f, 0x10, 0x1b, 0x1d, '\n', 0xff, 0x01, 0x13, /* 0x10 - 0x1f */
0x04, 0x06, 0x08, 0x09, 0x0a, 0x0b, 0x0c, ';',
'\'', '~', 0x00, 0x1c, 0x1a, 0x18, 0x03, 0x16, /* 0x20 - 0x2f */
'8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
'2', '3', '0', '.', 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x50 - 0x5F */
- '\r', 0xff, 0xff
+ '\r', 0xff, '/', '*',
+};
+
+static const uchar kbd_plain_xlate_german[] = {
+ 0xff, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 00-07 */
+ '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 08-0F */
+ 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
+ 'o', 'p', 0x81, '+', '\r', 0xff, 'a', 's', /* scan 18-1F */
+ 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
+ 0x84, '^', 0xff, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */
+ 'b', 'n', 'm', ',', '.', '-', 0xff, '*', /* scan 30-37 */
+ ' ', ' ', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '7', /* scan 40-47 */
+ '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
+ '2', '3', '0', ',', 0xff, 0xff, '<', 0xff, /* scan 50-57 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
+ '\r', 0xff, '/', '*',
+};
+
+static unsigned char kbd_shift_xlate_german[] = {
+ 0xff, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 00-07 */
+ '/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 08-0F */
+ 'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */
+ 'O', 'P', 0x9a, '*', '\r', 0xff, 'A', 'S', /* scan 18-1F */
+ 'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */
+ 0x8e, 0xf8, 0xff, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */
+ 'B', 'N', 'M', ';', ':', '_', 0xff, '*', /* scan 30-37 */
+ ' ', ' ', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '7', /* scan 40-47 */
+ '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
+ '2', '3', '0', ',', 0xff, 0xff, '>', 0xff, /* scan 50-57 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
+ '\r', 0xff, '/', '*',
+};
+
+static unsigned char kbd_right_alt_xlate_german[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 00-07 */
+ '{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 08-0F */
+ '@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10-17 */
+ 0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18-1F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20-27 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28-2F */
+ 0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30-37 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40-47 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50-57 */
+};
+
+enum kbd_mask {
+ KBD_ENGLISH = 1 << 0,
+ KBD_GERMAN = 1 << 1,
+};
+
+static struct kbd_entry {
+ int kbd_mask; /* Which languages this is for */
+ int left_keycode; /* Left keycode to select this map */
+ int right_keycode; /* Right keycode to select this map */
+ const uchar *xlate; /* Ascii code for each keycode */
+ int num_entries; /* Number of entries in xlate */
+} kbd_entry[] = {
+ { KBD_ENGLISH, -1, -1,
+ kbd_plain_xlate, ARRAY_SIZE(kbd_plain_xlate) },
+ { KBD_GERMAN, -1, -1,
+ kbd_plain_xlate_german, ARRAY_SIZE(kbd_plain_xlate_german) },
+ { KBD_ENGLISH, KEY_LEFTSHIFT, KEY_RIGHTSHIFT,
+ kbd_shift_xlate, ARRAY_SIZE(kbd_shift_xlate) },
+ { KBD_GERMAN, KEY_LEFTSHIFT, KEY_RIGHTSHIFT,
+ kbd_shift_xlate_german, ARRAY_SIZE(kbd_shift_xlate_german) },
+ { KBD_ENGLISH | KBD_GERMAN, KEY_LEFTCTRL, KEY_RIGHTCTRL,
+ kbd_ctrl_xlate, ARRAY_SIZE(kbd_ctrl_xlate) },
+ { KBD_GERMAN, -1, KEY_RIGHTALT,
+ kbd_right_alt_xlate_german,
+ ARRAY_SIZE(kbd_right_alt_xlate_german) },
+ {},
};
/*
return -1; /* buffer full */
config->fifo_in++;
}
+ debug(" {%02x} ", ch);
config->fifo[config->fifo_in] = (uchar)ch;
return 0;
static struct input_key_xlate *process_modifier(struct input_config *config,
int key, int release)
{
+#ifdef CONFIG_DM_KEYBOARD
+ struct udevice *dev = config->dev;
+ struct keyboard_ops *ops = keyboard_get_ops(dev);
+#endif
struct input_key_xlate *table;
- int flip = -1;
int i;
/* Start with the main table, and see what modifiers change it */
/* Handle the lighted keys */
if (!release) {
+ int flip = -1;
+
switch (key) {
case KEY_SCROLLLOCK:
flip = FLAG_SCROLL_LOCK;
flip = FLAG_CAPS_LOCK;
break;
}
- }
- if (flip != -1) {
- int leds = 0;
-
- config->leds ^= flip;
- if (config->flags & FLAG_NUM_LOCK)
- leds |= INPUT_LED_NUM;
- if (config->flags & FLAG_CAPS_LOCK)
- leds |= INPUT_LED_CAPS;
- if (config->flags & FLAG_SCROLL_LOCK)
- leds |= INPUT_LED_SCROLL;
- config->leds = leds;
+ if (flip != -1) {
+ int leds = 0;
+
+ config->flags ^= flip;
+ if (config->flags & FLAG_NUM_LOCK)
+ leds |= INPUT_LED_NUM;
+ if (config->flags & FLAG_CAPS_LOCK)
+ leds |= INPUT_LED_CAPS;
+ if (config->flags & FLAG_SCROLL_LOCK)
+ leds |= INPUT_LED_SCROLL;
+ config->leds = leds;
+ config->leds_changed = flip;
+
+#ifdef CONFIG_DM_KEYBOARD
+ if (ops->update_leds) {
+ if (ops->update_leds(dev, config->leds))
+ debug("Update keyboard's LED failed\n");
+ }
+#endif
+ }
}
return table;
/* Start conversion by looking for the first new keycode (by same). */
for (i = same; i < num_keycodes; i++) {
int key = keycode[i];
- int ch = (key < table->num_entries) ? table->xlate[key] : 0xff;
+ int ch;
/*
* For a normal key (with an ASCII value), add it; otherwise
* translate special key to escape sequence if possible.
*/
- if (ch != 0xff) {
- if (ch_count < max_chars)
- output_ch[ch_count] = (uchar)ch;
- ch_count++;
+ if (key < table->num_entries) {
+ ch = table->xlate[key];
+ if ((config->flags & FLAG_CAPS_LOCK) &&
+ ch >= 'a' && ch <= 'z')
+ ch -= 'a' - 'A';
+ /* ban digit numbers if 'Num Lock' is not on */
+ if (!(config->flags & FLAG_NUM_LOCK)) {
+ if (key >= KEY_KP7 && key <= KEY_KPDOT &&
+ key != KEY_KPMINUS && key != KEY_KPPLUS)
+ ch = 0xff;
+ }
+ if (ch_count < max_chars && ch != 0xff)
+ output_ch[ch_count++] = (uchar)ch;
} else {
ch_count += input_keycode_to_ansi364(config, key,
output_ch, max_chars);
return ch_count;
}
-int input_send_keycodes(struct input_config *config,
- int keycode[], int num_keycodes)
+static int _input_send_keycodes(struct input_config *config, int keycode[],
+ int num_keycodes, bool do_send)
{
char ch[num_keycodes * ANSI_CHAR_MAX];
int count, i, same = 0;
* insert another character if we later realise that we
* have missed a repeat slot.
*/
- is_repeat = config->repeat_rate_ms &&
- (int)get_timer(config->next_repeat_ms) >= 0;
+ is_repeat = config->allow_repeats || (config->repeat_rate_ms &&
+ (int)get_timer(config->next_repeat_ms) >= 0);
if (!is_repeat)
return 0;
}
count = input_keycodes_to_ascii(config, keycode, num_keycodes,
ch, sizeof(ch), is_repeat ? 0 : same);
- for (i = 0; i < count; i++)
- input_queue_ascii(config, ch[i]);
+ if (do_send) {
+ for (i = 0; i < count; i++)
+ input_queue_ascii(config, ch[i]);
+ }
delay_ms = is_repeat ?
config->repeat_rate_ms :
config->repeat_delay_ms;
return count;
}
+int input_send_keycodes(struct input_config *config, int keycode[],
+ int num_keycodes)
+{
+ return _input_send_keycodes(config, keycode, num_keycodes, true);
+}
+
+int input_add_keycode(struct input_config *config, int new_keycode,
+ bool release)
+{
+ int keycode[INPUT_MAX_MODIFIERS + 1];
+ int count, i;
+
+ /* Add the old keycodes which are not removed by this new one */
+ for (i = 0, count = 0; i < config->num_prev_keycodes; i++) {
+ int code = config->prev_keycodes[i];
+
+ if (new_keycode == code) {
+ if (release)
+ continue;
+ new_keycode = -1;
+ }
+ keycode[count++] = code;
+ }
+
+ if (!release && new_keycode != -1)
+ keycode[count++] = new_keycode;
+ debug("\ncodes for %02x/%d: ", new_keycode, release);
+ for (i = 0; i < count; i++)
+ debug("%02x ", keycode[i]);
+ debug("\n");
+
+ /* Don't output any ASCII characters if this is a key release */
+ return _input_send_keycodes(config, keycode, count, !release);
+}
+
int input_add_table(struct input_config *config, int left_keycode,
int right_keycode, const uchar *xlate, int num_entries)
{
config->repeat_rate_ms = repeat_rate_ms;
}
+void input_allow_repeats(struct input_config *config, bool allow_repeats)
+{
+ config->allow_repeats = allow_repeats;
+}
+
+int input_leds_changed(struct input_config *config)
+{
+ if (config->leds_changed)
+ return config->leds;
+
+ return -1;
+}
+
+int input_add_tables(struct input_config *config, bool german)
+{
+ struct kbd_entry *entry;
+ int mask;
+ int ret;
+
+ mask = german ? KBD_GERMAN : KBD_ENGLISH;
+ for (entry = kbd_entry; entry->kbd_mask; entry++) {
+ if (!(mask & entry->kbd_mask))
+ continue;
+ ret = input_add_table(config, entry->left_keycode,
+ entry->right_keycode, entry->xlate,
+ entry->num_entries);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
int input_init(struct input_config *config, int leds)
{
memset(config, '\0', sizeof(*config));
config->leds = leds;
- if (input_add_table(config, -1, -1,
- kbd_plain_xlate, ARRAY_SIZE(kbd_plain_xlate)) ||
- input_add_table(config, KEY_LEFTSHIFT, KEY_RIGHTSHIFT,
- kbd_shift_xlate, ARRAY_SIZE(kbd_shift_xlate)) ||
- input_add_table(config, KEY_LEFTCTRL, KEY_RIGHTCTRL,
- kbd_ctrl_xlate, ARRAY_SIZE(kbd_ctrl_xlate))) {
- debug("%s: Could not add modifier tables\n", __func__);
- return -1;
- }
return 0;
}
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <keyboard.h>
+
+static int keyboard_start(struct stdio_dev *sdev)
+{
+ struct udevice *dev = sdev->priv;
+ struct keyboard_ops *ops = keyboard_get_ops(dev);
+
+ if (ops->start)
+ return ops->start(dev);
+
+ return 0;
+}
+
+static int keyboard_stop(struct stdio_dev *sdev)
+{
+ struct udevice *dev = sdev->priv;
+ struct keyboard_ops *ops = keyboard_get_ops(dev);
+
+ if (ops->stop)
+ return ops->stop(dev);
+
+ return 0;
+}
+
+static int keyboard_tstc(struct stdio_dev *sdev)
+{
+ struct udevice *dev = sdev->priv;
+ struct keyboard_priv *priv = dev_get_uclass_priv(dev);
+ struct keyboard_ops *ops = keyboard_get_ops(dev);
+
+ /* Just get input to do this for us if we can */
+ if (priv->input.dev)
+ return input_tstc(&priv->input);
+ else if (ops->tstc)
+ return ops->tstc(dev);
+
+ return -ENOSYS;
+}
+
+static int keyboard_getc(struct stdio_dev *sdev)
+{
+ struct udevice *dev = sdev->priv;
+ struct keyboard_priv *priv = dev_get_uclass_priv(dev);
+ struct keyboard_ops *ops = keyboard_get_ops(dev);
+
+ /* Just get input to do this for us if we can */
+ if (priv->input.dev)
+ return input_getc(&priv->input);
+ else if (ops->getc)
+ return ops->getc(dev);
+
+ return -ENOSYS;
+}
+
+static int keyboard_pre_probe(struct udevice *dev)
+{
+ struct keyboard_priv *priv = dev_get_uclass_priv(dev);
+ struct stdio_dev *sdev = &priv->sdev;
+ int ret;
+
+ strlcpy(sdev->name, dev->name, sizeof(sdev->name));
+ sdev->flags = DEV_FLAGS_INPUT;
+ sdev->getc = keyboard_getc;
+ sdev->tstc = keyboard_tstc;
+ sdev->start = keyboard_start;
+ sdev->stop = keyboard_stop;
+ sdev->priv = dev;
+ ret = input_init(&priv->input, 0);
+ if (ret) {
+ debug("%s: Cannot set up input, ret=%d - please add DEBUG to drivers/input/input.c to figure out the cause\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+UCLASS_DRIVER(keyboard) = {
+ .id = UCLASS_KEYBOARD,
+ .name = "keyboard",
+ .pre_probe = keyboard_pre_probe,
+ .per_device_auto_alloc_size = sizeof(struct keyboard_priv),
+};
***********************************************************************/
#include <common.h>
+#include <console.h>
+#include <input.h>
#include <stdio_dev.h>
#include <keyboard.h>
+#include <stdio_dev.h>
-#undef KBG_DEBUG
-
-#ifdef KBG_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-
-#define DEVNAME "kbd"
-
-#define LED_SCR 0x01 /* scroll lock led */
-#define LED_CAP 0x04 /* caps lock led */
-#define LED_NUM 0x02 /* num lock led */
-
-#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
+static struct input_config config;
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
-int ps2ser_check(void);
+static int kbd_read_keys(struct input_config *config)
+{
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || \
+ defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+ /* no ISR is used, so received chars must be polled */
+ ps2ser_check();
#endif
-static volatile char kbd_buffer[KBD_BUFFER_LEN];
-static volatile int in_pointer = 0;
-static volatile int out_pointer = 0;
+ return 1;
+}
-static unsigned char leds = 0;
-static unsigned char num_lock = 0;
-static unsigned char caps_lock = 0;
-static unsigned char scroll_lock = 0;
-static unsigned char shift = 0;
-static unsigned char ctrl = 0;
-static unsigned char alt = 0;
-static unsigned char e0 = 0;
+static int check_leds(int ret)
+{
+ int leds;
-/******************************************************************
- * Queue handling
- ******************************************************************/
+ leds = input_leds_changed(&config);
+ if (leds >= 0)
+ pckbd_leds(leds);
-/* puts character in the queue and sets up the in and out pointer */
-static void kbd_put_queue(char data)
-{
- if((in_pointer+1)==KBD_BUFFER_LEN) {
- if(out_pointer==0) {
- return; /* buffer full */
- } else{
- in_pointer=0;
- }
- } else {
- if((in_pointer+1)==out_pointer)
- return; /* buffer full */
- in_pointer++;
- }
- kbd_buffer[in_pointer]=data;
- return;
+ return ret;
}
/* test if a character is in the queue */
static int kbd_testc(struct stdio_dev *dev)
{
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
- /* no ISR is used, so received chars must be polled */
- ps2ser_check();
-#endif
- if(in_pointer==out_pointer)
- return(0); /* no data */
- else
- return(1);
+ return check_leds(input_tstc(&config));
}
/* gets the character from the queue */
static int kbd_getc(struct stdio_dev *dev)
{
- char c;
- while(in_pointer==out_pointer) {
-#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
- /* no ISR is used, so received chars must be polled */
- ps2ser_check();
-#endif
- ;}
- if((out_pointer+1)==KBD_BUFFER_LEN)
- out_pointer=0;
- else
- out_pointer++;
- c=kbd_buffer[out_pointer];
- return (int)c;
-
+ return check_leds(input_getc(&config));
}
-/* Simple translation table for the keys */
-
-static unsigned char kbd_plain_xlate[] = {
- 0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */
- 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */
- 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */
- 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
- '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
- '\r',0xff,0xff
- };
-
-static unsigned char kbd_shift_xlate[] = {
- 0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */
- 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */
- 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */
- 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
- '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
- '\r',0xff,0xff
- };
-
-static unsigned char kbd_ctrl_xlate[] = {
- 0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */
- 0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */
- 0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */
- 0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
- 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
- '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
- '\r',0xff,0xff
- };
-
-
-void handle_scancode(unsigned char scancode)
+void handle_scancode(unsigned char scan_code)
{
- unsigned char keycode;
+ bool release = false;
- /* Convert scancode to keycode */
- PRINTF("scancode %x\n",scancode);
- if(scancode==0xe0) {
- e0=1; /* special charakters */
- return;
- }
- if(e0==1) {
- e0=0; /* delete flag */
- if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */
- ((scancode&0x7F)==0x1D)|| /* the right alt key */
- ((scancode&0x7F)==0x35)|| /* the right '/' key */
- ((scancode&0x7F)==0x1C) )) /* the right enter key */
- /* we swallow unknown e0 codes */
- return;
- }
- /* special cntrl keys */
- switch(scancode) {
- case 0x2A:
- case 0x36: /* shift pressed */
- shift=1;
- return; /* do nothing else */
- case 0xAA:
- case 0xB6: /* shift released */
- shift=0;
- return; /* do nothing else */
- case 0x38: /* alt pressed */
- alt=1;
- return; /* do nothing else */
- case 0xB8: /* alt released */
- alt=0;
- return; /* do nothing else */
- case 0x1d: /* ctrl pressed */
- ctrl=1;
- return; /* do nothing else */
- case 0x9d: /* ctrl released */
- ctrl=0;
- return; /* do nothing else */
- case 0x46: /* scrollock pressed */
- scroll_lock=~scroll_lock;
- if(scroll_lock==0)
- leds&=~LED_SCR; /* switch LED off */
- else
- leds|=LED_SCR; /* switch on LED */
- pckbd_leds(leds);
- return; /* do nothing else */
- case 0x3A: /* capslock pressed */
- caps_lock=~caps_lock;
- if(caps_lock==0)
- leds&=~LED_CAP; /* switch caps_lock off */
- else
- leds|=LED_CAP; /* switch on LED */
- pckbd_leds(leds);
- return;
- case 0x45: /* numlock pressed */
- num_lock=~num_lock;
- if(num_lock==0)
- leds&=~LED_NUM; /* switch LED off */
- else
- leds|=LED_NUM; /* switch on LED */
- pckbd_leds(leds);
- return;
- case 0xC6: /* scroll lock released */
- case 0xC5: /* num lock released */
- case 0xBA: /* caps lock released */
- return; /* just swallow */
- }
-#if 1
- if((scancode&0x80)==0x80) /* key released */
- return;
-#else
- if((scancode&0x80)==0x00) /* key pressed */
- return;
- scancode &= ~0x80;
-#endif
- /* now, decide which table we need */
- if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */
- PRINTF("unkown scancode %X\n",scancode);
- return; /* swallow it */
- }
- /* setup plain code first */
- keycode=kbd_plain_xlate[scancode];
- if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */
- if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
- PRINTF("unkown caps-locked scancode %X\n",scancode);
- return; /* swallow it */
- }
- keycode=kbd_shift_xlate[scancode];
- if(keycode<'A') { /* we only want the alphas capital */
- keycode=kbd_plain_xlate[scancode];
- }
- }
- if(shift==1) { /* shift overwrites caps_lock */
- if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
- PRINTF("unkown shifted scancode %X\n",scancode);
- return; /* swallow it */
- }
- keycode=kbd_shift_xlate[scancode];
- }
- if(ctrl==1) { /* ctrl overwrites caps_lock and shift */
- if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */
- PRINTF("unkown ctrl scancode %X\n",scancode);
- return; /* swallow it */
- }
- keycode=kbd_ctrl_xlate[scancode];
- }
- /* check if valid keycode */
- if(keycode==0xff) {
- PRINTF("unkown scancode %X\n",scancode);
- return; /* swallow unknown codes */
+ /* Compare with i8042_kbd_check() in i8042.c if some logic is missing */
+ if (scan_code & 0x80) {
+ scan_code &= 0x7f;
+ release = true;
}
- kbd_put_queue(keycode);
- PRINTF("%x\n",keycode);
+ input_add_keycode(&config, scan_code, release);
}
-/******************************************************************
- * Init
- ******************************************************************/
-
-#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-extern int overwrite_console (void);
-#define OVERWRITE_CONSOLE overwrite_console ()
-#else
-#define OVERWRITE_CONSOLE 0
-#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
-
+/* TODO: convert to driver model */
int kbd_init (void)
{
- int error;
- struct stdio_dev kbddev ;
- char *stdinname = getenv ("stdin");
+ struct stdio_dev kbddev;
+ struct input_config *input = &config;
if(kbd_init_hw()==-1)
return -1;
memset (&kbddev, 0, sizeof(kbddev));
- strcpy(kbddev.name, DEVNAME);
+ strcpy(kbddev.name, "kbd");
kbddev.flags = DEV_FLAGS_INPUT;
- kbddev.getc = kbd_getc ;
- kbddev.tstc = kbd_testc ;
+ kbddev.getc = kbd_getc;
+ kbddev.tstc = kbd_testc;
- error = stdio_register (&kbddev);
- if(error==0) {
- /* check if this is the standard input device */
- if(strcmp(stdinname,DEVNAME)==0) {
- /* reassign the console */
- if(OVERWRITE_CONSOLE) {
- return 1;
- }
- error=console_assign(stdin,DEVNAME);
- if(error==0)
- return 1;
- else
- return error;
- }
- return 1;
- }
- return error;
+ input_init(input, 0);
+ input->read_keys = kbd_read_keys;
+ input_add_tables(input, true);
+
+ return input_stdio_register(&kbddev);
}
*/
#include <common.h>
+#include <dm.h>
#include <fdtdec.h>
#include <input.h>
+#include <keyboard.h>
#include <key_matrix.h>
#include <stdio_dev.h>
#include <tegra-kbc.h>
};
/* keyboard controller config and state */
-static struct keyb {
- struct input_config input; /* The input layer */
+struct tegra_kbd_priv {
+ struct input_config *input; /* The input layer */
struct key_matrix matrix; /* The key matrix layer */
struct kbc_tegra *kbc; /* tegra keyboard controller */
unsigned char inited; /* 1 if keyboard has been inited */
unsigned char first_scan; /* 1 if this is our first key scan */
- unsigned char created; /* 1 if driver has been created */
/*
* After init we must wait a short time before polling the keyboard.
unsigned int start_time_ms; /* Time that we inited (in ms) */
unsigned int last_poll_ms; /* Time we should last polled */
unsigned int next_repeat_ms; /* Next time we repeat a key */
-} config;
+};
/**
* reads the keyboard fifo for current keypresses
*
- * @param config Keyboard config
+ * @param priv Keyboard private data
* @param fifo Place to put fifo results
* @param max_keycodes Maximum number of key codes to put in the fifo
* @return number of items put into fifo
*/
-static int tegra_kbc_find_keys(struct keyb *config, int *fifo,
+static int tegra_kbc_find_keys(struct tegra_kbd_priv *priv, int *fifo,
int max_keycodes)
{
struct key_matrix_key keys[KBC_MAX_KPENT], *key;
for (key = keys, i = 0; i < KBC_MAX_KPENT; i++, key++) {
/* Get next word */
if (!(i & 3))
- kp_ent = readl(&config->kbc->kp_ent[i / 4]);
+ kp_ent = readl(&priv->kbc->kp_ent[i / 4]);
key->valid = (kp_ent & KBC_KPENT_VALID) != 0;
key->row = (kp_ent >> 3) & 0xf;
/* Shift to get next entry */
kp_ent >>= 8;
}
- return key_matrix_decode(&config->matrix, keys, KBC_MAX_KPENT, fifo,
+ return key_matrix_decode(&priv->matrix, keys, KBC_MAX_KPENT, fifo,
max_keycodes);
}
* Note: if fifo_cnt is 0, we will tell the input layer that no keys are
* pressed.
*
- * @param config Keyboard config
+ * @param priv Keyboard private data
* @param fifo_cnt Number of entries in the keyboard fifo
*/
-static void process_fifo(struct keyb *config, int fifo_cnt)
+static void process_fifo(struct tegra_kbd_priv *priv, int fifo_cnt)
{
int fifo[KBC_MAX_KPENT];
int cnt = 0;
/* Always call input_send_keycodes() at least once */
do {
if (fifo_cnt)
- cnt = tegra_kbc_find_keys(config, fifo, KBC_MAX_KPENT);
+ cnt = tegra_kbc_find_keys(priv, fifo, KBC_MAX_KPENT);
- input_send_keycodes(&config->input, fifo, cnt);
+ input_send_keycodes(priv->input, fifo, cnt);
} while (--fifo_cnt > 0);
}
* Check the keyboard controller and emit ASCII characters for any keys that
* are pressed.
*
- * @param config Keyboard config
+ * @param priv Keyboard private data
*/
-static void check_for_keys(struct keyb *config)
+static void check_for_keys(struct tegra_kbd_priv *priv)
{
int fifo_cnt;
- if (!config->first_scan &&
- get_timer(config->last_poll_ms) < KBC_REPEAT_RATE_MS)
+ if (!priv->first_scan &&
+ get_timer(priv->last_poll_ms) < KBC_REPEAT_RATE_MS)
return;
- config->last_poll_ms = get_timer(0);
- config->first_scan = 0;
+ priv->last_poll_ms = get_timer(0);
+ priv->first_scan = 0;
/*
* Once we get here we know the keyboard has been scanned. So if there
* scan waiting for us, we know that nothing is held down.
*/
- fifo_cnt = (readl(&config->kbc->interrupt) >> 4) & 0xf;
- process_fifo(config, fifo_cnt);
+ fifo_cnt = (readl(&priv->kbc->interrupt) >> 4) & 0xf;
+ process_fifo(priv, fifo_cnt);
}
/**
* Wkup mode to Continous polling mode and the repoll time. We can
* deduct the time that's already elapsed.
*
- * @param config Keyboard config
+ * @param priv Keyboard private data
*/
-static void kbd_wait_for_fifo_init(struct keyb *config)
+static void kbd_wait_for_fifo_init(struct tegra_kbd_priv *priv)
{
- if (!config->inited) {
+ if (!priv->inited) {
unsigned long elapsed_time;
long delay_ms;
- elapsed_time = get_timer(config->start_time_ms);
- delay_ms = config->init_dly_ms - elapsed_time;
+ elapsed_time = get_timer(priv->start_time_ms);
+ delay_ms = priv->init_dly_ms - elapsed_time;
if (delay_ms > 0) {
udelay(delay_ms * 1000);
debug("%s: delay %ldms\n", __func__, delay_ms);
}
- config->inited = 1;
+ priv->inited = 1;
}
}
*/
static int tegra_kbc_check(struct input_config *input)
{
- kbd_wait_for_fifo_init(&config);
- check_for_keys(&config);
+ struct tegra_kbd_priv *priv = dev_get_priv(input->dev);
- return 1;
-}
+ kbd_wait_for_fifo_init(priv);
+ check_for_keys(priv);
-/**
- * Test if keys are available to be read
- *
- * @return 0 if no keys available, 1 if keys are available
- */
-static int kbd_tstc(struct stdio_dev *dev)
-{
- /* Just get input to do this for us */
- return input_tstc(&config.input);
-}
-
-/**
- * Read a key
- *
- * TODO: U-Boot wants 0 for no key, but Ctrl-@ is a valid key...
- *
- * @return ASCII key code, or 0 if no key, or -1 if error
- */
-static int kbd_getc(struct stdio_dev *dev)
-{
- /* Just get input to do this for us */
- return input_getc(&config.input);
+ return 1;
}
/* configures keyboard GPIO registers to use the rows and columns */
-static void config_kbc_gpio(struct kbc_tegra *kbc)
+static void config_kbc_gpio(struct tegra_kbd_priv *priv, struct kbc_tegra *kbc)
{
int i;
row_cfg &= ~r_mask;
col_cfg &= ~c_mask;
- if (i < config.matrix.num_rows) {
+ if (i < priv->matrix.num_rows) {
row_cfg |= ((i << 1) | 1) << r_shift;
} else {
- col_cfg |= (((i - config.matrix.num_rows) << 1) | 1)
+ col_cfg |= (((i - priv->matrix.num_rows) << 1) | 1)
<< c_shift;
}
/**
* Start up the keyboard device
*/
-static void tegra_kbc_open(void)
+static void tegra_kbc_open(struct tegra_kbd_priv *priv)
{
- struct kbc_tegra *kbc = config.kbc;
+ struct kbc_tegra *kbc = priv->kbc;
unsigned int scan_period;
u32 val;
* Before reading from the keyboard we must wait for the init_dly
* plus the rpt_delay, plus 2ms for the row scan time.
*/
- config.init_dly_ms = scan_period * 2 + 2;
+ priv->init_dly_ms = scan_period * 2 + 2;
val = KBC_DEBOUNCE_COUNT << KBC_DEBOUNCE_CNT_SHIFT;
val |= 1 << KBC_FIFO_TH_CNT_SHIFT; /* fifo interrupt threshold */
val |= KBC_CONTROL_KBC_EN; /* enable */
writel(val, &kbc->control);
- config.start_time_ms = get_timer(0);
- config.last_poll_ms = config.next_repeat_ms = get_timer(0);
- config.first_scan = 1;
+ priv->start_time_ms = get_timer(0);
+ priv->last_poll_ms = get_timer(0);
+ priv->next_repeat_ms = priv->last_poll_ms;
+ priv->first_scan = 1;
+}
+
+static int tegra_kbd_start(struct udevice *dev)
+{
+ struct tegra_kbd_priv *priv = dev_get_priv(dev);
+
+ /* Set up pin mux and enable the clock */
+ funcmux_select(PERIPH_ID_KBC, FUNCMUX_DEFAULT);
+ clock_enable(PERIPH_ID_KBC);
+ config_kbc_gpio(priv, priv->kbc);
+
+ tegra_kbc_open(priv);
+ debug("%s: Tegra keyboard ready\n", __func__);
+
+ return 0;
}
/**
*
* @return 0 if ok, -ve on error
*/
-static int init_tegra_keyboard(struct stdio_dev *dev)
+static int tegra_kbd_probe(struct udevice *dev)
{
- /* check if already created */
- if (config.created)
- return 0;
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
- int node;
-
- node = fdtdec_next_compatible(gd->fdt_blob, 0,
- COMPAT_NVIDIA_TEGRA20_KBC);
- if (node < 0) {
- debug("%s: cannot locate keyboard node\n", __func__);
- return node;
- }
- config.kbc = (struct kbc_tegra *)fdtdec_get_addr(gd->fdt_blob,
- node, "reg");
- if ((fdt_addr_t)config.kbc == FDT_ADDR_T_NONE) {
+ struct tegra_kbd_priv *priv = dev_get_priv(dev);
+ struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct stdio_dev *sdev = &uc_priv->sdev;
+ struct input_config *input = &uc_priv->input;
+ int node = dev->of_offset;
+ int ret;
+
+ priv->kbc = (struct kbc_tegra *)dev_get_addr(dev);
+ if ((fdt_addr_t)priv->kbc == FDT_ADDR_T_NONE) {
debug("%s: No keyboard register found\n", __func__);
- return -1;
+ return -EINVAL;
}
- input_set_delays(&config.input, KBC_REPEAT_DELAY_MS,
- KBC_REPEAT_RATE_MS);
+ input_set_delays(input, KBC_REPEAT_DELAY_MS, KBC_REPEAT_RATE_MS);
/* Decode the keyboard matrix information (16 rows, 8 columns) */
- if (key_matrix_init(&config.matrix, 16, 8, 1)) {
- debug("%s: Could not init key matrix\n", __func__);
- return -1;
+ ret = key_matrix_init(&priv->matrix, 16, 8, 1);
+ if (ret) {
+ debug("%s: Could not init key matrix: %d\n", __func__, ret);
+ return ret;
}
- if (key_matrix_decode_fdt(&config.matrix, gd->fdt_blob, node)) {
- debug("%s: Could not decode key matrix from fdt\n", __func__);
- return -1;
+ ret = key_matrix_decode_fdt(&priv->matrix, gd->fdt_blob, node);
+ if (ret) {
+ debug("%s: Could not decode key matrix from fdt: %d\n",
+ __func__, ret);
+ return ret;
}
- if (config.matrix.fn_keycode) {
- if (input_add_table(&config.input, KEY_FN, -1,
- config.matrix.fn_keycode,
- config.matrix.key_count))
- return -1;
+ if (priv->matrix.fn_keycode) {
+ ret = input_add_table(input, KEY_FN, -1,
+ priv->matrix.fn_keycode,
+ priv->matrix.key_count);
+ if (ret) {
+ debug("%s: input_add_table() failed\n", __func__);
+ return ret;
+ }
}
-#else
-#error "Tegra keyboard driver requires FDT definitions"
-#endif
- /* Set up pin mux and enable the clock */
- funcmux_select(PERIPH_ID_KBC, FUNCMUX_DEFAULT);
- clock_enable(PERIPH_ID_KBC);
- config_kbc_gpio(config.kbc);
-
- tegra_kbc_open();
- config.created = 1;
- debug("%s: Tegra keyboard ready\n", __func__);
+ /* Register the device. init_tegra_keyboard() will be called soon */
+ priv->input = input;
+ input->dev = dev;
+ input->read_keys = tegra_kbc_check;
+ input_add_tables(input, false);
+ strcpy(sdev->name, "tegra-kbc");
+ ret = input_stdio_register(sdev);
+ if (ret) {
+ debug("%s: input_stdio_register() failed\n", __func__);
+ return ret;
+ }
return 0;
}
-int drv_keyboard_init(void)
-{
- struct stdio_dev dev;
- char *stdinname = getenv("stdin");
- int error;
-
- if (input_init(&config.input, 0)) {
- debug("%s: Cannot set up input\n", __func__);
- return -1;
- }
- config.input.read_keys = tegra_kbc_check;
+static const struct keyboard_ops tegra_kbd_ops = {
+ .start = tegra_kbd_start,
+};
- memset(&dev, '\0', sizeof(dev));
- strcpy(dev.name, "tegra-kbc");
- dev.flags = DEV_FLAGS_INPUT;
- dev.getc = kbd_getc;
- dev.tstc = kbd_tstc;
- dev.start = init_tegra_keyboard;
+static const struct udevice_id tegra_kbd_ids[] = {
+ { .compatible = "nvidia,tegra20-kbc" },
+ { }
+};
- /* Register the device. init_tegra_keyboard() will be called soon */
- error = input_stdio_register(&dev);
- if (error)
- return error;
-#ifdef CONFIG_CONSOLE_MUX
- error = iomux_doenv(stdin, stdinname);
- if (error)
- return error;
-#endif
- return 0;
-}
+U_BOOT_DRIVER(tegra_kbd) = {
+ .name = "tegra_kbd",
+ .id = UCLASS_KEYBOARD,
+ .of_match = tegra_kbd_ids,
+ .probe = tegra_kbd_probe,
+ .ops = &tegra_kbd_ops,
+ .priv_auto_alloc_size = sizeof(struct tegra_kbd_priv),
+};
*/
#include <common.h>
-
+#include <console.h>
#ifndef CONFIG_SYS_COREBOOT
#error This driver requires coreboot
#endif
return len;
}
-int cros_ec_scan_keyboard(struct cros_ec_dev *dev, struct mbkp_keyscan *scan)
+int cros_ec_scan_keyboard(struct udevice *dev, struct mbkp_keyscan *scan)
{
- if (ec_command(dev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan,
+ struct cros_ec_dev *cdev = dev_get_uclass_priv(dev);
+
+ if (ec_command(cdev, EC_CMD_MKBP_STATE, 0, NULL, 0, scan,
sizeof(scan->data)) != sizeof(scan->data))
return -1;
return 0;
}
-int cros_ec_interrupt_pending(struct cros_ec_dev *dev)
+int cros_ec_interrupt_pending(struct udevice *dev)
{
+ struct cros_ec_dev *cdev = dev_get_uclass_priv(dev);
+
/* no interrupt support : always poll */
- if (!dm_gpio_is_valid(&dev->ec_int))
+ if (!dm_gpio_is_valid(&cdev->ec_int))
return -ENOENT;
- return dm_gpio_get_value(&dev->ec_int);
+ return dm_gpio_get_value(&cdev->ec_int);
}
int cros_ec_info(struct cros_ec_dev *dev, struct ec_response_mkbp_info *info)
len = cros_ec_keyscan(ec, resp_data);
break;
case EC_CMD_ENTERING_MODE:
+ len = 0;
break;
default:
printf(" ** Unknown EC command %#02x\n", req_hdr->command);
SDHCI_QUIRK_BROKEN_R1B;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
- add_sdhci(host, 52000000, 52000000 >> 9);
+ add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 52000000 >> 9);
return 0;
}
/* #define DEBUG */
#include <common.h>
+#include <console.h>
#include <dm.h>
#include <errno.h>
#include <fdt_support.h>
*/
#include <common.h>
+#include <console.h>
#include <asm/io.h>
#ifdef DEBUG
obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
-obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
+++ /dev/null
-/*
- * Copyright (C) 2009
- * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spi.h>
-
-#define SPI_EEPROM_WREN 0x06
-#define SPI_EEPROM_RDSR 0x05
-#define SPI_EEPROM_READ 0x03
-#define SPI_EEPROM_WRITE 0x02
-
-#ifndef CONFIG_DEFAULT_SPI_BUS
-#define CONFIG_DEFAULT_SPI_BUS 0
-#endif
-
-#ifndef CONFIG_DEFAULT_SPI_MODE
-#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
-#endif
-
-#ifndef CONFIG_SYS_SPI_WRITE_TOUT
-#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
-#endif
-
-ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
-{
- struct spi_slave *slave;
- u8 cmd = SPI_EEPROM_READ;
-
- slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
- CONFIG_DEFAULT_SPI_MODE);
- if (!slave)
- return 0;
-
- spi_claim_bus(slave);
-
- /* command */
- if (spi_xfer(slave, 8, &cmd, NULL, SPI_XFER_BEGIN))
- return -1;
-
- /*
- * if alen == 3, addr[0] is the block number, we never use it here.
- * All we need are the lower 16 bits.
- */
- if (alen == 3)
- addr++;
-
- /* address, and data */
- if (spi_xfer(slave, 16, addr, NULL, 0))
- return -1;
- if (spi_xfer(slave, 8 * len, NULL, buffer, SPI_XFER_END))
- return -1;
-
- spi_release_bus(slave);
- spi_free_slave(slave);
- return len;
-}
-
-ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
-{
- struct spi_slave *slave;
- char buf[3];
- ulong start;
-
- slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
- CONFIG_DEFAULT_SPI_MODE);
- if (!slave)
- return 0;
-
- spi_claim_bus(slave);
-
- buf[0] = SPI_EEPROM_WREN;
- if (spi_xfer(slave, 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END))
- return -1;
-
- buf[0] = SPI_EEPROM_WRITE;
-
- /* As for reading, drop addr[0] if alen is 3 */
- if (alen == 3) {
- alen--;
- addr++;
- }
-
- memcpy(buf + 1, addr, alen);
- /* command + addr, then data */
- if (spi_xfer(slave, 24, buf, NULL, SPI_XFER_BEGIN))
- return -1;
- if (spi_xfer(slave, len * 8, buffer, NULL, SPI_XFER_END))
- return -1;
-
- start = get_timer(0);
- do {
- buf[0] = SPI_EEPROM_RDSR;
- buf[1] = 0;
- spi_xfer(slave, 16, buf, buf, SPI_XFER_BEGIN | SPI_XFER_END);
-
- if (!(buf[1] & 1))
- break;
-
- } while (get_timer(start) < CONFIG_SYS_SPI_WRITE_TOUT);
-
- if (buf[1] & 1)
- printf("*** spi_write: Timeout while writing!\n");
-
- spi_release_bus(slave);
- spi_free_slave(slave);
- return len;
-}
#include <dm/device-internal.h>
#include "sf_internal.h"
+DECLARE_GLOBAL_DATA_PTR;
+
int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf)
{
return sf_get_ops(dev)->read(dev, offset, len, buf);
return device_remove(dev);
}
+static int spi_flash_post_bind(struct udevice *dev)
+{
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+ struct dm_spi_flash_ops *ops = sf_get_ops(dev);
+ static int reloc_done;
+
+ if (!reloc_done) {
+ if (ops->read)
+ ops->read += gd->reloc_off;
+ if (ops->write)
+ ops->write += gd->reloc_off;
+ if (ops->erase)
+ ops->erase += gd->reloc_off;
+
+ reloc_done++;
+ }
+#endif
+ return 0;
+}
+
UCLASS_DRIVER(spi_flash) = {
.id = UCLASS_SPI_FLASH,
.name = "spi_flash",
+ .post_bind = spi_flash_post_bind,
.per_device_auto_alloc_size = sizeof(struct spi_flash),
};
#define SPI_FLASH_CFI_MFR_SPANSION 0x01
#define SPI_FLASH_CFI_MFR_STMICRO 0x20
#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
+#define SPI_FLASH_CFI_MFR_SST 0xbf
#define SPI_FLASH_CFI_MFR_WINBOND 0xef
/* Erase commands */
}
#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO
+#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
u32 *len)
{
u8 status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 shift = ffs(mask) - 1, pow, val;
+ int ret;
- spi_flash_cmd_read_status(flash, &status_old);
+ ret = spi_flash_cmd_read_status(flash, &status_old);
+ if (ret < 0)
+ return ret;
/* SPI NOR always locks to the end */
if (ofs + len != flash->size) {
uint8_t status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
u8 shift = ffs(mask) - 1, pow, val;
+ int ret;
- spi_flash_cmd_read_status(flash, &status_old);
+ ret = spi_flash_cmd_read_status(flash, &status_old);
+ if (ret < 0)
+ return ret;
/* Cannot unlock; would unlock larger region than requested */
if (stm_is_locked_sr(flash, status_old, ofs - flash->erase_size,
return 0;
}
-#endif /* CONFIG_SPI_FLASH_STMICRO */
+#endif
flash->memory_map = spi->memory_map;
flash->dual_flash = flash->spi->option;
+ /* Assign spi flash flags */
+ if (params->flags & SST_WR)
+ flash->flags |= SNOR_F_SST_WR;
+
/* Assign spi_flash ops */
#ifndef CONFIG_DM_SPI_FLASH
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
- if (params->flags & SST_WR)
- flash->flags |= SNOR_F_SST_WR;
-
- if (params->flags & SNOR_F_SST_WR) {
+ if (flash->flags & SNOR_F_SST_WR) {
if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
flash->write = sst_write_bp;
else
/* lock hooks are flash specific - assign them based on idcode0 */
switch (idcode[0]) {
-#ifdef CONFIG_SPI_FLASH_STMICRO
+#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
case SPI_FLASH_CFI_MFR_STMICRO:
+ case SPI_FLASH_CFI_MFR_SST:
flash->flash_lock = stm_lock;
flash->flash_unlock = stm_unlock;
flash->flash_is_locked = stm_is_locked;
#include <common.h>
+#include <console.h>
#include "e1000.h"
#include <linux/compiler.h>
*/
#include <common.h>
#include <command.h>
+#include <console.h>
#include <net.h>
#include <phy.h>
obj-$(CONFIG_PHY_REALTEK) += realtek.o
obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
+obj-$(CONFIG_PHY_TI) += ti.o
obj-$(CONFIG_PHY_VITESSE) += vitesse.o
#include <config.h>
#include <common.h>
+#include <console.h>
#include <dm.h>
#include <malloc.h>
#include <net.h>
#ifdef CONFIG_PHY_TERANETICS
phy_teranetics_init();
#endif
+#ifdef CONFIG_PHY_TI
+ phy_ti_init();
+#endif
#ifdef CONFIG_PHY_VITESSE
phy_vitesse_init();
#endif
--- /dev/null
+/*
+ * TI PHY drivers
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+#include <common.h>
+#include <phy.h>
+
+/* TI DP83867 */
+#define DP83867_DEVADDR 0x1f
+
+#define MII_DP83867_PHYCTRL 0x10
+#define MII_DP83867_MICR 0x12
+#define DP83867_CTRL 0x1f
+
+/* Extended Registers */
+#define DP83867_RGMIICTL 0x0032
+#define DP83867_RGMIIDCTL 0x0086
+
+#define DP83867_SW_RESET BIT(15)
+#define DP83867_SW_RESTART BIT(14)
+
+/* MICR Interrupt bits */
+#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
+#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
+#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
+#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
+#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
+#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
+#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
+#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
+#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
+#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
+#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
+#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
+
+/* RGMIICTL bits */
+#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
+#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
+
+/* PHY CTRL bits */
+#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
+
+/* RGMIIDCTL bits */
+#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
+
+#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
+#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
+
+/* MMD Access Control register fields */
+#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
+#define MII_MMD_CTRL_ADDR 0x0000 /* Address */
+#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */
+#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
+#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
+
+/**
+ * phy_read_mmd_indirect - reads data from the MMD registers
+ * @phydev: The PHY device bus
+ * @prtad: MMD Address
+ * @devad: MMD DEVAD
+ * @addr: PHY address on the MII bus
+ *
+ * Description: it reads data from the MMD registers (clause 22 to access to
+ * clause 45) of the specified phy address.
+ * To read these registers we have:
+ * 1) Write reg 13 // DEVAD
+ * 2) Write reg 14 // MMD Address
+ * 3) Write reg 13 // MMD Data Command for MMD DEVAD
+ * 3) Read reg 14 // Read MMD data
+ */
+int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
+ int devad, int addr)
+{
+ int value = -1;
+
+ /* Write the desired MMD Devad */
+ phy_write(phydev, addr, MII_MMD_CTRL, devad);
+
+ /* Write the desired MMD register address */
+ phy_write(phydev, addr, MII_MMD_DATA, prtad);
+
+ /* Select the Function : DATA with no post increment */
+ phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
+
+ /* Read the content of the MMD's selected register */
+ value = phy_read(phydev, addr, MII_MMD_DATA);
+ return value;
+}
+
+/**
+ * phy_write_mmd_indirect - writes data to the MMD registers
+ * @phydev: The PHY device
+ * @prtad: MMD Address
+ * @devad: MMD DEVAD
+ * @addr: PHY address on the MII bus
+ * @data: data to write in the MMD register
+ *
+ * Description: Write data from the MMD registers of the specified
+ * phy address.
+ * To write these registers we have:
+ * 1) Write reg 13 // DEVAD
+ * 2) Write reg 14 // MMD Address
+ * 3) Write reg 13 // MMD Data Command for MMD DEVAD
+ * 3) Write reg 14 // Write MMD data
+ */
+void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
+ int devad, int addr, u32 data)
+{
+ /* Write the desired MMD Devad */
+ phy_write(phydev, addr, MII_MMD_CTRL, devad);
+
+ /* Write the desired MMD register address */
+ phy_write(phydev, addr, MII_MMD_DATA, prtad);
+
+ /* Select the Function : DATA with no post increment */
+ phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
+
+ /* Write the data into MMD's selected register */
+ phy_write(phydev, addr, MII_MMD_DATA, data);
+}
+
+/**
+ * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
+ * is RGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+{
+ return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
+ phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
+}
+
+/* User setting - can be taken from DTS */
+#define RX_ID_DELAY 8
+#define TX_ID_DELAY 0xa
+#define FIFO_DEPTH 1
+
+static int dp83867_config(struct phy_device *phydev)
+{
+ unsigned int val, delay;
+ int ret;
+
+ /* Restart the PHY. */
+ val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
+ phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
+ val | DP83867_SW_RESTART);
+
+ if (phy_interface_is_rgmii(phydev)) {
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
+ (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
+ if (ret)
+ return ret;
+ }
+
+ if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
+ (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
+ val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
+ DP83867_DEVADDR, phydev->addr);
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
+ DP83867_RGMII_RX_CLK_DELAY_EN);
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ val |= DP83867_RGMII_TX_CLK_DELAY_EN;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ val |= DP83867_RGMII_RX_CLK_DELAY_EN;
+
+ phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
+ DP83867_DEVADDR, phydev->addr, val);
+
+ delay = (RX_ID_DELAY |
+ (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
+
+ phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
+ DP83867_DEVADDR, phydev->addr, delay);
+ }
+
+ genphy_config_aneg(phydev);
+ return 0;
+}
+
+static struct phy_driver DP83867_driver = {
+ .name = "TI DP83867",
+ .uid = 0x2000a231,
+ .mask = 0xfffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &dp83867_config,
+ .startup = &genphy_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+int phy_ti_init(void)
+{
+ phy_register(&DP83867_driver);
+ return 0;
+}
#include <config.h>
#include <common.h>
+#include <console.h>
#include <asm/io.h>
#include <asm/errno.h>
#include "vsc7385.h"
#include <asm/system.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
+#include <asm-generic/errno.h>
#if !defined(CONFIG_PHYLIB)
# error XILINX_GEM_ETHERNET requires PHYLIB
/* Wrap bit, last descriptor */
#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
+#define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */
#ifdef CONFIG_ARM64
# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
ZYNQ_GEM_DMACR_TXSIZE | \
ZYNQ_GEM_DMACR_RXBUF)
+#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
+
/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG 1
/* Device registers */
struct zynq_gem_regs {
- u32 nwctrl; /* Network Control reg */
- u32 nwcfg; /* Network Config reg */
- u32 nwsr; /* Network Status reg */
+ u32 nwctrl; /* 0x0 - Network Control reg */
+ u32 nwcfg; /* 0x4 - Network Config reg */
+ u32 nwsr; /* 0x8 - Network Status reg */
u32 reserved1;
- u32 dmacr; /* DMA Control reg */
- u32 txsr; /* TX Status reg */
- u32 rxqbase; /* RX Q Base address reg */
- u32 txqbase; /* TX Q Base address reg */
- u32 rxsr; /* RX Status reg */
+ u32 dmacr; /* 0x10 - DMA Control reg */
+ u32 txsr; /* 0x14 - TX Status reg */
+ u32 rxqbase; /* 0x18 - RX Q Base address reg */
+ u32 txqbase; /* 0x1c - TX Q Base address reg */
+ u32 rxsr; /* 0x20 - RX Status reg */
u32 reserved2[2];
- u32 idr; /* Interrupt Disable reg */
+ u32 idr; /* 0x2c - Interrupt Disable reg */
u32 reserved3;
- u32 phymntnc; /* Phy Maintaince reg */
+ u32 phymntnc; /* 0x34 - Phy Maintaince reg */
u32 reserved4[18];
- u32 hashl; /* Hash Low address reg */
- u32 hashh; /* Hash High address reg */
+ u32 hashl; /* 0x80 - Hash Low address reg */
+ u32 hashh; /* 0x84 - Hash High address reg */
#define LADDR_LOW 0
#define LADDR_HIGH 1
- u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
- u32 match[4]; /* Type ID1 Match reg */
+ u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
+ u32 match[4]; /* 0xa8 - Type ID1 Match reg */
u32 reserved6[18];
- u32 stat[44]; /* Octects transmitted Low reg - stat start */
+#define STAT_SIZE 44
+ u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
+ u32 reserved7[164];
+ u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
+ u32 reserved8[15];
+ u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
};
/* BD descriptors */
*/
#define BD_SPACE 0x100000
/* BD separation space */
-#define BD_SEPRN_SPACE 64
+#define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
+
+/* Setup the first free TX descriptor */
+#define TX_FREE_DESC 2
/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
struct zynq_gem_priv {
int phyaddr;
u32 emio;
int init;
+ phy_interface_t interface;
struct phy_device *phydev;
struct mii_dev *bus;
};
static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
{
- return phy_setup_op(dev, phy_addr, regnum,
+ u32 ret;
+
+ ret = phy_setup_op(dev, phy_addr, regnum,
ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
+
+ if (!ret)
+ debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
+ phy_addr, regnum, *val);
+
+ return ret;
}
static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
{
+ debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
+ regnum, data);
+
return phy_setup_op(dev, phy_addr, regnum,
ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
}
u32 i;
unsigned long clk_rate = 0;
struct phy_device *phydev;
- const u32 stat_size = (sizeof(struct zynq_gem_regs) -
- offsetof(struct zynq_gem_regs, stat)) / 4;
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
struct zynq_gem_priv *priv = dev->priv;
+ struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
+ struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
const u32 supported = SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
writel(0x0, ®s->hashh);
/* Clear all counters */
- for (i = 0; i <= stat_size; i++)
+ for (i = 0; i < STAT_SIZE; i++)
readl(®s->stat[i]);
/* Setup RxBD space */
/* Setup for Network Control register, MDIO, Rx and Tx enable */
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
+ /* Disable the second priority queue */
+ dummy_tx_bd->addr = 0;
+ dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
+ ZYNQ_GEM_TXBUF_LAST_MASK|
+ ZYNQ_GEM_TXBUF_USED_MASK;
+
+ dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
+ ZYNQ_GEM_RXBUF_NEW_MASK;
+ dummy_rx_bd->status = 0;
+ flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
+ sizeof(dummy_tx_bd));
+ flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
+ sizeof(dummy_rx_bd));
+
+ writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
+ writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
+
priv->init++;
}
/* interface - look at tsec */
phydev = phy_connect(priv->bus, priv->phyaddr, dev,
- PHY_INTERFACE_MODE_MII);
+ priv->interface);
phydev->supported = supported | ADVERTISED_Pause |
ADVERTISED_Asym_Pause;
clk_rate = ZYNQ_GEM_FREQUENCY_1000;
break;
case SPEED_100:
- clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
- ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
+ writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
+ ®s->nwcfg);
clk_rate = ZYNQ_GEM_FREQUENCY_100;
break;
case SPEED_10:
return 0;
}
+static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
+ bool set, unsigned int timeout)
+{
+ u32 val;
+ unsigned long start = get_timer(0);
+
+ while (1) {
+ val = readl(reg);
+
+ if (!set)
+ val = ~val;
+
+ if ((val & mask) == mask)
+ return 0;
+
+ if (get_timer(start) > timeout)
+ break;
+
+ udelay(1);
+ }
+
+ debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
+ func, reg, mask, set);
+
+ return -ETIMEDOUT;
+}
+
static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
{
u32 addr, size;
struct zynq_gem_priv *priv = dev->priv;
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
-
- /* setup BD */
- writel((ulong)priv->tx_bd, ®s->txqbase);
+ struct emac_bd *current_bd = &priv->tx_bd[1];
/* Setup Tx BD */
memset(priv->tx_bd, 0, sizeof(struct emac_bd));
priv->tx_bd->addr = (ulong)ptr;
priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
- ZYNQ_GEM_TXBUF_LAST_MASK |
- ZYNQ_GEM_TXBUF_WRAP_MASK;
+ ZYNQ_GEM_TXBUF_LAST_MASK;
+ /* Dummy descriptor to mark it as the last in descriptor chain */
+ current_bd->addr = 0x0;
+ current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
+ ZYNQ_GEM_TXBUF_LAST_MASK|
+ ZYNQ_GEM_TXBUF_USED_MASK;
+
+ /* setup BD */
+ writel((ulong)priv->tx_bd, ®s->txqbase);
addr = (ulong) ptr;
addr &= ~(ARCH_DMA_MINALIGN - 1);
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
/* Read TX BD status */
- if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
- printf("TX underrun\n");
if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
printf("TX buffers exhausted in mid frame\n");
- return 0;
+ return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE,
+ true, 20000);
}
/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
priv->phyaddr = phy_addr;
priv->emio = emio;
+#ifndef CONFIG_ZYNQ_GEM_INTERFACE
+ priv->interface = PHY_INTERFACE_MODE_MII;
+#else
+ priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
+#endif
+
sprintf(dev->name, "Gem.%lx", base_addr);
dev->iobase = base_addr;
bus_addr = phys_addr - res->phys_start + res->bus_start;
if (bus_addr >= res->bus_start &&
- bus_addr < res->bus_start + res->size) {
+ (bus_addr - res->bus_start) < res->size) {
*ba = bus_addr;
return 0;
}
prompt "Select Sunxi PMIC Variant"
depends on ARCH_SUNXI
default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
- default AXP221_POWER if MACH_SUN6I || MACH_SUN8I
+ default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
+ default SUNXI_NO_PMIC if MACH_SUN8I_H3
config SUNXI_NO_PMIC
boolean "board without a pmic"
config AXP221_POWER
boolean "axp221 / axp223 pmic support"
- depends on MACH_SUN6I || MACH_SUN8I
+ depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
---help---
Select this to enable support for the axp221/axp223 pmic found on most
A23 and A31 boards.
*/
#include <common.h>
+#include <console.h>
#include <power/pmic.h>
#include <power/battery.h>
#include <power/max8997_pmic.h>
choice
prompt "Select which UART will provide the debug UART"
depends on DEBUG_UART
+ default DEBUG_UART_NS16550
config DEBUG_UART_ALTERA_JTAGUART
bool "Altera JTAG UART"
Select this to enable an UART for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
-config ROCKCHIP_SERIAL
- bool "Rockchip on-chip UART support"
- depends on ARCH_ROCKCHIP && DM_SERIAL
+config SYS_NS16550
+ bool "NS16550 UART or compatible"
help
- Select this to enable a debug UART for Rockchip devices. This uses
- the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in
- your board config header. The clock input is automatically set to
- use the oscillator (24MHz).
+ Support NS16550 UART or compatible. This can be enabled in the
+ device tree with the correct input clock frequency. If the input
+ clock frequency is not defined in the device tree, the macro
+ CONFIG_SYS_NS16550_CLK defined in a legacy board header file will
+ be used. It can be a constant or a function to get clock, eg,
+ get_serial_clock().
config SANDBOX_SERIAL
bool "Sandbox UART support"
If you have a UniPhier based board and want to use the on-chip
serial ports, say Y to this option. If unsure, say N.
-config X86_SERIAL
- bool "Support for 16550 serial port on x86 machines"
- depends on X86
- default y
- help
- Most x86 machines have a ns16550 UART or compatible. This can be
- enabled in the device tree with the correct input clock frequency
- provided (default 1843200). Enable this to obtain serial console
- output.
-
endmenu
ifdef CONFIG_DM_SERIAL
obj-y += serial-uclass.o
obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o
-obj-$(CONFIG_PPC) += serial_ppc.o
else
obj-y += serial.o
obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
-obj-$(CONFIG_DW_SERIAL) += serial_dw.o
obj-$(CONFIG_EFI_APP) += serial_efi.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += mcfuart.o
obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
-obj-$(CONFIG_KEYSTONE_SERIAL) += serial_keystone.o
obj-$(CONFIG_SYS_NS16550) += ns16550.o
obj-$(CONFIG_S5P) += serial_s5p.o
obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
obj-$(CONFIG_MXS_AUART) += mxs_auart.o
-obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
-obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
-obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
-obj-$(CONFIG_X86_SERIAL) += serial_x86.o
obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
ifndef CONFIG_SPL_BUILD
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
-#include <mapmem.h>
#include <ns16550.h>
#include <serial.h>
#include <watchdog.h>
#ifdef CONFIG_DM_SERIAL
+#ifndef CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_CLK 0
+#endif
+
static inline void serial_out_shift(void *addr, int shift, int value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = map_sysmem(plat->base, 0) + offset;
+ addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
/*
* As far as we know it doesn't make sense to support selection of
* these options at run-time, so use the existing CONFIG options.
unsigned char *addr;
offset *= 1 << plat->reg_shift;
- addr = map_sysmem(plat->base, 0) + offset;
+ addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
return serial_in_shift(addr, plat->reg_shift);
}
plat->base = addr;
plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"reg-shift", 1);
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "clock-frequency",
+ CONFIG_SYS_NS16550_CLK);
+ if (!plat->clock) {
+ debug("ns16550 clock not defined\n");
+ return -EINVAL;
+ }
return 0;
}
.getc = ns16550_serial_getc,
.setbrg = ns16550_serial_setbrg,
};
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct udevice_id ns16550_serial_ids[] = {
+ { .compatible = "ns16550" },
+ { .compatible = "ns16550a" },
+ { .compatible = "nvidia,tegra20-uart" },
+ { .compatible = "snps,dw-apb-uart" },
+ { .compatible = "ti,omap2-uart" },
+ { .compatible = "ti,omap3-uart" },
+ { .compatible = "ti,omap4-uart" },
+ { .compatible = "ti,am3352-uart" },
+ { .compatible = "ti,am4372-uart" },
+ { .compatible = "ti,dra742-uart" },
+ {}
+};
+#endif
+
+U_BOOT_DRIVER(ns16550_serial) = {
+ .name = "ns16550_serial",
+ .id = UCLASS_SERIAL,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ .of_match = ns16550_serial_ids,
+ .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+#endif
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = ns16550_serial_probe,
+ .ops = &ns16550_serial_ops,
+};
#endif /* CONFIG_DM_SERIAL */
+++ /dev/null
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <serial.h>
-
-static const struct udevice_id dw_serial_ids[] = {
- { .compatible = "snps,dw-apb-uart" },
- { }
-};
-
-static int dw_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
- plat->clock = CONFIG_SYS_NS16550_CLK;
-
- return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
- .name = "serial_dw",
- .id = UCLASS_SERIAL,
- .of_match = dw_serial_ids,
- .ofdata_to_platdata = dw_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
-};
+++ /dev/null
-/*
- * Copyright (c) 2015 Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <ns16550.h>
-#include <serial.h>
-#include <asm/arch/clock.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct udevice_id keystone_serial_ids[] = {
- { .compatible = "ti,keystone-uart" },
- { .compatible = "ns16550a" },
- { }
-};
-
-static int keystone_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
- plat->clock = CONFIG_SYS_NS16550_CLK;
- return 0;
-}
-#endif
-
-U_BOOT_DRIVER(serial_keystone_ns16550) = {
- .name = "serial_keystone",
- .id = UCLASS_SERIAL,
-#if CONFIG_IS_ENABLED(OF_CONTROL)
- .of_match = of_match_ptr(keystone_serial_ids),
- .ofdata_to_platdata = of_match_ptr(keystone_serial_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
-#endif
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <ns16550.h>
-#include <serial.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct udevice_id omap_serial_ids[] = {
- { .compatible = "ti,omap2-uart" },
- { .compatible = "ti,omap3-uart" },
- { .compatible = "ti,omap4-uart" },
- { .compatible = "ti,am3352-uart" },
- { .compatible = "ti,am4372-uart" },
- { .compatible = "ti,dra742-uart" },
- { }
-};
-
-static int omap_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "clock-frequency", DEFAULT_CLK_SPEED);
- plat->reg_shift = 2;
-
- return 0;
-}
-#endif
-
-U_BOOT_DRIVER(serial_omap_ns16550) = {
- .name = "serial_omap",
- .id = UCLASS_SERIAL,
- .of_match = of_match_ptr(omap_serial_ids),
- .ofdata_to_platdata = of_match_ptr(omap_serial_ofdata_to_platdata),
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <serial.h>
-
-static const struct udevice_id ppc_serial_ids[] = {
- { .compatible = "ns16550" },
- { }
-};
-
-static int ppc_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
- plat->clock = get_serial_clock();
-
- return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
- .name = "serial_ppc",
- .id = UCLASS_SERIAL,
- .of_match = ppc_serial_ids,
- .ofdata_to_platdata = ppc_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (c) 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <serial.h>
-#include <asm/arch/clock.h>
-
-static const struct udevice_id rockchip_serial_ids[] = {
- { .compatible = "rockchip,rk3288-uart" },
- { }
-};
-
-static int rockchip_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
-
- /* Do all Rockchip parts use 24MHz? */
- plat->clock = 24 * 1000000;
-
- return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
- .name = "serial_rockchip",
- .id = UCLASS_SERIAL,
- .of_match = rockchip_serial_ids,
- .ofdata_to_platdata = rockchip_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <serial.h>
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct udevice_id tegra_serial_ids[] = {
- { .compatible = "nvidia,tegra20-uart" },
- { }
-};
-
-static int tegra_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
- plat->clock = V_NS16550_CLK;
-
- return 0;
-}
-#else
-struct ns16550_platdata tegra_serial = {
- .base = CONFIG_SYS_NS16550_COM1,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
-};
-
-U_BOOT_DEVICE(ns16550_serial) = {
- "serial_tegra20", &tegra_serial
-};
-#endif
-
-U_BOOT_DRIVER(serial_ns16550) = {
- .name = "serial_tegra20",
- .id = UCLASS_SERIAL,
-#if CONFIG_IS_ENABLED(OF_CONTROL)
- .of_match = tegra_serial_ids,
- .ofdata_to_platdata = tegra_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
-#endif
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <ns16550.h>
-#include <serial.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct udevice_id x86_serial_ids[] = {
- { .compatible = "x86-uart" },
- { }
-};
-
-static int x86_serial_ofdata_to_platdata(struct udevice *dev)
-{
- struct ns16550_platdata *plat = dev_get_platdata(dev);
- int ret;
-
- ret = ns16550_serial_ofdata_to_platdata(dev);
- if (ret)
- return ret;
-
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "clock-frequency", 1843200);
-
- return 0;
-}
-
-U_BOOT_DRIVER(serial_ns16550) = {
- .name = "serial_x86",
- .id = UCLASS_SERIAL,
- .of_match = x86_serial_ids,
- .ofdata_to_platdata = x86_serial_ofdata_to_platdata,
- .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
- .priv_auto_alloc_size = sizeof(struct NS16550),
- .probe = ns16550_serial_probe,
- .ops = &ns16550_serial_ops,
-};
/*#define DEBUG*/
#include <common.h>
+#include <console.h>
#include <malloc.h>
#include <spi.h>
*/
#include <common.h>
+#include <console.h>
#include <malloc.h>
#include <spi.h>
*/
#include <common.h>
+#include <console.h>
#include <malloc.h>
#include <spi.h>
#include <asm/arch/rmobile.h>
*/
#include <common.h>
+#include <console.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
"spi-max-frequency", 0);
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+ struct dm_spi_ops *ops = spi_get_ops(bus);
+
+
+ if (ops->claim_bus)
+ ops->claim_bus += gd->reloc_off;
+ if (ops->release_bus)
+ ops->release_bus += gd->reloc_off;
+ if (ops->set_wordlen)
+ ops->set_wordlen += gd->reloc_off;
+ if (ops->xfer)
+ ops->xfer += gd->reloc_off;
+ if (ops->set_speed)
+ ops->set_speed += gd->reloc_off;
+ if (ops->set_mode)
+ ops->set_mode += gd->reloc_off;
+ if (ops->cs_info)
+ ops->cs_info += gd->reloc_off;
+#endif
+
return 0;
}
debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
+ /* dummy readl to ensure bus sync */
+ readl(&qslave->base->cmd);
}
void spi_init(void)
Select this to enable an timer for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
+config SANDBOX_TIMER
+ bool "Sandbox Timer support"
+ depends on SANDBOX && TIMER
+ help
+ Select this to enable an emulated timer for sandbox. It gets
+ time from host os.
+
endmenu
obj-$(CONFIG_TIMER) += timer-uclass.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
+obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <timer.h>
+#include <os.h>
+
+/* system timer offset in ms */
+static unsigned long sandbox_timer_offset;
+
+void sandbox_timer_add_offset(unsigned long offset)
+{
+ sandbox_timer_offset += offset;
+}
+
+static int sandbox_timer_get_count(struct udevice *dev, unsigned long *count)
+{
+ *count = os_get_nsec() / 1000 + sandbox_timer_offset * 1000;
+
+ return 0;
+}
+
+static int sandbox_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->clock_rate = 1000000;
+
+ return 0;
+}
+
+static const struct timer_ops sandbox_timer_ops = {
+ .get_count = sandbox_timer_get_count,
+};
+
+static const struct udevice_id sandbox_timer_ids[] = {
+ { .compatible = "sandbox,timer" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_timer) = {
+ .name = "sandbox_timer",
+ .id = UCLASS_TIMER,
+ .of_match = sandbox_timer_ids,
+ .probe = sandbox_timer_probe,
+ .ops = &sandbox_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
obj-$(CONFIG_USB_EMUL) += sandbox_flash.o
obj-$(CONFIG_USB_EMUL) += sandbox_hub.o
+obj-$(CONFIG_USB_EMUL) += sandbox_keyb.o
obj-$(CONFIG_USB_EMUL) += usb-emul-uclass.o
PHASE_STATUS,
};
+enum {
+ STRINGID_MANUFACTURER = 1,
+ STRINGID_PRODUCT,
+ STRINGID_SERIAL,
+
+ STRINGID_COUNT,
+};
+
/**
* struct sandbox_flash_priv - private state for this driver
*
struct sandbox_flash_plat {
const char *pathname;
+ struct usb_string flash_strings[STRINGID_COUNT];
};
struct scsi_inquiry_resp {
u8 spare2[3];
};
-enum {
- STRINGID_MANUFACTURER = 1,
- STRINGID_PRODUCT,
- STRINGID_SERIAL,
-
- STRINGID_COUNT,
-};
-
-static struct usb_string flash_strings[] = {
- {STRINGID_MANUFACTURER, "sandbox"},
- {STRINGID_PRODUCT, "flash"},
- {STRINGID_SERIAL, "2345"},
- {},
-};
-
static struct usb_device_descriptor flash_device_desc = {
.bLength = sizeof(flash_device_desc),
.bDescriptorType = USB_DT_DEVICE,
}
}
-static int handle_ufi_command(struct sandbox_flash_priv *priv, const void *buff,
+static int handle_ufi_command(struct sandbox_flash_plat *plat,
+ struct sandbox_flash_priv *priv, const void *buff,
int len)
{
const struct SCSI_cmd_block *req = buff;
resp->data_format = 1;
resp->additional_len = 0x1f;
strncpy(resp->vendor,
- flash_strings[STRINGID_MANUFACTURER - 1].s,
+ plat->flash_strings[STRINGID_MANUFACTURER - 1].s,
sizeof(resp->vendor));
- strncpy(resp->product, flash_strings[STRINGID_PRODUCT - 1].s,
+ strncpy(resp->product,
+ plat->flash_strings[STRINGID_PRODUCT - 1].s,
sizeof(resp->product));
strncpy(resp->revision, "1.0", sizeof(resp->revision));
setup_response(priv, resp, sizeof(*resp));
static int sandbox_flash_bulk(struct udevice *dev, struct usb_device *udev,
unsigned long pipe, void *buff, int len)
{
+ struct sandbox_flash_plat *plat = dev_get_platdata(dev);
struct sandbox_flash_priv *priv = dev_get_priv(dev);
int ep = usb_pipeendpoint(pipe);
struct umass_bbb_cbw *cbw = buff;
goto err;
priv->transfer_len = cbw->dCBWDataTransferLength;
priv->tag = cbw->dCBWTag;
- return handle_ufi_command(priv, cbw->CBWCDB,
+ return handle_ufi_command(plat, priv, cbw->CBWCDB,
cbw->bCDBLength);
case PHASE_DATA:
debug("data out\n");
static int sandbox_flash_bind(struct udevice *dev)
{
- return usb_emul_setup_device(dev, PACKET_SIZE_64, flash_strings,
+ struct sandbox_flash_plat *plat = dev_get_platdata(dev);
+ struct usb_string *fs;
+
+ fs = plat->flash_strings;
+ fs[0].id = STRINGID_MANUFACTURER;
+ fs[0].s = "sandbox";
+ fs[1].id = STRINGID_PRODUCT;
+ fs[1].s = "flash";
+ fs[2].id = STRINGID_SERIAL;
+ fs[2].s = dev->name;
+
+ return usb_emul_setup_device(dev, PACKET_SIZE_64, plat->flash_strings,
flash_desc_list);
}
DECLARE_GLOBAL_DATA_PTR;
/* We only support up to 8 */
-#define SANDBOX_NUM_PORTS 2
+#define SANDBOX_NUM_PORTS 4
struct sandbox_hub_platdata {
struct usb_dev_platdata plat;
--- /dev/null
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <os.h>
+#include <scsi.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This driver emulates a USB keyboard using the USB HID specification (boot
+ * protocol)
+ */
+
+enum {
+ SANDBOX_KEYB_EP_IN = 1, /* endpoints */
+};
+
+enum cmd_phase {
+ PHASE_START,
+ PHASE_DATA,
+ PHASE_STATUS,
+};
+
+enum {
+ STRINGID_MANUFACTURER = 1,
+ STRINGID_PRODUCT,
+ STRINGID_SERIAL,
+
+ STRINGID_COUNT,
+};
+
+/**
+ * struct sandbox_keyb_priv - private state for this driver
+ *
+ */
+struct sandbox_keyb_priv {
+ struct membuff in;
+};
+
+struct sandbox_keyb_plat {
+ struct usb_string keyb_strings[STRINGID_COUNT];
+};
+
+static struct usb_device_descriptor keyb_device_desc = {
+ .bLength = sizeof(keyb_device_desc),
+ .bDescriptorType = USB_DT_DEVICE,
+
+ .bcdUSB = __constant_cpu_to_le16(0x0100),
+
+ .bDeviceClass = 0,
+ .bDeviceSubClass = 0,
+ .bDeviceProtocol = 0,
+
+ .idVendor = __constant_cpu_to_le16(0x1234),
+ .idProduct = __constant_cpu_to_le16(0x5679),
+ .iManufacturer = STRINGID_MANUFACTURER,
+ .iProduct = STRINGID_PRODUCT,
+ .iSerialNumber = STRINGID_SERIAL,
+ .bNumConfigurations = 1,
+};
+
+static struct usb_config_descriptor keyb_config0 = {
+ .bLength = sizeof(keyb_config0),
+ .bDescriptorType = USB_DT_CONFIG,
+
+ /* wTotalLength is set up by usb-emul-uclass */
+ .bNumInterfaces = 2,
+ .bConfigurationValue = 0,
+ .iConfiguration = 0,
+ .bmAttributes = 1 << 7 | 1 << 5,
+ .bMaxPower = 50,
+};
+
+static struct usb_interface_descriptor keyb_interface0 = {
+ .bLength = sizeof(keyb_interface0),
+ .bDescriptorType = USB_DT_INTERFACE,
+
+ .bInterfaceNumber = 0,
+ .bAlternateSetting = 0,
+ .bNumEndpoints = 1,
+ .bInterfaceClass = USB_CLASS_HID,
+ .bInterfaceSubClass = USB_SUB_HID_BOOT,
+ .bInterfaceProtocol = USB_PROT_HID_KEYBOARD,
+ .iInterface = 0,
+};
+
+static struct usb_class_hid_descriptor keyb_report0 = {
+ .bLength = sizeof(keyb_report0),
+ .bDescriptorType = USB_DT_HID,
+ .bcdCDC = 0x101,
+ .bCountryCode = 0,
+ .bNumDescriptors = 1,
+ .bDescriptorType0 = USB_DT_HID_REPORT,
+ .wDescriptorLength0 = 0x3f,
+};
+
+static struct usb_endpoint_descriptor keyb_endpoint0_in = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+
+ .bEndpointAddress = SANDBOX_KEYB_EP_IN | USB_ENDPOINT_DIR_MASK,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK |
+ USB_ENDPOINT_XFER_ISOC,
+ .wMaxPacketSize = __constant_cpu_to_le16(8),
+ .bInterval = 0xa,
+};
+
+static struct usb_interface_descriptor keyb_interface1 = {
+ .bLength = sizeof(keyb_interface1),
+ .bDescriptorType = USB_DT_INTERFACE,
+
+ .bInterfaceNumber = 1,
+ .bAlternateSetting = 0,
+ .bNumEndpoints = 1,
+ .bInterfaceClass = USB_CLASS_HID,
+ .bInterfaceSubClass = USB_SUB_HID_BOOT,
+ .bInterfaceProtocol = USB_PROT_HID_MOUSE,
+ .iInterface = 0,
+};
+
+static struct usb_class_hid_descriptor keyb_report1 = {
+ .bLength = sizeof(struct usb_class_hid_descriptor),
+ .bDescriptorType = USB_DT_HID,
+ .bcdCDC = 0x101,
+ .bCountryCode = 0,
+ .bNumDescriptors = 1,
+ .bDescriptorType0 = USB_DT_HID_REPORT,
+ .wDescriptorLength0 = 0x32,
+};
+
+static struct usb_endpoint_descriptor keyb_endpoint1_in = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+
+ .bEndpointAddress = SANDBOX_KEYB_EP_IN | USB_ENDPOINT_DIR_MASK,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK |
+ USB_ENDPOINT_XFER_ISOC,
+ .wMaxPacketSize = __constant_cpu_to_le16(8),
+ .bInterval = 0xa,
+};
+
+static void *keyb_desc_list[] = {
+ &keyb_device_desc,
+ &keyb_config0,
+ &keyb_interface0,
+ &keyb_report0,
+ &keyb_endpoint0_in,
+ &keyb_interface1,
+ &keyb_report1,
+ &keyb_endpoint1_in,
+ NULL,
+};
+
+int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str)
+{
+ struct sandbox_keyb_priv *priv = dev_get_priv(dev);
+ int len, ret;
+
+ len = strlen(str);
+ ret = membuff_put(&priv->in, str, len);
+ if (ret != len)
+ return -ENOSPC;
+
+ return 0;
+}
+
+static int sandbox_keyb_control(struct udevice *dev, struct usb_device *udev,
+ unsigned long pipe, void *buff, int len,
+ struct devrequest *setup)
+{
+ debug("pipe=%lx\n", pipe);
+
+ return -EIO;
+}
+
+static int sandbox_keyb_interrupt(struct udevice *dev, struct usb_device *udev,
+ unsigned long pipe, void *buffer, int length, int interval)
+{
+ struct sandbox_keyb_priv *priv = dev_get_priv(dev);
+ uint8_t *data = buffer;
+ int ch;
+
+ memset(data, '\0', length);
+ ch = membuff_getbyte(&priv->in);
+ if (ch != -1)
+ data[2] = 4 + ch - 'a';
+
+ return 0;
+}
+
+static int sandbox_keyb_bind(struct udevice *dev)
+{
+ struct sandbox_keyb_plat *plat = dev_get_platdata(dev);
+ struct usb_string *fs;
+
+ fs = plat->keyb_strings;
+ fs[0].id = STRINGID_MANUFACTURER;
+ fs[0].s = "sandbox";
+ fs[1].id = STRINGID_PRODUCT;
+ fs[1].s = "keyboard";
+ fs[2].id = STRINGID_SERIAL;
+ fs[2].s = dev->name;
+
+ return usb_emul_setup_device(dev, PACKET_SIZE_8, plat->keyb_strings,
+ keyb_desc_list);
+}
+
+static int sandbox_keyb_probe(struct udevice *dev)
+{
+ struct sandbox_keyb_priv *priv = dev_get_priv(dev);
+
+ return membuff_new(&priv->in, 256);
+}
+
+static const struct dm_usb_ops sandbox_usb_keyb_ops = {
+ .control = sandbox_keyb_control,
+ .interrupt = sandbox_keyb_interrupt,
+};
+
+static const struct udevice_id sandbox_usb_keyb_ids[] = {
+ { .compatible = "sandbox,usb-keyb" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_sandbox_keyb) = {
+ .name = "usb_sandbox_keyb",
+ .id = UCLASS_USB_EMUL,
+ .of_match = sandbox_usb_keyb_ids,
+ .bind = sandbox_keyb_bind,
+ .probe = sandbox_keyb_probe,
+ .ops = &sandbox_usb_keyb_ops,
+ .priv_auto_alloc_size = sizeof(struct sandbox_keyb_priv),
+ .platdata_auto_alloc_size = sizeof(struct sandbox_keyb_plat),
+};
return upto ? upto : length ? -EIO : 0;
}
-int usb_emul_find(struct udevice *bus, ulong pipe, struct udevice **emulp)
+static int usb_emul_find_devnum(int devnum, struct udevice **emulp)
{
- int devnum = usb_pipedevice(pipe);
struct udevice *dev;
struct uclass *uc;
int ret;
return -ENOENT;
}
+int usb_emul_find(struct udevice *bus, ulong pipe, struct udevice **emulp)
+{
+ int devnum = usb_pipedevice(pipe);
+
+ return usb_emul_find_devnum(devnum, emulp);
+}
+
+int usb_emul_find_for_dev(struct udevice *dev, struct udevice **emulp)
+{
+ struct usb_dev_platdata *udev = dev_get_parent_platdata(dev);
+
+ return usb_emul_find_devnum(udev->devnum, emulp);
+}
+
int usb_emul_control(struct udevice *emul, struct usb_device *udev,
unsigned long pipe, void *buffer, int length,
struct devrequest *setup)
return ops->bulk(emul, udev, pipe, buffer, length);
}
+int usb_emul_int(struct udevice *emul, struct usb_device *udev,
+ unsigned long pipe, void *buffer, int length, int interval)
+{
+ struct dm_usb_ops *ops = usb_get_emul_ops(emul);
+
+ if (!ops->interrupt)
+ return -ENOSYS;
+ debug("%s: dev=%s\n", __func__, emul->name);
+
+ return ops->interrupt(emul, udev, pipe, buffer, length, interval);
+}
+
int usb_emul_setup_device(struct udevice *dev, int maxpacketsize,
struct usb_string *strings, void **desc_list)
{
*/
#include <common.h>
+#include <console.h>
#include <asm/errno.h>
#include <linux/netdevice.h>
#include <linux/usb/ch9.h>
#include <config.h>
#include <malloc.h>
#include <common.h>
+#include <console.h>
#include <g_dnl.h>
#include <linux/err.h>
#include <errno.h>
#include <common.h>
+#include <console.h>
#include <malloc.h>
#include <memalign.h>
#include <version.h>
*/
#include <common.h>
+#include <console.h>
#include <usb.h>
#include <asm/io.h>
return ret;
}
+static int sandbox_submit_int(struct udevice *bus, struct usb_device *udev,
+ unsigned long pipe, void *buffer, int length,
+ int interval)
+{
+ struct udevice *emul;
+ int ret;
+
+ /* Just use child of dev as emulator? */
+ debug("%s: bus=%s\n", __func__, bus->name);
+ ret = usb_emul_find(bus, pipe, &emul);
+ usbmon_trace(bus, pipe, NULL, emul);
+ if (ret)
+ return ret;
+ ret = usb_emul_int(emul, udev, pipe, buffer, length, interval);
+
+ return ret;
+}
+
static int sandbox_alloc_device(struct udevice *dev, struct usb_device *udev)
{
return 0;
static const struct dm_usb_ops sandbox_usb_ops = {
.control = sandbox_submit_control,
.bulk = sandbox_submit_bulk,
+ .interrupt = sandbox_submit_int,
.alloc_device = sandbox_alloc_device,
};
ret = device_remove(bus);
if (ret && !err)
err = ret;
- ret = device_unbind_children(bus);
- if (ret && !err)
- err = ret;
}
#ifdef CONFIG_SANDBOX
printf("%d USB Device(s) found\n", priv->next_addr);
}
+static void remove_inactive_children(struct uclass *uc, struct udevice *bus)
+{
+ uclass_foreach_dev(bus, uc) {
+ struct udevice *dev, *next;
+
+ if (!device_active(bus))
+ continue;
+ device_foreach_child_safe(dev, next, bus) {
+ if (!device_active(dev))
+ device_unbind(dev);
+ }
+ }
+}
+
int usb_init(void)
{
int controllers_initialized = 0;
}
debug("scan end\n");
+
+ /* Remove any devices that were not found on this scan */
+ remove_inactive_children(uc, bus);
+
+ ret = uclass_get(UCLASS_USB_HUB, &uc);
+ if (ret)
+ return ret;
+ remove_inactive_children(uc, bus);
+
/* if we were not able to find at least one working bus, bail out */
if (!count)
printf("No controllers found\n");
return usb_started ? 0 : -1;
}
+/*
+ * TODO(sjg@chromium.org): Remove this legacy function. At present it is needed
+ * to support boards which use driver model for USB but not Ethernet, and want
+ * to use USB Ethernet.
+ *
+ * The #if clause is here to ensure that remains the only case.
+ */
+#if !defined(CONFIG_DM_ETH) && defined(CONFIG_USB_HOST_ETHER)
static struct usb_device *find_child_devnum(struct udevice *parent, int devnum)
{
struct usb_device *udev;
return find_child_devnum(dev, devnum);
}
+#endif
int usb_post_bind(struct udevice *dev)
{
}
/**
- * usb_find_emul_child() - Find an existing device for emulated devices
+ * usb_find_child() - Find an existing device which matches our needs
+ *
+ *
*/
-static int usb_find_emul_child(struct udevice *parent,
- struct usb_device_descriptor *desc,
- struct usb_interface_descriptor *iface,
- struct udevice **devp)
+static int usb_find_child(struct udevice *parent,
+ struct usb_device_descriptor *desc,
+ struct usb_interface_descriptor *iface,
+ struct udevice **devp)
{
-#ifdef CONFIG_SANDBOX
struct udevice *dev;
*devp = NULL;
return 0;
}
}
-#endif
+
return -ENOENT;
}
debug("read_descriptor for '%s': ret=%d\n", parent->name, ret);
if (ret)
return ret;
- ret = usb_find_emul_child(parent, &udev->descriptor, iface, &dev);
- debug("** usb_find_emul_child returns %d\n", ret);
+ ret = usb_find_child(parent, &udev->descriptor, iface, &dev);
+ debug("** usb_find_child returns %d\n", ret);
if (ret) {
if (ret != -ENOENT)
return ret;
#include <common.h>
+#include <console.h>
#include <watchdog.h>
#ifdef CONFIG_ARCH_SUNXI
#include <asm/arch/usb_phy.h>
writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
}
+/******************************************************************************
+ * Needed for the DFU polling magic
+ ******************************************************************************/
+
+static u8 last_int_usb;
+
+bool dfu_usb_get_reset(void)
+{
+ return !!(last_int_usb & MUSB_INTR_RESET);
+}
+
/******************************************************************************
* MUSB Glue code
******************************************************************************/
/* read and flush interrupts */
musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
+ last_int_usb = musb->int_usb;
if (musb->int_usb)
musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
* logo can be placed in the upper left corner and additional board
* information strings (that normally goes to serial port) can be drawn.
*
- * The console driver can use the standard PC keyboard interface (i8042)
- * for character input. Character output goes to a memory mapped video
+ * The console driver can use a keyboard interface for character input
+ * but this is deprecated. Only rk51 uses it.
+ *
+ * Character output goes to a memory-mapped video
* framebuffer with little or big-endian organisation.
* With environment setting 'console=serial' the console i/o can be
* forced to serial port.
* VIDEO_DATA_FORMAT - graphical data format GDF
* VIDEO_FB_ADRS - start of video memory
*
- * CONFIG_I8042_KBD - AT Keyboard driver for i8042
* VIDEO_KBD_INIT_FCT - init function for keyboard
* VIDEO_TSTC_FCT - keyboard_tstc function
* VIDEO_GETC_FCT - keyboard_getc function
*
- * CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with
- * delay loop in VIDEO_TSTC_FCT (i8042)
- *
- * CONFIG_SYS_CONSOLE_BLINK_COUNT - value for delay loop - blink rate
- * CONFIG_CONSOLE_TIME - display time/date in upper right
- * corner, needs CONFIG_CMD_DATE and
- * CONFIG_CONSOLE_CURSOR
* CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner.
* Use CONFIG_SPLASH_SCREEN_ALIGN with
* environment variable "splashpos" to place
#define VIDEO_DATA_FORMAT (pGD->gdfIndex)
#define VIDEO_FB_ADRS (pGD->frameAdrs)
-/*
- * Console device defines with i8042 keyboard controller
- * Any other keyboard controller must change this section
- */
-
-#ifdef CONFIG_I8042_KBD
-#include <i8042.h>
-
-#define VIDEO_KBD_INIT_FCT i8042_kbd_init()
-#define VIDEO_TSTC_FCT i8042_tstc
-#define VIDEO_GETC_FCT i8042_getc
-#endif
-
/*
* Console device
*/
/*
* Cursor definition:
- * CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c)
- * to let the cursor blink. Uses the macros
- * CURSOR_OFF and CURSOR_ON.
* CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No
* blinking is provided. Uses the macros CURSOR_SET
* and CURSOR_OFF.
* must disable the hardware register of the graphic
* chip. Otherwise a blinking field is displayed
*/
-#if !defined(CONFIG_CONSOLE_CURSOR) && \
- !defined(CONFIG_VIDEO_SW_CURSOR) && \
- !defined(CONFIG_VIDEO_HW_CURSOR)
+#if !defined(CONFIG_VIDEO_SW_CURSOR) && !defined(CONFIG_VIDEO_HW_CURSOR)
/* no Cursor defined */
#define CURSOR_ON
#define CURSOR_OFF
#define CURSOR_SET
#endif
-#if defined(CONFIG_CONSOLE_CURSOR) || defined(CONFIG_VIDEO_SW_CURSOR)
-#if defined(CURSOR_ON) || \
- (defined(CONFIG_CONSOLE_CURSOR) && defined(CONFIG_VIDEO_SW_CURSOR))
-#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \
- or CONFIG_VIDEO_HW_CURSOR can be defined
+#if defined(CONFIG_VIDEO_SW_CURSOR)
+#if defined(CONFIG_VIDEO_HW_CURSOR)
+#error only one of CONFIG_VIDEO_SW_CURSOR or CONFIG_VIDEO_HW_CURSOR can be \
+ defined
#endif
void console_cursor(int state);
#define CURSOR_ON console_cursor(1)
#define CURSOR_OFF console_cursor(0)
#define CURSOR_SET video_set_cursor()
-#endif /* CONFIG_CONSOLE_CURSOR || CONFIG_VIDEO_SW_CURSOR */
-
-#ifdef CONFIG_CONSOLE_CURSOR
-#ifndef CONFIG_CONSOLE_TIME
-#error CONFIG_CONSOLE_CURSOR must be defined for CONFIG_CONSOLE_TIME
-#endif
-#ifndef CONFIG_I8042_KBD
-#warning Cursor drawing on/off needs timer function s.a. drivers/input/i8042.c
-#endif
-#endif /* CONFIG_CONSOLE_CURSOR */
-
+#endif /* CONFIG_VIDEO_SW_CURSOR */
#ifdef CONFIG_VIDEO_HW_CURSOR
#ifdef CURSOR_ON
-#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \
- or CONFIG_VIDEO_HW_CURSOR can be defined
+#error only one of CONFIG_VIDEO_SW_CURSOR or CONFIG_VIDEO_HW_CURSOR can be \
+ defined
#endif
#define CURSOR_ON
#define CURSOR_OFF
video_drawchars(xx, yy + video_logo_height, &c, 1);
}
-#if defined(CONFIG_CONSOLE_CURSOR) || defined(CONFIG_VIDEO_SW_CURSOR)
+#if defined(CONFIG_VIDEO_SW_CURSOR)
static void video_set_cursor(void)
{
if (cursor_state)
void console_cursor(int state)
{
-#ifdef CONFIG_CONSOLE_TIME
- struct rtc_time tm;
- char info[16];
-
- /* time update only if cursor is on (faster scroll) */
- if (state) {
- rtc_get(&tm);
-
- sprintf(info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min,
- tm.tm_sec);
- video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y, (uchar *) info);
-
- sprintf(info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon,
- tm.tm_year);
- video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
- VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT,
- (uchar *) info);
- }
-#endif
-
if (cursor_state != state) {
if (cursor_state) {
/* turn off the cursor */
#include "glue.h"
-/*
- * printf() and vprintf() are stolen from u-boot/common/console.c
- */
-int printf (const char *fmt, ...)
-{
- va_list args;
- uint i;
- char printbuffer[256];
-
- va_start (args, fmt);
-
- /* For this to work, printbuffer must be larger than
- * anything we ever want to print.
- */
- i = vsprintf (printbuffer, fmt, args);
- va_end (args);
-
- /* Print the string */
- ub_puts (printbuffer);
- return i;
-}
-
-int vprintf (const char *fmt, va_list args)
+void putc(const char c)
{
- uint i;
- char printbuffer[256];
-
- /* For this to work, printbuffer must be larger than
- * anything we ever want to print.
- */
- i = vsprintf (printbuffer, fmt, args);
-
- /* Print the string */
- ub_puts (printbuffer);
- return i;
+ ub_putc(c);
}
-void putc (const char c)
+void puts(const char *s)
{
- ub_putc(c);
+ ub_puts(s);
}
void __udelay(unsigned long usec)
#include <common.h>
+#include <console.h>
#include <exports.h>
DECLARE_GLOBAL_DATA_PTR;
*/
#include <common.h>
+#include <console.h>
#include <exports.h>
#include <linux/ctype.h>
#include "../drivers/net/smc911x.h"
if (status < 0)
return 0;
+ if (dirent.direntlen == 0) {
+ printf("Failed to iterate over directory %s\n", name);
+ return 0;
+ }
+
if (dirent.namelen != 0) {
char filename[dirent.namelen + 1];
struct ext2fs_node *fdiro;
*/
#ifndef __ASSEMBLY__
+#include <membuff.h>
#include <linux/list.h>
typedef struct global_data {
#endif
struct udevice *cur_serial_dev; /* current serial device */
struct arch_global_data arch; /* architecture-specific data */
+#ifdef CONFIG_CONSOLE_RECORD
+ struct membuff console_out; /* console output */
+ struct membuff console_in; /* console input */
+#endif
} gd_t;
#endif
#define GD_FLG_FULL_MALLOC_INIT 0x00200 /* Full malloc() is ready */
#define GD_FLG_SPL_INIT 0x00400 /* spl_init() has been called */
#define GD_FLG_SKIP_RELOC 0x00800 /* Don't relocate */
+#define GD_FLG_RECORD 0x01000 /* Record console */
#endif /* __ASM_GENERIC_GBL_DATA_H */
* @return 0 on success, or != 0 on error.
*/
int run_command_list(const char *cmd, int len, int flag);
-extern char console_buffer[];
/* arch/$(ARCH)/lib/board.c */
void board_init_f(ulong);
void fdc_hw_init (void);
/* $(BOARD)/eeprom.c */
-void eeprom_init (void);
-#ifndef CONFIG_SPI
-int eeprom_probe (unsigned dev_addr, unsigned offset);
-#endif
+void eeprom_init (int bus);
int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
unsigned int rand(void);
unsigned int rand_r(unsigned int *seedp);
-/* common/console.c */
-int console_init_f(void); /* Before relocation; uses the serial stuff */
-int console_init_r(void); /* After relocation; uses the console stuff */
-int console_assign(int file, const char *devname); /* Assign the console */
-int ctrlc (void);
-int had_ctrlc (void); /* have we had a Control-C since last clear? */
-void clear_ctrlc (void); /* clear the Control-C condition */
-int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */
-int confirm_yesno(void); /* 1 if input is "y", "Y", "yes" or "YES" */
/*
* STDIO based functions (can always be used)
*/
return string_to_ip(getenv(var));
}
-/*
- * CONSOLE multiplexing.
- */
-#ifdef CONFIG_CONSOLE_MUX
-#include <iomux.h>
-#endif
-
int pcmcia_init (void);
#ifdef CONFIG_STATUS_LED
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */
+#define CONFIG_SYS_NS16550_MEM32
/*
* Flash
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* I2C EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_CMD_I2C
-#define CONFIG_FSL_ESPI
/* eSPI - Enhanced SPI */
#ifdef CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
* used for SLIC
*/
/* eSPI - Enhanced SPI */
-#define CONFIG_FSL_ESPI /* SPI */
#ifdef CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* I2C EEPROM */
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_CMD_I2C
/* eSPI - Enhanced SPI */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_EON
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
# define CONFIG_SYS_DSPI_CS2
-# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
DSPI_CTAR_PCSSCK_1CLK | \
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
-# define CONFIG_SPI_FLASH_ATMEL
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
DSPI_CTAR_PCSSCK_1CLK | \
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI
-# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
DSPI_CTAR_PCSSCK_1CLK | \
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x13
#ifdef CONFIG_CMD_SPI
-# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
DSPI_CTAR_PCSSCK_1CLK | \
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */
-/************************************************************
- * Keyboard support
- ************************************************************/
-#undef CONFIG_ISA_KEYBOARD
-
/************************************************************
* Video support
************************************************************/
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#ifdef CONFIG_MPC8XXX_SPI
#define CONFIG_CMD_SPI
#define CONFIG_USE_SPIFLASH
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#endif
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
#if defined(CONFIG_SPI_FLASH)
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_CONSOLE_CURSOR*/
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_CONSOLE_CURSOR*/
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_CONSOLE_CURSOR*/
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_CONSOLE_CURSOR*/
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#endif
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
*/
#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
/* eSPI - Enhanced SPI */
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */
-/************************************************************
- * Keyboard support
- ************************************************************/
-#define CONFIG_ISA_KEYBOARD
-
/************************************************************
* Video support
************************************************************/
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
#endif
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_BAR
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
#if defined(CONFIG_T1024RDB)
-#define CONFIG_SPI_FLASH_STMICRO
#elif defined(CONFIG_T1023RDB)
-#define CONFIG_SPI_FLASH_SPANSION
#endif
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_BAR
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
* eSPI - Enhanced SPI
*/
#ifdef CONFIG_SPI_FLASH
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
#endif
#define CONFIG_CMD_SF
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
* eSPI - Enhanced SPI
*/
#ifdef CONFIG_SPI_FLASH
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */
/* I2C RTC */
#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SST 1
-#define CONFIG_SPI_FLASH_STMICRO 1
-#define CONFIG_SPI_FLASH_WINBOND 1
#define CONFIG_CMD_SF 1
#define CONFIG_CMD_SPI 1
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
#define CONFIG_BAUDRATE 38400
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
#define CONFIG_SYS_NS16550_REG_SIZE -4
/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_QUAD
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* PMIC support */
#define CONFIG_POWER_TPS65217
/* SPI flash. */
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_SPEED 24000000
/* Network. */
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#include <asm/arch/omap.h>
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK 48000000
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#else
-#define CONFIG_OMAP_SERIAL
#endif
/* I2C Configuration */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* Power */
#define CONFIG_POWER
/* SPI */
#undef CONFIG_OMAP3_SPI
-#define CONFIG_TI_QSPI
-#define CONFIG_SPI_FLASH_MACRONIX
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_TI_SPI_MMAP
#define CONFIG_QSPI_SEL_GPIO 48
#define CONFIG_SF_DEFAULT_SPEED 48000000
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
+#define CONFIG_QSPI_QUAD_SUPPORT
+#define CONFIG_TI_EDMA3
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
/*
* UART
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_MTD
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/* DataFlash */
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_3
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
/* DataFlash */
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_SYS_ICACHE_LINESZ 32
#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_SYS_ICACHE_LINESZ 32
* UART configuration
*/
#define CONFIG_DW_SERIAL
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK 33333333
#define CONFIG_SYS_NS16550_MEM32
/*
* EEPROM configuration
*/
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
/* SPI flash. */
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_SPEED 24000000
/* Network. */
#define CONFIG_MMC_SDMA
#define CONFIG_CMD_MMC
-/* BayTrail IGD support */
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x006ff000
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
/* Serial Info */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
/* Post pad 3 bytes after each reg addr */
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_ENV_OVERWRITE
/* Serial Info */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_MMC_ENV_PART 2
/* SPI */
-#define CONFIG_TEGRA20_SLINK
#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
/*
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_HZ 30000000
-#define CONFIG_SPI_FLASH_EON
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_SST
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_SF_DEFAULT_SPEED 10000000
-#define CONFIG_SPI_FLASH_ATMEL
/*
* SPI Settings
*/
#ifdef CONFIG_SPI_FLASH_ALL
-# define CONFIG_SPI_FLASH_ATMEL
-# define CONFIG_SPI_FLASH_EON
-# define CONFIG_SPI_FLASH_MACRONIX
-# define CONFIG_SPI_FLASH_SPANSION
-# define CONFIG_SPI_FLASH_SST
-# define CONFIG_SPI_FLASH_STMICRO
-# define CONFIG_SPI_FLASH_WINBOND
#endif
/*
/* SPI FLASH */
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
/* For the M25P64 SCK Should be Kept < 15Mhz */
#define CONFIG_ENV_SPI_MAX_HZ 15000000
#define CONFIG_SF_DEFAULT_SPEED 15000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
* FLASH organization and environment definitions
#define CONFIG_ENV_SPI_MAX_HZ 15000000
#define CONFIG_SF_DEFAULT_SPEED 15000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
* Interactive command settings
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#include <asm/arch/omap.h>
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_MMC_ENV_PART 2
/* SPI */
-#define CONFIG_TEGRA20_SLINK
#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
/* Avoid a warning in the Realtek Ethernet driver */
#define CONFIG_SYS_CACHELINE_SIZE 16
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-
#endif /* __CONFIG_H */
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#include <asm/arch/omap.h>
/* Serial support */
-#define CONFIG_OMAP_SERIAL
#define CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_NS16550_COM1 0x44e09000
/* SPI Flash support */
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_EON
-#define CONFIG_SPI_FLASH_GIGADEVICE
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_TI_SPI_MMAP
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SF_DEFAULT_SPEED 48000000
#ifdef CONFIG_OF_CONTROL
#define CONFIG_DM_SPI
#define CONFIG_CMD_SPI
-#define CONFIG_FSL_DSPI
#endif
#endif /* __CONFIG_H */
* Serial Port
*/
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_PCI_PNP
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_MMC
#define CONFIG_SDHCI
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
/*
* General PCI
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-#define CONFIG_SPI_FLASH_STMICRO
/*
* SDIO/MMC Card Configuration
/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-#define CONFIG_SPI_FLASH_STMICRO
/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
/* SPI */
#undef CONFIG_OMAP3_SPI
-#define CONFIG_TI_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_TI_SPI_MMAP
#ifdef CONFIG_CMD_SF
#define CONFIG_HARD_SPI 1
#define CONFIG_KIRKWOOD_SPI 1
-#define CONFIG_SPI_FLASH_MACRONIX 1
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#undef CONFIG_CMD_IMLS
-#undef CONFIG_SYS_NS16550
#undef CONFIG_X86_SERIAL
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
/* 512kB DataFlash at NPCS0 */
#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
#define CONFIG_HAS_DATAFLASH
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_ATMEL_DATAFLASH_SPI
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
#define DATAFLASH_TCSS (0x1a << 16)
/* SPI */
#ifdef CONFIG_SPI_FLASH
-#define CONFIG_EXYNOS_SPI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 50000000
#endif
* Serial Port
*/
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
/* SH Ether */
#define CONFIG_SH_ETHER
/* Flash Support */
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_ATMEL
/*
* mv-common.h should be defined after CMD configs since it used them
#define CONFIG_MXC_SPI
#define CONFIG_SPI_FLASH_MTD
#define CONFIG_SPI_FLASH_BAR
- #define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
/* GPIO 3-19 (21248) */
* Serial Port
*/
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
/*
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
#define CONFIG_SYS_MMC_ENV_PART 2
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
#define IIC0_BOOTPROM_ADDR 0x50
#define IIC0_ALT_BOOTPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0x50)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_KM_COMMON_ETH_INIT
/* EEprom support 24C08, 24C16, 24C64 */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#define CONFIG_SYS_I2C_SOFT_SPEED 100000
/* EEprom support 24C128, 24C256 valid for environment eeprom */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_SPI_FLASH_STMICRO
/* SPI bus claim MPP configuration */
#define CONFIG_SYS_KW_SPI_MPP 0x0
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* eSPI - Enhanced SPI
*/
-#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
/* SH Ether */
#define CONFIG_SH_ETHER
/* SPI */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SYS_NO_FLASH
/* SH Ether */
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* SPI */
#ifdef CONFIG_QSPI_BOOT
/* QSPI */
-#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE 0x40000000
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SPI_FLASH_SPANSION
/* DSPI */
-#define CONFIG_FSL_DSPI
/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* SPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
-#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE 0x40000000
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SPI_FLASH_STMICRO
/* DSPI */
-#define CONFIG_FSL_DSPI
-#define CONFIG_SPI_FLASH_ATMEL
#endif
/* DM SPI */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#ifdef CONFIG_FSL_DSPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
#endif
/*
#ifdef CONFIG_FSL_DSPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
#endif
#define CONFIG_SUPPORT_RAW_INITRD
/* ST M25P40 */
-#undef CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_STMICRO
#undef CONFIG_ENV_SPI_MAX_HZ
#define CONFIG_ENV_SPI_MAX_HZ 25000000
#undef CONFIG_SF_DEFAULT_SPEED
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
* Serial Port
*/
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
/* EEPROM */
#ifdef CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#endif
/* SPI FLASH */
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
*/
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (115200 * 16)
/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SPANSION
/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
# define CONSOLE_ARG "console=console=ttyUL0,115200\0"
#elif XILINX_UART16550_BASEADDR
-# define CONFIG_SYS_NS16550 1
# define CONFIG_SYS_NS16550_SERIAL
# if defined(__MICROBLAZEEL__)
# define CONFIG_SYS_NS16550_REG_SIZE -4
#ifdef SPIFLASH
# define CONFIG_SYS_NO_FLASH 1
# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
-# define CONFIG_XILINX_SPI 1
# define CONFIG_SPI 1
-# define CONFIG_SPI_FLASH_STMICRO 1
# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_FIT_SIGNATURE
#define CONFIG_RSA
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */
/*
* RTC configuration
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/*
* NS16550 Configuration
*/
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL)
-#define CONFIG_DW_SERIAL
-#endif
-
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#if !defined(CONFIG_DM_SERIAL)
* Common SPI Flash configuration
*/
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_MACRONIX 1
#endif
/*
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
/* this may vary and depends on the installed chip */
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#endif
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_CMD_TIME
-#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SYS_FSL_QSPI_LE
#define CONFIG_SYS_FSL_QSPI_AHB
#ifdef CONFIG_MX6SX_SABRESD_REVA
#define CONFIG_CMD_CACHE
#endif
-#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
* set Linux BASE_BAUD to 403200.
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
--- /dev/null
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ * Luka Perkov <luka.perkov@sartura.hr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_NSA310S_H
+#define _CONFIG_NSA310S_H
+
+/* high level configuration options */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KW88F6192 1 /* SOC Name */
+#define CONFIG_KW88F6702 1 /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
+/* add target to build it automatically upon "make" */
+#define CONFIG_BUILD_TARGET "u-boot.kwb"
+
+/* compression configuration */
+#define CONFIG_BZIP2
+#define CONFIG_LZMA
+
+/* commands configuration */
+#define CONFIG_SYS_NO_FLASH /* declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* environment variables configuration */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_OFFSET 0xe0000
+
+/* default environment variables */
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+ "ubi part root; " \
+ "ubifsmount ubi:rootfs; " \
+ "ubifsload 0x800000 ${kernel}; " \
+ "ubifsload 0x700000 ${fdt}; " \
+ "ubifsumount; " \
+ "fdt addr 0x700000; fdt resize; fdt chosen; " \
+ "bootz 0x800000 - 0x700000"
+
+#define CONFIG_MTDPARTS \
+ "mtdparts=orion_nand:" \
+ "0xe0000@0x0(uboot)," \
+ "0x20000@0xe0000(uboot_env)," \
+ "0x100000@0x100000(second_stage_uboot)," \
+ "-@0x200000(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=console=ttyS0,115200\0" \
+ "mtdids=nand0=orion_nand\0" \
+ "mtdparts="CONFIG_MTDPARTS \
+ "kernel=/boot/zImage\0" \
+ "fdt=/boot/nsa310s.dtb\0" \
+ "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0"
+
+/* Ethernet driver configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 1
+#define CONFIG_PHY_GIGE
+#define CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/* SATA driver configuration */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
+#endif /* CONFIG_CMD_IDE */
+
+/* RTC driver configuration */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_NSA310S_H */
#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* NS16550 Configuration
*/
-#undef CONFIG_OMAP_SERIAL
+#undef CONFIG_SYS_NS16550_CLK
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* Serial Driver info
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
/*
* SERIAL
*/
-# define CONFIG_SYS_NS16550
# define CONFIG_SYS_NS16550_SERIAL
# define CONFIG_SYS_NS16550_REG_SIZE 1
# define CONFIG_CONS_INDEX 1
/* SF Configs */
#define CONFIG_CMD_SF
#define CONFIG_SPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
#if defined(CONFIG_SPI_FLASH)
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* enable read and write access to EEPROM */
#define CONFIG_CMD_EEPROM
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
-#define CONFIG_FSL_ESPI
#if defined(CONFIG_PCI)
/*
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ (8 * 1024 * 1024))
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
#define CONFIG_PHY_MICREL
/* QSPI Configs*/
-#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SYS_FSL_QSPI_LE
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* SPL */
#define CONFIG_SPL_POWER_SUPPORT
/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_QUAD
#define CONFIG_SYS_NO_FLASH
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
/*
#define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_NE2000_BASE 0xb4000300
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 115200
#define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 115200
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
#define CONFIG_PCI_PNP
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
#undef CONFIG_INTEL_ICH6_GPIO
/* SPI is not supported */
-#undef CONFIG_ICH_SPI
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_CMD_I2C
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_SPEED 30000000
#endif
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
#define CONFIG_ATMEL_SPI0
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 30000000
#ifdef CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
#define CONFIG_ATMEL_SPI0
-#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_IO_TRACE
#define CONFIG_CMD_IOTRACE
+#ifndef CONFIG_TIMER
#define CONFIG_SYS_TIMER_RATE 1000000
+#endif
#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_LONGHELP /* #undef to save memory */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SILENT_CONSOLE
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_CMD_SF
#define CONFIG_CMD_SF_TEST
#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_EON
-#define CONFIG_SPI_FLASH_GIGADEVICE
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_I2C
#define CONFIG_I2C_EDID
#define CONFIG_KEYBOARD
-#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb\0" \
+#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \
"stdout=serial,lcd\0" \
"stderr=serial,lcd\0"
#else
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
/* SPI */
#define CONFIG_SH_SPI 1
#define CONFIG_SH_SPI_BASE 0xfe002000
-#define CONFIG_SPI_FLASH_STMICRO 1
-#define CONFIG_SPI_FLASH_MACRONIX 1
/* MMCIF */
#define CONFIG_MMC 1
/* SPI */
#define CONFIG_SH_SPI 1
#define CONFIG_SH_SPI_BASE 0xfe002000
-#define CONFIG_SPI_FLASH_STMICRO 1
-#define CONFIG_SPI_FLASH_MACRONIX 1
/* MMCIF */
#define CONFIG_MMC 1
/* SPI */
#define CONFIG_SH_SPI 1
#define CONFIG_SH_SPI_BASE 0xfe002000
-#define CONFIG_SPI_FLASH_STMICRO 1
/* MMCIF */
#define CONFIG_MMC 1
#define CONFIG_SPI
#define CONFIG_OMAP3_SPI
#define CONFIG_MTD_DEVICE
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED (75000000)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_QUAD
#define CONFIG_SYS_NO_FLASH
*/
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_OMAP_SERIAL
-#else
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#endif
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_CONS_INDEX 3
#define CONFIG_SERIAL3 3
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
/*
* The base address is configurable in QSys, each board must specify the
/*
* QSPI support
*/
-#define CONFIG_CADENCE_QSPI
/* Enable multiple SPI NOR flash manufacturers */
-#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
-#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
#define CONFIG_CMD_MTDPARTS
/*
* Designware SPI support
*/
-#define CONFIG_DESIGNWARE_SPI
#define CONFIG_CMD_SPI
/*
* Serial Driver
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
/* SPI */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_QUAD
#define CONFIG_SYS_NO_FLASH
* Serial Port
*/
#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+ * QSPI support
+ */
#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
-#define CONFIG_CADENCE_QSPI
#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
-#define CONFIG_SPI_FLASH_WINBOND /* WINBOND */
#define CONFIG_CMD_SF
#endif
#define CONFIG_ARMV7_PSCI_NR_CPUS 2
#elif defined(CONFIG_MACH_SUN8I_A33)
#define CONFIG_ARMV7_PSCI_NR_CPUS 4
+#elif defined(CONFIG_MACH_SUN8I_H3)
+#define CONFIG_ARMV7_PSCI_NR_CPUS 4
#else
#error Unsupported sun8i variant
#endif
#endif
/* Serial & console */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
/* ns16550 reg in the low bits of cpu reg */
#define CONFIG_SYS_NS16550_CLK 24000000
-#ifdef CONFIG_DM_SERIAL
-# define CONFIG_DW_SERIAL
-#else
+#ifndef CONFIG_DM_SERIAL
# define CONFIG_SYS_NS16550_REG_SIZE -4
# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#endif
#define CONFIG_G_DNL_MANUFACTURER "Allwinner Technology"
#endif
+#ifdef CONFIG_USB_FUNCTION_DFU
+#define CONFIG_CMD_DFU
+#define CONFIG_DFU_RAM
+#endif
+
#ifdef CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
* 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
* 1M script, 1M pxe and the ramdisk at the end.
*/
+
+#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
+#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
+#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
+
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0xa000000\0" \
- "kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \
- "fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \
- "scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \
- "pxefile_addr_r=" __stringify(SDRAM_OFFSET(3200000)) "\0" \
- "ramdisk_addr_r=" __stringify(SDRAM_OFFSET(3300000)) "\0"
+ "kernel_addr_r=" KERNEL_ADDR_R "\0" \
+ "fdt_addr_r=" FDT_ADDR_R "\0" \
+ "scriptaddr=" SCRIPT_ADDR_R "\0" \
+ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
+ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0"
+
+#define DFU_ALT_INFO_RAM \
+ "dfu_alt_info_ram=" \
+ "kernel ram " KERNEL_ADDR_R " 0x1000000;" \
+ "fdt ram " FDT_ADDR_R " 0x100000;" \
+ "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0"
#ifdef CONFIG_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONSOLE_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
+ DFU_ALT_INFO_RAM \
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"console=ttyS0,115200\0" \
BOOTCMD_SUNXI_COMPAT \
*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_ATMEL_SPI
-#define CONFIG_SPI_FLASH_STMICRO
#define TAURUS_SPI_MASK (1 << 4)
#define TAURUS_SPI_CS_PIN AT91_PIN_PA3
/*
* UART configuration
*/
-#define CONFIG_DW_SERIAL
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK 166666666
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_MMC_ENV_PART 2
/* SPI */
-#define CONFIG_TEGRA20_SLINK
#define CONFIG_TEGRA_SLINK_CTRLS 6
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
/*
* NS16550 Configuration
*/
-#define CONFIG_TEGRA_SERIAL
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* Common HW configuration.
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
/*
* NS16550 Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_OMAP_SERIAL
-#endif
-
#include <asm/arch/omap.h>
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
/* UART Configuration */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
-#else
-#define CONFIG_KEYSTONE_SERIAL
#endif
#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
#endif
/* SPI Configuration */
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED 30000000
"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \
- "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
+ "burn_uboot_spi=sf probe; sf erase 0 0x80000; " \
"sf write ${loadaddr} 0 ${filesize}\0" \
"burn_uboot_nand=nand erase 0 0x100000; " \
"nand write ${loadaddr} 0 ${filesize}\0" \
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
-#ifndef CONFIG_SPL_BUILD
-# define CONFIG_OMAP_SERIAL
-#endif
-
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
/* NS16550 Configuration */
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#ifdef CONFIG_SPL_BUILD
# define CONFIG_SYS_NS16550_SERIAL
# define CONFIG_SYS_NS16550_REG_SIZE (-4)
-# define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#endif
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
/*
* Hardware drivers
*/
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK 48000000
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
-#else
-#define CONFIG_OMAP_SERIAL
#endif
#define CONFIG_CONS_INDEX 3
/*
* Hardware drivers
*/
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_CLK 48000000
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK 48000000
-#else
-#define CONFIG_OMAP_SERIAL
#endif
/*
#define CONFIG_MXC_SPI
/* SPI Flash */
-#define CONFIG_SPI_FLASH_STMICRO
#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
/* EEPROM */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_BUS_NUM 1
#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
/* SPI */
-#define CONFIG_TEGRA20_SFLASH
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_OMAP3_SPI
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#ifdef CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
#define CONFIG_SYS_NS16550_CLK 12288000
#define CONFIG_SYS_NS16550_REG_SIZE -2
#endif
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 UART_1_BASE
#define CONFIG_CONS_INDEX 1
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* SPI */
-#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_TEXT_BASE 0xe0000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
-#else
-#error "Unknown board variant"
#endif
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define GICD_BASE (0x2C010000)
#define GICC_BASE (0x2C02f000)
-#else
-#error "Unknown board variant"
#endif
#endif /* !CONFIG_GICV3 */
#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
-#define PHYS_SDRAM_2 (0x880000000)
/* Top 16MB reserved for secure world use */
#define DRAM_SEC_SIZE 0x01000000
#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
-#define PHYS_SDRAM_2_SIZE 0x180000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_NR_DRAM_BANKS 2
+#define PHYS_SDRAM_2 (0x880000000)
+#define PHYS_SDRAM_2_SIZE 0x180000000
+#else
+#define CONFIG_NR_DRAM_BANKS 1
+#endif
+
/* Enable memtest */
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_BOOTDELAY 1
-#else
-#error "Unknown board variant"
#endif
-/* Do not preserve environment */
-#define CONFIG_ENV_IS_NOWHERE 1
-#define CONFIG_ENV_SIZE 0x1000
-
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS 64 /* max command args */
-/* Flash memory is available on the Juno board only */
-#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
-#define CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_FLASH_BASE 0x08000000
+/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT 259
+/* Store environment at top of flash in the same location as blank.img */
+/* in the Juno firmware. */
+#define CONFIG_ENV_ADDR 0x0BFC0000
+#define CONFIG_ENV_SECT_SIZE 0x00010000
#else
+#define CONFIG_SYS_FLASH_BASE 0x0C000000
+/* 256 x 256KiB sectors */
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+/* Store environment at top of flash */
+#define CONFIG_ENV_ADDR 0x0FFC0000
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#endif
+
#define CONFIG_CMD_ARMFLASH
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
-#define CONFIG_SYS_FLASH_BASE 0x08000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
-/* Timeout values in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
-
-/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
-#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+#define FLASH_MAX_SECTOR_SIZE 0x00040000
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_IS_IN_FLASH 1
-#endif
#endif /* __VEXPRESS_AEMV8A_H */
#define CONFIG_PHY_MICREL
/* QSPI Configs*/
-#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SYS_FSL_QSPI_LE
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x003f8000
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"
/*-----------------------------------------------------------------------
* Serial Configuration
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
9600, 19200, 38400, 115200}
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SW_CURSOR
#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_I8042_KBD
+#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CFB_CONSOLE
#define CONFIG_CONSOLE_SCROLL_LINES 5
/*-----------------------------------------------------------------------
* FLASH configuration
*/
-#define CONFIG_ICH_SPI
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SPI_FLASH_GIGADEVICE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CMD_SF
#define CONFIG_CMD_SF_TEST
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
#else
#ifdef XPAR_UARTNS550_0_BASEADDR
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 4
#define CONFIG_CONS_INDEX 1
/* SPI */
#ifdef CONFIG_ZYNQ_SPI
-# define CONFIG_SPI_FLASH_SST
# define CONFIG_CMD_SF
#endif
# define CONFIG_SDHCI
# define CONFIG_ZYNQ_SDHCI
# define CONFIG_CMD_MMC
+# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
+# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000
+# endif
#endif
#if defined(CONFIG_ZYNQ_SDHCI)
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHYLIB
# define CONFIG_PHY_MARVELL
+# define CONFIG_PHY_TI
#endif
/* I2C */
#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
#define CONFIG_ZYNQ_I2C0
#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_ZYNQ_EEPROM
* Serial Port
*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
/* SPI */
#ifdef CONFIG_ZYNQ_SPI
-# define CONFIG_SPI_FLASH_SST
# define CONFIG_CMD_SF
#endif
#ifdef CONFIG_ZYNQ_QSPI
# define CONFIG_SF_DEFAULT_SPEED 30000000
# define CONFIG_SPI_FLASH_ISSI
-# define CONFIG_SPI_FLASH_SPANSION
-# define CONFIG_SPI_FLASH_STMICRO
-# define CONFIG_SPI_FLASH_WINBOND
# define CONFIG_SPI_FLASH_BAR
# define CONFIG_CMD_SF
#endif
# define CONFIG_SDHCI
# define CONFIG_ZYNQ_SDHCI
# define CONFIG_CMD_MMC
+# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
#endif
#ifdef CONFIG_ZYNQ_USB
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
-#ifdef CONFIG_OF_CONTROL
+#ifdef CONFIG_OF_SEPARATE
# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
#else
# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
# define CONFIG_ZYNQ_GEM0
# define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
# define CONFIG_ZYNQ_SDHCI0
-# define CONFIG_ZYNQ_SPI
#elif defined(CONFIG_ZC770_XM011)
--- /dev/null
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONSOLE_H
+#define __CONSOLE_H
+
+extern char console_buffer[];
+
+/* common/console.c */
+int console_init_f(void); /* Before relocation; uses the serial stuff */
+int console_init_r(void); /* After relocation; uses the console stuff */
+int console_assign(int file, const char *devname); /* Assign the console */
+int ctrlc(void);
+int had_ctrlc(void); /* have we had a Control-C since last clear? */
+void clear_ctrlc(void); /* clear the Control-C condition */
+int disable_ctrlc(int); /* 1 to disable, 0 to enable Control-C detect */
+int confirm_yesno(void); /* 1 if input is "y", "Y", "yes" or "YES" */
+
+/**
+ * console_record_init() - set up the console recording buffers
+ *
+ * This should be called as soon as malloc() is available so that the maximum
+ * amount of console output can be recorded.
+ */
+int console_record_init(void);
+
+/**
+ * console_record_reset() - reset the console recording buffers
+ *
+ * Removes any data in the buffers
+ */
+void console_record_reset(void);
+
+/**
+ * console_record_reset_enable() - reset and enable the console buffers
+ *
+ * This should be called to enable the console buffer.
+ */
+void console_record_reset_enable(void);
+
+/*
+ * CONSOLE multiplexing.
+ */
+#ifdef CONFIG_CONSOLE_MUX
+#include <iomux.h>
+#endif
+
+#endif
* @param scan Place to put the scan results
* @return 0 if ok, -1 on error
*/
-int cros_ec_scan_keyboard(struct cros_ec_dev *dev, struct mbkp_keyscan *scan);
+int cros_ec_scan_keyboard(struct udevice *dev, struct mbkp_keyscan *scan);
/**
* Read which image is currently running on the CROS-EC device.
* @param dev CROS-EC device
* @return 0 if no interrupt is pending
*/
-int cros_ec_interrupt_pending(struct cros_ec_dev *dev);
+int cros_ec_interrupt_pending(struct udevice *dev);
enum {
CROS_EC_OK,
static inline int device_unbind(struct udevice *dev) { return 0; }
#endif
-/**
- * device_remove_children() - Stop all device's children
- * @dev: The device whose children are to be removed
- * @return 0 on success, -ve on error
- */
-#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
-int device_remove_children(struct udevice *dev);
-#else
-static inline int device_remove_children(struct udevice *dev) { return 0; }
-#endif
-
-/**
- * device_unbind_children() - Unbind all device's children from the device
- *
- * On error, the function continues to unbind all children, and reports the
- * first error.
- *
- * @dev: The device that is to be stripped of its children
- * @return 0 on success, -ve on error
- */
-#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
-int device_unbind_children(struct udevice *dev);
-#else
-static inline int device_unbind_children(struct udevice *dev) { return 0; }
-#endif
-
#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
void device_free(struct udevice *dev);
#else
return device_get_uclass_id(dev->parent) == UCLASS_PCI;
}
+/**
+ * device_foreach_child_safe() - iterate through child devices safely
+ *
+ * This allows the @pos child to be removed in the loop if required.
+ *
+ * @pos: struct udevice * for the current device
+ * @next: struct udevice * for the next device
+ * @parent: parent device to scan
+ */
+#define device_foreach_child_safe(pos, next, parent) \
+ list_for_each_entry_safe(pos, next, &parent->child_head, sibling_node)
+
/* device resource management */
typedef void (*dr_release_t)(struct udevice *dev, void *res);
typedef int (*dr_match_t)(struct udevice *dev, void *res, void *match_data);
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
UCLASS_I2C_GENERIC, /* Generic I2C device */
UCLASS_I2C_MUX, /* I2C multiplexer */
+ UCLASS_KEYBOARD, /* Keyboard input device */
UCLASS_LED, /* Light-emitting diode (LED) */
UCLASS_LPC, /* x86 'low pin count' interface */
UCLASS_MASS_STORAGE, /* Mass storage device */
#define uclass_foreach_dev(pos, uc) \
list_for_each_entry(pos, &uc->dev_head, uclass_node)
+/**
+ * uclass_foreach_dev_safe() - Helper function to safely iteration through devs
+ *
+ * This creates a for() loop which works through the available devices in
+ * a uclass in order from start to end. Inside the loop, it is safe to remove
+ * @pos if required.
+ *
+ * @pos: struct udevice * to hold the current device. Set to NULL when there
+ * are no more devices.
+ * @next: struct udevice * to hold the next next
+ * @uc: uclass to scan
+ */
+#define uclass_foreach_dev_safe(pos, next, uc) \
+ list_for_each_entry_safe(pos, next, &uc->dev_head, uclass_node)
+
#endif
COMPAT_UNKNOWN,
COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
- COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
COMPAT_NVIDIA_TEGRA124_DC, /* Tegra 124 Display controller */
struct udevice **devp);
/**
- * i2c_get_chip() - get a device to use to access a chip on a bus number
+ * i2c_get_chip_for_busnum() - get a device to use to access a chip on
+ * a bus number
*
* This returns the device for the given chip address on a particular bus
* number.
*/
int i8042_disable(void);
-struct stdio_dev;
-
-int i8042_kbd_init(void);
-int i8042_tstc(struct stdio_dev *dev);
-int i8042_getc(struct stdio_dev *dev);
-
#endif /* _I8042_H_ */
#define IH_TYPE_RKIMAGE 23 /* Rockchip Boot Image */
#define IH_TYPE_RKSD 24 /* Rockchip SD card */
#define IH_TYPE_RKSPI 25 /* Rockchip SPI image */
+#define IH_TYPE_ZYNQIMAGE 26 /* Xilinx Zynq Boot Image */
-#define IH_TYPE_COUNT 26 /* Number of image types */
+#define IH_TYPE_COUNT 27 /* Number of image types */
/*
* Compression Types
enum {
/* Keyboard LEDs */
INPUT_LED_SCROLL = 1 << 0,
- INPUT_LED_CAPS = 1 << 1,
- INPUT_LED_NUM = 1 << 2,
+ INPUT_LED_NUM = 1 << 1,
+ INPUT_LED_CAPS = 1 << 2,
};
/*
};
struct input_config {
+ struct udevice *dev;
uchar fifo[INPUT_BUFFER_LEN];
int fifo_in, fifo_out;
/* Which modifiers are active (1 bit for each MOD_... value) */
uchar modifiers;
uchar flags; /* active state keys (FLAGS_...) */
- uchar leds; /* active LEDS (INPUT_LED_...) */
+ uchar leds; /* active LEDs (INPUT_LED_...) */
+ uchar leds_changed; /* LEDs that just changed */
uchar num_tables; /* number of modifier tables */
int prev_keycodes[INPUT_BUFFER_LEN]; /* keys held last time */
int num_prev_keycodes; /* number of prev keys */
* unknown
*/
int (*read_keys)(struct input_config *config);
+ bool allow_repeats; /* Don't filter out repeats */
unsigned int next_repeat_ms; /* Next time we repeat a key */
unsigned int repeat_delay_ms; /* Time before autorepeat starts */
unsigned int repeat_rate_ms; /* Autorepeat rate in ms */
*/
int input_send_keycodes(struct input_config *config, int keycode[], int count);
+/**
+ * Add a new keycode to an existing list of keycodes
+ *
+ * This can be used to handle keyboards which do their own scanning. An
+ * internal list of depressed keys is maintained by the input library. Then
+ * this function is called to add a new key to the list (when a 'make code' is
+ * received), or remove a key (when a 'break code' is received).
+ *
+ * This function looks after maintenance of the list of active keys, and calls
+ * input_send_keycodes() with its updated list.
+ *
+ * @param config Input state
+ * @param new_keycode New keycode to add/remove
+ * @param release true if this key was released, false if depressed
+ * @return number of ascii characters sent, or 0 if none, or -1 for an
+ * internal error
+ */
+int input_add_keycode(struct input_config *config, int new_keycode,
+ bool release);
+
/**
* Add a new key translation table to the input
*
void input_set_delays(struct input_config *config, int repeat_delay_ms,
int repeat_rate_ms);
+/**
+ * Tell the input layer whether to allow the caller to determine repeats
+ *
+ * Generally the input library handles processing of a list of scanned keys.
+ * Repeated keys need to be generated based on a timer in this case, since all
+ * that is provided is a list of keys current depressed.
+ *
+ * Keyboards which do their own scanning will resend codes when they want to
+ * inject a repeating key. This function can be called at start-up to select
+ * this behaviour.
+ *
+ * @param config Input state
+ * @param allow_repeats true to repeat depressed keys every time
+ * input_send_keycodes() is called, false to do normal
+ * keyboard repeat processing with a timer.
+ */
+void input_allow_repeats(struct input_config *config, bool allow_repeats);
+
+/**
+ * Check if keyboard LEDs need to be updated
+ *
+ * This can be called after input_tstc() to see if keyboard LEDs need
+ * updating.
+ *
+ * @param config Input state
+ * @return -1 if no LEDs need updating, other value if they do
+ */
+int input_leds_changed(struct input_config *config);
+
+/**
+ * Set up the key map tables
+ *
+ * This must be called after input_init() or keycode decoding will not work.
+ *
+ * @param config Input state
+ * @param german true to use German keyboard layout, false for US
+ * @return 0 if ok, -1 on error
+ */
+int input_add_tables(struct input_config *config, bool german);
+
/**
* Set up the input handler with basic key maps.
*
#ifndef __KEYBOARD_H
#define __KEYBOARD_H
+#ifdef CONFIG_DM_KEYBOARD
+#include <input.h>
+#include <stdio_dev.h>
+
+/**
+ * struct keyboard_priv - information about a keyboard, for the uclass
+ *
+ * @sdev: stdio device
+ * @input: input configuration (the driver may use this if desired)
+ */
+struct keyboard_priv {
+ struct stdio_dev sdev;
+
+ /*
+ * This is set up by the uclass but will only be used if the driver
+ * sets input.dev to its device pointer (it is initially NULL).
+ */
+ struct input_config input;
+};
+
+/**
+ * struct keyboard_ops - keyboard device operations
+ */
+struct keyboard_ops {
+ /**
+ * start() - enable the keyboard ready for use
+ *
+ * @dev: Device to enable
+ * @return 0 if OK, -ve on error
+ */
+ int (*start)(struct udevice *dev);
+
+ /**
+ * stop() - disable the keyboard when no-longer needed
+ *
+ * @dev: Device to disable
+ * @return 0 if OK, -ve on error
+ */
+ int (*stop)(struct udevice *dev);
+
+ /**
+ * tstc() - check if a key is available
+ *
+ * @dev: Device to check
+ * @return 0 if no key is available, 1 if a key is available, -ve on
+ * error
+ */
+ int (*tstc)(struct udevice *dev);
+
+ /**
+ * getc() - get a key
+ *
+ * TODO(sjg@chromium.org): At present this method may wait if it calls
+ * input_getc().
+ *
+ * @dev: Device to read from
+ * @return -EAGAIN if no key is available, otherwise key value read
+ * (as ASCII).
+ */
+ int (*getc)(struct udevice *dev);
+
+ /**
+ * update_leds() - update keyboard LEDs
+ *
+ * This is called when the LEDs have changed and need to be updated.
+ * For example, if 'caps lock' is pressed then this method will be
+ * called with the new LED value.
+ *
+ * @dev: Device to update
+ * @leds: New LED mask (see INPUT_LED_... in input.h)
+ */
+ int (*update_leds)(struct udevice *dev, int leds);
+};
+
+#define keyboard_get_ops(dev) ((struct keyboard_ops *)(dev)->driver->ops)
+
+#else
+
#ifdef CONFIG_PS2MULT
#include <ps2mult.h>
#endif
extern void handle_scancode(unsigned char scancode);
extern int kbd_init_hw(void);
extern void pckbd_leds(unsigned char leds);
+#endif /* !CONFIG_DM_KEYBOARD */
+
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || \
+ defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+int ps2ser_check(void);
+#endif
#endif /* __KEYBOARD_H */
#define USB_DT_PIPE_USAGE 0x24
/* From the USB 3.0 spec */
#define USB_DT_SS_ENDPOINT_COMP 0x30
+/* From HID 1.11 spec */
+#define USB_DT_HID_REPORT 0x22
/* Conventional codes for class-specific descriptors. The convention is
* defined in the USB "Common Class" Spec (3.11). Individual class specs
__u8 bDescriptorType;
};
+struct __packed usb_class_hid_descriptor {
+ u8 bLength;
+ u8 bDescriptorType;
+ u16 bcdCDC;
+ u8 bCountryCode;
+ u8 bNumDescriptors; /* 0x01 */
+ u8 bDescriptorType0;
+ u16 wDescriptorLength0;
+ /* optional descriptors are not supported. */
+};
+
+struct __packed usb_class_report_descriptor {
+ u8 bLength; /* dummy */
+ u8 bDescriptorType;
+ u16 wLength;
+ u8 bData[0];
+};
+
/*
* Endpoints
*/
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * Copyright (c) 1992 Simon Glass
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MEMBUFF_H
+#define _MEMBUFF_H
+
+/**
+ * @struct membuff: holds the state of a membuff - it is used for input and
+ * output buffers. The buffer extends from @start to (@start + @size - 1).
+ * Data in the buffer extends from @tail to @head: it is written in at
+ * @head and read out from @tail. The membuff is empty when @head == @tail
+ * and full when adding another character would make @head == @tail. We
+ * therefore waste one character in the membuff to avoid having an extra flag
+ * to determine whether (when @head == @tail) the membuff is empty or full.
+ *
+ * xxxxxx data
+ * ...... empty
+ *
+ * .............xxxxxxxxxxxxxxxx.........................
+ * ^ ^
+ * tail head
+ *
+ * xxxxxxxxxxxxx................xxxxxxxxxxxxxxxxxxxxxxxxx
+ * ^ ^
+ * head tail
+ */
+struct membuff {
+ char *start; /** the start of the buffer */
+ char *end; /** the end of the buffer (start + length) */
+ char *head; /** current buffer head */
+ char *tail; /** current buffer tail */
+};
+
+/**
+ * membuff_purge() - reset a membuff to the empty state
+ *
+ * Initialise head and tail pointers so that the membuff becomes empty.
+ *
+ * @mb: membuff to purge
+ */
+void membuff_purge(struct membuff *mb);
+
+/**
+ * membuff_putraw() - find out where bytes can be written
+ *
+ * Work out where in the membuff some data could be written. Return a pointer
+ * to the address and the number of bytes which can be written there. If
+ * @update is true, the caller must then write the data immediately, since
+ * the membuff is updated as if the write has been done,
+ *
+ * Note that because the spare space in a membuff may not be contiguous, this
+ * function may not return @maxlen even if there is enough space in the
+ * membuff. However, by calling this function twice (with @update == true),
+ * you will get access to all the spare space.
+ *
+ * @mb: membuff to adjust
+ * @maxlen: the number of bytes we want to write
+ * @update: true to update the membuff as if the write happened, false to not
+ * @data: the address data can be written to
+ * @return number of bytes which can be written
+ */
+int membuff_putraw(struct membuff *mb, int maxlen, bool update, char **data);
+
+/**
+ * membuff_getraw() - find and return a pointer to available bytes
+ *
+ * Returns a pointer to any valid input data in the given membuff and
+ * optionally marks it as read. Note that not all input data may not be
+ * returned, since data is not necessarily contiguous in the membuff. However,
+ * if you call this function twice (with @update == true) you are guaranteed
+ * to get all available data, in at most two installments.
+ *
+ * @mb: membuff to adjust
+ * @maxlen: maximum number of bytes to get
+ * @update: true to update the membuff as if the bytes have been read (use
+ * false to check bytes without reading them)
+ * @data: returns address of data in input membuff
+ * @return the number of bytes available at *@data
+ */
+int membuff_getraw(struct membuff *mb, int maxlen, bool update, char **data);
+
+/**
+ * membuff_putbyte() - Writes a byte to a membuff
+ *
+ * @mb: membuff to adjust
+ * @ch: byte to write
+ * @return true on success, false if membuff is full
+ */
+bool membuff_putbyte(struct membuff *mb, int ch);
+
+/**
+ * @mb: membuff to adjust
+ * membuff_getbyte() - Read a byte from the membuff
+ * @return the byte read, or -1 if the membuff is empty
+ */
+int membuff_getbyte(struct membuff *mb);
+
+/**
+ * membuff_peekbyte() - check the next available byte
+ *
+ * Return the next byte which membuff_getbyte() would return, without
+ * removing it from the membuff.
+ *
+ * @mb: membuff to adjust
+ * @return the byte peeked, or -1 if the membuff is empty
+ */
+int membuff_peekbyte(struct membuff *mb);
+
+/**
+ * membuff_get() - get data from a membuff
+ *
+ * Copies any available data (up to @maxlen bytes) to @buff and removes it
+ * from the membuff.
+ *
+ * @mb: membuff to adjust
+ * @Buff: address of membuff to transfer bytes to
+ * @maxlen: maximum number of bytes to read
+ * @return the number of bytes read
+ */
+int membuff_get(struct membuff *mb, char *buff, int maxlen);
+
+/**
+ * membuff_put() - write data to a membuff
+ *
+ * Writes some data to a membuff. Returns the number of bytes added. If this
+ * is less than @lnehgt, then the membuff got full
+ *
+ * @mb: membuff to adjust
+ * @data: the data to write
+ * @length: number of bytes to write from 'data'
+ * @return the number of bytes added
+ */
+int membuff_put(struct membuff *mb, const char *buff, int length);
+
+/**
+ * membuff_isempty() - check if a membuff is empty
+ *
+ * @mb: membuff to check
+ * @return true if empty, else false
+ */
+bool membuff_isempty(struct membuff *mb);
+
+/**
+ * membuff_avail() - check available data in a membuff
+ *
+ * @mb: membuff to check
+ * @return number of bytes of data available
+ */
+int membuff_avail(struct membuff *mb);
+
+/**
+ * membuff_size() - get the size of a membuff
+ *
+ * Note that a membuff can only old data up to one byte less than its size.
+ *
+ * @mb: membuff to check
+ * @return total size
+ */
+int membuff_size(struct membuff *mb);
+
+/**
+ * membuff_makecontig() - adjust all membuff data to be contiguous
+ *
+ * This places all data in a membuff into a single contiguous lump, if
+ * possible
+ *
+ * @mb: membuff to adjust
+ * @return true on success
+ */
+bool membuff_makecontig(struct membuff *mb);
+
+/**
+ * membuff_free() - find the number of bytes that can be written to a membuff
+ *
+ * @mb: membuff to check
+ * @return returns the number of bytes free in a membuff
+ */
+int membuff_free(struct membuff *mb);
+
+/**
+ * membuff_readline() - read a line of text from a membuff
+ *
+ * Reads a line of text of up to 'maxlen' characters from a membuff and puts
+ * it in @str. Any character less than @minch is assumed to be the end of
+ * line character
+ *
+ * @mb: membuff to adjust
+ * @str: Place to put the line
+ * @maxlen: Maximum line length (excluding terminator)
+ * @return number of bytes read (including terminator) if a line has been
+ * read, 0 if nothing was there
+ */
+int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch);
+
+/**
+ * membuff_extend_by() - expand a membuff
+ *
+ * Extends a membuff by the given number of bytes
+ *
+ * @mb: membuff to adjust
+ * @by: Number of bytes to increase the size by
+ * @max: Maximum size to allow
+ * @return 0 if the expand succeeded, -ENOMEM if not enough memory, -E2BIG
+ * if the the size would exceed @max
+ */
+int membuff_extend_by(struct membuff *mb, int by, int max);
+
+/**
+ * membuff_init() - set up a new membuff using an existing membuff
+ *
+ * @mb: membuff to set up
+ * @buff: Address of buffer
+ * @size: Size of buffer
+ */
+void membuff_init(struct membuff *mb, char *buff, int size);
+
+/**
+ * membuff_uninit() - clear a membuff so it can no longer be used
+ *
+ * @mb: membuff to uninit
+ */
+void membuff_uninit(struct membuff *mb);
+
+/**
+ * membuff_new() - create a new membuff
+ *
+ * @mb: membuff to init
+ * @size: size of membuff to create
+ * @return 0 if OK, -ENOMEM if out of memory
+ */
+int membuff_new(struct membuff *mb, int size);
+
+/**
+ * membuff_dispose() - free memory allocated to a membuff and uninit it
+ *
+ * @mb: membuff to dispose
+ */
+void membuff_dispose(struct membuff *mb);
+
+#endif
* @return - '0' on success, otherwise error
*/
int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf);
+
+/**
+ * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header
+ * and partition table entries (PTE)
+ *
+ * As a side effect if sets gpt_head and gpt_pte so they point to GPT data.
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_head - pointer to GPT header data read from medium
+ * @param gpt_pte - pointer to GPT partition table enties read from medium
+ *
+ * @return - '0' on success, otherwise error
+ */
+int gpt_verify_headers(block_dev_desc_t *dev_desc, gpt_header *gpt_head,
+ gpt_entry **gpt_pte);
+
+/**
+ * gpt_verify_partitions() - Function to check if partitions' name, start and
+ * size correspond to '$partitions' env variable
+ *
+ * This function checks if on medium stored GPT data is in sync with information
+ * provided in '$partitions' environment variable. Specificially, name, start
+ * and size of the partition is checked.
+ *
+ * @param dev_desc - block device descriptor
+ * @param partitions - partition data read from '$partitions' env variable
+ * @param parts - number of partitions read from '$partitions' env variable
+ * @param gpt_head - pointer to GPT header data read from medium
+ * @param gpt_pte - pointer to GPT partition table enties read from medium
+ *
+ * @return - '0' on success, otherwise error
+ */
+int gpt_verify_partitions(block_dev_desc_t *dev_desc,
+ disk_partition_t *partitions, int parts,
+ gpt_header *gpt_head, gpt_entry **gpt_pte);
#endif
#endif /* _PART_H */
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
+int phy_ti_init(void);
int phy_vitesse_init(void);
int board_phy_config(struct phy_device *phydev);
int usb_emul_bulk(struct udevice *emul, struct usb_device *udev,
unsigned long pipe, void *buffer, int length);
+/**
+ * usb_emul_int() - Send an interrupt packet to an emulator
+ *
+ * @emul: Emulator device
+ * @udev: USB device (which the emulator is causing to appear)
+ * See struct dm_usb_ops for details on other parameters
+ * @return 0 if OK, -ve on error
+ */
+int usb_emul_int(struct udevice *emul, struct usb_device *udev,
+ unsigned long pipe, void *buffer, int length, int interval);
+
/**
* usb_emul_find() - Find an emulator for a particular device
*
*/
int usb_emul_find(struct udevice *bus, ulong pipe, struct udevice **emulp);
+/**
+ * usb_emul_find_for_dev() - Find an emulator for a particular device
+ *
+ * @bus: USB bus (controller)
+ * @dev: USB device to check
+ * @emulp: Returns pointer to emulator, or NULL if not found
+ * @return 0 if found, -ve on error
+ */
+int usb_emul_find_for_dev(struct udevice *dev, struct udevice **emulp);
+
/**
* usb_emul_reset() - Reset all emulators ready for use
*
*/
void usb_emul_reset(struct udevice *dev);
+/**
+ * usb_show_tree() - show the USB device tree
+ *
+ * This shows a list of active USB devices along with basic information about
+ * each.
+ */
+void usb_show_tree(void);
+
#endif /*_USB_H_ */
Thumb-2, about 420 bytes). Enable this option for safety when
using sprintf() with data you do not control.
+config USE_TINY_PRINTF
+ bool "Enable tiny printf() version"
+ help
+ This option enables a tiny, stripped down printf version.
+ This should only be used in space limited environments,
+ like SPL versions with hard memory limits. This version
+ reduces the code size by about 2.5KiB on armv7.
+
+ The supported format specifiers are %c, %s, %u/%d and %x.
+
config REGEX
bool "Enable regular expression support"
default y if NET
obj-y += hang.o
obj-y += linux_compat.o
obj-y += linux_string.o
+obj-y += membuff.o
obj-$(CONFIG_REGEX) += slre.o
obj-y += string.o
obj-y += time.o
obj-$(CONFIG_TRACE) += trace.o
obj-$(CONFIG_LIB_UUID) += uuid.o
-obj-y += vsprintf.o
obj-$(CONFIG_LIB_RAND) += rand.o
+ifdef CONFIG_SPL_BUILD
+# SPL U-Boot may use full-printf, tiny-printf or none at all
+ifdef CONFIG_USE_TINY_PRINTF
+obj-$(CONFIG_SPL_SERIAL_SUPPORT) += tiny-printf.o
+else
+obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o
+endif
+else
+# Main U-Boot always uses the full printf support
+obj-y += vsprintf.o
+endif
+
subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <config.h>
#include <common.h>
+#include <console.h>
#include <div64.h>
#include <inttypes.h>
#include <version.h>
COMPAT(UNKNOWN, "<none>"),
COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
- COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"),
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
COMPAT(NVIDIA_TEGRA124_DC, "nvidia,tegra124-dc"),
#include <common.h>
#include <watchdog.h>
#include <command.h>
+#include <console.h>
#include <image.h>
#include <malloc.h>
#include <u-boot/zlib.h>
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * Copyright (c) 1992 Simon Glass
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include "membuff.h"
+
+void membuff_purge(struct membuff *mb)
+{
+ /* set mb->head and mb->tail so the buffers look empty */
+ mb->head = mb->start;
+ mb->tail = mb->start;
+}
+
+static int membuff_putrawflex(struct membuff *mb, int maxlen, bool update,
+ char ***data, int *offsetp)
+{
+ int len;
+
+ /* always write to 'mb->head' */
+ assert(data && offsetp);
+ *data = &mb->start;
+ *offsetp = mb->head - mb->start;
+
+ /* if there is no buffer, we can do nothing */
+ if (!mb->start)
+ return 0;
+
+ /*
+ * if head is ahead of tail, we can write from head until the end of
+ * the buffer
+ */
+ if (mb->head >= mb->tail) {
+ /* work out how many bytes can fit here */
+ len = mb->end - mb->head - 1;
+ if (maxlen >= 0 && len > maxlen)
+ len = maxlen;
+
+ /* update the head pointer to mark these bytes as written */
+ if (update)
+ mb->head += len;
+
+ /*
+ * if the tail isn't at start of the buffer, then we can
+ * write one more byte right at the end
+ */
+ if ((maxlen < 0 || len < maxlen) && mb->tail != mb->start) {
+ len++;
+ if (update)
+ mb->head = mb->start;
+ }
+
+ /* otherwise now we can write until head almost reaches tail */
+ } else {
+ /* work out how many bytes can fit here */
+ len = mb->tail - mb->head - 1;
+ if (maxlen >= 0 && len > maxlen)
+ len = maxlen;
+
+ /* update the head pointer to mark these bytes as written */
+ if (update)
+ mb->head += len;
+ }
+
+ /* return the number of bytes which can be/must be written */
+ return len;
+}
+
+int membuff_putraw(struct membuff *mb, int maxlen, bool update, char **data)
+{
+ char **datap;
+ int offset;
+ int size;
+
+ size = membuff_putrawflex(mb, maxlen, update, &datap, &offset);
+ *data = *datap + offset;
+
+ return size;
+}
+
+bool membuff_putbyte(struct membuff *mb, int ch)
+{
+ char *data;
+
+ if (membuff_putraw(mb, 1, true, &data) != 1)
+ return false;
+ *data = ch;
+
+ return true;
+}
+
+int membuff_getraw(struct membuff *mb, int maxlen, bool update, char **data)
+{
+ int len;
+
+ /* assume for now there is no data to get */
+ len = 0;
+
+ /*
+ * in this case head is ahead of tail, so we must return data between
+ *'tail' and 'head'
+ */
+ if (mb->head > mb->tail) {
+ /* work out the amount of data */
+ *data = mb->tail;
+ len = mb->head - mb->tail;
+
+ /* check it isn't too much */
+ if (maxlen >= 0 && len > maxlen)
+ len = maxlen;
+
+ /* & mark it as read from the buffer */
+ if (update)
+ mb->tail += len;
+ }
+
+ /*
+ * if head is before tail, then we have data between 'tail' and 'end'
+ * and some more data between 'start' and 'head'(which we can't
+ * return this time
+ */
+ else if (mb->head < mb->tail) {
+ /* work out the amount of data */
+ *data = mb->tail;
+ len = mb->end - mb->tail;
+ if (maxlen >= 0 && len > maxlen)
+ len = maxlen;
+ if (update) {
+ mb->tail += len;
+ if (mb->tail == mb->end)
+ mb->tail = mb->start;
+ }
+ }
+
+ debug("getraw: maxlen=%d, update=%d, head=%d, tail=%d, data=%d, len=%d",
+ maxlen, update, (int)(mb->head - mb->start),
+ (int)(mb->tail - mb->start), (int)(*data - mb->start), len);
+
+ /* return the number of bytes we found */
+ return len;
+}
+
+int membuff_getbyte(struct membuff *mb)
+{
+ char *data = 0;
+
+ return membuff_getraw(mb, 1, true, &data) != 1 ? -1 : *(uint8_t *)data;
+}
+
+int membuff_peekbyte(struct membuff *mb)
+{
+ char *data = 0;
+
+ return membuff_getraw(mb, 1, false, &data) != 1 ? -1 : *(uint8_t *)data;
+}
+
+int membuff_get(struct membuff *mb, char *buff, int maxlen)
+{
+ char *data = 0, *buffptr = buff;
+ int len = 1, i;
+
+ /*
+ * do this in up to two lots(see GetRaw for why) stopping when there
+ * is no more data
+ */
+ for (i = 0; len && i < 2; i++) {
+ /* get a pointer to the data available */
+ len = membuff_getraw(mb, maxlen, true, &data);
+
+ /* copy it into the buffer */
+ memcpy(buffptr, data, len);
+ buffptr += len;
+ maxlen -= len;
+ }
+
+ /* return the number of bytes read */
+ return buffptr - buff;
+}
+
+int membuff_put(struct membuff *mb, const char *buff, int length)
+{
+ char *data;
+ int towrite, i, written;
+
+ for (i = written = 0; i < 2; i++) {
+ /* ask where some data can be written */
+ towrite = membuff_putraw(mb, length, true, &data);
+
+ /* and write it, updating the bytes length */
+ memcpy(data, buff, towrite);
+ written += towrite;
+ buff += towrite;
+ length -= towrite;
+ }
+
+ /* return the number of bytes written */
+ return written;
+}
+
+bool membuff_isempty(struct membuff *mb)
+{
+ return mb->head == mb->tail;
+}
+
+int membuff_avail(struct membuff *mb)
+{
+ struct membuff copy;
+ int i, avail;
+ char *data = 0;
+
+ /* make a copy of this buffer's control data */
+ copy = *mb;
+
+ /* now read everything out of the copied buffer */
+ for (i = avail = 0; i < 2; i++)
+ avail += membuff_getraw(©, -1, true, &data);
+
+ /* and return how much we read */
+ return avail;
+}
+
+int membuff_size(struct membuff *mb)
+{
+ return mb->end - mb->start;
+}
+
+bool membuff_makecontig(struct membuff *mb)
+{
+ int topsize, botsize;
+
+ debug("makecontig: head=%d, tail=%d, size=%d",
+ (int)(mb->head - mb->start), (int)(mb->tail - mb->start),
+ (int)(mb->end - mb->start));
+
+ /*
+ * first we move anything at the start of the buffer into the correct
+ * place some way along
+ */
+ if (mb->tail > mb->head) {
+ /*
+ * the data is split into two parts, from 0 to ->head and
+ * from ->tail to ->end. We move the stuff from 0 to ->head
+ * up to make space for the other data before it
+ */
+ topsize = mb->end - mb->tail;
+ botsize = mb->head - mb->start;
+
+ /*
+ * must move data at bottom up by 'topsize' bytes - check if
+ * there's room
+ */
+ if (mb->head + topsize >= mb->tail)
+ return false;
+ memmove(mb->start + topsize, mb->start, botsize);
+ debug(" - memmove(%d, %d, %d)", topsize, 0, botsize);
+
+ /* nothing at the start, so skip that step */
+ } else {
+ topsize = mb->head - mb->tail;
+ botsize = 0;
+ }
+
+ /* now move data at top down to the bottom */
+ memcpy(mb->start, mb->tail, topsize);
+ debug(" - memcpy(%d, %d, %d)", 0, (int)(mb->tail - mb->start), topsize);
+
+ /* adjust pointers */
+ mb->tail = mb->start;
+ mb->head = mb->start + topsize + botsize;
+
+ debug(" - head=%d, tail=%d", (int)(mb->head - mb->start),
+ (int)(mb->tail - mb->start));
+
+ /* all ok */
+ return true;
+}
+
+int membuff_free(struct membuff *mb)
+{
+ return mb->end == mb->start ? 0 :
+ (mb->end - mb->start) - 1 - membuff_avail(mb);
+}
+
+int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch)
+{
+ int len; /* number of bytes read (!= string length) */
+ char *s, *end;
+ bool ok = false;
+ char *orig = str;
+
+ end = mb->head >= mb->tail ? mb->head : mb->end;
+ for (len = 0, s = mb->tail; s < end && len < maxlen - 1; str++) {
+ *str = *s++;
+ len++;
+ if (*str == '\n' || *str < minch) {
+ ok = true;
+ break;
+ }
+ if (s == end && mb->tail > mb->head) {
+ s = mb->start;
+ end = mb->head;
+ }
+ }
+
+ /* couldn't get the whole string */
+ if (!ok) {
+ if (maxlen)
+ *orig = '\0';
+ return 0;
+ }
+
+ /* terminate the string, update the membuff and return success */
+ *str = '\0';
+ mb->tail = s == mb->end ? mb->start : s;
+
+ return len;
+}
+
+int membuff_extend_by(struct membuff *mb, int by, int max)
+{
+ int oldhead, oldtail;
+ int size, orig;
+ char *ptr;
+
+ /* double the buffer size until it is big enough */
+ assert(by >= 0);
+ for (orig = mb->end - mb->start, size = orig; size < orig + by;)
+ size *= 2;
+ if (max != -1)
+ size = min(size, max);
+ by = size - orig;
+
+ /* if we're already at maximum, give up */
+ if (by <= 0)
+ return -E2BIG;
+
+ oldhead = mb->head - mb->start;
+ oldtail = mb->tail - mb->start;
+ ptr = realloc(mb->start, size);
+ if (!ptr)
+ return -ENOMEM;
+ mb->start = ptr;
+ mb->head = mb->start + oldhead;
+ mb->tail = mb->start + oldtail;
+
+ if (mb->head < mb->tail) {
+ memmove(mb->tail + by, mb->tail, orig - oldtail);
+ mb->tail += by;
+ }
+ mb->end = mb->start + size;
+
+ return 0;
+}
+
+void membuff_init(struct membuff *mb, char *buff, int size)
+{
+ mb->start = buff;
+ mb->end = mb->start + size;
+ membuff_purge(mb);
+}
+
+int membuff_new(struct membuff *mb, int size)
+{
+ mb->start = malloc(size);
+ if (!mb->start)
+ return -ENOMEM;
+
+ membuff_init(mb, mb->start, size);
+ return 0;
+}
+
+void membuff_uninit(struct membuff *mb)
+{
+ mb->end = NULL;
+ mb->start = NULL;
+ membuff_purge(mb);
+}
+
+void membuff_dispose(struct membuff *mb)
+{
+ free(&mb->start);
+ membuff_uninit(mb);
+}
--- /dev/null
+/*
+ * Tiny printf version for SPL
+ *
+ * Copied from:
+ * http://www.sparetimelabs.com/printfrevisited/printfrevisited.php
+ *
+ * Copyright (C) 2004,2008 Kustaa Nyholm
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#include <common.h>
+#include <stdarg.h>
+#include <serial.h>
+
+static char *bf;
+static char zs;
+
+static void out(char c)
+{
+ *bf++ = c;
+}
+
+static void out_dgt(char dgt)
+{
+ out(dgt + (dgt < 10 ? '0' : 'a' - 10));
+ zs = 1;
+}
+
+static void div_out(unsigned int *num, unsigned int div)
+{
+ unsigned char dgt = 0;
+
+ while (*num >= div) {
+ *num -= div;
+ dgt++;
+ }
+
+ if (zs || dgt > 0)
+ out_dgt(dgt);
+}
+
+int printf(const char *fmt, ...)
+{
+ va_list va;
+ char ch;
+ char *p;
+ unsigned int num;
+ char buf[12];
+ unsigned int div;
+
+ va_start(va, fmt);
+
+ while ((ch = *(fmt++))) {
+ if (ch != '%') {
+ putc(ch);
+ } else {
+ char lz = 0;
+ char w = 0;
+
+ ch = *(fmt++);
+ if (ch == '0') {
+ ch = *(fmt++);
+ lz = 1;
+ }
+
+ if (ch >= '0' && ch <= '9') {
+ w = 0;
+ while (ch >= '0' && ch <= '9') {
+ w = (w * 10) + ch - '0';
+ ch = *fmt++;
+ }
+ }
+ bf = buf;
+ p = bf;
+ zs = 0;
+
+ switch (ch) {
+ case 0:
+ goto abort;
+ case 'u':
+ case 'd':
+ num = va_arg(va, unsigned int);
+ if (ch == 'd' && (int)num < 0) {
+ num = -(int)num;
+ out('-');
+ }
+ for (div = 1000000000; div; div /= 10)
+ div_out(&num, div);
+ break;
+ case 'x':
+ num = va_arg(va, unsigned int);
+ for (div = 0x10000000; div; div /= 0x10)
+ div_out(&num, div);
+ break;
+ case 'c':
+ out((char)(va_arg(va, int)));
+ break;
+ case 's':
+ p = va_arg(va, char*);
+ break;
+ case '%':
+ out('%');
+ default:
+ break;
+ }
+
+ *bf = 0;
+ bf = p;
+ while (*bf++ && w > 0)
+ w--;
+ while (w-- > 0)
+ putc(lz ? '0' : ' ');
+ while ((ch = *p++))
+ putc(ch);
+ }
+ }
+
+abort:
+ va_end(va);
+ return 0;
+}
return i;
}
+int printf(const char *fmt, ...)
+{
+ va_list args;
+ uint i;
+ char printbuffer[CONFIG_SYS_PBSIZE];
+
+ va_start(args, fmt);
+
+ /*
+ * For this to work, printbuffer must be larger than
+ * anything we ever want to print.
+ */
+ i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
+ va_end(args);
+
+ /* Print the string */
+ puts(printbuffer);
+ return i;
+}
+
+int vprintf(const char *fmt, va_list args)
+{
+ uint i;
+ char printbuffer[CONFIG_SYS_PBSIZE];
+
+ /*
+ * For this to work, printbuffer must be larger than
+ * anything we ever want to print.
+ */
+ i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
+
+ /* Print the string */
+ puts(printbuffer);
+ return i;
+}
+
static void panic_finish(void) __attribute__ ((noreturn));
static void panic_finish(void)
#include <common.h>
#include <command.h>
+#include <console.h>
#include <environment.h>
#include <errno.h>
#include <net.h>
MLO MLO.byteswap: $(obj)/u-boot-spl.bin
$(call if_changed,mkimage)
+ifeq ($(CONFIG_SYS_SOC),"at91")
MKIMAGEFLAGS_boot.bin = -T atmelimage
ifeq ($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y)
boot.bin: $(obj)/u-boot-spl.bin
$(call if_changed,mkimage)
+else
+MKIMAGEFLAGS_boot.bin = -T zynqimage
+
+spl/boot.bin: $(obj)/u-boot-spl-dtb.bin
+ $(call if_changed,mkimage)
+endif
ALL-y += $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN).cfg
ALL-y += boot.bin
endif
+ifdef CONFIG_ARCH_ZYNQ
+ALL-y += $(obj)/boot.bin
+endif
+
all: $(ALL-y)
quiet_cmd_cat = CAT $@
obj-$(CONFIG_DM_USB) += usb.o
obj-$(CONFIG_DM_PMIC) += pmic.o
obj-$(CONFIG_DM_REGULATOR) += regulator.o
+obj-$(CONFIG_TIMER) += timer.o
obj-$(CONFIG_ADC) += adc.o
endif
#include <common.h>
#include <command.h>
+#include <console.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
+#include <asm/state.h>
#include <dm/test.h>
#include <dm/root.h>
#include <dm/uclass-internal.h>
struct unit_test *tests = ll_entry_start(struct unit_test, dm_test);
const int n_ents = ll_entry_count(struct unit_test, dm_test);
struct unit_test_state *uts = &global_dm_test_state;
+ struct sandbox_state *state = state_get_current();
uts->priv = &_global_priv_dm_test_state;
struct unit_test *test;
int run_count;
if (test->flags & DM_TESTF_SCAN_FDT)
ut_assertok(dm_scan_fdt(gd->fdt_blob, false));
+ /*
+ * Silence the console and rely on console reocrding to get
+ * our output.
+ */
+ console_record_reset();
+ if (!state->show_test_output)
+ gd->flags |= GD_FLG_SILENT;
test->func(uts);
+ gd->flags &= ~GD_FLG_SILENT;
+ state_set_skip_delays(false);
ut_assertok(dm_test_destroy(uts));
}
--- /dev/null
+/*
+ * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <timer.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Basic test of the timer uclass.
+ */
+static int dm_test_timer_base(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_get_device(UCLASS_TIMER, 0, &dev));
+ ut_asserteq(1000000, timer_get_rate(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_timer_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
*/
#include <common.h>
+#include <console.h>
#include <dm.h>
#include <usb.h>
#include <asm/io.h>
+#include <asm/state.h>
+#include <asm/test.h>
+#include <dm/device-internal.h>
#include <dm/test.h>
+#include <dm/uclass-internal.h>
#include <test/ut.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/* Test that sandbox USB works correctly */
static int dm_test_usb_base(struct unit_test_state *uts)
{
block_dev_desc_t *dev_desc;
char cmp[1024];
+ state_set_skip_delays(true);
ut_assertok(usb_init());
ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 0, &dev));
ut_assertok(get_device("usb", "0", &dev_desc));
return 0;
}
DM_TEST(dm_test_usb_flash, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* test that we can handle multiple storage devices */
+static int dm_test_usb_multi(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ state_set_skip_delays(true);
+ ut_assertok(usb_init());
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 0, &dev));
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 1, &dev));
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 2, &dev));
+
+ return 0;
+}
+DM_TEST(dm_test_usb_multi, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int count_usb_devices(void)
+{
+ struct udevice *hub;
+ struct uclass *uc;
+ int count = 0;
+ int ret;
+
+ ret = uclass_get(UCLASS_USB_HUB, &uc);
+ if (ret)
+ return ret;
+
+ uclass_foreach_dev(hub, uc) {
+ struct udevice *dev;
+
+ count++;
+ for (device_find_first_child(hub, &dev);
+ dev;
+ device_find_next_child(&dev)) {
+ count++;
+ }
+ }
+
+ return count;
+}
+
+/* test that we can remove an emulated device and it is then not found */
+static int dm_test_usb_remove(struct unit_test_state *uts)
+{
+ struct udevice *dev, *emul;
+
+ /* Scan and check that all devices are present */
+ state_set_skip_delays(true);
+ ut_assertok(usb_init());
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 0, &dev));
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 1, &dev));
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 2, &dev));
+ ut_asserteq(5, count_usb_devices());
+ ut_assertok(usb_stop());
+ ut_asserteq(5, count_usb_devices());
+
+ /* Remove the second emulation device */
+ ut_assertok(uclass_find_device_by_name(UCLASS_USB_EMUL, "flash-stick@1",
+ &dev));
+ ut_assertok(device_unbind(dev));
+
+ /* Rescan - only the first and third should be present */
+ ut_assertok(usb_init());
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 0, &dev));
+ ut_assertok(usb_emul_find_for_dev(dev, &emul));
+ ut_asserteq_str("flash-stick@0", emul->name);
+ ut_assertok(uclass_get_device(UCLASS_MASS_STORAGE, 1, &dev));
+ ut_assertok(usb_emul_find_for_dev(dev, &emul));
+ ut_asserteq_str("flash-stick@2", emul->name);
+
+ ut_asserteq(-ENODEV, uclass_get_device(UCLASS_MASS_STORAGE, 2, &dev));
+
+ ut_asserteq(4, count_usb_devices());
+ ut_assertok(usb_stop());
+ ut_asserteq(4, count_usb_devices());
+
+ return 0;
+}
+DM_TEST(dm_test_usb_remove, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+const char usb_tree_base[] =
+" 1 Hub (12 Mb/s, 100mA)\n"
+" | sandbox hub 2345\n"
+" |\n"
+" |\b+-2 Mass Storage (12 Mb/s, 100mA)\n"
+" | sandbox flash flash-stick@0\n"
+" | \n"
+" |\b+-3 Mass Storage (12 Mb/s, 100mA)\n"
+" | sandbox flash flash-stick@1\n"
+" | \n"
+" |\b+-4 Mass Storage (12 Mb/s, 100mA)\n"
+" sandbox flash flash-stick@2\n"
+" \n";
+
+/* test that the 'usb tree' command output looks correct */
+static int dm_test_usb_tree(struct unit_test_state *uts)
+{
+ char *data;
+ int len;
+
+ state_set_skip_delays(true);
+ ut_assertok(usb_init());
+ console_record_reset_enable();
+ usb_show_tree();
+ len = membuff_getraw(&gd->console_out, -1, true, &data);
+ if (len)
+ data[len] = '\0';
+ ut_asserteq_str(usb_tree_base, data);
+ ut_assertok(usb_stop());
+
+ return 0;
+}
+DM_TEST(dm_test_usb_tree, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+const char usb_tree_remove[] =
+" 1 Hub (12 Mb/s, 100mA)\n"
+" | sandbox hub 2345\n"
+" |\n"
+" |\b+-2 Mass Storage (12 Mb/s, 100mA)\n"
+" | sandbox flash flash-stick@0\n"
+" | \n"
+" |\b+-3 Mass Storage (12 Mb/s, 100mA)\n"
+" sandbox flash flash-stick@2\n"
+" \n";
+
+/*
+ * test that the 'usb tree' command output looks correct when we remove a
+ * device
+ */
+static int dm_test_usb_tree_remove(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ char *data;
+ int len;
+
+ /* Remove the second emulation device */
+ ut_assertok(uclass_find_device_by_name(UCLASS_USB_EMUL, "flash-stick@1",
+ &dev));
+ ut_assertok(device_unbind(dev));
+
+ state_set_skip_delays(true);
+ ut_assertok(usb_init());
+ console_record_reset_enable();
+ usb_show_tree();
+ len = membuff_getraw(&gd->console_out, -1, true, &data);
+ if (len)
+ data[len] = '\0';
+ ut_asserteq_str(usb_tree_remove, data);
+ ut_assertok(usb_stop());
+
+ return 0;
+}
+DM_TEST(dm_test_usb_tree_remove, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+const char usb_tree_reorder[] =
+" 1 Hub (12 Mb/s, 100mA)\n"
+" | sandbox hub 2345\n"
+" |\n"
+" |\b+-2 Mass Storage (12 Mb/s, 100mA)\n"
+" | sandbox flash flash-stick@0\n"
+" | \n"
+" |\b+-3 Mass Storage (12 Mb/s, 100mA)\n"
+" | sandbox flash flash-stick@2\n"
+" | \n"
+" |\b+-4 Mass Storage (12 Mb/s, 100mA)\n"
+" sandbox flash flash-stick@1\n"
+" \n";
+
+/*
+ * test that the 'usb tree' command output looks correct when we reorder two
+ * devices.
+ */
+static int dm_test_usb_tree_reorder(struct unit_test_state *uts)
+{
+ struct udevice *dev, *parent;
+ char *data;
+ int len;
+
+ /* Remove the second emulation device */
+ ut_assertok(uclass_find_device_by_name(UCLASS_USB_EMUL, "flash-stick@1",
+ &dev));
+ parent = dev->parent;
+
+ /* Reorder the devices in the parent list and uclass list */
+ list_del(&dev->sibling_node);
+ list_add_tail(&dev->sibling_node, &parent->child_head);
+
+ list_del(&dev->uclass_node);
+ list_add_tail(&dev->uclass_node, &dev->uclass->dev_head);
+
+ state_set_skip_delays(true);
+ ut_assertok(usb_init());
+ console_record_reset_enable();
+ usb_show_tree();
+ len = membuff_getraw(&gd->console_out, -1, true, &data);
+ if (len)
+ data[len] = '\0';
+ ut_asserteq_str(usb_tree_reorder, data);
+ ut_assertok(usb_stop());
+
+ return 0;
+}
+DM_TEST(dm_test_usb_tree_reorder, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+static int dm_test_usb_keyb(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ state_set_skip_delays(true);
+ ut_assertok(usb_init());
+
+ /* Initially there should be no characters */
+ ut_asserteq(0, tstc());
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_USB_EMUL, "keyb",
+ &dev));
+
+ /*
+ * Add a string to the USB keyboard buffer - it should appear in
+ * stdin
+ */
+ ut_assertok(sandbox_usb_keyb_add_string(dev, "ab"));
+ ut_asserteq(1, tstc());
+ ut_asserteq('a', getc());
+ ut_asserteq(1, tstc());
+ ut_asserteq('b', getc());
+ ut_asserteq(0, tstc());
+
+ ut_assertok(usb_stop());
+
+ return 0;
+}
+DM_TEST(dm_test_usb_keyb, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
#include <test/test.h>
#include <test/ut.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void ut_fail(struct unit_test_state *uts, const char *fname, int line,
const char *func, const char *cond)
{
+ gd->flags &= ~(GD_FLG_SILENT | GD_FLG_RECORD);
printf("%s:%d, %s(): %s\n", fname, line, func, cond);
uts->fail_count++;
}
{
va_list args;
+ gd->flags &= ~(GD_FLG_SILENT | GD_FLG_RECORD);
printf("%s:%d, %s(): %s: ", fname, line, func, cond);
va_start(args, fmt);
vprintf(fmt, args);
lib/sha256.o \
common/hash.o \
ublimage.o \
+ zynqimage.o \
$(LIBFDT_OBJS) \
$(RSA_OBJS-y)
main_hdr = image;
/* Fill in the main header */
- main_hdr->blocksize = payloadsz + sizeof(uint32_t) - headersz;
- main_hdr->srcaddr = headersz;
+ main_hdr->blocksize =
+ cpu_to_le32(payloadsz + sizeof(uint32_t) - headersz);
+ main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = has_ext;
- main_hdr->destaddr = params->addr;
- main_hdr->execaddr = params->ep;
+ main_hdr->destaddr = cpu_to_le32(params->addr);
+ main_hdr->execaddr = cpu_to_le32(params->ep);
e = image_find_option(IMAGE_CFG_BOOT_FROM);
if (e)
main_hdr->nandeccmode = e->nandeccmode;
e = image_find_option(IMAGE_CFG_NAND_PAGESZ);
if (e)
- main_hdr->nandpagesize = e->nandpagesz;
+ main_hdr->nandpagesize = cpu_to_le16(e->nandpagesz);
main_hdr->checksum = image_checksum8(image,
sizeof(struct main_hdr_v0));
int cfgi, datai;
ext_hdr = image + sizeof(struct main_hdr_v0);
- ext_hdr->offset = 0x40;
+ ext_hdr->offset = cpu_to_le32(0x40);
for (cfgi = 0, datai = 0; cfgi < cfgn; cfgi++) {
e = &image_cfg[cfgi];
if (e->type != IMAGE_CFG_DATA)
continue;
- ext_hdr->rcfg[datai].raddr = e->regdata.raddr;
- ext_hdr->rcfg[datai].rdata = e->regdata.rdata;
+ ext_hdr->rcfg[datai].raddr =
+ cpu_to_le32(e->regdata.raddr);
+ ext_hdr->rcfg[datai].rdata =
+ cpu_to_le32(e->regdata.rdata);
datai++;
}
return 0;
}
- headersz += s.st_size +
- binarye->binary.nargs * sizeof(unsigned int);
+ headersz += sizeof(struct opt_hdr_v1) +
+ s.st_size +
+ (binarye->binary.nargs + 2) * sizeof(uint32_t);
if (hasext)
*hasext = 1;
}
cur += sizeof(struct main_hdr_v1);
/* Fill the main header */
- main_hdr->blocksize = payloadsz - headersz + sizeof(uint32_t);
- main_hdr->headersz_lsb = headersz & 0xFFFF;
+ main_hdr->blocksize =
+ cpu_to_le32(payloadsz - headersz + sizeof(uint32_t));
+ main_hdr->headersz_lsb = cpu_to_le16(headersz & 0xFFFF);
main_hdr->headersz_msb = (headersz & 0xFFFF0000) >> 16;
- main_hdr->destaddr = params->addr;
- main_hdr->execaddr = params->ep;
- main_hdr->srcaddr = headersz;
+ main_hdr->destaddr = cpu_to_le32(params->addr);
+ main_hdr->execaddr = cpu_to_le32(params->ep);
+ main_hdr->srcaddr = cpu_to_le32(headersz);
main_hdr->ext = hasext;
main_hdr->version = 1;
e = image_find_option(IMAGE_CFG_BOOT_FROM);
binarye = image_find_option(IMAGE_CFG_BINARY);
if (binarye) {
struct opt_hdr_v1 *hdr = cur;
- unsigned int *args;
+ uint32_t *args;
size_t binhdrsz;
struct stat s;
int argi;
fstat(fileno(bin), &s);
binhdrsz = sizeof(struct opt_hdr_v1) +
- (binarye->binary.nargs + 1) * sizeof(unsigned int) +
+ (binarye->binary.nargs + 2) * sizeof(uint32_t) +
s.st_size;
/*
* next-header byte and 3-byte alignment at the end.
*/
binhdrsz = ALIGN_SUP(binhdrsz, 4) + 4;
- hdr->headersz_lsb = binhdrsz & 0xFFFF;
+ hdr->headersz_lsb = cpu_to_le16(binhdrsz & 0xFFFF);
hdr->headersz_msb = (binhdrsz & 0xFFFF0000) >> 16;
cur += sizeof(struct opt_hdr_v1);
args = cur;
- *args = binarye->binary.nargs;
+ *args = cpu_to_le32(binarye->binary.nargs);
args++;
for (argi = 0; argi < binarye->binary.nargs; argi++)
- args[argi] = binarye->binary.args[argi];
+ args[argi] = cpu_to_le32(binarye->binary.args[argi]);
- cur += (binarye->binary.nargs + 1) * sizeof(unsigned int);
+ cur += (binarye->binary.nargs + 1) * sizeof(uint32_t);
ret = fread(cur, s.st_size, 1, bin);
if (ret != 1) {
free(image_cfg);
/* Build and add image checksum header */
- checksum = image_checksum32((uint32_t *)ptr, sbuf->st_size);
+ checksum =
+ cpu_to_le32(image_checksum32((uint32_t *)ptr, sbuf->st_size));
size = write(ifd, &checksum, sizeof(uint32_t));
if (size != sizeof(uint32_t)) {
fprintf(stderr, "Error:%s - Checksum write %d bytes %s\n",
tparams->header_size = alloc_len;
tparams->hdr = hdr;
- return 0;
+ /*
+ * The resulting image needs to be 4-byte aligned. At least
+ * the Marvell hdrparser tool complains if its unaligned.
+ * By returning 1 here in this function, called via
+ * tparams->vrec_header() in mkimage.c, mkimage will
+ * automatically pad the the resulting image to a 4-byte
+ * size if necessary.
+ */
+ return 1;
}
/*
#ifndef _KWBIMAGE_H_
#define _KWBIMAGE_H_
+#include <compiler.h>
#include <stdint.h>
#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
#define OPT_HDR_V1_REGISTER_TYPE 0x3
#define KWBHEADER_V1_SIZE(hdr) \
- (((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb)
+ (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
enum kwbimage_cmd {
CMD_INVALID,
--- /dev/null
+/*
+ * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * The following Boot Header format/structures and values are defined in the
+ * following documents:
+ * * Xilinx Zynq-7000 Technical Reference Manual (Section 6.3)
+ * * Xilinx Zynq-7000 Software Developers Guide (Appendix A.7 and A.8)
+ *
+ * Expected Header Size = 0x8C0
+ * Forced as 'little' endian, 32-bit words
+ *
+ * 0x 0 - Interrupt Table (8 words)
+ * ... (Default value = 0xeafffffe)
+ * 0x 1f
+ * 0x 20 - Width Detection
+ * * DEFAULT_WIDTHDETECTION 0xaa995566
+ * 0x 24 - Image Identifier
+ * * DEFAULT_IMAGEIDENTIFIER 0x584c4e58
+ * 0x 28 - Encryption
+ * * 0x00000000 - None
+ * * 0xa5c3c5a3 - eFuse
+ * * 0x3a5c3c5a - bbRam
+ * 0x 2C - User Field
+ * 0x 30 - Image Offset
+ * 0x 34 - Image Size
+ * 0x 38 - Reserved (0x00000000) (according to spec)
+ * * FSBL defines this field for Image Destination Address.
+ * 0x 3C - Image Load
+ * 0x 40 - Image Stored Size
+ * 0x 44 - Reserved (0x00000000) (according to spec)
+ * * FSBL defines this field for QSPI configuration Data.
+ * 0x 48 - Checksum
+ * 0x 4c - Unused (21 words)
+ * ...
+ * 0x 9c
+ * 0x a0 - Register Initialization, 256 Address and Data word pairs
+ * * List is terminated with an address of 0xffffffff or
+ * ... * at the max number of entries
+ * 0x89c
+ * 0x8a0 - Unused (8 words)
+ * ...
+ * 0x8bf
+ * 0x8c0 - Data/Image starts here or above
+ */
+
+#include "imagetool.h"
+#include "mkimage.h"
+#include <image.h>
+
+#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe))
+#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff))
+#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566))
+#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58))
+
+enum {
+ ENCRYPTION_EFUSE = 0xa5c3c5a3,
+ ENCRYPTION_BBRAM = 0x3a5c3c5a,
+ ENCRYPTION_NONE = 0x0,
+};
+
+struct zynq_reginit {
+ uint32_t address;
+ uint32_t data;
+};
+
+#define HEADER_INTERRUPT_VECTORS 8
+#define HEADER_REGINITS 256
+
+struct zynq_header {
+ uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */
+ uint32_t width_detection; /* 0x20 */
+ uint32_t image_identifier; /* 0x24 */
+ uint32_t encryption; /* 0x28 */
+ uint32_t user_field; /* 0x2c */
+ uint32_t image_offset; /* 0x30 */
+ uint32_t image_size; /* 0x34 */
+ uint32_t __reserved1; /* 0x38 */
+ uint32_t image_load; /* 0x3c */
+ uint32_t image_stored_size; /* 0x40 */
+ uint32_t __reserved2; /* 0x44 */
+ uint32_t checksum; /* 0x48 */
+ uint32_t __reserved3[21]; /* 0x4c */
+ struct zynq_reginit register_init[HEADER_REGINITS]; /* 0xa0 */
+ uint32_t __reserved4[8]; /* 0x8a0 */
+};
+
+static struct zynq_header zynqimage_header;
+
+static uint32_t zynqimage_checksum(struct zynq_header *ptr)
+{
+ uint32_t checksum = 0;
+
+ if (ptr == NULL)
+ return 0;
+
+ checksum += le32_to_cpu(ptr->width_detection);
+ checksum += le32_to_cpu(ptr->image_identifier);
+ checksum += le32_to_cpu(ptr->encryption);
+ checksum += le32_to_cpu(ptr->user_field);
+ checksum += le32_to_cpu(ptr->image_offset);
+ checksum += le32_to_cpu(ptr->image_size);
+ checksum += le32_to_cpu(ptr->__reserved1);
+ checksum += le32_to_cpu(ptr->image_load);
+ checksum += le32_to_cpu(ptr->image_stored_size);
+ checksum += le32_to_cpu(ptr->__reserved2);
+ checksum = ~checksum;
+
+ return cpu_to_le32(checksum);
+}
+
+static void zynqimage_default_header(struct zynq_header *ptr)
+{
+ int i;
+
+ if (ptr == NULL)
+ return;
+
+ ptr->width_detection = HEADER_WIDTHDETECTION;
+ ptr->image_identifier = HEADER_IMAGEIDENTIFIER;
+ ptr->encryption = cpu_to_le32(ENCRYPTION_NONE);
+
+ /* Setup not-supported/constant/reserved fields */
+ for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++)
+ ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT;
+
+ for (i = 0; i < HEADER_REGINITS; i++) {
+ ptr->register_init[i].address = HEADER_REGINIT_NULL;
+ ptr->register_init[i].data = HEADER_REGINIT_NULL;
+ }
+
+ /*
+ * Certain reserved fields are required to be set to 0, ensure they are
+ * set as such.
+ */
+ ptr->__reserved1 = 0x0;
+ ptr->__reserved2 = 0x0;
+}
+
+/* mkimage glue functions */
+static int zynqimage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct zynq_header *zynqhdr = (struct zynq_header *)ptr;
+
+ if (image_size < sizeof(struct zynq_header))
+ return -1;
+
+ if (zynqhdr->width_detection != HEADER_WIDTHDETECTION)
+ return -1;
+ if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER)
+ return -1;
+
+ if (zynqimage_checksum(zynqhdr) != zynqhdr->checksum)
+ return -1;
+
+ return 0;
+}
+
+static void zynqimage_print_header(const void *ptr)
+{
+ struct zynq_header *zynqhdr = (struct zynq_header *)ptr;
+ int i;
+
+ printf("Image Type : Xilinx Zynq Boot Image support\n");
+ printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset));
+ printf("Image Size : %lu bytes (%lu bytes packed)\n",
+ (unsigned long)le32_to_cpu(zynqhdr->image_size),
+ (unsigned long)le32_to_cpu(zynqhdr->image_stored_size));
+ printf("Image Load : 0x%08x\n", le32_to_cpu(zynqhdr->image_load));
+ printf("User Field : 0x%08x\n", le32_to_cpu(zynqhdr->user_field));
+ printf("Checksum : 0x%08x\n", le32_to_cpu(zynqhdr->checksum));
+
+ for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) {
+ if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT)
+ continue;
+
+ printf("Modified Interrupt Vector Address [%d]: 0x%08x\n", i,
+ le32_to_cpu(zynqhdr->interrupt_vectors[i]));
+ }
+
+ for (i = 0; i < HEADER_REGINITS; i++) {
+ if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL)
+ break;
+
+ if (i == 0)
+ printf("Custom Register Initialization:\n");
+
+ printf(" @ 0x%08x -> 0x%08x\n",
+ le32_to_cpu(zynqhdr->register_init[i].address),
+ le32_to_cpu(zynqhdr->register_init[i].data));
+ }
+}
+
+static int zynqimage_check_params(struct image_tool_params *params)
+{
+ if (!params)
+ return 0;
+
+ if (params->addr != 0x0) {
+ fprintf(stderr, "Error: Load Address cannot be specified.\n");
+ return -1;
+ }
+
+ /*
+ * If the entry point is specified ensure it is 64 byte aligned.
+ */
+ if (params->eflag && (params->ep % 64 != 0)) {
+ fprintf(stderr,
+ "Error: Entry Point must be aligned to a 64-byte boundary.\n");
+ return -1;
+ }
+
+ return !((params->lflag || params->dflag) ||
+ (params->dflag && params->eflag));
+}
+
+static int zynqimage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_ZYNQIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static void zynqimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ struct zynq_header *zynqhdr = (struct zynq_header *)ptr;
+ zynqimage_default_header(zynqhdr);
+
+ /* place image directly after header */
+ zynqhdr->image_offset =
+ cpu_to_le32((uint32_t)sizeof(struct zynq_header));
+ zynqhdr->image_size = cpu_to_le32((uint32_t)sbuf->st_size);
+ zynqhdr->image_stored_size = zynqhdr->image_size;
+ zynqhdr->image_load = 0x0;
+ if (params->eflag)
+ zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
+
+ zynqhdr->checksum = zynqimage_checksum(zynqhdr);
+}
+
+U_BOOT_IMAGE_TYPE(
+ zynqimage,
+ "Xilinx Zynq Boot Image support",
+ sizeof(struct zynq_header),
+ (void *)&zynqimage_header,
+ zynqimage_check_params,
+ zynqimage_verify_header,
+ zynqimage_print_header,
+ zynqimage_set_header,
+ NULL,
+ zynqimage_check_image_types,
+ NULL,
+ NULL
+);
projects / oweals / u-boot.git / commitdiff