config FIT
bool "Support Flattened Image Tree"
select MD5
+ select SHA1
help
This option allows you to boot the new uImage structure,
Flattened Image Tree. FIT is formally a FDT, which can include
if FIT
+config FIT_ENABLE_SHA256_SUPPORT
+ bool "Support SHA256 checksum of FIT image contents"
+ select SHA256
+ default y
+ help
+ Enable this to support SHA256 checksum of FIT image contents. A
+ SHA256 checksum is a 256-bit (32-byte) hash value used to check that
+ the image contents have not been corrupted. SHA256 is recommended
+ for use in secure applications since (as at 2016) there is no known
+ feasible attack that could produce a 'collision' with differing
+ input data. Use this for the highest security. Note that only the
+ SHA256 variant is supported: SHA512 and others are not currently
+ supported in U-Boot.
+
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
depends on DM
injected into the FIT creation (i.e. the blobs would have been pre-
processed before being added to the FIT image).
+if SPL
+
config SPL_FIT
bool "Support Flattened Image Tree within SPL"
depends on SPL
+ select SPL_OF_LIBFDT
config SPL_FIT_SIGNATURE
bool "Enable signature verification of FIT firmware within SPL"
- depends on SPL_FIT
depends on SPL_DM
+ select SPL_FIT
select SPL_RSA
config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT"
+ select SPL_FIT
help
Normally with the SPL framework a legacy image is generated as part
of the build. This contains U-Boot along with information as to
injected into the FIT creation (i.e. the blobs would have been pre-
processed before being added to the FIT image).
+config SPL_FIT_SOURCE
+ string ".its source file for U-Boot FIT image"
+ depends on SPL_FIT
+ help
+ Specifies a (platform specific) FIT source file to generate the
+ U-Boot FIT image. This could specify further image to load and/or
+ execute.
+
+config SPL_FIT_GENERATOR
+ string ".its file generator script for U-Boot FIT image"
+ depends on SPL_FIT
+ default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
+ help
+ Specifies a (platform specific) script file to generate the FIT
+ source file used to build the U-Boot FIT image file. This gets
+ passed a list of supported device tree file stub names to
+ include in the generated image.
+
+endif # SPL
+
endif # FIT
config OF_BOARD_SETUP
cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
$(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
+quiet_cmd_mkfitimage = MKIMAGE $@
+cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \
+ $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT))
+
quiet_cmd_cat = CAT $@
cmd_cat = cat $(filter-out $(PHONY), $^) > $@
cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
-DDO_DEPS_ONLY -D__ASSEMBLY__ -x assembler-with-cpp -P -dM -E -o $@ $<
+# Boards with more complex image requirments can provide an .its source file
+# or a generator script
+ifneq ($(CONFIG_SPL_FIT_SOURCE),"")
+U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
+else
+ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
+U_BOOT_ITS := u-boot.its
+$(U_BOOT_ITS): FORCE
+ $(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
+ $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
+endif
+endif
+
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE
$(call if_changed,mkimage)
+u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
+ $(call if_changed,mkfitimage)
+
u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
CONFIG_SPL_STACK_R_ADDR points into SDRAM
- preloader_console_init() can be called here - typically this is
- done by defining CONFIG_SPL_BOARD_INIT and then supplying a
+ done by selecting CONFIG_SPL_BOARD_INIT and then supplying a
spl_board_init() function containing this call
- loads U-Boot or (in falcon mode) Linux
CONFIG_CMD_CRC32 * crc32
CONFIG_CMD_DHCP * DHCP support
CONFIG_CMD_DIAG * Diagnostics
- CONFIG_CMD_DS4510 * ds4510 I2C gpio commands
- CONFIG_CMD_DS4510_INFO * ds4510 I2C info command
- CONFIG_CMD_DS4510_MEM * ds4510 I2C eeprom/sram commansd
- CONFIG_CMD_DS4510_RST * ds4510 I2C rst command
- CONFIG_CMD_DTT * Digital Therm and Thermostat
CONFIG_CMD_ECHO echo arguments
CONFIG_CMD_EDITENV edit env variable
- CONFIG_CMD_EEPROM * EEPROM read/write support
- CONFIG_CMD_EEPROM_LAYOUT* EEPROM layout aware commands
CONFIG_CMD_ELF * bootelf, bootvx
- CONFIG_CMD_ENV_CALLBACK * display details about env callbacks
- CONFIG_CMD_ENV_FLAGS * display details about env flags
CONFIG_CMD_ENV_EXISTS * check existence of env variable
CONFIG_CMD_EXPORTENV * export the environment
CONFIG_CMD_EXT2 * ext2 command support
that work for multiple fs types
CONFIG_CMD_FS_UUID * Look up a filesystem UUID
CONFIG_CMD_SAVEENV saveenv
- CONFIG_CMD_FDC * Floppy Disk Support
CONFIG_CMD_FAT * FAT command support
CONFIG_CMD_FLASH flinfo, erase, protect
CONFIG_CMD_FPGA FPGA device initialization support
- CONFIG_CMD_FUSE * Device fuse support
- CONFIG_CMD_GETTIME * Get time since boot
CONFIG_CMD_GO * the 'go' command (exec code)
CONFIG_CMD_GREPENV * search environment
- CONFIG_CMD_HASH * calculate hash / digest
CONFIG_CMD_I2C * I2C serial bus support
- CONFIG_CMD_IDE * IDE harddisk support
CONFIG_CMD_IMI iminfo
CONFIG_CMD_IMLS List all images found in NOR flash
CONFIG_CMD_IMLS_NAND * List all images found in NAND flash
- CONFIG_CMD_IMMAP * IMMR dump support
- CONFIG_CMD_IOTRACE * I/O tracing for debugging
CONFIG_CMD_IMPORTENV * import an environment
CONFIG_CMD_INI * import data from an ini file into the env
- CONFIG_CMD_IRQ * irqinfo
CONFIG_CMD_ITEST Integer/string test of 2 values
- CONFIG_CMD_JFFS2 * JFFS2 Support
- CONFIG_CMD_KGDB * kgdb
CONFIG_CMD_LDRINFO * ldrinfo (display Blackfin loader)
CONFIG_CMD_LINK_LOCAL * link-local IP address auto-configuration
(169.254.*.*)
disk/part_efi.c
CONFIG_MTD_PARTITIONS Memory Technology Device partition table.
- If IDE or SCSI support is enabled (CONFIG_CMD_IDE or
+ If IDE or SCSI support is enabled (CONFIG_IDE or
CONFIG_SCSI) you must configure support for at
least one non-MTD partition type as well.
the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should
be at least 4MB.
- CONFIG_LZMA
-
- If this option is set, support for lzma compressed
- images is included.
-
- Note: The LZMA algorithm adds between 2 and 4KB of code and it
- requires an amount of dynamic memory that is given by the
- formula:
-
- (1846 + 768 << (lc + lp)) * sizeof(uint16)
-
- Where lc and lp stand for, respectively, Literal context bits
- and Literal pos bits.
-
- This value is upper-bounded by 14MB in the worst case. Anyway,
- for a ~4MB large kernel image, we have lc=3 and lp=0 for a
- total amount of (1846 + 768 << (3 + 0)) * 2 = ~41KB... that is
- a very small buffer.
-
- Use the lzmainfo tool to determinate the lc and lp values and
- then calculate the amount of needed dynamic memory (ensuring
- the appropriate CONFIG_SYS_MALLOC_LEN value).
-
CONFIG_LZO
If this option is set, support for LZO compressed images
If defined, then this indicates the I2C bus number for the RTC.
If not defined, then U-Boot assumes that RTC is on I2C bus 0.
- CONFIG_SYS_DTT_BUS_NUM
-
- If defined, then this indicates the I2C bus number for the DTT.
- If not defined, then U-Boot assumes that DTT is on I2C bus 0.
-
- CONFIG_SYS_I2C_DTT_ADDR:
-
- If defined, specifies the I2C address of the DTT device.
- If not defined, then U-Boot uses predefined value for
- specified DTT device.
-
CONFIG_SOFT_I2C_READ_REPEATED_START
defining this will force the i2c_read() function in
Specify the number of FPGA devices to support.
- CONFIG_CMD_FPGA_LOADMK
-
- Enable support for fpga loadmk command
-
- CONFIG_CMD_FPGA_LOADP
-
- Enable support for fpga loadp command - load partial bitstream
-
- CONFIG_CMD_FPGA_LOADBP
-
- Enable support for fpga loadbp command - load partial bitstream
- (Xilinx only)
-
CONFIG_SYS_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.
but sometimes that is not allowed.
- Hashing support:
- CONFIG_CMD_HASH
-
- This enables a generic 'hash' command which can produce
- hashes / digests from a few algorithms (e.g. SHA1, SHA256).
-
CONFIG_HASH_VERIFY
Enable the hash verify command (hash -v). This adds to code
size a little.
- CONFIG_SHA1 - This option enables support of hashing using SHA1
- algorithm. The hash is calculated in software.
- CONFIG_SHA256 - This option enables support of hashing using
- SHA256 algorithm. The hash is calculated in software.
- CONFIG_SHA_HW_ACCEL - This option enables hardware acceleration
- for SHA1/SHA256 hashing.
- This affects the 'hash' command and also the
- hash_lookup_algo() function.
- CONFIG_SHA_PROG_HW_ACCEL - This option enables
- hardware-acceleration for SHA1/SHA256 progressive hashing.
- Data can be streamed in a block at a time and the hashing
- is performed in hardware.
-
Note: There is also a sha1sum command, which should perhaps
be deprecated in favour of 'hash sha1'.
-- Freescale i.MX specific commands:
- CONFIG_CMD_HDMIDETECT
- This enables 'hdmidet' command which returns true if an
- HDMI monitor is detected. This command is i.MX 6 specific.
-
- bootcount support:
CONFIG_BOOTCOUNT_LIMIT
This define is introduced, as the legacy image format is
enabled per default for backward compatibility.
-- FIT image support:
- CONFIG_FIT_DISABLE_SHA256
- Supporting SHA256 hashes has quite an impact on binary size.
- For constrained systems sha256 hash support can be disabled
- with this option.
-
- TODO(sjg@chromium.org): Adjust this option to be positive,
- and move it to Kconfig
-
- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
void dev_stor_init(void)
{
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_IDE)
specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE;
specs[ENUM_IDE].enum_started = 0;
specs[ENUM_IDE].enum_ended = 0;
config MICROBLAZE
bool "MicroBlaze architecture"
select SUPPORT_OF_CONTROL
+ imply CMD_IRQ
config MIPS
bool "MIPS architecture"
config NDS32
bool "NDS32 architecture"
+ select SUPPORT_OF_CONTROL
config NIOS2
bool "Nios II architecture"
select DM_SPI
select DM_GPIO
select DM_MMC
+ imply CMD_GETTIME
+ imply CMD_HASH
+ imply CMD_IO
+ imply CMD_IOTRACE
+ imply LZMA
+ imply CMD_LZMADEC
config SH
bool "SuperH architecture"
select DM_SPI_FLASH
select USB_EHCI_HCD
select DM_MMC if MMC
+ imply CMD_FPGA_LOADMK
+ imply CMD_GETTIME
+ imply CMD_IO
+ imply CMD_IRQ
config XTENSA
bool "Xtensa architecture"
config ARCH_AT91
bool "Atmel AT91"
+ select SPL_BOARD_INIT if SPL
config TARGET_EDB93XX
bool "Support edb93xx"
config TARGET_BCMCYGNUS
bool "Support bcmcygnus"
select CPU_V7
+ imply CMD_HASH
config TARGET_BCMNSP
bool "Support bcmnsp"
config ARCH_OMAP2PLUS
bool "TI OMAP2+"
select CPU_V7
+ select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
imply FIT
select CPU_V7
select SUPPORT_SPL
select OF_CONTROL
+ select SPL_BOARD_INIT if SPL
select SPL_OF_CONTROL if SPL
select DM
select DM_ETH
select DM_SERIAL
select SUPPORT_SPL
select CLK
+ select SPL_BOARD_INIT if SPL
select SPL_CLK
select DM_USB if USB
select OF_CONTROL
select OF_LIBFDT
select PINCTRL
+ select SPL_BOARD_INIT if SPL
select SPL_DM if SPL
select SPL_LIBCOMMON_SUPPORT if SPL
select SPL_LIBGENERIC_SUPPORT if SPL
select ARM_ERRATA_751472 if !MX6UL
select ARM_ERRATA_761320 if !MX6UL
select ARM_ERRATA_794072 if !MX6UL
+ imply CMD_FUSE
config MX6D
bool
select CPU_V7_HAS_VIRT
select CPU_V7_HAS_NONSEC
select ARCH_SUPPORT_PSCI
+ imply CMD_FUSE
default y
config MX7D
select ROM_UNIFIED_SECTIONS
+ imply CMD_FUSE
bool
choice
Freescale secure boot mechanism. This command encapsulates and
creates a blob of data. See also CMD_BLOB and doc/README.mxc_hab for
more information.
+
+config CMD_HDMIDETECT
+ bool "Support the 'hdmidet' command"
+ help
+ This enables the 'hdmidet' command which detects if an HDMI monitor
+ is connected.
#define BOOT0_MAGIC "eGON.BT0"
#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
-#define SPL_HEADER_VERSION 1
+#define SPL_HEADER_VERSION 2
#ifdef CONFIG_SUNXI_HIGH_SRAM
#define SPL_ADDR 0x10000
* compatible format, ready to be imported via "env import -t".
*/
uint32_t fel_uEnv_length;
- uint32_t reserved1[2];
+ /*
+ * Offset of an ASCIIZ string (relative to the SPL header), which
+ * contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE).
+ * This is optional and may be set to NULL. Is intended to be used
+ * by flash programming tools for providing nice informative messages
+ * to the users.
+ */
+ uint32_t dt_name_offset;
+ uint32_t reserved1;
uint32_t boot_media; /* written here by the boot ROM */
- uint32_t reserved2[5]; /* padding, align to 64 bytes */
+ /* A padding area (may be used for storing text strings) */
+ uint32_t string_pool[13];
+ /* The header must be a multiple of 32 bytes (for VBAR alignment) */
};
+/* Compile time check to assure proper alignment of structure */
+typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)];
+
#define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
#endif
#define __FSL_SECURE_BOOT_H
#ifdef CONFIG_CHAIN_OF_TRUST
-#define CONFIG_CMD_ESBC_VALIDATE
#define CONFIG_FSL_SEC_MON
-#define CONFIG_SHA_HW_ACCEL
-#define CONFIG_SHA_PROG_HW_ACCEL
-#define CONFIG_SPL_BOARD_INIT
#ifdef CONFIG_SPL_BUILD
/*
* Define the key hash for U-Boot here if public/private key pair used to
#define CONFIG_KEY_REVOCATION
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_HASH
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
* is picked up from an Extension Table which has
ifdef CONFIG_CPU_V7M
obj-y += interrupts_m.o
else ifdef CONFIG_ARM64
-obj-y += ccn504.o
+obj-$(CONFIG_FSL_LAYERSCAPE) += ccn504.o
+ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),)
obj-y += gic_64.o
+endif
obj-y += interrupts_64.o
else
obj-y += interrupts.o
bool "Exynos5 SoC family"
select CPU_V7
select BOARD_EARLY_INIT_F
+ select SHA_HW_ACCEL
+ imply CMD_HASH
help
Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
config TARGET_K2HK_EVM
bool "TI Keystone 2 Kepler/Hawking EVM"
+ select SPL_BOARD_INIT if SPL
imply DM_I2C
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
+ select SPL_BOARD_INIT if SPL
imply DM_I2C
config TARGET_K2L_EVM
bool "TI Keystone 2 Lamar EVM"
+ select SPL_BOARD_INIT if SPL
imply DM_I2C
config TARGET_K2G_EVM
bool "TI Keystone 2 Galileo EVM"
select BOARD_LATE_INIT
+ select SPL_BOARD_INIT if SPL
select TI_I2C_BOARD_DETECT
imply DM_I2C
/*
* IDE Support on SATA ports
*/
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#define __io
#define CONFIG_MVSATA_IDE
#define CONFIG_IDE_PREINIT
#define CONFIG_SYS_ATA_STRIDE 4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
-/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+/* CONFIG_IDE requires some #defines for ATA registers */
#define CONFIG_SYS_IDE_MAXBUS 2
#define CONFIG_SYS_IDE_MAXDEVICE 2
/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
-#endif /* CONFIG_CMD_IDE */
+#endif /* CONFIG_IDE */
/*
* I2C related stuff
config ROCKCHIP_RK3188
bool "Support Rockchip RK3188"
select CPU_V7
+ select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
select SUPPORT_TPL
select SPL
config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
select CPU_V7
+ select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
select SPL
help
config TARGET_SOCFPGA_ARRIA10
bool
+ select SPL_BOARD_INIT if SPL
config TARGET_SOCFPGA_CYCLONE5
bool
select SUNXI_GEN_SUN6I
select SUNXI_HIGH_SRAM
select SUPPORT_SPL
+ select FIT
+ select SPL_LOAD_FIT
config MACH_SUN50I_H5
bool "sun50i (Allwinner H5)"
select ARM64
select MACH_SUNXI_H3_H5
select SUNXI_HIGH_SRAM
+ select FIT
+ select SPL_LOAD_FIT
endchoice
bool "Tegra 32-bit common options"
select CPU_V7
select SPL
+ select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
select TEGRA_COMMON
select TEGRA_GPIO
source "arch/arm/mach-tegra/tegra210/Kconfig"
source "arch/arm/mach-tegra/tegra186/Kconfig"
+config CMD_ENTERRCM
+ bool "Enable 'enterrcm' command"
+ default y
+ help
+ Tegra's boot ROM supports a mode whereby code may be downloaded and
+ flash-programmed over a USB connection. On dev boards, this is
+ typically entered by holding down a "force recovery" button and
+ resetting the CPU. However, not all boards have such a button (one
+ example is the Compulab Trimslice), so a method to enter RCM from
+ software is useful.
+
+ Even on boards other than Trimslice, controlling this over a UART
+ may be useful, e.g. to allow simple remote control without the need
+ for mechanical button actuators, or hooking up relays/... to the
+ button.
+
endif
config TARGET_ADP_AG101P
bool "Support adp-ag101p"
+config TARGET_ADP_AE3XX
+ bool "Support adp-ae3xx"
+
endchoice
source "board/AndesTech/adp-ag101p/Kconfig"
+source "board/AndesTech/adp-ae3xx/Kconfig"
endmenu
extra-y = start.o
obj-$(if $(filter ag101,$(SOC)),y) += ag101/
+obj-$(if $(filter ae3xx,$(SOC)),y) += ae3xx/
--- /dev/null
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cpu.o timer.o
+obj-y += lowlevel_init.o
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+obj-y += watchdog.o
+endif
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ /* turn off I/D-cache */
+ cache_flush();
+ icache_disable();
+ dcache_disable();
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ disable_interrupts();
+ panic("AE3XX wdt not support yet.\n");
+}
--- /dev/null
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.pic
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#include <asm/macro.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
+#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
+#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
+#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
+#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
+
+#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
+#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
+#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
+#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
+
+#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
+#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
+
+
+/*
+ * for Orca and Emerald
+ */
+#define BOARD_ID_REG 0x104
+#define BOARD_ID_FAMILY_MASK 0xfff000
+#define BOARD_ID_FAMILY_V5 0x556000
+#define BOARD_ID_FAMILY_K7 0x74b000
+
+/*
+ * parameters for the static memory controller
+ */
+#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
+#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
+
+#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
+#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
+
+/*
+ * for Orca and Emerald
+ */
+#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
+#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the pmu controoler
+ */
+#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
+
+/*
+ * numeric 7 segment display
+ */
+.macro led, num
+ write32 CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro wait_sdram
+ li $r0, CONFIG_FTSDMC021_BASE
+1:
+ lwi $r1, [$r0+FTSDMC021_CR2]
+ bnez $r1, 1b
+.endm
+
+.globl mem_init
+mem_init:
+ move $r11, $lp
+ li $r0, SMC_BANK0_CR_A
+ lwi $r1, [$r0+#0x00]
+ ori $r1, $r1, 0x8f0
+ xori $r1, $r1, 0x8f0
+ /* 16-bit mode */
+ ori $r1, $r1, 0x60
+ li $r2, 0x00153153
+ swi $r1, [$r0+#0x00]
+ swi $r2, [$r0+#0x04]
+ move $lp, $r11
+ ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl lowlevel_init
+lowlevel_init:
+ move $r10, $lp
+ jal remap
+
+#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
+ jal enable_fpu
+#endif
+ ret $r10
+
+remap:
+ move $r11, $lp
+relo_base:
+ mfusr $r0, $pc
+
+#ifdef CONFIG_MEM_REMAP
+ li $r4, 0x00000000
+ li $r5, 0x80000000
+ la $r6, _end@GOTOFF
+1:
+ lmw.bim $r12, [$r5], $r19
+ smw.bim $r12, [$r4], $r19
+ blt $r5, $r6, 1b
+#endif /* #ifdef CONFIG_MEM_REMAP */
+ move $lp, $r11
+2:
+ ret
+
+ /*
+ * enable_fpu:
+ * Some of Andes CPU version support FPU coprocessor, if so,
+ * and toolchain support FPU instruction set, we should enable it.
+ */
+#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
+enable_fpu:
+ mfsr $r0, $CPU_VER /* enable FPU if it exists */
+ srli $r0, $r0, 3
+ andi $r0, $r0, 1
+ beqz $r0, 1f /* skip if no COP */
+ mfsr $r0, $FUCOP_EXIST
+ srli $r0, $r0, 31
+ beqz $r0, 1f /* skip if no FPU */
+ mfsr $r0, $FUCOP_CTL
+ ori $r0, $r0, 1
+ mtsr $r0, $FUCOP_CTL
+1:
+ ret
+#endif
+
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
--- /dev/null
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef CONFIG_TIMER
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+#error "AE3XX timer only support DM flow"
+#endif /* CONFIG_TIMER */
--- /dev/null
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch-ag101/ag101.h>
+#include <linux/linkage.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+ENTRY(turnoff_watchdog)
+#error "AE3XX not support wdt yet"
+ENDPROC(turnoff_watchdog)
+#endif
#
obj-y := cpu.o timer.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
obj-y += lowlevel_init.o
-endif
ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
obj-y += watchdog.o
{
disable_interrupts();
-#ifdef CONFIG_MMU
/* turn off I/D-cache */
+ cache_flush();
icache_disable();
dcache_disable();
-
- /* flush I/D-cache */
- invalidate_icac();
- invalidate_dcac();
-#endif
-
return 0;
}
bnez $r1, 1b
.endm
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-.globl lowlevel_init
-lowlevel_init:
- move $r10, $lp
-
- led 0x0
- jal mem_init
-
- led 0x10
- jal remap
-
-#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
- led 0x1f
- jal enable_fpu
-#endif
-
- led 0x20
- ret $r10
-
+.globl mem_init
mem_init:
move $r11, $lp
lwi $r1, [$r0+#0x00]
ori $r1, $r1, 0x8f0
xori $r1, $r1, 0x8f0
- /*
- * check board
- */
+ /* check board */
li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
lwi $r3, [$r3]
li $r4, BOARD_ID_FAMILY_MASK
li $r4, BOARD_ID_FAMILY_K7
xor $r4, $r3, $r4
beqz $r4, use_flash_16bit_boot
- /*
- * 32-bit mode
- */
+ /* 32-bit mode */
use_flash_32bit_boot:
ori $r1, $r1, 0x50
li $r2, 0x00151151
j sdram_b0_cr
- /*
- * 16-bit mode
- */
+ /* 16-bit mode */
use_flash_16bit_boot:
ori $r1, $r1, 0x60
li $r2, 0x00153153
- /*
- * SRAM bank0 config
- */
+ /* SRAM bank0 config */
sdram_b0_cr:
swi $r1, [$r0+#0x00]
swi $r2, [$r0+#0x04]
- /*
- * config AHB Controller
- */
+ /* config AHB Controller */
led 0x02
/*
move $lp, $r11
ret
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+.globl lowlevel_init
+lowlevel_init:
+ move $r10, $lp
+ led 0x10
+ jal remap
+#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
+ led 0x1f
+ jal enable_fpu
+#endif
+ led 0x20
+ ret $r10
+
remap:
move $r11, $lp
#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
mfusr $r0, $pc
#endif /* __NDS32_N1213_43U1H__ */
- /*
- * Remapping
- */
+ /* Remapping */
led 0x1a
write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800
write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
+#ifndef CONFIG_TIMER
#include <common.h>
#include <asm/io.h>
#include <faraday/fttmr010.h>
return CONFIG_SYS_CLK_FREQ;
#endif
}
+#endif /* CONFIG_TIMER */
set_ivb:
li $r0, 0x0
-
/* turn on BTB */
mtsr $r0, $misc_ctl
/* set IVIC, vector size: 4 bytes, base: 0x0 */
mtsr $r0, $ivb
+/*
+ * MMU_CTL NTC0 Cacheable/Write-Back
+ */
+ li $r0, ~0x3
+ mfsr $r1, $mr8
+ and $r1, $r1, $r0
+ mtsr $r1, $mr8
+#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
+ li $r0, 0x4
+ mfsr $r1, $mr0
+ or $r1, $r1, $r0
+ mtsr $r1, $mr0
+#endif
+
+#if !defined(CONFIG_SYS_ICACHE_OFF)
+ li $r0, 0x1
+ mfsr $r1, $mr8
+ or $r1, $r1, $r0
+ mtsr $r1, $mr8
+#endif
+
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+ li $r0, 0x2
+ mfsr $r1, $mr8
+ or $r1, $r1, $r0
+ mtsr $r1, $mr8
+#endif
+
+ jal mem_init
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
jal lowlevel_init
ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
add5.pc $gp
#endif
-
/*
* do critical initializations first (shall be in short time)
* do self_relocation ASAP.
*/
call_board_init_f:
li $sp, CONFIG_SYS_INIT_SP_ADDR
- li $r10, GD_SIZE /* get GD size */
- sub $sp, $sp, $r10 /* GD start addr */
- move $r10, $sp
+ move $r0, $sp
+ bal board_init_f_alloc_reserve
+ move $sp, $r0
+ bal board_init_f_init_reserve
+#ifdef CONFIG_DEBUG_UART
+ bal debug_uart_init
+#endif
li $r0, 0x00000000
-
#ifdef __PIC__
#ifdef __NDS32_N1213_43U1H__
/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
la $r1, _end@GOTOFF
move $r2, $r6 /* r2 <- scratch for copy_loop */
-
copy_loop:
- lwi.p $r7, [$r0], #4
- swi.p $r7, [$r2], #4
+ lmw.bim $r11, [$r0], $r18
+ smw.bim $r11, [$r2], $r18
blt $r0, $r1, copy_loop
-
/*
* fix relocations related issues
*/
* initialization, now running from RAM.
*/
call_board_init_r:
+ bal invalidate_icache_all
+ bal flush_dcache_all
la $r0, board_init_r@GOTOFF
move $lp, $r0 /* offset of board_init_r() */
add $lp, $lp, $r9 /* real address of board_init_r() */
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb
+dtb-$(CONFIG_TARGET_ADP_AE3XX) += ae3xx.dtb
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := *.dtb
--- /dev/null
+/dts-v1/;
+/ {
+ compatible = "nds32 ae3xx";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ aliases {
+ uart0 = &serial0;
+ } ;
+
+ chosen {
+ /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */
+ bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
+ stdout-path = "uart0:38400n8";
+ tick-timer = &timer0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "andestech,n13";
+ reg = <0>;
+ /* FIXME: to fill correct frqeuency */
+ clock-frequency = <60000000>;
+ };
+ };
+
+ intc: interrupt-controller {
+ compatible = "andestech,atnointc010";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ serial0: serial@f0300000 {
+ compatible = "andestech,uart16550", "ns16550a";
+ reg = <0xf0300000 0x1000>;
+ interrupts = <7 4>;
+ clock-frequency = <14745600>;
+ reg-shift = <2>;
+ reg-offset = <32>;
+ no-loopback-test = <1>;
+ };
+
+ timer0: timer@f0400000 {
+ compatible = "andestech,atcpit100";
+ reg = <0xf0400000 0x1000>;
+ interrupts = <2 4>;
+ clock-frequency = <30000000>;
+ };
+
+ nor@0,0 {
+ compatible = "cfi-flash";
+ reg = <0x88000000 0x1000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+};
--- /dev/null
+/dts-v1/;
+/ {
+ compatible = "nds32 ag101p";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ aliases {
+ uart0 = &serial0;
+ } ;
+
+ chosen {
+ /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */
+ bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7";
+ stdout-path = "uart0:38400n8";
+ tick-timer = &timer0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "andestech,n13";
+ reg = <0>;
+ /* FIXME: to fill correct frqeuency */
+ clock-frequency = <60000000>;
+ };
+ };
+
+ intc: interrupt-controller {
+ compatible = "andestech,atnointc010";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ serial0: serial@99600000 {
+ compatible = "andestech,uart16550", "ns16550a";
+ reg = <0x99600000 0x1000>;
+ interrupts = <7 4>;
+ clock-frequency = <14745600>;
+ reg-shift = <2>;
+ no-loopback-test = <1>;
+ };
+
+ timer0: timer@98400000 {
+ compatible = "andestech,attmr010";
+ reg = <0x98400000 0x1000>;
+ interrupts = <19 4>;
+ clock-frequency = <15000000>;
+ };
+
+};
--- /dev/null
+/*
+ * Copyright (C) 2016 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AE3XX_H
+#define __AE3XX_H
+
+/* Hardware register bases */
+
+/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSMC020_BASE 0xe0400000
+/* DMA Controller */
+#define CONFIG_FTDMAC020_BASE 0xf0c00000
+/* AHB-to-APB Bridge */
+#define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000
+/* Reserved */
+#define CONFIG_RESERVED_01_BASE 0xe0500000
+/* Reserved */
+#define CONFIG_RESERVED_02_BASE 0xf0800000
+/* Reserved */
+#define CONFIG_RESERVED_03_BASE 0xf0900000
+/* Ethernet */
+#define CONFIG_FTMAC100_BASE 0xe0100000
+/* Reserved */
+#define CONFIG_RESERVED_04_BASE 0xf1000000
+
+/* APB Device definitions */
+
+/* UART1 */
+#define CONFIG_FTUART010_01_BASE 0xf0200000
+/* UART2 */
+#define CONFIG_FTUART010_02_BASE 0xf0300000
+/* Counter/Timers */
+#define CONFIG_FTTMR010_BASE 0xf0400000
+/* Watchdog Timer */
+#define CONFIG_FTWDT010_BASE 0xf0500000
+/* Real Time Clock */
+#define CONFIG_FTRTC010_BASE 0xf0600000
+/* GPIO */
+#define CONFIG_FTGPIO010_BASE 0xf0700000
+/* I2C */
+#define CONFIG_FTIIC010_BASE 0xf0a00000
+/* SD Controller */
+#define CONFIG_FTSDC010_BASE 0xf0e00000
+
+/* The following address was not defined in Linux */
+
+/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_FTSSP010_01_BASE 0xf0d00000
+#endif /* __AE3XX_H */
--- /dev/null
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef NDS32_BOOTM_H
+#define NDS32_BOOTM_H
+
+extern void udc_disconnect(void);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+ defined(CONFIG_CMDLINE_TAG) || \
+ defined(CONFIG_INITRD_TAG) || \
+ defined(CONFIG_SERIAL_TAG) || \
+ defined(CONFIG_REVISION_TAG)
+# define BOOTM_ENABLE_TAGS 1
+#else
+# define BOOTM_ENABLE_TAGS 0
+#endif
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+# define BOOTM_ENABLE_MEMORY_TAGS 1
+#else
+# define BOOTM_ENABLE_MEMORY_TAGS 0
+#endif
+
+#ifdef CONFIG_CMDLINE_TAG
+ #define BOOTM_ENABLE_CMDLINE_TAG 1
+#else
+ #define BOOTM_ENABLE_CMDLINE_TAG 0
+#endif
+
+#ifdef CONFIG_INITRD_TAG
+ #define BOOTM_ENABLE_INITRD_TAG 1
+#else
+ #define BOOTM_ENABLE_INITRD_TAG 0
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+ #define BOOTM_ENABLE_SERIAL_TAG 1
+void get_board_serial(struct tag_serialnr *serialnr);
+#else
+ #define BOOTM_ENABLE_SERIAL_TAG 0
+static inline void get_board_serial(struct tag_serialnr *serialnr)
+{
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+ #define BOOTM_ENABLE_REVISION_TAG 1
+u32 get_board_rev(void);
+#else
+ #define BOOTM_ENABLE_REVISION_TAG 0
+static inline u32 get_board_rev(void)
+{
+ return 0;
+}
+#endif
+
+#endif
int dcache_status(void);
void dcache_enable(void);
void dcache_disable(void);
+void cache_flush(void);
#define DEFINE_GET_SYS_REG(reg) \
static inline unsigned long GET_##reg(void) \
enum cache_t {ICACHE, DCACHE};
DEFINE_GET_SYS_REG(ICM_CFG);
DEFINE_GET_SYS_REG(DCM_CFG);
-#define ICM_CFG_OFF_ISZ 6 /* I-cache line size */
-#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ)
-#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */
-#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ)
+/* I-cache sets (# of cache lines) per way */
+#define ICM_CFG_OFF_ISET 0
+/* I-cache ways */
+#define ICM_CFG_OFF_IWAY 3
+#define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET)
+#define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY)
+/* D-cache sets (# of cache lines) per way */
+#define DCM_CFG_OFF_DSET 0
+/* D-cache ways */
+#define DCM_CFG_OFF_DWAY 3
+#define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET)
+#define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY)
+/* I-cache line size */
+#define ICM_CFG_OFF_ISZ 6
+#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ)
+/* D-cache line size */
+#define DCM_CFG_OFF_DSZ 6
+#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ)
/*
* The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_LMB
#endif
/* see arch/arm/kernel/arch.c for a description of these */
#define MACH_TYPE_ADPAG101P 1
+#define MACH_TYPE_ADPAE3XX 2
#ifdef CONFIG_ARCH_ADPAG101P
# ifdef machine_arch_type
obj-y += cache.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_GO) += boot.o
obj-y += interrupts.o
--- /dev/null
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long do_go_exec(ulong (*entry)(int, char * const []),
+ int argc, char * const argv[])
+{
+ cleanup_before_linux();
+
+ return entry(argc, argv);
+}
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
+#include <asm/bootm.h>
DECLARE_GLOBAL_DATA_PTR;
+int arch_fixup_fdt(void *blob)
+{
+ return 0;
+}
+
+
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \
debug("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)theKernel);
+ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+#ifdef CONFIG_OF_LIBFDT
+ debug("using: FDT\n");
+ if (image_setup_linux(images)) {
+ printf("FDT creation failed! hanging...");
+ hang();
+ }
+#endif
+ } else if (BOOTM_ENABLE_TAGS) {
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \
udc_disconnect();
}
#endif
-
+ }
cleanup_before_linux();
-
- theKernel(0, machid, bd->bi_boot_params);
+ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
+ theKernel(0, machid, (unsigned long)images->ft_addr);
+ else
+ theKernel(0, machid, bd->bi_boot_params);
/* does not return */
return 1;
}
-
#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
defined(CONFIG_CMDLINE_TAG) || \
defined(CONFIG_INITRD_TAG) || \
params = tag_next(params);
}
-
#ifdef CONFIG_SETUP_MEMORY_TAGS
static void setup_memory_tags(bd_t *bd)
{
}
#endif /* CONFIG_SETUP_MEMORY_TAGS */
-
static void setup_commandline_tag(bd_t *bd, char *commandline)
{
char *p;
params = tag_next(params);
}
-
#ifdef CONFIG_INITRD_TAG
static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
{
}
#endif /* CONFIG_REVISION_TAG */
-
static void setup_end_tag(bd_t *bd)
{
params->hdr.tag = ATAG_NONE;
*/
#include <common.h>
+#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))
+static inline unsigned long CACHE_SET(unsigned char cache)
+{
+ if (cache == ICACHE)
+ return 64 << ((GET_ICM_CFG() & ICM_CFG_MSK_ISET) \
+ >> ICM_CFG_OFF_ISET);
+ else
+ return 64 << ((GET_DCM_CFG() & DCM_CFG_MSK_DSET) \
+ >> DCM_CFG_OFF_DSET);
+}
+
+static inline unsigned long CACHE_WAY(unsigned char cache)
+{
+ if (cache == ICACHE)
+ return 1 + ((GET_ICM_CFG() & ICM_CFG_MSK_IWAY) \
+ >> ICM_CFG_OFF_IWAY);
+ else
+ return 1 + ((GET_DCM_CFG() & DCM_CFG_MSK_DWAY) \
+ >> DCM_CFG_OFF_DWAY);
+}
static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
{
if (cache == ICACHE)
return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
- >> ICM_CFG_OFF_ISZ) - 1);
+ >> ICM_CFG_OFF_ISZ) - 1);
else
return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
- >> DCM_CFG_OFF_DSZ) - 1);
+ >> DCM_CFG_OFF_DSZ) - 1);
}
+#endif
-void flush_dcache_range(unsigned long start, unsigned long end)
+#ifndef CONFIG_SYS_ICACHE_OFF
+void invalidate_icache_all(void)
{
- unsigned long line_size;
+ unsigned long end, line_size;
+ line_size = CACHE_LINE_SIZE(ICACHE);
+ end = line_size * CACHE_WAY(ICACHE) * CACHE_SET(ICACHE);
+ do {
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
- line_size = CACHE_LINE_SIZE(DCACHE);
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
- while (end > start) {
- asm volatile (
- "\n\tcctl %0, L1D_VA_WB"
- "\n\tcctl %0, L1D_VA_INVAL"
- :
- : "r" (start)
- );
- start += line_size;
- }
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
+ } while (end > 0);
}
void invalidate_icache_range(unsigned long start, unsigned long end)
}
}
-void invalidate_dcache_range(unsigned long start, unsigned long end)
-{
- unsigned long line_size;
-
- line_size = CACHE_LINE_SIZE(DCACHE);
- while (end > start) {
- asm volatile (
- "\n\tcctl %0, L1D_VA_INVAL"
- :
- : "r"(start)
- );
- start += line_size;
- }
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
- flush_dcache_range(addr, addr + size);
- invalidate_icache_range(addr, addr + size);
-}
-
void icache_enable(void)
{
asm volatile (
return ret;
}
+#else
+void invalidate_icache_all(void)
+{
+}
+
+void invalidate_icache_range(unsigned long start, unsigned long end)
+{
+}
+
+void icache_enable(void)
+{
+}
+
+void icache_disable(void)
+{
+}
+
+int icache_status(void)
+{
+ return 0;
+}
+
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void dcache_wbinval_all(void)
+{
+ unsigned long end, line_size;
+ line_size = CACHE_LINE_SIZE(DCACHE);
+ end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE);
+ do {
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
+ __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
+ __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
+ __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
+ __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
+
+ } while (end > 0);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(DCACHE);
+
+ while (end > start) {
+ asm volatile (
+ "\n\tcctl %0, L1D_VA_WB"
+ "\n\tcctl %0, L1D_VA_INVAL" : : "r" (start)
+ );
+ start += line_size;
+ }
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(DCACHE);
+ while (end > start) {
+ asm volatile (
+ "\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)
+ );
+ start += line_size;
+ }
+}
+
void dcache_enable(void)
{
asm volatile (
int dcache_status(void)
{
int ret;
-
asm volatile (
"mfsr $p0, $mr8\n\t"
"andi %0, $p0, 0x02\n\t"
:
: "memory"
);
-
return ret;
}
+
+#else
+void dcache_wbinval_all(void)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+ return 0;
+}
+
+#endif
+
+
+void flush_dcache_all(void)
+{
+ dcache_wbinval_all();
+}
+
+void cache_flush(void)
+{
+ flush_dcache_all();
+ invalidate_icache_all();
+}
+
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+ flush_dcache_range(addr, addr + size);
+ invalidate_icache_range(addr, addr + size);
+}
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
imply USB_EHCI_HCD if USB
+ imply CMD_HASH
+ imply CMD_IRQ
config MPC86xx
bool "MPC86xx"
config 4xx
bool "PPC4xx"
select CREATE_ARCH_SYMLINK
+ imply CMD_IRQ
endchoice
+source "arch/powerpc/lib/Kconfig"
+
source "arch/powerpc/cpu/mpc512x/Kconfig"
source "arch/powerpc/cpu/mpc5xx/Kconfig"
source "arch/powerpc/cpu/mpc5xxx/Kconfig"
config TARGET_DIGSY_MTC
bool "Support digsy_mtc"
+ imply CMD_IRQ
config TARGET_PCM030
bool "Support pcm030"
*/
#include <common.h>
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_IDE)
#include <mpc5xxx.h>
DECLARE_GLOBAL_DATA_PTR;
config TARGET_MPC8349ITX
bool "Support MPC8349ITX"
+ imply CMD_IRQ
config TARGET_MPC837XEMDS
bool "Support MPC837XEMDS"
config SYS_CPU
default "mpc85xx"
+config CMD_ERRATA
+ bool "Enable the 'errata' command"
+ depends on MPC85xx
+ default y
+ help
+ This enables the 'errata' command which displays a list of errata
+ work-arounds which are enabled for the current board.
+
choice
prompt "Target select"
optional
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select SUPPORT_TPL
+ imply CMD_EEPROM
config TARGET_P1010RDB_PB
bool "Support P1010RDB_PB"
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select SUPPORT_TPL
+ imply CMD_EEPROM
config TARGET_P1022DS
bool "Support P1022DS"
config TARGET_P1023RDB
bool "Support P1023RDB"
select ARCH_P1023
+ imply CMD_EEPROM
config TARGET_P1020MBG
bool "Support P1020MBG-PC"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1020
+ imply CMD_EEPROM
config TARGET_P1020RDB_PC
bool "Support P1020RDB-PC"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1020
+ imply CMD_EEPROM
config TARGET_P1020RDB_PD
bool "Support P1020RDB-PD"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1020
+ imply CMD_EEPROM
config TARGET_P1020UTM
bool "Support P1020UTM"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1020
+ imply CMD_EEPROM
config TARGET_P1021RDB
bool "Support P1021RDB"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1021
+ imply CMD_EEPROM
config TARGET_P1024RDB
bool "Support P1024RDB"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1024
+ imply CMD_EEPROM
config TARGET_P1025RDB
bool "Support P1025RDB"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1025
+ imply CMD_EEPROM
config TARGET_P2020RDB
bool "Support P2020RDB-PC"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P2020
+ imply CMD_EEPROM
config TARGET_P1_TWR
bool "Support p1_twr"
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ imply CMD_EEPROM
config TARGET_T1023RDB
bool "Support T1023RDB"
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ imply CMD_EEPROM
config TARGET_T1024RDB
bool "Support T1024RDB"
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ imply CMD_EEPROM
config TARGET_T1040QDS
bool "Support T1040QDS"
select ARCH_T1040
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select PHYS_64BIT
+ imply CMD_EEPROM
config TARGET_T1040RDB
bool "Support T1040RDB"
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_IFC
+ imply CMD_EEPROM
config ARCH_B4860
bool
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_IFC
+ imply CMD_EEPROM
config ARCH_BSC9131
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select FSL_IFC
+ imply CMD_EEPROM
config ARCH_BSC9132
bool
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_IFC
+ imply CMD_EEPROM
config ARCH_C29X
bool
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_IFC
+ imply CMD_EEPROM
config ARCH_P1011
bool
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
+ imply CMD_EEPROM
config ARCH_P1025
bool
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_ELBC
+ imply CMD_EEPROM
config ARCH_P2041
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
select FSL_IFC
+ imply CMD_EEPROM
config ARCH_T1024
bool
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
select FSL_IFC
+ imply CMD_EEPROM
config ARCH_T1040
bool
and control the CPU and peripehrals clocks. The programmed
configuration is then used when the board boots.
+config CMD_ECCTEST
+ bool "Enable the 'ecctest' command"
+ help
+ This command tests memory ECC by single and double error bit
+ injection.
+
source "board/amcc/acadia/Kconfig"
source "board/amcc/bamboo/Kconfig"
source "board/amcc/bubinga/Kconfig"
#define CONFIG_SPL_UBOOT_KEY_HASH NULL
#endif /* ifdef CONFIG_SPL_BUILD */
-#define CONFIG_CMD_ESBC_VALIDATE
#define CONFIG_FSL_SEC_MON
-#define CONFIG_SHA_PROG_HW_ACCEL
#ifndef CONFIG_SPL_BUILD
/*
--- /dev/null
+config CMD_IMMAP
+ bool "Enable various commands to dump IMMR information"
+ help
+ This enables various commands such as:
+
+ siuinfo - print System Interface Unit (SIU) registers
+ memcinfo - print Memory Controller registers
+ sitinfo - print System Integration Timers (SIT) registers
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o
obj-y += extable.o
+obj-$(CONFIG_CMD_IMMAP) += immap.o
obj-y += interrupts.o
obj-$(CONFIG_CMD_KGDB) += kgdb.o
-obj-$(CONFIG_CMD_IDE) += ide.o
+obj-$(CONFIG_IDE) += ide.o
obj-y += stack.o
obj-y += time.o
--- /dev/null
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * MPC8xx/MPC8260 Internal Memory Map Functions
+ */
+
+#include <common.h>
+#include <command.h>
+
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
+
+#if defined(CONFIG_8xx)
+#include <asm/8xx_immap.h>
+#include <commproc.h>
+#include <asm/iopin_8xx.h>
+#elif defined(CONFIG_MPC8260)
+#include <asm/immap_8260.h>
+#include <asm/cpm_8260.h>
+#include <asm/iopin_8260.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void
+unimplemented ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ printf ("Sorry, but the '%s' command has not been implemented\n",
+ cmdtp->name);
+}
+
+int
+do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+#if defined(CONFIG_8xx)
+ volatile sysconf8xx_t *sc = &immap->im_siu_conf;
+#elif defined(CONFIG_MPC8260)
+ volatile sysconf8260_t *sc = &immap->im_siu_conf;
+#endif
+
+ printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr);
+#if defined(CONFIG_8xx)
+ printf ("SWT = %08x\n", sc->sc_swt);
+ printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask);
+ printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec);
+ printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr);
+#elif defined(CONFIG_MPC8260)
+ printf ("BCR = %08x\n", sc->sc_bcr);
+ printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n",
+ sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl);
+ printf ("L_ACR = %02x L_ALRH= %08x L_ALRL= %08x\n",
+ sc->sc_lcl_acr, sc->sc_lcl_alrh, sc->sc_lcl_alrl);
+ printf ("PTESR1= %08x PTESR2= %08x\n", sc->sc_tescr1, sc->sc_tescr2);
+ printf ("LTESR1= %08x LTESR2= %08x\n", sc->sc_ltescr1, sc->sc_ltescr2);
+ printf ("PDTEA = %08x PDTEM = %02x\n", sc->sc_pdtea, sc->sc_pdtem);
+ printf ("LDTEA = %08x LDTEM = %02x\n", sc->sc_ldtea, sc->sc_ldtem);
+#endif
+ return 0;
+}
+
+int
+do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+#if defined(CONFIG_8xx)
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ int nbanks = 8;
+#elif defined(CONFIG_MPC8260)
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ int nbanks = 12;
+#endif
+ volatile uint *p = &memctl->memc_br0;
+ int i;
+
+ for (i = 0; i < nbanks; i++, p += 2) {
+ if (i < 10) {
+ printf ("BR%d = %08x OR%d = %08x\n",
+ i, p[0], i, p[1]);
+ } else {
+ printf ("BR%d = %08x OR%d = %08x\n",
+ i, p[0], i, p[1]);
+ }
+ }
+
+ printf ("MAR = %08x", memctl->memc_mar);
+#if defined(CONFIG_8xx)
+ printf (" MCR = %08x\n", memctl->memc_mcr);
+#elif defined(CONFIG_MPC8260)
+ putc ('\n');
+#endif
+ printf ("MAMR = %08x MBMR = %08x",
+ memctl->memc_mamr, memctl->memc_mbmr);
+#if defined(CONFIG_8xx)
+ printf ("\nMSTAT = %04x\n", memctl->memc_mstat);
+#elif defined(CONFIG_MPC8260)
+ printf (" MCMR = %08x\n", memctl->memc_mcmr);
+#endif
+ printf ("MPTPR = %04x MDR = %08x\n",
+ memctl->memc_mptpr, memctl->memc_mdr);
+#if defined(CONFIG_MPC8260)
+ printf ("PSDMR = %08x LSDMR = %08x\n",
+ memctl->memc_psdmr, memctl->memc_lsdmr);
+ printf ("PURT = %02x PSRT = %02x\n",
+ memctl->memc_purt, memctl->memc_psrt);
+ printf ("LURT = %02x LSRT = %02x\n",
+ memctl->memc_lurt, memctl->memc_lsrt);
+ printf ("IMMR = %08x\n", memctl->memc_immr);
+#endif
+ return 0;
+}
+
+int
+do_sitinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unimplemented (cmdtp, flag, argc, argv);
+ return 0;
+}
+
+#ifdef CONFIG_MPC8260
+int
+do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unimplemented (cmdtp, flag, argc, argv);
+ return 0;
+}
+#endif
+
+int
+do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+#if defined(CONFIG_8xx)
+ volatile car8xx_t *car = &immap->im_clkrst;
+#elif defined(CONFIG_MPC8260)
+ volatile car8260_t *car = &immap->im_clkrst;
+#endif
+
+#if defined(CONFIG_8xx)
+ printf ("SCCR = %08x\n", car->car_sccr);
+ printf ("PLPRCR= %08x\n", car->car_plprcr);
+ printf ("RSR = %08x\n", car->car_rsr);
+#elif defined(CONFIG_MPC8260)
+ printf ("SCCR = %08x\n", car->car_sccr);
+ printf ("SCMR = %08x\n", car->car_scmr);
+ printf ("RSR = %08x\n", car->car_rsr);
+ printf ("RMR = %08x\n", car->car_rmr);
+#endif
+ return 0;
+}
+
+static int counter;
+
+static void
+header(void)
+{
+ char *data = "\
+ -------------------------------- --------------------------------\
+ 00000000001111111111222222222233 00000000001111111111222222222233\
+ 01234567890123456789012345678901 01234567890123456789012345678901\
+ -------------------------------- --------------------------------\
+ ";
+ int i;
+
+ if (counter % 2)
+ putc('\n');
+ counter = 0;
+
+ for (i = 0; i < 4; i++, data += 79)
+ printf("%.79s\n", data);
+}
+
+static void binary (char *label, uint value, int nbits)
+{
+ uint mask = 1 << (nbits - 1);
+ int i, second = (counter++ % 2);
+
+ if (second)
+ putc (' ');
+ puts (label);
+ for (i = 32 + 1; i != nbits; i--)
+ putc (' ');
+
+ while (mask != 0) {
+ if (value & mask)
+ putc ('1');
+ else
+ putc ('0');
+ mask >>= 1;
+ }
+
+ if (second)
+ putc ('\n');
+}
+
+#if defined(CONFIG_8xx)
+#define PA_NBITS 16
+#define PA_NB_ODR 8
+#define PB_NBITS 18
+#define PB_NB_ODR 16
+#define PC_NBITS 12
+#define PD_NBITS 13
+#elif defined(CONFIG_MPC8260)
+#define PA_NBITS 32
+#define PA_NB_ODR 32
+#define PB_NBITS 28
+#define PB_NB_ODR 28
+#define PC_NBITS 32
+#define PD_NBITS 28
+#endif
+
+int
+do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+#if defined(CONFIG_8xx)
+ volatile iop8xx_t *iop = &immap->im_ioport;
+ volatile ushort *l, *r;
+#elif defined(CONFIG_MPC8260)
+ volatile iop8260_t *iop = &immap->im_ioport;
+ volatile uint *l, *r;
+#endif
+ volatile uint *R;
+
+ counter = 0;
+ header ();
+
+ /*
+ * Ports A & B
+ */
+
+#if defined(CONFIG_8xx)
+ l = &iop->iop_padir;
+ R = &immap->im_cpm.cp_pbdir;
+#elif defined(CONFIG_MPC8260)
+ l = &iop->iop_pdira;
+ R = &iop->iop_pdirb;
+#endif
+ binary ("PA_DIR", *l++, PA_NBITS);
+ binary ("PB_DIR", *R++, PB_NBITS);
+ binary ("PA_PAR", *l++, PA_NBITS);
+ binary ("PB_PAR", *R++, PB_NBITS);
+#if defined(CONFIG_MPC8260)
+ binary ("PA_SOR", *l++, PA_NBITS);
+ binary ("PB_SOR", *R++, PB_NBITS);
+#endif
+ binary ("PA_ODR", *l++, PA_NB_ODR);
+ binary ("PB_ODR", *R++, PB_NB_ODR);
+ binary ("PA_DAT", *l++, PA_NBITS);
+ binary ("PB_DAT", *R++, PB_NBITS);
+
+ header ();
+
+ /*
+ * Ports C & D
+ */
+
+#if defined(CONFIG_8xx)
+ l = &iop->iop_pcdir;
+ r = &iop->iop_pddir;
+#elif defined(CONFIG_MPC8260)
+ l = &iop->iop_pdirc;
+ r = &iop->iop_pdird;
+#endif
+ binary ("PC_DIR", *l++, PC_NBITS);
+ binary ("PD_DIR", *r++, PD_NBITS);
+ binary ("PC_PAR", *l++, PC_NBITS);
+ binary ("PD_PAR", *r++, PD_NBITS);
+#if defined(CONFIG_8xx)
+ binary ("PC_SO ", *l++, PC_NBITS);
+ binary (" ", 0, 0);
+ r++;
+#elif defined(CONFIG_MPC8260)
+ binary ("PC_SOR", *l++, PC_NBITS);
+ binary ("PD_SOR", *r++, PD_NBITS);
+ binary ("PC_ODR", *l++, PC_NBITS);
+ binary ("PD_ODR", *r++, PD_NBITS);
+#endif
+ binary ("PC_DAT", *l++, PC_NBITS);
+ binary ("PD_DAT", *r++, PD_NBITS);
+#if defined(CONFIG_8xx)
+ binary ("PC_INT", *l++, PC_NBITS);
+#endif
+
+ header ();
+ return 0;
+}
+
+/*
+ * set the io pins
+ * this needs a clean up for smaller tighter code
+ * use *uint and set the address based on cmd + port
+ */
+int
+do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ uint rcode = 0;
+ iopin_t iopin;
+ static uint port = 0;
+ static uint pin = 0;
+ static uint value = 0;
+ static enum {
+ DIR,
+ PAR,
+ SOR,
+ ODR,
+ DAT,
+#if defined(CONFIG_8xx)
+ INT
+#endif
+ } cmd = DAT;
+
+ if (argc != 5) {
+ puts ("iopset PORT PIN CMD VALUE\n");
+ return 1;
+ }
+ port = argv[1][0] - 'A';
+ if (port > 3)
+ port -= 0x20;
+ if (port > 3)
+ rcode = 1;
+ pin = simple_strtol (argv[2], NULL, 10);
+ if (pin > 31)
+ rcode = 1;
+
+
+ switch (argv[3][0]) {
+ case 'd':
+ if (argv[3][1] == 'a')
+ cmd = DAT;
+ else if (argv[3][1] == 'i')
+ cmd = DIR;
+ else
+ rcode = 1;
+ break;
+ case 'p':
+ cmd = PAR;
+ break;
+ case 'o':
+ cmd = ODR;
+ break;
+ case 's':
+ cmd = SOR;
+ break;
+#if defined(CONFIG_8xx)
+ case 'i':
+ cmd = INT;
+ break;
+#endif
+ default:
+ printf ("iopset: unknown command %s\n", argv[3]);
+ rcode = 1;
+ }
+ if (argv[4][0] == '1')
+ value = 1;
+ else if (argv[4][0] == '0')
+ value = 0;
+ else
+ rcode = 1;
+ if (rcode == 0) {
+ iopin.port = port;
+ iopin.pin = pin;
+ iopin.flag = 0;
+ switch (cmd) {
+ case DIR:
+ if (value)
+ iopin_set_out (&iopin);
+ else
+ iopin_set_in (&iopin);
+ break;
+ case PAR:
+ if (value)
+ iopin_set_ded (&iopin);
+ else
+ iopin_set_gen (&iopin);
+ break;
+ case SOR:
+ if (value)
+ iopin_set_opt2 (&iopin);
+ else
+ iopin_set_opt1 (&iopin);
+ break;
+ case ODR:
+ if (value)
+ iopin_set_odr (&iopin);
+ else
+ iopin_set_act (&iopin);
+ break;
+ case DAT:
+ if (value)
+ iopin_set_high (&iopin);
+ else
+ iopin_set_low (&iopin);
+ break;
+#if defined(CONFIG_8xx)
+ case INT:
+ if (value)
+ iopin_set_falledge (&iopin);
+ else
+ iopin_set_anyedge (&iopin);
+ break;
+#endif
+ }
+
+ }
+ return rcode;
+}
+
+int
+do_dmainfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unimplemented (cmdtp, flag, argc, argv);
+ return 0;
+}
+
+int
+do_fccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unimplemented (cmdtp, flag, argc, argv);
+ return 0;
+}
+
+static void prbrg (int n, uint val)
+{
+ uint extc = (val >> 14) & 3;
+ uint cd = (val & CPM_BRG_CD_MASK) >> 1;
+ uint div16 = (val & CPM_BRG_DIV16) != 0;
+
+#if defined(CONFIG_8xx)
+ ulong clock = gd->cpu_clk;
+#elif defined(CONFIG_MPC8260)
+ ulong clock = gd->arch.brg_clk;
+#endif
+
+ printf ("BRG%d:", n);
+
+ if (val & CPM_BRG_RST)
+ puts (" RESET");
+ else
+ puts (" ");
+
+ if (val & CPM_BRG_EN)
+ puts (" ENABLED");
+ else
+ puts (" DISABLED");
+
+ printf (" EXTC=%d", extc);
+
+ if (val & CPM_BRG_ATB)
+ puts (" ATB");
+ else
+ puts (" ");
+
+ printf (" DIVIDER=%4d", cd);
+ if (extc == 0 && cd != 0) {
+ uint baudrate;
+
+ if (div16)
+ baudrate = (clock / 16) / (cd + 1);
+ else
+ baudrate = clock / (cd + 1);
+
+ printf ("=%6d bps", baudrate);
+ } else {
+ puts (" ");
+ }
+
+ if (val & CPM_BRG_DIV16)
+ puts (" DIV16");
+ else
+ puts (" ");
+
+ putc ('\n');
+}
+
+int
+do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+#if defined(CONFIG_8xx)
+ volatile cpm8xx_t *cp = &immap->im_cpm;
+ volatile uint *p = &cp->cp_brgc1;
+#elif defined(CONFIG_MPC8260)
+ volatile uint *p = &immap->im_brgc1;
+#endif
+ int i = 1;
+
+ while (i <= 4)
+ prbrg (i++, *p++);
+
+#if defined(CONFIG_MPC8260)
+ p = &immap->im_brgc5;
+ while (i <= 8)
+ prbrg (i++, *p++);
+#endif
+ return 0;
+}
+
+int
+do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+#if defined(CONFIG_8xx)
+ volatile i2c8xx_t *i2c = &immap->im_i2c;
+ volatile cpm8xx_t *cp = &immap->im_cpm;
+ volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC];
+#elif defined(CONFIG_MPC8260)
+ volatile i2c8260_t *i2c = &immap->im_i2c;
+ volatile iic_t *iip;
+ uint dpaddr;
+
+ dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
+ if (dpaddr == 0)
+ iip = NULL;
+ else
+ iip = (iic_t *) & immap->im_dprambase[dpaddr];
+#endif
+
+ printf ("I2MOD = %02x I2ADD = %02x\n", i2c->i2c_i2mod, i2c->i2c_i2add);
+ printf ("I2BRG = %02x I2COM = %02x\n", i2c->i2c_i2brg, i2c->i2c_i2com);
+ printf ("I2CER = %02x I2CMR = %02x\n", i2c->i2c_i2cer, i2c->i2c_i2cmr);
+
+ if (iip == NULL)
+ puts ("i2c parameter ram not allocated\n");
+ else {
+ printf ("RBASE = %08x TBASE = %08x\n",
+ iip->iic_rbase, iip->iic_tbase);
+ printf ("RFCR = %02x TFCR = %02x\n",
+ iip->iic_rfcr, iip->iic_tfcr);
+ printf ("MRBLR = %04x\n", iip->iic_mrblr);
+ printf ("RSTATE= %08x RDP = %08x\n",
+ iip->iic_rstate, iip->iic_rdp);
+ printf ("RBPTR = %04x RBC = %04x\n",
+ iip->iic_rbptr, iip->iic_rbc);
+ printf ("RXTMP = %08x\n", iip->iic_rxtmp);
+ printf ("TSTATE= %08x TDP = %08x\n",
+ iip->iic_tstate, iip->iic_tdp);
+ printf ("TBPTR = %04x TBC = %04x\n",
+ iip->iic_tbptr, iip->iic_tbc);
+ printf ("TXTMP = %08x\n", iip->iic_txtmp);
+ }
+ return 0;
+}
+
+int
+do_sccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unimplemented (cmdtp, flag, argc, argv);
+ return 0;
+}
+
+int
+do_smcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unimplemented (cmdtp, flag, argc, argv);
+ return 0;
+}
+
+int
+do_spiinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unimplemented (cmdtp, flag, argc, argv);
+ return 0;
+}
+
+int
+do_muxinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unimplemented (cmdtp, flag, argc, argv);
+ return 0;
+}
+
+int
+do_siinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unimplemented (cmdtp, flag, argc, argv);
+ return 0;
+}
+
+int
+do_mccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unimplemented (cmdtp, flag, argc, argv);
+ return 0;
+}
+
+/***************************************************/
+
+U_BOOT_CMD(
+ siuinfo, 1, 1, do_siuinfo,
+ "print System Interface Unit (SIU) registers",
+ ""
+);
+
+U_BOOT_CMD(
+ memcinfo, 1, 1, do_memcinfo,
+ "print Memory Controller registers",
+ ""
+);
+
+U_BOOT_CMD(
+ sitinfo, 1, 1, do_sitinfo,
+ "print System Integration Timers (SIT) registers",
+ ""
+);
+
+#ifdef CONFIG_MPC8260
+U_BOOT_CMD(
+ icinfo, 1, 1, do_icinfo,
+ "print Interrupt Controller registers",
+ ""
+);
+#endif
+
+U_BOOT_CMD(
+ carinfo, 1, 1, do_carinfo,
+ "print Clocks and Reset registers",
+ ""
+);
+
+U_BOOT_CMD(
+ iopinfo, 1, 1, do_iopinfo,
+ "print I/O Port registers",
+ ""
+);
+
+U_BOOT_CMD(
+ iopset, 5, 0, do_iopset,
+ "set I/O Port registers",
+ "PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1"
+);
+
+U_BOOT_CMD(
+ dmainfo, 1, 1, do_dmainfo,
+ "print SDMA/IDMA registers",
+ ""
+);
+
+U_BOOT_CMD(
+ fccinfo, 1, 1, do_fccinfo,
+ "print FCC registers",
+ ""
+);
+
+U_BOOT_CMD(
+ brginfo, 1, 1, do_brginfo,
+ "print Baud Rate Generator (BRG) registers",
+ ""
+);
+
+U_BOOT_CMD(
+ i2cinfo, 1, 1, do_i2cinfo,
+ "print I2C registers",
+ ""
+);
+
+U_BOOT_CMD(
+ sccinfo, 1, 1, do_sccinfo,
+ "print SCC registers",
+ ""
+);
+
+U_BOOT_CMD(
+ smcinfo, 1, 1, do_smcinfo,
+ "print SMC registers",
+ ""
+);
+
+U_BOOT_CMD(
+ spiinfo, 1, 1, do_spiinfo,
+ "print Serial Peripheral Interface (SPI) registers",
+ ""
+);
+
+U_BOOT_CMD(
+ muxinfo, 1, 1, do_muxinfo,
+ "print CPM Multiplexing registers",
+ ""
+);
+
+U_BOOT_CMD(
+ siinfo, 1, 1, do_siinfo,
+ "print Serial Interface (SI) registers",
+ ""
+);
+
+U_BOOT_CMD(
+ mccinfo, 1, 1, do_mccinfo,
+ "print MCC registers",
+ ""
+);
+
+#endif
--- /dev/null
+if TARGET_ADP_AE3XX
+
+config SYS_CPU
+ default "n1213"
+
+config SYS_BOARD
+ default "adp-ae3xx"
+
+config SYS_VENDOR
+ default "AndesTech"
+
+config SYS_SOC
+ default "ae3xx"
+
+config SYS_CONFIG_NAME
+ default "adp-ae3xx"
+
+endif
--- /dev/null
+ADP-AG101P BOARD
+M: Andes <uboot@andestech.com>
+S: Maintained
+F: board/AndesTech/adp-ae3xx/
+F: include/configs/adp-ae3xx.h
+F: configs/adp-ae3xx_defconfig
--- /dev/null
+#
+# Copyright (C) 2016 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := adp-ae3xx.o
--- /dev/null
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#if defined(CONFIG_FTMAC100)
+#include <netdev.h>
+#endif
+#include <linux/io.h>
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int board_init(void)
+{
+ /*
+ * refer to BOOT_PARAMETER_PA_BASE within
+ * "linux/arch/nds32/include/asm/misc_spec.h"
+ */
+ printf("Board: %s\n" , CONFIG_SYS_BOARD);
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAE3XX;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+ unsigned long actual_size;
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+ gd->ram_size = actual_size;
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#if defined(CONFIG_FTMAC100)
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_DM_MMC
+#ifdef CONFIG_FTSDC010
+ ftsdc010_mmc_init(0);
+#endif
+#endif
+ return 0;
+}
*/
#include <common.h>
+#if defined(CONFIG_FTMAC100)
#include <netdev.h>
-#include <asm/io.h>
+#endif
+#include <linux/io.h>
#include <faraday/ftsdc010.h>
#include <faraday/ftsmc020.h>
* refer to BOOT_PARAMETER_PA_BASE within
* "linux/arch/nds32/include/asm/misc_spec.h"
*/
+ printf("Board: %s\n" , CONFIG_SYS_BOARD);
gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
return 0;
}
+#if defined(CONFIG_FTMAC100)
int board_eth_init(bd_t *bd)
{
return ftmac100_initialize(bd);
}
+#endif
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
int board_mmc_init(bd_t *bis)
{
+#ifdef CONFIG_FTSDC010
ftsdc010_mmc_init(0);
+#endif
return 0;
}
config CHAIN_OF_TRUST
depends on !FIT_SIGNATURE && SECURE_BOOT
imply CMD_BLOB
+ imply CMD_HASH if ARM
select FSL_CAAM
+ select SPL_BOARD_INIT if (ARM && SPL)
+ select SHA_HW_ACCEL
+ select SHA_PROG_HW_ACCEL
bool
default y
+
+config CMD_ESBC_VALIDATE
+ bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
+ default y if CHAIN_OF_TRUST
+ help
+ This option enables two commands used for secure booting:
+
+ esbc_validate - validate signature using RSA verification
+ esbc_halt - put the core in spin loop (Secure Boot Only)
return (0);
}
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#include <ata.h>
int ide_preinit(void)
{
setbits_8(&ata->cr, 0x01);
}
}
-#endif /* CONFIG_CMD_IDE */
+#endif /* CONFIG_IDE */
#ifdef CONFIG_DRIVER_DM9000
return (0);
}
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#include <ata.h>
int ide_preinit(void)
{
setbits_8(&ata->cr, 0x01);
}
}
-#endif /* CONFIG_CMD_IDE */
+#endif /* CONFIG_IDE */
return (0);
}
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_IDE)
#include <ata.h>
int ide_preinit(void)
config SYS_CONFIG_NAME
default "gw_ventana"
+config CMD_EECONFIG
+ bool "Enable the 'econfig' command"
+ help
+ Provides access to EEPROM configuration on Gateworks Ventana
+
+config CMD_GSC
+ bool "Enable the 'gsc' command"
+ help
+ Provides access to the GSC configuration:
+
+ gsc sleep - sleeps for a period of seconds
+ gsc wd - enables / disables the watchdog
+
endif
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
-#include <dtt.h>
#include "405ep.h"
#include <gdsys_fpga.h>
int misc_init_r(void)
{
- /* startup fans */
- dtt_init();
+ /*
+ * Note: DTT has been removed. Please use UCLASS_THERMAL.
+ *
+ * startup fans
+ *
+ * dtt_init();
+ */
return 0;
}
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
-#include <dtt.h>
#include <miiphy.h>
#include "405ep.h"
int misc_init_r(void)
{
- /* startup fans */
- dtt_init();
+ /*
+ * Note: DTT has been removed. Please use UCLASS_THERMAL.
+ *
+ * startup fans
+ *
+ * dtt_init();
+ */
return 0;
}
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
-#include <dtt.h>
#include "405ep.h"
#include <gdsys_fpga.h>
int misc_init_r(void)
{
- /* startup fans */
- dtt_init();
+ /*
+ * Note: DTT has been removed. Please use UCLASS_THERMAL.
+ *
+ * startup fans
+ *
+ * dtt_init();
+ */
return 0;
}
#include <miiphy.h>
#include <i2c.h>
-#include <dtt.h>
DECLARE_GLOBAL_DATA_PTR;
*/
int misc_init_r(void)
{
- /* startup fans */
- dtt_init();
+ /*
+ * Note: DTT has been removed. Please use UCLASS_THERMAL.
+ *
+ * startup fans
+ *
+ * dtt_init();
+ */
#ifdef CONFIG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
default "strider"
endif
+
+config CMD_IOLOOP
+ bool "Enable 'ioloop' and 'ioreflect' commands"
+ help
+ These commands provide FPGA tests.
}
#endif
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#ifdef CONFIG_IDE_RESET
setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
}
#endif /* CONFIG_IDE_RESET */
-#endif /* CONFIG_CMD_IDE */
+#endif /* CONFIG_IDE */
#ifdef CONFIG_OF_BOARD_SETUP
static void ft_delete_node(void *fdt, const char *compat)
}
#endif
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
void init_ide_reset (void)
{
}
#endif /* CONFIG_OF_BOARD_SETUP */
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
#define GPIO_PSC2_4 0x02000000UL
} else
setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
}
-#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
+#endif /* defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) */
F: include/configs/sun9i.h
F: configs/Merrii_A80_Optimus_defconfig
F: include/configs/sun50i.h
-F: configs/pine64_plus_defconfig
A20-OLIMEX-SOM-EVB BOARD
M: Marcus Cooper <codekipper@gmail.com>
S: Maintained
F: configs/orangepi_pc2_defconfig
+PINE64 BOARDS
+M: Andre Przywara <andre.przywara@arm.com>
+S: Maintained
+F: configs/pine64_plus_defconfig
+
R16 EVB PARROT BOARD
M: Quentin Schulz <quentin.schulz@free-electrons.com>
S: Maintained
+++ /dev/null
-Pine64 board README
-====================
-
-The Pine64(+) is a single board computer equipped with an AArch64 capable ARMv8
-compliant Allwinner A64 SoC.
-This chip has ARM Cortex A-53 cores and thus can run both in AArch32
-(compatible to 32-bit ARMv7) and AArch64 modes. Upon reset the SoC starts
-in AArch32 mode and executes 32-bit code from the Boot ROM (BROM).
-This has some implications on U-Boot.
-
-Quick start
-============
-- Get hold of a boot0.img file (see below for more details).
-- Get the boot0img tool source from the tools directory in [1] and compile
- that on your host.
-- Build U-Boot:
-$ export CROSS_COMPILE=aarch64-linux-gnu-
-$ make pine64_plus_defconfig
-$ make
-- You also need a compiled ARM Trusted Firmware (ATF) binary. Checkout the
- "allwinner" branch from the github repository [2] and build it:
-$ export CROSS_COMPILE=aarch64-linux-gnu-
-$ make PLAT=sun50iw1p1 DEBUG=1 bl31
- The resulting binary is build/sun50iw1p1/debug/bl31.bin.
-
-Now put an empty (or disposable) micro SD card in your card reader and learn
-its device file name, replacing /dev/sd<x> below with the result (that could
-be /dev/mmcblk<x> as well):
-
-$ ./boot0img --device /dev/sd<x> -e -u u-boot.bin -B boot0.img \
- -d trampoline64:0x44000 -s bl31.bin -a 0x44008 -p 100
-(either copying the respective files to the working directory or specifying
-the paths directly)
-
-This will create a new partition table (with a 100 MB FAT boot partition),
-copies boot0.img, ATF and U-Boot to the proper locations on the SD card and
-will fill in the magic Allwinner header to be recognized by boot0.
-Prefix the above call with "sudo" if you don't have write access to the
-uSD card. You can also use "-o output.img" instead of "--device /dev/sd<x>"
-to create an image file and "dd" that to the uSD card.
-Omitting the "-p" option will skip the partition table.
-
-Now put this uSD card in the board and power it on. You should be greeted by
-the U-Boot prompt.
-
-
-Main U-Boot
-============
-The main U-Boot proper is a real 64-bit ARMv8 port and runs entirely in the
-64-bit AArch64 mode. It can load any AArch64 code, EFI applications or arm64
-Linux kernel images (often named "Image") using the booti command.
-Launching 32-bit code and kernels is technically possible, though not without
-drawbacks (or hacks to avoid them) and currently not implemented.
-
-SPL support
-============
-The main task of the SPL support is to bring up the DRAM controller and make
-DRAM actually accessible. At the moment there is no documentation or source
-code available which would do this.
-There are currently two ways to overcome this situation: using a tainted 32-bit
-SPL (involving some hacks and resulting in a non-redistributable binary, thus
-not described here) or using the Allwinner boot0 blob.
-
-boot0 method
--------------
-boot0 is Allwiner's secondary program loader and it can be used as some kind
-of SPL replacement to get U-Boot up and running.
-The binary is a 32 KByte blob and contained on every Pine64 image distributed
-so far. It can be easily extracted from a micro SD card or an image file:
-# dd if=/dev/sd<x> of=boot0.bin bs=8k skip=1 count=4
-where /dev/sd<x> is the device name of the uSD card or the name of the image
-file. Apparently Allwinner allows re-distribution of this proprietary code
-as-is.
-For the time being this boot0 blob is the only redistributable way of making
-U-Boot work on the Pine64. Beside loading the various parts of the (original)
-firmware it also switches the core into AArch64 mode.
-The original boot0 code looks for U-Boot at a certain place on an uSD card
-(at 19096 KB), also it expects a header with magic bytes and a checksum.
-There is a tool called boot0img[1] which takes a boot0.bin image and a compiled
-U-Boot binary (plus other binaries) and will populate that header accordingly.
-To make space for the magic header, the pine64_plus_defconfig will make sure
-there is sufficient space at the beginning of the U-Boot binary.
-boot0img will also take care of putting the different binaries at the right
-places on the uSD card and works around unused, but mandatory parts by using
-trampoline code. See the output of "boot0img -h" for more information.
-boot0img can also patch boot0 to avoid loading U-Boot from 19MB, instead
-fetching it from just behind the boot0 binary (-B option).
-
-FEL boot
-=========
-FEL is the name of the Allwinner defined USB boot protocol built-in the
-mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely
-by using the USB-OTG interface and a host port on another computer.
-Since FEL boot does not work with boot0, it requires the libdram hack, which
-is not described here.
-
-[1] https://github.com/apritzel/pine64/
-[2] https://github.com/apritzel/arm-trusted-firmware.git
--- /dev/null
+Allwinner 64-bit boards README
+==============================
+
+Newer Allwinner SoCs feature ARMv8 cores (ARM Cortex-A53) with support for
+both the 64-bit AArch64 mode and the ARMv7 compatible 32-bit AArch32 mode.
+Examples are the Allwinner A64 (used for instance on the Pine64 board) or
+the Allwinner H5 SoC (as used on the OrangePi PC 2).
+These SoCs are wired to start in AArch32 mode on reset and execute 32-bit
+code from the Boot ROM (BROM). As this has some implications on U-Boot, this
+file describes how to make full use of the 64-bit capabilities.
+
+Quick Start / Overview
+======================
+- Build the ARM Trusted Firmware binary (see "ARM Trusted Firmware (ATF)" below)
+- Build U-Boot (see "SPL/U-Boot" below)
+- Transfer to an uSD card (see "microSD card" below)
+- Boot and enjoy!
+
+Building the firmware
+=====================
+
+The Allwinner A64/H5 firmware consists of three parts: U-Boot's SPL, an
+ARM Trusted Firmware (ATF) build and the U-Boot proper.
+The SPL will load both ATF and U-Boot proper along with the right device
+tree blob (.dtb) and will pass execution to ATF (in EL3), which in turn will
+drop into the U-Boot proper (in EL2).
+As the ATF binary will become part of the U-Boot image file, you will need
+to build it first.
+
+ ARM Trusted Firmware (ATF)
+----------------------------
+Checkout the "allwinner" branch from the github repository [1] and build it:
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make PLAT=sun50iw1p1 DEBUG=1 bl31
+The resulting binary is build/sun50iw1p1/debug/bl31.bin. Either put the
+location of this file into the BL31 environment variable or copy this to
+the root of your U-Boot build directory (or create a symbolic link).
+$ export BL31=/src/arm-trusted-firmware/build/sun50iw1p1/debug/bl31.bin
+ (adjust the actual path accordingly)
+
+ SPL/U-Boot
+------------
+Both U-Boot proper and the SPL are using the 64-bit mode. As the boot ROM
+enters the SPL still in AArch32 secure SVC mode, there is some shim code to
+enter AArch64 very early. The rest of the SPL runs in AArch64 EL3.
+U-Boot proper runs in EL2 and can load any AArch64 code (using the "go"
+command), EFI applications (with "bootefi") or arm64 Linux kernel images
+(often named "Image"), using the "booti" command.
+
+$ make clean
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make pine64_plus_defconfig
+$ make
+
+This will build the SPL in spl/sunxi-spl.bin and a FIT image called u-boot.itb,
+which contains the rest of the firmware.
+
+
+Boot process
+============
+The on-die BROM code will try several methods to load and execute the firmware.
+On a typical board like the Pine64 this will result in the following boot order:
+
+1) Reading 32KB from sector 16 (@8K) of the microSD card to SRAM A1. If the
+BROM finds the magic "eGON" header in the first bytes, it will execute that
+code. If not (no SD card at all or invalid magic), it will:
+2) Try to read 32KB from sector 16 (@8K) of memory connected to the MMC2
+controller, typically an on-board eMMC chip. If there is no eMMC or it does
+not contain a valid boot header, it will:
+3) Initialize the SPI0 controller and try to access a NOR flash connected to
+it (using the CS0 pin). If a flash chip is found, the BROM will load the
+first 32KB (from offset 0) into SRAM A1. Now it checks for the magic eGON
+header and checksum and will execute the code upon finding it. If not, it will:
+4) Initialize the USB OTG controller and will wait for a host to connect to
+it, speaking the Allwinner proprietary (but deciphered) "FEL" USB protocol.
+
+
+To boot the Pine64 board, you can use U-Boot and any of the described methods.
+
+FEL boot (USB OTG)
+------------------
+FEL is the name of the Allwinner defined USB boot protocol built in the
+mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely
+by using the USB-OTG interface and a host port on another computer.
+As the FEL mode is controlled by the boot ROM, it expects to be running in
+AArch32. For now the AArch64 SPL cannot properly return into FEL mode, so the
+feature is disabled in the configuration at the moment.
+
+microSD card
+------------
+Transfer the SPL and the U-Boot FIT image directly to an uSD card:
+# dd if=spl/sunxi-spl.bin of=/dev/sdx bs=8k seek=1
+# dd if=u-boot.itb of=/dev/sdx bs=8k seek=5
+# sync
+(replace /dev/sdx with you SD card device file name, which could be
+/dev/mmcblk[x] as well).
+
+Alternatively you can concatenate the SPL and the U-Boot FIT image into a
+single file and transfer that instead:
+$ cat spl/sunxi-spl.bin u-boot.itb > u-boot-sunxi-with-spl.bin
+# dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1
+
+You can partition the microSD card, but leave the first MB unallocated (most
+partitioning tools will do this anyway).
+
+NOR flash
+---------
+Some boards (like the SoPine, Pinebook or the OrangePi PC2) come with a
+soldered SPI NOR flash chip. On other boards like the Pine64 such a chip
+can be connected to the SPI0/CS0 pins on the PI-2 headers.
+Create the SPL and FIT image like described above for the SD card.
+Now connect either an "A to A" USB cable to the upper USB port on the Pine64
+or get an adaptor and use a regular A-microB cable connected to it. Other
+boards often have a proper micro-B USB socket connected to the USB OTB port.
+Remove a microSD card from the slot and power on the board.
+On your host computer download and build the sunxi-tools package[2], then
+use "sunxi-fel" to access the board:
+$ ./sunxi-fel ver -v -p
+This should give you an output starting with: AWUSBFEX soc=00001689(A64) ...
+Now use the sunxi-fel tool to write to the NOR flash:
+$ ./sunxi-fel spiflash-write 0 spl/sunxi-spl.bin
+$ ./sunxi-fel spiflash-write 32768 u-boot.itb
+Now boot the board without an SD card inserted and you should see the
+U-Boot prompt on the serial console.
+
+(Legacy) boot0 method
+---------------------
+boot0 is Allwiner's secondary program loader and it can be used as some kind
+of SPL replacement to get U-Boot up and running from an microSD card.
+For some time using boot0 was the only option to get the Pine64 booted.
+With working DRAM init code in U-Boot's SPL this is no longer necessary,
+but this method is described here for the sake of completeness.
+Please note that this method works only with the boot0 files shipped with
+A64 based boards, the H5 uses an incompatible layout which is not supported
+by this method.
+
+The boot0 binary is a 32 KByte blob and contained in the official Pine64 images
+distributed by Pine64 or Allwinner. It can be easily extracted from a micro
+SD card or an image file:
+# dd if=/dev/sd<x> of=boot0.bin bs=8k skip=1 count=4
+where /dev/sd<x> is the device name of the uSD card or the name of the image
+file. Apparently Allwinner allows re-distribution of this proprietary code
+"as-is".
+This boot0 blob takes care of DRAM initialisation and loads the remaining
+firmware parts, then switches the core into AArch64 mode.
+The original boot0 code looks for U-Boot at a certain place on an uSD card
+(at 19096 KB), also it expects a header with magic bytes and a checksum.
+There is a tool called boot0img[3] which takes a boot0.bin image and a compiled
+U-Boot binary (plus other binaries) and will populate that header accordingly.
+To make space for the magic header, the pine64_plus_defconfig will make sure
+there is sufficient space at the beginning of the U-Boot binary.
+boot0img will also take care of putting the different binaries at the right
+places on the uSD card and works around unused, but mandatory parts by using
+trampoline code. See the output of "boot0img -h" for more information.
+boot0img can also patch boot0 to avoid loading U-Boot from 19MB, instead
+fetching it from just behind the boot0 binary (-B option).
+$ ./boot0img -o firmware.img -B boot0.img -u u-boot-dtb.bin -e -s bl31.bin \
+-a 0x44008 -d trampoline64:0x44000
+Then write this image to a microSD card, replacing /dev/sdx with the right
+device file (see above):
+$ dd if=firmware.img of=/dev/sdx bs=8k seek=1
+
+[1] https://github.com/apritzel/arm-trusted-firmware.git
+[2] git://github.com/linux-sunxi/sunxi-tools.git
+[3] https://github.com/apritzel/pine64/
void sunxi_board_init(void)
{
int power_failed = 0;
- unsigned long ramsize;
#ifdef CONFIG_SY8106A_POWER
power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
#endif
#endif
printf("DRAM:");
- ramsize = sunxi_dram_init();
- printf(" %d MiB\n", (int)(ramsize >> 20));
- if (!ramsize)
+ gd->ram_size = sunxi_dram_init();
+ printf(" %d MiB\n", (int)(gd->ram_size >> 20));
+ if (!gd->ram_size)
hang();
/*
#endif
return 0;
}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
+ const char *cmp_str = (void *)(ulong)SPL_ADDR;
+
+ /* Check if there is a DT name stored in the SPL header and use that. */
+ if (spl->dt_name_offset) {
+ cmp_str += spl->dt_name_offset;
+ } else {
+#ifdef CONFIG_DEFAULT_DEVICE_TREE
+ cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
+#else
+ return 0;
+#endif
+ };
+
+/* Differentiate the two Pine64 board DTs by their DRAM size. */
+ if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
+ if ((gd->ram_size > 512 * 1024 * 1024))
+ return !strstr(name, "plus");
+ else
+ return !!strstr(name, "plus");
+ } else {
+ return strcmp(name, cmp_str);
+ }
+}
+#endif
--- /dev/null
+#!/bin/sh
+#
+# script to generate FIT image source for 64-bit sunxi boards with
+# ARM Trusted Firmware and multiple device trees (given on the command line)
+#
+# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+
+[ -z "$BL31" ] && BL31="bl31.bin"
+
+if [ ! -f $BL31 ]; then
+ echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2
+ echo "Please read the section on ARM Trusted Firmware (ATF) in board/sunxi/README.sunxi64" >&2
+ BL31=/dev/null
+fi
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+
+ images {
+ uboot@1 {
+ description = "U-Boot (64-bit)";
+ data = /incbin/("u-boot-nodtb.bin");
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <0x4a000000>;
+ };
+ atf@1 {
+ description = "ARM Trusted Firmware";
+ data = /incbin/("$BL31");
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x44000>;
+ entry = <0x44000>;
+ };
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+ cat << __FDT_IMAGE_EOF
+ fdt@$cnt {
+ description = "$(basename $dtname .dtb)";
+ data = /incbin/("$dtname");
+ type = "flat_dt";
+ compression = "none";
+ };
+__FDT_IMAGE_EOF
+ cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+ };
+ configurations {
+ default = "config@1";
+
+__CONF_HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+ cat << __CONF_SECTION_EOF
+ config@$cnt {
+ description = "$(basename $dtname .dtb)";
+ firmware = "uboot@1";
+ loadables = "atf@1";
+ fdt = "fdt@$cnt";
+ };
+__CONF_SECTION_EOF
+ cnt=$((cnt+1))
+done
+
+cat << __ITS_EOF
+ };
+};
+__ITS_EOF
imply CMD_BOOTZ
imply CMD_DFU if USB_GADGET_DOWNLOAD
imply CMD_DHCP
+ imply CMD_EEPROM
imply CMD_EXT2
imply CMD_EXT4
imply CMD_EXT4_WRITE
}
#endif
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
#if defined (CONFIG_MINIFAP)
#define SM501_POWER_MODE0_GATE 0x00000040UL
return 0;
}
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
void init_ide_reset(void)
{
debug("init_ide_reset\n");
config SYS_CONFIG_NAME
default "work_92105"
+config CMD_HD44760
+ bool "Enable 'hd44780' LCD-control comand"
+ help
+ This controls the LCD driver.
+
endif
"HD44780 LCD driver control",
hd44780_help_text
);
-#endif /* CONFIG_CMD_HD44780 */
+#endif /* CONFIG_CMD_HD44760 */
Check if a variable is defined in the environment for use in
shell scripting.
+config CMD_ENV_CALLBACK
+ bool "env callbacks - print callbacks and their associated variables"
+ help
+ Some environment variable have callbacks defined by
+ U_BOOT_ENV_CALLBACK. These are called when the variable changes.
+ For example changing "baudrate" adjust the serial baud rate. This
+ command lists the currently defined callbacks.
+
+config CMD_ENV_FLAGS
+ bool "env flags -print variables that have non-default flags"
+ help
+ Some environment variables have special flags that control their
+ behaviour. For example, serial# can only be written once and cannot
+ be deleted. This command shows the variables that have special
+ flags.
+
endmenu
menu "Memory commands"
config CMD_CRC32
bool "crc32"
+ select HASH
default y
help
Compute CRC32.
+config CMD_EEPROM
+ bool "eeprom - EEPROM subsystem"
+ help
+ (deprecated, needs conversion to driver model)
+ Provides commands to read and write EEPROM (Electrically Erasable
+ Programmable Read Only Memory) chips that are connected over an
+ I2C bus.
+
+config CMD_EEPROM_LAYOUT
+ bool "Enable layout-aware eeprom commands"
+ depends on CMD_EEPROM
+ help
+ (deprecated, needs conversion to driver model)
+ When enabled, additional eeprom sub-commands become available.
+
+ eeprom print - prints the contents of the eeprom in a human-readable
+ way (eeprom layout fields, and data formatted to be fit for human
+ consumption).
+
+ eeprom update - allows user to update eeprom fields by specifying
+ the field name, and providing the new data in a human readable format
+ (same format as displayed by the eeprom print command).
+
+ Both commands can either auto detect the layout, or be told which
+ layout to use.
+
+ Feature API:
+ __weak int parse_layout_version(char *str)
+ - override to provide your own layout name parsing
+ __weak void __eeprom_layout_assign(struct eeprom_layout *layout,
+ int layout_version);
+ - override to setup the layout metadata based on the version
+ __weak int eeprom_layout_detect(unsigned char *data)
+ - override to provide your own algorithm for detecting layout
+ version
+ eeprom_field.c
+ - contains various printing and updating functions for common
+ types of eeprom fields. Can be used for defining
+ custom layouts.
+
+config EEPROM_LAYOUT_HELP_STRING
+ string "Tells user what layout names are supported"
+ depends on CMD_EEPROM_LAYOUT
+ default "<not defined>"
+ help
+ Help printed with the LAYOUT VERSIONS part of the 'eeprom'
+ command's help.
+
config CMD_MD5SUM
bool "md5sum"
default n
help
Display memory information.
+endmenu
+
+menu "Compression commands"
+
+config CMD_LZMADEC
+ bool "lzmadec"
+ select LZMA
+ help
+ Support decompressing an LZMA (Lempel-Ziv-Markov chain algorithm)
+ image from memory.
+
config CMD_UNZIP
bool "unzip"
help
option is to use sandbox and pass the -d point to sandbox's
u-boot.dtb file.
+config CMD_IDE
+ bool "ide - Support for IDE drivers"
+ select IDE
+ help
+ Provides an 'ide' command which allows accessing the IDE drive,
+ reseting the IDE interface, printing the partition table and
+ geting device info. It also enables the 'diskboot' command which
+ permits booting from an IDE drive.
+
+config CMD_IO
+ bool "io - Support for performing I/O accesses"
+ help
+ Provides an 'iod' command to display I/O space and an 'iow' command
+ to write values to the I/O space. This can be useful for manually
+ checking the state of devices during boot when debugging device
+ drivers, etc.
+
+config CMD_IOTRACE
+ bool "iotrace - Support for tracing I/O activity"
+ help
+ Provides an 'iotrace' command which supports recording I/O reads and
+ writes in a trace buffer in memory . It also maintains a checksum
+ of the trace records (even if space is exhausted) so that the
+ sequence of I/O accesses can be verified.
+
+ When debugging drivers it is useful to see what I/O accesses were
+ done and in what order.
+
+ Even if the individual accesses are of little interest it can be
+ useful to verify that the access pattern is consistent each time
+ an operation is performed. In this case a checksum can be used to
+ characterise the operation of a driver. The checksum can be compared
+ across different runs of the operation to verify that the driver is
+ working properly.
+
+ In particular, when performing major refactoring of the driver, where
+ the access pattern should not change, the checksum provides assurance
+ that the refactoring work has not broken the driver.
+
+ This works by sneaking into the io.h heder for an architecture and
+ redirecting I/O accesses through iotrace's tracing mechanism.
+
+ For now no commands are provided to examine the trace buffer. The
+ format is fairly simple, so 'md' is a reasonable substitute.
+
+ Note: The checksum feature is only useful for I/O regions where the
+ contents do not change outside of software control. Where this is not
+ suitable you can fall back to manually comparing the addresses. It
+ might be useful to enhance tracing to only checksum the accesses and
+ not the data read/written.
+
config CMD_LOADB
bool "loadb"
default y
help
FPGA support.
+config CMD_FPGA_LOADBP
+ bool "fpga loadbp - load partial bitstream (Xilinx only)"
+ depends on CMD_FPGA
+ help
+ Supports loading an FPGA device from a bitstream buffer containing
+ a partial bitstream.
+
+config CMD_FPGA_LOADFS
+ bool "fpga loadfs - load bitstream from FAT filesystem (Xilinx only)"
+ depends on CMD_FPGA
+ help
+ Supports loading an FPGA device from a FAT filesystem.
+
+config CMD_FPGA_LOADMK
+ bool "fpga loadmk - load bitstream from image"
+ depends on CMD_FPGA
+ help
+ Supports loading an FPGA device from a image generated by mkimage.
+
+config CMD_FPGA_LOADP
+ bool "fpga loadp - load partial bitstream"
+ depends on CMD_FPGA
+ help
+ Supports loading an FPGA device from a bitstream buffer containing
+ a partial bitstream.
+
+config CMD_FPGAD
+ bool "fpgad - dump FPGA registers"
+ help
+ (legacy, needs conversion to driver model)
+ Provides a way to dump FPGA registers by calling the board-specific
+ fpga_get_reg() function. This functions similarly to the 'md'
+ command.
+
+config CMD_FUSE
+ bool "fuse - support for the fuse subssystem"
+ help
+ (deprecated - needs conversion to driver model)
+ This allows reading, sensing, programming or overriding fuses
+ which control the behaviour of the device. The command uses the
+ fuse_...() API.
+
config CMD_REMOTEPROC
bool "remoteproc"
depends on REMOTEPROC
help
GPIO support.
+config CMD_FDC
+ bool "fdcboot - Boot from floppy device"
+ help
+ The 'fdtboot' command allows booting an image from a floppy disk.
+
endmenu
help
Acquire a network IP address using the link-local protocol
+config CMD_ETHSW
+ bool "ethsw"
+ help
+ Allow control of L2 Ethernet switch commands. These are supported
+ by the vsc9953 Ethernet driver at present. Sub-commands allow
+ operations such as enabling / disabling a port and
+ viewing/maintaining the filtering database (FDB)
+
endmenu
menu "Misc commands"
help
Run commands and summarize execution time.
+config CMD_GETTIME
+ bool "gettime - read elapsed time"
+ help
+ Enable the 'gettime' command which reads the elapsed time since
+ U-Boot started running. This shows the time in seconds and
+ milliseconds. See also the 'bootstage' command which provides more
+ flexibility for boot timing.
+
# TODO: rename to CMD_SLEEP
config CMD_MISC
bool "sleep"
generation/use as key for cryptographic operation. Key
modifier should be 16 byte long.
+config CMD_HASH
+ bool "Support 'hash' command"
+ select HASH
+ help
+ This provides a way to hash data in memory using various supported
+ algorithms (such as SHA1, MD5, CRC32). The computed digest can be
+ saved to memory or to an environment variable. It is also possible
+ to verify a hash against data in memory.
+
config CMD_TPM
bool "Enable the 'tpm' command"
depends on TPM
help
Enables fsuuid command for filesystem UUID.
+config CMD_JFFS2
+ bool "jffs2 command"
+ select FS_JFFS2
+ help
+ Enables commands to support the JFFS2 (Journalling Flash File System
+ version 2) filesystem. This enables fsload, ls and fsinfo which
+ provide the ability to load files, list directories and obtain
+ filesystem information.
+
config CMD_MTDPARTS
depends on ARCH_SUNXI
bool "MTD partition support"
available tests and running either all the tests, or specific tests
identified by name.
+config CMD_IRQ
+ bool "irq - Show information about interrupts"
+ depends on !ARM && !MIPS && !SH && !MPC512X
+ help
+ This enables two commands:
+
+ interrupts - enable or disable interrupts
+ irqinfo - print device-specific interrupt information
+
+config CMD_KGDB
+ bool "kgdb - Allow debugging of U-Boot with gdb"
+ help
+ This enables a 'kgdb' command which allows gdb to connect to U-Boot
+ over a serial link for debugging purposes. This allows
+ single-stepping, inspecting variables, etc. This is supported only
+ on PowerPC at present.
+
endmenu
config CMD_UBI
obj-$(CONFIG_CMD_DIAG) += diag.o
endif
obj-$(CONFIG_CMD_DISPLAY) += display.o
-obj-$(CONFIG_CMD_DTT) += dtt.o
obj-$(CONFIG_CMD_ECHO) += echo.o
obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
obj-$(CONFIG_CMD_EEPROM) += eeprom.o
obj-$(CONFIG_CMD_IOTRACE) += iotrace.o
obj-$(CONFIG_CMD_HASH) += hash.o
obj-$(CONFIG_CMD_IDE) += ide.o disk.o
-obj-$(CONFIG_CMD_IMMAP) += immap.o
obj-$(CONFIG_CMD_INI) += ini.o
obj-$(CONFIG_CMD_IRQ) += irq.o
obj-$(CONFIG_CMD_ITEST) += itest.o
obj-$(CONFIG_CMD_UBIFS) += ubifs.o
obj-$(CONFIG_CMD_UNIVERSE) += universe.o
obj-$(CONFIG_CMD_UNZIP) += unzip.o
-ifdef CONFIG_LZMA
obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o
-endif
obj-$(CONFIG_CMD_USB) += usb.o disk.o
obj-$(CONFIG_CMD_FASTBOOT) += fastboot.o
# define OFFSET_ADJUSTMENT (flash_info[id.num].start[0])
#endif
-#ifndef CONFIG_CMD_JFFS2
+#ifndef CONFIG_FS_JFFS2
#include <linux/stat.h>
char *mkmodestr(unsigned long mode, char *str)
{
str[10] = '\0';
return str;
}
-#endif /* CONFIG_CMD_JFFS2 */
+#endif /* CONFIG_FS_JFFS2 */
extern int cramfs_check (struct part_info *info);
extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename);
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-
-#include <dtt.h>
-#include <i2c.h>
-#include <tmu.h>
-#include <linux/bug.h>
-
-#if defined CONFIG_DTT_SENSORS
-static unsigned long sensor_initialized;
-
-static void _initialize_dtt(void)
-{
- int i;
- unsigned char sensors[] = CONFIG_DTT_SENSORS;
-
- for (i = 0; i < sizeof(sensors); i++) {
- if ((sensor_initialized & (1 << i)) == 0) {
- if (dtt_init_one(sensors[i]) != 0) {
- printf("DTT%d: Failed init!\n", i);
- continue;
- }
- sensor_initialized |= (1 << i);
- }
- }
-}
-
-void dtt_init(void)
-{
- int old_bus;
-
- /* switch to correct I2C bus */
- old_bus = I2C_GET_BUS();
- I2C_SET_BUS(CONFIG_SYS_DTT_BUS_NUM);
-
- _initialize_dtt();
-
- /* switch back to original I2C bus */
- I2C_SET_BUS(old_bus);
-}
-#endif
-
-int dtt_i2c(void)
-{
-#if defined CONFIG_DTT_SENSORS
- int i;
- unsigned char sensors[] = CONFIG_DTT_SENSORS;
- int old_bus;
-
- /* Force a compilation error, if there are more then 32 sensors */
- BUILD_BUG_ON(sizeof(sensors) > 32);
- /* switch to correct I2C bus */
-#ifdef CONFIG_SYS_I2C
- old_bus = i2c_get_bus_num();
- i2c_set_bus_num(CONFIG_SYS_DTT_BUS_NUM);
-#else
- old_bus = I2C_GET_BUS();
- I2C_SET_BUS(CONFIG_SYS_DTT_BUS_NUM);
-#endif
-
- _initialize_dtt();
-
- /*
- * Loop through sensors, read
- * temperature, and output it.
- */
- for (i = 0; i < sizeof(sensors); i++)
- printf("DTT%d: %i C\n", i + 1, dtt_get_temp(sensors[i]));
-
- /* switch back to original I2C bus */
-#ifdef CONFIG_SYS_I2C
- i2c_set_bus_num(old_bus);
-#else
- I2C_SET_BUS(old_bus);
-#endif
-#endif
-
- return 0;
-}
-
-int dtt_tmu(void)
-{
-#if defined CONFIG_TMU_CMD_DTT
- int cur_temp;
-
- /* Sense and return latest thermal info */
- if (tmu_monitor(&cur_temp) == TMU_STATUS_INIT) {
- puts("TMU is in unknown state, temperature is invalid\n");
- return -1;
- }
- printf("Current temperature: %u degrees Celsius\n", cur_temp);
-#endif
- return 0;
-}
-
-int do_dtt(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- int err = 0;
-
- err |= dtt_i2c();
- err |= dtt_tmu();
-
- return err;
-} /* do_dtt() */
-
-/***************************************************/
-
-U_BOOT_CMD(
- dtt, 1, 1, do_dtt,
- "Read temperature from Digital Thermometer and Thermostat",
- ""
-);
static unsigned char eeprom_buf[CONFIG_SYS_EEPROM_SIZE];
-#ifndef CONFIG_EEPROM_LAYOUT_HELP_STRING
-#define CONFIG_EEPROM_LAYOUT_HELP_STRING "<not defined>"
-#endif
-
#endif
enum eeprom_action {
#define MAX_LEVEL 32 /* how deeply nested we will go */
#define SCRATCHPAD 1024 /* bytes of scratchpad memory */
-#ifndef CONFIG_CMD_FDT_MAX_DUMP
-#define CONFIG_CMD_FDT_MAX_DUMP 64
-#endif
+#define CMD_FDT_MAX_DUMP 64
/*
* Global data (for the gd->bd)
}
if ((len %4) == 0) {
- if (len > CONFIG_CMD_FDT_MAX_DUMP)
+ if (len > CMD_FDT_MAX_DUMP)
printf("* 0x%p [0x%08x]", data, len);
else {
const __be32 *p;
printf(">");
}
} else { /* anything else... hexdump */
- if (len > CONFIG_CMD_FDT_MAX_DUMP)
+ if (len > CMD_FDT_MAX_DUMP)
printf("* 0x%p [0x%08x]", data, len);
else {
const u8 *s;
+++ /dev/null
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * MPC8xx/MPC8260 Internal Memory Map Functions
- */
-
-#include <common.h>
-#include <command.h>
-
-#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
-
-#if defined(CONFIG_8xx)
-#include <asm/8xx_immap.h>
-#include <commproc.h>
-#include <asm/iopin_8xx.h>
-#elif defined(CONFIG_MPC8260)
-#include <asm/immap_8260.h>
-#include <asm/cpm_8260.h>
-#include <asm/iopin_8260.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void
-unimplemented ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf ("Sorry, but the '%s' command has not been implemented\n",
- cmdtp->name);
-}
-
-int
-do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-#if defined(CONFIG_8xx)
- volatile sysconf8xx_t *sc = &immap->im_siu_conf;
-#elif defined(CONFIG_MPC8260)
- volatile sysconf8260_t *sc = &immap->im_siu_conf;
-#endif
-
- printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr);
-#if defined(CONFIG_8xx)
- printf ("SWT = %08x\n", sc->sc_swt);
- printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask);
- printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec);
- printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr);
-#elif defined(CONFIG_MPC8260)
- printf ("BCR = %08x\n", sc->sc_bcr);
- printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n",
- sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl);
- printf ("L_ACR = %02x L_ALRH= %08x L_ALRL= %08x\n",
- sc->sc_lcl_acr, sc->sc_lcl_alrh, sc->sc_lcl_alrl);
- printf ("PTESR1= %08x PTESR2= %08x\n", sc->sc_tescr1, sc->sc_tescr2);
- printf ("LTESR1= %08x LTESR2= %08x\n", sc->sc_ltescr1, sc->sc_ltescr2);
- printf ("PDTEA = %08x PDTEM = %02x\n", sc->sc_pdtea, sc->sc_pdtem);
- printf ("LDTEA = %08x LDTEM = %02x\n", sc->sc_ldtea, sc->sc_ldtem);
-#endif
- return 0;
-}
-
-int
-do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-#if defined(CONFIG_8xx)
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- int nbanks = 8;
-#elif defined(CONFIG_MPC8260)
- volatile memctl8260_t *memctl = &immap->im_memctl;
- int nbanks = 12;
-#endif
- volatile uint *p = &memctl->memc_br0;
- int i;
-
- for (i = 0; i < nbanks; i++, p += 2) {
- if (i < 10) {
- printf ("BR%d = %08x OR%d = %08x\n",
- i, p[0], i, p[1]);
- } else {
- printf ("BR%d = %08x OR%d = %08x\n",
- i, p[0], i, p[1]);
- }
- }
-
- printf ("MAR = %08x", memctl->memc_mar);
-#if defined(CONFIG_8xx)
- printf (" MCR = %08x\n", memctl->memc_mcr);
-#elif defined(CONFIG_MPC8260)
- putc ('\n');
-#endif
- printf ("MAMR = %08x MBMR = %08x",
- memctl->memc_mamr, memctl->memc_mbmr);
-#if defined(CONFIG_8xx)
- printf ("\nMSTAT = %04x\n", memctl->memc_mstat);
-#elif defined(CONFIG_MPC8260)
- printf (" MCMR = %08x\n", memctl->memc_mcmr);
-#endif
- printf ("MPTPR = %04x MDR = %08x\n",
- memctl->memc_mptpr, memctl->memc_mdr);
-#if defined(CONFIG_MPC8260)
- printf ("PSDMR = %08x LSDMR = %08x\n",
- memctl->memc_psdmr, memctl->memc_lsdmr);
- printf ("PURT = %02x PSRT = %02x\n",
- memctl->memc_purt, memctl->memc_psrt);
- printf ("LURT = %02x LSRT = %02x\n",
- memctl->memc_lurt, memctl->memc_lsrt);
- printf ("IMMR = %08x\n", memctl->memc_immr);
-#endif
- return 0;
-}
-
-int
-do_sitinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unimplemented (cmdtp, flag, argc, argv);
- return 0;
-}
-
-#ifdef CONFIG_MPC8260
-int
-do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unimplemented (cmdtp, flag, argc, argv);
- return 0;
-}
-#endif
-
-int
-do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-#if defined(CONFIG_8xx)
- volatile car8xx_t *car = &immap->im_clkrst;
-#elif defined(CONFIG_MPC8260)
- volatile car8260_t *car = &immap->im_clkrst;
-#endif
-
-#if defined(CONFIG_8xx)
- printf ("SCCR = %08x\n", car->car_sccr);
- printf ("PLPRCR= %08x\n", car->car_plprcr);
- printf ("RSR = %08x\n", car->car_rsr);
-#elif defined(CONFIG_MPC8260)
- printf ("SCCR = %08x\n", car->car_sccr);
- printf ("SCMR = %08x\n", car->car_scmr);
- printf ("RSR = %08x\n", car->car_rsr);
- printf ("RMR = %08x\n", car->car_rmr);
-#endif
- return 0;
-}
-
-static int counter;
-
-static void
-header(void)
-{
- char *data = "\
- -------------------------------- --------------------------------\
- 00000000001111111111222222222233 00000000001111111111222222222233\
- 01234567890123456789012345678901 01234567890123456789012345678901\
- -------------------------------- --------------------------------\
- ";
- int i;
-
- if (counter % 2)
- putc('\n');
- counter = 0;
-
- for (i = 0; i < 4; i++, data += 79)
- printf("%.79s\n", data);
-}
-
-static void binary (char *label, uint value, int nbits)
-{
- uint mask = 1 << (nbits - 1);
- int i, second = (counter++ % 2);
-
- if (second)
- putc (' ');
- puts (label);
- for (i = 32 + 1; i != nbits; i--)
- putc (' ');
-
- while (mask != 0) {
- if (value & mask)
- putc ('1');
- else
- putc ('0');
- mask >>= 1;
- }
-
- if (second)
- putc ('\n');
-}
-
-#if defined(CONFIG_8xx)
-#define PA_NBITS 16
-#define PA_NB_ODR 8
-#define PB_NBITS 18
-#define PB_NB_ODR 16
-#define PC_NBITS 12
-#define PD_NBITS 13
-#elif defined(CONFIG_MPC8260)
-#define PA_NBITS 32
-#define PA_NB_ODR 32
-#define PB_NBITS 28
-#define PB_NB_ODR 28
-#define PC_NBITS 32
-#define PD_NBITS 28
-#endif
-
-int
-do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-#if defined(CONFIG_8xx)
- volatile iop8xx_t *iop = &immap->im_ioport;
- volatile ushort *l, *r;
-#elif defined(CONFIG_MPC8260)
- volatile iop8260_t *iop = &immap->im_ioport;
- volatile uint *l, *r;
-#endif
- volatile uint *R;
-
- counter = 0;
- header ();
-
- /*
- * Ports A & B
- */
-
-#if defined(CONFIG_8xx)
- l = &iop->iop_padir;
- R = &immap->im_cpm.cp_pbdir;
-#elif defined(CONFIG_MPC8260)
- l = &iop->iop_pdira;
- R = &iop->iop_pdirb;
-#endif
- binary ("PA_DIR", *l++, PA_NBITS);
- binary ("PB_DIR", *R++, PB_NBITS);
- binary ("PA_PAR", *l++, PA_NBITS);
- binary ("PB_PAR", *R++, PB_NBITS);
-#if defined(CONFIG_MPC8260)
- binary ("PA_SOR", *l++, PA_NBITS);
- binary ("PB_SOR", *R++, PB_NBITS);
-#endif
- binary ("PA_ODR", *l++, PA_NB_ODR);
- binary ("PB_ODR", *R++, PB_NB_ODR);
- binary ("PA_DAT", *l++, PA_NBITS);
- binary ("PB_DAT", *R++, PB_NBITS);
-
- header ();
-
- /*
- * Ports C & D
- */
-
-#if defined(CONFIG_8xx)
- l = &iop->iop_pcdir;
- r = &iop->iop_pddir;
-#elif defined(CONFIG_MPC8260)
- l = &iop->iop_pdirc;
- r = &iop->iop_pdird;
-#endif
- binary ("PC_DIR", *l++, PC_NBITS);
- binary ("PD_DIR", *r++, PD_NBITS);
- binary ("PC_PAR", *l++, PC_NBITS);
- binary ("PD_PAR", *r++, PD_NBITS);
-#if defined(CONFIG_8xx)
- binary ("PC_SO ", *l++, PC_NBITS);
- binary (" ", 0, 0);
- r++;
-#elif defined(CONFIG_MPC8260)
- binary ("PC_SOR", *l++, PC_NBITS);
- binary ("PD_SOR", *r++, PD_NBITS);
- binary ("PC_ODR", *l++, PC_NBITS);
- binary ("PD_ODR", *r++, PD_NBITS);
-#endif
- binary ("PC_DAT", *l++, PC_NBITS);
- binary ("PD_DAT", *r++, PD_NBITS);
-#if defined(CONFIG_8xx)
- binary ("PC_INT", *l++, PC_NBITS);
-#endif
-
- header ();
- return 0;
-}
-
-/*
- * set the io pins
- * this needs a clean up for smaller tighter code
- * use *uint and set the address based on cmd + port
- */
-int
-do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- uint rcode = 0;
- iopin_t iopin;
- static uint port = 0;
- static uint pin = 0;
- static uint value = 0;
- static enum {
- DIR,
- PAR,
- SOR,
- ODR,
- DAT,
-#if defined(CONFIG_8xx)
- INT
-#endif
- } cmd = DAT;
-
- if (argc != 5) {
- puts ("iopset PORT PIN CMD VALUE\n");
- return 1;
- }
- port = argv[1][0] - 'A';
- if (port > 3)
- port -= 0x20;
- if (port > 3)
- rcode = 1;
- pin = simple_strtol (argv[2], NULL, 10);
- if (pin > 31)
- rcode = 1;
-
-
- switch (argv[3][0]) {
- case 'd':
- if (argv[3][1] == 'a')
- cmd = DAT;
- else if (argv[3][1] == 'i')
- cmd = DIR;
- else
- rcode = 1;
- break;
- case 'p':
- cmd = PAR;
- break;
- case 'o':
- cmd = ODR;
- break;
- case 's':
- cmd = SOR;
- break;
-#if defined(CONFIG_8xx)
- case 'i':
- cmd = INT;
- break;
-#endif
- default:
- printf ("iopset: unknown command %s\n", argv[3]);
- rcode = 1;
- }
- if (argv[4][0] == '1')
- value = 1;
- else if (argv[4][0] == '0')
- value = 0;
- else
- rcode = 1;
- if (rcode == 0) {
- iopin.port = port;
- iopin.pin = pin;
- iopin.flag = 0;
- switch (cmd) {
- case DIR:
- if (value)
- iopin_set_out (&iopin);
- else
- iopin_set_in (&iopin);
- break;
- case PAR:
- if (value)
- iopin_set_ded (&iopin);
- else
- iopin_set_gen (&iopin);
- break;
- case SOR:
- if (value)
- iopin_set_opt2 (&iopin);
- else
- iopin_set_opt1 (&iopin);
- break;
- case ODR:
- if (value)
- iopin_set_odr (&iopin);
- else
- iopin_set_act (&iopin);
- break;
- case DAT:
- if (value)
- iopin_set_high (&iopin);
- else
- iopin_set_low (&iopin);
- break;
-#if defined(CONFIG_8xx)
- case INT:
- if (value)
- iopin_set_falledge (&iopin);
- else
- iopin_set_anyedge (&iopin);
- break;
-#endif
- }
-
- }
- return rcode;
-}
-
-int
-do_dmainfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unimplemented (cmdtp, flag, argc, argv);
- return 0;
-}
-
-int
-do_fccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unimplemented (cmdtp, flag, argc, argv);
- return 0;
-}
-
-static void prbrg (int n, uint val)
-{
- uint extc = (val >> 14) & 3;
- uint cd = (val & CPM_BRG_CD_MASK) >> 1;
- uint div16 = (val & CPM_BRG_DIV16) != 0;
-
-#if defined(CONFIG_8xx)
- ulong clock = gd->cpu_clk;
-#elif defined(CONFIG_MPC8260)
- ulong clock = gd->arch.brg_clk;
-#endif
-
- printf ("BRG%d:", n);
-
- if (val & CPM_BRG_RST)
- puts (" RESET");
- else
- puts (" ");
-
- if (val & CPM_BRG_EN)
- puts (" ENABLED");
- else
- puts (" DISABLED");
-
- printf (" EXTC=%d", extc);
-
- if (val & CPM_BRG_ATB)
- puts (" ATB");
- else
- puts (" ");
-
- printf (" DIVIDER=%4d", cd);
- if (extc == 0 && cd != 0) {
- uint baudrate;
-
- if (div16)
- baudrate = (clock / 16) / (cd + 1);
- else
- baudrate = clock / (cd + 1);
-
- printf ("=%6d bps", baudrate);
- } else {
- puts (" ");
- }
-
- if (val & CPM_BRG_DIV16)
- puts (" DIV16");
- else
- puts (" ");
-
- putc ('\n');
-}
-
-int
-do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-#if defined(CONFIG_8xx)
- volatile cpm8xx_t *cp = &immap->im_cpm;
- volatile uint *p = &cp->cp_brgc1;
-#elif defined(CONFIG_MPC8260)
- volatile uint *p = &immap->im_brgc1;
-#endif
- int i = 1;
-
- while (i <= 4)
- prbrg (i++, *p++);
-
-#if defined(CONFIG_MPC8260)
- p = &immap->im_brgc5;
- while (i <= 8)
- prbrg (i++, *p++);
-#endif
- return 0;
-}
-
-int
-do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-#if defined(CONFIG_8xx)
- volatile i2c8xx_t *i2c = &immap->im_i2c;
- volatile cpm8xx_t *cp = &immap->im_cpm;
- volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC];
-#elif defined(CONFIG_MPC8260)
- volatile i2c8260_t *i2c = &immap->im_i2c;
- volatile iic_t *iip;
- uint dpaddr;
-
- dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)];
- if (dpaddr == 0)
- iip = NULL;
- else
- iip = (iic_t *) & immap->im_dprambase[dpaddr];
-#endif
-
- printf ("I2MOD = %02x I2ADD = %02x\n", i2c->i2c_i2mod, i2c->i2c_i2add);
- printf ("I2BRG = %02x I2COM = %02x\n", i2c->i2c_i2brg, i2c->i2c_i2com);
- printf ("I2CER = %02x I2CMR = %02x\n", i2c->i2c_i2cer, i2c->i2c_i2cmr);
-
- if (iip == NULL)
- puts ("i2c parameter ram not allocated\n");
- else {
- printf ("RBASE = %08x TBASE = %08x\n",
- iip->iic_rbase, iip->iic_tbase);
- printf ("RFCR = %02x TFCR = %02x\n",
- iip->iic_rfcr, iip->iic_tfcr);
- printf ("MRBLR = %04x\n", iip->iic_mrblr);
- printf ("RSTATE= %08x RDP = %08x\n",
- iip->iic_rstate, iip->iic_rdp);
- printf ("RBPTR = %04x RBC = %04x\n",
- iip->iic_rbptr, iip->iic_rbc);
- printf ("RXTMP = %08x\n", iip->iic_rxtmp);
- printf ("TSTATE= %08x TDP = %08x\n",
- iip->iic_tstate, iip->iic_tdp);
- printf ("TBPTR = %04x TBC = %04x\n",
- iip->iic_tbptr, iip->iic_tbc);
- printf ("TXTMP = %08x\n", iip->iic_txtmp);
- }
- return 0;
-}
-
-int
-do_sccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unimplemented (cmdtp, flag, argc, argv);
- return 0;
-}
-
-int
-do_smcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unimplemented (cmdtp, flag, argc, argv);
- return 0;
-}
-
-int
-do_spiinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unimplemented (cmdtp, flag, argc, argv);
- return 0;
-}
-
-int
-do_muxinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unimplemented (cmdtp, flag, argc, argv);
- return 0;
-}
-
-int
-do_siinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unimplemented (cmdtp, flag, argc, argv);
- return 0;
-}
-
-int
-do_mccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unimplemented (cmdtp, flag, argc, argv);
- return 0;
-}
-
-/***************************************************/
-
-U_BOOT_CMD(
- siuinfo, 1, 1, do_siuinfo,
- "print System Interface Unit (SIU) registers",
- ""
-);
-
-U_BOOT_CMD(
- memcinfo, 1, 1, do_memcinfo,
- "print Memory Controller registers",
- ""
-);
-
-U_BOOT_CMD(
- sitinfo, 1, 1, do_sitinfo,
- "print System Integration Timers (SIT) registers",
- ""
-);
-
-#ifdef CONFIG_MPC8260
-U_BOOT_CMD(
- icinfo, 1, 1, do_icinfo,
- "print Interrupt Controller registers",
- ""
-);
-#endif
-
-U_BOOT_CMD(
- carinfo, 1, 1, do_carinfo,
- "print Clocks and Reset registers",
- ""
-);
-
-U_BOOT_CMD(
- iopinfo, 1, 1, do_iopinfo,
- "print I/O Port registers",
- ""
-);
-
-U_BOOT_CMD(
- iopset, 5, 0, do_iopset,
- "set I/O Port registers",
- "PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1"
-);
-
-U_BOOT_CMD(
- dmainfo, 1, 1, do_dmainfo,
- "print SDMA/IDMA registers",
- ""
-);
-
-U_BOOT_CMD(
- fccinfo, 1, 1, do_fccinfo,
- "print FCC registers",
- ""
-);
-
-U_BOOT_CMD(
- brginfo, 1, 1, do_brginfo,
- "print Baud Rate Generator (BRG) registers",
- ""
-);
-
-U_BOOT_CMD(
- i2cinfo, 1, 1, do_i2cinfo,
- "print I2C registers",
- ""
-);
-
-U_BOOT_CMD(
- sccinfo, 1, 1, do_sccinfo,
- "print SCC registers",
- ""
-);
-
-U_BOOT_CMD(
- smcinfo, 1, 1, do_smcinfo,
- "print SMC registers",
- ""
-);
-
-U_BOOT_CMD(
- spiinfo, 1, 1, do_spiinfo,
- "print Serial Peripheral Interface (SPI) registers",
- ""
-);
-
-U_BOOT_CMD(
- muxinfo, 1, 1, do_muxinfo,
- "print CPM Multiplexing registers",
- ""
-);
-
-U_BOOT_CMD(
- siinfo, 1, 1, do_siinfo,
- "print Serial Interface (SI) registers",
- ""
-);
-
-U_BOOT_CMD(
- mccinfo, 1, 1, do_mccinfo,
- "print MCC registers",
- ""
-);
-
-#endif
#undef CHECK_IDE_DEVICE
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CHECK_IDE_DEVICE
#endif
endmenu
+menu "Security support"
+
+config HASH
+ bool # "Support hashing API (SHA1, SHA256, etc.)"
+ help
+ This provides a way to hash data in memory using various supported
+ algorithms (such as SHA1, MD5, CRC32). The API is defined in hash.h
+ and the algorithms it supports are defined in common/hash.c. See
+ also CMD_HASH for command-line access.
+
+endmenu
+
source "common/spl/Kconfig"
obj-y += init/
obj-y += main.o
obj-y += exports.o
-obj-y += hash.o
+obj-$(CONFIG_HASH) += hash.o
obj-$(CONFIG_HUSH_PARSER) += cli_hush.o
obj-$(CONFIG_AUTOBOOT) += autoboot.o
ifdef CONFIG_SYS_MALLOC_F_LEN
obj-y += malloc_simple.o
endif
-obj-$(CONFIG_CMD_IDE) += ide.o
obj-y += image.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
#include <dm.h>
#include <environment.h>
#include <fdtdec.h>
-#if defined(CONFIG_CMD_IDE)
#include <ide.h>
-#endif
#include <initcall.h>
#include <init_helpers.h>
#ifdef CONFIG_PS2KBD
}
#endif
-#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE)
static int initr_pcmcia(void)
{
puts("PCMCIA:");
}
#endif
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_IDE)
static int initr_ide(void)
{
#ifdef CONFIG_IDE_8xx_PCCARD
#ifdef CONFIG_POST
initr_post,
#endif
-#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE)
initr_pcmcia,
#endif
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_IDE)
initr_ide,
#endif
#ifdef CONFIG_LAST_STAGE_INIT
return 0;
}
-#endif
-#endif
+#endif /* CONFIG_CMD_HASH || CONFIG_CMD_SHA1SUM || CONFIG_CMD_CRC32) */
+#endif /* !USE_HOSTCC */
+++ /dev/null
-/*
- * (C) Copyright 2000-2011
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ata.h>
-#include <dm.h>
-#include <ide.h>
-#include <watchdog.h>
-#include <asm/io.h>
-
-#ifdef __PPC__
-# define EIEIO __asm__ volatile ("eieio")
-# define SYNC __asm__ volatile ("sync")
-#else
-# define EIEIO /* nothing */
-# define SYNC /* nothing */
-#endif
-
-/* Current offset for IDE0 / IDE1 bus access */
-ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
-#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
- CONFIG_SYS_ATA_IDE0_OFFSET,
-#endif
-#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)
- CONFIG_SYS_ATA_IDE1_OFFSET,
-#endif
-};
-
-static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
-
-struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
-
-#define IDE_TIME_OUT 2000 /* 2 sec timeout */
-
-#define ATAPI_TIME_OUT 7000 /* 7 sec timeout (5 sec seems to work...) */
-
-#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
-
-#ifndef CONFIG_SYS_ATA_PORT_ADDR
-#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
-#endif
-
-#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */
-# define DEVICE_LED(x) 0
-# define LED_IDE1 1
-# define LED_IDE2 2
-#endif
-
-#ifdef CONFIG_IDE_RESET
-extern void ide_set_reset(int idereset);
-
-static void ide_reset(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
- ide_bus_ok[i] = 0;
- for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
- ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-
- ide_set_reset(1); /* assert reset */
-
- /* the reset signal shall be asserted for et least 25 us */
- udelay(25);
-
- WATCHDOG_RESET();
-
- /* de-assert RESET signal */
- ide_set_reset(0);
-
- /* wait 250 ms */
- for (i = 0; i < 250; ++i)
- udelay(1000);
-}
-#else
-#define ide_reset() /* dummy */
-#endif /* CONFIG_IDE_RESET */
-
-/*
- * Wait until Busy bit is off, or timeout (in ms)
- * Return last status
- */
-static uchar ide_wait(int dev, ulong t)
-{
- ulong delay = 10 * t; /* poll every 100 us */
- uchar c;
-
- while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
- udelay(100);
- if (delay-- == 0)
- break;
- }
- return c;
-}
-
-/*
- * copy src to dest, skipping leading and trailing blanks and null
- * terminate the string
- * "len" is the size of available memory including the terminating '\0'
- */
-static void ident_cpy(unsigned char *dst, unsigned char *src,
- unsigned int len)
-{
- unsigned char *end, *last;
-
- last = dst;
- end = src + len - 1;
-
- /* reserve space for '\0' */
- if (len < 2)
- goto OUT;
-
- /* skip leading white space */
- while ((*src) && (src < end) && (*src == ' '))
- ++src;
-
- /* copy string, omitting trailing white space */
- while ((*src) && (src < end)) {
- *dst++ = *src;
- if (*src++ != ' ')
- last = dst;
- }
-OUT:
- *last = '\0';
-}
-
-#ifdef CONFIG_ATAPI
-/****************************************************************************
- * ATAPI Support
- */
-
-#if defined(CONFIG_IDE_SWAP_IO)
-/* since ATAPI may use commands with not 4 bytes alligned length
- * we have our own transfer functions, 2 bytes alligned */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
- ushort *dbuf;
- volatile ushort *pbuf;
-
- pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
- dbuf = (ushort *)sect_buf;
-
- debug("in output data shorts base for read is %lx\n",
- (unsigned long) pbuf);
-
- while (shorts--) {
- EIEIO;
- *pbuf = *dbuf++;
- }
-}
-
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
- ushort *dbuf;
- volatile ushort *pbuf;
-
- pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
- dbuf = (ushort *)sect_buf;
-
- debug("in input data shorts base for read is %lx\n",
- (unsigned long) pbuf);
-
- while (shorts--) {
- EIEIO;
- *dbuf++ = *pbuf;
- }
-}
-
-#else /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
- outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
-}
-
-__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
-{
- insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
-}
-
-#endif /* CONFIG_IDE_SWAP_IO */
-
-/*
- * Wait until (Status & mask) == res, or timeout (in ms)
- * Return last status
- * This is used since some ATAPI CD ROMs clears their Busy Bit first
- * and then they set their DRQ Bit
- */
-static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
-{
- ulong delay = 10 * t; /* poll every 100 us */
- uchar c;
-
- /* prevents to read the status before valid */
- c = ide_inb(dev, ATA_DEV_CTL);
-
- while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
- /* break if error occurs (doesn't make sense to wait more) */
- if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
- break;
- udelay(100);
- if (delay-- == 0)
- break;
- }
- return c;
-}
-
-/*
- * issue an atapi command
- */
-unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
- unsigned char *buffer, int buflen)
-{
- unsigned char c, err, mask, res;
- int n;
-
- ide_led(DEVICE_LED(device), 1); /* LED on */
-
- /* Select device
- */
- mask = ATA_STAT_BUSY | ATA_STAT_DRQ;
- res = 0;
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
- c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
- if ((c & mask) != res) {
- printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
- c);
- err = 0xFF;
- goto AI_OUT;
- }
- /* write taskfile */
- ide_outb(device, ATA_ERROR_REG, 0); /* no DMA, no overlaped */
- ide_outb(device, ATA_SECT_CNT, 0);
- ide_outb(device, ATA_SECT_NUM, 0);
- ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
- ide_outb(device, ATA_CYL_HIGH,
- (unsigned char) ((buflen >> 8) & 0xFF));
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-
- ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
- udelay(50);
-
- mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
- res = ATA_STAT_DRQ;
- c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
-
- if ((c & mask) != res) { /* DRQ must be 1, BSY 0 */
- printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
- device, c);
- err = 0xFF;
- goto AI_OUT;
- }
-
- /* write command block */
- ide_output_data_shorts(device, (unsigned short *)ccb, ccblen / 2);
-
- /* ATAPI Command written wait for completition */
- udelay(5000); /* device must set bsy */
-
- mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
- /*
- * if no data wait for DRQ = 0 BSY = 0
- * if data wait for DRQ = 1 BSY = 0
- */
- res = 0;
- if (buflen)
- res = ATA_STAT_DRQ;
- c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
- if ((c & mask) != res) {
- if (c & ATA_STAT_ERR) {
- err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
- debug("atapi_issue 1 returned sense key %X status %02X\n",
- err, c);
- } else {
- printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x) status 0x%02x\n",
- ccb[0], c);
- err = 0xFF;
- }
- goto AI_OUT;
- }
- n = ide_inb(device, ATA_CYL_HIGH);
- n <<= 8;
- n += ide_inb(device, ATA_CYL_LOW);
- if (n > buflen) {
- printf("ERROR, transfer bytes %d requested only %d\n", n,
- buflen);
- err = 0xff;
- goto AI_OUT;
- }
- if ((n == 0) && (buflen < 0)) {
- printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
- err = 0xff;
- goto AI_OUT;
- }
- if (n != buflen) {
- debug("WARNING, transfer bytes %d not equal with requested %d\n",
- n, buflen);
- }
- if (n != 0) { /* data transfer */
- debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
- /* we transfer shorts */
- n >>= 1;
- /* ok now decide if it is an in or output */
- if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
- debug("Write to device\n");
- ide_output_data_shorts(device, (unsigned short *)buffer,
- n);
- } else {
- debug("Read from device @ %p shorts %d\n", buffer, n);
- ide_input_data_shorts(device, (unsigned short *)buffer,
- n);
- }
- }
- udelay(5000); /* seems that some CD ROMs need this... */
- mask = ATA_STAT_BUSY | ATA_STAT_ERR;
- res = 0;
- c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
- if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
- err = (ide_inb(device, ATA_ERROR_REG) >> 4);
- debug("atapi_issue 2 returned sense key %X status %X\n", err,
- c);
- } else {
- err = 0;
- }
-AI_OUT:
- ide_led(DEVICE_LED(device), 0); /* LED off */
- return err;
-}
-
-/*
- * sending the command to atapi_issue. If an status other than good
- * returns, an request_sense will be issued
- */
-
-#define ATAPI_DRIVE_NOT_READY 100
-#define ATAPI_UNIT_ATTN 10
-
-unsigned char atapi_issue_autoreq(int device,
- unsigned char *ccb,
- int ccblen,
- unsigned char *buffer, int buflen)
-{
- unsigned char sense_data[18], sense_ccb[12];
- unsigned char res, key, asc, ascq;
- int notready, unitattn;
-
- unitattn = ATAPI_UNIT_ATTN;
- notready = ATAPI_DRIVE_NOT_READY;
-
-retry:
- res = atapi_issue(device, ccb, ccblen, buffer, buflen);
- if (res == 0)
- return 0; /* Ok */
-
- if (res == 0xFF)
- return 0xFF; /* error */
-
- debug("(auto_req)atapi_issue returned sense key %X\n", res);
-
- memset(sense_ccb, 0, sizeof(sense_ccb));
- memset(sense_data, 0, sizeof(sense_data));
- sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
- sense_ccb[4] = 18; /* allocation Length */
-
- res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
- key = (sense_data[2] & 0xF);
- asc = (sense_data[12]);
- ascq = (sense_data[13]);
-
- debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
- debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
- sense_data[0], key, asc, ascq);
-
- if ((key == 0))
- return 0; /* ok device ready */
-
- if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
- if (unitattn-- > 0) {
- udelay(200 * 1000);
- goto retry;
- }
- printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
- goto error;
- }
- if ((asc == 0x4) && (ascq == 0x1)) {
- /* not ready, but will be ready soon */
- if (notready-- > 0) {
- udelay(200 * 1000);
- goto retry;
- }
- printf("Drive not ready, tried %d times\n",
- ATAPI_DRIVE_NOT_READY);
- goto error;
- }
- if (asc == 0x3a) {
- debug("Media not present\n");
- goto error;
- }
-
- printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
- ascq);
-error:
- debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
- return 0xFF;
-}
-
-/*
- * atapi_read:
- * we transfer only one block per command, since the multiple DRQ per
- * command is not yet implemented
- */
-#define ATAPI_READ_MAX_BYTES 2048 /* we read max 2kbytes */
-#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
-#define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
-
-ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer)
-{
- int device = block_dev->devnum;
- ulong n = 0;
- unsigned char ccb[12]; /* Command descriptor block */
- ulong cnt;
-
- debug("atapi_read dev %d start " LBAF " blocks " LBAF
- " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
-
- do {
- if (blkcnt > ATAPI_READ_MAX_BLOCK)
- cnt = ATAPI_READ_MAX_BLOCK;
- else
- cnt = blkcnt;
-
- ccb[0] = ATAPI_CMD_READ_12;
- ccb[1] = 0; /* reserved */
- ccb[2] = (unsigned char) (blknr >> 24) & 0xFF; /* MSB Block */
- ccb[3] = (unsigned char) (blknr >> 16) & 0xFF; /* */
- ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
- ccb[5] = (unsigned char) blknr & 0xFF; /* LSB Block */
- ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
- ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
- ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
- ccb[9] = (unsigned char) cnt & 0xFF; /* LSB Block */
- ccb[10] = 0; /* reserved */
- ccb[11] = 0; /* reserved */
-
- if (atapi_issue_autoreq(device, ccb, 12,
- (unsigned char *)buffer,
- cnt * ATAPI_READ_BLOCK_SIZE)
- == 0xFF) {
- return n;
- }
- n += cnt;
- blkcnt -= cnt;
- blknr += cnt;
- buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
- } while (blkcnt > 0);
- return n;
-}
-
-static void atapi_inquiry(struct blk_desc *dev_desc)
-{
- unsigned char ccb[12]; /* Command descriptor block */
- unsigned char iobuf[64]; /* temp buf */
- unsigned char c;
- int device;
-
- device = dev_desc->devnum;
- dev_desc->type = DEV_TYPE_UNKNOWN; /* not yet valid */
- dev_desc->block_read = atapi_read;
-
- memset(ccb, 0, sizeof(ccb));
- memset(iobuf, 0, sizeof(iobuf));
-
- ccb[0] = ATAPI_CMD_INQUIRY;
- ccb[4] = 40; /* allocation Legnth */
- c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 40);
-
- debug("ATAPI_CMD_INQUIRY returned %x\n", c);
- if (c != 0)
- return;
-
- /* copy device ident strings */
- ident_cpy((unsigned char *)dev_desc->vendor, &iobuf[8], 8);
- ident_cpy((unsigned char *)dev_desc->product, &iobuf[16], 16);
- ident_cpy((unsigned char *)dev_desc->revision, &iobuf[32], 5);
-
- dev_desc->lun = 0;
- dev_desc->lba = 0;
- dev_desc->blksz = 0;
- dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
- dev_desc->type = iobuf[0] & 0x1f;
-
- if ((iobuf[1] & 0x80) == 0x80)
- dev_desc->removable = 1;
- else
- dev_desc->removable = 0;
-
- memset(ccb, 0, sizeof(ccb));
- memset(iobuf, 0, sizeof(iobuf));
- ccb[0] = ATAPI_CMD_START_STOP;
- ccb[4] = 0x03; /* start */
-
- c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
-
- debug("ATAPI_CMD_START_STOP returned %x\n", c);
- if (c != 0)
- return;
-
- memset(ccb, 0, sizeof(ccb));
- memset(iobuf, 0, sizeof(iobuf));
- c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
-
- debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
- if (c != 0)
- return;
-
- memset(ccb, 0, sizeof(ccb));
- memset(iobuf, 0, sizeof(iobuf));
- ccb[0] = ATAPI_CMD_READ_CAP;
- c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 8);
- debug("ATAPI_CMD_READ_CAP returned %x\n", c);
- if (c != 0)
- return;
-
- debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
- iobuf[0], iobuf[1], iobuf[2], iobuf[3],
- iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
-
- dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
- ((unsigned long) iobuf[1] << 16) +
- ((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
- dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
- ((unsigned long) iobuf[5] << 16) +
- ((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
- dev_desc->log2blksz = LOG2(dev_desc->blksz);
-#ifdef CONFIG_LBA48
- /* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
- dev_desc->lba48 = 0;
-#endif
- return;
-}
-
-#endif /* CONFIG_ATAPI */
-
-static void ide_ident(struct blk_desc *dev_desc)
-{
- unsigned char c;
- hd_driveid_t iop;
-
-#ifdef CONFIG_ATAPI
- int retries = 0;
-#endif
- int device;
-
- device = dev_desc->devnum;
- printf(" Device %d: ", device);
-
- ide_led(DEVICE_LED(device), 1); /* LED on */
- /* Select device
- */
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
- dev_desc->if_type = IF_TYPE_IDE;
-#ifdef CONFIG_ATAPI
-
- retries = 0;
-
- /* Warning: This will be tricky to read */
- while (retries <= 1) {
- /* check signature */
- if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
- (ide_inb(device, ATA_SECT_NUM) == 0x01) &&
- (ide_inb(device, ATA_CYL_LOW) == 0x14) &&
- (ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
- /* ATAPI Signature found */
- dev_desc->if_type = IF_TYPE_ATAPI;
- /*
- * Start Ident Command
- */
- ide_outb(device, ATA_COMMAND, ATAPI_CMD_IDENT);
- /*
- * Wait for completion - ATAPI devices need more time
- * to become ready
- */
- c = ide_wait(device, ATAPI_TIME_OUT);
- } else
-#endif
- {
- /*
- * Start Ident Command
- */
- ide_outb(device, ATA_COMMAND, ATA_CMD_IDENT);
-
- /*
- * Wait for completion
- */
- c = ide_wait(device, IDE_TIME_OUT);
- }
- ide_led(DEVICE_LED(device), 0); /* LED off */
-
- if (((c & ATA_STAT_DRQ) == 0) ||
- ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) {
-#ifdef CONFIG_ATAPI
- {
- /*
- * Need to soft reset the device
- * in case it's an ATAPI...
- */
- debug("Retrying...\n");
- ide_outb(device, ATA_DEV_HD,
- ATA_LBA | ATA_DEVICE(device));
- udelay(100000);
- ide_outb(device, ATA_COMMAND, 0x08);
- udelay(500000); /* 500 ms */
- }
- /*
- * Select device
- */
- ide_outb(device, ATA_DEV_HD,
- ATA_LBA | ATA_DEVICE(device));
- retries++;
-#else
- return;
-#endif
- }
-#ifdef CONFIG_ATAPI
- else
- break;
- } /* see above - ugly to read */
-
- if (retries == 2) /* Not found */
- return;
-#endif
-
- ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
-
- ident_cpy((unsigned char *)dev_desc->revision, iop.fw_rev,
- sizeof(dev_desc->revision));
- ident_cpy((unsigned char *)dev_desc->vendor, iop.model,
- sizeof(dev_desc->vendor));
- ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
- sizeof(dev_desc->product));
-#ifdef __LITTLE_ENDIAN
- /*
- * firmware revision, model, and serial number have Big Endian Byte
- * order in Word. Convert all three to little endian.
- *
- * See CF+ and CompactFlash Specification Revision 2.0:
- * 6.2.1.6: Identify Drive, Table 39 for more details
- */
-
- strswab(dev_desc->revision);
- strswab(dev_desc->vendor);
- strswab(dev_desc->product);
-#endif /* __LITTLE_ENDIAN */
-
- if ((iop.config & 0x0080) == 0x0080)
- dev_desc->removable = 1;
- else
- dev_desc->removable = 0;
-
-#ifdef CONFIG_ATAPI
- if (dev_desc->if_type == IF_TYPE_ATAPI) {
- atapi_inquiry(dev_desc);
- return;
- }
-#endif /* CONFIG_ATAPI */
-
-#ifdef __BIG_ENDIAN
- /* swap shorts */
- dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16);
-#else /* ! __BIG_ENDIAN */
- /*
- * do not swap shorts on little endian
- *
- * See CF+ and CompactFlash Specification Revision 2.0:
- * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
- */
- dev_desc->lba = iop.lba_capacity;
-#endif /* __BIG_ENDIAN */
-
-#ifdef CONFIG_LBA48
- if (iop.command_set_2 & 0x0400) { /* LBA 48 support */
- dev_desc->lba48 = 1;
- dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] |
- ((unsigned long long) iop.lba48_capacity[1] << 16) |
- ((unsigned long long) iop.lba48_capacity[2] << 32) |
- ((unsigned long long) iop.lba48_capacity[3] << 48);
- } else {
- dev_desc->lba48 = 0;
- }
-#endif /* CONFIG_LBA48 */
- /* assuming HD */
- dev_desc->type = DEV_TYPE_HARDDISK;
- dev_desc->blksz = ATA_BLOCKSIZE;
- dev_desc->log2blksz = LOG2(dev_desc->blksz);
- dev_desc->lun = 0; /* just to fill something in... */
-
-#if 0 /* only used to test the powersaving mode,
- * if enabled, the drive goes after 5 sec
- * in standby mode */
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
- c = ide_wait(device, IDE_TIME_OUT);
- ide_outb(device, ATA_SECT_CNT, 1);
- ide_outb(device, ATA_LBA_LOW, 0);
- ide_outb(device, ATA_LBA_MID, 0);
- ide_outb(device, ATA_LBA_HIGH, 0);
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
- ide_outb(device, ATA_COMMAND, 0xe3);
- udelay(50);
- c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
-#endif
-}
-
-__weak void ide_led(uchar led, uchar status)
-{
-#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
- static uchar led_buffer; /* Buffer for current LED status */
-
- uchar *led_port = LED_PORT;
-
- if (status) /* switch LED on */
- led_buffer |= led;
- else /* switch LED off */
- led_buffer &= ~led;
-
- *led_port = led_buffer;
-#endif
-}
-
-__weak void ide_outb(int dev, int port, unsigned char val)
-{
- debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
- dev, port, val,
- (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-
-#if defined(CONFIG_IDE_AHB)
- if (port) {
- /* write command */
- ide_write_register(dev, port, val);
- } else {
- /* write data */
- outb(val, (ATA_CURR_BASE(dev)));
- }
-#else
- outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-#endif
-}
-
-__weak unsigned char ide_inb(int dev, int port)
-{
- uchar val;
-
-#if defined(CONFIG_IDE_AHB)
- val = ide_read_register(dev, port);
-#else
- val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
-#endif
-
- debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
- dev, port,
- (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
- return val;
-}
-
-void ide_init(void)
-{
- unsigned char c;
- int i, bus;
-
-#ifdef CONFIG_IDE_8xx_PCCARD
- extern int ide_devices_found; /* Initialized in check_ide_device() */
-#endif /* CONFIG_IDE_8xx_PCCARD */
-
-#ifdef CONFIG_IDE_PREINIT
- WATCHDOG_RESET();
-
- if (ide_preinit()) {
- puts("ide_preinit failed\n");
- return;
- }
-#endif /* CONFIG_IDE_PREINIT */
-
- WATCHDOG_RESET();
-
- /*
- * Reset the IDE just to be sure.
- * Light LED's to show
- */
- ide_led((LED_IDE1 | LED_IDE2), 1); /* LED's on */
-
- /* ATAPI Drives seems to need a proper IDE Reset */
- ide_reset();
-
-#ifdef CONFIG_IDE_INIT_POSTRESET
- WATCHDOG_RESET();
-
- if (ide_init_postreset()) {
- puts("ide_preinit_postreset failed\n");
- return;
- }
-#endif /* CONFIG_IDE_INIT_POSTRESET */
-
- /*
- * Wait for IDE to get ready.
- * According to spec, this can take up to 31 seconds!
- */
- for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
- int dev =
- bus * (CONFIG_SYS_IDE_MAXDEVICE /
- CONFIG_SYS_IDE_MAXBUS);
-
-#ifdef CONFIG_IDE_8xx_PCCARD
- /* Skip non-ide devices from probing */
- if ((ide_devices_found & (1 << bus)) == 0) {
- ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
- continue;
- }
-#endif
- printf("Bus %d: ", bus);
-
- ide_bus_ok[bus] = 0;
-
- /* Select device
- */
- udelay(100000); /* 100 ms */
- ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
- udelay(100000); /* 100 ms */
- i = 0;
- do {
- udelay(10000); /* 10 ms */
-
- c = ide_inb(dev, ATA_STATUS);
- i++;
- if (i > (ATA_RESET_TIME * 100)) {
- puts("** Timeout **\n");
- /* LED's off */
- ide_led((LED_IDE1 | LED_IDE2), 0);
- return;
- }
- if ((i >= 100) && ((i % 100) == 0))
- putc('.');
-
- } while (c & ATA_STAT_BUSY);
-
- if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
- puts("not available ");
- debug("Status = 0x%02X ", c);
-#ifndef CONFIG_ATAPI /* ATAPI Devices do not set DRDY */
- } else if ((c & ATA_STAT_READY) == 0) {
- puts("not available ");
- debug("Status = 0x%02X ", c);
-#endif
- } else {
- puts("OK ");
- ide_bus_ok[bus] = 1;
- }
- WATCHDOG_RESET();
- }
-
- putc('\n');
-
- ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
-
- for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
- int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
- ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
- ide_dev_desc[i].if_type = IF_TYPE_IDE;
- ide_dev_desc[i].devnum = i;
- ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
- ide_dev_desc[i].blksz = 0;
- ide_dev_desc[i].log2blksz =
- LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
- ide_dev_desc[i].lba = 0;
-#ifndef CONFIG_BLK
- ide_dev_desc[i].block_read = ide_read;
- ide_dev_desc[i].block_write = ide_write;
-#endif
- if (!ide_bus_ok[IDE_BUS(i)])
- continue;
- ide_led(led, 1); /* LED on */
- ide_ident(&ide_dev_desc[i]);
- ide_led(led, 0); /* LED off */
- dev_print(&ide_dev_desc[i]);
-
- if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
- /* initialize partition type */
- part_init(&ide_dev_desc[i]);
- }
- }
- WATCHDOG_RESET();
-}
-
-/* We only need to swap data if we are running on a big endian cpu. */
-#if defined(__LITTLE_ENDIAN)
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
- ide_input_data(dev, sect_buf, words);
-}
-#else
-__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
- volatile ushort *pbuf =
- (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
- ushort *dbuf = (ushort *)sect_buf;
-
- debug("in input swap data base for read is %lx\n",
- (unsigned long) pbuf);
-
- while (words--) {
-#ifdef __MIPS__
- *dbuf++ = swab16p((u16 *)pbuf);
- *dbuf++ = swab16p((u16 *)pbuf);
-#else
- *dbuf++ = ld_le16(pbuf);
- *dbuf++ = ld_le16(pbuf);
-#endif /* !MIPS */
- }
-}
-#endif /* __LITTLE_ENDIAN */
-
-
-#if defined(CONFIG_IDE_SWAP_IO)
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
- ushort *dbuf;
- volatile ushort *pbuf;
-
- pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
- dbuf = (ushort *)sect_buf;
- while (words--) {
- EIEIO;
- *pbuf = *dbuf++;
- EIEIO;
- *pbuf = *dbuf++;
- }
-}
-#else /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
-{
-#if defined(CONFIG_IDE_AHB)
- ide_write_data(dev, sect_buf, words);
-#else
- outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
-#endif
-}
-#endif /* CONFIG_IDE_SWAP_IO */
-
-#if defined(CONFIG_IDE_SWAP_IO)
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
-{
- ushort *dbuf;
- volatile ushort *pbuf;
-
- pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
- dbuf = (ushort *)sect_buf;
-
- debug("in input data base for read is %lx\n", (unsigned long) pbuf);
-
- while (words--) {
- EIEIO;
- *dbuf++ = *pbuf;
- EIEIO;
- *dbuf++ = *pbuf;
- }
-}
-#else /* ! CONFIG_IDE_SWAP_IO */
-__weak void ide_input_data(int dev, ulong *sect_buf, int words)
-{
-#if defined(CONFIG_IDE_AHB)
- ide_read_data(dev, sect_buf, words);
-#else
- insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
-#endif
-}
-
-#endif /* CONFIG_IDE_SWAP_IO */
-
-#ifdef CONFIG_BLK
-ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer)
-#else
-ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
- void *buffer)
-#endif
-{
-#ifdef CONFIG_BLK
- struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
-#endif
- int device = block_dev->devnum;
- ulong n = 0;
- unsigned char c;
- unsigned char pwrsave = 0; /* power save */
-
-#ifdef CONFIG_LBA48
- unsigned char lba48 = 0;
-
- if (blknr & 0x0000fffff0000000ULL) {
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
- debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
- device, blknr, blkcnt, (ulong) buffer);
-
- ide_led(DEVICE_LED(device), 1); /* LED on */
-
- /* Select device
- */
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
- c = ide_wait(device, IDE_TIME_OUT);
-
- if (c & ATA_STAT_BUSY) {
- printf("IDE read: device %d not ready\n", device);
- goto IDE_READ_E;
- }
-
- /* first check if the drive is in Powersaving mode, if yes,
- * increase the timeout value */
- ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
- udelay(50);
-
- c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
-
- if (c & ATA_STAT_BUSY) {
- printf("IDE read: device %d not ready\n", device);
- goto IDE_READ_E;
- }
- if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
- printf("No Powersaving mode %X\n", c);
- } else {
- c = ide_inb(device, ATA_SECT_CNT);
- debug("Powersaving %02X\n", c);
- if (c == 0)
- pwrsave = 1;
- }
-
-
- while (blkcnt-- > 0) {
- c = ide_wait(device, IDE_TIME_OUT);
-
- if (c & ATA_STAT_BUSY) {
- printf("IDE read: device %d not ready\n", device);
- break;
- }
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- ide_outb(device, ATA_SECT_CNT, 0);
- ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
-#ifdef CONFIG_SYS_64BIT_LBA
- ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
- ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
-#else
- ide_outb(device, ATA_LBA_MID, 0);
- ide_outb(device, ATA_LBA_HIGH, 0);
-#endif
- }
-#endif
- ide_outb(device, ATA_SECT_CNT, 1);
- ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
- ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
- ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
-
-#ifdef CONFIG_LBA48
- if (lba48) {
- ide_outb(device, ATA_DEV_HD,
- ATA_LBA | ATA_DEVICE(device));
- ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
-
- } else
-#endif
- {
- ide_outb(device, ATA_DEV_HD, ATA_LBA |
- ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
- ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
- }
-
- udelay(50);
-
- if (pwrsave) {
- /* may take up to 4 sec */
- c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
- pwrsave = 0;
- } else {
- /* can't take over 500 ms */
- c = ide_wait(device, IDE_TIME_OUT);
- }
-
- if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
- ATA_STAT_DRQ) {
- printf("Error (no IRQ) dev %d blk " LBAF
- ": status %#02x\n", device, blknr, c);
- break;
- }
-
- ide_input_data(device, buffer, ATA_SECTORWORDS);
- (void) ide_inb(device, ATA_STATUS); /* clear IRQ */
-
- ++n;
- ++blknr;
- buffer += ATA_BLOCKSIZE;
- }
-IDE_READ_E:
- ide_led(DEVICE_LED(device), 0); /* LED off */
- return n;
-}
-
-#ifdef CONFIG_BLK
-ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
- const void *buffer)
-#else
-ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
- const void *buffer)
-#endif
-{
-#ifdef CONFIG_BLK
- struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
-#endif
- int device = block_dev->devnum;
- ulong n = 0;
- unsigned char c;
-
-#ifdef CONFIG_LBA48
- unsigned char lba48 = 0;
-
- if (blknr & 0x0000fffff0000000ULL) {
- /* more than 28 bits used, use 48bit mode */
- lba48 = 1;
- }
-#endif
-
- ide_led(DEVICE_LED(device), 1); /* LED on */
-
- /* Select device
- */
- ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
-
- while (blkcnt-- > 0) {
- c = ide_wait(device, IDE_TIME_OUT);
-
- if (c & ATA_STAT_BUSY) {
- printf("IDE read: device %d not ready\n", device);
- goto WR_OUT;
- }
-#ifdef CONFIG_LBA48
- if (lba48) {
- /* write high bits */
- ide_outb(device, ATA_SECT_CNT, 0);
- ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
-#ifdef CONFIG_SYS_64BIT_LBA
- ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
- ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
-#else
- ide_outb(device, ATA_LBA_MID, 0);
- ide_outb(device, ATA_LBA_HIGH, 0);
-#endif
- }
-#endif
- ide_outb(device, ATA_SECT_CNT, 1);
- ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
- ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
- ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
-
-#ifdef CONFIG_LBA48
- if (lba48) {
- ide_outb(device, ATA_DEV_HD,
- ATA_LBA | ATA_DEVICE(device));
- ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
-
- } else
-#endif
- {
- ide_outb(device, ATA_DEV_HD, ATA_LBA |
- ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
- ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
- }
-
- udelay(50);
-
- /* can't take over 500 ms */
- c = ide_wait(device, IDE_TIME_OUT);
-
- if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
- ATA_STAT_DRQ) {
- printf("Error (no IRQ) dev %d blk " LBAF
- ": status %#02x\n", device, blknr, c);
- goto WR_OUT;
- }
-
- ide_output_data(device, buffer, ATA_SECTORWORDS);
- c = ide_inb(device, ATA_STATUS); /* clear IRQ */
- ++n;
- ++blknr;
- buffer += ATA_BLOCKSIZE;
- }
-WR_OUT:
- ide_led(DEVICE_LED(device), 0); /* LED off */
- return n;
-}
-
-#if defined(CONFIG_OF_IDE_FIXUP)
-int ide_device_present(int dev)
-{
- if (dev >= CONFIG_SYS_IDE_MAXBUS)
- return 0;
- return ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1;
-}
-#endif
-
-#ifdef CONFIG_BLK
-static const struct blk_ops ide_blk_ops = {
- .read = ide_read,
- .write = ide_write,
-};
-
-U_BOOT_DRIVER(ide_blk) = {
- .name = "ide_blk",
- .id = UCLASS_BLK,
- .ops = &ide_blk_ops,
-};
-#else
-U_BOOT_LEGACY_BLK(ide) = {
- .if_typename = "ide",
- .if_type = IF_TYPE_IDE,
- .max_devs = CONFIG_SYS_IDE_MAXDEVICE,
- .desc = ide_dev_desc,
-};
-#endif
help
If you want to build SPL as well as the normal image, say Y.
+config SPL_BOARD_INIT
+ depends on SPL
+ bool "Call board-specific initialization in SPL"
+ help
+ If this option is enabled, U-Boot will call the function
+ spl_board_init() from board_init_r(). This function should be
+ provided by the board.
+
config SPL_RAW_IMAGE_SUPPORT
bool "Support SPL loading and booting of RAW images"
depends on SPL
config SPL_SHA1_SUPPORT
bool "Support SHA1"
depends on SPL_FIT
+ select SHA1
help
Enable this to support SHA1 in FIT images within SPL. A SHA1
checksum is a 160-bit (20-byte) hash value used to check that the
config SPL_SHA256_SUPPORT
bool "Support SHA256"
depends on SPL_FIT
+ select SHA256
help
Enable this to support SHA256 in FIT images within SPL. A SHA256
checksum is a 256-bit (32-byte) hash value used to check that the
config SPL_HASH_SUPPORT
bool "Support hashing drivers"
+ select SHA1
+ select SHA256
depends on SPL
help
Enable hashing drivers in SPL. These drivers can be used to
#include <libfdt.h>
#include <spl.h>
+#define FDT_ERROR ((ulong)(-1))
+
static ulong fdt_getprop_u32(const void *fdt, int node, const char *prop)
{
const u32 *cell;
int len;
cell = fdt_getprop(fdt, node, prop, &len);
- if (len != sizeof(*cell))
- return -1U;
+ if (!cell || len != sizeof(*cell))
+ return FDT_ERROR;
+
return fdt32_to_cpu(*cell);
}
-static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
+/*
+ * Iterate over all /configurations subnodes and call a platform specific
+ * function to find the matching configuration.
+ * Returns the node offset or a negative error number.
+ */
+static int spl_fit_find_config_node(const void *fdt)
{
- const char *name, *fdt_name;
- int conf, node, fdt_node;
- int len;
+ const char *name;
+ int conf, node, len;
- *fdt_offsetp = 0;
conf = fdt_path_offset(fdt, FIT_CONFS_PATH);
if (conf < 0) {
debug("%s: Cannot find /configurations node: %d\n", __func__,
continue;
debug("Selecting config '%s'", name);
- fdt_name = fdt_getprop(fdt, node, FIT_FDT_PROP, &len);
- if (!fdt_name) {
- debug("%s: Cannot find fdt name property: %d\n",
- __func__, len);
- return -EINVAL;
- }
- debug(", fdt '%s'\n", fdt_name);
- fdt_node = fdt_subnode_offset(fdt, images, fdt_name);
- if (fdt_node < 0) {
- debug("%s: Cannot find fdt node '%s': %d\n",
- __func__, fdt_name, fdt_node);
- return -EINVAL;
+ return node;
+ }
+
+ return -ENOENT;
+}
+
+/**
+ * spl_fit_get_image_node(): By using the matching configuration subnode,
+ * retrieve the name of an image, specified by a property name and an index
+ * into that.
+ * @fit: Pointer to the FDT blob.
+ * @images: Offset of the /images subnode.
+ * @type: Name of the property within the configuration subnode.
+ * @index: Index into the list of strings in this property.
+ *
+ * Return: the node offset of the respective image node or a negative
+ * error number.
+ */
+static int spl_fit_get_image_node(const void *fit, int images,
+ const char *type, int index)
+{
+ const char *name, *str;
+ int node, conf_node;
+ int len, i;
+
+ conf_node = spl_fit_find_config_node(fit);
+ if (conf_node < 0) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ printf("No matching DT out of these options:\n");
+ for (node = fdt_first_subnode(fit, conf_node);
+ node >= 0;
+ node = fdt_next_subnode(fit, node)) {
+ name = fdt_getprop(fit, node, "description", &len);
+ printf(" %s\n", name);
}
+#endif
+ return conf_node;
+ }
- *fdt_offsetp = fdt_getprop_u32(fdt, fdt_node, "data-offset");
- len = fdt_getprop_u32(fdt, fdt_node, "data-size");
- debug("FIT: Selected '%s'\n", name);
+ name = fdt_getprop(fit, conf_node, type, &len);
+ if (!name) {
+ debug("cannot find property '%s': %d\n", type, len);
+ return -EINVAL;
+ }
- return len;
+ str = name;
+ for (i = 0; i < index; i++) {
+ str = strchr(str, '\0') + 1;
+ if (!str || (str - name >= len)) {
+ debug("no string for index %d\n", index);
+ return -E2BIG;
+ }
}
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("No matching DT out of these options:\n");
- for (node = fdt_first_subnode(fdt, conf);
- node >= 0;
- node = fdt_next_subnode(fdt, node)) {
- name = fdt_getprop(fdt, node, "description", &len);
- printf(" %s\n", name);
+ debug("%s: '%s'\n", type, str);
+ node = fdt_subnode_offset(fit, images, str);
+ if (node < 0) {
+ debug("cannot find image node '%s': %d\n", str, node);
+ return -EINVAL;
}
-#endif
- return -ENOENT;
+ return node;
}
static int get_aligned_image_offset(struct spl_load_info *info, int offset)
return (data_size + info->bl_len - 1) / info->bl_len;
}
+/**
+ * spl_load_fit_image(): load the image described in a certain FIT node
+ * @info: points to information about the device to load data from
+ * @sector: the start sector of the FIT image on the device
+ * @fit: points to the flattened device tree blob describing the FIT
+ * image
+ * @base_offset: the beginning of the data area containing the actual
+ * image data, relative to the beginning of the FIT
+ * @node: offset of the DT node describing the image to load (relative
+ * to @fit)
+ * @image_info: will be filled with information about the loaded image
+ * If the FIT node does not contain a "load" (address) property,
+ * the image gets loaded to the address pointed to by the
+ * load_addr member in this struct.
+ *
+ * Return: 0 on success or a negative error number.
+ */
+static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
+ void *fit, ulong base_offset, int node,
+ struct spl_image_info *image_info)
+{
+ ulong offset;
+ size_t length;
+ ulong load_addr, load_ptr;
+ void *src;
+ ulong overhead;
+ int nr_sectors;
+ int align_len = ARCH_DMA_MINALIGN - 1;
+
+ offset = fdt_getprop_u32(fit, node, "data-offset");
+ if (offset == FDT_ERROR)
+ return -ENOENT;
+ offset += base_offset;
+ length = fdt_getprop_u32(fit, node, "data-size");
+ if (length == FDT_ERROR)
+ return -ENOENT;
+ load_addr = fdt_getprop_u32(fit, node, "load");
+ if (load_addr == FDT_ERROR && image_info)
+ load_addr = image_info->load_addr;
+ load_ptr = (load_addr + align_len) & ~align_len;
+
+ overhead = get_aligned_image_overhead(info, offset);
+ nr_sectors = get_aligned_image_size(info, length, offset);
+
+ if (info->read(info, sector + get_aligned_image_offset(info, offset),
+ nr_sectors, (void*)load_ptr) != nr_sectors)
+ return -EIO;
+ debug("image: dst=%lx, offset=%lx, size=%lx\n", load_ptr, offset,
+ (unsigned long)length);
+
+ src = (void *)load_ptr + overhead;
+#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
+ board_fit_image_post_process(&src, &length);
+#endif
+
+ memcpy((void*)load_addr, src, length);
+
+ if (image_info) {
+ image_info->load_addr = load_addr;
+ image_info->size = length;
+ image_info->entry_point = fdt_getprop_u32(fit, node, "entry");
+ }
+
+ return 0;
+}
+
int spl_load_simple_fit(struct spl_image_info *spl_image,
struct spl_load_info *info, ulong sector, void *fit)
{
int sectors;
- ulong size, load;
+ ulong size;
unsigned long count;
- int node, images;
- void *load_ptr;
- int fdt_offset, fdt_len;
- int data_offset, data_size;
+ struct spl_image_info image_info;
+ int node, images, ret;
int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
- int src_sector;
- void *dst, *src;
+ int index = 0;
/*
* Figure out where the external images start. This is the base for the
if (count == 0)
return -EIO;
- /* find the firmware image to load */
+ /* find the node holding the images information */
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
if (images < 0) {
debug("%s: Cannot find /images node: %d\n", __func__, images);
return -1;
}
- node = fdt_first_subnode(fit, images);
+
+ /* find the U-Boot image */
+ node = spl_fit_get_image_node(fit, images, "firmware", 0);
+ if (node < 0) {
+ debug("could not find firmware image, trying loadables...\n");
+ node = spl_fit_get_image_node(fit, images, "loadables", 0);
+ /*
+ * If we pick the U-Boot image from "loadables", start at
+ * the second image when later loading additional images.
+ */
+ index = 1;
+ }
if (node < 0) {
- debug("%s: Cannot find first image node: %d\n", __func__, node);
+ debug("%s: Cannot find u-boot image node: %d\n",
+ __func__, node);
return -1;
}
- /* Get its information and set up the spl_image structure */
- data_offset = fdt_getprop_u32(fit, node, "data-offset");
- data_size = fdt_getprop_u32(fit, node, "data-size");
- load = fdt_getprop_u32(fit, node, "load");
- debug("data_offset=%x, data_size=%x\n", data_offset, data_size);
- spl_image->load_addr = load;
- spl_image->entry_point = load;
- spl_image->os = IH_OS_U_BOOT;
-
- /*
- * Work out where to place the image. We read it so that the first
- * byte will be at 'load'. This may mean we need to load it starting
- * before then, since we can only read whole blocks.
- */
- data_offset += base_offset;
- sectors = get_aligned_image_size(info, data_size, data_offset);
- load_ptr = (void *)load;
- debug("U-Boot size %x, data %p\n", data_size, load_ptr);
- dst = load_ptr;
-
- /* Read the image */
- src_sector = sector + get_aligned_image_offset(info, data_offset);
- debug("Aligned image read: dst=%p, src_sector=%x, sectors=%x\n",
- dst, src_sector, sectors);
- count = info->read(info, src_sector, sectors, dst);
- if (count != sectors)
- return -EIO;
- debug("image: dst=%p, data_offset=%x, size=%x\n", dst, data_offset,
- data_size);
- src = dst + get_aligned_image_overhead(info, data_offset);
+ /* Load the image and set up the spl_image structure */
+ ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+ spl_image);
+ if (ret)
+ return ret;
-#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
- board_fit_image_post_process((void **)&src, (size_t *)&data_size);
-#endif
-
- memcpy(dst, src, data_size);
+ spl_image->os = IH_OS_U_BOOT;
/* Figure out which device tree the board wants to use */
- fdt_len = spl_fit_select_fdt(fit, images, &fdt_offset);
- if (fdt_len < 0)
- return fdt_len;
+ node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
+ if (node < 0) {
+ debug("%s: cannot find FDT node\n", __func__);
+ return node;
+ }
/*
- * Read the device tree and place it after the image. There may be
- * some extra data before it since we can only read entire blocks.
- * And also align the destination address to ARCH_DMA_MINALIGN.
+ * Read the device tree and place it after the image.
+ * Align the destination address to ARCH_DMA_MINALIGN.
*/
- dst = (void *)((load + data_size + align_len) & ~align_len);
- fdt_offset += base_offset;
- sectors = get_aligned_image_size(info, fdt_len, fdt_offset);
- src_sector = sector + get_aligned_image_offset(info, fdt_offset);
- count = info->read(info, src_sector, sectors, dst);
- debug("Aligned fdt read: dst %p, src_sector = %x, sectors %x\n",
- dst, src_sector, sectors);
- if (count != sectors)
- return -EIO;
+ image_info.load_addr = spl_image->load_addr + spl_image->size;
+ ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+ &image_info);
+ if (ret < 0)
+ return ret;
+
+ /* Now check if there are more images for us to load */
+ for (; ; index++) {
+ node = spl_fit_get_image_node(fit, images, "loadables", index);
+ if (node < 0)
+ break;
+
+ ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+ &image_info);
+ if (ret < 0)
+ continue;
+
+ /*
+ * If the "firmware" image did not provide an entry point,
+ * use the first valid entry point from the loadables.
+ */
+ if (spl_image->entry_point == FDT_ERROR &&
+ image_info.entry_point != FDT_ERROR)
+ spl_image->entry_point = image_info.entry_point;
+ }
/*
- * Copy the device tree so that it starts immediately after the image.
- * After this we will have the U-Boot image and its device tree ready
- * for us to start.
+ * If a platform does not provide CONFIG_SYS_UBOOT_START, U-Boot's
+ * Makefile will set it to 0 and it will end up as the entry point
+ * here. What it actually means is: use the load address.
*/
- debug("fdt: dst=%p, data_offset=%x, size=%x\n", dst, fdt_offset,
- fdt_len);
- src = dst + get_aligned_image_overhead(info, fdt_offset);
- dst = load_ptr + data_size;
-
-#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS
- board_fit_image_post_process((void **)&src, (size_t *)&fdt_len);
-#endif
-
- memcpy(dst, src, fdt_len);
+ if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0)
+ spl_image->entry_point = spl_image->load_addr;
return 0;
}
CONFIG_TPL_I2C_SUPPORT=y
CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_NETDEVICES=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_NETDEVICES=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
+CONFIG_CMD_JFFS2=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
+CONFIG_CMD_JFFS2=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_TARGET_M5253DEMO=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_TARGET_M5253EVBE=y
CONFIG_BOOTDELAY=5
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666"
CONFIG_BOOTDELAY=1
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
CONFIG_SYS_PROMPT="-> "
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666"
CONFIG_BOOTDELAY=1
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_TARGET_M54455EVB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333"
CONFIG_BOOTDELAY=1
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_SF=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
+CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="MPC8349E-mITX> "
+CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_PPC=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8536DS=y
CONFIG_PHYS_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_SYS_FSL_DDR2=y
CONFIG_PPC=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8536DS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_SYS_FSL_DDR2=y
CONFIG_PPC=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8536DS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_SYS_FSL_DDR2=y
CONFIG_PPC=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8536DS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_SYS_FSL_DDR2=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8540ADS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8541CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8541CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8544DS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_PHYS_64BIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8555CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8555CDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8560ADS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_OF_LIBFDT=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8568MDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8569MDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8569MDS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_SYS_FSL_DDR2=y
# CONFIG_MMC is not set
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_SYS_FSL_DDR2=y
# CONFIG_MMC is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_BSP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020UTM=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020UTM=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020UTM=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020UTM=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1021RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1023RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=-1
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_EEPROM is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1024RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1024RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1025RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1025RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1025RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1025RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1025RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_TPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_BSP=y
+CONFIG_CMD_IRQ=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
+CONFIG_CMD_FDC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_BSP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
+# CONFIG_CMD_IRQ is not set
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_FSL_CAAM=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_FSL_CAAM=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_FSL_CAAM=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_FSL_CAAM=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_FSL_CAAM=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_FSL_CAAM=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_DM=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_FSL_CAAM=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_FSL_CAAM=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_CMD_IRQ is not set
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_CMD_IRQ is not set
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_CMD_IRQ is not set
CONFIG_DM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_CMD_IRQ is not set
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_CMD_IRQ is not set
CONFIG_FSL_CAAM=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+# CONFIG_CMD_IRQ is not set
CONFIG_FSL_CAAM=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_BSP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_BSP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_BSP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_BSP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_BSP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_BSP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
# CONFIG_MMC is not set
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
+CONFIG_CMD_JFFS2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
# CONFIG_MMC is not set
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1_TWR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=10
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_DATE=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_DATE=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT2=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="asdfg"
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
--- /dev/null
+CONFIG_NDS32=y
+CONFIG_TARGET_ADP_AE3XX=y
+CONFIG_DEFAULT_DEVICE_TREE="ae3xx"
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="NDS32 # "
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DATE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_MMC=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_BAUDRATE=38400
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_MTD=y
+CONFIG_CFI_FLASH=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_AE3XX_TIMER=y
CONFIG_NDS32=y
CONFIG_TARGET_ADP_AG101P=y
+CONFIG_DEFAULT_DEVICE_TREE="ag101p"
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="NDS32 # "
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_BAUDRATE=38400
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_AG101P_TIMER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_RSA=y
-CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_AR933X_UART=y
CONFIG_DM_SPI=y
CONFIG_ATH79_SPI=y
+CONFIG_LZMA=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_ATH79_SPI=y
+CONFIG_LZMA=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARCH_MX6=y
CONFIG_TARGET_APALIS_IMX6=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARCH_MX6=y
CONFIG_TARGET_APALIS_IMX6=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=2048"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_PROMPT="BIOS> "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="URMEL > "
CONFIG_CMD_I2C=y
+CONFIG_CMD_FPGA_LOADMK=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
+CONFIG_CMD_JFFS2=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_MII=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_MMC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_HASH=y
CONFIG_CMD_FAT=y
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_BSP=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_BSP=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_PPC=y
CONFIG_MPC5xxx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_CANMB=y
CONFIG_BOOTDELAY=5
CONFIG_CMD_ASKENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_BSP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_EEPROM_LAYOUT=y
+CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_BSP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_EEPROM_LAYOUT=y
+CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_EEPROM_LAYOUT=y
+CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_SYS_PROMPT="CM-T3517 # "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_EEPROM_LAYOUT=y
+CONFIG_EEPROM_LAYOUT_HELP_STRING="v1, v2, v3"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_SYS_PROMPT="CM-T3x # "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_EEPROM_LAYOUT=y
+CONFIG_EEPROM_LAYOUT_HELP_STRING="v1, v2, v3"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_EEPROM_LAYOUT=y
+CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_EEPROM_LAYOUT=y
+CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_ARCH_MX6=y
CONFIG_TARGET_COLIBRI_IMX6=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256"
CONFIG_BOOTDELAY=1
# CONFIG_CONSOLE_MUX is not set
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_TPM=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_TPM=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_PPC=y
CONFIG_IDENT_STRING=" controlcenterd trailblazer 0.01"
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP"
CONFIG_BOOTDELAY=-2
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_TPM=y
+# CONFIG_CMD_IRQ is not set
CONFIG_DOS_PARTITION=y
CONFIG_DM=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
+CONFIG_SHA1=y
CONFIG_PPC=y
CONFIG_IDENT_STRING=" controlcenterd trailblazer 0.01"
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_CONTROLCENTERD=y
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH"
CONFIG_BOOTDELAY=-2
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_TPM=y
+# CONFIG_CMD_IRQ is not set
CONFIG_DOS_PARTITION=y
CONFIG_DM=y
# CONFIG_PCI is not set
CONFIG_SYS_NS16550=y
CONFIG_TPM_AUTH_SESSIONS=y
CONFIG_TPM=y
+CONFIG_SHA1=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_ELF is not set
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="d2v2> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_SAVEENV is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_SAVEENV is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_SAVEENV is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_MMC_OMAP_HS=y
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR=" "
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_4xx=y
CONFIG_TARGET_DLVISION_10G=y
CONFIG_FIT=y
+# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_4xx=y
CONFIG_TARGET_DLVISION=y
CONFIG_FIT=y
+# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_TARGET_DS109=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ECO5-PK # "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
# CONFIG_DOS_PARTITION is not set
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="EDMiniV2> "
+CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_BSP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="GoFlexHome> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_GW_VENTANA=y
+CONFIG_CMD_EECONFIG=y
+CONFIG_CMD_GSC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
+CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_GW_VENTANA=y
+CONFIG_CMD_EECONFIG=y
+CONFIG_CMD_GSC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
+CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_GW_VENTANA=y
+CONFIG_CMD_EECONFIG=y
+CONFIG_CMD_GSC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_VIDEO=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
+CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_ARM=y
CONFIG_TARGET_H2200=y
CONFIG_FIT=y
+# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_IDENT_STRING=" hrcon 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
+CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_FPGAD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_IDENT_STRING=" hrcon dh 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_HRCON=y
+CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_FPGAD=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_SYS_PROMPT="ib62x0 => "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
CONFIG_AUTOBOOT_DELAY_STR="ids"
+CONFIG_CMD_ENV_FLAGS=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_TARGET_IMX31_PHYCORE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="uboot> "
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_TARGET_INKA4X0=y
CONFIG_BOOTDELAY=1
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MAC_PARTITION=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_4xx=y
CONFIG_TARGET_IO=y
CONFIG_FIT=y
+# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_4xx=y
CONFIG_TARGET_IOCON=y
CONFIG_FIT=y
+# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_LOOPW=y
+CONFIG_CMD_FPGAD=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DIAG=y
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_LOOPW=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_BMP=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_IRQ=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_4xx=y
CONFIG_TARGET_KATMAI=y
CONFIG_CMD_CHIP_CONFIG=y
+CONFIG_CMD_ECCTEST=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_KMP204X=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
+CONFIG_CMD_JFFS2=y
+# CONFIG_CMD_IRQ is not set
CONFIG_CMD_UBI=y
CONFIG_DOS_PARTITION=y
# CONFIG_MMC is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_KM8360=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_KM8360=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_KMP204X=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
+CONFIG_CMD_JFFS2=y
+# CONFIG_CMD_IRQ is not set
CONFIG_CMD_UBI=y
CONFIG_DOS_PARTITION=y
# CONFIG_MMC is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_PPC=y
CONFIG_MPC83xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="malta # "
# CONFIG_AUTOBOOT is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="maltael # "
# CONFIG_AUTOBOOT is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="malta # "
# CONFIG_AUTOBOOT is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="maltael # "
# CONFIG_AUTOBOOT is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL"
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL"
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_PPC=y
CONFIG_MPC8260=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_KM82XX=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC8260=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_KM82XX=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_PPC=y
CONFIG_MPC5xxx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_MOTIONPRO=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_VERSION_VARIABLE=y
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_BEDBUG=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
+CONFIG_CMD_JFFS2=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mt_ventoux => "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
+CONFIG_CMD_FPGA_LOADMK=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_PPC=y
CONFIG_MPC5xxx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_MUNICES=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_FUSE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set
+CONFIG_CMD_HDMIDETECT=y
CONFIG_VIDEO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="nas220> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_4xx=y
CONFIG_TARGET_NEO=y
CONFIG_FIT=y
+# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
# CONFIG_CMD_NFS is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="2big2> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_NITROGEN6X=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_VIDEO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_SYS_PROMPT="nsa310s => "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SYS_PROMPT="OMAP Logic # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_EEPROM is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_USB is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_EEPROM is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
+CONFIG_CMD_JFFS2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
+CONFIG_CMD_JFFS2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_BOOTDELAY=3
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
+CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_JFFS2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_JFFS2=y
# CONFIG_MMC is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
# CONFIG_MMC is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_QEMU_PPCE500=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
# CONFIG_MMC is not set
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="qemu-mips64 # "
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_LZMA=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="qemu-mips64el # "
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_LZMA=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="qemu-mips # "
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_LZMA=y
CONFIG_BOOTDELAY=10
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="qemu-mipsel # "
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
+CONFIG_LZMA=y
CONFIG_SH=y
CONFIG_TARGET_R2DPLUS=y
CONFIG_BOOTDELAY=-1
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_ENV_CALLBACK=y
+CONFIG_CMD_ENV_FLAGS=y
CONFIG_CMD_MD5SUM=y
CONFIG_LOOPW=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_DEMO=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_GPT=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_ETHSW=y
CONFIG_CMD_BMP=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_ENV_CALLBACK=y
+CONFIG_CMD_ENV_FLAGS=y
CONFIG_CMD_MD5SUM=y
CONFIG_LOOPW=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_DEMO=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_GPT=y
CONFIG_CMD_PART=y
CONFIG_CMD_SF=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_ENV_CALLBACK=y
+CONFIG_CMD_ENV_FLAGS=y
CONFIG_CMD_MD5SUM=y
CONFIG_LOOPW=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_DEMO=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_GPT=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SBC8548=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+# CONFIG_CMD_HASH is not set
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
# CONFIG_PCI is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_MISC is not set
+CONFIG_CMD_JFFS2=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_IDE=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
+CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_PPC=y
CONFIG_VIDEO=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SOCRATES=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_IDENT_STRING=" strider con 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_FPGAD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_IDENT_STRING=" strider con dp 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_FPGAD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_IDENT_STRING=" strider cpu 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_FPGAD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_IDENT_STRING=" strider cpu dp 0.01"
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
+CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_FPGAD=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_SUVD3=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_4xx=y
CONFIG_TARGET_T3CORP=y
CONFIG_CMD_CHIP_CONFIG=y
+CONFIG_CMD_ECCTEST=y
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_TARGET_TBS2910=y
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_PRE_CON_BUF_ADDR=0x7c000000
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
+CONFIG_LZMA=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068"
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_PPC=y
CONFIG_MPC83xx=y
+CONFIG_CMD_IMMAP=y
CONFIG_TARGET_TUXX1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="twister => "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
+CONFIG_CMD_FUSE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_TARGET_V38B=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_CMD_IDE=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
+CONFIG_CMD_IRQ=y
CONFIG_MAC_PARTITION=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="VCT# "
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_BOOTDELAY=5
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_FAT=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
CONFIG_SYS_NS16550=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_CMD_HDMIDETECT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
# CONFIG_CONSOLE_MUX is not set
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
CONFIG_HUSH_PARSER=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_CMD_HD44760=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_I2C=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_BMP=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
+CONFIG_CMD_JFFS2=y
CONFIG_MAC_PARTITION=y
CONFIG_DOS_PARTITION=y
# CONFIG_MMC is not set
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
+CONFIG_CMD_FPGA_LOADMK=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_OF_EMBED=y
# CONFIG_MMC is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_JFFS2=y
CONFIG_CMD_DIAG=y
CONFIG_OF_EMBED=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
+CONFIG_CMD_JFFS2=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
+CONFIG_CMD_JFFS2=y
+CONFIG_CMD_IRQ=y
+CONFIG_DS4510=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_XPEDITE520X=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
+CONFIG_CMD_JFFS2=y
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_XPEDITE537X=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
+CONFIG_CMD_JFFS2=y
+# CONFIG_CMD_IRQ is not set
CONFIG_SYS_FSL_DDR2=y
+CONFIG_DS4510=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_PPC=y
CONFIG_MPC85xx=y
+# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_XPEDITE550X=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_CMD_PING=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DATE=y
+# CONFIG_CMD_HASH is not set
+CONFIG_CMD_JFFS2=y
+# CONFIG_CMD_IRQ is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_SYS_NS16550=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
CONFIG_LOOPW=y
CONFIG_CMD_I2C=y
CONFIG_CMD_DHCP=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_LCD=y
+CONFIG_LZMA=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
ls - list files in a directory
chpart - change active partition
+If you do now need the commands, you can enable the filesystem separately
+with CONFIG_FS_JFFS2 and call the jffs2 functions yourself.
+
If you boot from a partition which is mounted writable, and you
update your boot environment by replacing single files on that
partition, you should also define CONFIG_SYS_JFFS2_SORT_FRAGMENTS. Scanning
+ ---------------> image file --------------------> bootm
image data file(s)
+SPL usage
+---------
+
+The SPL can make use of the new image format as well, this traditionally
+is used to ship multiple device tree files within one image. Code in the SPL
+will choose the one matching the current board and append this to the
+U-Boot proper binary to be automatically used up by it.
+Aside from U-Boot proper and one device tree blob the SPL can load multiple,
+arbitrary image files as well. These binaries should be specified in their
+own subnode under the /images node, which should then be referenced from one or
+multiple /configurations subnodes. The required images must be enumerated in
+the "loadables" property as a list of strings.
+
+If a platform specific image source file (.its) is shipped with the U-Boot
+source, it can be specified using the CONFIG_SPL_FIT_SOURCE Kconfig symbol.
+In this case it will be automatically used by U-Boot's Makefile to generate
+the image.
+If a static source file is not flexible enough, CONFIG_SPL_FIT_GENERATOR
+can point to a script which generates this image source file during
+the build process. It gets passed a list of device tree files (taken from the
+CONFIG_OF_LIST symbol).
Example 1 -- old-style (non-FDT) kernel booting
-----------------------------------------------
--- /dev/null
+/dts-v1/;
+
+/*
+ * (Bogus) example FIT image description file demonstrating the usage
+ * of multiple images loaded by the SPL.
+ * Several binaries will be loaded at their respective load addresses.
+ * Finally the one image specifying an entry point will be entered by the SPL.
+ */
+
+/ {
+ description = "multiple firmware blobs and U-Boot, loaded by SPL";
+ #address-cells = <0x1>;
+
+ images {
+
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <0x4a000000>;
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x18000>;
+ entry = <0x18000>;
+ };
+
+ mgmt-firmware {
+ description = "arisc management processor firmware";
+ type = "firmware";
+ arch = "or1k";
+ compression = "none";
+ load = <0x40000>;
+ };
+
+ fdt@1 {
+ description = "Pine64+ DT";
+ type = "flat_dt";
+ compression = "none";
+ load = <0x4fa00000>;
+ arch = "arm64";
+ };
+
+ fdt@2 {
+ description = "Pine64 DT";
+ type = "flat_dt";
+ compression = "none";
+ load = <0x4fa00000>;
+ arch = "arm64";
+ };
+
+ kernel {
+ description = "4.7-rc5 kernel";
+ type = "kernel";
+ compression = "none";
+ load = <0x40080000>;
+ arch = "arm64";
+ };
+
+ initrd {
+ description = "Debian installer initrd";
+ type = "ramdisk";
+ compression = "none";
+ load = <0x4fe00000>;
+ arch = "arm64";
+ };
+ };
+
+ configurations {
+ default = "config@1";
+
+ config@1 {
+ description = "sun50i-a64-pine64-plus";
+ loadables = "uboot", "atf", "kernel", "initrd";
+ fdt = "fdt@1";
+ };
+
+ config@2 {
+ description = "sun50i-a64-pine64";
+ loadables = "uboot", "atf", "mgmt-firmware";
+ fdt = "fdt@2";
+ };
+ };
+};
source "drivers/gpio/Kconfig"
-source "drivers/hwmon/Kconfig"
-
source "drivers/i2c/Kconfig"
source "drivers/input/Kconfig"
obj-y += crypto/
obj-y += firmware/
obj-$(CONFIG_FPGA) += fpga/
-obj-y += hwmon/
obj-y += misc/
obj-$(CONFIG_MMC) += mmc/
obj-y += pcmcia/
obj-y += sysreset/
obj-y += timer/
obj-y += tpm/
-obj-y += twserial/
obj-y += video/
obj-y += watchdog/
obj-$(CONFIG_QE) += qe/
Synopsys DWC AHCI module.
endmenu
+
+config IDE
+ bool "Support IDE controllers"
+ help
+ Enables support for IDE (Integrated Drive Electronics) hard drives.
+ This allows access to raw blocks and filesystems on an IDE drive
+ from U-Boot. See also CMD_IDE which provides an 'ide' command for
+ performing various IDE operations.
obj-$(CONFIG_SCSI_AHCI) += ahci.o
obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
+obj-$(CONFIG_IDE) += ide.o
obj-$(CONFIG_IDE_FTIDE020) += ftide020.o
obj-$(CONFIG_LIBATA) += libata.o
obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
--- /dev/null
+/*
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ata.h>
+#include <dm.h>
+#include <ide.h>
+#include <watchdog.h>
+#include <asm/io.h>
+
+#ifdef __PPC__
+# define EIEIO __asm__ volatile ("eieio")
+# define SYNC __asm__ volatile ("sync")
+#else
+# define EIEIO /* nothing */
+# define SYNC /* nothing */
+#endif
+
+/* Current offset for IDE0 / IDE1 bus access */
+ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS] = {
+#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
+ CONFIG_SYS_ATA_IDE0_OFFSET,
+#endif
+#if defined(CONFIG_SYS_ATA_IDE1_OFFSET) && (CONFIG_SYS_IDE_MAXBUS > 1)
+ CONFIG_SYS_ATA_IDE1_OFFSET,
+#endif
+};
+
+static int ide_bus_ok[CONFIG_SYS_IDE_MAXBUS];
+
+struct blk_desc ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
+
+#define IDE_TIME_OUT 2000 /* 2 sec timeout */
+
+#define ATAPI_TIME_OUT 7000 /* 7 sec timeout (5 sec seems to work...) */
+
+#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
+
+#ifndef CONFIG_SYS_ATA_PORT_ADDR
+#define CONFIG_SYS_ATA_PORT_ADDR(port) (port)
+#endif
+
+#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */
+# define DEVICE_LED(x) 0
+# define LED_IDE1 1
+# define LED_IDE2 2
+#endif
+
+#ifdef CONFIG_IDE_RESET
+extern void ide_set_reset(int idereset);
+
+static void ide_reset(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; ++i)
+ ide_bus_ok[i] = 0;
+ for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i)
+ ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+
+ ide_set_reset(1); /* assert reset */
+
+ /* the reset signal shall be asserted for et least 25 us */
+ udelay(25);
+
+ WATCHDOG_RESET();
+
+ /* de-assert RESET signal */
+ ide_set_reset(0);
+
+ /* wait 250 ms */
+ for (i = 0; i < 250; ++i)
+ udelay(1000);
+}
+#else
+#define ide_reset() /* dummy */
+#endif /* CONFIG_IDE_RESET */
+
+/*
+ * Wait until Busy bit is off, or timeout (in ms)
+ * Return last status
+ */
+static uchar ide_wait(int dev, ulong t)
+{
+ ulong delay = 10 * t; /* poll every 100 us */
+ uchar c;
+
+ while ((c = ide_inb(dev, ATA_STATUS)) & ATA_STAT_BUSY) {
+ udelay(100);
+ if (delay-- == 0)
+ break;
+ }
+ return c;
+}
+
+/*
+ * copy src to dest, skipping leading and trailing blanks and null
+ * terminate the string
+ * "len" is the size of available memory including the terminating '\0'
+ */
+static void ident_cpy(unsigned char *dst, unsigned char *src,
+ unsigned int len)
+{
+ unsigned char *end, *last;
+
+ last = dst;
+ end = src + len - 1;
+
+ /* reserve space for '\0' */
+ if (len < 2)
+ goto OUT;
+
+ /* skip leading white space */
+ while ((*src) && (src < end) && (*src == ' '))
+ ++src;
+
+ /* copy string, omitting trailing white space */
+ while ((*src) && (src < end)) {
+ *dst++ = *src;
+ if (*src++ != ' ')
+ last = dst;
+ }
+OUT:
+ *last = '\0';
+}
+
+#ifdef CONFIG_ATAPI
+/****************************************************************************
+ * ATAPI Support
+ */
+
+#if defined(CONFIG_IDE_SWAP_IO)
+/* since ATAPI may use commands with not 4 bytes alligned length
+ * we have our own transfer functions, 2 bytes alligned */
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *)sect_buf;
+
+ debug("in output data shorts base for read is %lx\n",
+ (unsigned long) pbuf);
+
+ while (shorts--) {
+ EIEIO;
+ *pbuf = *dbuf++;
+ }
+}
+
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *)sect_buf;
+
+ debug("in input data shorts base for read is %lx\n",
+ (unsigned long) pbuf);
+
+ while (shorts--) {
+ EIEIO;
+ *dbuf++ = *pbuf;
+ }
+}
+
+#else /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
+}
+
+__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
+}
+
+#endif /* CONFIG_IDE_SWAP_IO */
+
+/*
+ * Wait until (Status & mask) == res, or timeout (in ms)
+ * Return last status
+ * This is used since some ATAPI CD ROMs clears their Busy Bit first
+ * and then they set their DRQ Bit
+ */
+static uchar atapi_wait_mask(int dev, ulong t, uchar mask, uchar res)
+{
+ ulong delay = 10 * t; /* poll every 100 us */
+ uchar c;
+
+ /* prevents to read the status before valid */
+ c = ide_inb(dev, ATA_DEV_CTL);
+
+ while (((c = ide_inb(dev, ATA_STATUS)) & mask) != res) {
+ /* break if error occurs (doesn't make sense to wait more) */
+ if ((c & ATA_STAT_ERR) == ATA_STAT_ERR)
+ break;
+ udelay(100);
+ if (delay-- == 0)
+ break;
+ }
+ return c;
+}
+
+/*
+ * issue an atapi command
+ */
+unsigned char atapi_issue(int device, unsigned char *ccb, int ccblen,
+ unsigned char *buffer, int buflen)
+{
+ unsigned char c, err, mask, res;
+ int n;
+
+ ide_led(DEVICE_LED(device), 1); /* LED on */
+
+ /* Select device
+ */
+ mask = ATA_STAT_BUSY | ATA_STAT_DRQ;
+ res = 0;
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+ if ((c & mask) != res) {
+ printf("ATAPI_ISSUE: device %d not ready status %X\n", device,
+ c);
+ err = 0xFF;
+ goto AI_OUT;
+ }
+ /* write taskfile */
+ ide_outb(device, ATA_ERROR_REG, 0); /* no DMA, no overlaped */
+ ide_outb(device, ATA_SECT_CNT, 0);
+ ide_outb(device, ATA_SECT_NUM, 0);
+ ide_outb(device, ATA_CYL_LOW, (unsigned char) (buflen & 0xFF));
+ ide_outb(device, ATA_CYL_HIGH,
+ (unsigned char) ((buflen >> 8) & 0xFF));
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+
+ ide_outb(device, ATA_COMMAND, ATAPI_CMD_PACKET);
+ udelay(50);
+
+ mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
+ res = ATA_STAT_DRQ;
+ c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+
+ if ((c & mask) != res) { /* DRQ must be 1, BSY 0 */
+ printf("ATAPI_ISSUE: Error (no IRQ) before sending ccb dev %d status 0x%02x\n",
+ device, c);
+ err = 0xFF;
+ goto AI_OUT;
+ }
+
+ /* write command block */
+ ide_output_data_shorts(device, (unsigned short *)ccb, ccblen / 2);
+
+ /* ATAPI Command written wait for completition */
+ udelay(5000); /* device must set bsy */
+
+ mask = ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR;
+ /*
+ * if no data wait for DRQ = 0 BSY = 0
+ * if data wait for DRQ = 1 BSY = 0
+ */
+ res = 0;
+ if (buflen)
+ res = ATA_STAT_DRQ;
+ c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+ if ((c & mask) != res) {
+ if (c & ATA_STAT_ERR) {
+ err = (ide_inb(device, ATA_ERROR_REG)) >> 4;
+ debug("atapi_issue 1 returned sense key %X status %02X\n",
+ err, c);
+ } else {
+ printf("ATAPI_ISSUE: (no DRQ) after sending ccb (%x) status 0x%02x\n",
+ ccb[0], c);
+ err = 0xFF;
+ }
+ goto AI_OUT;
+ }
+ n = ide_inb(device, ATA_CYL_HIGH);
+ n <<= 8;
+ n += ide_inb(device, ATA_CYL_LOW);
+ if (n > buflen) {
+ printf("ERROR, transfer bytes %d requested only %d\n", n,
+ buflen);
+ err = 0xff;
+ goto AI_OUT;
+ }
+ if ((n == 0) && (buflen < 0)) {
+ printf("ERROR, transfer bytes %d requested %d\n", n, buflen);
+ err = 0xff;
+ goto AI_OUT;
+ }
+ if (n != buflen) {
+ debug("WARNING, transfer bytes %d not equal with requested %d\n",
+ n, buflen);
+ }
+ if (n != 0) { /* data transfer */
+ debug("ATAPI_ISSUE: %d Bytes to transfer\n", n);
+ /* we transfer shorts */
+ n >>= 1;
+ /* ok now decide if it is an in or output */
+ if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
+ debug("Write to device\n");
+ ide_output_data_shorts(device, (unsigned short *)buffer,
+ n);
+ } else {
+ debug("Read from device @ %p shorts %d\n", buffer, n);
+ ide_input_data_shorts(device, (unsigned short *)buffer,
+ n);
+ }
+ }
+ udelay(5000); /* seems that some CD ROMs need this... */
+ mask = ATA_STAT_BUSY | ATA_STAT_ERR;
+ res = 0;
+ c = atapi_wait_mask(device, ATAPI_TIME_OUT, mask, res);
+ if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
+ err = (ide_inb(device, ATA_ERROR_REG) >> 4);
+ debug("atapi_issue 2 returned sense key %X status %X\n", err,
+ c);
+ } else {
+ err = 0;
+ }
+AI_OUT:
+ ide_led(DEVICE_LED(device), 0); /* LED off */
+ return err;
+}
+
+/*
+ * sending the command to atapi_issue. If an status other than good
+ * returns, an request_sense will be issued
+ */
+
+#define ATAPI_DRIVE_NOT_READY 100
+#define ATAPI_UNIT_ATTN 10
+
+unsigned char atapi_issue_autoreq(int device,
+ unsigned char *ccb,
+ int ccblen,
+ unsigned char *buffer, int buflen)
+{
+ unsigned char sense_data[18], sense_ccb[12];
+ unsigned char res, key, asc, ascq;
+ int notready, unitattn;
+
+ unitattn = ATAPI_UNIT_ATTN;
+ notready = ATAPI_DRIVE_NOT_READY;
+
+retry:
+ res = atapi_issue(device, ccb, ccblen, buffer, buflen);
+ if (res == 0)
+ return 0; /* Ok */
+
+ if (res == 0xFF)
+ return 0xFF; /* error */
+
+ debug("(auto_req)atapi_issue returned sense key %X\n", res);
+
+ memset(sense_ccb, 0, sizeof(sense_ccb));
+ memset(sense_data, 0, sizeof(sense_data));
+ sense_ccb[0] = ATAPI_CMD_REQ_SENSE;
+ sense_ccb[4] = 18; /* allocation Length */
+
+ res = atapi_issue(device, sense_ccb, 12, sense_data, 18);
+ key = (sense_data[2] & 0xF);
+ asc = (sense_data[12]);
+ ascq = (sense_data[13]);
+
+ debug("ATAPI_CMD_REQ_SENSE returned %x\n", res);
+ debug(" Sense page: %02X key %02X ASC %02X ASCQ %02X\n",
+ sense_data[0], key, asc, ascq);
+
+ if ((key == 0))
+ return 0; /* ok device ready */
+
+ if ((key == 6) || (asc == 0x29) || (asc == 0x28)) { /* Unit Attention */
+ if (unitattn-- > 0) {
+ udelay(200 * 1000);
+ goto retry;
+ }
+ printf("Unit Attention, tried %d\n", ATAPI_UNIT_ATTN);
+ goto error;
+ }
+ if ((asc == 0x4) && (ascq == 0x1)) {
+ /* not ready, but will be ready soon */
+ if (notready-- > 0) {
+ udelay(200 * 1000);
+ goto retry;
+ }
+ printf("Drive not ready, tried %d times\n",
+ ATAPI_DRIVE_NOT_READY);
+ goto error;
+ }
+ if (asc == 0x3a) {
+ debug("Media not present\n");
+ goto error;
+ }
+
+ printf("ERROR: Unknown Sense key %02X ASC %02X ASCQ %02X\n", key, asc,
+ ascq);
+error:
+ debug("ERROR Sense key %02X ASC %02X ASCQ %02X\n", key, asc, ascq);
+ return 0xFF;
+}
+
+/*
+ * atapi_read:
+ * we transfer only one block per command, since the multiple DRQ per
+ * command is not yet implemented
+ */
+#define ATAPI_READ_MAX_BYTES 2048 /* we read max 2kbytes */
+#define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
+#define ATAPI_READ_MAX_BLOCK (ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE)
+
+ulong atapi_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+{
+ int device = block_dev->devnum;
+ ulong n = 0;
+ unsigned char ccb[12]; /* Command descriptor block */
+ ulong cnt;
+
+ debug("atapi_read dev %d start " LBAF " blocks " LBAF
+ " buffer at %lX\n", device, blknr, blkcnt, (ulong) buffer);
+
+ do {
+ if (blkcnt > ATAPI_READ_MAX_BLOCK)
+ cnt = ATAPI_READ_MAX_BLOCK;
+ else
+ cnt = blkcnt;
+
+ ccb[0] = ATAPI_CMD_READ_12;
+ ccb[1] = 0; /* reserved */
+ ccb[2] = (unsigned char) (blknr >> 24) & 0xFF; /* MSB Block */
+ ccb[3] = (unsigned char) (blknr >> 16) & 0xFF; /* */
+ ccb[4] = (unsigned char) (blknr >> 8) & 0xFF;
+ ccb[5] = (unsigned char) blknr & 0xFF; /* LSB Block */
+ ccb[6] = (unsigned char) (cnt >> 24) & 0xFF; /* MSB Block cnt */
+ ccb[7] = (unsigned char) (cnt >> 16) & 0xFF;
+ ccb[8] = (unsigned char) (cnt >> 8) & 0xFF;
+ ccb[9] = (unsigned char) cnt & 0xFF; /* LSB Block */
+ ccb[10] = 0; /* reserved */
+ ccb[11] = 0; /* reserved */
+
+ if (atapi_issue_autoreq(device, ccb, 12,
+ (unsigned char *)buffer,
+ cnt * ATAPI_READ_BLOCK_SIZE)
+ == 0xFF) {
+ return n;
+ }
+ n += cnt;
+ blkcnt -= cnt;
+ blknr += cnt;
+ buffer += (cnt * ATAPI_READ_BLOCK_SIZE);
+ } while (blkcnt > 0);
+ return n;
+}
+
+static void atapi_inquiry(struct blk_desc *dev_desc)
+{
+ unsigned char ccb[12]; /* Command descriptor block */
+ unsigned char iobuf[64]; /* temp buf */
+ unsigned char c;
+ int device;
+
+ device = dev_desc->devnum;
+ dev_desc->type = DEV_TYPE_UNKNOWN; /* not yet valid */
+ dev_desc->block_read = atapi_read;
+
+ memset(ccb, 0, sizeof(ccb));
+ memset(iobuf, 0, sizeof(iobuf));
+
+ ccb[0] = ATAPI_CMD_INQUIRY;
+ ccb[4] = 40; /* allocation Legnth */
+ c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 40);
+
+ debug("ATAPI_CMD_INQUIRY returned %x\n", c);
+ if (c != 0)
+ return;
+
+ /* copy device ident strings */
+ ident_cpy((unsigned char *)dev_desc->vendor, &iobuf[8], 8);
+ ident_cpy((unsigned char *)dev_desc->product, &iobuf[16], 16);
+ ident_cpy((unsigned char *)dev_desc->revision, &iobuf[32], 5);
+
+ dev_desc->lun = 0;
+ dev_desc->lba = 0;
+ dev_desc->blksz = 0;
+ dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz));
+ dev_desc->type = iobuf[0] & 0x1f;
+
+ if ((iobuf[1] & 0x80) == 0x80)
+ dev_desc->removable = 1;
+ else
+ dev_desc->removable = 0;
+
+ memset(ccb, 0, sizeof(ccb));
+ memset(iobuf, 0, sizeof(iobuf));
+ ccb[0] = ATAPI_CMD_START_STOP;
+ ccb[4] = 0x03; /* start */
+
+ c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+
+ debug("ATAPI_CMD_START_STOP returned %x\n", c);
+ if (c != 0)
+ return;
+
+ memset(ccb, 0, sizeof(ccb));
+ memset(iobuf, 0, sizeof(iobuf));
+ c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 0);
+
+ debug("ATAPI_CMD_UNIT_TEST_READY returned %x\n", c);
+ if (c != 0)
+ return;
+
+ memset(ccb, 0, sizeof(ccb));
+ memset(iobuf, 0, sizeof(iobuf));
+ ccb[0] = ATAPI_CMD_READ_CAP;
+ c = atapi_issue_autoreq(device, ccb, 12, (unsigned char *)iobuf, 8);
+ debug("ATAPI_CMD_READ_CAP returned %x\n", c);
+ if (c != 0)
+ return;
+
+ debug("Read Cap: LBA %02X%02X%02X%02X blksize %02X%02X%02X%02X\n",
+ iobuf[0], iobuf[1], iobuf[2], iobuf[3],
+ iobuf[4], iobuf[5], iobuf[6], iobuf[7]);
+
+ dev_desc->lba = ((unsigned long) iobuf[0] << 24) +
+ ((unsigned long) iobuf[1] << 16) +
+ ((unsigned long) iobuf[2] << 8) + ((unsigned long) iobuf[3]);
+ dev_desc->blksz = ((unsigned long) iobuf[4] << 24) +
+ ((unsigned long) iobuf[5] << 16) +
+ ((unsigned long) iobuf[6] << 8) + ((unsigned long) iobuf[7]);
+ dev_desc->log2blksz = LOG2(dev_desc->blksz);
+#ifdef CONFIG_LBA48
+ /* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
+ dev_desc->lba48 = 0;
+#endif
+ return;
+}
+
+#endif /* CONFIG_ATAPI */
+
+static void ide_ident(struct blk_desc *dev_desc)
+{
+ unsigned char c;
+ hd_driveid_t iop;
+
+#ifdef CONFIG_ATAPI
+ int retries = 0;
+#endif
+ int device;
+
+ device = dev_desc->devnum;
+ printf(" Device %d: ", device);
+
+ ide_led(DEVICE_LED(device), 1); /* LED on */
+ /* Select device
+ */
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ dev_desc->if_type = IF_TYPE_IDE;
+#ifdef CONFIG_ATAPI
+
+ retries = 0;
+
+ /* Warning: This will be tricky to read */
+ while (retries <= 1) {
+ /* check signature */
+ if ((ide_inb(device, ATA_SECT_CNT) == 0x01) &&
+ (ide_inb(device, ATA_SECT_NUM) == 0x01) &&
+ (ide_inb(device, ATA_CYL_LOW) == 0x14) &&
+ (ide_inb(device, ATA_CYL_HIGH) == 0xEB)) {
+ /* ATAPI Signature found */
+ dev_desc->if_type = IF_TYPE_ATAPI;
+ /*
+ * Start Ident Command
+ */
+ ide_outb(device, ATA_COMMAND, ATAPI_CMD_IDENT);
+ /*
+ * Wait for completion - ATAPI devices need more time
+ * to become ready
+ */
+ c = ide_wait(device, ATAPI_TIME_OUT);
+ } else
+#endif
+ {
+ /*
+ * Start Ident Command
+ */
+ ide_outb(device, ATA_COMMAND, ATA_CMD_IDENT);
+
+ /*
+ * Wait for completion
+ */
+ c = ide_wait(device, IDE_TIME_OUT);
+ }
+ ide_led(DEVICE_LED(device), 0); /* LED off */
+
+ if (((c & ATA_STAT_DRQ) == 0) ||
+ ((c & (ATA_STAT_FAULT | ATA_STAT_ERR)) != 0)) {
+#ifdef CONFIG_ATAPI
+ {
+ /*
+ * Need to soft reset the device
+ * in case it's an ATAPI...
+ */
+ debug("Retrying...\n");
+ ide_outb(device, ATA_DEV_HD,
+ ATA_LBA | ATA_DEVICE(device));
+ udelay(100000);
+ ide_outb(device, ATA_COMMAND, 0x08);
+ udelay(500000); /* 500 ms */
+ }
+ /*
+ * Select device
+ */
+ ide_outb(device, ATA_DEV_HD,
+ ATA_LBA | ATA_DEVICE(device));
+ retries++;
+#else
+ return;
+#endif
+ }
+#ifdef CONFIG_ATAPI
+ else
+ break;
+ } /* see above - ugly to read */
+
+ if (retries == 2) /* Not found */
+ return;
+#endif
+
+ ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
+
+ ident_cpy((unsigned char *)dev_desc->revision, iop.fw_rev,
+ sizeof(dev_desc->revision));
+ ident_cpy((unsigned char *)dev_desc->vendor, iop.model,
+ sizeof(dev_desc->vendor));
+ ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
+ sizeof(dev_desc->product));
+#ifdef __LITTLE_ENDIAN
+ /*
+ * firmware revision, model, and serial number have Big Endian Byte
+ * order in Word. Convert all three to little endian.
+ *
+ * See CF+ and CompactFlash Specification Revision 2.0:
+ * 6.2.1.6: Identify Drive, Table 39 for more details
+ */
+
+ strswab(dev_desc->revision);
+ strswab(dev_desc->vendor);
+ strswab(dev_desc->product);
+#endif /* __LITTLE_ENDIAN */
+
+ if ((iop.config & 0x0080) == 0x0080)
+ dev_desc->removable = 1;
+ else
+ dev_desc->removable = 0;
+
+#ifdef CONFIG_ATAPI
+ if (dev_desc->if_type == IF_TYPE_ATAPI) {
+ atapi_inquiry(dev_desc);
+ return;
+ }
+#endif /* CONFIG_ATAPI */
+
+#ifdef __BIG_ENDIAN
+ /* swap shorts */
+ dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16);
+#else /* ! __BIG_ENDIAN */
+ /*
+ * do not swap shorts on little endian
+ *
+ * See CF+ and CompactFlash Specification Revision 2.0:
+ * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
+ */
+ dev_desc->lba = iop.lba_capacity;
+#endif /* __BIG_ENDIAN */
+
+#ifdef CONFIG_LBA48
+ if (iop.command_set_2 & 0x0400) { /* LBA 48 support */
+ dev_desc->lba48 = 1;
+ dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] |
+ ((unsigned long long) iop.lba48_capacity[1] << 16) |
+ ((unsigned long long) iop.lba48_capacity[2] << 32) |
+ ((unsigned long long) iop.lba48_capacity[3] << 48);
+ } else {
+ dev_desc->lba48 = 0;
+ }
+#endif /* CONFIG_LBA48 */
+ /* assuming HD */
+ dev_desc->type = DEV_TYPE_HARDDISK;
+ dev_desc->blksz = ATA_BLOCKSIZE;
+ dev_desc->log2blksz = LOG2(dev_desc->blksz);
+ dev_desc->lun = 0; /* just to fill something in... */
+
+#if 0 /* only used to test the powersaving mode,
+ * if enabled, the drive goes after 5 sec
+ * in standby mode */
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ c = ide_wait(device, IDE_TIME_OUT);
+ ide_outb(device, ATA_SECT_CNT, 1);
+ ide_outb(device, ATA_LBA_LOW, 0);
+ ide_outb(device, ATA_LBA_MID, 0);
+ ide_outb(device, ATA_LBA_HIGH, 0);
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ ide_outb(device, ATA_COMMAND, 0xe3);
+ udelay(50);
+ c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
+#endif
+}
+
+__weak void ide_led(uchar led, uchar status)
+{
+#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
+ static uchar led_buffer; /* Buffer for current LED status */
+
+ uchar *led_port = LED_PORT;
+
+ if (status) /* switch LED on */
+ led_buffer |= led;
+ else /* switch LED off */
+ led_buffer &= ~led;
+
+ *led_port = led_buffer;
+#endif
+}
+
+__weak void ide_outb(int dev, int port, unsigned char val)
+{
+ debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
+ dev, port, val,
+ (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+
+#if defined(CONFIG_IDE_AHB)
+ if (port) {
+ /* write command */
+ ide_write_register(dev, port, val);
+ } else {
+ /* write data */
+ outb(val, (ATA_CURR_BASE(dev)));
+ }
+#else
+ outb(val, (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+#endif
+}
+
+__weak unsigned char ide_inb(int dev, int port)
+{
+ uchar val;
+
+#if defined(CONFIG_IDE_AHB)
+ val = ide_read_register(dev, port);
+#else
+ val = inb((ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)));
+#endif
+
+ debug("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
+ dev, port,
+ (ATA_CURR_BASE(dev) + CONFIG_SYS_ATA_PORT_ADDR(port)), val);
+ return val;
+}
+
+void ide_init(void)
+{
+ unsigned char c;
+ int i, bus;
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+ extern int ide_devices_found; /* Initialized in check_ide_device() */
+#endif /* CONFIG_IDE_8xx_PCCARD */
+
+#ifdef CONFIG_IDE_PREINIT
+ WATCHDOG_RESET();
+
+ if (ide_preinit()) {
+ puts("ide_preinit failed\n");
+ return;
+ }
+#endif /* CONFIG_IDE_PREINIT */
+
+ WATCHDOG_RESET();
+
+ /*
+ * Reset the IDE just to be sure.
+ * Light LED's to show
+ */
+ ide_led((LED_IDE1 | LED_IDE2), 1); /* LED's on */
+
+ /* ATAPI Drives seems to need a proper IDE Reset */
+ ide_reset();
+
+#ifdef CONFIG_IDE_INIT_POSTRESET
+ WATCHDOG_RESET();
+
+ if (ide_init_postreset()) {
+ puts("ide_preinit_postreset failed\n");
+ return;
+ }
+#endif /* CONFIG_IDE_INIT_POSTRESET */
+
+ /*
+ * Wait for IDE to get ready.
+ * According to spec, this can take up to 31 seconds!
+ */
+ for (bus = 0; bus < CONFIG_SYS_IDE_MAXBUS; ++bus) {
+ int dev =
+ bus * (CONFIG_SYS_IDE_MAXDEVICE /
+ CONFIG_SYS_IDE_MAXBUS);
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+ /* Skip non-ide devices from probing */
+ if ((ide_devices_found & (1 << bus)) == 0) {
+ ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
+ continue;
+ }
+#endif
+ printf("Bus %d: ", bus);
+
+ ide_bus_ok[bus] = 0;
+
+ /* Select device
+ */
+ udelay(100000); /* 100 ms */
+ ide_outb(dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
+ udelay(100000); /* 100 ms */
+ i = 0;
+ do {
+ udelay(10000); /* 10 ms */
+
+ c = ide_inb(dev, ATA_STATUS);
+ i++;
+ if (i > (ATA_RESET_TIME * 100)) {
+ puts("** Timeout **\n");
+ /* LED's off */
+ ide_led((LED_IDE1 | LED_IDE2), 0);
+ return;
+ }
+ if ((i >= 100) && ((i % 100) == 0))
+ putc('.');
+
+ } while (c & ATA_STAT_BUSY);
+
+ if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
+ puts("not available ");
+ debug("Status = 0x%02X ", c);
+#ifndef CONFIG_ATAPI /* ATAPI Devices do not set DRDY */
+ } else if ((c & ATA_STAT_READY) == 0) {
+ puts("not available ");
+ debug("Status = 0x%02X ", c);
+#endif
+ } else {
+ puts("OK ");
+ ide_bus_ok[bus] = 1;
+ }
+ WATCHDOG_RESET();
+ }
+
+ putc('\n');
+
+ ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
+
+ for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
+ int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
+ ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
+ ide_dev_desc[i].if_type = IF_TYPE_IDE;
+ ide_dev_desc[i].devnum = i;
+ ide_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+ ide_dev_desc[i].blksz = 0;
+ ide_dev_desc[i].log2blksz =
+ LOG2_INVALID(typeof(ide_dev_desc[i].log2blksz));
+ ide_dev_desc[i].lba = 0;
+#ifndef CONFIG_BLK
+ ide_dev_desc[i].block_read = ide_read;
+ ide_dev_desc[i].block_write = ide_write;
+#endif
+ if (!ide_bus_ok[IDE_BUS(i)])
+ continue;
+ ide_led(led, 1); /* LED on */
+ ide_ident(&ide_dev_desc[i]);
+ ide_led(led, 0); /* LED off */
+ dev_print(&ide_dev_desc[i]);
+
+ if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
+ /* initialize partition type */
+ part_init(&ide_dev_desc[i]);
+ }
+ }
+ WATCHDOG_RESET();
+}
+
+/* We only need to swap data if we are running on a big endian cpu. */
+#if defined(__LITTLE_ENDIAN)
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+ ide_input_data(dev, sect_buf, words);
+}
+#else
+__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+ volatile ushort *pbuf =
+ (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ ushort *dbuf = (ushort *)sect_buf;
+
+ debug("in input swap data base for read is %lx\n",
+ (unsigned long) pbuf);
+
+ while (words--) {
+#ifdef __MIPS__
+ *dbuf++ = swab16p((u16 *)pbuf);
+ *dbuf++ = swab16p((u16 *)pbuf);
+#else
+ *dbuf++ = ld_le16(pbuf);
+ *dbuf++ = ld_le16(pbuf);
+#endif /* !MIPS */
+ }
+}
+#endif /* __LITTLE_ENDIAN */
+
+
+#if defined(CONFIG_IDE_SWAP_IO)
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *)sect_buf;
+ while (words--) {
+ EIEIO;
+ *pbuf = *dbuf++;
+ EIEIO;
+ *pbuf = *dbuf++;
+ }
+}
+#else /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+#if defined(CONFIG_IDE_AHB)
+ ide_write_data(dev, sect_buf, words);
+#else
+ outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
+#endif
+}
+#endif /* CONFIG_IDE_SWAP_IO */
+
+#if defined(CONFIG_IDE_SWAP_IO)
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *)sect_buf;
+
+ debug("in input data base for read is %lx\n", (unsigned long) pbuf);
+
+ while (words--) {
+ EIEIO;
+ *dbuf++ = *pbuf;
+ EIEIO;
+ *dbuf++ = *pbuf;
+ }
+}
+#else /* ! CONFIG_IDE_SWAP_IO */
+__weak void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+#if defined(CONFIG_IDE_AHB)
+ ide_read_data(dev, sect_buf, words);
+#else
+ insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
+#endif
+}
+
+#endif /* CONFIG_IDE_SWAP_IO */
+
+#ifdef CONFIG_BLK
+ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+#else
+ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ void *buffer)
+#endif
+{
+#ifdef CONFIG_BLK
+ struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
+ int device = block_dev->devnum;
+ ulong n = 0;
+ unsigned char c;
+ unsigned char pwrsave = 0; /* power save */
+
+#ifdef CONFIG_LBA48
+ unsigned char lba48 = 0;
+
+ if (blknr & 0x0000fffff0000000ULL) {
+ /* more than 28 bits used, use 48bit mode */
+ lba48 = 1;
+ }
+#endif
+ debug("ide_read dev %d start " LBAF ", blocks " LBAF " buffer at %lX\n",
+ device, blknr, blkcnt, (ulong) buffer);
+
+ ide_led(DEVICE_LED(device), 1); /* LED on */
+
+ /* Select device
+ */
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+ c = ide_wait(device, IDE_TIME_OUT);
+
+ if (c & ATA_STAT_BUSY) {
+ printf("IDE read: device %d not ready\n", device);
+ goto IDE_READ_E;
+ }
+
+ /* first check if the drive is in Powersaving mode, if yes,
+ * increase the timeout value */
+ ide_outb(device, ATA_COMMAND, ATA_CMD_CHK_PWR);
+ udelay(50);
+
+ c = ide_wait(device, IDE_TIME_OUT); /* can't take over 500 ms */
+
+ if (c & ATA_STAT_BUSY) {
+ printf("IDE read: device %d not ready\n", device);
+ goto IDE_READ_E;
+ }
+ if ((c & ATA_STAT_ERR) == ATA_STAT_ERR) {
+ printf("No Powersaving mode %X\n", c);
+ } else {
+ c = ide_inb(device, ATA_SECT_CNT);
+ debug("Powersaving %02X\n", c);
+ if (c == 0)
+ pwrsave = 1;
+ }
+
+
+ while (blkcnt-- > 0) {
+ c = ide_wait(device, IDE_TIME_OUT);
+
+ if (c & ATA_STAT_BUSY) {
+ printf("IDE read: device %d not ready\n", device);
+ break;
+ }
+#ifdef CONFIG_LBA48
+ if (lba48) {
+ /* write high bits */
+ ide_outb(device, ATA_SECT_CNT, 0);
+ ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+#ifdef CONFIG_SYS_64BIT_LBA
+ ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
+ ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+ ide_outb(device, ATA_LBA_MID, 0);
+ ide_outb(device, ATA_LBA_HIGH, 0);
+#endif
+ }
+#endif
+ ide_outb(device, ATA_SECT_CNT, 1);
+ ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
+ ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
+ ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+
+#ifdef CONFIG_LBA48
+ if (lba48) {
+ ide_outb(device, ATA_DEV_HD,
+ ATA_LBA | ATA_DEVICE(device));
+ ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
+
+ } else
+#endif
+ {
+ ide_outb(device, ATA_DEV_HD, ATA_LBA |
+ ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+ ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
+ }
+
+ udelay(50);
+
+ if (pwrsave) {
+ /* may take up to 4 sec */
+ c = ide_wait(device, IDE_SPIN_UP_TIME_OUT);
+ pwrsave = 0;
+ } else {
+ /* can't take over 500 ms */
+ c = ide_wait(device, IDE_TIME_OUT);
+ }
+
+ if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
+ ATA_STAT_DRQ) {
+ printf("Error (no IRQ) dev %d blk " LBAF
+ ": status %#02x\n", device, blknr, c);
+ break;
+ }
+
+ ide_input_data(device, buffer, ATA_SECTORWORDS);
+ (void) ide_inb(device, ATA_STATUS); /* clear IRQ */
+
+ ++n;
+ ++blknr;
+ buffer += ATA_BLOCKSIZE;
+ }
+IDE_READ_E:
+ ide_led(DEVICE_LED(device), 0); /* LED off */
+ return n;
+}
+
+#ifdef CONFIG_BLK
+ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
+#else
+ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+ const void *buffer)
+#endif
+{
+#ifdef CONFIG_BLK
+ struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
+#endif
+ int device = block_dev->devnum;
+ ulong n = 0;
+ unsigned char c;
+
+#ifdef CONFIG_LBA48
+ unsigned char lba48 = 0;
+
+ if (blknr & 0x0000fffff0000000ULL) {
+ /* more than 28 bits used, use 48bit mode */
+ lba48 = 1;
+ }
+#endif
+
+ ide_led(DEVICE_LED(device), 1); /* LED on */
+
+ /* Select device
+ */
+ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
+
+ while (blkcnt-- > 0) {
+ c = ide_wait(device, IDE_TIME_OUT);
+
+ if (c & ATA_STAT_BUSY) {
+ printf("IDE read: device %d not ready\n", device);
+ goto WR_OUT;
+ }
+#ifdef CONFIG_LBA48
+ if (lba48) {
+ /* write high bits */
+ ide_outb(device, ATA_SECT_CNT, 0);
+ ide_outb(device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
+#ifdef CONFIG_SYS_64BIT_LBA
+ ide_outb(device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
+ ide_outb(device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+ ide_outb(device, ATA_LBA_MID, 0);
+ ide_outb(device, ATA_LBA_HIGH, 0);
+#endif
+ }
+#endif
+ ide_outb(device, ATA_SECT_CNT, 1);
+ ide_outb(device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
+ ide_outb(device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
+ ide_outb(device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
+
+#ifdef CONFIG_LBA48
+ if (lba48) {
+ ide_outb(device, ATA_DEV_HD,
+ ATA_LBA | ATA_DEVICE(device));
+ ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
+
+ } else
+#endif
+ {
+ ide_outb(device, ATA_DEV_HD, ATA_LBA |
+ ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
+ ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
+ }
+
+ udelay(50);
+
+ /* can't take over 500 ms */
+ c = ide_wait(device, IDE_TIME_OUT);
+
+ if ((c & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
+ ATA_STAT_DRQ) {
+ printf("Error (no IRQ) dev %d blk " LBAF
+ ": status %#02x\n", device, blknr, c);
+ goto WR_OUT;
+ }
+
+ ide_output_data(device, buffer, ATA_SECTORWORDS);
+ c = ide_inb(device, ATA_STATUS); /* clear IRQ */
+ ++n;
+ ++blknr;
+ buffer += ATA_BLOCKSIZE;
+ }
+WR_OUT:
+ ide_led(DEVICE_LED(device), 0); /* LED off */
+ return n;
+}
+
+#if defined(CONFIG_OF_IDE_FIXUP)
+int ide_device_present(int dev)
+{
+ if (dev >= CONFIG_SYS_IDE_MAXBUS)
+ return 0;
+ return ide_dev_desc[dev].type == DEV_TYPE_UNKNOWN ? 0 : 1;
+}
+#endif
+
+#ifdef CONFIG_BLK
+static const struct blk_ops ide_blk_ops = {
+ .read = ide_read,
+ .write = ide_write,
+};
+
+U_BOOT_DRIVER(ide_blk) = {
+ .name = "ide_blk",
+ .id = UCLASS_BLK,
+ .ops = &ide_blk_ops,
+};
+#else
+U_BOOT_LEGACY_BLK(ide) = {
+ .if_typename = "ide",
+ .if_type = IF_TYPE_IDE,
+ .max_devs = CONFIG_SYS_IDE_MAXDEVICE,
+ .desc = ide_dev_desc,
+};
+#endif
* incorrect for the target board (e.g. the sequoia board requires 0).
* #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0
*
- * #define CONFIG_CMD_IDE
+ * #define CONFIG_IDE
* #undef CONFIG_IDE_8xx_DIRECT
* #undef CONFIG_IDE_LED
* #undef CONFIG_IDE_RESET
config FSL_CAAM
bool "Freescale Crypto Driver Support"
+ select SHA_HW_ACCEL
+ imply CMD_HASH
help
Enables the Freescale's Cryptographic Accelerator and Assurance
Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2001
-# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#ccflags-y += -DDEBUG
-
-obj-$(CONFIG_DTT_ADM1021) += adm1021.o
-obj-$(CONFIG_DTT_ADT7460) += adt7460.o
-obj-$(CONFIG_DTT_DS1621) += ds1621.o
-obj-$(CONFIG_DTT_DS1722) += ds1722.o
-obj-$(CONFIG_DTT_DS1775) += ds1775.o
-obj-$(CONFIG_DTT_DS620) += ds620.o
-obj-$(CONFIG_DTT_LM63) += lm63.o
-obj-$(CONFIG_DTT_LM73) += lm73.o
-obj-$(CONFIG_DTT_LM75) += lm75.o
-obj-$(CONFIG_DTT_LM81) += lm81.o
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Murray Jensen, CSIRO-MIT, Murray.Jensen@csiro.au
- *
- * based on dtt/lm75.c which is ...
- *
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Analog Devices's ADM1021
- * "Low Cost Microprocessor System Temperature Monitor"
- */
-
-#include <common.h>
-
-#include <i2c.h>
-#include <dtt.h>
-
-#define DTT_READ_LOC_VALUE 0x00
-#define DTT_READ_REM_VALUE 0x01
-#define DTT_READ_STATUS 0x02
-#define DTT_READ_CONFIG 0x03
-#define DTT_READ_CONVRATE 0x04
-#define DTT_READ_LOC_HIGHLIM 0x05
-#define DTT_READ_LOC_LOWLIM 0x06
-#define DTT_READ_REM_HIGHLIM 0x07
-#define DTT_READ_REM_LOWLIM 0x08
-#define DTT_READ_DEVID 0xfe
-
-#define DTT_WRITE_CONFIG 0x09
-#define DTT_WRITE_CONVRATE 0x0a
-#define DTT_WRITE_LOC_HIGHLIM 0x0b
-#define DTT_WRITE_LOC_LOWLIM 0x0c
-#define DTT_WRITE_REM_HIGHLIM 0x0d
-#define DTT_WRITE_REM_LOWLIM 0x0e
-#define DTT_WRITE_ONESHOT 0x0f
-
-#define DTT_STATUS_BUSY 0x80 /* 1=ADC Converting */
-#define DTT_STATUS_LHIGH 0x40 /* 1=Local High Temp Limit Tripped */
-#define DTT_STATUS_LLOW 0x20 /* 1=Local Low Temp Limit Tripped */
-#define DTT_STATUS_RHIGH 0x10 /* 1=Remote High Temp Limit Tripped */
-#define DTT_STATUS_RLOW 0x08 /* 1=Remote Low Temp Limit Tripped */
-#define DTT_STATUS_OPEN 0x04 /* 1=Remote Sensor Open-Circuit */
-
-#define DTT_CONFIG_ALERT_MASKED 0x80 /* 0=ALERT Enabled, 1=ALERT Masked */
-#define DTT_CONFIG_STANDBY 0x40 /* 0=Run, 1=Standby */
-
-#define DTT_ADM1021_DEVID 0x41
-
-typedef
- struct {
- uint i2c_addr:7; /* 7bit i2c chip address */
- uint conv_rate:3; /* conversion rate */
- uint enable_alert:1; /* enable alert output pin */
- uint enable_local:1; /* enable internal temp sensor */
- uint max_local:8; /* internal temp maximum */
- uint min_local:8; /* internal temp minimum */
- uint enable_remote:1; /* enable remote temp sensor */
- uint max_remote:8; /* remote temp maximum */
- uint min_remote:8; /* remote temp minimum */
- }
-dtt_cfg_t;
-
-dtt_cfg_t dttcfg[] = CONFIG_SYS_DTT_ADM1021;
-
-int
-dtt_read (int sensor, int reg)
-{
- dtt_cfg_t *dcp = &dttcfg[sensor >> 1];
- uchar data;
-
- if (i2c_read(dcp->i2c_addr, reg, 1, &data, 1) != 0)
- return -1;
-
- return (int)data;
-} /* dtt_read() */
-
-int
-dtt_write (int sensor, int reg, int val)
-{
- dtt_cfg_t *dcp = &dttcfg[sensor >> 1];
- uchar data;
-
- data = (uchar)(val & 0xff);
-
- if (i2c_write(dcp->i2c_addr, reg, 1, &data, 1) != 0)
- return 1;
-
- return 0;
-} /* dtt_write() */
-
-int
-dtt_init_one(int sensor)
-{
- dtt_cfg_t *dcp = &dttcfg[sensor >> 1];
- int reg, val;
-
- if (((sensor & 1) == 0 ? dcp->enable_local : dcp->enable_remote) == 0)
- return 1; /* sensor is disabled (or rather ignored) */
-
- /*
- * Setup High Limit register
- */
- if ((sensor & 1) == 0) {
- reg = DTT_WRITE_LOC_HIGHLIM;
- val = dcp->max_local;
- }
- else {
- reg = DTT_WRITE_REM_HIGHLIM;
- val = dcp->max_remote;
- }
- if (dtt_write (sensor, reg, val) != 0)
- return 1;
-
- /*
- * Setup Low Limit register
- */
- if ((sensor & 1) == 0) {
- reg = DTT_WRITE_LOC_LOWLIM;
- val = dcp->min_local;
- }
- else {
- reg = DTT_WRITE_REM_LOWLIM;
- val = dcp->min_remote;
- }
- if (dtt_write (sensor, reg, val) != 0)
- return 1;
-
- /* shouldn't hurt if the rest gets done twice */
-
- /*
- * Setup Conversion Rate register
- */
- if (dtt_write (sensor, DTT_WRITE_CONVRATE, dcp->conv_rate) != 0)
- return 1;
-
- /*
- * Setup configuraton register
- */
- val = 0; /* running */
- if (dcp->enable_alert == 0)
- val |= DTT_CONFIG_ALERT_MASKED; /* mask ALERT pin */
- if (dtt_write (sensor, DTT_WRITE_CONFIG, val) != 0)
- return 1;
-
- return 0;
-} /* dtt_init_one() */
-
-int
-dtt_get_temp (int sensor)
-{
- signed char val;
-
- if ((sensor & 1) == 0)
- val = dtt_read(sensor, DTT_READ_LOC_VALUE);
- else
- val = dtt_read(sensor, DTT_READ_REM_VALUE);
-
- return (int) val;
-} /* dtt_get_temp() */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid, ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology http://qtec.com/
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <dtt.h>
-
-#define ADT7460_ADDRESS 0x2c
-#define ADT7460_INVALID 128
-#define ADT7460_CONFIG 0x40
-#define ADT7460_REM1_TEMP 0x25
-#define ADT7460_LOCAL_TEMP 0x26
-#define ADT7460_REM2_TEMP 0x27
-
-int dtt_read(int sensor, int reg)
-{
- u8 dir = reg;
- u8 data;
-
- if (i2c_read(ADT7460_ADDRESS, dir, 1, &data, 1) == -1)
- return -1;
- if (data == ADT7460_INVALID)
- return -1;
-
- return data;
-}
-
-int dtt_write(int sensor, int reg, int val)
-{
- u8 dir = reg;
- u8 data = val;
-
- if (i2c_write(ADT7460_ADDRESS, dir, 1, &data, 1) == -1)
- return -1;
-
- return 0;
-}
-
-int dtt_init_one(int sensor)
-{
- printf("ADT7460 at I2C address 0x%2x\n", ADT7460_ADDRESS);
-
- if (dtt_write(0, ADT7460_CONFIG, 1) == -1) {
- puts("Error initialiting ADT7460\n");
- return -1;
- }
-
- return 0;
-}
-
-int dtt_get_temp(int sensor)
-{
- int aux;
- u8 table[] =
- { ADT7460_REM1_TEMP, ADT7460_LOCAL_TEMP, ADT7460_REM2_TEMP };
-
- if (sensor > 2) {
- puts("DTT sensor does not exist\n");
- return -1;
- }
-
- aux = dtt_read(0, table[sensor]);
- if (aux == -1) {
- puts("DTT temperature read failed\n");
- return -1;
- }
-
- return aux;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <dtt.h>
-
-/*
- * Device code
- */
-#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */
-#define DTT_READ_TEMP 0xAA
-#define DTT_READ_COUNTER 0xA8
-#define DTT_READ_SLOPE 0xA9
-#define DTT_WRITE_START_CONV 0xEE
-#define DTT_WRITE_STOP_CONV 0x22
-#define DTT_TEMP_HIGH 0xA1
-#define DTT_TEMP_LOW 0xA2
-#define DTT_CONFIG 0xAC
-
-/*
- * Config register bits
- */
-#define DTT_CONFIG_1SHOT 0x01
-#define DTT_CONFIG_POLARITY 0x02
-#define DTT_CONFIG_R0 0x04 /* ds1631 only */
-#define DTT_CONFIG_R1 0x08 /* ds1631 only */
-#define DTT_CONFIG_NVB 0x10
-#define DTT_CONFIG_TLF 0x20
-#define DTT_CONFIG_THF 0x40
-#define DTT_CONFIG_DONE 0x80
-
-
-int dtt_read(int sensor, int reg)
-{
- int dlen;
- uchar data[2];
-
- /* Calculate sensor address and command */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/
-
- /* Prepare to handle 2 byte result */
- switch(reg) {
- case DTT_READ_TEMP:
- case DTT_TEMP_HIGH:
- case DTT_TEMP_LOW:
- dlen = 2;
- break;
- default:
- dlen = 1;
- }
-
- /* Now try to read the register */
- if (i2c_read(sensor, reg, 1, data, dlen) != 0)
- return 1;
-
- /* Handle 2 byte result */
- if (dlen == 2)
- return (short)((data[0] << 8) | data[1]);
-
- return (int)data[0];
-}
-
-
-int dtt_write(int sensor, int reg, int val)
-{
- int dlen;
- uchar data[2];
-
- /* Calculate sensor address and register */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
-
- /* Handle various data sizes. */
- switch(reg) {
- case DTT_READ_TEMP:
- case DTT_TEMP_HIGH:
- case DTT_TEMP_LOW:
- dlen = 2;
- data[0] = (char)((val >> 8) & 0xff); /* MSB first */
- data[1] = (char)(val & 0xff);
- break;
- case DTT_WRITE_START_CONV:
- case DTT_WRITE_STOP_CONV:
- dlen = 0;
- data[0] = (char)0;
- data[1] = (char)0;
- break;
- default:
- dlen = 1;
- data[0] = (char)(val & 0xff);
- }
-
- /* Write value to device */
- if (i2c_write(sensor, reg, 1, data, dlen) != 0)
- return 1;
-
- /* Poll NV memory busy bit in case write was to register stored in EEPROM */
- while(i2c_reg_read(sensor, DTT_CONFIG) & DTT_CONFIG_NVB)
- ;
-
- return 0;
-}
-
-
-int dtt_init_one(int sensor)
-{
- int val;
-
- /* Setup High Temp */
- val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80;
- if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0)
- return 1;
-
- /* Setup Low Temp - hysteresis */
- val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
- if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0)
- return 1;
-
- /*
- * Setup configuraton register
- *
- * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES
- *
- * We run in polled mode, since there isn't any way to know if this
- * lousy device is ready to provide temperature readings on power up.
- */
- val = 0x9;
- if (dtt_write(sensor, DTT_CONFIG, val) != 0)
- return 1;
-
- return 0;
-}
-
-int dtt_get_temp(int sensor)
-{
- int i;
-
- /* Start a conversion, may take up to 1 second. */
- dtt_write(sensor, DTT_WRITE_START_CONV, 0);
- for (i = 0; i <= 10; i++) {
- udelay(100000);
- if (dtt_read(sensor, DTT_CONFIG) & DTT_CONFIG_DONE)
- break;
- }
-
- return (dtt_read(sensor, DTT_READ_TEMP) / 256);
-}
+++ /dev/null
-#include <common.h>
-#include <asm/ic/ssi.h>
-#include <ds1722.h>
-
-static void ds1722_select(int dev)
-{
- ssi_set_interface(4096, 0, 0, 0);
- ssi_chip_select(0);
- udelay(1);
- ssi_chip_select(dev);
- udelay(1);
-}
-
-
-u8 ds1722_read(int dev, int addr)
-{
- u8 res;
-
- ds1722_select(dev);
-
- ssi_tx_byte(addr);
- res = ssi_rx_byte();
-
- ssi_chip_select(0);
-
- return res;
-}
-
-void ds1722_write(int dev, int addr, u8 data)
-{
- ds1722_select(dev);
-
- ssi_tx_byte(0x80|addr);
- ssi_tx_byte(data);
-
- ssi_chip_select(0);
-}
-
-
-u16 ds1722_temp(int dev, int resolution)
-{
- static int useconds[] = {
- 75000, 150000, 300000, 600000, 1200000
- };
- char temp;
- u16 res;
-
-
- /* set up the desired resulotion ... */
- ds1722_write(dev, 0, 0xe0 | (resolution << 1));
-
- /* wait while the chip measures the tremperature */
- udelay(useconds[resolution]);
-
- res = (temp = ds1722_read(dev, 2)) << 8;
-
- if (temp < 0) {
- temp = (16 - (ds1722_read(dev, 1) >> 4)) & 0x0f;
- } else {
- temp = (ds1722_read(dev, 1) >> 4);
- }
-
- switch (temp) {
- case 0:
- /* .0000 */
- break;
- case 1:
- /* .0625 */
- res |=1;
- break;
- case 2:
- /* .1250 */
- res |=1;
- break;
- case 3:
- /* .1875 */
- res |=2;
- break;
- case 4:
- /* .2500 */
- res |=3;
- break;
- case 5:
- /* .3125 */
- res |=3;
- break;
- case 6:
- /* .3750 */
- res |=4;
- break;
- case 7:
- /* .4375 */
- res |=4;
- break;
- case 8:
- /* .5000 */
- res |=5;
- break;
- case 9:
- /* .5625 */
- res |=6;
- break;
- case 10:
- /* .6250 */
- res |=6;
- break;
- case 11:
- /* .6875 */
- res |=7;
- break;
- case 12:
- /* .7500 */
- res |=8;
- break;
- case 13:
- /* .8125 */
- res |=8;
- break;
- case 14:
- /* .8750 */
- res |=9;
- break;
- case 15:
- /* .9375 */
- res |=9;
- break;
- }
- return res;
-
-}
-
-int ds1722_probe(int dev)
-{
- u16 temp = ds1722_temp(dev, DS1722_RESOLUTION_12BIT);
- printf("%d.%d deg C\n\n", (char)(temp >> 8), temp & 0xff);
- return 0;
-}
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Dallas Semiconductor's DS1775 Digital Thermometer and Thermostat
- */
-
-#include <common.h>
-
-#include <i2c.h>
-#include <dtt.h>
-
-#define DTT_I2C_DEV_CODE CONFIG_SYS_I2C_DTT_ADDR /* Dallas Semi's DS1775 device code */
-#define DTT_READ_TEMP 0x0
-#define DTT_CONFIG 0x1
-#define DTT_TEMP_HYST 0x2
-#define DTT_TEMP_OS 0x3
-
-int dtt_read(int sensor, int reg)
-{
- int dlen;
- uchar data[2];
-
- /*
- * Calculate sensor address and command
- */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1775 */
-
- /*
- * Prepare to handle 2 byte result
- */
- if ((reg == DTT_READ_TEMP) ||
- (reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST))
- dlen = 2;
- else
- dlen = 1;
-
- /*
- * Now try to read the register
- */
- if (i2c_read(sensor, reg, 1, data, dlen) != 0)
- return 1;
-
- /*
- * Handle 2 byte result
- */
- if (dlen == 2)
- return ((int)((short)data[1] + (((short)data[0]) << 8)));
-
- return (int) data[0];
-}
-
-
-int dtt_write(int sensor, int reg, int val)
-{
- int dlen;
- uchar data[2];
-
- /*
- * Calculate sensor address and register
- */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
-
- /*
- * Handle various data sizes
- */
- if ((reg == DTT_READ_TEMP) ||
- (reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST)) {
- dlen = 2;
- data[0] = (char)((val >> 8) & 0xff); /* MSB first */
- data[1] = (char)(val & 0xff);
- } else {
- dlen = 1;
- data[0] = (char)(val & 0xff);
- }
-
- /*
- * Write value to device
- */
- if (i2c_write(sensor, reg, 1, data, dlen) != 0)
- return 1;
-
- return 0;
-}
-
-
-int dtt_init_one(int sensor)
-{
- int val;
-
- /*
- * Setup High Temp
- */
- val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80;
- if (dtt_write(sensor, DTT_TEMP_OS, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
-
- /*
- * Setup Low Temp - hysteresis
- */
- val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
- if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
-
- /*
- * Setup configuraton register
- *
- * Fault Tolerance limits 4, Thermometer resolution bits is 9,
- * Polarity = Active Low,continuous conversion mode, Thermostat
- * mode is interrupt mode
- */
- val = 0xa;
- if (dtt_write(sensor, DTT_CONFIG, val) != 0)
- return 1;
- udelay(50000); /* Max 50ms */
-
- return 0;
-}
-
-int dtt_get_temp(int sensor)
-{
- return (dtt_read(sensor, DTT_READ_TEMP) / 256);
-}
+++ /dev/null
-/*
- * DS620 DTT support
- *
- * (C) Copyright 2014 3ADEV <http://www.3adev.com>
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <dtt.h>
-
-/*
- * Device code
- */
-#define DTT_I2C_DEV_CODE 0x48
-#define DTT_START_CONVERT 0x51
-#define DTT_TEMP 0xAA
-#define DTT_CONFIG 0xAC
-
-/*
- * Config register MSB bits
- */
-#define DTT_CONFIG_1SHOT 0x01
-#define DTT_CONFIG_AUTOC 0x02
-#define DTT_CONFIG_R0 0x04 /* always 1 */
-#define DTT_CONFIG_R1 0x08 /* always 1 */
-#define DTT_CONFIG_TLF 0x10
-#define DTT_CONFIG_THF 0x20
-#define DTT_CONFIG_NVB 0x40
-#define DTT_CONFIG_DONE 0x80
-
-#define CHIP(sensor) (DTT_I2C_DEV_CODE + (sensor & 0x07))
-
-int dtt_init_one(int sensor)
-{
- uint8_t config = DTT_CONFIG_1SHOT
- | DTT_CONFIG_R0
- | DTT_CONFIG_R1;
- return i2c_write(CHIP(sensor), DTT_CONFIG, 1, &config, 1);
-}
-
-int dtt_get_temp(int sensor)
-{
- uint8_t status;
- uint8_t temp[2];
-
- /* Start a conversion, may take up to 1 second. */
- i2c_write(CHIP(sensor), DTT_START_CONVERT, 1, NULL, 0);
- do {
- if (i2c_read(CHIP(sensor), DTT_CONFIG, 1, &status, 1))
- /* bail out if I2C error */
- status |= DTT_CONFIG_DONE;
- } while (!(status & DTT_CONFIG_DONE));
- if (i2c_read(CHIP(sensor), DTT_TEMP, 1, temp, 2))
- /* bail out if I2C error */
- return -274; /* below absolute zero == error */
-
- return ((int16_t)(temp[1] | (temp[0] << 8))) >> 7;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- * based on lm75.c by Bill Hunter
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * National LM63/LM64 Temperature Sensor
- * Main difference: LM 64 has -16 Kelvin temperature offset
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <dtt.h>
-
-#define DTT_I2C_LM63_ADDR 0x4C /* National LM63 device */
-
-#define DTT_READ_TEMP_RMT_MSB 0x01
-#define DTT_CONFIG 0x03
-#define DTT_READ_TEMP_RMT_LSB 0x10
-#define DTT_TACHLIM_LSB 0x48
-#define DTT_TACHLIM_MSB 0x49
-#define DTT_FAN_CONFIG 0x4A
-#define DTT_PWM_FREQ 0x4D
-#define DTT_PWM_LOOKUP_BASE 0x50
-
-struct pwm_lookup_entry {
- u8 temp;
- u8 pwm;
-};
-
-/*
- * Device code
- */
-
-int dtt_read(int sensor, int reg)
-{
- int dlen;
- uchar data[2];
-
- /*
- * Calculate sensor address and register.
- */
- if (!sensor)
- sensor = DTT_I2C_LM63_ADDR; /* legacy config */
-
- dlen = 1;
-
- /*
- * Now try to read the register.
- */
- if (i2c_read(sensor, reg, 1, data, dlen) != 0)
- return -1;
-
- return (int)data[0];
-} /* dtt_read() */
-
-int dtt_write(int sensor, int reg, int val)
-{
- int dlen;
- uchar data[2];
-
- /*
- * Calculate sensor address and register.
- */
- if (!sensor)
- sensor = DTT_I2C_LM63_ADDR; /* legacy config */
-
- dlen = 1;
- data[0] = (char)(val & 0xff);
-
- /*
- * Write value to register.
- */
- if (i2c_write(sensor, reg, 1, data, dlen) != 0)
- return 1;
-
- return 0;
-} /* dtt_write() */
-
-static int is_lm64(int sensor)
-{
- return sensor && (sensor != DTT_I2C_LM63_ADDR);
-}
-
-int dtt_init_one(int sensor)
-{
- int i;
- int val;
-
- struct pwm_lookup_entry pwm_lookup[] = CONFIG_DTT_PWM_LOOKUPTABLE;
-
- /*
- * Set PWM Frequency to 2.5% resolution
- */
- val = 20;
- if (dtt_write(sensor, DTT_PWM_FREQ, val) != 0)
- return 1;
-
- /*
- * Set Tachometer Limit
- */
- val = CONFIG_DTT_TACH_LIMIT;
- if (dtt_write(sensor, DTT_TACHLIM_LSB, val & 0xff) != 0)
- return 1;
- if (dtt_write(sensor, DTT_TACHLIM_MSB, (val >> 8) & 0xff) != 0)
- return 1;
-
- /*
- * Make sure PWM Lookup-Table is writeable
- */
- if (dtt_write(sensor, DTT_FAN_CONFIG, 0x20) != 0)
- return 1;
-
- /*
- * Setup PWM Lookup-Table
- */
- for (i = 0; i < ARRAY_SIZE(pwm_lookup); i++) {
- int address = DTT_PWM_LOOKUP_BASE + 2 * i;
- val = pwm_lookup[i].temp;
- if (is_lm64(sensor))
- val -= 16;
- if (dtt_write(sensor, address, val) != 0)
- return 1;
- val = dtt_read(sensor, address);
- val = pwm_lookup[i].pwm;
- if (dtt_write(sensor, address + 1, val) != 0)
- return 1;
- }
-
- /*
- * Enable PWM Lookup-Table, PWM Clock 360 kHz, Tachometer Mode 2
- */
- val = 0x02;
- if (dtt_write(sensor, DTT_FAN_CONFIG, val) != 0)
- return 1;
-
- /*
- * Enable Tach input
- */
- val = dtt_read(sensor, DTT_CONFIG) | 0x04;
- if (dtt_write(sensor, DTT_CONFIG, val) != 0)
- return 1;
-
- return 0;
-}
-
-int dtt_get_temp(int sensor)
-{
- s16 temp = (dtt_read(sensor, DTT_READ_TEMP_RMT_MSB) << 8)
- | (dtt_read(sensor, DTT_READ_TEMP_RMT_LSB));
-
- if (is_lm64(sensor))
- temp += 16 << 8;
-
- /* Ignore LSB for now, U-Boot only prints natural numbers */
- return temp >> 8;
-}
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Larry Johnson, lrj@acm.org
- *
- * based on dtt/lm75.c which is ...
- *
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * National Semiconductor LM73 Temperature Sensor
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <dtt.h>
-
-/*
- * Device code
- */
-#define DTT_I2C_DEV_CODE 0x48 /* National Semi's LM73 device */
-#define DTT_READ_TEMP 0x0
-#define DTT_CONFIG 0x1
-#define DTT_TEMP_HIGH 0x2
-#define DTT_TEMP_LOW 0x3
-#define DTT_CONTROL 0x4
-#define DTT_ID 0x7
-
-int dtt_read(int const sensor, int const reg)
-{
- int dlen;
- uint8_t data[2];
-
- /*
- * Validate 'reg' param and get register size.
- */
- switch (reg) {
- case DTT_CONFIG:
- case DTT_CONTROL:
- dlen = 1;
- break;
- case DTT_READ_TEMP:
- case DTT_TEMP_HIGH:
- case DTT_TEMP_LOW:
- case DTT_ID:
- dlen = 2;
- break;
- default:
- return -1;
- }
- /*
- * Try to read the register at the calculated sensor address.
- */
- if (0 !=
- i2c_read(DTT_I2C_DEV_CODE + (sensor & 0x07), reg, 1, data, dlen))
- return -1;
- /*
- * Handle 2 byte result.
- */
- if (2 == dlen)
- return (int)((unsigned)data[0] << 8 | (unsigned)data[1]);
-
- return (int)data[0];
-} /* dtt_read() */
-
-int dtt_write(int const sensor, int const reg, int const val)
-{
- int dlen;
- uint8_t data[2];
-
- /*
- * Validate 'reg' param and handle register size
- */
- switch (reg) {
- case DTT_CONFIG:
- case DTT_CONTROL:
- dlen = 1;
- data[0] = (uint8_t) val;
- break;
- case DTT_TEMP_HIGH:
- case DTT_TEMP_LOW:
- dlen = 2;
- data[0] = (uint8_t) (val >> 8); /* MSB first */
- data[1] = (uint8_t) val;
- break;
- default:
- return -1;
- }
- /*
- * Write value to register at the calculated sensor address.
- */
- return 0 != i2c_write(DTT_I2C_DEV_CODE + (sensor & 0x07), reg, 1, data,
- dlen);
-} /* dtt_write() */
-
-int dtt_init_one(int const sensor)
-{
- int val;
-
- /*
- * Validate the Identification register
- */
- if (0x0190 != dtt_read(sensor, DTT_ID))
- return -1;
- /*
- * Setup THIGH (upper-limit) and TLOW (lower-limit) registers
- */
- val = CONFIG_SYS_DTT_MAX_TEMP << 7;
- if (dtt_write(sensor, DTT_TEMP_HIGH, val))
- return -1;
-
- val = CONFIG_SYS_DTT_MIN_TEMP << 7;
- if (dtt_write(sensor, DTT_TEMP_LOW, val))
- return -1;
- /*
- * Setup configuraton register
- */
- /* config = alert active low, disabled, and reset */
- val = 0x64;
- if (dtt_write(sensor, DTT_CONFIG, val))
- return -1;
- /*
- * Setup control/status register
- */
- /* control = temp resolution 0.25C */
- val = 0x00;
- if (dtt_write(sensor, DTT_CONTROL, val))
- return -1;
-
- dtt_read(sensor, DTT_CONTROL); /* clear temperature flags */
- return 0;
-} /* dtt_init_one() */
-
-int dtt_get_temp(int const sensor)
-{
- int const ret = dtt_read(sensor, DTT_READ_TEMP);
-
- if (ret < 0) {
- printf("DTT temperature read failed.\n");
- return 0;
- }
- return (int)((int16_t) ret + 0x0040) >> 7;
-} /* dtt_get_temp() */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * On Semiconductor's LM75 Temperature Sensor
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <dtt.h>
-
-/*
- * Device code
- */
-#if defined(CONFIG_SYS_I2C_DTT_ADDR)
-#define DTT_I2C_DEV_CODE CONFIG_SYS_I2C_DTT_ADDR
-#else
-#define DTT_I2C_DEV_CODE 0x48 /* ON Semi's LM75 device */
-#endif
-#define DTT_READ_TEMP 0x0
-#define DTT_CONFIG 0x1
-#define DTT_TEMP_HYST 0x2
-#define DTT_TEMP_SET 0x3
-
-int dtt_read(int sensor, int reg)
-{
- int dlen;
- uchar data[2];
-
-#ifdef CONFIG_DTT_AD7414
- /*
- * On AD7414 the first value upon bootup is not read correctly.
- * This is most likely because of the 800ms update time of the
- * temp register in normal update mode. To get current values
- * each time we issue the "dtt" command including upon powerup
- * we switch into one-short mode.
- *
- * Issue one-shot mode command
- */
- dtt_write(sensor, DTT_CONFIG, 0x64);
-#endif
-
- /* Validate 'reg' param */
- if((reg < 0) || (reg > 3))
- return -1;
-
- /* Calculate sensor address and register. */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
-
- /* Prepare to handle 2 byte result. */
- if ((reg == DTT_READ_TEMP) ||
- (reg == DTT_TEMP_HYST) ||
- (reg == DTT_TEMP_SET))
- dlen = 2;
- else
- dlen = 1;
-
- /* Now try to read the register. */
- if (i2c_read(sensor, reg, 1, data, dlen) != 0)
- return -1;
-
- /* Handle 2 byte result. */
- if (dlen == 2)
- return ((int)((short)data[1] + (((short)data[0]) << 8)));
-
- return (int)data[0];
-} /* dtt_read() */
-
-
-int dtt_write(int sensor, int reg, int val)
-{
- int dlen;
- uchar data[2];
-
- /* Validate 'reg' param */
- if ((reg < 0) || (reg > 3))
- return 1;
-
- /* Calculate sensor address and register. */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
-
- /* Handle 2 byte values. */
- if ((reg == DTT_READ_TEMP) ||
- (reg == DTT_TEMP_HYST) ||
- (reg == DTT_TEMP_SET)) {
- dlen = 2;
- data[0] = (char)((val >> 8) & 0xff); /* MSB first */
- data[1] = (char)(val & 0xff);
- } else {
- dlen = 1;
- data[0] = (char)(val & 0xff);
- }
-
- /* Write value to register. */
- if (i2c_write(sensor, reg, 1, data, dlen) != 0)
- return 1;
-
- return 0;
-} /* dtt_write() */
-
-
-int dtt_init_one(int sensor)
-{
- int val;
-
- /* Setup TSET ( trip point ) register */
- val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80; /* trip */
- if (dtt_write(sensor, DTT_TEMP_SET, val) != 0)
- return 1;
-
- /* Setup THYST ( untrip point ) register - Hysteresis */
- val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
- if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0)
- return 1;
-
- /* Setup configuraton register */
-#ifdef CONFIG_DTT_AD7414
- /* config = alert active low and disabled */
- val = 0x60;
-#else
- /* config = 6 sample integration, int mode, active low, and enable */
- val = 0x18;
-#endif
- if (dtt_write(sensor, DTT_CONFIG, val) != 0)
- return 1;
-
- return 0;
-} /* dtt_init_one() */
-
-int dtt_get_temp(int sensor)
-{
- int const ret = dtt_read(sensor, DTT_READ_TEMP);
-
- if (ret < 0) {
- printf("DTT temperature read failed.\n");
- return 0;
- }
- return (int)((int16_t) ret / 256);
-} /* dtt_get_temp() */
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Heiko Schocher, DENX Software Enginnering <hs@denx.de>
- *
- * based on dtt/lm75.c which is ...
- *
- * (C) Copyright 2001
- * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * On Semiconductor's LM81 Temperature Sensor
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <dtt.h>
-
-/*
- * Device code
- */
-#define DTT_I2C_DEV_CODE 0x2c /* ON Semi's LM81 device */
-#define DTT_READ_TEMP 0x27
-#define DTT_CONFIG_TEMP 0x4b
-#define DTT_TEMP_MAX 0x39
-#define DTT_TEMP_HYST 0x3a
-#define DTT_CONFIG 0x40
-
-int dtt_read(int sensor, int reg)
-{
- int dlen = 1;
- uchar data[2];
-
- /*
- * Calculate sensor address and register.
- */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */
-
- /*
- * Now try to read the register.
- */
- if (i2c_read(sensor, reg, 1, data, dlen) != 0)
- return -1;
-
- return (int)data[0];
-} /* dtt_read() */
-
-
-int dtt_write(int sensor, int reg, int val)
-{
- uchar data;
-
- /*
- * Calculate sensor address and register.
- */
- sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */
-
- data = (char)(val & 0xff);
-
- /*
- * Write value to register.
- */
- if (i2c_write(sensor, reg, 1, &data, 1) != 0)
- return 1;
-
- return 0;
-} /* dtt_write() */
-
-#define DTT_MANU 0x3e
-#define DTT_REV 0x3f
-#define DTT_CONFIG 0x40
-#define DTT_ADR 0x48
-
-int dtt_init_one(int sensor)
-{
- int man;
- int adr;
- int rev;
-
- if (dtt_write (sensor, DTT_CONFIG, 0x01) < 0)
- return 1;
- /* The LM81 needs 400ms to get the correct values ... */
- udelay (400000);
- man = dtt_read (sensor, DTT_MANU);
- if (man != 0x01)
- return 1;
- adr = dtt_read (sensor, DTT_ADR);
- if (adr < 0)
- return 1;
- rev = dtt_read (sensor, DTT_REV);
- if (rev < 0)
- return 1;
-
- debug ("DTT: Found LM81@%x Rev: %d\n", adr, rev);
- return 0;
-} /* dtt_init_one() */
-
-
-#define TEMP_FROM_REG(temp) \
- ((temp)<256?((((temp)&0x1fe) >> 1) * 10) + ((temp) & 1) * 5: \
- ((((temp)&0x1fe) >> 1) -255) * 10 - ((temp) & 1) * 5) \
-
-int dtt_get_temp(int sensor)
-{
- int val = dtt_read (sensor, DTT_READ_TEMP);
- int tmpcnf = dtt_read (sensor, DTT_CONFIG_TEMP);
-
- return (TEMP_FROM_REG((val << 1) + ((tmpcnf & 0x80) >> 7))) / 10;
-} /* dtt_get_temp() */
provides a faster and more robust interface than I2C but the bugs
are less interesting.
+config DS4510
+ bool "Enable support for DS4510 CPU supervisor"
+ help
+ Enable support for the Maxim DS4510 CPU supervisor. It has an
+ integrated 64-byte EEPROM, four programmable non-volatile I/O pins
+ and a configurable timer for the supervisor function. The device is
+ connected over I2C.
+
config FSL_SEC_MON
bool "Enable FSL SEC_MON Driver"
help
#include <common.h>
#include <i2c.h>
#include <command.h>
-#include <ds4510.h>
-
-/* Default to an address that hopefully won't corrupt other i2c devices */
-#ifndef CONFIG_SYS_I2C_DS4510_ADDR
-#define CONFIG_SYS_I2C_DS4510_ADDR (~0)
-#endif
+#include "ds4510.h"
enum {
DS4510_CMD_INFO,
/*
* Write to DS4510, taking page boundaries into account
*/
-int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count)
+static int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count)
{
int wrlen;
int i = 0;
/*
* General read from DS4510
*/
-int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count)
+static int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count)
{
return i2c_read(chip, offset, 1, buf, count);
}
* nv = 0 - Writes to SEEPROM registers behave like EEPROM
* nv = 1 - Writes to SEEPROM registers behave like SRAM
*/
-int ds4510_see_write(uint8_t chip, uint8_t nv)
+static int ds4510_see_write(uint8_t chip, uint8_t nv)
{
uint8_t data;
/*
* Write de-assertion of reset signal delay
*/
-int ds4510_rstdelay_write(uint8_t chip, uint8_t delay)
+static int ds4510_rstdelay_write(uint8_t chip, uint8_t delay)
{
uint8_t data;
/*
* Write pullup characteristics of IO pins
*/
-int ds4510_pullup_write(uint8_t chip, uint8_t val)
+static int ds4510_pullup_write(uint8_t chip, uint8_t val)
{
val &= DS4510_IO_MASK;
/*
* Read pullup characteristics of IO pins
*/
-int ds4510_pullup_read(uint8_t chip)
+static int ds4510_pullup_read(uint8_t chip)
{
uint8_t val;
/*
* Write drive level of IO pins
*/
-int ds4510_gpio_write(uint8_t chip, uint8_t val)
+static int ds4510_gpio_write(uint8_t chip, uint8_t val)
{
uint8_t data;
int i;
/*
* Read drive level of IO pins
*/
-int ds4510_gpio_read(uint8_t chip)
+static int ds4510_gpio_read(uint8_t chip)
{
uint8_t data;
int val = 0;
/*
* Read physical level of IO pins
*/
-int ds4510_gpio_read_val(uint8_t chip)
+static int ds4510_gpio_read_val(uint8_t chip)
{
uint8_t val;
return val & DS4510_IO_MASK;
}
-#ifdef CONFIG_CMD_DS4510
-#ifdef CONFIG_CMD_DS4510_INFO
/*
* Display DS4510 information
*/
return 0;
}
-#endif /* CONFIG_CMD_DS4510_INFO */
cmd_tbl_t cmd_ds4510[] = {
U_BOOT_CMD_MKENT(device, 3, 0, (void *)DS4510_CMD_DEVICE, "", ""),
U_BOOT_CMD_MKENT(output, 4, 0, (void *)DS4510_CMD_OUTPUT, "", ""),
U_BOOT_CMD_MKENT(input, 3, 0, (void *)DS4510_CMD_INPUT, "", ""),
U_BOOT_CMD_MKENT(pullup, 4, 0, (void *)DS4510_CMD_PULLUP, "", ""),
-#ifdef CONFIG_CMD_DS4510_INFO
U_BOOT_CMD_MKENT(info, 2, 0, (void *)DS4510_CMD_INFO, "", ""),
-#endif
-#ifdef CONFIG_CMD_DS4510_RST
U_BOOT_CMD_MKENT(rstdelay, 3, 0, (void *)DS4510_CMD_RSTDELAY, "", ""),
-#endif
-#ifdef CONFIG_CMD_DS4510_MEM
U_BOOT_CMD_MKENT(eeprom, 6, 0, (void *)DS4510_CMD_EEPROM, "", ""),
U_BOOT_CMD_MKENT(seeprom, 6, 0, (void *)DS4510_CMD_SEEPROM, "", ""),
U_BOOT_CMD_MKENT(sram, 6, 0, (void *)DS4510_CMD_SRAM, "", ""),
-#endif
};
int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- static uint8_t chip = CONFIG_SYS_I2C_DS4510_ADDR;
+ static uint8_t chip = 0x51;
cmd_tbl_t *c;
ulong ul_arg2 = 0;
ulong ul_arg3 = 0;
int tmp;
-#ifdef CONFIG_CMD_DS4510_MEM
ulong addr;
ulong off;
ulong cnt;
int end;
int (*rw_func)(uint8_t, int, uint8_t *, int);
-#endif
c = find_cmd_tbl(argv[1], cmd_ds4510, ARRAY_SIZE(cmd_ds4510));
else
tmp &= ~(1 << ul_arg2);
return ds4510_pullup_write(chip, tmp);
-#ifdef CONFIG_CMD_DS4510_INFO
case DS4510_CMD_INFO:
return ds4510_info(chip);
-#endif
-#ifdef CONFIG_CMD_DS4510_RST
case DS4510_CMD_RSTDELAY:
return ds4510_rstdelay_write(chip, ul_arg2);
-#endif
-#ifdef CONFIG_CMD_DS4510_MEM
case DS4510_CMD_EEPROM:
end = DS4510_EEPROM + DS4510_EEPROM_SIZE;
off = DS4510_EEPROM;
end = DS4510_SRAM + DS4510_SRAM_SIZE;
off = DS4510_SRAM;
break;
-#endif
default:
/* We should never get here... */
return 1;
}
-#ifdef CONFIG_CMD_DS4510_MEM
/* Only eeprom, seeprom, and sram commands should make it here */
if (strcmp(argv[2], "read") == 0)
rw_func = ds4510_mem_read;
}
return rw_func(chip, off, (uint8_t *)addr, cnt);
-#endif
}
U_BOOT_CMD(
"ds4510 eeprom/seeprom/sram/gpio access",
"device [dev]\n"
" - show or set current device address\n"
-#ifdef CONFIG_CMD_DS4510_INFO
"ds4510 info\n"
" - display ds4510 info\n"
-#endif
"ds4510 output pin 0|1\n"
" - set pin low or high-Z\n"
"ds4510 input pin\n"
" - disable/enable pullup on specified pin\n"
"ds4510 nv 0|1\n"
" - make gpio and seeprom writes volatile/non-volatile"
-#ifdef CONFIG_CMD_DS4510_RST
"\n"
"ds4510 rstdelay 0-3\n"
" - set reset output delay"
-#endif
-#ifdef CONFIG_CMD_DS4510_MEM
"\n"
"ds4510 eeprom read addr off cnt\n"
"ds4510 eeprom write addr off cnt\n"
"ds4510 sram read addr off cnt\n"
"ds4510 sram write addr off cnt\n"
" - read/write 'cnt' bytes at SRAM offset 'off'"
-#endif
);
-#endif /* CONFIG_CMD_DS4510 */
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __DS4510_H_
+#define __DS4510_H_
+
+/* General defines */
+#define DS4510_NUM_IO 0x04
+#define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1)
+#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/* EEPROM from 0x00 - 0x39 */
+#define DS4510_EEPROM 0x00
+#define DS4510_EEPROM_SIZE 0x40
+#define DS4510_EEPROM_PAGE_SIZE 0x08
+#define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1))
+
+/* SEEPROM from 0xf0 - 0xf7 */
+#define DS4510_SEEPROM 0xf0
+#define DS4510_SEEPROM_SIZE 0x08
+
+/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */
+#define DS4510_PULLUP 0xF0
+#define DS4510_PULLUP_DIS 0x00
+#define DS4510_PULLUP_EN 0x01
+#define DS4510_RSTDELAY 0xF1
+#define DS4510_RSTDELAY_MASK 0x03
+#define DS4510_RSTDELAY_125 0x00
+#define DS4510_RSTDELAY_250 0x01
+#define DS4510_RSTDELAY_500 0x02
+#define DS4510_RSTDELAY_1000 0x03
+#define DS4510_IO3 0xF4
+#define DS4510_IO2 0xF5
+#define DS4510_IO1 0xF6
+#define DS4510_IO0 0xF7
+
+/* Status configuration registers from 0xf8 - 0xf9*/
+#define DS4510_IO_STATUS 0xF8
+#define DS4510_CFG 0xF9
+#define DS4510_CFG_READY 0x80
+#define DS4510_CFG_TRIP_POINT 0x40
+#define DS4510_CFG_RESET 0x20
+#define DS4510_CFG_SEE 0x10
+#define DS4510_CFG_SWRST 0x08
+
+/* SRAM from 0xfa - 0xff */
+#define DS4510_SRAM 0xfa
+#define DS4510_SRAM_SIZE 0x06
+
+#endif /* __DS4510_H_ */
#define CONFIG_PCMCIA
#endif
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_IDE)
#define CONFIG_PCMCIA
#endif
#define CONFIG_PCMCIA
#endif
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#define CONFIG_PCMCIA
#endif
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
obj-$(CONFIG_RTC_PL031) += pl031.o
obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o
-obj-$(CONFIG_RTC_RTC4543) += rtc4543.o
obj-$(CONFIG_RTC_RV3029) += rv3029.o
obj-$(CONFIG_RTC_RX8025) += rx8025.o
obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
+++ /dev/null
-/*
- * (C) Copyright 2008, 2009
- * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <command.h>
-#include <config.h>
-#include <rtc.h>
-#include <tws.h>
-
-#if defined(CONFIG_CMD_DATE)
-
-/*
- * Note: The acrobatics below is due to the hideously ingenius idea of
- * the chip designers. As the chip does not allow register
- * addressing, all values need to be read and written in one go. Sure
- * enough, the 'wday' field (0-6) is transferred using the economic
- * number of 4 bits right in the middle of the packet.....
- */
-
-int rtc_get(struct rtc_time *tm)
-{
- int rel = 0;
- uchar buffer[7];
-
- memset(buffer, 0, 7);
-
- /* Read 52 bits into our buffer */
- tws_read(buffer, 52);
-
- tm->tm_sec = bcd2bin( buffer[0] & 0x7F);
- tm->tm_min = bcd2bin( buffer[1] & 0x7F);
- tm->tm_hour = bcd2bin( buffer[2] & 0x3F);
- tm->tm_wday = bcd2bin( buffer[3] & 0x07);
- tm->tm_mday = bcd2bin((buffer[3] & 0xF0) >> 4 | (buffer[4] & 0x0F) << 4);
- tm->tm_mon = bcd2bin((buffer[4] & 0x30) >> 4 | (buffer[5] & 0x0F) << 4);
- tm->tm_year = bcd2bin((buffer[5] & 0xF0) >> 4 | (buffer[6] & 0x0F) << 4) + 2000;
- tm->tm_yday = 0;
- tm->tm_isdst = 0;
-
- if (tm->tm_sec & 0x80) {
- puts("### Warning: RTC Low Voltage - date/time not reliable\n");
- rel = -1;
- }
-
- debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
- tm->tm_hour, tm->tm_min, tm->tm_sec);
-
- return rel;
-}
-
-int rtc_set(struct rtc_time *tm)
-{
- uchar buffer[7];
- uchar tmp;
-
- debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
- tm->tm_hour, tm->tm_min, tm->tm_sec);
-
- memset(buffer, 0, 7);
- buffer[0] = bin2bcd(tm->tm_sec);
- buffer[1] = bin2bcd(tm->tm_min);
- buffer[2] = bin2bcd(tm->tm_hour);
- buffer[3] = bin2bcd(tm->tm_wday);
- tmp = bin2bcd(tm->tm_mday);
- buffer[3] |= (tmp & 0x0F) << 4;
- buffer[4] = (tmp & 0xF0) >> 4;
- tmp = bin2bcd(tm->tm_mon);
- buffer[4] |= (tmp & 0x0F) << 4;
- buffer[5] = (tmp & 0xF0) >> 4;
- tmp = bin2bcd(tm->tm_year % 100);
- buffer[5] |= (tmp & 0x0F) << 4;
- buffer[6] = (tmp & 0xF0) >> 4;
-
- /* Write the resulting 52 bits to device */
- tws_write(buffer, 52);
-
- return 0;
-}
-
-void rtc_reset(void)
-{
- struct rtc_time tmp;
-
- tmp.tm_sec = 0;
- tmp.tm_min = 0;
- tmp.tm_hour = 0;
- tmp.tm_wday = 4;
- tmp.tm_mday = 1;
- tmp.tm_mon = 1;
- tmp.tm_year = 2000;
- rtc_set(&tmp);
-}
-
-#endif
usually at least one of them exists. Either of them is supported
in U-Boot.
+config AG101P_TIMER
+ bool "AG101P timer support"
+ depends on TIMER && NDS32
+ help
+ Select this to enable a timer for AG01P devices.
+
+config AE3XX_TIMER
+ bool "AE3XX timer support"
+ depends on TIMER && NDS32
+ help
+ Select this to enable a timer for AE3XX devices.
+
endmenu
obj-$(CONFIG_AST_TIMER) += ast_timer.o
obj-$(CONFIG_STI_TIMER) += sti-timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
+obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
+obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
--- /dev/null
+/*
+ * Andestech ATCPIT100 timer driver
+ *
+ * (C) Copyright 2016
+ * Rick Chen, NDS32 Software Engineering, rick@andestech.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <timer.h>
+#include <linux/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define REG32_TMR(x) (*(unsigned long *) ((plat->regs) + (x>>2)))
+
+/*
+ * Definition of register offsets
+ */
+
+/* ID and Revision Register */
+#define ID_REV 0x0
+
+/* Configuration Register */
+#define CFG 0x10
+
+/* Interrupt Enable Register */
+#define INT_EN 0x14
+#define CH_INT_EN(c , i) ((1<<i)<<(4*c))
+
+/* Interrupt Status Register */
+#define INT_STA 0x18
+#define CH_INT_STA(c , i) ((1<<i)<<(4*c))
+
+/* Channel Enable Register */
+#define CH_EN 0x1C
+#define CH_TMR_EN(c , t) ((1<<t)<<(4*c))
+
+/* Ch n Control REgister */
+#define CH_CTL(n) (0x20+0x10*n)
+/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
+#define APB_CLK (1<<3)
+/* Channel mode , bit 0~2 */
+#define TMR_32 1
+#define TMR_16 2
+#define TMR_8 3
+#define PWM 4
+
+#define CH_REL(n) (0x24+0x10*n)
+#define CH_CNT(n) (0x28+0x10*n)
+
+struct atctmr_timer_regs {
+ u32 id_rev; /* 0x00 */
+ u32 reservd[3]; /* 0x04 ~ 0x0c */
+ u32 cfg; /* 0x10 */
+ u32 int_en; /* 0x14 */
+ u32 int_st; /* 0x18 */
+ u32 ch_en; /* 0x1c */
+ u32 ch0_ctrl; /* 0x20 */
+ u32 ch0_reload; /* 0x24 */
+ u32 ch0_cntr; /* 0x28 */
+ u32 reservd1; /* 0x2c */
+ u32 ch1_ctrl; /* 0x30 */
+ u32 ch1_reload; /* 0x34 */
+ u32 int_mask; /* 0x38 */
+};
+
+struct atftmr_timer_platdata {
+ unsigned long *regs;
+};
+
+static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct atftmr_timer_platdata *plat = dev->platdata;
+ u32 val;
+ val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
+ *count = timer_conv_64(val);
+ return 0;
+}
+
+static int atctmr_timer_probe(struct udevice *dev)
+{
+ struct atftmr_timer_platdata *plat = dev->platdata;
+ REG32_TMR(CH_REL(1)) = 0xffffffff;
+ REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
+ REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
+ return 0;
+}
+
+static int atctme_timer_ofdata_to_platdata(struct udevice *dev)
+{
+ struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
+ plat->regs = map_physmem(dev_get_addr(dev) , 0x100 , MAP_NOCACHE);
+ return 0;
+}
+
+static const struct timer_ops ag101p_timer_ops = {
+ .get_count = atftmr_timer_get_count,
+};
+
+static const struct udevice_id ag101p_timer_ids[] = {
+ { .compatible = "andestech,atcpit100" },
+ {}
+};
+
+U_BOOT_DRIVER(altera_timer) = {
+ .name = "ae3xx_timer",
+ .id = UCLASS_TIMER,
+ .of_match = ag101p_timer_ids,
+ .ofdata_to_platdata = atctme_timer_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
+ .probe = atctmr_timer_probe,
+ .ops = &ag101p_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+/*
+ * Andestech ATFTMR010 timer driver
+ *
+ * (C) Copyright 2016
+ * Rick Chen, NDS32 Software Engineering, rick@andestech.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <timer.h>
+#include <linux/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Timer Control Register
+ */
+#define T3_UPDOWN (1 << 11)
+#define T2_UPDOWN (1 << 10)
+#define T1_UPDOWN (1 << 9)
+#define T3_OFENABLE (1 << 8)
+#define T3_CLOCK (1 << 7)
+#define T3_ENABLE (1 << 6)
+#define T2_OFENABLE (1 << 5)
+#define T2_CLOCK (1 << 4)
+#define T2_ENABLE (1 << 3)
+#define T1_OFENABLE (1 << 2)
+#define T1_CLOCK (1 << 1)
+#define T1_ENABLE (1 << 0)
+
+/*
+ * Timer Interrupt State & Mask Registers
+ */
+#define T3_OVERFLOW (1 << 8)
+#define T3_MATCH2 (1 << 7)
+#define T3_MATCH1 (1 << 6)
+#define T2_OVERFLOW (1 << 5)
+#define T2_MATCH2 (1 << 4)
+#define T2_MATCH1 (1 << 3)
+#define T1_OVERFLOW (1 << 2)
+#define T1_MATCH2 (1 << 1)
+#define T1_MATCH1 (1 << 0)
+
+struct atftmr_timer_regs {
+ u32 t1_counter; /* 0x00 */
+ u32 t1_load; /* 0x04 */
+ u32 t1_match1; /* 0x08 */
+ u32 t1_match2; /* 0x0c */
+ u32 t2_counter; /* 0x10 */
+ u32 t2_load; /* 0x14 */
+ u32 t2_match1; /* 0x18 */
+ u32 t2_match2; /* 0x1c */
+ u32 t3_counter; /* 0x20 */
+ u32 t3_load; /* 0x24 */
+ u32 t3_match1; /* 0x28 */
+ u32 t3_match2; /* 0x2c */
+ u32 cr; /* 0x30 */
+ u32 int_state; /* 0x34 */
+ u32 int_mask; /* 0x38 */
+};
+
+struct atftmr_timer_platdata {
+ struct atftmr_timer_regs *regs;
+};
+
+static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct atftmr_timer_platdata *plat = dev->platdata;
+ struct atftmr_timer_regs *const regs = plat->regs;
+ u32 val;
+ val = readl(®s->t3_counter);
+ *count = timer_conv_64(val);
+ return 0;
+}
+
+static int atftmr_timer_probe(struct udevice *dev)
+{
+ struct atftmr_timer_platdata *plat = dev->platdata;
+ struct atftmr_timer_regs *const regs = plat->regs;
+ u32 cr;
+ writel(0, ®s->t3_load);
+ writel(0, ®s->t3_counter);
+ writel(TIMER_LOAD_VAL, ®s->t3_match1);
+ writel(TIMER_LOAD_VAL, ®s->t3_match2);
+ /* disable interrupts */
+ writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , ®s->int_mask);
+ cr = readl(®s->cr);
+ cr |= (T3_ENABLE|T3_UPDOWN);
+ writel(cr, ®s->cr);
+ return 0;
+}
+
+static int atftme_timer_ofdata_to_platdata(struct udevice *dev)
+{
+ struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
+ plat->regs = map_physmem(dev_get_addr(dev),
+ sizeof(struct atftmr_timer_regs),
+ MAP_NOCACHE);
+ return 0;
+}
+
+static const struct timer_ops ag101p_timer_ops = {
+ .get_count = atftmr_timer_get_count,
+};
+
+static const struct udevice_id ag101p_timer_ids[] = {
+ { .compatible = "andestech,attmr010" },
+ {}
+};
+
+U_BOOT_DRIVER(altera_timer) = {
+ .name = "ag101p_timer",
+ .id = UCLASS_TIMER,
+ .of_match = ag101p_timer_ids,
+ .ofdata_to_platdata = atftme_timer_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
+ .probe = atftmr_timer_probe,
+ .ops = &ag101p_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+++ /dev/null
-#
-# (C) Copyright 2009
-# Detlev Zundel, DENX Software Engineering, dzu@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_SOFT_TWS) += soft_tws.o
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define TWS_IMPLEMENTATION
-#include <common.h>
-
-/*=====================================================================*/
-/* Public Functions */
-/*=====================================================================*/
-
-/*-----------------------------------------------------------------------
- * Read bits
- */
-int tws_read(uchar *buffer, int len)
-{
- int rem = len;
- uchar accu, shift;
-
- debug("tws_read: buffer %p len %d\n", buffer, len);
-
- /* Configure the data pin for input */
- tws_data_config_output(0);
-
- /* Disable WR, i.e. setup a read */
- tws_wr(0);
- udelay(1);
-
- /* Rise CE */
- tws_ce(1);
- udelay(1);
-
- for (; rem > 0; ) {
- for (shift = 0, accu = 0;
- (rem > 0) && (shift < 8);
- rem--, shift++) {
- tws_clk(1);
- udelay(10);
- accu |= (tws_data_read() << shift); /* LSB first */
- tws_clk(0);
- udelay(10);
- }
- *buffer++ = accu;
- }
-
- /* Lower CE */
- tws_ce(0);
-
- return len - rem;
-}
-
-
-/*-----------------------------------------------------------------------
- * Write bits
- */
-int tws_write(uchar *buffer, int len)
-{
- int rem = len;
- uchar accu, shift;
-
- debug("tws_write: buffer %p len %d\n", buffer, len);
-
- /* Configure the data pin for output */
- tws_data_config_output(1);
-
- /* Enable WR, i.e. setup a write */
- tws_wr(1);
- udelay(1);
-
- /* Rise CE */
- tws_ce(1);
- udelay(1);
-
- for (; rem > 0; ) {
- for (shift = 0, accu = *buffer++;
- (rem > 0) && (shift < 8);
- rem--, shift++) {
- tws_data(accu & 0x01); /* LSB first */
- tws_clk(1);
- udelay(10);
- tws_clk(0);
- udelay(10);
- accu >>= 1;
- }
- }
-
- /* Lower CE */
- tws_ce(0);
-
- return len - rem;
-}
int len;
len = mcs7830_recv_common(ueth, buf);
- if (len <= 0)
+ if (len >= 0) {
net_process_received_packet(buf, len);
+ return 0;
+ }
- return 0;
+ return len;
}
/*
This driver supports combination of Chipidea USB controller
and Synapsys USB PHY in host mode only.
+config USB_EHCI_RCAR_GEN3
+ bool "Support for Renesas RCar M3/H3 EHCI USB controller"
+ depends on RCAR_GEN3
+ default y
+ ---help---
+ Enables support for the on-chip EHCI controller on Renesas
+ R8A7795 and R8A7796 SoCs.
+
config USB_EHCI_ZYNQ
bool "Support for Xilinx Zynq on-chip EHCI USB controller"
depends on ARCH_ZYNQ
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
+obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
--- /dev/null
+/*
+ * drivers/usb/host/ehci-rcar_gen3.
+ * This file is EHCI HCD (Host Controller Driver) for USB.
+ *
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <usb/ehci-ci.h>
+#include "ehci.h"
+
+#define RCAR_GEN3_USB_BASE(n) (0xEE080000 + ((n) * 0x20000))
+
+#define EHCI_USBCMD 0x120
+
+#define CORE_SPD_RSM_TIMSET 0x30c
+#define CORE_OC_TIMSET 0x310
+
+/* Register offset */
+#define AHB_OFFSET 0x200
+
+#define BASE_HSUSB 0xE6590000
+#define REG_LPSTS (BASE_HSUSB + 0x0102) /* 16bit */
+#define SUSPM 0x4000
+#define SUSPM_NORMAL BIT(14)
+#define REG_UGCTRL2 (BASE_HSUSB + 0x0184) /* 32bit */
+#define USB0SEL 0x00000030
+#define USB0SEL_EHCI 0x00000010
+
+#define SMSTPCR7 0xE615014C
+#define SMSTPCR700 BIT(0) /* EHCI3 */
+#define SMSTPCR701 BIT(1) /* EHCI2 */
+#define SMSTPCR702 BIT(2) /* EHCI1 */
+#define SMSTPCR703 BIT(3) /* EHCI0 */
+#define SMSTPCR704 BIT(4) /* HSUSB */
+
+#define AHB_PLL_RST BIT(1)
+
+#define USBH_INTBEN BIT(2)
+#define USBH_INTAEN BIT(1)
+
+#define AHB_INT_ENABLE 0x200
+#define AHB_USBCTR 0x20c
+
+int ehci_hcd_stop(int index)
+{
+#if defined(CONFIG_R8A7795)
+ const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;
+#else
+ const u32 mask = SMSTPCR703 | SMSTPCR702;
+#endif
+ const u32 base = RCAR_GEN3_USB_BASE(index);
+ int ret;
+
+ /* Reset EHCI */
+ setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
+ ret = wait_for_bit("ehci-rcar", (void *)(uintptr_t)base + EHCI_USBCMD,
+ CMD_RESET, false, 10, true);
+ if (ret) {
+ printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
+ index, ret);
+ }
+
+ setbits_le32(SMSTPCR7, BIT(3 - index));
+
+ if ((readl(SMSTPCR7) & mask) == mask)
+ setbits_le32(SMSTPCR7, SMSTPCR704);
+
+ return 0;
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ const void __iomem *base =
+ (void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
+ struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;
+
+ clrbits_le32(SMSTPCR7, BIT(3 - index));
+ clrbits_le32(SMSTPCR7, SMSTPCR704);
+
+ *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+ /* Enable interrupt */
+ setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);
+ writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
+ writel(0x000209ab, base + CORE_OC_TIMSET);
+
+ /* Choice USB0SEL */
+ clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
+
+ /* Clock & Reset */
+ clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
+
+ /* low power status */
+ clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);
+
+ return 0;
+}
obj-$(CONFIG_CMD_CRAMFS) += cramfs/
obj-$(CONFIG_FS_EXT4) += ext4/
obj-y += fat/
-obj-$(CONFIG_CMD_JFFS2) += jffs2/
+obj-$(CONFIG_FS_JFFS2) += jffs2/
obj-$(CONFIG_CMD_REISER) += reiserfs/
obj-$(CONFIG_SANDBOX) += sandbox/
obj-$(CONFIG_CMD_UBIFS) += ubifs/
return 1;
}
-#if defined(CONFIG_CMD_IDE) || \
+#if defined(CONFIG_IDE) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_SCSI) || \
defined(CONFIG_CMD_USB) || \
+config FS_JFFS2
+ bool "Enable JFFS2 filesystem support"
+ help
+ This provides support for reading images from JFFS2 (Journalling
+ Flash File System version 2). JFFS2 is a log-structured file system
+ for use with flash memory devices. It supports raw NAND devices,
+ hard links and compression.
* Alphabetical list of all possible commands.
*/
-#define CONFIG_CMD_DTT /* Digital Therm and Thermostat */
-#define CONFIG_CMD_EEPROM /* EEPROM read/write support */
-#define CONFIG_CMD_FDC /* Floppy Disk Support */
-#define CONFIG_CMD_FUSE /* Device fuse support */
-#define CONFIG_CMD_GETTIME /* Get time since boot */
-#define CONFIG_CMD_HASH /* calculate hash / digest */
-#define CONFIG_CMD_IDE /* IDE harddisk support */
-#define CONFIG_CMD_IMMAP /* IMMR dump support */
-#define CONFIG_CMD_IO /* Access to X86 IO space */
-#define CONFIG_CMD_IRQ /* irqinfo */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
-#define CONFIG_CMD_KGDB /* kgdb */
#define CONFIG_CMD_MFSL /* FSL support for Microblaze */
#define CONFIG_CMD_MTDPARTS /* mtd parts support */
#define CONFIG_CMD_NAND /* NAND support */
BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
#endif
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#define BOOTENV_SHARED_IDE BOOTENV_SHARED_BLKDEV(ide)
#define BOOTENV_DEV_IDE BOOTENV_DEV_BLKDEV
#define BOOTENV_DEV_NAME_IDE BOOTENV_DEV_NAME_BLKDEV
#else
#define BOOTENV_SHARED_IDE
#define BOOTENV_DEV_IDE \
- BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_CMD_IDE
+ BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE
#define BOOTENV_DEV_NAME_IDE \
- BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_CMD_IDE
+ BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE
#endif
#if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI)
#endif
/* Rather than repeat this expression each time, add a define for it */
-#if defined(CONFIG_CMD_IDE) || \
+#if defined(CONFIG_IDE) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_SCSI) || \
defined(CONFIG_CMD_USB) || \
/*
* Command line configuration.
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
/*
* USB
*/
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
/* I2C EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
/*
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* enable read and write access to EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
/*
* Miscellaneous configurable options
*/
/* I2C EEPROM */
/* enable read and write access to EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
/*
* Miscellaneous configurable options
*/
* Command line configuration.
*/
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_EEPROM
#undef CONFIG_WATCHDOG /* watchdog disabled */
* Command line configuration.
*/
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_EEPROM
#define CONFIG_SUPPORT_VFAT
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
#define CONFIG_HOSTNAME M52277EVB
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
/* ATA */
# define CONFIG_IDE_RESET 1
# define CONFIG_IDE_PREINIT 1
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
/* ATA */
#define CONFIG_IDE_RESET 1
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
-#undef CONFIG_CMD_JFFS2
#undef CONFIG_CMD_NAND
#define CONFIG_CMD_REGINFO
#define CONFIG_MII_INIT 1
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_RX_ETH_BUFFER 2
-#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#define CONFIG_SYS_TX_ETH_BUFFER 2
#define CONFIG_HAS_ETH1
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
-#undef CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
/* Network configuration */
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_PCI
#define CONFIG_CMD_REGINFO
/*
* Command line configuration.
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_PCI
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVES
/*
* Command line configuration.
*/
-#define CONFIG_CMD_EEPROM
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SDRAM
#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
#define CONFIG_SUPPORT_VFAT
#endif
-#ifdef CONFIG_COMPACT_FLASH
- #define CONFIG_CMD_IDE
-#endif
-
#ifdef CONFIG_SATA_SIL3114
#define CONFIG_CMD_SATA
#endif
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
#endif
/* enable read and write access to EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#undef CONFIG_WATCHDOG /* watchdog disabled */
|| defined(CONFIG_FSL_SATA)
#endif
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
/*
* Miscellaneous configurable options
*/
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
/*
* Miscellaneous configurable options
*/
*/
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IRQ
#define CONFIG_BOOTCOMMAND "" /* autoboot command */
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_FDC
#define CONFIG_SCSI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SAVES
* Command line configuration.
*/
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_IDE
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_EEPROM
#define CONFIG_SUPPORT_VFAT
/*
* Command line configuration.
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PCI
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SYS_EEPROM_WREN 1
#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
-/*
- * standard dtt sensor configuration - bottom bit will determine local or
- * remote sensor of the TMP401
- */
-#define CONFIG_DTT_SENSORS { 0, 1 }
-
-/*
- * The PMC440 uses a TI TMP401 temperature sensor. This part
- * is basically compatible to the ADM1021 that is supported
- * by U-Boot.
- *
- * - i2c addr 0x4c
- * - conversion rate 0x02 = 0.25 conversions/second
- * - ALERT ouput disabled
- * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
- * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
- */
-#define CONFIG_DTT_ADM1021
-#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
-
#define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \
"\\\"painit\\\" to preboot command"
/* Partitions */
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_REGINFO
/*
* Command line configuration.
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#include <asm/fsl_secure_boot.h>
#endif /* __T1024QDS_H */
/*
* Command line configuration.
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#include <asm/fsl_secure_boot.h>
#endif /* __T1024RDB_H */
/* Enable VSC9953 L2 Switch driver */
#define CONFIG_VSC9953
-#define CONFIG_CMD_ETHSW
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
/*
* Command line configuration.
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
/*
* Miscellaneous configurable options
*/
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
#define CONFIG_VSC9953
-#define CONFIG_CMD_ETHSW
#ifdef CONFIG_TARGET_T1040RDB
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
/*
* Miscellaneous configurable options
*/
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
/*
* Miscellaneous configurable options
*/
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
/*
* USB
*/
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#define __USB_PHY_TYPE utmi
/*
* Command line configuration.
*/
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
- #define CONFIG_CMD_IDE
#endif
#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_NETCONSOLE
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_NETCONSOLE
#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-/* I2C SYSMON (LM75) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
/*
* TSEC
*/
/*
* Command line configuration.
*/
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_NETCONSOLE
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_NETCONSOLE
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_NETCONSOLE
/*
* Command line configuration.
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_NETCONSOLE
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_NETCONSOLE
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_NETCONSOLE
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_NETCONSOLE
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_NETCONSOLE
/*
* Command line configuration.
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_NETCONSOLE
/*
* Command line configuration.
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IDE
/*
* Miscellaneous configurable options
#define CONFIG_HWCONFIG
-#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
-#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
-#define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */
-/*
- * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details).
- * there will be one entry in this array for each two (dummy) sensors in
- * CONFIG_DTT_SENSORS.
- *
- * For uCP1020 module:
- * - only one ADM1021/NCT72
- * - i2c addr 0x41
- * - conversion rate 0x02 = 0.25 conversions/second
- * - ALERT output disabled
- * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
- * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
- */
-#define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \
- 0x02, 0, 1, 0, 85, 1, 0, 85} }
-
-#define CONFIG_CMD_DTT
-
/*
* These can be toggled for performance analysis, otherwise use default.
*/
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_ERRATA
/*
* USB
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_EEPROM
#undef CONFIG_WATCHDOG /* watchdog disabled */
* SPL related defines
*/
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_TEXT_BASE 0xfc000000
/* Place BSS for SPL near end of SDRAM */
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_LOADS_ECHO 1
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
-#undef CONFIG_CMD_FUSE
-#undef CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_AD7414 1 /* use AD7414 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
/*-----------------------------------------------------------------------
* Ethernet
*----------------------------------------------------------------------*/
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_DTT
#define CONFIG_CMD_NAND
/*-----------------------------------------------------------------------
--- /dev/null
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch-ae3xx/ae3xx.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SKIP_TRUNOFF_WATCHDOG
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_PANIC_HANG
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SERVERIP
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x00500000
+#ifdef CONFIG_OF_CONTROL
+#undef CONFIG_OF_SEPARATE
+#define CONFIG_OF_EMBED
+#endif
+#else
+
+#define CONFIG_SYS_TEXT_BASE 0x80000000
+#endif
+
+/*
+ * Timer
+ */
+#define CONFIG_SYS_CLK_FREQ 39062500
+#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ (5*1000000)
+#define OSC_CLK (4*OSC_5MHZ)
+#define RTC_DIV_COUNT (0.5) /* Why?? */
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#endif
+#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FTMAC100
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER 1
+#define CONFIG_FTSDC010_SDIO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN (512 << 10)
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
+
+#define PHYS_SDRAM_1 \
+ (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
+
+#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
+
+#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
+#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#define CONFIG_SYS_FTSMC020_CONFIGS { \
+ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
+ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
+ FTSMC020_TPR_AST(1) | \
+ FTSMC020_TPR_CTW(1) | \
+ FTSMC020_TPR_ATI(1) | \
+ FTSMC020_TPR_AT2(1) | \
+ FTSMC020_TPR_WTC(1) | \
+ FTSMC020_TPR_AHT(1) | \
+ FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * FLASH on ADP_AG101P is connected to BANK0
+ * Just disalbe the other BANK to avoid detection error.
+ */
+#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG (0x00)
+#define FTSMC020_BANK1_TIMING (0x00)
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
+
+/* support JEDEC */
+#ifdef CONFIG_CFI_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+#endif
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#endif
+#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
+#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
+#define CONFIG_ENV_SIZE 8192
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
+/* Increase max gunzip size */
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
+#endif /* __CONFIG_H */
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+#define CONFIG_CMDLINE_EDITING
-/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
-#define CONFIG_INITRD_TAG /* send initrd params */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SERVERIP
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_MEM_REMAP
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0x00500000
+#ifdef CONFIG_OF_CONTROL
+#undef CONFIG_OF_SEPARATE
+#define CONFIG_OF_EMBED
+#endif
#else
#ifdef CONFIG_MEM_REMAP
#define CONFIG_SYS_TEXT_BASE 0x80000000
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
+#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
+#endif
#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
/*
*/
#define CONFIG_FTMAC100
-
/*
* SD (MMC) controller
*/
* There are 4 banks supported for this Controller,
* but we have only 1 bank connected to flash on board
*/
+#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#endif
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* max number of sectors on one chip */
#define CONFIG_ENV_SIZE 8192
#define CONFIG_ENV_OVERWRITE
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
+/* Increase max gunzip size */
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
#endif /* __CONFIG_H */
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
-#define CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
/* SATA Configs */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#endif /* CONFIG_USB_AM35X */
/* commands to include */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_NAND /* NAND support */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
#endif
/* I2C Configuration */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
#define CONFIG_SYS_OMAP_ABE_SYSCK
/* Define the default GPT table for eMMC */
*/
#if defined(CONFIG_440)
#endif
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
/*
#define CONFIG_BOOTCOMMAND "sf probe;" \
"mtdparts default;" \
"bootm 0x9f650000"
-#define CONFIG_LZMA
#define MTDIDS_DEFAULT "nor0=spi-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
#define CONFIG_BOOTCOMMAND "sf probe;" \
"mtdparts default;" \
"bootm 0x9f680000"
-#define CONFIG_LZMA
#define MTDIDS_DEFAULT "nor0=spi-flash.0"
#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \
#define CONFIG_AP325RXA 1
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_IDE
#define CONFIG_BOOTARGS "console=ttySC2,38400"
#define CONFIG_SYS_TEXT_BASE 0x8BFC0000
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_ENV
#define CONFIG_BOOTARGS "console=ttySC4,115200"
#define CONFIG_SYS_I2C_SPEED 100000
/* OCOTP Configs */
-#define CONFIG_CMD_FUSE
#ifdef CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
#endif
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IPUV3_CLK 260000000
-#define CONFIG_CMD_HDMIDETECT
#define CONFIG_CONSOLE_MUX
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
/*
* U-Boot Commands
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */
#define CONFIG_CMD_MTDPARTS /* MTD partition support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_LOADS_ECHO 1
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
-#undef CONFIG_CMD_FUSE
-#undef CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
/* Define which commands should be available at u-boot command prompt */
-#if ENABLE_JFFS
-#define CONFIG_CMD_JFFS2
-#endif
#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMDLINE_EDITING
#define CONFIG_MCFRTC
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#define CONFIG_SYS_MASTER_CLOCK 132096000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#define CONFIG_SYS_MASTER_CLOCK 132096000
/*
* Command line configuration.
*/
-#define CONFIG_CMD_JFFS2
#define CONFIG_ATMEL_USART
#define CONFIG_MACB
/*
* Command line configuration.
*/
-#define CONFIG_CMD_JFFS2
#define CONFIG_ATMEL_USART
#define CONFIG_MACB
/*
* Command line configuration.
*/
-#define CONFIG_CMD_JFFS2
#define CONFIG_ATMEL_USART
#define CONFIG_MACB
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_FAT_WRITE
/* SHA hashing */
-#define CONFIG_CMD_HASH
#define CONFIG_HASH_VERIFY
-#define CONFIG_SHA1
-#define CONFIG_SHA256
/* Enable Time Command */
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
/* General parts of the framework, required. */
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#endif /* ! __BUR_AM335X_COMMON_H__ */
/*
* U-Boot commands
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVES
#ifndef CONFIG_DRIVER_TI_EMAC
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_REGINFO
/*
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
-#define CONFIG_DTT_AD7414 /* use AD7414 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
-#if defined(CONFIG_ARCHES)
-#define CONFIG_SYS_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */
-#endif
-
#if !defined(CONFIG_ARCHES)
/* RTC configuration */
#define CONFIG_RTC_M41T62
* Commands additional to the ones defined in amcc-common.h
*/
#if defined(CONFIG_ARCHES)
-#define CONFIG_CMD_DTT
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#elif defined(CONFIG_CANYONLANDS)
-#define CONFIG_CMD_DTT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SATA
#define CONFIG_CMD_SDRAM
#elif defined(CONFIG_GLACIER)
-#define CONFIG_CMD_DTT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_BUS 3
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EEPROM_LAYOUT
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_EEPROM_SIZE 256
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_PCI
/* I2C */
/*
* Supported commands
*/
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
/*
#define CONFIG_VIDEO_BMP_LOGO
/* EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 256
-#define CONFIG_CMD_EEPROM_LAYOUT
-#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
-
#endif /* __CONFIG_CM_FX6_H */
/* Status LED polarity is inversed, so init it in the "off" state */
/* EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 256
-#define CONFIG_CMD_EEPROM_LAYOUT
-#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
-
#ifndef CONFIG_SPL_BUILD
/*
* Enable PCA9555 at I2C0-0x26.
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
/* EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 256
-#define CONFIG_CMD_EEPROM_LAYOUT
-#define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
-
#endif /* __CONFIG_H */
#define CONFIG_OMAP3_SPI
/* EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 256
-#define CONFIG_CMD_EEPROM_LAYOUT
-#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v1, v2, v3"
-
#endif /* __CONFIG_H */
#define CONFIG_SPL_SPI_LOAD
/* EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 256
-#define CONFIG_CMD_EEPROM_LAYOUT
-#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
-
#endif /* __CONFIG_CM_T43_H */
/* Enabled commands */
/* EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 256
-#define CONFIG_CMD_EEPROM_LAYOUT
-#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
-
/* USB Networking options */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_SYS_I2C_SPEED 100000
/* OCOTP Configs */
-#define CONFIG_CMD_FUSE
#ifdef CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
#endif
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IPUV3_CLK 260000000
-#define CONFIG_CMD_HDMIDETECT
#define CONFIG_CONSOLE_MUX
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
/*
* Bootloader Components Configuration
*/
-#define CONFIG_CMD_ENV
/* I2C support */
#ifdef CONFIG_SYS_I2C
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_CMD_FUSE
#ifdef CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
#endif
#define CONFIG_PCA9698 /* NXP PCA9698 */
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SF_DEFAULT_MODE 0
#endif
-#define CONFIG_SHA1
-
/*
* MMC
*/
#ifndef CONFIG_TRAILBLAZER
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
/*
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_LAST_STAGE_INIT
-#define CONFIG_SPL_BOARD_INIT
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SCSI
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K)
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_ECC
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_PCI
/*
* U-Boot commands
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVES
#ifdef CONFIG_CMD_BDI
!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_ENV
#endif
#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
/* I2C */
#define CONFIG_SYS_I2C
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_PCI
/* SPI NOR flash default params, used by sf commands */
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_PCI
#define CONFIG_SCSI
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SATA
#ifdef CONFIG_DBAU1550
-#undef CONFIG_CMD_IDE
#undef CONFIG_CMD_PCMCIA
-
-#else
-
-#define CONFIG_CMD_IDE
-
#endif
/*
#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
#define CONFIG_SYS_NAND_USE_FLASH_BBT
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
/*
/* SPL will use SRAM as stack */
#define CONFIG_SPL_STACK 0x0000FFF8
-#define CONFIG_SPL_BOARD_INIT
/* Use the framework and generic lib */
#define CONFIG_SPL_FRAMEWORK
/* partition */
/* commands to include */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
#undef CONFIG_SUPPORT_RAW_INITRD
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PCI
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVES
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66
-/* new uImage format support */
-#define CONFIG_FIT_DISABLE_SHA256
-
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
/*
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_IRQ
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
#define CONFIG_SYS_SPD_BUS_NUM 4
/* Temp sensor/hwmon/dtt */
-#define CONFIG_SYS_DTT_BUS_NUM 4
-#define CONFIG_DTT_LM63 1 /* National LM63 */
-#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
-#define CONFIG_DTT_PWM_LOOKUPTABLE \
- { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
- { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
-#define CONFIG_DTT_TACH_LIMIT 0xa10
#define CONFIG_SYS_ICS8N3QV01_I2C {1, 3}
#define CONFIG_SYS_SIL1178_I2C {0, 2}
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-/* new uImage format support */
-#define CONFIG_FIT_DISABLE_SHA256
-
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
/*
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_IRQ
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_IDE
#define CONFIG_SYS_MVFS
#define CONFIG_NR_DRAM_BANKS 1
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_NAND
/*
* mv-common.h should be defined after CMD configs since it used them
/*
* File system
*/
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
#define CONFIG_SYS_OMAP_ABE_SYSCK
#ifndef CONFIG_SPL_BUILD
#define CONFIG_USB_ETHER_SMSC95XX
/* Extra Commands */
-#define CONFIG_CMD_ENV
/* Enable that for switching of boot partitions */
/* Disabled by default as some sub-commands can brick eMMC */
/*#define CONFIG_SUPPORT_EMMC_BOOT */
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
/* I2C */
#define CONFIG_SYS_I2C
/*
* U-Boot commands
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVES
#ifdef CONFIG_CMD_BDI
!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_ENV
#endif
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_ENV
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */
/* Monitor configuration */
-#define CONFIG_CMD_JFFS2
#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_UBOOT_BASE 0xfff90000
#define CONFIG_SYS_UBOOT_START 0x00800000
#define CONFIG_SYS_TEXT_BASE 0x00800000
/*
* Commands configuration
*/
-#define CONFIG_CMD_IDE
/*
* Network
/*
* IDE
*/
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#define __io
#define CONFIG_IDE_PREINIT
/* ED Mini V has an IDE-compatible SATA connector for port 1 */
* Command line configuration.
*/
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_ENV
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_AT91_GPIO
/* Command line configuration */
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
/* Enable ACE acceleration for SHA1 and SHA256 */
#define CONFIG_EXYNOS_ACE_SHA
-#define CONFIG_SHA_HW_ACCEL
/* Power Down Modes */
#define S5P_CHECK_SLEEP 0x00000BAD
/* select serial console configuration */
#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
-#define CONFIG_CMD_HASH
-
/* Thermal Management Unit */
#define CONFIG_EXYNOS_TMU
-#define CONFIG_CMD_DTT
-#define CONFIG_TMU_CMD_DTT
/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR 0x02020030
#endif /*CONFIG_CMD_NET*/
/* SHA hashing */
-#define CONFIG_CMD_HASH
#define CONFIG_HASH_VERIFY
-#define CONFIG_SHA1
-#define CONFIG_SHA256
/* Enable Time Command */
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_PCI
-#undef CONFIG_CMD_EEPROM
/*
* PCI stuff
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
-#define CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
/* SATA Configs */
* Commands configuration
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_IDE
#define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */
/*
* Command line configuration.
*/
/* add useful commands */
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
#define CONFIG_AUTO_COMPLETE
#define __CONFIG_H
/* SPL */
-#define CONFIG_SPL_BOARD_INIT
/* Location in NAND to read U-Boot from */
#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M)
#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c
/* Various command support */
-#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */
-#define CONFIG_CMD_GSC
-#define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */
#define CONFIG_CMD_UNZIP /* gzwrite */
#define CONFIG_RBTREE
#define CONFIG_VIDEO_IPUV3
#define CONFIG_VIDEO_LOGO
#define CONFIG_IPUV3_CLK 260000000
-#define CONFIG_CMD_HDMIDETECT
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 }
-#define CONFIG_FIT_DISABLE_SHA256
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_FS_EXT4
/* Command line configuration */
-#define CONFIG_CMD_ENV
#define CONFIG_MTD_PARTITIONS
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_CMD_FPGAD
-#define CONFIG_CMD_IOLOOP
-
/*
* System Clock Setup
*/
* Compression configuration
*/
#define CONFIG_BZIP2
-#define CONFIG_LZMA
/*
* Commands configuration
*/
#define CONFIG_SYS_MVFS
-#define CONFIG_CMD_IDE
/*
* mv-common.h should be defined after CMD configs since it used them
/*
* SATA driver configuration
*/
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT0
#define CONFIG_MVSATA_IDE_USE_PORT1
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif /* CONFIG_CMD_IDE */
+#endif /* CONFIG_IDE */
/*
* RTC driver configuration
* Compression configuration
*/
#define CONFIG_BZIP2
-#define CONFIG_LZMA
#define CONFIG_LZO
/*
* Commands configuration
*/
#define CONFIG_SYS_MVFS
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_NAND
/*
/*
* File system
*/
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE
*/
#define CONFIG_CMD_NAND
#define CONFIG_CMDLINE_EDITING
-#define CONFIG_CMD_JFFS2
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
#define CONFIG_LOADADDR 0x400000
-#define CONFIG_CMD_ENV_FLAGS
#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x9
#define CONFIG_IMAGE_FORMAT_LEGACY
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA1
-#define CONFIG_SHA256
#endif /* __CONFIG_H */
/*
* U-Boot commands
*/
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
/***********************************************************
* Command definition
***********************************************************/
-#define CONFIG_CMD_EEPROM
#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \
/* FIT */
#ifdef CONFIG_FIT
# define CONFIG_HASH_VERIFY
-# define CONFIG_SHA1
-# define CONFIG_SHA256
# define CONFIG_IMAGE_FORMAT_LEGACY
#endif
/* FIT */
#ifdef CONFIG_FIT
# define CONFIG_HASH_VERIFY
-# define CONFIG_SHA1
-# define CONFIG_SHA256
# define CONFIG_IMAGE_FORMAT_LEGACY
#endif
/* FIT */
#ifdef CONFIG_FIT
# define CONFIG_HASH_VERIFY
-# define CONFIG_SHA1
-# define CONFIG_SHA256
# define CONFIG_IMAGE_FORMAT_LEGACY
#endif
/* FIT */
#ifdef CONFIG_FIT
# define CONFIG_HASH_VERIFY
-# define CONFIG_SHA1
-# define CONFIG_SHA256
# define CONFIG_IMAGE_FORMAT_LEGACY
#endif
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
#define CONFIG_CMD_PCI
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_RTC4543 1 /* use external RTC */
-
-/*
- * Software (bit-bang) three wire serial configuration
- *
- * Note that we need the ifdefs because otherwise compilation of
- * mkimage.c fails.
- */
-#define CONFIG_SOFT_TWS 1
-
-#ifdef TWS_IMPLEMENTATION
-#include <mpc5xxx.h>
-#include <asm/io.h>
-
-#define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
-#define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
-#define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
-#define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
-
-static inline void tws_ce(unsigned bit)
-{
- struct mpc5xxx_wu_gpio *wu_gpio =
- (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
- if (bit)
- setbits_8(&wu_gpio->dvo, TWS_CE);
- else
- clrbits_8(&wu_gpio->dvo, TWS_CE);
-}
-
-static inline void tws_wr(unsigned bit)
-{
- struct mpc5xxx_wu_gpio *wu_gpio =
- (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
- if (bit)
- setbits_8(&wu_gpio->dvo, TWS_WR);
- else
- clrbits_8(&wu_gpio->dvo, TWS_WR);
-}
-
-static inline void tws_clk(unsigned bit)
-{
- struct mpc5xxx_gpio *gpio =
- (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
- if (bit)
- setbits_8(&gpio->sint_dvo, TWS_CLK);
- else
- clrbits_8(&gpio->sint_dvo, TWS_CLK);
-}
-
-static inline void tws_data(unsigned bit)
-{
- struct mpc5xxx_gpio *gpio =
- (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
- if (bit)
- setbits_8(&gpio->sint_dvo, TWS_DATA);
- else
- clrbits_8(&gpio->sint_dvo, TWS_DATA);
-}
-
-static inline unsigned tws_data_read(void)
-{
- struct mpc5xxx_gpio *gpio =
- (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
- return !!(in_8(&gpio->sint_ival) & TWS_DATA);
-}
-
-static inline void tws_data_config_output(unsigned output)
-{
- struct mpc5xxx_gpio *gpio =
- (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
- if (output)
- setbits_8(&gpio->sint_ddr, TWS_DATA);
- else
- clrbits_8(&gpio->sint_ddr, TWS_DATA);
-}
-#endif /* TWS_IMPLEMENTATION */
-
/*
* Miscellaneous configurable options
*/
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-/* I2C SYSMON */
-#define CONFIG_DTT_LM63 1 /* National LM63 */
-#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
-#define CONFIG_DTT_PWM_LOOKUPTABLE \
- { { 40, 10 }, { 50, 20 }, { 60, 40 } }
-#define CONFIG_DTT_TACH_LIMIT 0xa10
-
/* RTC configuration */
#define CONFIG_RTC_DS1337 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_DTT
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66
-/* new uImage format support */
-#define CONFIG_FIT_DISABLE_SHA256
-
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
/*
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_IRQ
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
/* Temp sensor/hwmon/dtt */
-#define CONFIG_DTT_LM63 1 /* National LM63 */
-#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
-#define CONFIG_DTT_PWM_LOOKUPTABLE \
- { { 40, 10 }, { 50, 20 }, { 60, 40 } }
-#define CONFIG_DTT_TACH_LIMIT 0xa10
/*
* FLASH organization
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-/* Temp sensor/hwmon/dtt */
-#define CONFIG_DTT_LM63 1 /* National LM63 */
-#define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */
-#define CONFIG_DTT_PWM_LOOKUPTABLE \
- { { 40, 10 }, { 43, 13 }, { 46, 16 }, \
- { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
-#define CONFIG_DTT_TACH_LIMIT 0xa10
-
/*-----------------------------------------------------------------------
* Ethernet
*----------------------------------------------------------------------*/
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_DTT
#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
#define PLLMR0_DEFAULT PLLMR0_266_133_66
#define PLLMR1_DEFAULT PLLMR1_266_133_66
-/* new uImage format support */
-#define CONFIG_FIT_DISABLE_SHA256
-
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
/*
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_FPGAD
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_IRQ
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
/*
* U-Boot commands
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVES
#ifdef CONFIG_CMD_BDI
/* defines for SPL */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE /* IDE harddisk support */
-#define CONFIG_CMD_IRQ /* irqinfo */
#define CONFIG_CMD_PCI /* pciinfo */
#define CONFIG_SYS_LOWBOOT 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
-/* I2C DTT */
-#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
-#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
-/*
- * standard dtt sensor configuration - bottom bit will determine local or
- * remote sensor of the ADM1021, the rest determines index into
- * CONFIG_SYS_DTT_ADM1021 array below.
- */
-#define CONFIG_DTT_SENSORS { 0, 1 }
-
-/*
- * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
- * there will be one entry in this array for each two (dummy) sensors in
- * CONFIG_DTT_SENSORS.
- *
- * For Katmai board:
- * - only one ADM1021
- * - i2c addr 0x18
- * - conversion rate 0x02 = 0.25 conversions/second
- * - ALERT ouput disabled
- * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
- * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
- */
-#define CONFIG_SYS_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
-
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_ECCTEST
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024)
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-#define CONFIG_SPL_BOARD_INIT
/*
* Console
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-/* Standard DTT sensor configuration */
-#define CONFIG_DTT_DS1775 1
-#define CONFIG_DTT_SENSORS { 0 }
-#define CONFIG_SYS_I2C_DTT_ADDR 0x48
-
/* RTC configuration */
#define CONFIG_RTC_DS1338 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MTDPARTS
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
#define CONFIG_BOOTCOUNT_LIMIT
-#define CONFIG_CMD_DTT
#define CONFIG_JFFS2_CMDLINE
/* standard km ethernet_present for piggy */
#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-#define CONFIG_SYS_DTT_BUS_NUM 1
-
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
* additionnal command line configuration.
*/
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_ERRATA
/* we don't need flash support */
#undef CONFIG_FLASH_CFI_MTD
int get_scl(void);
#endif
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-#define CONFIG_SYS_DTT_BUS_NUM 2
-
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_IMMR 0xF0000000
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_IDE
#ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */
#endif
*/
#ifdef CONFIG_CMD_I2C
/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* Command line configuration */
-#define CONFIG_CMD_ENV
#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_HZ 1000
/* EEPROM */
#define CONFIG_ID_EEPROM
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_MISC_INIT_R
-/* Hash command with SHA acceleration supported in hardware */
-
-#ifdef CONFIG_FSL_CAAM
-
-#define CONFIG_CMD_HASH
-
-#define CONFIG_SHA_HW_ACCEL
-
-#endif
-
#include <asm/fsl_secure_boot.h>
#endif
#define CONFIG_MISC_INIT_R
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#define CONFIG_MISC_INIT_R
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#endif
/* Command line configuration */
-#ifndef SPL_NO_ENV
-#define CONFIG_CMD_ENV
-#endif
/* MMC */
#ifndef SPL_NO_MMC
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#endif /* __LS1043A_COMMON_H */
#define CONFIG_SYS_I2C_MXC_I2C4
/* Command line configuration */
-#ifndef SPL_NO_ENV
-#define CONFIG_CMD_ENV
-#endif
/* MMC */
#ifndef SPL_NO_MMC
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#endif /* __LS1046A_COMMON_H */
#endif
/* Command line configuration */
-#define CONFIG_CMD_ENV
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
#endif /* __LS2_COMMON_H */
/* EEPROM */
#define CONFIG_ID_EEPROM
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
/* EEPROM */
#define CONFIG_ID_EEPROM
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_IDE
/*
* mv-common.h should be defined after CMD configs since it used them
#undef CONFIG_RESET_PHY_R
#endif /* CONFIG_CMD_NET */
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#undef CONFIG_IDE_LED
#undef CONFIG_SYS_IDE_MAXBUS
#define CONFIG_SYS_IDE_MAXBUS 1
/*
* Command line configuration.
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_TEXT_BASE 0x70008000
#define CONFIG_SPL_PAD_TO 0x8000
#define CONFIG_SPL_STACK 0x70004000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* Standard DTT sensor configuration */
-#define CONFIG_DTT_DS1775 1
-#define CONFIG_DTT_SENSORS { 0 }
-#define CONFIG_SYS_I2C_DTT_ADDR 0x48
-
/* RTC configuration */
#define CONFIG_RTC_X1205 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_DTT
#define CONFIG_CMD_PCI
/* POST support */
/*
* Commands
*/
-#define CONFIG_CMD_IDE
#define CONFIG_CMD_PCI
#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#include "imx6_spl.h"
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
#define CONFIG_SPL_OS_BOOT
#define CONFIG_USB_ETHER_MCS7830
/* commands to include */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_UBIFS
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
#define CONFIG_CMD_REGINFO
-#undef CONFIG_CMD_FUSE
-#undef CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
/*
* Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
#define GICD_BASE 0xc4301000
#define GICC_BASE 0xc4302000
-#define CONFIG_CMD_ENV
-
/* Monitor Command Prompt */
/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL
#if defined(FLASH)
-# define CONFIG_CMD_JFFS2
# undef CONFIG_CMD_UBIFS
# if !defined(RAMENV)
# define CONFIG_CMD_SAVES
# endif
#else
-# undef CONFIG_CMD_JFFS2
# undef CONFIG_CMD_UBIFS
#endif
#endif
/* SPL part */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
/*
* Command line configuration.
*/
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
/*
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO
-#undef CONFIG_CMD_FUSE
-
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
"1m(u-boot);" \
"mpc5121.nand:-(data)"
-#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
+#if defined(CONFIG_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
#define CONFIG_SUPPORT_VFAT
-#endif /* defined(CONFIG_CMD_IDE) */
+#endif /* defined(CONFIG_IDE) */
/*
* Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCMCIA
-#define CONFIG_CMD_IDE
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_BOOTFILE "/boot/zImage"
#define CONFIG_CPU_SH7722 1
#define CONFIG_MS7722SE 1
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_SDRAM
#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
/*
* FPGA
*/
-#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_CMD_KGDB)
* File system
*/
#ifdef CONFIG_SYS_MVFS
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
*/
#ifdef CONFIG_SYS_MVFS
#define CONFIG_BZIP2
-#define CONFIG_LZMA
#endif /* CONFIG_SYS_MVFS */
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_IDE
/*
* Extra file system
* Hardware drivers
*/
#define CONFIG_FSL_IIM
-#define CONFIG_CMD_FUSE
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_FSL_USDHC
/* Fuses */
-#define CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
/* Secure boot (HAB) support */
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
-#define CONFIG_CMD_HDMIDETECT
#define CONFIG_IMX_VIDEO_SKIP
/* USB */
#define CONFIG_FSL_USDHC
/* Fuses */
-#define CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
#define CONFIG_ARMV7_SECURE_BASE 0x00900000
* Commands configuration
*/
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_IDE
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
/*
* File system
*/
-#define CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_NAND
#define CONFIG_JFFS2_LZO
#define CONFIG_CMD_UBIFS
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-/* new uImage format support */
-#define CONFIG_FIT_DISABLE_SHA256
-
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
/*
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_IRQ
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-/* Temp sensor/hwmon/dtt */
-#define CONFIG_DTT_LM63 1 /* National LM63 */
-#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
-#define CONFIG_DTT_PWM_LOOKUPTABLE \
- { { 40, 10 }, { 50, 20 }, { 60, 40 } }
-#define CONFIG_DTT_TACH_LIMIT 0xa10
-
/*
* FLASH organization
*/
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024)
#define CONFIG_BMP_16BPP
#define CONFIG_IPUV3_CLK 260000000
-#define CONFIG_CMD_HDMIDETECT
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#include "mx6_common.h"
/* U-Boot Commands */
-#define CONFIG_CMD_EEPROM
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SATA
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_IPUV3_CLK 260000000
-#define CONFIG_CMD_HDMIDETECT
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#endif
/* compression configuration */
#define CONFIG_BZIP2
-#define CONFIG_LZMA
/* commands configuration */
#define CONFIG_SYS_MVFS
-#define CONFIG_CMD_IDE
/*
* mv-common.h should be defined after CMD configs since it used them
#endif /* CONFIG_CMD_NET */
/* SATA driver configuration */
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT0
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
-#endif /* CONFIG_CMD_IDE */
+#endif /* CONFIG_IDE */
/* RTC driver configuration */
#ifdef CONFIG_CMD_DATE
/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */
#undef CONFIG_EXYNOS_TMU
-#undef CONFIG_TMU_CMD_DTT
#define CONFIG_DFU_ALT_SYSTEM \
"uImage fat 0 1;" \
* ----------------------------------------------------------------------------
*/
-#define CONFIG_CMD_JFFS2
-
#define CONFIG_CMD_NAND
/* ----------------------------------------------------------------------------
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_OMAP3_ID_NAND
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/*
* U-Boot commands
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVES
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
!defined(CONFIG_USE_SPIFLASH)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (16 << 10)
-#undef CONFIG_CMD_ENV
#endif
/* SD/MMC */
#ifndef CONFIG_DIRECT_NOR_BOOT
/* defines for SPL */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
* Commands configuration
*/
#define CONFIG_SYS_MVFS
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_IDE
/*
* mv-common.h should be defined after CMD configs since it used them
#define CONFIG_SYS_I2C_SPEED 100000
/* OCOTP Configs */
-#define CONFIG_CMD_IMXOTP
#define CONFIG_IMX_OTP
#define IMX_OTP_BASE OCOTP_BASE_ADDR
#define IMX_OTP_ADDR_MAX 0x7F
#define CONFIG_PHY_SMSC
#ifndef CONFIG_SPL
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_BUS 1
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
/* enable read and write access to EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
/*
#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
/* enable read and write access to EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
/*
* Command line configuration.
*/
-#undef CONFIG_CMD_IDE
-
#endif /* __CONFIG_H */
/*
* Command line configuration.
*/
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_PCI
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* I2C Configuration */
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_RTC_BUS_NUM 2
/* EEPROM (24FC256) */
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_BUS 2
#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
/* Various command support */
-#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */
-#define CONFIG_CMD_GSC
-#define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */
#define CONFIG_RBTREE
/* Physical Memory Map */
#define CONFIG_CMD_REGINFO
-#undef CONFIG_CMD_FUSE
-
/*
* Miscellaneous configurable options
*/
/* I2C Configuration */
#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#endif
-#define CONFIG_CMD_JFFS2 1
#define CONFIG_JFFS2_CMDLINE 1
#define CONFIG_JFFS2_NAND 1
#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
*/
#define CONFIG_CMD_NAND 1
-#define CONFIG_CMD_JFFS2 1
#define CONFIG_JFFS2_CMDLINE 1
#define CONFIG_JFFS2_NAND 1
#define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */
* Commands configuration
*/
#define CONFIG_SYS_MVFS
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_NAND
/*
/*
* File system
*/
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_SYS_NS16550_COM1 0xb40003f8
#define CONFIG_CONS_INDEX 1
-#define CONFIG_CMD_IDE
-
#ifdef CONFIG_SYS_BIG_ENDIAN
#define CONFIG_IDE_SWAP_IO
#endif
#define MEM_SIZE 128
-#define CONFIG_LZMA
-
#endif /* __CONFIG_H */
#define CONFIG_SYS_NS16550_COM1 0xffffffffb40003f8
#define CONFIG_CONS_INDEX 1
-#define CONFIG_CMD_IDE
-
#ifdef CONFIG_SYS_BIG_ENDIAN
#define CONFIG_IDE_SWAP_IO
#endif
#define MEM_SIZE 128
-#define CONFIG_LZMA
-
#endif /* __CONFIG_H */
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IRQ
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
* - AHCI controller is supported for QEMU '-M q35' target
*
* Default configuraion is to support the QEMU default x86 target
- * Undefine CONFIG_CMD_IDE to support q35 target
+ * Undefine CONFIG_IDE to support q35 target
*/
-#define CONFIG_CMD_IDE
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#define CONFIG_SYS_IDE_MAXBUS 2
#define CONFIG_SYS_IDE_MAXDEVICE 4
#define CONFIG_SYS_ATA_BASE_ADDR 0
#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_ENV
#define CONFIG_BOOTARGS "console=ttySC3,115200"
* Command line configuration.
*/
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IDE
#define CONFIG_CMD_SH_ZIMAGEBOOT
/* SCIF */
*/
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IDE
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#endif
/* Compact flash Support */
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_IDE)
#define CONFIG_IDE_RESET 1
#define CONFIG_SYS_PIO_MODE 1
#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
#define CONFIG_IDE_SWAP_IO
-#endif /* CONFIG_CMD_IDE */
+#endif /* CONFIG_IDE */
#endif /* __R7780RP_H */
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SPL_BOARD_INIT
#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NS16550_MEM32
-#define CONFIG_SPL_BOARD_INIT
#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x0 once return from SPL */
#define CONFIG_LOADADDR 0xC307FFC0
#define CONFIG_BOOTARGS "console=ttyLF0 root=/dev/ram rw"
-#define CONFIG_CMD_ENV
#define CONFIG_EXTRA_ENV_SETTINGS \
"boot_scripts=boot.scr.uimg boot.scr\0" \
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_SERIALFLASH
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
#ifndef CONFIG_SPL_BUILD
#define CONFIG_IO_TRACE
-#define CONFIG_CMD_IOTRACE
#endif
#ifndef CONFIG_TIMER
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IO
#define CONFIG_FS_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_IP_DEFRAG
-/* Can't boot elf images */
-
-#define CONFIG_CMD_HASH
#define CONFIG_HASH_VERIFY
-#define CONFIG_SHA1
-#define CONFIG_SHA256
#define CONFIG_CMD_SANDBOX
-#define CONFIG_CMD_ENV_FLAGS
-#define CONFIG_CMD_ENV_CALLBACK
-
#define CONFIG_BOOTARGS ""
#ifndef SANDBOX_NO_SDL
#define CONFIG_GZIP_COMPRESSED
#define CONFIG_BZIP2
#define CONFIG_LZO
-#define CONFIG_LZMA
-
-#define CONFIG_CMD_LZMADEC
#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_IDE
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_ATA_IDE0_OFFSET 0
#define CONFIG_SYS_IDE_MAXDEVICE 2
#include <configs/sandbox.h>
-#define CONFIG_SPL_BOARD_INIT
-
#define CONFIG_SPL_FRAMEWORK
#endif
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_AD7414 1 /* use AD7414 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
/*
* Default environment variables
*/
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_DTT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
* Command line configuration.
*/
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_JFFS2
#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
#define CONFIG_ENV_OVERWRITE 1
/*
* SATA driver configuration
*/
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT0
#define CONFIG_MVSATA_IDE_USE_PORT1
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
-#endif /* CONFIG_CMD_IDE */
+#endif /* CONFIG_IDE */
#endif /* _CONFIG_SHEEVAPLUG_H */
/* #define CONFIG_T_SH7706LSR 1 */
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_ENV
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_AM33XX_BCH
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
#define CONFIG_SYS_USE_NANDFLASH 1
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
-#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SPL_BOARD_INIT
-#endif
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG
-#define CONFIG_CMD_EEPROM
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */
/* I2C W83782G HW-Monitoring IC */
#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
-/* I2C temp sensor */
-/* Socrates uses Maxim's DS75, which is compatible with LM75 */
-#define CONFIG_DTT_LM75 1
-#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 125
-#define CONFIG_SYS_DTT_LOW_TEMP -55
-#define CONFIG_SYS_DTT_HYSTERESIS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
/*
/*
* Command line configuration.
*/
-#define CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_REGINFO
* Command support defines
*/
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVES
/*
#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_CMD_FPGAD
-#define CONFIG_CMD_IOLOOP
-
/*
* System Clock Setup
*/
# define CONFIG_MACH_TYPE_COMPAT_REV 1
#endif
+#ifdef CONFIG_ARM64
+#define CONFIG_BUILD_TARGET "u-boot.itb"
+#endif
+
/* Serial & console */
#define CONFIG_SYS_NS16550_SERIAL
/* ns16550 reg in the low bits of cpu reg */
#endif
#ifdef CONFIG_SUNXI_HIGH_SRAM
-#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */
-#define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB */
+#define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */
+#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
+#ifdef CONFIG_ARM64
+/* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */
+#define LOW_LEVEL_SRAM_STACK 0x00054000
+#else
#define LOW_LEVEL_SRAM_STACK 0x00018000
+#endif /* !CONFIG_ARM64 */
#else
-#define CONFIG_SPL_TEXT_BASE 0x40 /* sram start+header */
-#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* 24KB on sun4i/sun7i */
+#define CONFIG_SPL_TEXT_BASE 0x60 /* sram start+header */
+#define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */
#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
#endif
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_ECCTEST
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
/*
* Command line configuration.
*/
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
/* commands to include */
#define CONFIG_CMD_NAND /* NAND support */
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_CONSOLE
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512)
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
#define CONFIG_SYS_USE_NANDFLASH 1
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
-#define CONFIG_CMD_HDMIDETECT
#endif
/* PCI */
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_CMD_ENTERRCM
-
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
CONFIG_SPL_TEXT_BASE)
/*
* Commands configuration
*/
-#define CONFIG_CMD_ENV
#define CONFIG_CMD_SATA
/*
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-#define CONFIG_SPL_BOARD_INIT
-
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-#define CONFIG_SPL_BOARD_INIT
-
#define CONFIG_SYS_TEXT_BASE 0x80800000
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#endif
/* General parts of the framework, required. */
-#define CONFIG_SPL_BOARD_INIT
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_BASE
/* U-Boot command configuration */
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_EEPROM
/* U-Boot general configuration */
#define CONFIG_MISC_INIT_R
#undef CONFIG_SPL_FPGA_SUPPORT
/* FPGA commands that we don't use */
-#undef CONFIG_CMD_FPGA_LOADMK
-#undef CONFIG_CMD_FPGA_LOADP
-#undef CONFIG_CMD_FPGA_LOADBP
-#undef CONFIG_CMD_FPGA_LOADFS
/* Extras */
#define CONFIG_CMD_MEMTEST
"console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
#define CONFIG_BOOTCOMMAND \
"dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr"
-#define CONFIG_LZMA
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 100000
-/* I2C SYSMON (LM75) */
-#define CONFIG_DTT_LM75
-#define CONFIG_DTT_MAX_TEMP 70
-#define CONFIG_DTT_MIN_TEMP -30
-#define CONFIG_DTT_HYSTERESIS 3
-#define CONFIG_CMD_DTT
-
/* I2C EEPROM (M24C64) */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */
#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CONFIG_CMD_EEPROM
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#endif
/* Support at least the sensor on TQMa6 SOM */
-#if !defined(CONFIG_DTT_SENSORS)
-#define CONFIG_DTT_SENSORS { 0 }
-#endif
#endif /* __CONFIG_H */
#ifndef __CONFIG_TQMA6_MBA6_H
#define __CONFIG_TQMA6_MBA6_H
-#define CONFIG_DTT_SENSORS { 0, 1 }
-
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#ifndef __CONFIG_TQMA6_WRU4_H
#define __CONFIG_TQMA6_WRU4_H
-/* DTT sensors */
-#define CONFIG_DTT_SENSORS { 0, 1 }
-#define CONFIG_SYS_DTT_BUS_NUM 2
-
/* Ethernet */
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
/* EEPROM */
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_BUS_NUM 1
#define CONFIG_CMD_UBIFS /* UBIFS commands */
#define CONFIG_LZO /* LZO is needed for UBIFS */
-#undef CONFIG_CMD_JFFS2 /* JFFS2 Support */
-
/* needed for ubi */
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
0x600000)
#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
-#define CONFIG_SPL_BOARD_INIT
#endif /* __CONFIG_H */
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#endif
-#define CONFIG_SPL_BOARD_INIT
-
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
/* subtract sizeof(struct image_header) */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
/* Fuse */
-#define CONFIG_CMD_FUSE
#define CONFIG_FSL_IIM
/* U-Boot memory offsets */
/*
* Command line configuration.
*/
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_SDRAM
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* Commands
*/
-#define CONFIG_CMD_EEPROM
/*
* Only Premium/Platinum have ethernet support right now
*/
#if defined(CONFIG_VCT_ONENAND)
#define CONFIG_SYS_USE_UBI
-#define CONFIG_CMD_JFFS2
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
* (NOR/OneNAND) usage and Linux kernel booting.
*/
#if defined(CONFIG_VCT_SMALL_IMAGE)
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_IRQ
-#undef CONFIG_CMD_LOADY
#undef CONFIG_CMD_REGINFO
#undef CONFIG_CMD_STRINGS
#undef CONFIG_CMD_TERMINAL
#endif
/*#define CONFIG_MENU_SHOW*/
-#define CONFIG_CMD_ENV
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
/* Enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG
-#define CONFIG_CMD_FUSE
#ifdef CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
#endif
#define CONFIG_CMD_PCI
#endif
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
-#endif
-
/* Pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IPUV3_CLK 260000000
-#define CONFIG_CMD_HDMIDETECT
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#endif
*/
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds"
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_TEXT_BASE 0x10002300
#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */
* I2C EEPROM
*/
-#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_RTC_DS1374
-/*
- * I2C Temperature Sensor (DTT)
- */
-
-#define CONFIG_CMD_DTT
-#define CONFIG_DTT_SENSORS { 0, 1 }
-#define CONFIG_DTT_DS620
-
/*
* U-Boot General Configurations
*/
#define CONFIG_LPC32XX_SSP
#define CONFIG_LPC32XX_SSP_TIMEOUT 100000
#define CONFIG_CMD_MAX6957
-#define CONFIG_CMD_HD44760
/*
* Environment
*/
#define CONFIG_SPL_TEXT_BASE 0x00000000
/* SPL will use SRAM as stack */
#define CONFIG_SPL_STACK 0x0000FFF8
-#define CONFIG_SPL_BOARD_INIT
/* Use the framework and generic lib */
#define CONFIG_SPL_FRAMEWORK
/* SPL will use serial */
/*
* Command support defines
*/
-#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_SAVES
/*-----------------------------------------------------------------------
* Command line configuration.
*/
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_IO
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PCI
-#define CONFIG_CMD_GETTIME
#define CONFIG_SCSI
#define CONFIG_CMD_ZBOOT
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
/*Cmd*/
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO
-#undef CONFIG_CMD_JFFS2
#undef CONFIG_CMD_MTDPARTS
-#undef CONFIG_CMD_DTT
-#undef CONFIG_CMD_EEPROM
/*Misc*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_FLASH_EMPTY_INFO 1
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
{ 4800, 9600, 19200, 38400, 57600, 115200 }
/* Command line configuration */
-#define CONFIG_CMD_ENV
#define CONFIG_MP
/* BOOTP options */
/* EEPROM */
#ifdef CONFIG_ZYNQMP_EEPROM
-# define CONFIG_CMD_EEPROM
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
/* u-boot is like dtb */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin"
#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS 5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20
/*
* Command configuration
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_PCI
/*
#define CONFIG_SYS_MEMTEST_END 0x20000000
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
CONFIG_SYS_POST_I2C)
-#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
- CONFIG_SYS_I2C_DS4510_ADDR, \
- CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_LM90_ADDR, \
- CONFIG_SYS_I2C_PCA9553_ADDR, \
- CONFIG_SYS_I2C_PCA953X_ADDR0, \
- CONFIG_SYS_I2C_PCA953X_ADDR1, \
- CONFIG_SYS_I2C_PCA953X_ADDR2, \
- CONFIG_SYS_I2C_PCA953X_ADDR3, \
- CONFIG_SYS_I2C_PEX8518_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR}
/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
#define I2C_ADDR_IGNORE_LIST {0x50}
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
/* I2C DS1631 temperature sensor */
-#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
-#define CONFIG_DTT_DS1621
-#define CONFIG_DTT_SENSORS { 0 }
#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-/* GPIO/EEPROM/SRAM */
-#define CONFIG_DS4510
-#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
-
/* GPIO */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
/*
* Command configuration.
*/
-#define CONFIG_CMD_DS4510
-#define CONFIG_CMD_DS4510_INFO
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
/*
* Command configuration.
*/
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_SYS_MEMTEST_END 0x20000000
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
CONFIG_SYS_POST_I2C)
-#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
- CONFIG_SYS_I2C_DS4510_ADDR, \
- CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_LM90_ADDR, \
- CONFIG_SYS_I2C_PCA953X_ADDR0, \
- CONFIG_SYS_I2C_PCA953X_ADDR1, \
- CONFIG_SYS_I2C_PCA953X_ADDR2, \
- CONFIG_SYS_I2C_PCA953X_ADDR3, \
- CONFIG_SYS_I2C_PEX8518_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR}
/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
#define I2C_ADDR_IGNORE_LIST {0x50}
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
/* I2C DS1631 temperature sensor */
-#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
-#define CONFIG_DTT_DS1621
-#define CONFIG_DTT_SENSORS { 0 }
#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-/* GPIO/EEPROM/SRAM */
-#define CONFIG_DS4510
-#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
-
/* GPIO */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
/*
* Command configuration.
*/
-#define CONFIG_CMD_DS4510
-#define CONFIG_CMD_DS4510_INFO
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
/* I2C DS7505 temperature sensor */
-#define CONFIG_DTT_LM75
-#define CONFIG_DTT_SENSORS { 0 }
#define CONFIG_SYS_I2C_LM75_ADDR 0x48
/* I2C ADT7461 temperature sensor */
/*
* Command configuration.
*/
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_ENV_OFFSET 0x0
#endif /* CONFIG_ENV_IS_IN_EEPROM */
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#define CONFIG_DTT_AD7414 1 /* use AD7414 */
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-
/*
* Default environment variables
*/
/*
* Commands additional to the ones defined in amcc-common.h
*/
-#define CONFIG_CMD_DTT
#define CONFIG_CMD_PCI
#ifdef CONFIG_440EP
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_TEXT_BASE 0x0
-#define CONFIG_LZMA /* LZMA compression support */
/*
* Serial Console Configuration
/*
* Bootloader Components Configuration
*/
-#define CONFIG_CMD_ENV
/*
* MMC Card Configuration
/* EEPROM */
#ifdef CONFIG_ZYNQ_EEPROM
-# define CONFIG_CMD_EEPROM
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_ZYNQPL
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_FPGA_LOADP
-#define CONFIG_CMD_FPGA_LOADBP
-#define CONFIG_CMD_FPGA_LOADFS
/* FIT support */
#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
/* SPL part */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds"
#define CONFIG_ZYNQ_I2C0
#define CONFIG_ZYNQ_I2C1
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x50
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA
#define CONFIG_DISPLAY
+++ /dev/null
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef __DS4510_H_
-#define __DS4510_H_
-
-/* General defines */
-#define DS4510_NUM_IO 0x04
-#define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1)
-#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20
-
-/* EEPROM from 0x00 - 0x39 */
-#define DS4510_EEPROM 0x00
-#define DS4510_EEPROM_SIZE 0x40
-#define DS4510_EEPROM_PAGE_SIZE 0x08
-#define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1))
-
-/* SEEPROM from 0xf0 - 0xf7 */
-#define DS4510_SEEPROM 0xf0
-#define DS4510_SEEPROM_SIZE 0x08
-
-/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */
-#define DS4510_PULLUP 0xF0
-#define DS4510_PULLUP_DIS 0x00
-#define DS4510_PULLUP_EN 0x01
-#define DS4510_RSTDELAY 0xF1
-#define DS4510_RSTDELAY_MASK 0x03
-#define DS4510_RSTDELAY_125 0x00
-#define DS4510_RSTDELAY_250 0x01
-#define DS4510_RSTDELAY_500 0x02
-#define DS4510_RSTDELAY_1000 0x03
-#define DS4510_IO3 0xF4
-#define DS4510_IO2 0xF5
-#define DS4510_IO1 0xF6
-#define DS4510_IO0 0xF7
-
-/* Status configuration registers from 0xf8 - 0xf9*/
-#define DS4510_IO_STATUS 0xF8
-#define DS4510_CFG 0xF9
-#define DS4510_CFG_READY 0x80
-#define DS4510_CFG_TRIP_POINT 0x40
-#define DS4510_CFG_RESET 0x20
-#define DS4510_CFG_SEE 0x10
-#define DS4510_CFG_SWRST 0x08
-
-/* SRAM from 0xfa - 0xff */
-#define DS4510_SRAM 0xfa
-#define DS4510_SRAM_SIZE 0x06
-
-int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count);
-int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count);
-int ds4510_see_write(uint8_t chip, uint8_t nv);
-int ds4510_rstdelay_write(uint8_t chip, uint8_t delay);
-int ds4510_pullup_write(uint8_t chip, uint8_t val);
-int ds4510_pullup_read(uint8_t chip);
-int ds4510_gpio_write(uint8_t chip, uint8_t val);
-int ds4510_gpio_read(uint8_t chip);
-int ds4510_gpio_read_val(uint8_t chip);
-
-#endif /* __DS4510_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Digital Thermometers and Thermostats.
- */
-#ifndef _DTT_H_
-#define _DTT_H_
-
-#if defined(CONFIG_DTT_ADM1021) || \
- defined(CONFIG_DTT_ADT7460) || \
- defined(CONFIG_DTT_DS1621) || \
- defined(CONFIG_DTT_DS1775) || \
- defined(CONFIG_DTT_DS620) || \
- defined(CONFIG_DTT_LM63) || \
- defined(CONFIG_DTT_LM73) || \
- defined(CONFIG_DTT_LM75) || \
- defined(CONFIG_DTT_LM81)
-
-#define CONFIG_DTT /* We have a DTT */
-
-#ifndef CONFIG_DTT_ADM1021
-#define DTT_COMMERCIAL_MAX_TEMP 70 /* 0 - +70 C */
-#define DTT_INDUSTRIAL_MAX_TEMP 85 /* -40 - +85 C */
-#define DTT_AUTOMOTIVE_MAX_TEMP 105 /* -40 - +105 C */
-
-#ifndef CONFIG_SYS_DTT_MAX_TEMP
-#define CONFIG_SYS_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP
-#endif
-
-#ifndef CONFIG_SYS_DTT_HYSTERESIS
-#define CONFIG_SYS_DTT_HYSTERESIS 5 /* 5 C */
-#endif
-#endif /* CONFIG_DTT_ADM1021 */
-
-extern void dtt_init(void);
-extern int dtt_init_one(int);
-extern int dtt_read(int sensor, int reg);
-extern int dtt_write(int sensor, int reg, int val);
-extern int dtt_get_temp(int sensor);
-#endif
-
-#endif /* _DTT_H_ */
#if !defined(CONFIG_SYS_RTC_BUS_NUM)
#define CONFIG_SYS_RTC_BUS_NUM 0
#endif
-#if !defined(CONFIG_SYS_DTT_BUS_NUM)
-#define CONFIG_SYS_DTT_BUS_NUM 0
-#endif
#if !defined(CONFIG_SYS_SPD_BUS_NUM)
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif
#define IMAGE_ENABLE_FIT 1
#define IMAGE_ENABLE_OF_LIBFDT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_ENABLE_SHA256_SUPPORT
+#define CONFIG_SHA1
+#define CONFIG_SHA256
#define IMAGE_ENABLE_IGNORE 0
#define IMAGE_INDENT_STRING ""
# ifdef CONFIG_SPL_SHA1_SUPPORT
# define IMAGE_ENABLE_SHA1 1
# endif
-# ifdef CONFIG_SPL_SHA256_SUPPORT
-# define IMAGE_ENABLE_SHA256 1
-# endif
# else
# define CONFIG_CRC32 /* FIT images need CRC32 support */
-# define CONFIG_SHA1 /* and SHA1 */
-# define CONFIG_SHA256 /* and SHA256 */
# define IMAGE_ENABLE_CRC32 1
# define IMAGE_ENABLE_MD5 1
# define IMAGE_ENABLE_SHA1 1
-# define IMAGE_ENABLE_SHA256 1
# endif
-#ifdef CONFIG_FIT_DISABLE_SHA256
-#undef CONFIG_SHA256
-#undef IMAGE_ENABLE_SHA256
-#endif
-
#ifndef IMAGE_ENABLE_CRC32
#define IMAGE_ENABLE_CRC32 0
#endif
#define IMAGE_ENABLE_SHA1 0
#endif
-#ifndef IMAGE_ENABLE_SHA256
+#if defined(CONFIG_FIT_ENABLE_SHA256_SUPPORT) || \
+ defined(CONFIG_SPL_SHA256_SUPPORT)
+#define IMAGE_ENABLE_SHA256 1
+#else
#define IMAGE_ENABLE_SHA256 0
#endif
* or try to generate a useful default
*/
#if defined(CONFIG_CMD_PCMCIA) || \
- (defined(CONFIG_CMD_IDE) && \
+ (defined(CONFIG_IDE) && \
(defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
#endif
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
extern int check_ide_device(int slot);
#endif
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _TWS_H_
-#define _TWS_H_
-
-/*
- * Read/Write interface:
- * buffer: Where to read/write the data
- * len: How many bits to read/write
- *
- * Returns: 0 on success, not 0 on failure
- */
-int tws_read(uchar *buffer, int len);
-int tws_write(uchar *buffer, int len);
-
-#endif /* _TWS_H_ */
frame format currently (2015) implemented in the Linux kernel
(generated by 'lz4 -l'). The two formats are incompatible.
+config LZMA
+ bool "Enable LZMA decompression support"
+ help
+ This enables support for LZMA (Lempel-Ziv-Markov chain algorithm),
+ a dictionary compression algorithm that provides a high compression
+ ratio and fairly fast decompression speed. See also
+ CONFIG_CMD_LZMADEC which provides a decode command.
+
config LZO
bool
endmenu
obj-y += list_sort.o
endif
-obj-$(CONFIG_$(SPL_)RSA) += rsa/
-obj-$(CONFIG_$(SPL_)SHA1) += sha1.o
-obj-$(CONFIG_$(SPL_)SHA256) += sha256.o
+obj-$(CONFIG_RSA) += rsa/
+obj-$(CONFIG_SHA1) += sha1.o
+obj-$(CONFIG_SHA256) += sha256.o
obj-$(CONFIG_SPL_SAVEENV) += qsort.o
obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/
$(call if_changed,mkimage)
quiet_cmd_mksunxiboot = MKSUNXI $@
-cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@
+cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \
+ --default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@
$(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE
$(call if_changed,mksunxiboot)
CONFIG_CMDLINE_EDITING
CONFIG_CMDLINE_PS_SUPPORT
CONFIG_CMDLINE_TAG
-CONFIG_CMD_DS4510
-CONFIG_CMD_DS4510_INFO
-CONFIG_CMD_DS4510_MEM
-CONFIG_CMD_DS4510_RST
-CONFIG_CMD_DTT
-CONFIG_CMD_ECCTEST
-CONFIG_CMD_EECONFIG
-CONFIG_CMD_EEPROM
-CONFIG_CMD_EEPROM_LAYOUT
-CONFIG_CMD_ENTERRCM
-CONFIG_CMD_ENV
-CONFIG_CMD_ENV_CALLBACK
-CONFIG_CMD_ENV_FLAGS
-CONFIG_CMD_ERRATA
-CONFIG_CMD_ESBC_VALIDATE
-CONFIG_CMD_ETHSW
-CONFIG_CMD_FDC
-CONFIG_CMD_FDT_MAX_DUMP
-CONFIG_CMD_FPGAD
-CONFIG_CMD_FPGA_LOADBP
-CONFIG_CMD_FPGA_LOADFS
-CONFIG_CMD_FPGA_LOADMK
-CONFIG_CMD_FPGA_LOADP
-CONFIG_CMD_FUSE
-CONFIG_CMD_GETTIME
-CONFIG_CMD_GSC
-CONFIG_CMD_HASH
-CONFIG_CMD_HD44760
-CONFIG_CMD_HD44780
-CONFIG_CMD_HDMIDETECT
-CONFIG_CMD_IDE
-CONFIG_CMD_IMMAP
-CONFIG_CMD_IMXOTP
-CONFIG_CMD_IMX_FUSE
-CONFIG_CMD_IO
-CONFIG_CMD_IOLOOP
-CONFIG_CMD_IOTRACE
-CONFIG_CMD_IRQ
-CONFIG_CMD_JFFS2
-CONFIG_CMD_KGDB
-CONFIG_CMD_LOADY
-CONFIG_CMD_LZMADEC
CONFIG_CMD_MAX6957
CONFIG_CMD_MEM
CONFIG_CMD_MFSL
CONFIG_DRIVE_SATA
CONFIG_DRIVE_TYPES
CONFIG_DRIVE_USB
-CONFIG_DS4510
CONFIG_DSP_CLUSTER_START
-CONFIG_DTT
-CONFIG_DTT_AD7414
-CONFIG_DTT_ADM1021
-CONFIG_DTT_DS1621
-CONFIG_DTT_DS1775
-CONFIG_DTT_DS620
-CONFIG_DTT_HYSTERESIS
-CONFIG_DTT_LM63
-CONFIG_DTT_LM75
-CONFIG_DTT_MAX_TEMP
-CONFIG_DTT_MIN_TEMP
-CONFIG_DTT_PWM_LOOKUPTABLE
-CONFIG_DTT_SENSORS
-CONFIG_DTT_TACH_LIMIT
CONFIG_DUOVERO
CONFIG_DV_USBPHY_CTL
CONFIG_DWC2_DFLT_SPEED_FULL
CONFIG_EDB93XX_SDCS3
CONFIG_EEPRO100
CONFIG_EEPRO100_SROM_WRITE
-CONFIG_EEPROM_LAYOUT_HELP_STRING
CONFIG_EFLASH_PROTSECTORS
CONFIG_EHCI_DESC_BIG_ENDIAN
CONFIG_EHCI_HCD_INIT_AFTER_RESET
CONFIG_FILE
CONFIG_FIRMWARE_OFFSET
CONFIG_FIRMWARE_SIZE
-CONFIG_FIT_DISABLE_SHA256
CONFIG_FIXED_PHY
CONFIG_FIXED_PHY_ADDR
CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
CONFIG_LWMON5
CONFIG_LXT971_NO_SLEEP
CONFIG_LYNXKDI
-CONFIG_LZMA
CONFIG_M41T94_SPI_CS
CONFIG_M520x
CONFIG_M52277EVB
CONFIG_RTC_MXS
CONFIG_RTC_PCF8563
CONFIG_RTC_PT7C4338
-CONFIG_RTC_RTC4543
CONFIG_RTC_RV3029
CONFIG_RTC_RX8025
CONFIG_RTC_X1205
CONFIG_SOFT_I2C_GPIO_SDA
CONFIG_SOFT_I2C_READ_REPEATED_START
CONFIG_SOFT_SPI
-CONFIG_SOFT_TWS
CONFIG_SOURCE
CONFIG_SPARSE_RCU_POINTER
CONFIG_SPDDRAM_SILENT
CONFIG_SYS_DSPI_CTAR5
CONFIG_SYS_DSPI_CTAR6
CONFIG_SYS_DSPI_CTAR7
-CONFIG_SYS_DTT_ADM1021
-CONFIG_SYS_DTT_BUS_NUM
-CONFIG_SYS_DTT_HYSTERESIS
-CONFIG_SYS_DTT_LOW_TEMP
-CONFIG_SYS_DTT_MAX_TEMP
-CONFIG_SYS_DTT_MIN_TEMP
CONFIG_SYS_DUART_RST
CONFIG_SYS_DV_CLKMODE
CONFIG_SYS_DV_NOR_BOOT_CFG
CONFIG_SYS_EXTRA_ENV_RELOC
CONFIG_SYS_EXT_SERIAL_CLOCK
CONFIG_SYS_FAST_CLK
-CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
CONFIG_SYS_FAULT_ECHO_LINK_DOWN
CONFIG_SYS_FAULT_MII_ADDR
CONFIG_SYS_FCC_PSMR
CONFIG_SYS_I2C_DAVINCI
CONFIG_SYS_I2C_DIRECT_BUS
CONFIG_SYS_I2C_DPMEM_OFFSET
-CONFIG_SYS_I2C_DS1621_ADDR
-CONFIG_SYS_I2C_DS4510_ADDR
CONFIG_SYS_I2C_DSPIC_2_ADDR
CONFIG_SYS_I2C_DSPIC_ADDR
CONFIG_SYS_I2C_DSPIC_IO_ADDR
CONFIG_SYS_I2C_DSPIC_KEYB_ADDR
-CONFIG_SYS_I2C_DTT_ADDR
CONFIG_SYS_I2C_DVI_ADDR
CONFIG_SYS_I2C_DVI_BUS_NUM
CONFIG_SYS_I2C_EARLY_INIT
CONFIG_TI_KEYSTONE_SERDES
CONFIG_TI_KSNAV
CONFIG_TI_SPI_MMAP
-CONFIG_TMU_CMD_DTT
CONFIG_TMU_TIMER
CONFIG_TOTAL5200
CONFIG_TPL_DRIVERS_MISC_SUPPORT
value = state_test_env.env[var]
validate_set(state_test_env, var, value)
+@pytest.mark.buildconfigspec('cmd_echo')
def test_env_echo_non_existent(state_test_env):
"""Test echoing a variable that doesn't exist."""
response = c.run_command('printenv %s' % var)
assert(response == '## Error: "%s" not defined' % var)
+@pytest.mark.buildconfigspec('cmd_echo')
def test_env_unset_non_existent(state_test_env):
"""Test unsetting a nonexistent variable."""
set_var(state_test_env, var, value)
validate_set(state_test_env, var, value)
+@pytest.mark.buildconfigspec('cmd_echo')
def test_env_unset_existing(state_test_env):
"""Test unsetting a variable."""
# Test basic shell functionality, such as commands separate by semi-colons.
+import pytest
+
+pytestmark = pytest.mark.buildconfigspec('cmd_echo')
+
def test_shell_execute(u_boot_console):
"""Test any shell command."""
#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1)
#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))
-#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */
-#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head))
+#define SUNXI_SRAM_SIZE 0x8000 /* SoC with smaller size are limited before */
+#define SRAM_LOAD_MAX_SIZE (SUNXI_SRAM_SIZE - sizeof(struct boot_file_head))
/*
* BROM (at least on A10 and A20) requires NAND-images to be explicitly aligned
struct boot_img img;
unsigned file_size;
int count;
+ char *tool_name = argv[0];
+ char *default_dt = NULL;
- if (argc < 2) {
- printf("\tThis program makes an input bin file to sun4i " \
- "bootable image.\n" \
- "\tUsage: %s input_file out_putfile\n", argv[0]);
+ /* a sanity check */
+ if ((sizeof(img.header) % 32) != 0) {
+ fprintf(stderr, "ERROR: the SPL header must be a multiple ");
+ fprintf(stderr, "of 32 bytes.\n");
+ return EXIT_FAILURE;
+ }
+
+ /* process optional command line switches */
+ while (argc >= 2 && argv[1][0] == '-') {
+ if (strcmp(argv[1], "--default-dt") == 0) {
+ if (argc >= 3) {
+ default_dt = argv[2];
+ argv += 2;
+ argc -= 2;
+ continue;
+ }
+ fprintf(stderr, "ERROR: no --default-dt arg\n");
+ return EXIT_FAILURE;
+ } else {
+ fprintf(stderr, "ERROR: bad option '%s'\n", argv[1]);
+ return EXIT_FAILURE;
+ }
+ }
+
+ if (argc < 3) {
+ printf("This program converts an input binary file to a sunxi bootable image.\n");
+ printf("\nUsage: %s [options] input_file output_file\n",
+ tool_name);
+ printf("Where [options] may be:\n");
+ printf(" --default-dt arg - 'arg' is the default device tree name\n");
+ printf(" (CONFIG_DEFAULT_DEVICE_TREE).\n");
return EXIT_FAILURE;
}
memcpy(img.header.spl_signature, SPL_SIGNATURE, 3); /* "sunxi" marker */
img.header.spl_signature[3] = SPL_HEADER_VERSION;
+ if (default_dt) {
+ if (strlen(default_dt) + 1 <= sizeof(img.header.string_pool)) {
+ strcpy((char *)img.header.string_pool, default_dt);
+ img.header.dt_name_offset =
+ cpu_to_le32(offsetof(struct boot_file_head,
+ string_pool));
+ } else {
+ printf("WARNING: The SPL header is too small\n");
+ printf(" and has no space to store the dt name.\n");
+ }
+ }
+
gen_check_sum(&img.header);
count = write(fd_out, &img, le32_to_cpu(img.header.length));
projects / oweals / u-boot.git / commitdiff