imx: imx8mm-evk: enable ethernet
authorPeng Fan <peng.fan@nxp.com>
Tue, 22 Oct 2019 03:30:04 +0000 (03:30 +0000)
committerStefano Babic <sbabic@denx.de>
Tue, 5 Nov 2019 09:27:18 +0000 (10:27 +0100)
add phy-reset-gpios to reset phy
Add board_phy_config to configure phy
Enable DM_ETH

Signed-off-by: Peng Fan <peng.fan@nxp.com>
arch/arm/dts/imx8mm-evk-u-boot.dtsi
board/freescale/imx8mm_evk/imx8mm_evk.c
configs/imx8mm_evk_defconfig
include/configs/imx8mm_evk.h

index f62a7cf97d7d9569d328db1d968f3db82dba3c9e..3502602fbb86e9ed22343cfd444fe490988843fe 100644 (file)
 &pinctrl_pmic {
        u-boot,dm-spl;
 };
+
+&fec1 {
+       phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
index e4742338e33068ebf2aaacb36280f5a4f0cacbb2..a0af550f5e2497fe7d2dc9fce71f8f8859f9e20d 100644 (file)
@@ -4,6 +4,11 @@
  */
 
 #include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/arch/clock.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -14,8 +19,40 @@ int dram_init(void)
        return 0;
 }
 
+#if IS_ENABLED(CONFIG_FEC_MXC)
+static int setup_fec(void)
+{
+       struct iomuxc_gpr_base_regs *gpr =
+               (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+       /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+       clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+       return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+       /* enable rgmii rxc skew and phy mode select to RGMII copper */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+       return 0;
+}
+#endif
+
 int board_init(void)
 {
+       if (IS_ENABLED(CONFIG_FEC_MXC))
+               setup_fec();
+
        return 0;
 }
 
index 4cbc62fd8f2f5d10b6ee1b41ae1a6b0ab26e1148..9bf5c45a87542a52d05f3059d4ca9b991e05f15e 100644 (file)
@@ -35,6 +35,9 @@ CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
@@ -62,7 +65,11 @@ CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
index a9d99ec8b7bf71ee0a60a2536d7cf4ac6c54c177..e0c5f5a6265190bf5a207b495d243610cf754f03 100644 (file)
 
 #define CONFIG_SYS_I2C_SPEED           100000
 
+#define CONFIG_ETHPRIME                 "FEC"
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define FEC_QUIRK_ENET_MAC
+
+#define IMX_FEC_BASE                   0x30BE0000
+
 #endif