ARM: dts: k3-am65: Add OSPI DT nodes
authorVignesh Raghavendra <vigneshr@ti.com>
Tue, 4 Feb 2020 05:39:51 +0000 (11:09 +0530)
committerLokesh Vutla <lokeshvutla@ti.com>
Tue, 3 Mar 2020 07:38:13 +0000 (13:08 +0530)
Add OSPI DT nodes to enable OSPI at U-Boot prompt and also to support
OSPI boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
arch/arm/dts/k3-am65-mcu.dtsi
arch/arm/dts/k3-am65.dtsi
arch/arm/dts/k3-am654-base-board-u-boot.dtsi
arch/arm/dts/k3-am654-base-board.dts
arch/arm/dts/k3-am654-r5-base-board.dts

index c42e7553c78f8a104f0c150832993ee08c5e926f..bc9a87210da995a98e3e9e6ba5924b10c17da971 100644 (file)
                        loczrama = <1>;
                };
        };
+
+       fss: fss@47000000 {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               ospi0: spi@47040000 {
+                       compatible = "ti,am654-ospi", "cdns,qspi-nor";
+                       reg = <0x0 0x47040000 0x0 0x100>,
+                               <0x5 0x00000000 0x1 0x0000000>;
+                       interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
+                       cdns,fifo-depth = <256>;
+                       cdns,fifo-width = <4>;
+                       cdns,trigger-address = <0x0>;
+                       clocks = <&k3_clks 248 0>;
+                       assigned-clocks = <&k3_clks 248 0>;
+                       assigned-clock-parents = <&k3_clks 248 2>;
+                       assigned-clock-rates = <166666666>;
+                       power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               ospi1: spi@47050000 {
+                       compatible = "ti,am654-ospi", "cdns,qspi-nor";
+                       reg = <0x0 0x47050000 0x0 0x100>,
+                               <0x7 0x00000000 0x1 0x00000000>;
+                       interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
+                       cdns,fifo-depth = <256>;
+                       cdns,fifo-width = <4>;
+                       cdns,trigger-address = <0x0>;
+                       clocks = <&k3_clks 249 6>;
+                       power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
 };
index 3ead944640a3075863e7672b0762c1d9836cd0fc..3d89bf32a9d14356c1abd1d7503cb5c55e3ac607 100644 (file)
@@ -30,6 +30,8 @@
                i2c3 = &main_i2c1;
                i2c4 = &main_i2c2;
                i2c5 = &main_i2c3;
+               spi0 = &ospi0;
+               spi1 = &ospi1;
        };
 
        chosen { };
                         <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
                         <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
                         <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
-                        <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
+                        <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+                        <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
+                        <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
+                        <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
+                        <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
 
                cbass_mcu: interconnect@28380000 {
                        compatible = "simple-bus";
                                 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
                                 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
                                 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
-                                <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
+                                <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
+                                <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /*  FSS OSPI0 data region 1 */
+                                <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
+                                <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
 
                        cbass_wakeup: interconnect@42040000 {
                                compatible = "simple-bus";
index a349edcfa5fd6d6100c7fddefa3908991468c511..2cbe69ed1504e19311a55cc197ff0e0f21f41015 100644 (file)
@@ -43,6 +43,7 @@
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
+               u-boot,dm-spl;
 
                ti,sci-dev-id = <119>;
 
@@ -59,6 +60,7 @@
                        ti,dma-ring-reset-quirk;
                        ti,sci = <&dmsc>;
                        ti,sci-dev-id = <195>;
+                       u-boot,dm-spl;
                };
 
                mcu_udmap: udmap@285c0000 {
@@ -81,6 +83,7 @@
                                                <0x4>; /* RX_CHAN */
                        ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
                        dma-coherent;
+                       u-boot,dm-spl;
                };
        };
 
                        AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
                >;
        };
+
+       mcu-fss0-ospi0-pins-default {
+               u-boot,dm-spl;
+       };
 };
 
 &main_uart0 {
 &usb1 {
        dr_mode = "peripheral";
 };
+
+&fss {
+       u-boot,dm-spl;
+};
+
+&ospi0 {
+       u-boot,dm-spl;
+
+        flash@0{
+               u-boot,dm-spl;
+       };
+};
index 7ebbf17862555c9c8586c6214c22511e872111eb..375f1d089c7d7acf1499848be004528ac88516c8 100644 (file)
                        AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
                >;
        };
+
+       mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
+               pinctrl-single,pins = <
+                       AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
+                       AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)   /* (U2) MCU_OSPI0_DQS */
+                       AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* (U4) MCU_OSPI0_D0 */
+                       AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* (U5) MCU_OSPI0_D1 */
+                       AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* (T2) MCU_OSPI0_D2 */
+                       AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* (T3) MCU_OSPI0_D3 */
+                       AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* (T4) MCU_OSPI0_D4 */
+                       AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* (T5) MCU_OSPI0_D5 */
+                       AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* (R2) MCU_OSPI0_D6 */
+                       AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* (R3) MCU_OSPI0_D7 */
+                       AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
+               >;
+       };
 };
 
 &sdhci0 {
 &usb0_phy {
        status = "disabled";
 };
+
+&ospi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+       flash@0{
+               compatible = "jedec,spi-nor";
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <8>;
+               spi-max-frequency = <40000000>;
+               cdns,tshsl-ns = <60>;
+               cdns,tsd2d-ns = <60>;
+               cdns,tchsh-ns = <60>;
+               cdns,tslch-ns = <60>;
+               cdns,read-delay = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+       };
+};
index 5d5689d2849600857a968f032a5fe04d7e7e8f87..257b56a1b0323f4ef1b28188e916634b4cb56f82 100644 (file)
                        AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
                >;
        };
+
+       mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
+               pinctrl-single,pins = <
+                       AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
+                       AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)   /* (U2) MCU_OSPI0_DQS */
+                       AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* (U4) MCU_OSPI0_D0 */
+                       AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* (U5) MCU_OSPI0_D1 */
+                       AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* (T2) MCU_OSPI0_D2 */
+                       AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* (T3) MCU_OSPI0_D3 */
+                       AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* (T4) MCU_OSPI0_D4 */
+                       AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* (T5) MCU_OSPI0_D5 */
+                       AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* (R2) MCU_OSPI0_D6 */
+                       AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* (R3) MCU_OSPI0_D7 */
+                       AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
+               >;
+       };
 };
 
 &main_pmx0 {
                u-boot,dm-spl;
        };
 };
+
+&ospi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+       reg = <0x0 0x47040000 0x0 0x100>,
+             <0x0 0x50000000 0x0 0x8000000>;
+
+       flash@0{
+               compatible = "jedec,spi-nor";
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <8>;
+               spi-max-frequency = <40000000>;
+               cdns,tshsl-ns = <60>;
+               cdns,tsd2d-ns = <60>;
+               cdns,tchsh-ns = <60>;
+               cdns,tslch-ns = <60>;
+               cdns,read-delay = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+       };
+};