-======================================================================
-Changes since U-Boot 1.1.4:
-======================================================================
+commit 78d620ebb5871d252270dedfad60c6568993b780
+Author: Wolfgang Denk <wd@atlas.denx.de>
+Date: Thu Nov 23 22:58:58 2006 +0100
-* Prevent USB commands from working when USB is stopped.
+ Updates for TQM5200 modules:
+ - fix off-by-one error in board/tqm5200/cam5200_flash.c error message
+ - simplify "udate" definitions
-* Add rudimentary handling of alternate settings of USB interfaces.
- This is in order to fix issues with some USB sticks timing out
- during initialization. Some code readability improvements.
+commit 2053283304eeddf250d109e6791eb6fa4cad14f7
+Author: Stefan Roese <sr@denx.de>
+Date: Wed Nov 22 13:20:50 2006 +0100
-* PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
- AMCC suggested to set the PMU bit to 0 for best performace on
- the PPC440 DDR controller.
- Please see doc/README.440-DDR-performance for details.
- Patch by Stefan Roese, 28 Jul 2006
+ [PATCH] PPC4xx start.S: Fix for processor errata
-* AMCC bamboo (440EP) U-Boot image reduced to 384kbyte
- Please see doc/README.bamboo for details.
- Patch by Stefan Roese, 27 Jul 2006
+ Fixed cpu/ppc4xx/start.S for 440EPx Errata: further corrects PPC440EPx
+ errata 1.12: 440_33 by moving patch up in code.
-* Fix CONFIG_CMDLINE_EDITING implementation
- Patch by Stefan Roese, 27 Jul 2006
+ Signed-off-by: Jeff Mann <mannj@embeddedplanet.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
-* Fix preboot message on TQM5200 after switching to hush parser.
+commit 4ef6251403f637841000e0fef9e832aa01339822
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Nov 20 20:39:52 2006 +0100
-* MCC200: set default configuration to low_boot DDR,
- and support for configurable options high_boot and/or SDRAM.
+ [PATCH] Update AMCC Sequoia config file to support 64MByte NOR FLASH
-* Add support for 256 MB SDRAM on CPU87
- Patch by Josef Wagner, 25 Nov 2005
+ Signed-off-by: Stefan Roese <sr@denx.de>
-* Add configuration for cam5200 board (based on TQM5200S).
+commit e4bbd8da164b976d38616bd9c69c5e86e193cdf0
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Mon Nov 20 10:28:30 2006 +0100
-* More code cleanup
+ Update CHANGELOG
-* Disabled kvme080 board in MAKEALL because of build problems.
+commit 260421a21e934a68d31fb6125b0fbd2631a8ca20
+Author: Stefan Roese <sr@denx.de>
+Date: Mon Nov 13 13:55:24 2006 +0100
-* Code cleanup
+ [PATCH] CFI driver AMD Command Set Top boot geometry reversal, etc. [Updated]
+
+ * Adds support for AMD command set Top Boot flash geometry reversal
+ * Adds support for reading JEDEC Manufacturer ID and Device ID
+ * Adds support for displaying command set, manufacturer id and
+ device ids (flinfo)
+ * Makes flinfo output to be consistent when CFG_FLASH_EMPTY_INFO defined
+ * Removes outdated change history (refer to git log instead)
+
+ Signed-off-by: Tolunay Orkun <listmember@orkun.us>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b21b511d4c50408f4853f46f06b601272196223f
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Sun Nov 12 21:13:23 2006 +0100
+
+ Update CHANGELOG
+
+commit ce3f1a40c507afbab06c5eb58ccdc6713eda3245
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Sat Nov 11 22:48:22 2006 +0100
+
+ Disable the watchdog in the default config for the V38B board.
+
+commit 44a47e6db2694841211f1c8fdbafd36992e9cd1a
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Sat Nov 11 22:43:00 2006 +0100
-* Update NetStar board
- Patch by Ladislav Michl, 03 Nov 2005
-
-* Make code better readable.
- Patch by Ladislav Michl, 14 Sep 2005
-
-* Enable initrd ATAG for xm250 board.
- Patch by Josef Wagner, 05 Sep 2005
-
-* Add readline cmdline-editing extension
- Patch by JinHua Luo, 01 Sep 2005
-
-* Add support for friendly-arm SBC-2410X board
- Patch by JinHua Luo, 01 Sep 2005
-
-* Fix multi-part image support on i386 platform.
- Patch by David Updegraff, 19 Aug 2005
-
-* Add support for KVME080 board
- Patch by Sangmoon Kim, 18 Aug 2005
-
-* Fix MIPS LE build problem
- Patch by Matej Kupljen, 10 Aug 2005
-
-* Check argument count in "mii" command.
- Problem pointed out by Andrew Dyer, 13 Jun 2005
-
-* Cleanup TQM5200 board configurations:
- - make highboot configurations use environment at high end, too,
- to avoid flash fragmentation
- - always use redundand environment
- - don't enable video code for modules without graphics controller
- - provide useful (though different) mtdparts settings
- - get rid of CONFIG_CS_AUTOCONF which was always set anyway
-
-* Extend mkconfig tool to print more useful target name
-
-* Add support for high-boot on TQM5200 and TQM5200S boards.
- Hint: the CPLD on the TQM5200 must be programmed with a software
- version supporting the high boot option! The new TQM5200S is
- already supporting this option. On the TQM5200 this option will be
- supported in configurations with MPC5200 rev B processors.
- To actually "high boot", set jumper X30 on the STK52xx.
- Patch by Martin Krause, 12 Jul 2006
+ Change the GPIO pin multiplexing configuration for V38B. The USB GPIO pin
+ group is enabled for USB earlier (in cpu_init_f() instead of
+ usb_lowlevel_init()).
-* Add support for new TQM5200 revisions
- - Support for TQM5200S (short version without graphic controller)
- - Support for modules with 'N' type S29GL128N Spansion flashes
- (requires changes to flash layout)
- - Support for MPC5200B cpu (mostly support for second SDRAM bank)
- Patch by Martin Krause, 07 Jul 2006
+commit 91650b3e4de688038d4f71279c44858e3e2c6870
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Mon Nov 6 17:06:36 2006 +0100
-* Fix support for PS/2 keyboard on TQM85xx boards
- The PS/2 keyobard driver for the TQM85xx modules only supports the
- internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't
- include a DUART, the TQM8560 modules can't be used with the PS/2
- keyboard controller on the STK85xx board.
- The PS/2 keyboard driver should work with the modules TQM8540,
- TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet.
- Make sure the PS/2 controller on the STK85xx is programmed. Jumper
- settings: X66 1-2, 9-10; X61 2-3
- Patch by Martin Krause, 21 Jun 2006
+ Sequential accesses to non-existent memory must be synchronized,
+ at least on G2 cores.
-* Adjust RTC century handling on STK52xx board to match Linux driver.
- Patch by Martin Krause, 12 Jun 2006
+ This fixes get_ram_size() problems on MPC5200 Rev. B boards.
-* Adjust filenames for USB update images on TRAB board.
- During an automatic update via USB stick, U-Boot searches for
- images with the name "firmware.img" and "kernel.img". This names
- are now changed to "firmw_01.img" and "kernl_01.img". This is done,
- to prevent updates of new boards (with the new macronics "c" step
- flashes) with old, incompatible firmware or kernel versions.
- Patch by Martin Krause, 21 Jun 2006
+commit c59200443072353044aa4bf737a5a60f9a9af231
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Thu Nov 2 15:15:01 2006 +0100
-* Bugfix in VFD routine on TRAB board.
- Make sure upper lext pixel can be set to blue, too
- (so far only red was possible).
- Patch by Martin Krause, 15 Feb 2006
+ Release U-Boot 1.1.6
-* Enable buffered flash writes for TB5200 board.
+commit 25721b5cec2be4bce79cfade17ec8f6aa1e67526
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Wed Nov 1 02:04:38 2006 +0100
-* Fix some bugs in TRAB board flash driver.
- - increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds
- - use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT
- - remove "Unlock Bypass" mode, because macronix flashes do not support
- this mode officially
- - fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified
- for Intel compatible flashes, not for AMD compatible.
- Patch by Martin Krause, 15 Feb 2006
+ Finish up support for MarelV38B board
+ - add watchdog support
+ - enable GPIO_WKUP_7 pin for input
+ - code cleanup
-* Add additional error messages to flash driver on TRAB board
- (for erase errors and timeout errors)
- Patch by Martin Krause, 14 Feb 2006
+commit ffa150bc90c943ca265170bd1be3f293674dd5c7
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Wed Nov 1 01:45:46 2006 +0100
-* Add support for TB5200 board
- The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
- integrated in a little aluminium case.
- Patch by Martin Krause, 8 Jun 2006
+ - Fix issues related to the use of ELDK 4 when compiling for MarelV38B:
+ * remove warnings when compiling ethaddr.c
+ * adjust linker script (fixes a crash resulting from incorrect
+ definition of __u_boot_cmd_start)
+ - Some MarelV38B code cleanup.
-* Enable buffered flash writes for TQM5200 board.
+commit dae80f3caf9754a6dd3ddf3cf903d0c46cbd4385
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Wed Nov 1 01:38:16 2006 +0100
-* Fix problems with SanDisk Corporation Cruzer Micro USB memory stick.
+ - Add MPC5XXX register definition MPC5XXX_WU_GPIO_DATA_I and change the
+ MPC5XXX_WU_GPIO_DATA macro to MPC5XXX_WU_GPIO_DATA_O (per MPC5200 User's
+ Manual). Replace the uses of MPC5XXX_WU_GPIO_DATA with
+ MPC5XXX_WU_GPIO_DATA_O for affected boards.
-* Add support for TQM885D board.
- Patch by Martin Krause, 20 Mar 2006
+ - Add defintions for some MPC5XXX GPIO pins.
-* Fix FEC initialisation: All MII configuration is done via FEC1
- registers, but MII_SPEED was configured according to FEC used. So
- if only FEC2 was used, this caused the real MII_SPEED register in
- FEC1 to stay uninitalised, leqading to "mii_send STUCK!" messages.
- Fix: always configure MII_SPEED on FEC1 only.
- Patch by Markus Klotzbuecher, 12 Jul 2006
+commit 82d9c9ec29a1bec1b03ba616425ebaed231072c8
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Wed Nov 1 01:34:29 2006 +0100
-* Add support for SPC1920 board.
- Patch by Markus Klotzbuecher, 12 Jul 2006
+ Changed MarelV38B board make target to lowercase. Config file cleanup.
-* MCC200 board: support console on any one of the Quad UART ports.
+commit 1954be6e9c9421b45d0a9d05b10356acc7563150
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Sun Oct 29 01:03:51 2006 +0200
-* Fix error in flash protection calculation on MCC200 board.
+ Automatically adjust ARFLAGS so "make -s" is really silent.
-* Major PCMCIA Cleanup to make code better readable and maintainable.
- Notes:
- - Board-dependend code for RPXLITE and RPXCLASSIC-based boards
- placed to the drivers/rpx_pmcia.c file to avoid duplication.
- Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c).
- - drivers/i82365.c has been split into two parts located at
- board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are
- the only boards using CONFIG_82365).
- - Changes were tested for clean build and *very* *few* boards.
+commit fae684e89844856383bdf101440889557df3e6b1
+Author: Stefan Roese <sr@denx.de>
+Date: Sat Oct 28 16:45:00 2006 +0200
-* Fix timer problems on AMCC yucca board.
- Set Timer Clock Select to use CPU clock as a timer input source.
+ [PATCH] omap925.c: Remove unused functions
-* Bring yucca config more in line with other AMCC boards.
+ Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+ Signed-off-by: Stefan Roese <sr@denx.de>
-* Add AMCC bamboo board to MAKEALL build script.
+commit 1265581502ab8ea8c08e8edbe9bf64fbd62fd776
+Author: Stefan Roese <sr@denx.de>
+Date: Sat Oct 28 17:12:58 2006 +0200
-* Fix AMCC bamboo eval board compilation errors.
+ [PATCH] Add some missing machtypes for netstar & voiceblue boards
-* Add system memory to the PCI region list for AMCC PPC44x CPUs.
- Enabled it for Yucca board.
+ Use MACH_TYPE_NETSTAR and MACH_TYPE_VOICEBLUE defines instead of
+ numbers in code.
-* Cleanup config file and bootup output for Yucca board.
+ Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+ Signed-off-by: Stefan Roese <sr@denx.de>
-* Fix CONFIG_440_GX define usage.
+commit 856f054410cef52d868feb330168b2a4c4091328
+Author: Stefan Roese <sr@denx.de>
+Date: Sat Oct 28 15:55:52 2006 +0200
-* Remove autogenerated bmp_logo.h file.
+ [PATCH] NAND: Partition name support added to NAND subsystem
-* Add support for AMCC 440SPe CPU based eval board (Yucca).
+ chpart, nboot and NAND subsystem related commands now accept also partition
+ name to specify offset.
-* Call serial_initialize() before first debug() is used.
+ Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+commit 07a69a18c2ecfda904231fdf23e2523ea7792eb6
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Sat Oct 28 02:29:44 2006 +0200
+
+ Update CHANGELOG.
+
+commit 2751a95abd1b96911081c357e96a12fa97b40dee
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Sat Oct 28 02:29:14 2006 +0200
+
+ Enable commandline editing and hush shell on all TQM boards.
+
+<<<<<<< master
* Code cleanup
* Various USB related patches
Patch by Bryan O'Donoghue <bodonoghue@codehermit.ie>, 29 May 2006
* Cleanup trab board for GCC-4.x
+=======
+commit 8078f1a5f63a739b8533478f6c2b62fb1e2f79d7
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Sat Oct 28 02:28:02 2006 +0200
+>>>>>>> trunk
-* VoiceBlue update: use new MTD flash partitioning methods, use more
- reasonable TEXT_BASE, update default environment and enable keyed
- autoboot.
- Patch by Ladislav Michl, 16. Aug 2005
-
-* Add forgotten changes for the PLEB 2 Board.
- Patch by David Snowdon, 13. Aug 2005
-
-* Add support for wrPPMC7xx/74xx boards
- Patch by Richard Danter, 12 Aug 2005
-
-* Add support for gth2 board
- Patch by Thomas Lange, Aug 11 2005
-
-* Add support for CONFIG_SERIAL_MULTI on MPC5xxx
- Patch by Martin Krause, 8 Jun 2006
-
- This patch supports two serial consoles on boards with
- a MPC5xxx CPU. The console can be switched at runtime
- by setting stdin, stdout and stderr to the desired serial
- interface (serial0 or serial1). The PSCs to be used as
- console port are definded by CONFIG_PSC_CONSOLE
- and CONFIG_PSC_CONSOLE2.
- See README.serial_multi for details.
-
-* Bugfix in I2C initialisation on S3C2400.
- If the bus is blocked because of a previously interrupted
- transfer, up to eleven clocks are generated on the I2CSCL
- line to complete the transfer and to free the bus.
- With this fix pin I2CSCL (PG6) is really configured as GPIO
- so the clock pulses are really generated.
- Patch by Martin Krause, 04 Apr 2006
-
-* Fix DDR6 errata on TQM834x boards
- Patch by Thomas Waehner, 07 Mar 2006
-
-* Remove obsolete flash driver board/tqm5200/flash.c
- Patch by Martin Krause, 11 Jan 2006
-
-* Update configuration for CMC-PU2 board
- Patch by Martin Krause, 17 Nov 2005
-
-* Add support for PS/2 keyboard on TQM85xx board
- Patch by Martin Krause, 07 Nov 2005
-
- Tested on a STK85XX baseboard. Make sure the PS/2 controller
- has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
-
-* Fix TRAB channel switching delay for trab_fkt.bin standalone applikation
- In tsc2000_read_channel() the delay after setting the multiplexer
- to a temperature channel is increased from 1,5 ms to 10 ms. This
- is to allow the multiplexer inputs to stabilize after huge steps
- of the input signal level.
- Patch by Martin Krause, 08 Nov 2005
-
-* Adjust TQM5200 make targets
- Make the automatic CS configuration the default.
- The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB
- and CONFIG_TQM5200_AC are removed.
- "TQM5200_config" is now the default for STK52XX.200 base boards.
- On a STK52XX.100 base board "TQM5200_STK100_config" must be used.
- Patch by Martin Krause, 07 Nov 2005
-
-* Fix setting of environment variable "ver" on trab board
- The environment variable "ver" is now set before
- do_auto_update() is called, so that "ver" can be used
- in USB update scripts.
- Patch by Martin Krause, 27 Oct 2005
-
-* Fix wrong usage of udelay() in led_blink() on trab board
- Patch by Martin Krause, 27 Oct 2005
-
-* Fix udelay bug in vfd.c for trab board
- Patch by Martin Krause, 27 Oct 2005
-
-* Disable JFFS2 support for trab board
- Patch by Martin Krause, 27 Oct 2005
-
-* Change mtdparts definition on trab board to match current flash map
- Patch by Martin Krause, 27 Oct 2005
-
-* Fix memory init problems on MCC200 board
-
-* Fix IxEthDB.h to compile again
- Patch by Stefan Roese, 14 Jun 2006
-
-* Minor cleanup for PCS440EP board
- Patch by Stefan Roese, 13 Jun 2006
-
-* Add MCF5282 support (without preloader)
- relocate ichache_State to ram
- u-boot can run from internal flash
- Add EB+MCF-EV123 board support.
- Add m68k Boards to MAKEALL
- Patch from Jens Scharsig, 08 Aug 2005
-
-* Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards
- Patch by Scott McNutt, 08 Jun 2006
-
-* Nios II - Add EPCS Controller bootrom work-around
- -When booting from an epcs controller, the epcs bootrom may leave the
- slave select in an asserted state causing soft reset hang. This
- patch ensures slave select is negated at reset.
- Patch by Scott McNutt, 08 Jun 2006
-
-* Update PK1C20 board
- -Update base addresses for standard configuration
- -Eliminate use of CACHE_BYPASS in board code
- Patch by Scott McNutt, 08 Jun 2006
-
-* Nios II - Fix I/O Macros and mini-app stubs
- -Fix asm/io.h macros
- -Eliminate use of CACHE_BYPASS in cpu code
- -Eliminate assembler warnings
- -Fix mini-app stubs and force no small data
- Patch by Scott McNutt, 08 Jun 2006
-
-* Fix U-Boot environment sector protection on MCC200 board
-
-* Minor cleanup for PCS440EP board
-
-* Update PCS440EP port to fit into one flash device (incl. environment)
- Patch by Stefan Roese, 06 Jun 2006
-
-* Add support for PCS440EP board
- Patch by Stefan Roese, 02 Jun 2006
-
-* Fix examples/Makefile; some build targets were lost
-
-* Fix watchdog handling in CFI flash driver
- Just use udelay() when waiting for status changes which will
- implicitely trigger the watchdog.
-
-* Fix PCI to memory window size problems on PM82x boards
- We use the "automatic" mode that was used for the MPC8266ADS and
- MPC8272 boards. Eventually this should be used on all boards?]
- Patch by Wolfgang Grandegger, 17 Jan 2006
-
-* Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone
- Patch by Stefan Roese, 29 May 2006
-
-* Update Intel IXP4xx support
- - Add IXP4xx NPE ethernet MAC support
- - Add support for Intel IXDPG425 board
- - Add support for Prodrive PDNB3 board
- - Add IRQ support
- Patch by Stefan Roese, 23 May 2006
-
-* Fix problem in PVR detection for 440GR
- Patch by Stefan Roese, 18 May 2006
-
-* Fix gcc 3.4.x AFLAGS setting for m68k platform.
-
-* Enable autoboot for M5271EVB board.
-
-* Changed default ramdisk addr in yosemite/yellowstone ports
- Patch by Stefan Roese, 15 May 2006
-
-* Fix PCMCIA support on virtlab2
-
-* Add support for VirtLab2 board
- (needed because of differences in the PCMCIA hardware).
-
-* Minor cleanup.
-
-* Update yosemite configuration to enable flash write buffer support
- Patch by Stefan Roese, 10 May 2006
-
-* Fix compile warnings in common/xyzModem.c
- Patch by Stefan Roese, 10 May 2006
-
-* Add support for AMCC 440EP Rev C and 440GR Rev B
- Patch by John Otken, 08 May 2006
-
-* OMAP 5912/OSK: update EMIFS CS1 timings:
- Problems have been seen in the linux kernel's smc91x network driver
- due to improper bus timings. The latest 2.6 OMAP kernels currently
- have a workaround, but this fix belongs in u-boot.
- Patch by Kevin Hilman, 13 Oct 2005
-
-* Fix REG_MPU_LOAD_TIMER definition in multiple OMAP ports
- Patch by Hiroki Kaminaga, 11 Mar 2006
-
-* Update omap5912osk board support
- - Fix OMAP support that omap5912osk compiles in current source tree
- - Update with code from "http://omap.spectrumdigital.com/osk5912"
- to fix problems with DDR initialization
- - Fix timer setup
- - Use CFI flash driver and support complete 32MB of onboard flash
- - Add "print_cpuinfo()" and "checkboard()" functions to display
- CPU (with frequency) and Board infos
- Patch by Stefan Roese, 10 May 2006
-
-* Fix watchdog issues for ColdFire boards.
-
-* Add M5271EVB board support.
-
-* Make R5200 specific low level initialization board conditional.
-
-* Update CPU target identification strings for ColdFire family.
-
-* Update register definitions for MCF5271.
-
-* Fix serial console support for MCF5271.
-
-* Fixes for gcc 3.4 based m68k toolchain,
- based on patch by Jate Sujjavanich.
-
-* Fix lowboot support on MCC200 board
-
-* Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port:
- - Removed MPC8349ADS port
- - Added PCI support to MPC8349ADS
- - reworked memory map to allow mapping of all regions with BATs
- Patch by Kumar Gala, 20 Apr 2006
-
-* Coding Style cleanup
-
-* Write RTC seconds first to maintain settings integrity per
- Maxim/Dallas DS1306 data sheet.
- Patch by Alan J. Luse, 02 May 2006
-
-* Scheduled for removal: strnicmp() which is unused
-
-* Update for Intel Monahans boards:
- - support for magic key detection and handling on delta board
- - NAND support for zylonite board + some minor cleanup
-
-* Declare load_serial_ymodem() when using CFG_CMD_LOADB.
- Patch by Jon Loeliger, 01 May 2006
-
-* Fixed handling of bad checksums with "mkimage -l"
-
-* Added support for BC3450 board
- Patch by Stefan Strobl, 21 Oct 2005
-
-* Update for NC650 board:
- - Support rev1 and rev2 hardware
- - adapt to new NAND layer
- - add CP850 configuration based on NC650
-
-* MPC5200: enable snooping of DMA transactions on XLB even if no PCI
- is configured; othrwise DMA accesses aren't cache coherent which
- causes for example USB to fail.
-
-* Some code cleanup
-
-* Fix dbau1x00 boards broken by dbau1550 patch
- PLL:s were not set for boards other than 1550.
- Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
- Default boot is now bootp for cards other than 1550.
- Patch by Thomas Lange, 10 Aug 2005
-
-* Fixes common/cmd_flash.c:
- - fix some compiler/parser error, if using m68k tool chain
- - optical fix for protect on/off all messages, if using more
- then one bank
- Patch by Jens Scharsig, 28 Jul 2005
-
-* Fix Quad UART mapping on MCC200 board due to new HW revision
-
-* Fix JFFS2 support for legacy NAND driver.
-
-* Remove dependencies between DoC code and old legacy NAND driver.
-
-* Fix PM828_PCI target, for which PCI was *not* configured in.
-
-* Fix Lite5200B support: initialize SDelay register
- See Freescale's AN3221 "MPC5200B SDRAM Initialization and
- Configuration", 3.3.1 SDelay--MBAR + 0x0190
-
-* Changes/fixes for drivers/cfi_flash.c:
-
- - Add Intel legacy lock/unlock support to common CFI driver
-
- On some Intel flash's (e.g. Intel J3) legacy unlocking is
- supported, meaning that unlocking of one sector will unlock
- all sectors of this bank. Using this feature, unlocking
- of all sectors upon startup (via env var "unlock=yes") will
- get much faster.
-
- - Fixed problem with multiple reads of envronment variable
- "unlock" as pointed out by Reinhard Arlt & Anders Larsen.
-
- - Removed unwanted linefeeds from "protect" command when
- CFG_FLASH_PROTECTION is enabled.
-
- - Changed p3p400 board to use CFG_FLASH_PROTECTION
-
- Patch by Stefan Roese, 01 Apr 2006
-
-* Changes/fixes for drivers/cfi_flash.c:
- - Correctly handle the cases where CFG_HZ != 1000 (several
- XScale-based boards)
- - Fix the timeout calculation of buffered writes (off by a
- factor of 1000)
- Patch by Anders Larsen, 31 Mar 2006
-
-* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
-
- 405 SDRAM: - The SDRAM parameters can now be defined in the board
- config file and the 405 SDRAM controller values will
- be calculated upon bootup (see PPChameleonEVB).
- When those settings are not defined in the board
- config file, the register setup will be as it is now,
- so this implementation should not break any current
- design using this code.
-
- Thanks to Andrea Marson from DAVE for this patch.
-
- 440 DDR: - Added function sdram_tr1_set to auto calculate the
- TR1 value for the DDR.
- - Added ECC support (see p3p440).
-
- Patch by Stefan Roese, 17 Mar 2006
-
-* Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S
- Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]
-
-* Add support for ymodem protocol download
- Patch by Stefano Babic, 29 Mar 2006
-
-* Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000
- Merge from Markus Klotzbücher's repo, 01 Apr 2006
-
-* GCC-4.x fixes: clean up global data pointer initialization for all
- boards
-
-* Update for Delta board:
- - redundant NAND environment
- - misc Monahans cleanups (remove dead code etc.)
- - DA9030 Initialization; some minimal changes to PXA I2C driver to
- make it work with the Monahans.
- - Make Monahans clock frequency configurable using
- CFG_MONAHANS_RUN_MODE_OSC_RATIO and
- CFG_MONAHANS_TURBO_RUN_MODE_RATIO.
- Merge from Markus Klotzbücher's repo, 25 Mar 2006
-
-* Enable Quad UART om MCC200 board.
-
-* Cleanup MCC200 board configuration; omit non-existent stuff.
-
-* Add support for MPC859/866 Rev. A.0
-
-* Add command for handling DDR ECC registers on MPC8349EE MDS board.
-
-* Fix DDR ECC bit definitions for MPC83xx.
-
-* Add initial support for MPC8349E MDS board.
-
-* Add support for ECC DDR initialization on MPC83xx.
-
-* Add DMA support for MPC83xx.
-
-* Add sync in do_reset() routine for MPC83xx after RPR register
- was written to. It is need on some targets when BAT translation
- is enabled.
-
-* Add bit definitions for MPC83xx DDR controller registers.
-
-* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.
-
-* Correct shift offsets in icache_status and dcache_status for MPC83xx.
-
-* Add support for DS1374 RTC chip.
-
-* Add support for Lite5200B board.
- Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006
-
-* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific
- timer and cpu_reset code from cpu/$(CPU) into the new
- cpu/$(CPU)/$(SOC) directories
- Patch by Andreas Engel, 13 Mar 2006
-
-* Change max size of uncompressed uImage's to 8MByte and add
- CFG_BOOTM_LEN to adjust this setting.
-
- As mentioned by Robin Getz on 2005-05-24 the size of uncompressed
- uImages was restricted to 4MBytes. This default size is now
- increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN
- in the board config file.
-
- Patch by Stefan Roese, 13 Mar 2006
-
-* Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c
- Patch by Stefan Roese, 13 Mar 2006
-
-* cpu/ppc4xx/start.S : exceptions are enabled after relocation
- Patch by Cedric Vincent, 06 Jul 2005
-
-* au1x00_eth.c: check malloc return value and abort if it failed
- Patch by Andrew Dyer, 26 Jul 2005
-
-* Change the sequence of events in soft_i2c.c:send_ack() to keep from
- incorrectly generating start/stop conditions on the bus.
- Patch by Andrew Dyer, 26 Jul 2005
-
-* Fix bug in [id]cache_status commands for MPC85xx processors;
- should look at LSB of L1CSRn registers to determine if L1 cache is
- enabled, not the MSB.
- Patch by Murray Jensen, 19 Jul 2005
-
-* Fix array overflow with fw_setenv on uninitialised environment
- Patch by Murray Jensen, 15 Jul 2005
-
-* Add support for EmbeddedPlanet EP88x boards
- Patch by Yuli Barcohen, 13 Jul 2005
-
-* Remove board specific configuration includes from the common xilinx
- ethernet and iic adapter code.
- Patch by Michael Libeskind, 12 Jul 2005
-
-* Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver
- Patch by Murray Jensen, 08 Jul 2005
-
-* Add (some) definitions for the MPC85xx local bus controller
- Patch by Murray Jensen, 08 Jul 2005
-
-* Add CPM2 I/O pin functions for MPC85xx processors
- Patch by Murray Jensen, 08 Jul 2005
-
-* Fix compile problem
-
-* Added PCI support for MPC8349ADS board
- Patch by Kumar Gala 11 Jan 2006
-
-* Enable address translation on MPC83xx
- Patch by Kumar Gala, 10 Feb 2006
-
-* Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx
- Patch by Kumar Gala, 25 Jan 2006
-
-* Fixed defines for MPC83xx SICRL register to match current specs
- Patch by Kumar Gala, 23 Jan 2006
-
-* Only disable the MPC83xx watchdog if its enabled out of reset.
- If its disabled out of reset SW can later enable it if so desired
- Patch by Kumar Gala, 11 Jan 2006
-
-* Allow config of GPIO direction & data registers at boot on 83xx
- Patch by Kumar Gala, 11 Jan 2006
-
-* Enable time handling on 83xx
- Patch by Kumar Gala, 11 Jan 2006
-
-* Make System IO Config Registers board configurable on MPC83xx
- Patch by Kumar Gala, 11 Jan 2006
-
-* Fixed PCI indirect config ops to handle multiple PCI controllers
- We need to adjust the bus number we are trying to access based
- on which PCI controller its on
- Patch by Kumar Gala, 12 Jan 2006
-
-* Report back PCI bus when doing table based device config
- Patch by Kumar Gala, 11 Jan 2006
-
-* Added support for PCI prefetchable region and BARs
- If a host controller sets up a region as prefetchable and
- a device's BAR denotes it as prefetchable, allocate the
- BAR into the prefetch region.
-
- If a BAR is prefetchable and no prefetchable region has
- been setup by the controller we fall back to allocating
- the BAR into the normally memory region.
- Patch by Kumar Gala, 11 Jan 2006
-
-* Add helper function for generic flat device tree fixups for mpc83xx
- Patch by Kumar Gala, 11 Jan 2006
-
-* Add support for passing initrd information via flat device tree
- Patch by Kumar Gala, 11 Jan 2006
-
-* Added OF_STDOUT_PATH and OF_SOC
-
- OF_STDOUT_PATH specifies the path to the device the kernel can use
- for console output
-
- OF_SOC specifies the proper name of the SOC node if one exists.
- Patch by Kumar Gala, 11 Jan 2006
-
-* Allow board code to fixup the flat device tree before booting a kernel
- Patch by Kumar Gala, 11 Jan 2006
-
-* Added CONFIG_ options for bd_t and env in flat dev tree
-
- CONFIG_OF_HAS_BD_T will put a copy of the bd_t
- into the resulting flat device tree.
-
- CONFIG_OF_HAS_UBOOT_ENV will copy the environment
- variables from u-boot into the flat device tree
-
- Patch by Kumar Gala, 11 Jan 2006
-
-* Add support for the DHCP vendor optional bootfile (#67).
- Ignores the vendor TFTP server name option (#66).
- Patch by Murray Jensen, 30 Jun 2005
-
-* Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode
- Patch by Andy Fleming, 14 Jun 2005
-
-* Fix bad register definitions for LTX971 PHY on MPC85xx boards.
- Patch by Gerhard Jaeger, 21 Jun 2005
-
-* Add netconsole and some more commands to RPXlite_DW board
- Patch by Sam Song, 19 Jun 2005
-
-* Fix bad declaration on pci_cfgfunc_nothing
- Patch by Sam Song, 19 Jun 2005
-
-* Adjust "echo" as a default command
- Patch by Sam Song, 19 Jun 2005
-
-* Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC
- Patch by KokHow Teh, 16 Jun 2005
-
-* Add crc of data to jffs2 (in jffs2_1pass_build_lists()).
- Patch by Rick Bronson, 15 Jun 2005
-
-* Coding Style cleanup
-
-* Avoid dereferencing NULL in find_cmd() if no valid commands were found
- Patch by Andrew Dyer, 13 Jun 2005
-
-* Add ADI Blackfin support
- - add support for Analog Devices Blackfin BF533 CPU
- - add support for the ADI BF533 Stamp uClinux board
- - add support for the ADI BF533 EZKit board
- Patches by Richard Klingler, 11 Jun 2005
-
-* Add loads of ntohl() in image header handling
- Patch by Steven Scholz, 10 Jun 2005
-
-* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment
- variable to set clock
- Patch by Yuli Barcohen, 05 Jun 2005
-
-* RPXlite configuration fixes
- - Use correct flash sector size
- - Use correct memory test end address
- - Add support for bzip2 compression
- - Various small fixes
- Patch by Yuli Barcohen, 05 Jun 2005
-
-* Memory configuration changes for ZPC.1900 board
- - Fix SDRAM timing on both local bus and 60x bus
- - Add support for second flash bank (SIMM)
- - Change boot flash base
- Patch by Yuli Barcohen, 05 Jun 2005
-
-* Add support for Adder boards with 16MB SDRAM;
- add support for second FEC on Adder87x board.
- Patch by Yuli Barcohen, 05 Jun 2005
-
-* Fix conditional for including ks8695eth driver
- Patch by Greg Ungerer, 04 Jun 2005
-
-* Fix Makefile: include config.mk only after CROSS_COMPILE is defined
- Patch by Friedrich Lobenstock, 02 Jun 2005
-
-* Fix comment in common/soft_i2c.c
- Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005
-
-* Cleanup compiler warnings.
- Patch by Greg Ungerer, 21 May 2005
-
-* Word alignment fixes for word aligned NS16550 UART
- Patch by Jean-Paul Saman, 01 Mar 2005
-
- Fixes bug with UART that only supports word aligned access: removed
- "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some
- (broken!) versions of GCC generate byte accesses when encountering
- the packed attribute regardless if the struct is already correctly
- aligned for a platform. Peripherals that can only handle word
- aligned access won't work properly when accessed with byte access.
- The struct NS16550 is already word aligned for REG_SIZE = 4, so
- there is no need to packed the struct in that case.
-
-* Fix behaviour if gatewayip is not set
- Patch by Robin Gilks, 23 Dec 2004
-
-* Fix cleanup for netstart board.
- Remove build results from repository
-
-* Some code cleanup for GCC 4.x
-
-* Fixes to support environment in NAND flash;
- enable NAND flash based environment for delta board.
-
-* Add support for Intel Monahans CPU on Zylonite and Delta boards
- (This is Work in Progress!)
-
-* Add support for TQM8260-AI boards.
-
-* Minor code cleanup
-
-* Merge the new NAND code (testing-NAND brach); see doc/README.nand
- Rewrite of NAND code based on what is in 2.6.12 Linux kernel
- Patch by Ladislav Michl, 29 Jun 2005
-
-* Add lowboot target to mcc200 board
- Patch by Stefan Roese, 4 Mar 2006
-
-* Fix problem with flash_get_size() from CFI driver update
- Patch by Stefan Roese, 1 Mar 2006
-
-* Make CFG_NO_FLASH work on ARM systems
- Patch by Markus Klotzbuecher, 27 Feb 2006
-
-* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock,
- use hush shell.
-
-* Convert mcc200 to use common CFI flash driver
- Patch by Stefan Roese, 28 Feb 2006
-
-* Add env-variable "unlock" to handle initial state of sectors
- (locked/unlocked).
-
- Only the U-Boot image and it's environment is protected,
- all other sectors are unprotected (unlocked) if flash
- hardware protection is used (CFG_FLASH_PROTECTION) and
- the environment variable "unlock" is set to "yes".
-
- Patch by Stefan Roese, 28 Feb 2006
-
-* Update drivers/cfi_flash.c:
- - find_sector() called in both versions of flash_write_cfiword()
- Patch by Peter Pearse, 27th Feb 2006
-
-* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode
- Patch by Jose Maria Lopez, 16 Jan 2006
-
-* Add support for AMD/Spansion Flashes in flash_write_cfibuffer
- Patch by Alex Bastos and Thomas Schaefer, 2005-08-29
-
-* Changes/fixes for drivers/cfi_flash.c:
- We *should* check if there are any error bits if the previous call
- returned ERR_OK (Otherwise we will have output an error message in
- flash_status_check() already.) The original code would only check for
- error bits if flash_status_check() returns ERR_TIMEOUT.
- Patch by Marcus Hall, 23 Aug 2005
-
-* Changes/fixes for drivers/cfi_flash.c:
- - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c
- - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c
- Patch by Sangmoon Kim, 19 Aug 2005
-
-* Fixes for drivers/cfi_flash.c:
- - Fix wrong timeout value usage in flash_status_check()
- - Round write_tout up when converting to msec in flash_get_size()
- - Remove clearing flash status at the end of flash_write_cfibuffer()
- which sets Intel 28F640J3 flash back to command mode on CSB472
- Patch by Tolunay Orkun, 02 July 2005
-
-* Add basic support for the SMMACO4 Board from PanDaCom.
- Patch by Heiko Schocher, 20 Feb 2006
-
-* Add GIT version information (commid ID) to untagged U-Boot versions
-
- As done in the linux kernel, the U-Boot version (U_BOOT_VERSION)
- of all unreleased (untagged) U-Boot images will be automatically
- extended upon compiletime with a part of the GIT commit ID and
- possibly with "dirty" if uncommited changes are detected.
-
- Here an example for the resulting version:
- "U-Boot 1.1.4-g3457ac18-dirty"
-
- The version is now maintained in the toplevel Makefile and the
- version headers are autogenerated.
-
- Patch by Stefan Roese, 9 Feb 2006
-
-* Update default environment for INKA4x00 board.
-
-* Convert CPCI750 to use common CFI flash driver
- Patch by Reinhard Arlt, 8 Feb 2006
-
-* Various changes to esd HH405 board specific files
- Patch by Matthias Fuchs, 07 Feb 2006
-
-* Cleanup U-Boot boot messages on ARM.
-
- To match the U-Boot user interface on ARM platforms to the U-Boot
- standard (as on PPC platforms), some messages with debug character
- are removed from the default U-Boot build.
- Enable DEBUG for lib_arm/board.c to enable debug messages.
- New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options.
- Patch by Stefan Roese, 24 Jan 2006
-
-* Fix various compiler warnings on ppc4xx builds (ELDK 4.0)
- Patch by Stefan Roese, 18 Jan 2006
-
-* Add VGA support (CT69000) to CPCI750 board.
- Insert missing __le32_to_cpu() for filesize in ext2fs_read_file().
- Patch by Reinhard Arlt, 30 Dec 2005
-
-* PMC405 and CPCI405: Moved configuration of pci resources
- into config file.
- PMC405 and CPCI2DP: Added firmware download and booting via pci.
- Patch by Matthias Fuchs, 20 Dec 2005
-
-* Add ColdFire targets to MAKEALL script
- Patch by Zachary Landau, 26 Jan 2006
-
-* Add support for r5200 board
- Patch by Zachary Landau, 26 Jan 2006
-
-* Add support for Freescale M5271 processor
- Patch by Zachary Landau, 26 Jan 2006
-
-* Fix 28F256J3A support on PM520 board
- (without bank-switching only 32 MB can be accessed)
-
-* Fix mkimage bug with multifile images created on 64 bit systems.
-
-* Add support for 28F256J3A flash (=> 64 MB) on PM520 board
-
-* Fix compiler problem with at91rm9200dk board.
- Patch by Eugen Bigz, 19 Dec 2005
-
-======================================================================
-Changes for U-Boot 1.1.4:
-======================================================================
-
-* Changes to Yellowstone & Yosemite 440EP/GR eval boards:
- - Changed GPIO setup to enable another address line in order to
- address 64M of FLASH.
- - Added function sdram_tr1_set to auto calculate the tr1 value for
- the DDR.
- Patch by Steven Blakeslee, 12 Dec 2005
-
-* MPC5200: Set PCI retry counter to 0 = infinite retry;
- The default of 255 is too short for slow devices.
- Patch by Martin Nykodym, 12 Dec 2005
-
-* Change port configuration for O2DNT (CODEC1 on PSC1).
-
-* Fix register for PCI async mode on PPC440EP
- Patch by Youngchul Bang, 08 Dec 2005
-
-* Fix U-Boot linking problems (add .eh_frame segment to linker script)
- This segment may be required by some libgcc.a functions
- (like _udivdi3).
-
-* Fix DPRAM offset/size for MPC8541/8555.
- Simplify TQM85xx Makefile handling.
-
-* Fix data overflow (typo?) in rtc/ds1302.c
-
-* Fix U-Boot compilation for MIPS boards using ELDK 4.0
-
-* Add support for TQM8541/8555 boards, TQM85xx support reworked:
- - Support for TQM8541/8555 boards added.
- - Complete rework of TQM8540/8560 support.
- - Common TQM85xx code now supports all current TQM85xx platforms
- (TQM8540/8541/8555/8560).
- - DDR SDRAM size detection added.
- - CAS latency default values can be overwritten by setting "serial#"
- to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used.
- If problems are detected with this non default CAS latency,
- the default values will be used instead.
- - Flash size detection added.
- - Moved FCC ethernet driver initialization behind TSEC driver init
- -> TSEC is first device.
- Patch by Stefan Roese, 30 Nov 2005
-
-* Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board.
- Patch by John Otken, 23 Nov 2005
-
-* Changed PPC44x startup message (cpu info, speed...) to common style:
- On PPC44x platforms, the startup message generated in "cpu.c" only
- comprised the ppc type and revision but not additional information
- like speed etc. Those speed infos where printed in the board specific
- code. This new implementation now prints all CPU infos in the common
- cpu specific code. No board specific code is needed anymore and
- therefore removed from all current 44x implementations.
- Patch by Stefan Roese, 27 Nov 2005
-
-* Adjust TQM834x PHY addresses for latest hardware revision.
-
-* Increase malloc arena on TQM5200 board to 256 kB.
- With 64 kb uniform flash sector size the old value of 128 kB was
- too small.
-
-* Fix miiphy global data initialization (problem on 4xx boards when
- no ethaddr is assigned). Initialization moved from
- miiphy_register() to eth_initialize().
-
- Based on initial patch for 4xx platform by Matthias Fuchs.
-
-* Remove unnnecessary #include <linux/types.h> from include/asm-*/u-boot.h
-
-* Allow use of include/image.h and include/asm-*/u-boot.h in proprietary code.
- The COPYING file was extended to make clear that these files can be
- used in non-GPL code, too.
- Also, a corresponding note was placed in the headers of the affected files.
-
-* Add support for Prodrive P3P440 board:
- - Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c
- - CFG_FLASH_QUIET_TEST added to use the common CFI driver
- for bank autodetection
- Patch by Stefan Roese, 22 Nov 2005
-
-* Change all '$(...)' variable references into '${...}'
- which makes the environment compatible with the hush shell.
- WARNING: Support for the old '$(...)' syntax will be
- discontinued in a later version.
-
-* Minor changes to init flags in TQM834x PCI.
-
-* Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM)
- Patch by Stefan Roese, 15 Nov 2005
-
-* New PPC 405EP board added: CMS700
- Added CONFIG_NET_MULTI for VOM405 board.
- Added reset_phy() for VOM405 board.
- Patch by Matthias Fuchs, 09 Nov 2005
-
-* Updated PCI mapping for esd CPCI2DP board.
- Add support for error LED.
- Patch by Matthias Fuchs, 07 Nov 2005
-
-* Fix MPC85xx PCI support (pci_register_hose() before pci config access)
- Patch by Stefan Roese, 07 Nov 2005
-
-* Correct PPC Timebase register definitions (SPRN_TBRL...)
- Patch by Stefan Roese, 07 Nov 2005
-
-* Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size
- Patch by Stefan Roese, 05 Nov 2005
-
-* Additional fix for external IRQ config on Yellowstone & Yosemite
- Patch by Stefan Roese, 03 Nov 2005
-
-* Add support for Ocotea pass 3 with 440GX Rev. F
- Patch by Stefan Roese, 01 Nov 2005
-
-* Fix external IRQ configuration on Yellowstone & Yosemite
- Patch by Stefan Roese, 28 Oct 2005
-
-* Add support for multiple PHYs.
- Tested on the following boards:
- cmcpu2 (at91rm9200/ether.c)
- PPChameleon (ppc4xx/4xx_enet.c)
- yukon (mpc8220/fec.c)
- uc100 (mpc8xx/fec.c)
- tqm834x (mpc834x/tsec.c) with EEPRO100
- lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c)
- Main changes include:
- common/miiphyutil.c
- - miiphy_register routine was added to allow multiple PHYs to be registered
- - miiphy_read and miiphy_write are now defined in this file, and
- require additional argument (char *devname)
- - other miiphy_* routines also require additional device name argument
- ../lib_i386/board.c
- ../lib_ppc/board.c
- Calling reset_phy() was moved to be executed *after* eth_initialize().
- This is necessary as now some of the implementations of reset_phy()
- may need to use miiphy_reset() which is not allowed before eth_initialize()
- as eth_initialize registers all required miiphy_* routines.
- Tested on IP860 and PHY initializes properly after this change.
-
-* Correct includes for flat tree builder.
-
-* Fix conflicting types (flash_write()) in trab auto_update.c.
-
-* Add PCI support for the TQM834x board.
-
-* Add missing 4xx board to MAKEALL
- Patch by Stefan Roese, 20 Oct 2005
-
-* Fix conflicting types (flash_write()) in esd auto_update.c
- Patch by Stefan Roese, 20 Oct 2005
-
-* Fix problem with sleep in NetConsole (use get_timer())
- Patch by Stefan Roese, 20 Oct 2005
-
-* Add NetConsole Support for AMCC eval boards
- Patch by Stefan Roese, 20 Oct 2005
-
-* Fix NetConsole support on 4xx (only print eth link on 1st transfer)
- Patch by Stefan Roese, 18 Oct 2005
-
-* Add fat & ext2 support to AMCC 440EP boards Yosemite & Bamboo.
- Fix identation on ext2ls help entry.
- Patch by Stefan Roese, 14 Oct 2005
-
-* Add support for TQM834x boards.
- Cleanup.
-
-* Cleanup for GCC-4.x
-
-* Add documentation for Open Firmware Flat Tree and usage.
- Patch by Pantelis Antoniou, 13 Oct 2005
-
-* Add missing files for Pantelis Antoniou's patch
- Patch by Pantelis Antoniou, 04 Sep 2005
-
-* Fix problem in ppc4xx eth-driver without ethaddr (only without
- CONFIG_NET_MULTI set)
- Patch by Stefan Roese, 10 Oct 2005
-
-* Fix gzip bmp support (test if malloc fails, warning when truncated).
- Increase CFG_VIDEO_LOGO_MAX_SIZE on HH405 board.
- Patch by Stefan Roese, 07 Oct 2005
-
-* Add support for OF flat tree for the STXtc board.
- Patch by Pantelis Antoniou, 04 Sep 2005
-
-* Support passing of OF flat trees to the kernel.
- Patch by Pantelis Antoniou, 04 Sep 2005
-
-* Cleanup
-
-* Add support for NetSilicon NS7520 processor.
- Patch by Art Shipkowski, 12 May 2005
-
-* Add support for AP1000 board.
- Patch by James MacAulay, 07 Oct 2005
-
-* Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200
- Patch by Anders Larsen, 07 Oct 2005
-
- The Atmel errata #11 states that the transfer buffer descriptor
- table must be aligned on a 16-word boundary. As it turned out, this
- is insufficient - it seems the table must be aligned on a boundary
- at least as large as the table itself (in Linux this is not an
- issue - the table is aligned on a PAGE_SIZE (4096) boundary).
-
-* Fixed compilation for ARM when using a (standard) hard-FP toolchain
- Patch by Anders Larsen, 07 Oct 2005
-
-* Cleanup warnings for cpu/arm720t & cpu/arm1136 files.
- sed the linker scripts, rather than pre-process them.
- Patch by Peter Pearse, 07 Oct 2005
-
-* Update make target for ARM supported boards.
- Use lowlevel_init() instead of platformsetup() [rename].
- Patch by Peter Pearse, 06 Oct 2005
-
-* Fix booting from serial dataflash on AT91RM9200
- Patch by Peter Menzebach, 29 Aug 2005
-
-* Add JFFS2 support for TRAB board
- Patch by Martin Krause, 25 Aug 2005
-
-* Remove unnecessary dependency of netconsole on CONFIG_NET_MULTI
- Patch by Marcus Hall, 24 Aug 2005
-
-* Fix the machine-id of the Cogent csb637 board
- Patch by Anders Larsen, 05 Oct 2005
-
-* Complete support for the KwikByte KB920x boards
- Patch by Anders Larsen, 05 Oct 2005
-
-* Set the AT91RM9200 clock to asynchronous mode
- Patch by Anders Larsen, 03 May 2005
-
-* Set the AT91RM9200 clock to synchronous mode
- Patch by Anders Larsen, 29 Apr 2005
-
-* Add support for Cogent csb637
- Patch by Anders Larsen, 29 Apr 2005
-
-* Fix dm9161.c initialization
- Patch by Anders Larsen, 29 Apr 2005
-
-* Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005
- (8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5)
-
-* Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200
- Patch by Anders Larsen, 29 Apr 2005
-
-* Fix device partition intialization for SystemACE disks.
- Patch by Stephen Williams, 28 Apr 2005
-
-* Added support for KwikByte KB920x boards (based on AT91RM9200)
- Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005
-
-* Add support for S29GL064M-R3 flash chip on xsengine board
- Patch by Kurt Stremerch, 18 Apr 2005
-
-* E500 update: repoint IVPR to RAM when code is relocated
- Patch by Kylo Ginsberg, 13 Apr 2005
-
-* Fix loop end test in lib_generic/string.c:strswab()
- Patch by Andrew Dyer, October 10, 2005
- Signed-off-by: Andrew Dyer <amdyer@gmail.com>
-
-* Cleanup
-
-* Update ARM Integrator boards:
- Correct addessing errors in platform files.
- Split off common core module data from Integrator header files to
- include/armcoremodule.h.
- Patch by Peter Pearse, 04 Oct 2005
-
-* Make sure only supported compiler options are used
- Import "cc-option" shell function from kernel and
- use it to get the correct ARM GCC options for individual CPUs
- Patch by Peter Pearse, 30 Jun 2005
-
-* Fix 440GR to print correct cpu revision
- Patch by Stefan Roese, 04 Oct 2005
-
-* Change board message on AMCC Yosemite & Yellowstone to common style
- Patch by Stefan Roese, 03 Oct 2005
-
-* Fix compiler warning
-
-* Fix FEC PHY addresses for TQM85xx boards
-
-* Fix uninitialized variable problem in hush shell
- Patch by Lars Rostock, 26 Sep 2005
-
-* Undo change of f6e20fc6ca... to include/configs/trab.h
- (Must have been an accident?)
-
-* Add support for AT91RM9200 OHCI Controller.
- Patch by Eric Benard, 07 Apr 2005
-
-* Update ARM mach-types.h
- Patch by Eric Benard, 07 Apr 2005
-
-* Add support for MP2USB board.
- Patch by Eric Benard, 07 Apr 2005
-
-* Add board support for armadillo HT1070
- Patch by Rowel Atienza, 06 Apr 2005
-
-* Second Ethernet address enabled for MPC885ADS and MPC8272ADS.
- Patch by Vitaly Bordug, 30 Mar 2005
-
-* Add iopset command on mpc8xx
- Patch by Daniel Eisenhut, 25 Mar 2005
-
-* Add support for MII in eepro100 driver.
- Patch by Gleb Natapov, 21 Mar 2005
-
-* Fixes to the Lubbock (PXA 25x) support:
- - Resolve the FIXME with respect to saving the u-boot environment.
- - Make the default load address land in real memory.
- - Fix lan91c96 SMC_{in,out}{b,w,l}() macros
- Patch by David Brownell, 10 Mar 2005
-
-* Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board
- Patch by Marc Leeman, 04 Mar 2005
-
-* OMAP242x H4 board update
- - fix for ES2 differences.
- - switch to using the cfi_flash driver.
- - fix SRAM build address.
- - fix for GP device operation.
- - unlock SRAM for GP devices.
- - display more device information.
- - fix potential deadlock in omap24xx_i2c driver.
- - fix DLL load values to match dpllout*1 operation.
- - fix 2nd chip select init for combo DDR device.
- - add support for CFI Intel 28F256L18 on H4 board.
- Patch by Richard Woodruff, 03 Mar 2005
-
-* Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h
- Patch by Steven Scholz, 02 Mar 2005
-
-* Fix typo in eth.c
- Patch by Ara Avanesyan, 24 Feb 2005
-
-* Remove unneeded #include <malloc.h>
- Patch by Ladislav Michl, 22 Feb 2005
-
-* Add cramfs support for m68k
- Patch by Zachary Landau, 21 Feb 2005
-
-* Update ep8260: Fix flash timeouts; improve clock resolution for faster UARTs
- Patch by Jeff Angielski, 21 Feb 2005
-
-* Fix au1x00_serial baud rate calculation:
- remove hardcoded cpu clock divisor and use register instead;
- round up instead of truncate
- Patch by Andrew Dyer, 15 Feb 2005
-
-* Add Xilinx Spartan3 family FPGA support
- Patch by Kurt Stremerch, 14 Feb 2005
-
-* Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET
- Patch by Zachary Landau, 11 Feb 2005
-
-* Fix VOH405 Support
- Patch by Matthias Fuchs, 25 Sep 2005
-
-* Added support for PCI bridge on MPC8272ADS
- Patch by Vitaly Bordug, Feb 09 2005
-
-* Update multicore CM9XX support for Integrator AP to allow booting from flash
- Patch by Jean-Paul Saman, 8 Feb 2005
-
-* Fix strswab() to reliably find end of string
- Patch by Andrew Dyer, 08 Feb 2005
-
-* Fix typos in include/ppc440.h
- Patch by Andrew E Mileski, 04 Feb 2005
-
-* Add Vibren (was Accelent) PXA255 IDP Support
- Patch by Cliff Brake, 04 Feb 2005
-
-* Fix tools/bmp_logo.c using incorrect offset to pixel data
- Patch by Andrew Dyer, 31 Jan 2005
-
-* Add ARM946E cpu and core module targets; remap memory to 0x00000000
- Patch by Peter Pearse, 2 Feb 2005
-
-* Fix error handling in tools/env/fw_env.c
- Patch by Ara Avanesyan, 01 Feb 2005
-
-* Fix MGT5100 PSC baudrate calculation
- Patch by Sebastian Schau, 27 Jan 2005
-
-* OMAP242x fix for GP device booting
- - Add SRAM unlock for GP devices.
- - Change DDR DLL unlock value to allow DPLLout*1 operation.
- Patches by Richard Woodruff, 21 Jan 2005:
-
-* Add support for AMD's Pb1x00 eval board;
- add MII routines to the au1x00 ethernet driver;
- add USB ohci driver (work in progress)
- Patch by Thomas Sailer, 20 Jan 2005
-
-* Update omap5912osk board
- Use drivers/cfi_flash.c instead of private flash driver;
- Remove hardcoded personalized settings from omap5912osk.h;
- Fix spacing with (RO) marks in 'flinfo' output.
- Patch by Michael Bendzick, 14 Jan 2005
-
-* Fix warnings for PCI code on ixp
- Patch by Joe <lgxue@yahoo.com>, 13 Jan 2005
-
-* virtex2 fix for bogus download error messages
- The virtex2 FPGA download code watches for init going active during
- a download of config data as an error condition. init also goes
- active after a configuration is finished in concert with the done
- signal. So far, the code does not check for done active until all
- of the configuration data is sent. If configuration data has a few
- extra pad bytes at the end, this would cause an error message even
- though the download had suceeded.
- NOTE: virtex2 slave serial and spartan2 versions may still have the
- same problem.
- Patch by Andrew Dyer, 12 Jan 2005
-
-* Optimize flash_make_cmd in drivers/cfi_flash.c for little endian
- Fix "WARNING: flash_make_cmd: unsuppported LittleEndian mode"
- message when probing for nonexistent flash in little endian mode.
- As a side effect more efficient and smaller code is generated,
- which is always a Good Thing (TM).
- Patch by Ladislav Michl, 24 Sep 2005
-
-* Update for TFTP using a fixed UDP port
- Use the approved environment variable names. Added "tftpdstp" to
- allow ports other than 69 per Tolunay Orkun's recommendation.
- Patch by Jerry Van Baren, 12 Jan 2005
-
-* Allow to force TFTP to use a fixed UDP port
- (Add a configuration option CONFIG_TFTP_PORT and optional env
- variable tftpport)
- Patch by Jerry Van Baren, 10 Jan 2005
-
-* Fix ethernet timeouts on dbau1550 and other au1x00 systems
- Patch by Leif Lindholm, 29 Dec 2004
-
-* Cleanup: fix broken builds
-
-* Fix PHY address argument passing with mii info command
- Patch by Andrew Dyer, 28 Dec 2004
-
-* Cleanup (PPC4xx is AMCC now)
-
-* esd CPCI2DP board added
- Patch by Matthias Fuchs, 22 Sep 2005
-
-* esd PMC405 board updated
- Patch by Matthias Fuchs, 22 Sep 2005
-
-* Add SM501 support to HH405 board.
- Add support for gzip compressed bmp's (CONFIG_VIDEO_BMP_GZIP).
- Add support for eeprom write-enable (CFG_EEPROM_WREN).
- Patch by Stefan Roese, 22 Sep 2005
-
-* Fix autonegotiation in tsec ethernet driver
- Patch by Stefan Roese, 21 Sep 2005
-
-* Fix bug in auto_update (trab board)
- Patch by Martin Krause, 16 Sep 2005
-
-* Fix computation of framebuffer palette for 8bpp LCD bitmaps
- Patch by Francesco Mandracci, 16 Sep 2005
-
-* Update configuration for INKA4x0 board
-
-* Update configuration for PM854 board
- Based on patch by R. Loeffl, 20 Jul 2005
-
-* Add PCI support to TQM8540 and TQM8560 boards
- Patch by Stefan Roese, 15 Sep 2005
-
-* Update AMCC Yosemite to get a consistent setup for all AMCC eval
- boards (baudrate, environment...). Flash driver fixed.
- Patch by Stefan Roese, 15 Sep 2005
-
-* Fix problem in 440GP ethernet driver (ebony). Add support for 2nd
- ethernet port on ebony.
- Patch by Stefan Roese, 7 Sep 2005
-
-* Added support for mtddevnum and mtddevname variables (mtdparts command)
-
-* Change default console baud rate for stxxtc board
-
-* Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT).
- Patch by Stefan Roese, 31 Aug 2005
-
-* Fix default command set (don't include CFG_CMD_DISPLAY command)
- Patch by Pantelis Antoniou, 02 Sep 2005
-
-* Cleanup
-
-* Enable SM712 driver support for HMI1001 board.
-
-* Fix problems with ld version 2.16 (dot outside sections problem)
- Pointed out by Gerhard Jaeger, 31 Aug 2005;
- cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html
-
-* Prepare U-Boot for gcc-4.x: fix global data pointer initialization
-
-* Adjust CS3 timings on HMI1001 board for dot matrix display under Linux
-
-* Add keyboard and dot matrix display support for HMI1001 board.
-
-* Prepare U-Boot for gcc-4.x
-
-* Fixed Bamboo port to enable running without DDR-DIMM
- (Bamboo has also 64MB onboard DDR)
- Patch by Stefan Roese, 24 Aug 2005
-
-* Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
- now handling all 4xx cpu's
- Patch by Stefan Roese, 16 Aug 2005
-
-* Fix make dependencies for at91rm9200 and ks8695 cpus
- Patch by Steven Scholz, 23 Aug 2005
-
-* Add JFFS2 support for TQM5200 board
-
-* Add esd cpci5200 and pf5200 boards
- Patch by Reinhard Arlt, 22 Aug 2005
-
-* Fix sysclock for TQM8540 and TQM8560 boards
- Patch by Martin Krause, 25 Jul 2005
-
-* Initialize serial# and ethaddr from manufacturer data in EEPROM on CMC-PU2
- Patch by Martin Krause, 08 Jun 2005
-
-* Add new board specific commands for TQM5200/STK52XX
- - Sound commands (beep, wav, sound)
- - Test commands (led, can, backlight, rs232)
- Patch by Martin Krause, 02 May 2005
-
-* Change main clock on CMC-PU2 board from 207 MHz to 179 MHz
- because of a bug in the AT91RM9200 CPU PLL
- Patch by Martin Krause, 22 Apr 2005
-
-* Add automatic HW detection for another CMC_PU2 variant
- Patch by Martin Krause, 20 Apr 2005
-
-* Remove CONFIG_AT91RM9200DK in CMC-PU2 configuration
- Patch by Martin Krause, 19 Apr 2005
-
-* Fix initialization problem on TQM5200 without SM501
- Patch by Martin Krause, 08 Apr 2005
-
-* Add RTC support for STK52XX.200
- Patch by Martin Krause, 07 Apr 2005
-
-* Add support for IFM o2dnt board
-
-* Enable PCI on hmi1001 board
-
-* Fix return values of the jffs2 commands ls/fsload/fsinfo,
- so we can use them to, e.g., check the existence of a file with
- "if ls foo; then this; else that; fi" in the hush shell
- Patch by Andreas Engel, 16 August 2005
-
-* Coding style cleanup
-
-* Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board.
- Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005
-
-* Check return value of malloc in 440gx_enet.c
- Patch by Travis B. Sawyer, 18 Jul 2005
-
-* Add Sandburst Metrobox and Sandburst Karef board support packages.
- Second serial port on 440GX now defined as a system device.
- Add 'Short Etch' code for Cicada PHY within 440gx_enet.c
- Patch by Travis B. Sawyer, 12 Jul 2005
-
-======================================================================
-Changes for U-Boot 1.1.3:
-======================================================================
-
-* Minor code cleanup
-
-* Add forgotten new fils from latest VoiceBlue update
-
-* Make bootretry feature work with hush shell.
- Caveat: this currently *requires* CONFIG_RESET_TO_RETRY to be set, too.
- Patch by Andreas Engel, 19 Jul 2005
-
-* Update Hymod Board Database PHP code in "tools" directory
- Patch by Murray Jensen, 01 Jul 2005
-
-* Make "tr" command use POSIX compliant; export HOSTOS make variable
- Patch by Murray Jensen, 30 Jun 2005
-
-* Fix Murray Jensen's mail address.
- Patch by Murray Jensen, 30 Jun 2005
-
-* Preserve PHY_BMCR during a soft reset.
- Patch by Carl Riechers, 24 Jun 2005
-
-* VoiceBlue update: eeprom tool can also store firmware version now.
- eeprom.bin is runable by jumping at load address.
- Patch by Ladislav Michl, 23 May 2005
-
-* Move the AT91RM9200DK to the ARM Systems list.
- Patch by Anders Larsen, 26 Apr 2005
-
-* Eliminate calls of ARM libgcc.a helper functions _divsi3 and _modsi3
- Patch by Anders Larsen, 26 Apr 2005
-
-* measure_gclk() is needed when DEBUG is enabled
- Patch by Bryan O'Donoghue, 25 Apr 2005
-
-* Add UPD-Checksum code, fix problem in net.c (return instead of break)
- Patch by Reinhard Arlt, 12 Aug 2005
-
-* esd PCI405 board updated
- Patch by Matthias Fuchs, 28 Jul 2005
-
-* esd WUH405 and DU405 board updated
- Patch by Matthias Fuchs, 27 Jul 2005
-
-* Fix problem in cmd_nand.c (only when defined CFG_NAND_SKIP_BAD_DOT_I)
- Patch by Matthias Fuchs, 4 May 2005
-
-* Update AMCC Yosemite to get a consistent setup for all AMCC eval
- boards (baudrate, environment...). Flash driver fixed.
- Patch by Stefan Roese, 11 Aug 2005
-
-* Changed AMCC Bubinga (405EP) configuration to support 2nd eth port
- Patch by Stefan Roese, 11 Aug 2005
-
-* Add NAND FLASH support for AMCC Bamboo 440EP eval board
- Patch by Stefan Roese, 11 Aug 2005
-
-* Add configuration for IFM AEV FIFO board.
- Minor coding style cleanup.
-
-* Add configuration for IFM SPI eval board
-
-* Fix CompactFlash problem on HMI1001 board
-
-* Make new "mtdparts" code build with older compilers
- Patch by Andrea Scian, 09 Aug 2005
-
-* Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to
- CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design
- with the 405 defines and the linux kernel defines.
- Patch by Stefan Roese, 08 Aug 2005
-
-* Fix compiler warnings with older GCC versions
-
-* Add common (with Linux) MTD partition scheme and "mtdparts" command
-
- Old, obsolete and duplicated code was cleaned up and replace by the
- new partitioning method. There are two possible approaches now:
-
- The first one is to define a single, static partition:
-
- #undef CONFIG_JFFS2_CMDLINE
- #define CONFIG_JFFS2_DEV "nor0"
- #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */
- #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */
- #define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
- The second method uses the mtdparts command line option and dynamic
- partitioning:
-
- /* mtdparts command line support */
- #define CONFIG_JFFS2_CMDLINE
- #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2"
- #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
-
- Command line of course produces bigger images, and may be inappropriate
- for some targets, so by default it's off.
-
-* Fix build problems for PM856 Board
-
-* Fix sign extension bug in 'fpga loadb' command;
- make 'fpga loadb' always print the file header info
- Patch by Andrew Dyer, 11 Jan 2005
-
-* Fix errors that occur when accessing SystemACE CF
- Patch by Jeff Angielski, 09 Jan 2005
-
-* Document switching between U-Boot and PlanetCore on RPXlite
- by Sam Song, 24 Dec 2004
-
-* Fix PowerQUICC II mask detection.
- Patch by Eugene Surovegin, 20 Dec 2004
-
-* Add support for Altera NIOS DK1C20 board
- Patch by Shlomo Kut, 13 Dec 2004
-
-* Add support for ep8248 board
- Patch by Yuli Barcohen, 12 Dec 2004
-
- Minor code cleanup.
-
-* Fix baudrate setting for KGDB on MPC8260
- Patch by HoJin, 11 Dec 2004
-
-* Fix 'mii help' text formatting
- Patch by Cory Tusar, 10 Dec 2004
-
-* Fix return code of NFS command
- Patch by Hiroshi Ito, 11 Dec 2004
-
-* Fix typo
-
-* Fix compiler warnings in cpu/ppc4xx/usbdev.c
- Patch by Steven Blakeslee, 04 Aug 2005
-
-* Add support for AMCC Bamboo PPC440EP eval board
- Patch by Stefan Roese, 04 Aug 2005
-
-* Patch by Jon Loeliger
- Fix style issues primarily in 85xx and 83xx boards.
- - C++ comments
- - Trailing white space
- - Indentation not by TAB
- - Excessive amount of empty lines
- - Trailing empty lines
-
-* Patch by Ron Alder, 11 Jul 2005
- Add Xianghua Xiao and Lunsheng Wang's support for the
- GDA MPC8540 EVAL board.
-
-* Patch by Eran Liberty
- Add support for the Freescale MPC8349ADS board.
-
-* Patch by Jon Loeliger, 25 Jul 2005
- Move the TSEC driver out of cpu/mpc85xx as it will be shared
- by the upcoming mpc83xx family as well.
-
-* Patch by Jon Loeliger, 05 May 2005
- Implemented support for MPC8548CDS board.
- Added DDR II support based on SPD values for MPC85xx boards.
- This roll-up patch also includes bugfies for the previously
- published patches:
- DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
-
-* Patch by Jon Loeliger, 10 Feb 2005
- Add config option CONFIG_HAS_FEC calling out 8540 FEC features.
-
-* Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005
- For MPC85xxCDS:
- Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow
- for faster flash parts.
- Add documentation for BR/OR for FLASH.
-
-* Patch by Jon Loeliger 08 Feb 2005
- Determine L2 Cache size dynamically on 85XX boards.
-
-* Patch by Jon Loeliger, Kumar Gala 08 Feb 2005
- - Convert the CPM2 based functionality to use new CONFIG_CPM2
- option rather than a myriad of CONFIG_MPC8560-like variants.
- Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
- Eliminates the CONFIG_MPC8560 option entirely. Distributes the
- new CONFIG_CPM2 option to each 8260 board.
-
-* Add support for MicroSys PM856 board
- Patch by Josef Wagner, 03 Aug 2005
-
-* Minor fixes to PM854 board
- Patch by Josef Wagner, 03 Aug 2005
-
-* Adjust configuration of XENIAX board
- (chip select and GPIO required for USB operation)
-
-* Fix typos in cpu/85xx/start.S which caused DataTLB exception to be
- routed to the Watchdog handler
- Patch by Eugene Surovegin, 18 Jun 2005
-
-* (re)enabled scsi commands do_scsi() and do_scsiboot()
- Patch by Denis Peter, 06 Dec 2004
-
-* Fix endianess problem in TFTP / NFS default filenames
- Patch by Hiroshi Ito, 06 Dec 2004
-
-* Ignore broadcast status bit in received frames in 8260 FCC ethernet
- loopback test code
- Patch by Murray Jensen, 18 Jul 2005
-
-* Fix typo in mkconfig script (used == instead of =)
- Patch by Murray Jensen, 18 Jul 2005
-
-* Cleanup build problems on 64 bit build hosts
-
-* Update MAINTAINERS file
-
-* Patch by Stefan Roese, 01 Aug 2005:
- - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea
- (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup"
- for details.
- - Sycamore (PPC405GPr) eval board added (Walnut port is extended
- to run on both 405GP and 405GPr eval boards).
-
-* Patch by Steven Blakeslee, 27 Jul 2005:
- - Add support for AMCC PPC440EP/GR.
- - Add support for AMCC Yosemite PPC440EP eval board.
- - Add support for AMCC Yellowstone PPC440GR eval board.
-
-* Minor fixes for PPChameleon Board:
- - fix alignment of NAND size
- - make code do what the comment says
-
-* Implement h/w sector protection status synchronization at boot.
- The code is provided for, and was tested on, the Yukon/Alaska
- and PM520 boards only.
-
- A bug in flash_real_protect() for the Yukon board was fixed by
- adding a function that tells if two banks are on one flash chip.
-
-* Fix sysmon POST problem: check I2C error codes
- This fixes a problem of displaying bogus voltages when the voltages
- are so low that the I2C devices start failing while the rest of the
- system keeps running.
-
-* Patch by Cedric Vincent, 6 Jul 2005:
- Fix CFG_CMD_SETGETDCR handling in "common/cmd_dcr.c"
-
-* Patch by Jon Loeliger, 20 Jul 2005:
- Add missing PCI IO port definitions.
-
-* Add CompactFlash support for HMI1001 board.
-
-* Adjust printed board ID for LWMON board.
-
-* Fix low-level OHCI transfers for ARM920t and MPC5xxx
-
-* Add new argument format for flash commands to allow for usage like
- "erase $(addr) +$(filesize)", i. e. a size argument can be used and
- U-Boot will automaticially find the end of the corresponding sector.
-
-* Patch by Stefan Roese, 5 Jul 2005:
- Update uc100 board PHY setup
-
-* Patch by Stefan Roese, 1 Jul 2005:
- Fix PHY address for CATcenter board (now correct!)
-
-* Patch by Stefan Roese, 30 Jun 2005:
- Fix PHY addresses for PPChameleon and CATcenter boards
- Change MAINTAINER for most esd boards
-
-* Patch by Detlev Zundel, 30 Jun 2005:
- Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code
-
-* Fix baudrate calculation problem on MPC5200 systems
-
-* Add EEPROM and RTC support for HMI1001 board
-
-* Patch by Detlev Zundel, 20 Jun 2005:
- Fix initialization of low active GPIO pins on inka4x0 board
-
-* Enable redundant environment, disable HW flash protection of
- HMI1001 board
-
-* Patch by Travis Sawyer, 10 Jun 2005:
- Initialize allocated dev and private hw structures
- after their respective allocation in 440gx_enet.c
-
-* Patch by Steven Scholz, 10 Jun 2005:
- Fix byteorder problems with second argument of "bootm" with
- standalone images;
-
-* Add support for HMI1001 board
-
-* Disable "date" and "sntp" commands on TQM866M
-
-* Fix watchdog reset problems on LWMON board
-
-* Patch by Juergen Selent, 17 May 2005:
- Add support for Funkwerk VoVPN gateway module.
-
-* Cleanup debug code for MPC8220 FEC driver
-
-* Extend burst mode RAM test program to take a loop count
- (0 = infinite)
-
-* Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on
- those boards that use it.
-
-* Patches by Greg Ungerer, 19 May 2005:
- - add support for the KS8695P (ARM 922 based) CPU
- - add support for the OpenGear CM4008, CM4116 and CM4148 boards
-
-* Patch by Steven Scholz, 19 May 2005:
- Add support for CONFIG_SERIAL_TAG on ARM boards
-
-* Add PCI support for Sorcery board.
- Code cleanup (especially Sorcery / Alaska / Yukon serial driver).
-
-* Fix compile problems caused by new burst mode SDRAM test;
- make port pins to trigger logic analyzer configurable
-
-* Fix timer handling on MPC85xx systems
-
-* Fix debug code in omap5912osk flash driver
-
-* Add support for MPC8247 based "IDS8247" board.
-
-* Add support for 2 x TSEC interfaces on the TQM8540 board.
-
-* On LWMON we must use the watchdog to reset the board as the CPU
- genereated HRESET pulse is too short to reset the external
- circuitry.
-
-* Add test tool to exercise SDRAM accesses in burst mode
- (as standalone program, MPC8xx/PowerPC only)
-
-* Increase CFG_MONITOR_LEN for Rattler board to match actual code
- size.
-
-* Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of
- March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI
- added to support LZO and LZARI compression modes (undefined by
- default).
-
-* Fix problem with symbolic links in JFFS2 code.
-
-* Use linker ASSERT statement to prevent undetected overlapping of
- sections on PPChameleon board; other boards might use this, too.
-
-* Patch by Stefan Roese, 03 May 2005:
- Update for P3G4
- Fix problems in cmd_universe.c
-
-* Patch by Matthias Fuchs, 03 May 2005:
- Added missing variable declaration in cmd_nand.c
- Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram
-
-* Fix INKA4x0: use CS1 as gpio_wkup_6 output
-
-* Fix bug in the SDRAM initialization code for canmb, IceCube and
- PM520 boards.
- Fix PHY address for canmb board.
-
-* Cleanup serial console baudrate calculation on AT91RM9200;
- get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition
-
-* Patch by Matthias Fuchs, 18 Apr 2005:
- Make PCI target address spaces on PMC405 and CPCI405 boards
- configurable via environment variables
-
-* Auto-size RAM on canmb board.
-
-* Add support for canmb board
-
-* Patch by Stefan Roese, 13 Apr 2005:
- Update for esd apc405
-
-* Fixes for TQM8560 board:
- - fix clock rates
- - remove debug messages
- - fix flash sector protection
-
-* Patch by Steven Scholz, 07 Apr 2005:
- Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C
-
-* Patches by Steven Scholz, 07 Apr 2005:
- Fix compiler warning in altera.c
- Fix warning in cpu/arm920t/at91rm9200/i2c.c
-
-* Patch by Ladislav Michl, 06 Apr 2005:
- Fix voiceblue configuration.
-
-* Patch by Stefan Roese, 06 Apr 2005:
- Updates for OCOTEA board:
- - Changed U-Boot size from 512kByte to 256kByte
- - Fixed flash driver to support boot from soldered user flash
- - Added README for switch from PIBS firmware to U-Boot
-
-* Patch by Travis Sawyer, 05 Apr 2005:
- - Change timer frequency for ppc 440 from 10 ms to 1 ms.
- Problem found by Andrew Wozniak.
-
-* Patch by Steven Scholz, 06 Apr 2005:
- - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
- - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
-
-* Patches by Robert Whaley, 29 Nov 2004:
- - update the pxa-regs.h file for PXA27x chips
- - add PXA27x based ADSVIX board
- - add support for MMC on PXA27x processors
-
-* Patch by Andrew E. Mileski, 28 Nov 2004:
- Fix PPC4xx SPD SDRAM detection bug
-
-* Patch by Hiroshi Ito, 26 Nov 2004:
- Fix logic of "test -z" and "test -n" commands
-
-* Patch by Ladislav Michl, 05 Apr 2005:
- Add support for VoiceBlue board.
-
-* Patch by Ladislav Michl, 05 Apr 2005:
- Fix netboot_common() prototypes.
-
-* Patch by Steven Scholz, 05 Apr 2005:
- Use i.MX watchdog timer for reset_cpu()
-
-* Patch by Steven Scholz, 05 Apr 2005:
- Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific
- subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/
- (now in interupts.c)
-
-* Add support for MPC8220 based "sorcery" board.
-
-* Add support for TQM8560 board.
-
-* Add FEC support for TQM8540 board.
- Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC
-
-* Patch by Martin Krause, 04 Apr 2005:
- Update default configuration for CMC_PU2 board.
-
-* Patch by Steven Scholz, 04 Apr 2005:
- - remove all references to CONFIG_INIT_CRITICAL for ARM based boards
- - introduce two new configuration options instead:
- CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT
-
-* Patch by Steven Scholz, 04 Apr 2005:
- Make sure that MDIO clock does not exceed 2.5 MHz on AT91
-
-* Fix timer code for ARM systems: make sure that udelay() does not
- reset timers so it's save to use udelay() in timeout code.
-
-* Patch by Mathias Küster, 23 Nov 2004:
- add udelay support for the mcf5282 cpu
-
-* Patch by Tolunay Orkun, 16 November 2004:
- fix incorrect onboard Xilinx CPLD base address
-
-* Patch by Jerry Van Baren, 08 Nov 2004:
- - Add low-boot option for MPC8260ADS board (if lowboot is selected,
- the jumper for the HRCW source should select flash. If lowboot is
- not selected, the jumper for the HRCW source should select the
- BCSR.
- - change default load base address to 0x00400000
-
-* Patch by Yuli Barcohen, 08 Nov 2004:
- Add support for Analogue & Micro Rattler boards.
- Tested on Rattler8248.
-
-* Patch by Andre Renaud, 08 Nov 2004:
- Fix watchdog support in common/lcd.c
-
-* Patch by Marc Leeman, 05 Nov 2003:
- Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU
- bug only affects the XPC8245 processors
-
-* Patches by Josef Wagner, 29 Oct 2004:
- - Add support for MicroSys CPU87 board
- - Add support for MicroSys PM854 board
-
-* Patch by Jian Zhang, 02 Nov 2004:
- Add 16-bit NAND support
-
-* Patch by Scott McNutt, 01 Nov 2004:
- Add missing NIOS/NIOS2 support for "iminfo" command
-
-* Patch by Detlev Zundel, 29 Oct 2004:
- Add missing NIOS/NIOS2 support for "mkimage" tool.
-
-* Patch by David Adair, 27 Oct 2004:
- Add missing 440GX SDRAM Controller reset
-
-* Patch by Steven Scholz, 25 Oct 2004:
- Declare reset_cpu() in include/common.h instead locally
-
-* Patch by Yusdi Santoso, 22 Oct 2004:
- - Add support for HIDDEN_DRAGON board
- - fix endianess problem in driver/rtl1839.c
-
-* Patch by Allen Curtis, 21 Oct 2004:
- support multiple serial ports
-
-* Patch by Richard Klingler, 03 Apr 2005:
- Add call to eth_halt() in net/net.c when called functions fail
- after eth_init() has been called.
-
-* Patch by Sam Song, 3 April 2005:
- - Update README.Netconsole
- - Update README
-
-* Prepare for SoC rework of ARM code:
- - rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL
- - rename memsetup into lowlevel_init (function name and source files)
- Patch by Steven Scholz, 03 Apr 2005:
- - create SoC specific directories include/asm-arm/arch-imx and
- include/asm-arm/arch-s3c24x0
-
-* Fix problems with SNTP support;
- enable SNTP support in some boards.
-
-* Patches by Martin Krause, 01 Apr 2005:
- - Fix flash erase timeout on CMC_PU2
- - Add automatic HW detection for CMC_PU2 and CMC_BASIC
-
-* Patch by Steven Scholz, 13 March 2005:
- fix cache enabling for AT91RM9200
-
-* Patch by Masami Komiya, 30 Mar 2005:
- add SNTP support and expand time server and time offset fields of
- DHCP support. See doc/README.SNTP
-
-* Patch by Steven Scholz, 13 Dec 2004:
- Fix bug in at91rm920 ethernet driver
-
-* Patch by Steven Scholz, 13 Dec 2004:
- Remove duplicated code by merging memsetup.S files for
- at91rm9200 boards into one cpu/at91rm9200/lowlevel.S
-
-* Patch by Detlev Zundel, 31 Mar 2005:
- Cleanup duplicate definition of overwrite_console()
-
-* Update TQM5200 configuration;
- prepare for Rev. 200 starter kit boards
-
-* Patch by Scott McNutt, 21 Oct 2004:
- Add support for Nios-II EPCS Controller core.
-
-* Patch by Scott McNutt, 20 Oct 2004:
- Nios-II cleanups:
- - Add sysid command (Nios-II only).
- - Locate default exception trampoline at proper offset.
- - Implement I/O routines (readb, writeb, etc)
- - Implement do_bootm_linux
-
-* Patches by Martin Krause, 22 Mar 2005:
- - use TQM5200_auto as MAKEALL target for TQM5200 systems
- - add support for SM501 graphics controller
- - add support for graphic console on TQM5200
- - add support for TQM5200 Rev 200
- - cleanup, fix typo in include/configs/TQM5200.h
-
-* Patch by Manfred Baral, 17 Mar 2005:
- Fix typo
-
-* Fix RTC configuration for PPChameleon board
-
-* Cleanup, fix typo in include/configs/TQM5200.h
-
-* Patch by Stefan Roese, 16 Mar 2005:
- Update for esd auto_update and hh405 board
-
-* Adapt for U-Boot image size (new features enabled) on TQM5200
-
-* Update code for TQM8540 board (and 85xx in general):
- - Change the name of the Ethernet driver: MOTO ENET -> ENET
- - Reformat boot messages
- - Enable redundant environment
- - Replace the -O2 optimization flag with -mno-string
-
-* Patch by David Brownell, 10 Mar 2005:
- Restore copyright statements in OHCI drivers.
-
-* Add support for TQM8540 board
-
-* Patch by Detlev Zundel, 14 Mar 2005:
- NC650: changed NAND flash addressing to using UPMB
-
-* Patch by Stefan Roese, 14 Mar 2005:
- Update for esd voh405 fpga image
-
-* INKA4x0: Allow initialization of LCD backlight dimming from
- "brightness" environment variable.
-
-* Add port initialization for digital I/O on INKA4x0
-
-* Patch by Stefan Roese, 01 Mar 2005:
- Update for esd boards dp405 and hub405
-
-* Fix get_partition_info() parameter error in all other calls
- (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c).
-
-* Enable USB and IDE support for INKA4x0 board
-
-* Patch by Andrew Dyer, 28 Feb 2005:
- fix ext2load passing an incorrect pointer to get_partition_info()
- resulting in load failure for devices other than 0
-
-* Add support for SRAM and 2 x Quad UARTs on INKA4x0 board
-
-* Cleanup USB and partition defines
-
-* Add support for ext2 filesystems and image timestamps to TQM5200 board
-
-* Add reset code for Coral-P on INKA4x0 board
-
-* Patch by Martin Krause, 28 Jun 2004:
- Update for TRAB board.
-
-* Fix some missing "volatile"s in MPC5xxx FEC driver
-
-* Fix cirrus voltage detection (for CPC45)
-
-* Fix byteorder problem in usbboot and scsiboot commands.
-
-* Patch by Cajus Hahn, 04 Feb 2005:
- - don't insist on leading '/' for filename in ext2load
- - set default partition to useful value (1) in ext2load
-
-* Patch by Andrew Dyer, 08 Jan 2005:
- fix wrong return codes in ext2 code
-
-* Removed '--no-warn-mismatch' option from Makefile. This option
- makes 'ld' to overlook binary objects compatibility.
-
-* Moved $(PLATFORM_LIBS) from the library group (--start-group ...
- --end-group) outside of the group. This will make 'ld' to do
- _multiple_ search in the library group when resolving symbol
- references and do only a _single_ seach in libgcc.a after the group
- search.
-
-* Fix stability problems on CPC45 board again.
-
-* Make image detection for diskboot / usbboot / scsiboot more robust
- (also check header checksum)
-
-* Update CPC45 board configuration.
-
-* Add USB and PCI support for INKA4x0 board
-
-* Fix IDE stability problems on CPC45 board (needs 2 x EIEIO).
-
-* Code cleanup
-
-* Patch by Robin Getz, 13 Oct 2004:
- Add standalone application to change SMC91C111 MAC addresses,
- see examples/README.smc91111_eeprom
-
-* Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004:
- Fix Flash support for ARM Integrator CP.
-
-* Patch by Richard Woodruff, 10 Jan 2005:
- Update support for OMAP2420 (ARM11) and H4 board:
- o clean up and add new types to H4 memory probe code.
- o fix to work with internal boot.
- o added PRCM config III operation.
- o fix marginal flash timings.
- o add revison ATAG usage.
- o enable voltage scaling at power chip.
- o fix compile error for i2c.
-
-* Fix network problem (error when receiving multiple ARP packets)
-
-* Patch by Daniel Poirot, 12 Oct 2004:
- Add support for Wind River sbc405 board
-
-* Patch by Rainer Brestan, 12 Oct 2004:
- Make examples/Makefile more robust
-
-* Patch by Sam Song, 11 October 2004:
- - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board
- - Adjust CPU:BUS frequency ratio 1:1 when core frequency
- less than 50MHz
-
-* Patch by Sam Song, 10 Oct 2004:
- Fix a parameter error in run_command() in main.c
-
-* Patch by Richard Woodruff, 01 Oct 2004:
- add support for the TI OMAP2420 processor and its H4 reference
- board
-
-* Patch by Christian Pellegrin, 24 Sep 2004:
- Added support for NE2000 compatible (DP8390, DP83902) NICs.
-
-* Patch by Leif Lindholm, 23 Sep 2004:
- add support for the AMD db1550 board
-
-* Patch by Travis Sawyer, 15 Sep 2004:
- Add CONFIG_SERIAL_MULTI support for ppc4xx,
- update README.serial_multi
-
-* Patches by David Snowdon, 07 Sep 2004:
- - add u-boot.hex target in the top level Makefile
- - add support for the UNSW/NICTA PLEB 2 board (pleb2)
- - use -mtune=xscale and -march=armv5 options for PXA
-
-* Patch by Florian Schlote, 08 Sep 2004:
- Add support for SenTec-COBRA5272-board (ColdFire).
-
-* Patch by Gleb Natapov, 07 Sep 2004:
- mpc824x: set PCI latency timer to a sane value
- (is 0 after reset).
-
-* Patch by Kurt Stremerch, 03 Sep 2004:
- Add bitstream configuration option for fpga command (Xilinx only).
-
-* Patch by Kurt Stremerch, 03 Sep 2004:
- Add Xilinx Spartan2E family FPGA support
-
-* Patch by Jeff Angielski, 02 Sep 2004:
- Add Added support for H2 revision of the EP8260 board.
- Fixed formatting for some of the EP8260 related source files.
-
-* Patch by Jon Loeliger, 02 Sep 2004:
- Reset monitor size back to 256 so environment can be written
- to flash on MPC85xx ADS and CDS releases.
-
-* Patch by Paolo Broggini, 02 Sep 2004:
- Make BSS clearing on ARM systems more robust
-
-* Patch by Yue Hu and Joe, 01 Sep 2004:
- - add PCI support for ixp425;
- - add EEPRO100 suppor tfor ixdp425 board.
-
-* Fix problem with protected sector detection in driver/cfi_flash.c
-
-======================================================================
-Changes for U-Boot 1.1.2:
-======================================================================
-
-* Code cleanup, mostly for GCC-3.3.x
-
-* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to
- pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for
- additional ethernet addresses.
-
-* Cleanup drivers/i82365.c - avoid duplication of code
-
-* Fix bogus "cannot span across banks" flash error message
-
-* Code cleanup
-
-* Add support for CompactFlash for the CPC45 Board.
-
-* Fix problems with CMC_PU2 flash driver.
-
-* Cleanup:
- - avoid trigraph warning in fs/ext2/ext2fs.c
- - rename UC100 -> uc100
-
-* Add support for UC100 board
-
-* Patch by Stefan Roese, 16 Dez 2004:
- - ext2fs support added
- - Tundra universe support added
- - ColdFire MCF5249 support added (no preloader needed!)
- - MCF5249 board TASREG added
- - PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405,
- VOM405, WUH405
- - some esd boards updated
- - memory commands "mdc" and "mwc" added for cyclic read/write
- (CONFIG_MX_CYCLIC, see README for further description)
-
-* Add support for INKA4X0 board
-
-* Patch by Steven Scholz, 12 Dec 2004:
- Fix typo in AT91 memory setup.
-
-* Patch by Martin Krause, 27 Oct 2004:
- - add support for "STK52xx" board (including PS/2 multiplexer)
- - add hardware detection for TQM5200
-
-* Clean up CMC PU2 flash driver
-
-* Update MAINTAINERS file
-
-* Fix bug in MPC823 LCD driver
-
-* Fix udelay() on AT91RM9200 for delays < 1 ms.
-
-* Enable long help on CMC PU2 board;
- fix reset issue;
- increase CPU speed from 179 to 207 MHz.
-
-* Fix smc91111 ethernet driver for Xaeniax board (need to handle
- unaligned tail part specially).
-
-* Update for AT91RM9200DK and CMC_PU2 boards:
- - Enable booting directly from flash
- - fix CMC_PU2 flash driver
-
-* Fix mkimage usage message
-
-* Map SRAM on NC650 board
-
-* Work around for Ethernet problems on Xaeniax board
-
-* Patch by TsiChung Liew, 23 Sep 2004:
- - add support for MPC8220 CPU
- - Add support for Alaska and Yukon boards
-
-* Fix configuration for ERIC board (needs more room)
-
-* Adjust MIPS compiler options at run-time depending on tools version
- ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new,
- "-mcpu=4kc" for old tools)
-
-* Add passing of the command line and memory size information to the
- kernel on xaeniax board.
-
-* Enable NAND flash support for NC650 board.
-
-* Patch by Thomas Lange 07 Oct 2004:
- Updated README for DBAu1x00 boards to match current status
-
-* Patch by Philippe Robin, 28 Sept 2004:
- Fix Flash support for Versatile.
-
-* Patch by Roger Blofeld, 16 Sep 2004:
- Fix timeout for DHCP command retry
-
-* Patch by Pantelis Antoniou, 14 Sep 2004:
- Fix early serial hang when CONFIG_SERIAL_MULTI is defined.
-
-* Patch by Pantelis Antoniou, 14 Sep 2004:
- Kick watchdog when bz-decompressing
-
-* Fix CFG_HZ problems on AT91RM9200 systems
- [Remember: CFG_HZ should be 1000 on ALL systems!]
-
-* Patch by Gridish Shlomi, 30 Aug 2004:
- - Add support to revA version of PQ27 and PQ27E.
- - Reverted MPC8260ADS baudrate back to original 115200
-
-* Patch by Hojin, 17 Sep 2004:
- Fix typo in cfi_flash.c
-
-* Patch by Mark Jonas, 09 September 2004:
- mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong
- error message
-
-* Patch by Mark Jonas, 31 August 2004:
- Added option CFG_XLB_PIPELINING to enable XLB pipelining. This
- improves FTP performance for MPC5200 systems. Enabled for IceCube
- by default.
-
-* Patch by Michael Bendzick, 30 Aug 2004:
- - Improve platform.S code for omap1510inn that detects whether code
- is running from SDRAM or not. Patch allows SDRAM to be configured
- if code is running out of SRAM at 0x20000000.
-
-* Patch by Frederick Klatt, 30 Aug 2004:
- Add support for the Wind River SBC8540/SBC8560 boards
-
-* Configure SX1 board to use drivers/cfi_flash.c
-
-* Patches by Michael Bendzick, 30 Aug 2004:
- - Configure omap1510inn board to use drivers/cfi_flash.c
- - Make drivers/cfi_flash.c protect environment and redundant
- environment.
-
-* Patch by Steven Scholz, 23 Jun 2004:
- - Add script (tools/img2brec.sh) to programm U-Boot into
- (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L
-
-* Patches by Scott McNutt, 24 Aug 2004:
- - Add support for Altera Nios-II processors.
- - Add support for Psyent PCI-5441 board.
- - Add support for Psyent PK1C20 board.
-
-* Patches by Jon Loeliger, 24 Aug 2004:
- - Add support for the MPC8541 and MPC8555 CDS boards
- - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
- - Convert MPC85xxADS to use common CFI flash driver
- - Fix PCI window on MPC85xx; remove unneeded PCI initialization
- from board_early_init_f()
- - Provide SW workaround for PCI initialization on 85xx CDS
-
-* Patches by George G. Davis, 24 Aug 2004:
- - Enable ramdisk/initrd tagged param support for omap1610h2_config
- - Remove static network setup defaults from mx1ads_config
- - update ARM boards to use constants from mach-types.h
-
-* Patch by Gary Jennejohn, 04 Oct 2004:
- - fix I2C on at91rm9200
- - add support for Ricoh RS5C372A RTC
-
-* Patch by Gary Jennejohn, 01 Oct 2004:
- - add support for CMC PU2 board
- - add support for I2C on at91rm9200
-
-* Patch by Gary Jennejohn, 28 Sep 2004:
- fix baudrate handling on at91rm9200
-
-* Patch by Yuli Barcohen, 22 Aug 2004:
- - remove ZPC.1900 board-specific flash driver;
- switch the port to generic CFI driver;
- - port clean-up
-
-* Patch by Hinko Kocevar, 21 Aug 2004:
- Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB
-
-* Clean up tools/bmp_logo.c to not add trailing white space
-
-* Patch by Hinko Kocevar, 21 Aug 2004:
- - Group common framebuffer functions in common/lcd.c
- - Group common framebuffer macros and #defines in include/lcd.h
- - Provide calc_fbsize() for video ATAG
-
-* Patch by Sam Song, 21 August 2004:
- - Fix a typo in README
- - Align "(RO)" output for "flinfo" after "protect on"
- - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency
- ratio 1:1 when core frequency less than 50MHz
-
-* Patches by Hinko Kocevar, 21 Aug 2004:
- - fix some "use of label at end of compound statement" warnings
- - Define type of LCD panel on lubbock board if CONFIG_LCD is used
-
-* Patch by Steven Scholz, 16 Aug 2004:
- - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)"
- - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0
- - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/
- - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/
- into cpu/arm920t/$(SOC)/
-
-* Patches by Sean Chang, 09 Aug 2004:
- - Added support for both 8 and 16 bit mode access to System ACE CF
- through MPU.
- - Fixed missing System ACE CF device during get FAT partition info
- in fat_register_device function.
- - Enabled System ACE CF support on ML300.
-
-* Patch by Sean Chang, 09 Aug 2004:
- Synch defines for saveenv and do_saveenv functions so they get
- compiled under the same statement.
-
-* Patch by Sean Chang, 09 Aug 2004:
- - Added I2C support for ML300.
- - Added support for ML300 to read out its environment information
- stored on the EEPROM.
- - Added support to use board specific parameters as part of
- U-Boot's environment information.
- - Updated MLD files to support configuration for new features
- above.
-
-* Patches by Travis Sawyer, 05 Aug 2004:
- - Remove incorrect bridge settings for eth group 6
- - Add call to setup bridge in ppc_440x_eth_initialize
- - Fix ppc_440x_eth_init to reset the phy only if its the
- first time through, otherwise, just check the phy for the
- autonegotiated speed/duplex. This allows the use of netconsole
- - only print the speed/duplex the first time the phy is reset.
-
-* Patch by Shlomo Kut, 29 Mar 2004:
- Add support for MKS Instruments "Quantum" board
-
-* Fix build problem with Cogent boards;
- avoid using <asm/byteorder.h> when using the host compiler
-
-* Patch by Ganapathi C, 04 Aug 2004:
- Fix NFS timeout issue
-
-* Patch by Yuli Barcohen, 19 Jul 2004:
- - Fix host tools building in Cygwin environment
- - Fix header files search order for host tools
-
-* Patch by Tom Armistead, 19 Jul 2004:
- Fix kgdb.S support for 74xx_75x cpu
-
-* Patch by Jon Loeliger, 15 Jul 2004:
- Fix MPC85xx I2C driver
-
-* Fix problems with CDROM drive as slave device on Lite5200 IDE bus.
-
-* Patch by Stephen Williams, 15 July 2004
- Set the PCI class code for JSE board as part of PCI interface setup
-
-* Patch by Michael Bendzick, 15 Jul 2004:
- Fix problem with writes with odd sizes in drivers/cfi_flash.c when
- CFG_FLASH_USE_BUFFER_WRITE is set
-
-* Patch by Yuli Barcohen, 13 Jul 2004:
- Allow clock setting on MPC866/MPC885 series chips according to
- environment variable `cpuclk'
-
-* Patch by Yuli Barcohen, 20 Apr 2004:
- Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
-
-* Patch by Vincent Dubey, 24 Sep 2004:
- Add support for xaeniax board
-
-* Add comment about non-GPL character of standalone applications to
- COPYING file
-
-* Fix FEC ethernet problem on NSCU board.
-
-* Patch by Gary Jennejohn, 09 Sep 2004:
- allow to use USART1 as console port on at91rm9200dk boards
-
-* Patch by Stefan Roese, 16 Sep 2004:
- Update AR405 board.
-
-* Fix SysClk handling for PPChameleon and CATcenter boards
-
-* Patch by Detlev Zundel, 08 Sep 2004:
- Update etags build target
-
-* Improve NetConsole support: add support for broadcast destination
- address and buffered input.
-
-* Cleanup compiler warnings for GCC 3.3.x and later
-
-* Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch
-
-* Add support for IDS "NC650" board
-
-* Add automatic update support for LWMON board
-
-* Clear Block Lock-Bits when erasing flash on LWMON board.
-
-* Fix return code of "fatload" command
-
-* Enable MSDOS/VFAT filesystem support for LWMON board
-
-* Patch by Martin Krause, 03 Aug 2004:
- change timing for SM501 graphics controller on TQM5200 module
-
-* Patch by Mark Jonas, 13 July 2004:
- - Total5200 LCD now run in little endian mode. Endianess conversion
- is done in hardware.
- - Removed last reference to "console" environment variable.
-
-* Patches by Lars Munch, 12 Jul 2004:
- - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk
- board specific
- - split out the LXT971A PHY from ns_9750_eth.h
- - split the dm9161 phy part out of at91rm9200_ether.c
-
-* Patch by Andreas Engel, 12 Jul 2004:
- Replaced hardcoded PL011 clock frequency with config variable.
- Fixed wrong CONFIG_CMD_DFL doc.
-
-* Patch by Thomas Viehweger, 09 Jun 2004:
- make it possible to remove chpart when there is only one partition
-
-* Add support for console over UDP (compatible to Ingo Molnar's
- netconsole patch under Linux)
-
-* Patch by Jon Loeliger, 16 Jul 2004:
- - support larger DDR memories up to 2G on the PC8540/8560ADS and
- STXGP3 boards
- - Made MPC8540/8560ADS be 33Mhz PCI by default.
- - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
- and CONFIG_L2_INIT_RAM options.
- - Refactor Local Bus initialization out of SDRAM setup.
- - Re-implement new version of LBC11/DDR11 errata workarounds.
- - Moved board specific PCI init parts out of CPU directory.
- - Added TLB entry for PCI-1 IO Memory
- - Updated README.mpc85xxads
-
-* Patch by Sascha Hauer, 28 Jun:
- - add generic support for Motorola i.MX architecture
- - add support for mx1ads, mx1fs2 and scb9328 boards
-
-* Patches by Marc Leeman, 23 Jul 2004:
- - Add define for the PCI/Memory Buffer Configuration Register
- - corrected comments in cpu/mpc824x/cpu_init.c
-
-* Add support for multiple serial interfaces
- (for example to allow modem dial-in / dial-out)
-
-* Patch by Stefan Roese, 15 Jul 2004:
- cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
-
-* Fix NSCU config; add ethernet wakeup code.
-
-* Add link for preloader for Motorola ColdFire to README.m68k
-
-* Patch by Michael Bendzick, 12 Jul 2004:
- fix output formatting in drivers/cfi_flash.c
-
-* Patch by Mark Jonas, 02 Jul 2004:
- Fix lowboot (again) on MPC5xxx
-
-* Patch by Curt Brune, 07 Jul 2004:
- relocate exception vectors on arm720t if needed
-
-* Patch by George G. Davis, 06 Jul 2004:
- - update mach-types.h to latest arm.linux.org.uk master list
- - Set correct OMAP1610 bi_arch_number for build target
-
-* Patch by Curt Brune, 06 Jul 2004:
- evb4510: add support for timer interrupt; cleanup
-
-* Patch by Dan Poirot, 06 Jul 2004:
- Fix sbc8260 environment variables
-
-* Cleanup redundand "console" environment variable
-
-* Patch by Mark Jonas, 05 Jul 2004:
- add support for the Total5100's and Total5200's LCD screen
-
-* Patches by Dan Eisenhut, 01 Jul 2004:
- - README fixes.
- - Move doc2000.h include to prevent compiler warning on some boards
-
-* Patch by Mark Jonas, 01 Jul 2004:
- Added support for Total5100 and Total5200 (Rev.1 and Rev.2)
- MGT5100 and MPC5200 based Freescale platforms.
-
-* Patch by Philippe Robin, 01 Jul 2004:
- Add initialization for Integrator and versatile board files.
-
-* Patch by Hinko Kocevar, 01 Jun 2004:
- Fix VFD FB allocation, add LCD FB allocation on ARM
-
-* Patch by Martin Krause, 30 Jun 2004:
- Add support for TQM5200 board
-
-* Patch by Martin Krause, 29 Jun 2004:
- Add loopw command: infinite write loop on address range
-
-* Patches by Yasushi Shoji, 29 Jun 2004:
- - add empty include/asm-microblaze/processor.h
- - add to CREDITS and MAINTAINERS
- - add gd initialization
- - add MicroBlaze and SUZAKU board to MAKEALL script
- - add reset support for SUZAKU
- - add flush_cache() for MicroBlaze
- - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed
- size flash memory on SUZAKU
-
-* Patch by Prakash Kumar, 27 Jun 2004:
- Add support for the PXA250 based Intrinsyc Cerf board.
-
-* Patch by Yasushi Shoji, 27 Jun 2004:
- fix comment in include/common.h
-
-* Rename SBC8560 into sbc8560 for consistency
-
-* Patch by Daniel Poirot, 24 Jun 2004:
- Add support for Wind River's sbc8240 board
-
-* Patches by Yasushi Shoji, 26 Jun 2004:
- - drivers/serial_xuartlite.c: fix "return 0" in void function
- - add microblaze support to mkimage tool
-
-* Patch by Fred Klatt, 25 Jun 2004:
- Add support for WindRiver's sbc8560 board
-
-* Patch by Nicolas Lacressonniere, 24 Jun 2004
- Small Bugs fixes for "at91rm9200dk" board:
- - Timing modifications for SPI DataFlash access
- - Fix NAND flash detection bug
-
-* Patch by Nicolas Lacressonniere, 24 Jun 2004:
- Add Support for Flash AT49BV6416 for AT91RM9200DK board
-
-* Patch by Jon Loeliger, 17 June 2004:
- Completion of the 8540ADS/8560ADS updates:
- Fix some PCI and Rapid I/O memory maps,
- Initialize both TSEC 1 and 2,
- Initialize SDRAM
- Update MAINTAINER for 85xx boards and README.mpc85xxads
-
-* Patch by Yuli Barcohen, 16 Jun 2004:
- Remove obsolete AdderII port which was superseded by unified
- AdderII/Adder87x port
-
-* Patch by Ladislav Michl, 16 Jun 2004:
- Fix gcc-3.3.3 warnings for smc91111.c
-
-* Patch by Stefan Roese, 02 Jul 2004:
- - Fix bug in 405 ethernet driver; allocated data not cleared!
- - Fix problem in 405 i2c driver; don't try to print without console!
-
-* Patch by Paul Ruhland, 11 Jun 2004:
- Remove debug code from 'board/lpd7a40x/flash.c'
-
-* Patch by Andrea Marson, 11 Jun 2004:
- Update for PPChameleon board:
- - support for SysClk @ 25MHz
- - support for Silicon Motion SM712 VGA controller
- - some clean ups
-
-* Patches by Richard Woodruff, 10 Jun 2004:
- - fix problems with examples/stubs.c for GCC >= 3.4
- - fix problems with gd initialization
-
-* Patch by Curt Brune, 17 May 2004:
- - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
- - Add support for ESPD-Inc. EVB4510 Board
-
-* Patch by Marc Leeman, 11 May 2004:
- Fix for MPC8245 - reading PPC Memory from another device with the
- PPC as PCI target device corrupts data due to interenal hardware
- buffering.
-
-* Fix "cls" command when used with splash screen
-
-* Increase NFS download timeout (now 1 min - 10 sec is to short for a
- slow download of a big image)
-
-* Add "cls" function to MPC823 LCD driver so we can reinitialize the
- display even after showing a bitmap
-
-* Patch by Josef Wagner, 04 Jun 2004:
- - DDR Ram support for PM520 (MPC5200)
- - support for different flash types (PM520)
- - USB / IDE / CF-Card / DiskOnChip support for PM520
- - 8 bit boot rom support for PM520/CE520
- - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
- - I2C and RTC support for CPC45
- - support of new flash type (28F160C3T) for CPC45
-
-* Fix flash parameters passed to Linux for PPChameleon board
-
-* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
-
-* Patch by Paul Ruhland, 10 Jun 2004:
- fix support for Logic SDK-LH7A404 board and clean up the
- LH7A404 register macros.
-
-* Patch by Matthew McClintock, 10 Jun 2004:
- Modify code to select correct serial clock on Sandpoint8245
-
-* Patch by Robert Schwebel, 10 Jun 2004:
- Add support for Intel K3 strata flash.
-
-* Patch by Thomas Brand, 10 Jun 2004:
- Fix "loads" command on DK1S10 board
-
-* Patch by Yuli Barcohen, 09 Jun 2004:
- Add support for 8MB flash SIMM and JFFS2 file system on
- Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS).
-
-* Patch by Yuli Barcohen, 09 Jun 2004:
- Add support for Analogue&Micro Adder87x and the older AdderII board.
-
-* Patch by Ming-Len Wu, 09 Jun 2004:
- Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
-
-* Patch by Sam Song, 09 Jun 2004:
- - Add support for RPXlite_DW board
- - Update FLASH driver for 4*AM29DL323DB90VI
- - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board
-
-* Patch by Mark Jonas, 08 June 2004:
- - Make MPC5200 boards evaluate the SVR to print processor name and
- version in checkcpu() (cpu/mpc5xxx/cpu.c).
-
-* Patch by Kai-Uwe Bloem, 06 May 2004:
- Fix endianess problem in cramfs code
-
-* Patch by Tom Armistead, 04 Jun 2004:
- Add support for MAX6900 RTC
-
-* Patches by Ladislav Michl, 03 Jun 2004:
- - fix cfi_flash.c on LE systems
- - let 'make mrproper' delete u-boot.img as well
- - turn printf into debug in cfi_flash.c
-
-* Patch by Kurt Stremerch, 28 May 2004:
- Add support for Exys XSEngine board
-
-* Patch by Martin Krause, 27 May 2004:
- Fix a MPC5xxx I2C timing issue in i2c_probe().
-
-* Patch by Leif Lindholm, 27 May 2004:
- Fix board_init_f() for dbau1x00 board.
-
-* Patch by Imre Deak, 26 May 2004:
- On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3).
- Set flash base accordingly, and decide whether to do or skip board
- specific setup steps.
-
-* Patch by Josef Baumgartner, 26 May 2004:
- Add missing define in include/asm-m68k/global_data.h
-
-* Patch by Josef Baumgartner, 25 May 2004:
- Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c
-
-* Patch by Paul Ruhland, 24 May 2004:
- fix SDRAM initialization for LPD7A400 board.
-
-* Patch by Jian Zhang, 20 May 2004:
- add support for environment in NAND flash
-
-* Patch by Yuli Barcohen, 20 May 2004:
- Add support for Interphase iSPAN boards.
-
-* Patches by Paul Ruhland, 17 May 2004:
- - Add I/O functions to the smc91111 ethernet driver to support the
- Logic LPD7A40x boards.
- - Add support for the Logic Zoom LH7A40x based SDK board(s),
- specifically the LPD7A400.
-
-* Patches by Robert Schwebel, 15 May 2004:
- - call MAC address reading code also for SMSC91C111;
- - make SMSC91C111 timeout configurable, remove duplicate code
- - fix get_timer() for PXA
- - update doc/README.JFFS2
- - use "bootfile" env variable also for jffs2
-
-* Patch by Tolunay Orkun, 14 May 2004:
- Add support for Cogent CSB472 board (8MB Flash Rev)
-
-* Patch by Thomas Viehweger, 14 May 2004:
- - flash.h: more flash types added
- - immap_8260.h: some bits added (useful for RMII)
- - cmd_coninfo.c: typo corrected, printf -> puts
- - reduced size by replacing spaces with tab
-
-* Patch by Robert Schwebel, 13 May 2004:
- Add 'imgextract' command: extract one part of a multi file image.
-
-* Patches by Jon Loeliger, 11 May 2004:
- Dynamically handle REV1 and REV2 MPC85xx parts.
- (Jon Loeliger, 10-May-2004).
- New consistent memory map and Local Access Window across MPC85xx line.
- New CCSRBAR at 0xE000_0000 now.
- Add RAPID I/O memory map.
- New memory map in README.MPC85xxads
- (Kumar Gala, 10-May-2004)
- Better board and CPU identification on MPC85xx boards at boot.
- (Jon Loeliger, 10-May-2004)
- SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
- Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
- (Jim Robertson, 10-May-2004)
- Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
- Supports multiple PHYs.
- (Andy Fleming, 10-May-2004)
- Some README.MPC85xxads updates.
- (Kumar Gala, 10-May-2004)
- Copyright updates for "Freescale"
- (Andy Fleming, 10-May-2004)
-
-* Patch by Stephen Williams, 11 May 2004:
- Add flash support for ST M29W040B
- Reduce JSE specific flash.c to remove dead code.
-
-* Patch by Markus Pietrek, 04 May 2004:
- Fix clear_bss code for ARM systems (all except s3c44b0 which
- doesn't clear BSS at all?)
-
-* Fix "ping" problem on INC-IP board. Strange problem:
- Sometimes the store word instruction hangs while writing to one of
- the Switch registers, but only if the next instruction is 16-byte
- aligned. Moving the instruction into a separate function somehow
- makes the problem go away.
-
-* Patch by Rishi Bhattacharya, 08 May 2004:
- Add support for TI OMAP5912 OSK Board
-
-* Patch by Sam Song May, 07 May 2004:
- Fix typo of UPM table for rmu board
-
-* Patch by Pantelis Antoniou, 05 May 2004:
- - Intracom board update.
- - Add Codec POST.
-
-* Add support for the second Ethernet interface for the 'PPChameleon'
- board.
-
-* Patch by Dave Peverley, 30 Apr 2004:
- Add support for OMAP730 Perseus2 Development board
-
-* Patch by Alan J. Luse, 29 Apr 2004:
- Fix flash chip-select (OR0) option register setting on FADS boards.
-
-* Patch by Alan J. Luse, 29 Apr 2004:
- Report MII network speed and duplex setting properly when
- auto-negotiate is not enabled.
-
-* Patch by Jarrett Redd, 29 Apr 2004:
- Fix hang on reset on Ocotea board due to flash in wrong mode.
-
-* Patch by Dave Peverley, 29 Apr 2004:
- add MAC address detection to smc91111 driver
-
-* Patch by David Müller, 28 Apr 2004:
- fix typo in lib_arm/board.c
-
-* Patch by Tolunay Orkun, 20 Apr 2004:
- - README update: add CONFIG_CSB272 and csb272_config
- - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and
- i2cfast environment variable
-
-* Patch by Yuli Barcohen, 19 Apr 2004:
- - Rename DUET_ADS to MPC885ADS
- - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
- - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
- - Clean up FADS family port to use the new defines
-
-* Fix PCI support on CPC45 board
-
-* Patch by Scott McNutt, 25 Apr 2004:
- Add Nios GDB/JTAG Console support:
- - Add stubs to support gdb via JTAG.
- - Add support for console over JTAG.
- - Minor cleanup.
-
-* Add support for CATcenter board (based on PPChameleon ME module)
-
-* Patch by Klaus Heydeck, 12 May 2004:
- Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
- load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;
- various changes to KUP4 board specific files
-
-* Fix minor network problem on MPC5200: need some delay between
- resetting the PHY and sending the first packet. Implemented in a
- "natural" way by invoking the PHY reset and initialization code
- only once after power on vs. each time the interface is brought up.
-
-* Add some limited support for low-speed devices to SL811 USB controller
- (at least "usb reset" now passes successfully and "usb info" displays
- correct information)
-
-* Change init sequence for multiple network interfaces: initialize
- on-chip interfaces before external cards.
-
-* Fix memory leak in the NAND-specific JFFS2 code
-
-* Fix SL811 USB controller when attached to a USB hub
-
-* Fix config option spelling in PM520 config file
-
-* Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by
- patches by Pantelis Antoniou, 30 Mar 2004)
-
-* Fix minor NAND JFFS2 related issue
-
-* Fixes for SL811 USB controller:
- - implement workaround for broken memory stick
- - improve error handling
-
-* Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better
- cope with congested networks.
-
-======================================================================
-Changes for U-Boot 1.1.1:
-======================================================================
-
-* Patch by Travis Sawyer, 23 Apr 2004:
- Fix VSC/CIS 8201 phy descrambler interoperability timing due to
- errata from Vitesse Semiconductor.
-
-* Patch by Philippe Robin, 22 Apr 2004:
- Fix ethernet configuration for "versatile" board
-
-* Patch by Kshitij Gupta, 21 Apr 2004:
- Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards
-
-* Patch by Steven Scholz, 24 Feb 2004:
- Fix a bug in AT91RM9200 ethernet driver:
- The MII interface is now initialized before accessing the PHY.
-
-* Patch by John Kerl, 19 Apr 2004:
- Use U-boot's miiphy.h for PHY register names, rather than
- introducing a new header file.
-
-* Update pci_ids.h from linux-2.4.26
-
-* Patch by Masami Komiya, 19 Apr 2004:
- Fix problem cause by VLAN function on little endian architecture
- without VLAN environment
-
-* Clean up the TQM8xx_YYMHz configurations; allow to use the same
- binary image for all clock frequencies. Implement run-time
- optimization of flash access timing based on the actual bus
- frequency.
-
-* Modify KUP4X board configuration to use SL811 driver for USB memory
- sticks (including FAT / VFAT filesystem support)
-
-* Add SL811 Host Controller Interface driver for USB
-
-* Add CFG_I2C_EEPROM_ADDR_OVERFLOW desription to README
-
-* Patch by Pantelis Antoniou, 19 Apr 2004:
- Allow to use shell style syntax (i. e. ${var} ) with standard parser.
- Minor patches for Intracom boards.
-
-* Patch by Christian Pell, 19 Apr 2004:
- cleanup support for CF/IDE on PCMCIA for PXA25X
-
-* Temporarily disabled John Kerl's extended MII command code because
- "miivals.h" is missing
-
-* Patches by Mark Jonas, 13 Apr 2004:
- - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S
- - Add sync instructions to IceCube SDRAM init code
- - Move SDRAM chip constants into seperate include files
- - Unify DDR and SDR initialization code
- - Unify all IceCube (Lite5xxx) target names
-
-* Patch by John Kerl, 16 Apr 2004:
- Enable ranges in mii command, e.g. mii read 0-1f 0 or
- mii read 4-7 18-1a. Also add mii dump subcommand for
- pretty-printing standard regs 0-5.
-
-* Patch by Stephen Williams, 16 April 2004:
- fix typo in JSE.h; update MAINTAINERS
-
-* Patch by Matthew S. McClintock, 14 Apr 2004:
- fix initdram function for utx8245 board
-
-* Patch by Markus Pietrek, 14 Apr 2004:
- use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag
-
-* Patch by Reinhard Meyer, 18 Apr 2004:
- provide the IDE Reset Function for EMK 5200 boards
-
-* Patch by Masami Komiya, 12 Apr 2004:
- fix pci_hose_write_config_{byte,word}_via_dword problems
-
-* Patch by Sangmoon Kim, 12 Apr 2004:
- Update max RAM size for debris board
-
-* Patch by Travis Sawyer, 08 Apr 2004:
- Add TLB entry for second DIMM slot on ocotea
-
-* Patch by Masami Komiya, 08 Apr 2004:
- add RTL8169 network driver
-
-* Patch by Dan Malek, 07 Apr 2004:
- - Add support for RPC/STx GP3, Motorola 8560 board
- - Update 85xx TSEC driver so it searches MII for first available PHY
- and uses that one.
- - Add functions to support console MII commands.
-
-* Patch by Tolunay Orkun, 07 Apr 2004:
- Move initialization of bi_iic_fast[]
- from board_init_f() to board_init_r()
-
-* Patch by Yasushi Shoji, 07 Apr 2004:
- Cleanup microblaze port
-
-* Patch by Sangmoon Kim, 07 Apr 2004:
- Add auto SDRAM module detection for Debris board
-
-* Patch by Rune Torgersen, 06 Apr 2004:
- - Fix some PCI problems on the MPC8266ADS board
- - Fix the location of some PCI entries in the immap structure
-
-* Patch by Yasushi Shoji, 07 Apr 2004:
- - add support for microblaze processors
- - add support for AtmarkTechno "suzaku" board
-
-* Configure PPChameleon board to use redundand environment in flash
-
-* Configure PPChameleon board to use JFFS2 NAND support.
-
-* Added support for JFFS2 filesystem (read-only) on top of NAND flash
-
-* Patch by Rune Torgersen, 16 Apr 2004:
- LBA48 fixes
-
-* Patches by Pantelis Antoniou, 16 Apr 2004:
- - add support for a new version of an Intracom board and fix
- various other things on others.
- - add verify support to the crc32 command (define
- CONFIG_CRC32_VERIFY to enable it)
- - fix FEC driver for MPC8xx systems:
- 1. fix compilation problems for boards that use dynamic
- allocation of DPRAM
- 2. shut down FEC after network transfers
- - HUSH parser fixes:
- 1. A new test command was added. This is a simplified version of
- the one in the bourne shell.
- 2. A new exit command was added which terminates the current
- executing script.
- 3. Fixed handing of $? (exit code of last executed command)
- - Fix some compile problems;
- add "once" functionality for the netretry variable
-
-* Patch by George G. Davis, 02 Apr 2004:
- add support for Intel Assabet board
-
-* Patch by Stephen Williams, 01 Apr 2004:
- Add support for Picture Elements JSE board
-
-* Patch by Christian Pell, 01 Apr 2004:
- Add CompactFlash support for PXA systems.
-
-* Patches by Pantelis Antoniou, 30 Mar 2004:
- - add auto-complete support to the U-Boot CLI
- - add support for NETTA and NETPHONE boards; fix NETVIA board
- - add support for the Epson 156x series of graphical displays
- (These displays are serial and not suitable for using a normal
- framebuffer console on them)
- - add infrastructure needed in order to POST any DSPs in a board
- - improve and fix various things in the MPC8xx FEC driver:
- 1. The new 87x and 88x series of processors have two FECs,
- and the new driver supports them both.
- 2. Another change in the 87x/88x series is support for
- the RMII (Reduced MII) interface. However numerous
- changes are needed to make it work since the PHYs
- are connected to the same lines. That means that
- you have to address them correctly over the MII
- interface.
- 3. We now correctly match the MII/RMII interface
- configuration to what the PHY reports.
- - Fix problem when readingthe MII status register. Due to the
- internal design of many PHYs you have to read the register
- twice. The problem is more apparent in 10Mbit mode.
- - add new mode ".jffs2s" for reading from a NAND device: it just
- skips over bad blocks.
- - add networking support for VLANs (802.1q), and CDP (Cisco
- Discovery Protocol)
- - some minor patches / cleanup
-
-* Patch by Yuli Barcohen, 28 Mar 2004:
- - Add support for MPC8272 family including MPC8247/8248/8271/8272
- - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS)
- - Change configuration method for MPC8260ADS family
-
-* add startup code to clear the BSS of standalone applications
-
-* Fix if / elif handling bug in HUSH shell
-
-======================================================================
-Changes for U-Boot 1.1.0:
-======================================================================
-
-* Patch by Mark Jonas: Remove config.tmp files only when
- unconfiguring the board
-
-* Adapt RMU board for bigger flash memory
-
-* Patch by Klaus Heydeck, 13 Mar 2003:
- Add support for KUP4X Board
-
-* Patch by Pavel Bartusek, 21 Mar 2004
- Add Reiserfs support
-
-* Patch by Hinko Kocevar, 20 Mar 2004
- - Add auto-release for SMSC LAN91c111 driver
- - Add save/restore of PTR and PNR regs as suggested in datasheet
-
-* Patch by Stephen Williams, 19 March 2004
- Increase speed of sector reads from SystemACE,
- shorten poll timeout and remove a useless reset
-
-* Patch by Tolunay Orkun, 19 Mar 2004:
- Make GigE PHY 1000Mbps Speed/Duplex detection conditional
- (CONFIG_PHY_GIGE)
-
-* Patch by Brad Kemp, 18 Mar 2004:
- prevent machine checks during a PCI scan
-
-* Patch by Pierre Aubert, 18 Mar 2004:
- Fix string cleaning in IDE identification
-
-* Patch by Pierre Aubert, 18 Mar 2004:
- - Unify video mode handling for Chips & Technologies 69000 Video
- chip and Silicon Motion SMI 712/710/810 Video chip
- - Add selection of the video output (CRT or LCD) via 'videoout'
- environment variable for the Silicon Motion
- - README update
-
-* Patch by Pierre Aubert, 18 Mar 2004:
- include/common.h typo fix
-
-* Patches by Tolunay Orkun, 17 Mar 2004:
- - Add support for bd->bi_iic_fast[] initialization via environment
- variable "i2cfast" (CONFIG_I2CFAST)
- - Add "i2cfast" u-boot environment variable support for csb272
-
-* Patch by Carl Riechers, 17 Mar 2004:
- Ignore '\0' characters in console input for use with telnet and
- telco pads.
-
-* Patch by Leon Kukovec, 17 Mar 2004:
- typo fix for strswab prototype #ifdef
-
-* Patches by Thomas Viehweger, 16 Mar 2004:
- - show PCI clock frequency on MPC8260 systems
- - add FCC_PSMR_RMII flag for HiP7 processors
- - in do_jffs2_fsload(), take load address from load_addr if not set
- explicit, update load_addr otherwise
- - replaced printf by putc/puts when no formatting is needed
- (smaller code size, faster execution)
-
-* Patch by Phillippe Robin, 16 Mar 2004:
- avoid dereferencing NULL pointer in lib_arm/armlinux.c
-
-* Patch by Stephen Williams, 15 Mar 2004:
- Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation
-
-* Patch by Tolunay Orkun, 15 Mar 2004:
- Initialize bi_opbfreq to real OPB frequency via get_OPB_freq()
-
-* Patch by Travis Sawyer, 15 Mar 2004:
- Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port
-
-* Add start-up delay to make sure power has stabilized before
- attempting to switch on USB on SX1 board.
-
-* Patch by Josef Wagner, 18 Mar 2004:
- - Add support for MicroSys XM250 board (PXA255)
- - Add support for MicroSys PM828 board (MPC8280)
- - Add support for 32 MB Flash on PM825/826
- - new SDRAM refresh rate for PM825/PM826
- - added support for MicroSys PM520 (MPC5200)
- - replaced Query by Identify command in CPU86/flash.c
- to support 28F160F3B
-
-* Fix wrap around problem with udelay() on ARM920T
-
-* Add support for Macronix flash on TRAB board
-
-* Patch by Pierre Aubert, 15 Mar 2004:
- Fix buffer overflow in IDE identification
-
-* Fix power-off of LCD for out-of-band temperatures on LWMON board
-
-* Remove redundand #define in IceCube.h
-
-* Patch by Steven Scholz, 27 Feb 2004:
- - Adding get_ticks() and get_tbclk() for AT91RM9200
- - Many white space fixes in cpu/at91rm9200/interrupts.c
-
-* Patches by Steven Scholz, 20 Feb 2004:
- some cleanup in AT91RM9200 related code
-
-* Patches by Travis Sawyer, 12 Mar 2004:
- - Fix Gigabit Ethernet support for 440GX
- - Add Gigabit Ethernet Support to MII PHY utilities
-
-* Patch by Brad Kemp, 12 Mar 2004:
- Fixes for drivers/cfi_flash.c:
- - Better support for x8/x16 implementations
- - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE
- - Added defines for AMD command and address constants
-
-* Patch by Leon Kukovec, 12 Mar 2004:
- Fix get_dentfromdir() to correctly handle deleted dentries
-
-* Patch by George G. Davis, 11 Mar 2004:
- Remove hard coded network settings in TI OMAP1610 H2
- default board config
-
-* Patch by George G. Davis, 11 Mar 2004:
- add support for ADS GraphicsClient+ board.
-
-* Patch by Pierre Aubert, 11 Mar 2004:
- - add bitmap command and splash screen support in cfb console
- - add [optional] origin in the bitmap display command
-
-* Patch by Travis Sawyer, 11 Mar 2004:
- Fix ocotea board early init interrupt setup.
-
-* Patch by Thomas Viehweger, 11 Mar 2004:
- Remove redundand code; add PCI-specific bits to include/mpc8260.h
-
-* Patch by Stephan Linz, 09 Mar 2004
- - Add support for the SSV ADNP/ESC1 (Nios Softcore)
-
-* Patch by George G. Davis, 9 Mar 2004:
- fix recent build failure for SA1100 target
-
-* Patch by Travis Sawyer, 09 Mar 2004:
- Support native interrupt mode for the IBM440GX.
- Previously it was running in 440GP compatibility mode.
-
-* Patch by Philippe Robin, 09 Mar 2004:
- Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference
- Platform support.
-
-* Patch by Masami Komiya, 08 Mar 2004:
- Don't overwrite server IP address or boot file name
- when the boot server does not return values
-
-* Patch by Tolunay Orkun, 5 Mar 2004:
- Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC
-
-* Patch by Tolunay Orkun, 5 Mar 2004:
- Fix early board initialization for Cogent CSB272 board
-
-* Patch by Ed Okerson, 3 Mar 2004:
- fix CFI flash writes for little endian systems
-
-* Patch by Reinhard Meyer, 01 Mar 2004:
- generalize USB and IDE support for MPC5200 with according
- changes to IceCube.h and TOP5200.h
- add Am29LV256 256 MBit FLASH support for TOP5200 boards
- add info about USB and IDE to README
-
-* Patch by Yuli Barcohen, 4 Mar 2004:
- Fix problems with GCC 3.3.x which changed handling of global
- variables explicitly initialized to zero (now in .bss instead of
- .data as before).
-
-* Patch by Leon Kukovec, 02 Mar 2004:
- add strswab() to fix IDE LBA capacity, firmware and model numbers
- on little endian machines
-
-* Patch by Masami Komiya, 02 Mar 2004:
- - Remove get_ticks() from NFS code
- - Add verification of RPC transaction ID
-
-* Patch by Pierre Aubert, 02 Mar 2004:
- cleanup for IDE and USB drivers for MPC5200
-
-* Patch by Travis Sawyer, 01 Mar 2004:
- Ocotea:
- - Add IBM PPC440GX Ref Platform support (Ocotea)
- Original code by Paul Reynolds <PaulReynolds@lhsolutions.com>
- Adapted to U-Boot and 440GX port
- 440gx_enet.c:
- - Add gracious handling of all Ethernet Pin Selections for 440GX
- - Add RGMII selection for Cicada CIS8201 Gigabit PHY
- ppc440.h:
- - Add needed bit definitions
- - Fix formatting
-
-* Patch by Carl Riechers, 1 Mar 2004:
- Add PPC440GX prbdv0 divider to fix memory clock calculation.
-
-* Patch by Stephan Linz, 27 Feb 2004
- - avoid problems for targets without NFS download support
-
-* Patch by Rune Torgersen, 27 Feb 2004:
- - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA)
- - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF)
- - Added support for 64bit strtoul (CFG_64BIT_STRTOUL)
-
-* Patch by Masami Komiya, 27 Feb 2004:
- Fix rarpboot: add autoload by NFS
-
-* Patch by Dan Eisenhut, 26 Feb 2004:
- fix flash_write return value in saveenv
-
-* Patch by Stephan Linz, 11 Dec 2003
- expand config.mk to avoid trigraph warnings on NIOS
-
-* Rename "BMS2003" board into "HMI10"
-
-* SX1 patches: use "serial#" for USB serial #; use redundand environment
- storage; auto-set console on USB port (using preboot command)
-
-* Add support for SX1 mobile phone; add support for USB-based console
- (enable with "setenv stdout usbtty; setenv stdin usbtty")
-
-* Fix LOWBOOT configuration for MPC5200 with DDR memory
-
-* Fix SDRAM timings for LITE5200 / IceCube board
-
-* Handle Auti-MDIX / connection status for INCA-IP
-
-* Fix USB problems when attempting to read 0 bytes
-
-* Patch by Travis Sawyer, 26 Feb 2004:
- Fix broken compile for XPEDITE1K target.
-
-* Patch by Stephan Linz, 26 Feb 2004:
- Bug fix for NFS code on NIOS targets
-
-* Patch by Stephen Williams, 26 Feb 2004:
- Break up SystemACE reads of large block counts
-
-* Patch by Pierre Aubert, 26 Feb 2004
- add IDE support for MPC5200
-
-* Patch by Masami Komiya, 26 Feb 2004:
- add autoload via NFS
-
-* Patch by Stephen Williams
- Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses
- elsewhere in the source.
-
-* Patch by Steven Scholz, 25 Feb 2004:
- - Timeouts in FPGA code should be based on CFG_HZ
- - Minor cleanup in code for Altera FPGA ACEX1K
-
-* Patch by Steven Scholz, 25 Feb 2004:
- Changed "Directory Hierarchy" section in README
-
-* Patch by Masami Komiya, 25 Feb 2004:
- Reduce copy count in nfs_read_reply() of NFS code
-
-* Patch by Markus Pietrek, 24 Feb 2004:
- NS9750 DevBoard added
-
-* Patch by Pierre Aubert, 24 Feb 2004
- add USB support for MPC5200
-
-* Patch by Steven Scholz, 24 Feb 2004:
- - fix MII commands to use values from last command
-
-* Patch by Torsten Demke, 24 Feb 2004:
- Add support for the eXalion platform (SPSW-8240, F-30, F-300)
-
-* Patch by Rahul Shanbhag, 19 Feb 2004:
- Fixes for for OMAP1610 board:
- - shift some IRQ specific code to platform.S file
- - remove duplicatewatchdog reset code from start.S
-
-* Make Auto-MDIX Support configurable on INCA-IP board
-
-* Fix license for mkimage tool
-
-* Patch by Masami Komiya, 24 Feb 2004:
- Update NetBootFileXferSize in NFS code
-
-* Patch by Scott McNutt, 24 Feb 2004:
- fix packet length in NFS code
-
-* Patch by Masami Komiy, 22 Feb 2004:
- Add support for NFS for file download
-
-* Patch by Andrea Scian, 17 Feb 2004:
- Add support for S3C44B0 processor and DAVE B2 board
-
-* Patch by Steven Scholz, 20 Feb 2004:
- - Add support for MII commands on AT91RM9200 boards
- - some cleanup in AT91RM9200 ethernet code
-
-* Patch by Peter Ryser, 20 Feb 2004:
- Add support for the Xilinx ML300 platform
-
-* Patch by Stephan Linz, 17 Feb 2004:
- Fix watchdog support for NIOS
-
-* Patch by Josh Fryman, 16 Feb 2004:
- Fix byte-swapping for cfi_flash.c for different bus widths
-
-* Patch by Jon Diekema, 14 Jeb 2004:
- Remove duplicate "FPGA Support" notes from the README file
-
-* Patches by Reinhard Meyer, 14 Feb 2004:
- - update board/emk tree; use common flash driver
- - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c
- [adapted for other PPC CPUs -- wd]
- - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c
-
-* Patch by Jon Diekema, 13 Feb 2004:
- Call show_boot_progress() whenever POST "FAILED" is printed.
-
-* Patch by Nishant Kamat, 13 Feb 2004:
- Add support for TI OMAP1610 H2 Board
- Fixes for cpu/arm926ejs/interrupt.c
- (based on Richard Woodruff's patch for arm925, 16 Oct 03)
- Fix for a timer bug in OMAP1610 Innovator
- Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2
-
-* Patches by Stephan Linz, 12 Feb 2004:
- - add support for NIOS timer with variable period preload counter value
- - prepare POST framework support for NIOS targets
-
-* Patch by Denis Peter, 11 Feb 2004:
- add POST support for the MIP405 board
-
-* Patch by Laurent Mohin, 10 Feb 2004:
- Fix buffer overflow in common/usb.c
-
-* Patch by Tolunay Orkun, 10 Feb 2004:
- Add support for Cogent CSB272 board
-
-* Patch by Thomas Elste, 10 Feb 2004:
- Add support for NET+50 CPU and ModNET50 board
-
-* Patch by Sam Song, 10 Feb 2004:
- Fix typos in cfi_flash.c
-
-* Patch by Leon Kukovec, 10 Feb 2004
- Fixed long dir entry slot id calculation in get_vfatname
-
-* Patch by Robin Gilks, 10 Feb 2004:
- add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==,
- !=, <>, <, >, <=, >=)
-
-* Fix problem with side effects in macros in include/usb.h
-
-* Patch by David Benson, 13 Nov 2003:
- bug 841358 - fix TFTP download size limit
-
-* Fixing bug 850768:
- improper flush_cache() in load_serial()
-
-* Fixing bug 834943:
- MPC8540 - missing volatile declarations
-
-* Patch by Stephen Williams, 09 Feb 2004:
- Add support for Xilinx SystemACE chip:
- - New files common/cmd_ace.c and include/systemace.h
- - Hook systemace support into cmd_fat and the partition manager
-
-* Patch by Travis Sawyer, 09 Feb 2004:
- Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux
-
-* Patch by Travis Sawyer, 09 Feb 2004:
- o 440GX:
- - Fix PCI Indirect access for type 1 config cycles with ppc440.
- - Add phymode for 440 enet
- - fix pci pre init
- o XPedite1K:
- - Change board_pre_init to board_early_init_f
- - Add user flash to bus controller setup
- - Fix pci pre init
- - Fix is_pci_host to check GPIO for monarch bit
- - Force xpedite1k to pci conventional mode (via #define option)
-
-* Patch by Brad Kemp, 4 Feb 2004:
- - handle the machine check that is generated during the PCI scans
- on 82xx processors.
- - define the registers used in the IMMR by the PCI subsystem.
-
-* Patch by Pierre Aubert, 03 Feb 2004:
- cpu/mpc5xxx/start.S: copy MBAR into SPR311
-
-* Patch by Jeff Angielski, 03 Feb 2004:
- Fix copy & paste error in cpu/mpc8260/pci.c
-
-* Patch by Reinhard Meyer, 24 Jan 2004:
- Fix typo in cpu/mpc5xxx/pci_mpc5200.c
-
-* Add Auto-MDIX support for INCA-IP
-
-* Some code cleanup
-
-* Patch by Josef Baumgartner, 10 Feb 2004:
- Fixes for ColdFire port
-
-* Patch by Brad Kemp, 11 Feb 2004:
- Fix CFI flash driver problems
-
-* Make sure to use a bus clock divider of 2 only when running TQM8xxM
- modules at CPU clock frequencies above 66 MHz.
-
-* Optimize flash programming speed for LWMON (by another 100% :-)
-
-* Patch by Jian Zhang, 3 Feb 2004:
- - Changed the incorrect FAT12BUFSIZE
- - data_begin in fsdata can be negative. Changed it to be short.
-
-* Patches by Stephan Linz, 30 Jan 2004:
- 1: - board/altera/common/flash.c:flash_erase():
- o allow interrupts befor get_timer() call
- o check-up each erased sector and avoid unexpected timeouts
- - board/altera/dk1c20/dk1s10.c:board_early_init_f():
- o enclose sevenseg_set() in cpp condition
- - remove the ASMI configuration for DK1S10_standard_32 (never present)
- - fix some typed in mistakes in the NIOS documentation
- 2: - split DK1C20 configuration into several header files:
- o two new files for each NIOS CPU description
- o U-Boot related part is remaining in DK1C20.h
- 3: - split DK1S10 configuration into several header files:
- o two new files for each NIOS CPU description
- o U-Boot related part is remaining in DK1S10.h
- 4: - Add support for the Microtronix Linux Development Kit
- NIOS CPU configuration at the Altera Nios Development Kit,
- Stratix Edition (DK-1S10)
- 5: - Add documentation for the Altera Nios Development Kit,
- Stratix Edition (DK-1S10)
- 6: - Add support for the Nios Serial Peripharel Interface (SPI)
- (master only)
- 7: - Add support for the common U-Boot SPI framework at
- RTC driver DS1306
-
-* Patch by Rahul Shanbhag, 28 Jan 2004:
- Fix flash protection/locking handling for OMAP1610 innovator board.
-
-* Patch by Rolf Peukert, 28 Jan 2004:
- fix flash write problems on CSB226 board (write with 32 bit bus width)
-
-* Patches by Mark Jonas, 16 Jan 2004:
- - fix rounding error when calculating baudrates for MPC5200 PSCs
- - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same
- time which is not supported
-
-* Patch by Yuli Barcohen, 26 Jan 2004:
- Allow bzip2 compression for small memory footprint boards
-
-* Patch by Brad Kemp, 21 Jan 2004:
- Add support for CFI flash driver for both the Intel and the AMD
- command sets.
-
-* Patch by Travis Sawyer, 20 Jan 2004:
- Fix pci bridge auto enumeration of sibling p2p bridges.
-
-* Patch by Tolunay Orkun, 12 Jan 2004:
- Add some delays as needed for Intel LXT971A PHY support
-
-* Patches by Stephan Linz, 09 Jan 2004:
- - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c
- - make DK1C20 board configuration related to ASMI conform to
- documentation
-
-* Patch by Anders Larsen, 09 Jan 2004:
-
- ARM memory layout fixes: the abort-stack is now set up in the
- correct RAM area, and the BSS is zeroed out as it should be.
-
- Furthermore, the magic variables 'armboot_end' and 'armboot_end_data'
- of the linker scripts are replaced by '__bss_start' and '_end',
- resp., which is a further step to eliminate unnecessary differences
- between the implementation of the CPU architectures.
-
-* Patch by liang a lei, 9 Jan 2004:
- Fix Intel 28F128J3 ID in include/flash.h
+ README says CFG_AUTO_COMPLETE, but ocde uses CONFIG_AUTO_COMPLETE
-* Patch by Masami Komiya, 09 Jan 2004:
- add support for TB0229 board (NEC VR4131 MIPS processor)
+commit 471a7be7a042e95e440f5de969c9765214ae8d6e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sat Oct 28 01:14:32 2006 +0200
-* Patch by Leon Kukovec, 12 Dec 2003:
- changed extern __inline__ into static __inline__ in
- include/linux/byteorder/swab.h
+ Check for illegal character '=' in environment variable names.
-* Patch by Travis Sawyer, 30 Dec 2003:
- Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
- select MDI port based on enabled EMAC device.
- Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX
- base PrPMC board.
+ Make sure the string passed as variable name does not contain a '='
+ character. This not only prevents the common error or typing
+ "setenv foo=bar" instead of "setenv foo bar", but (more importantly)
+ also closes a backdoor which allowed to delete write-protected
+ environment variables, for example by using "setenv ethaddr=".
-* Patch by Wolter Kamphuis, 15 Dec 2003:
- made CONFIG_SILENT_CONSOLE usable on all architectures
+commit 19973b6ad9863a56f5c5fbcfd90e20ab2490a2c2
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Sat Oct 28 00:38:39 2006 +0200
-* Disable date command on TQM866M - there is no RTC on MPC866
+ Minor code cleanup.
-* Fix variable CPU clock for MPC859/866 systems for low CPU clocks
+commit e11887a77d81077416a2d1c5e0354916fee8c034
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Thu Oct 26 17:55:31 2006 +0200
-* Implement adaptive SDRAM timing configuration based on actual CPU
- clock frequency for INCA-IP; fix problem with board hanging when
- switching from 150MHz to 100MHz
+ Don't pass any debug options directly to the assembler
-* Add PCMCIA CS support for BMS2003 board
+ When passing the -g option to gcc, gcc automatically selects a
+ suitable --g<format> option to pass on to the assembler.
+ Thus, there's no point in forcing a specific debug option on the
+ assembler using the -Wa mechanism.
-* Add variable CPU clock for MPC859/866 systems (so far only TQM866M):
- see doc/README.MPC866 for details;
- implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866;
- calculate CPU clock frequency from PLL register values.
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
-* Add support for 128 MB RAM on TQM8xxL/M modules
+commit ea08ff6e14f9ebb8c07cfa79c51ef540eb087393
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Fri Oct 27 07:47:22 2006 -0500
-* Fix PS/2 keyboard problem caused by statically initialized variable
- pointing to a location in flash
+ MPC86xx: Cleaned up unused and conditionally used local variables.
-* Fix INCA-IP clock calculation: 400/3 = 133.3 MHz, not 130.
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* The PS/2 mux on the BMS2003 board needs 450 ms after power on
- before we can access it; add delay in case we are faster (with no
- CF card inserted)
+commit d38936cdae46bfd2623ff83f6ce9b616d36ab0f9
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Fri Oct 27 11:55:21 2006 +0200
-* Cleanup of some init functions
+ Fix "ar" flags in some Makefiles to allow for silent "make -s"
-* Make sure SCC Ethernet is always stopped by the time we boot Linux
- to avoid Linux crashes by early packets coming in.
+commit 4653f91c13ed51c21cc4c3855745d69a3fb1817f
+Author: Ben Warren <bwarren@qstreams.com>
+Date: Thu Oct 26 14:38:25 2006 -0400
-* Accelerate flash accesses on LWMON board by using buffered writes
+ Fix TSEC driver (now for real): avoid crashes if PHY is not attached
+ to a TSEC (e.g. a switch is connected via RMII) or
+ if the PHY is defective/incorrectly configured.
-* Fix typo in Makefile;
- fix problem with PARTNUM detection
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
-* Patch by Reinhard Meyer, 09 Jan 2004:
- - add RTC support for MPC5200 based boards (requires RTC_XTAL)
+commit b985b5d6e4fb88f508f7aa0f126c2e27ada2b999
+Author: Ben Warren <bwarren@qstreams.com>
+Date: Thu Oct 26 14:38:25 2006 -0400
-* Add support for IDE LED on BMS2003 board
- (exclusive with status LED!)
+ Fix TSEC driver: avoid crashes if PHY is not attached
+ to a TSEC (e.g. a switch is connected via RMII) or
+ if the PHY is defective/incorrectly configured.
-* Add support for PS/2 keyboard (used with PS/2 multiplexor on
- BMS2003 board)
+ Signed-off-by: Ben Warren <bwarren@qstreams.com>
-* Patches by Reinhard Meyer, 4 Jan 2004 + 7 Jan 2004:
- Add common files for "emk" boards
+commit 2b2a40bebbf1822506e80e631d7253e60f0e0fe6
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Thu Oct 26 16:24:31 2006 +0200
-* Add a common get_ram_size() function and modify the the
- board-specific files to invoke that common implementation.
+ Code cleanup.
-======================================================================
-Changes for U-Boot 1.0.1:
-======================================================================
+commit 5e3b0bc19f07ed277d85324ad0427642c8981baf
+Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Wed Oct 25 15:48:59 2006 +0200
-* Set default clock for INCA-IP to 150 MHz
+ Finish up support for the ATSTK1000/ATSTK1002 boards
-* Make BMS2003 use a separate config file to avoid #ifdef mess;
- add I2C support; add support for DS1337 RTC
+ Add atstk1002_config target to Makefile and move the AVR32 section
+ down below Blackfin so that it doesn't end up in the middle of
+ MIPS.
-* Add CompactFlash support for BMS2003 board
+ Drop the autogenerated linker script thing for now. Will have to
+ revisit how to handle chips with different flash and RAM layout
+ later.
-* Add support for status LED on BMS2003 board
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
-* Patch by Scott McNutt, 02 Jan 2004:
- Add support for the Nios Active Serial Memory Interface (ASMI)
- on Cyclone devices
+commit c76f951a747cfb87ba826ef45b5aea82d5b5dbb4
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Oct 24 23:47:37 2006 -0500
-* Patch by Andrea Marson, 16 Dec 2003:
- Add support for the PPChameleon ME and HI modules
+ Added support for Multi-Image files that contain a device tree
-* Patch by Yuli Barcohen, 22 Dec 2003:
- Add support for Motorola DUET ADS board (MPC87x/88x)
+ If a Multi-Image file contains a third image we try to use it as a
+ device tree. The device tree image is assumed to be uncompressed in the
+ image file. We automatically allocate space for the device tree in memory
+ and provide an 8k pad to allow more than a reasonable amount of growth.
-* Patch by Robert Schwebel, 15 Dec 2003:
- add support for cramfs (uses JFFS2 command interface)
+ Additionally, a device tree that was contained in flash will now automatically
+ get copied to system memory as part of boot. Previously an error was
+ reported if one tried to boot a device tree that was in flash.
-* Patches by Stephan Linz, 11 Dec 2003:
- - more documentation for NIOS port
- - new struct nios_pio_t, struct nios_spi_t
- - Reconfiguration for NIOS Development Kit DK1C20:
- o move board related code from board/dk1c20
- to board/altera/dk1c20
- o create a new common source path board/altera/common
- and move generic flash access stuff into it
- o change/expand configuration file DK1C20.h
- - Add support for NIOS Development Kit DK1S10
- - Add status LED support for NIOS systems
- - Add dual 7-segment LED support for Altera NIOS DevKits
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-* Patch by Ronen Shitrit, 10 Dec 2003:
- Add support for the Marvell DB64360 / DB64460 development boards
+commit 7c52c4b943ff52bbe8796a7e2d3e476ceaf3f512
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Oct 24 21:35:55 2006 +0200
-* Patch by Detlev Zundel, 10 Dec 2003:
- fix dependency problem in examples/Makefile
+ Switch to automatically generated CHANGELOG file.
+ (use "make CHANGELOG" to update it from time to time)
-* Patch by Denis Peter, 8 Dec 2003
- - add support for the PATI board (MPC555)
- - add SPI support for the MPC5xx
+commit 7ade0c634a979c32fa91a74e8f5775f24651fbe6
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Oct 24 18:06:48 2006 +0200
-* Patch by Anders Larsen, 08 Dec 2003:
- add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG
- to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target;
- cleanup some redundand #defines
+ Fix bug in PPC440 NAND driver cpu/ppc4xx/ndfc.c
+ Patch by Stefan Roese, 24 Oct 2006
-* Patch by André Schwarz, 8 Dec 2003:
- fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM):
- - TX and RX deskriptors must be quad-word aligned
- - does not work with only one TX deskriptor
- - standard reset method does not work
+commit 8ae3b713b2286e0c3213b7802062e4c1599010de
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 17:24:55 2006 +0200
-* Patch by Masami Komiya, 08 Dec 2003:
- add RTL8139 ethernet driver
+ Merge with /home/wd/git/u-boot/master
-* Patches by Ed Okerson, 07 Dec 2003:
- - fix ethernet for the AU1x00 processors in little-endian mode.
- - extend memsetup.S for the AU1x00 processors in BE and LE modes
+commit 47a6989c10685d2ab3efcf95228ce50d2a496d3e
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 15:32:57 2006 +0200
-* Minor code cleanup (coding style)
+ Code cleanup
-* Patch by Reinhard Meyer, 30 Dec 2003:
- - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
- - added CONFIG_PHY_ADDR to include/configs/IceCube.h,
- - turned debug print of PHY registers into a function (called in two places)
- - added support for EMK MPC5200 based modules
+commit 3a78e3e75b633ecb6413114ffd11e2f000c4f11e
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 14:51:36 2006 +0200
-* Fix MPC8xx PLPRCR_MFD_SHIFT typo
+ Move atstk1000 files into vendor specific directory.
+ Patch by Haavard Skinnemoen, 12 Sep 2006
-* Add support for TQM866M modules
+commit 6ccec4492e77428fd6eafd3dfe94fbdf08e91d37
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 14:42:37 2006 +0200
-* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)
+ Add ATSTK1000 and ATSTK1002 board support
+ Patch by Haavard Skinnemoen, 06 Sep 2006
-* Fix a few compiler warnings
+ This patch adds support for the ATSTK1000 with the ATSTK1002 CPU
+ daughterboard.
-* Patch by Reinhard Meyer, 28 Dec 2003:
- Add initial support for TOP5200 board
-
-* Make CPU clock on ICA-IP board controllable by a "cpuclk"
- environment variable which can set to "100", "133", or "150". The
- CPU clock will be configured accordingly upon next reboot. Other
- values are ignored. In case of an invalid or undefined "cpuclk"
- value, the compile-time default CPU clock speed will be used.
-
-* Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory
- window that is used to access the UART registers by the Linux driver)
-
-* Patch by Reinhard Meyer, 20 Dec 2003:
- Fix clock calculation for the MPC5200 for higher clock frequencies
- (above 2**32 / 10 = 429.5 MHz).
-
-* Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration
-
-* Fix IceCube CLKIN configuration (it's 33.000000MHz)
-
-* Add new configuration for IceCube board with DDR memory
-
-* Update TRAB memory configurations
-
-* Add JFFS2 support for INCA-IP board
-
-* Patch by Bill Hargen, 09 Dec 2003:
- - BUBINGA405EP: changed flash driver to protect top sector containing
- first instruction.
- - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM.
- - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access).
- - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1).
- - 405EP: added/fixed support for "reginfo" command.
- - 4xx: removed spurious MII error messages on "mii info" command.
-
-* Patch by Bernhard Kuhn, 28 Nov 2003:
- add support for ColdFire CPU
- add support for Motorola M5272C3 and M5282EVB boards
-
-* Patch by Pierre Aubert, 24 Nov 2003:
- - add a return value for the fpga command
- - add ide_preinit() function called in ide_init if CONFIG_IDE_PREINIT
- is defined. If ide_preinit fails, ide_init is aborted.
- - fix an endianess problem in fat.h
-
-* Patch by Wolter Kamphuis, 05 Dec 2003:
- Add support for SNMC's QS850/QS823/QS860T boards
-
-* Patch by Yuli Barcohen, 3 Dec 2003:
- "revive" U-Boot support for old Motorola MPC860ADS board
-
-* Patch by Cam(ilo?), 03 Dec 2003:
- make examples build even with broken Montavista objcopy
+ ATSTK1000 is a full-featured development board for AT32AP CPUs. It
+ has two ethernet ports, a high quality QVGA LCD panel, a loudspeaker,
+ and connectors for USART, PS/2, VGA, USB, MMC/SD cards and
+ CompactFlash cards. For more information, please see this page:
-* Patch by Pavel Bartusek, 27 Nov 2003:
- fix conversion problem with "bootretry" evironment variable
+ http://www.atmel.com/dyn/products/tools.asp?family_id=682
-* Patch by Andre Schwarz, 24 Nov 2003:
- add support for mvblue (mvBlueLYNX and mvBlueBOX) boards
+ The ATSTK1002 is a daughterboard for the ATSTK1000 supporting the
+ AT32AP7000 chip.
-* Patch by Pavel Bartusek, 21 Nov 2003:
- set ZMII bridge speed on 440
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
-* Patch by Anders Larsen, 17 Nov 2003:
- Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h
+commit f93ae788c3640fcde5db383471d45548ff4060d0
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 14:31:24 2006 +0200
-* Patches by David Müller, 14 Nov 2003:
- - board/mpl/common/common_util.c
- * implement support for BZIP2 compressed images
- * various cleanups (printf -> puts, ...)
- - board/mpl/common/flash.c
- * report correct errors to upper layers
- * check the erase fail and VPP low bits in status reg
- - board/mpl/vcma9/cmd_vcma9.c
- - board/mpl/vcma9/flash.c
- * various cleanups (printf -> puts, ...)
- - common/cmd_usb.c
- * fix typo in comment
- - cpu/arm920t/usb_ohci.c
- * support for S3C2410 is missing in #if line
- - drivers/cs8900.c
- * reinit some registers in case of error (cable missing, ...)
- - fs/fat/fat.c
- * support for USB/MMC devices is missing in #if line
- - include/configs/MIP405.h
- - include/configs/PIP405.h
- * enable BZIP2 support
- * enlarge malloc space to 1MiB because of BZIP2 support
- - include/configs/VCMA9.h
- * enable BZIP2 support
- * enlarge malloc space to 1MiB because of BZIP2 support
- * enable USB support
- - lib_arm/armlinux.c
- * change calling convention of ARM Linux kernel as
- described on http://www.arm.linux.org.uk/developer/booting.php
+ Add common serial driver for Atmel AT32 and AT91 chips
+ Patch by Haavard Skinnemoen, 06 Sep 2006
-* Patch by Thomas Lange, 14 Nov 2003:
- Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs to
- support all these AMD boards.
+ This is a first attempt at creating a common serial driver for Atmel
+ chips. For now, it supports the AT32AP7000 AVR32 chip, but it should
+ be possible to support AT91RM9200 and other ARM-based chips with some
+ minor modifications.
-* Patch by Thomas Lange, 14 Nov 2003:
- Workaround for mips au1x00 physical memory accesses (the au1x00
- uses a 36 bit bus internally and cannot access physical memory
- directly. Use the uncached SDRAM address instead of the physical
- one.)
+ There's nothing fundamentally AVR32-specific in this driver, but it
+ does use some features which are currently only defined for the
+ AT32AP CPU port:
+ * pm_get_clock_freq: Obtain the clock frequency of a given domain
+ * gd->console_uart: A "struct device" containing information about
+ register mappings, gpio resources and clocks associated with the
+ UART device.
-* Patch by Xue Ligong (Joe), 13 Nov 2003:
- add Realtek 8019 ethernet driver
+ For more information about these features, please see the "AT32AP
+ CPU" patch.
-* Patch by Yuli Barcohen, 13 Nov 2003:
- MPC826xADS/PQ2FADS cleanup
+commit 72a087e04705c26cad982879ebd06b5281bf825a
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 14:27:35 2006 +0200
-* Patch by Anders Larsen, 12 Nov 2003:
- Update README to mark the PORTIO commands non-standard
+ Add AT32AP CPU and AT32AP7000 SoC support
+ Patch by Haavard Skinnemoen, 06 Sep 2006
-* Patch by Nicolas Lacressonnière, 12 Nov 2003:
- update for for Atmel AT91RM9200DK development kit:
- - support for environment variables in DataFlash
- - Atmel DataFlash AT45DB1282 support
+ This patch adds support for the AT32AP CPU family and the AT32AP7000
+ chip, which is the first chip implementing the AVR32 architecture.
-* Patch by Jeff Carr, 11 Nov 2003:
- add support for new version of 8270 processors
+ The AT32AP CPU core is a high-performance implementation featuring a
+ 7-stage pipeline, separate instruction- and data caches, and a MMU.
+ For more information, please see the "AVR32 AP Technical Reference":
-* Patches by George G. Davis, 05 Nov 2003:
- - only pass the ARM linux initrd tag to the kernel when an initrd
- is actually present
- - update omap1510inn configuration file
+ http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf
-* Patches by Stephan Linz, 3 Nov 2003:
- - more endianess fixes for LAN91C111 driver
- - CFG_HZ configuration patch for NIOS Cyclone board
+ In addition to this, the AT32AP7000 chip comes with a large set of
+ integrated peripherals, many of which are shared with the AT91 series
+ of ARM-based microcontrollers from Atmel. Full data sheet is
+ available here:
-* Patch by Stephan Linz, 28 Oct 2003:
- fix PHY_INT_REG vs. PHY_MASK_REG bug in drivers/smc91111.c
+ http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf
-* Patch by Steven Scholz, 20 Oct 2003:
- - make "mii info <addr>" show infor for PHY at "addr" only
- - Endian fix for miiphy_info()
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
-* Patch by Gleb Natapov, 19 Sep 2003:
- Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c
+commit 7b64fef33c66be648826c0ff9758298ef13d0604
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 14:21:16 2006 +0200
-* Patch by Anders Larsen, 17 Sep 2003:
- Bring ARM memory layout in sync with the documentation:
- stack and malloc-heap are now located _below_ the U-Boot code
+ Add AVR32 architecture support
+ Patch by Haavard Skinnemoen, 6 Sep 2006 16:23:02 +0200
-* Accelerate booting on TRAB board: read and check autoupdate image
- headers first instead of always reading the whole images.
+ This patch adds common infrastructure code for the Atmel AVR32
+ architecture. See doc/README.AVR32 for details.
-* Fix type in MPC5XXX code (pointed out by Victor Wren)
+ Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
-* Enabled password check on RMU board
+commit 2da2d9a4766063b9848f3a35ad6025499cf87265
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 13:57:33 2006 +0200
-* Fix configuration problem with IceCube in LOWBOOT configuration:
- envrionment got embedded, corrupting the image layout.
+ Use -g instead of -gstabs in AFLAGS_DEBUG
+ Patch by Haavard Skinnemoen, 30 Aug 2006
-* Fix NEC display names (it's 6440 [for 640x480], not 6640).
+ In config.mk, -Wa,-gstabs is unconditionally appended to AFLAGS no
+ matter what the target's preferred debugging format is. This patch
+ simply replaces -gstabs with -g, so that the default debugging format
+ for the architecture is used.
-* Added BMS2003 board
- add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display
+commit 965829872169c2996023840d98e1d85ad148d629
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date: Tue Oct 24 13:55:18 2006 +0200
-* Fix flash driver for TRAB board (must use Unlock Bypass Reset
- command to exit Unlock Bypass Mode); adjust timings for flash, SRAM
- and CPLD
+ Fix/workaround broken dependency handling with make 3.81
+ Based on patch by Haavard Skinnemoen, 29 Aug 2006 11:20:39 +0200
-* Use "-fPIC" instead of "-mrelocatable" to prevent problems with
- recent tools
+commit 8318fbf8cc30418b621ea9f39b84b4c1a08f003a
+Author: Marian Balakowicz <m8@semihalf.com>
+Date: Mon Oct 23 22:17:05 2006 +0200
-* Add checksum verification to 'imls' command
+ Fix sequoia separate object direcory building problems.
-* Add bd_info fields needed for 4xx Linux I2C driver
+commit 3dfa9cfdcee78b30da3432318b32821ffabe974b
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Fri Oct 20 17:16:35 2006 -0500
-* Patch by Martin Krause, 4 Nov. 2003:
- Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap)
+ Use generic I2C register block on 85xx and 86xx.
-* Print used network interface when CONFIG_NET_MULTI is set
+ Replace private IMMAP I2C structures with generic reg block
+ and allow 86xx to have multiple I2C device busses.
-* Patch by Bernhard Kuhn, 28 Oct 2003:
- Add low boot support for MPC5200
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Fix problem with dual PCMCIA support (NSCU)
+commit f5012827df11ca0c9be1df5f8b153e188dc2fa7c
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Fri Oct 20 15:54:34 2006 -0500
-* Fix MPC5200 I2C initialization function
+ Fix compilation warnings on a few 85xx boards.
-======================================================================
-Changes for U-Boot 1.0.0:
-======================================================================
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Fix parameter passing to standalone images with bootm command
+commit 2047672684cf85cb6f96a1fbc993180aaaf19a99
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Fri Oct 20 15:50:15 2006 -0500
-* Patch by Kyle Harris, 30 Oct 2003:
- Fix build errors for ixdp425 board
+ Converted all 85xx boards to use a common FSL I2C driver.
+ Introduced COFIG_FSL_I2C to select the common FSL I2C driver.
+ And removed hard i2c path from a few u-boot.lds scipts too.
+ Minor whitespace cleanups along the way.
-* Patch by David M. Horn, 29 Oct 2003:
- Fixes to build under CYGWIN
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Get IceCube MGT5100 working (again)
+commit 4d45f69e362b05892c9e92a7907e5820995612aa
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Oct 19 12:02:24 2006 -0500
-* Fix problems in memory test on some boards (which was not
- non-destructive as intended)
+ Rewrite a series of goto statements as a sequences of
+ conditional expressions instead.
-* Patch by Gary Jennejohn, 28 Oct 2003:
- Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack
- to prevent stack overflow on ARM systems
+ Use consistent return code 0/-1 for good/bad indicators.
-* Patch by Stephan Linz, 28 Oct 2003:
- fix init sequence error for NIOS port
+ Include one fewer file if the driver isn't used at all.
-* Allow lowercase spelling for IceCube_5200; support MPC5200LITE name
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Add CONFIG_VERSION_VARIABLE to TRAB configuration
+commit 7237c033b02fe295880435f1eb80819a0c987532
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Oct 19 11:02:16 2006 -0500
-* Patch by Xiao Xianghua, 23 Oct 2003:
- small patch for mpc85xx
+ Moved i2c driver out of cpu/mpc86xx/i2c.c into drivers/fsl_i2c.c
-* Fix small problem in MPC5200 I2C driver
+ in an effort to begin to unify the umpteen FSL I2C drivers that
+ are all otherwise very similar.
-* Fix FCC3 support on ATC board
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Correct header printing for multi-image files in do_bootm()
+commit 13a7fcdf37f6ea9429ae04c9df67f893364cfe4b
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Oct 19 11:33:52 2006 -0500
-* Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED
+ * Fix a bunch of compiler warnings for gcc 4.0
-* Fix PCI problems on PPChameleon board
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Patch by Steven Scholz, 18 Oct 2003:
- Fix AT91RM9200 ethernet driver
+commit af9e1f5b9e6f9ce810f5e8bf2961c9542a5865c2
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Oct 17 06:14:31 2006 +0200
-* Patch by Nye Liu, 17 Oct 2003:
- Fix typo in include/mpc8xx.h
+ Add monitor functions for indirect access to PPC440 DCR's
+ Patch by Leonid Baryudin, 12 Oct 2006
-* Patch by Richard Woodruff, 16 Oct 03:
- Fixes for cpu/arm925/interrupt.c
- - Initialize timestamp & lastdec vars.
- - fix timestamp overflows.
- - fix lastdec overflow.
- - smarter normalization to allow udelay() below 1ms to work.
+commit 5f3249a0a168e446a4cc9669b2bce0bc456f0a09
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Fri Oct 13 16:47:53 2006 -0500
-* Patch by Scott McNutt, 16 Oct
- add networking support for the Altera Nios Development Kit,
- Cyclone Edition (DK-1C20)
+ Fixed leading whitespace issues.
+ Removed spurious LAWAR thing.
-* Patch by Jon Diekema, 14 Oct 2003:
- add hint about doc/README.silent to README file
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Add CompactFlash support for NSCU
+commit 0ee90cb77e01d6e8ccd37e1bd96678597875c391
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Oct 12 10:42:36 2006 -0500
-* Fix PCI problems on PPChameleonEVB
+ Remove unneeded include files and local variable.
-* TRAB auto-update: Base decision if we have to strip the image
- header on image type as encoded in the header
- (include image type patch by Martin Krause, 17 Oct 2003)
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Patches by Xianghua Xiao, 15 Oct 2003:
+commit 1eaf3a5ff4960a46f3a9063568ba2af7883f07c5
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Tue Oct 10 00:23:32 2006 -0600
- - Added Motorola CPU 8540/8560 support (cpu/85xx)
- - Added Motorola MPC8540ADS board support (board/mpc8540ads)
- - Added Motorola MPC8560ADS board support (board/mpc8560ads)
+ Fix possible uninitialized variable compiler warning.
-* Fix flash timings on TRAB board
+ When CONFIG_OF_FLAG_TREE is set, the compiler complains that 'len' in
+ do_bootm_linux() may be uninitialized. There is no possibility in the
+ current code that len will get used uninitialized, but this fix follows
+ the existing convention of setting both len and data to zero at the same
+ time.
-* Make sure HUSH is initialized for running auto-update scripts
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
-* Make 5200 reset command _really_ reset the board, without running
- any other code after it
+commit 7376eb87aaa601f728f9b8e5e9cd2711a67f529e
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Oct 11 15:13:01 2006 -0500
-* Fix errors with flash erase when range spans across banks
- that are mapped in reverse order
+ * Fix a bunch of compiler warnings for gcc 4.0
-* Fix flash mapping and display on P3G4 board
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Patch by Kyle Harris, 15 Jul 2003:
- - add support for Intel IXP425 CPU
- - add support for IXDP425 eval board
+commit bf651baa365e5447246aad6a633ccd667cf24a39
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed Oct 11 10:10:43 2006 -0500
-* Added config option CONFIG_SILENT_CONSOLE. See doc/README.silent
- for more information
+ Move "ar" flags to config.mk to allow for silent "make -s"
-* Patch by Steven Scholz, 10 Oct 2003
- - Add support for Altera FPGA ACEX1K
+commit 1fd5699a4a24f5c1dab1b32f480bace1ebb9fc3e
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:19:03 2006 -0500
-* Patches by Thomas Lange, 09 Oct 2003:
- - fix cmd_ide.c for non ppc boards (read/write functions did not
- add ATA base address)
- - fix for shannon board
- - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code
- - Endian swap ATA identity for all big endian CPUs, not just PPC
- - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
- args to linux
- - add support for dbau1x00 board (MIPS32)
+ Coding style changes to remove local varible blocks
+ and reformat a bit nicer.
-* Patch by Sangmoon Kim, 07 Oct 2003:
- add support for debris board
+commit 8b283dbb3a08d1b8d406bc15f119e081b3e2606a
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:16:04 2006 -0500
-* Patch by Martin Krause, 09 Oct 2003:
- Fixes for TRAB board
- - /board/trab/rs485.c: correct baudrate
- - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
- udelay(); fix some timing problems with adc controller
- - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power;
- modify commands: touch and buzzer
+ Fix whitespace issues.
-* Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE
- (quick & dirty workaround for rogue pointer problem in get_vfatname());
- Use direct function calls for auto_update instead of hush commands
+commit 7b382b7125f2397cce63253df62f183e3dfa2770
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:14:45 2006 -0500
-* Patch by Scott McNutt, 04 Oct 2003:
- - add support for Altera Nios-32 CPU
- - add support for Nios Cyclone Development Kit (DK-1C20)
+ Fix whitespace issues.
-* Patch by Steven Scholz, 29 Sep 2003:
- - A second parameter for bootm overwrites the load address for
- "Standalone Application" images.
- - bootm sets environment variable "filesize" to the resulting
- (uncompressed) data length for "Standalone Application" images
- when autostart is set to "no". Now you can do something like
- if bootm $fpgadata $some_free_ram ; then
- fpga load 0 $some_free_ram $filesize
- fi
+commit e10390ddd736b0dad1528eec4b0fe35c0827139a
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:06:53 2006 -0500
-* Patch by Denis Peter, 25 Sept 2003:
- add support for the MIP405 Rev. C board
+ Fix whitespace issues.
-* Patch by Yuli Barcohen, 25 Sep 2003:
- add support for Zephyr Engineering ZPC.1900 board
+commit 89875e96ba3f023157bf50d5f8e33bf254964a76
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:03:43 2006 -0500
-* Patch by Anders Larsen, 23 Sep 2003:
- add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only
- implemented for the x86 architecture)
+ Ran lindent and cleaned up whitespace issues.
+ Format for 80-columns too.
-* Patch by Sangmoon Kim, 23 Sep 2003:
- fix pll_pci_to_mem_multiplier table for MPC8245
+commit 333961ae7095fc66d8a041fce1ac9ee873b09d86
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Oct 10 17:02:22 2006 -0500
-* Patch by Anders Larsen, 22 Sep 2003:
- enable timed autoboot on PXA
+ Fix whitespace and 80-col issues.
-* Patch by David Müller, 22 Sep 2003:
- - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver
- returns correct libgcc file path
- - "latency" reduction of busy-loop waiting to improve "U-Boot" boot
- time on s3c24x0 systems
+commit f55df18187e7a45cb73fec4370d12135e6691ae1
+Author: John Traill <john.traill@freescale.com>
+Date: Fri Sep 29 08:23:12 2006 +0100
-* Patch by Jon Diekema, 19 Sep 2003:
- - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet
- link state to the fault LED.
- - In NetLoop, make the Fault LED reflect the link status. The link
- status gets updated on entry, and on timeouts.
+ Fix missing tCycle/modfreq calculation.
-* Patch by Anders Larsen, 18 Sep 2003:
- allow mkimage to build and run on Cygwin-hosted systems
+ Signed-off-by: John Traill <john.traill@freescale.com>
-* Patch by Frank Müller, 18 Sep 2003:
- use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in
- cpu/mpc8xx/fec.c
+commit 8272dc2f58f2473d8995fcc9b916440cfba080f0
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Sep 13 10:33:35 2006 -0500
-* Patch by Pantelis Antoniou, 16 Sep 2003:
- add tool to compute fileds in the PLPRCR register for MPC86x
+ Updated config headers to add default FDT-based booting
-* Use IH_TYPE_FILESYSTEM for TRAB "disk" images.
+commit 09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Sep 13 10:34:18 2006 -0500
-* Fix build problems under FreeBSD
+ Add support for eTSEC 3 & 4 on 8548 CDS
-* Add generic filesystem image type
+ * Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS.
+ This will only work on rev 1.3 boards (but doesn't break older boards)
+ * Cleaned up some comments to reflect the expanded role of tsec
+ in other systems
-* Make fatload set filesize environment variable
+commit 084d648b109c8984f83674043c1a7fa3885ef801
+Author: Andy Fleming <afleming@freescale.com>
+Date: Wed Sep 13 10:33:56 2006 -0500
-* enable basic / medium / high-end configurations for PPChameleonEVB
- board; fix NAND code
+ Added code to support 2.6.18 PCI changes in u-boot
-* enable TFTP client code to specify to the server the desired
- timeout value (see RFC-2349)
+ * Added code to swizzle the IRQ map for the PCI
-* Improve SDRAM setup for TRAB board
+commit afbdc649f8751e4f4f1a6f527edfe139773f2c15
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Sep 19 09:34:10 2006 -0500
-* Suppress all output with splashscreen configured only if "splashimage"
- is set
+ Modified makefile for new build mechanism.
-* Fix problems with I2C support for mpc5200
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Adapt TRAB configuration and auto_update to new memory layout
+commit d14ba6a798beb753e7a864500414fcc2d198b8bc
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Sep 14 08:40:36 2006 -0500
-* Add configuration for wtk board
+ Handle 86xx SVR values according to the new Reference Manual.
+ Both 8641 and 8641D have SVR == 0x8090, and are distinguished
+ by the byte in bits 16-23 instead.
+ Thanks to Jason Jin for noticing.
-* Add support for the Sharp LQ065T9DR51U LCD display
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Patch by Rune Torgersen, 17 Sep 2003:
- - Fixes for MPC8266 default config
- - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
+commit 88c8f4921fc47fb0eb2384b16586f1bd7f275be7
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Mon Aug 28 14:25:31 2006 +0800
-* Patches by Jon Diekema, 17 Sep 2003:
- - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and
- env_common.c)
- - sbc8260 tweaks
- - adjust "help" output
+ Fixed an OF-tree off-by-one bug when adding a new property name.
+ This bug will cause the kernel booting to pause a long time.
-* Patches by Anders Larsen, 17 Sep 2003:
- - fix spelling errors
- - set GD_FLG_DEVINIT flag only after device function pointers
- are valid
- - Allow CFG_ALT_MEMTEST on systems where address zero isn't
- writeable
- - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs
- - trigger watchdog while waiting in serial driver
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
+ (cherry picked from 2f15776ccc6dc32377d8ba9652b8f58059c27c6d commit)
-* Add auto-update code for TRAB board using USB memory sticks,
- support new configuration with more memory
+commit 9bff7a69a885adebbd2bd45990494ec4cf998a30
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 29 11:05:09 2006 -0500
-* disable MPC5200 bus pipelining as workaround for bus contention
+ Remove trailing empty lines.
-* Modify XLB arbiter priorities on MPC5200 so all devices use same
- priority; configure critical interrupts to be handled like external
- interrupts
+commit cd6d73d5b895a5935ac4fde0a356288142a584e0
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 29 09:48:49 2006 -0500
-* Make IPB clock on MGT5100/MPC5200 configurable in board config file;
- go back to 66 MHz for stability
+ Remove bogus msync and use volatile asm.
-* Patches by Jon Diekema, 15 Sep 2003:
- - add description for missing CFG_CMD_* entries in the README file
- - sacsng tweaks
+commit 778d45049ce5927b65b3ff1d8e6692b654bdd49e
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 29 08:17:14 2006 -0500
-* Patch by Gleb Natapov, 14 Sep 2003:
- enable watchdog support for all MPC824x boards that have a watchdog
+ Add myself as maintainer for MPC8641HPCN.
-* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
- "Non-octet Aligned Frame" errors we see at 100 Mbps
+commit 2f15776ccc6dc32377d8ba9652b8f58059c27c6d
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Mon Aug 28 14:25:31 2006 +0800
-* Patch by Sharad Gupta, 14 Sep 2003:
- fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
+ Fixed an OF-tree off-by-one bug when adding a new property name.
+ This bug will cause the kernel booting to pause a long time.
-* Patch by llandre, 11 Sep 2003:
- update configuration for PPChameleonEVB board
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
-* Patch by David Müller, 13 Sep 2003:
- various changes to VCMA9 board specific files
+commit 5567806b67d0ae83493aa8823ad3b6c914f581d7
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Fri Aug 25 14:38:34 2006 -0400
-* Add I2C support for MGT5100 / MPC5200
+ Change ramdiskaddr and dtbaddr
+ Remove PEX fluff commands.
-* Patch by Rune Torgersen, 11 Sep 2003:
- Changed default memory option on MPC8266ADS to NOT be Page Based
- Interleave, since this doesn't work very well with the standard
- 16MB DIMM
+ Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Patch by George G. Davis, 12 Sep 2003:
- fix Makefile settings for sk98 driver
+commit b2b78421d9db49c21a821af8a19c21c1f7dfb29e
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Aug 23 13:32:45 2006 -0500
-* Patch by Stefan Roese, 12 Sep 2003:
- - new boards added: DP405, HUB405, PLU405, VOH405
- - some esd boards updated
- - cpu/ppc4xx/sdram.c: disable memory controller before setting
- first values
- - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems
+ * Another small fix for booting with disable_of
-* Patch by Martin Krause, 11 Sep 2003:
- add burn-in tests for TRAB board
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Enable instruction cache on MPC5200 board
+commit 4a7cc0f21918e6ecf07ed57075d67df2c4a1299c
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed Aug 23 11:04:43 2006 -0500
-* Patch by Denis Peter, 11 Sep 2003:
- - fix USB data pointer assignment for bulk only transfer.
- - prevent to display erased directories in FAT filesystem.
+ Cleanup and lindent new AHCI driver.
-* Change output format for NAND flash - make it look like for other
- memory, too
+commit dabf9ef8c10b4dead5ef2106ef742b1c06b542de
+Author: Jin Zhengxiong <jason@bus.ap.freescale.net>
+Date: Wed Aug 23 19:15:12 2006 +0800
-======================================================================
-Changes for U-Boot 0.4.8:
-======================================================================
+ Add AHCI define and sata support for MPC8641HPCN board.
-* Add I2C and RTC support for RMU board
+ Signed-off-by:Jason Jin<jason.jin@freescale.com>
-* Patches by Denis Peter, 9 Sep 2003:
- add FAT support for IDE, SCSI and USB
+commit 4782ac80b02f0d01afd309e2200dd3c7037f2ba4
+Author: Jin Zhengxiong <jason@bus.ap.freescale.net>
+Date: Wed Aug 23 19:10:44 2006 +0800
-* Patches by Gleb Natapov, 2 Sep 2003:
- - cleanup of POST code for unsupported architectures
- - MPC824x locks way0 of data cache for use as initial RAM;
- this patch unlocks it after relocation to RAM and invalidates
- the locked entries.
+ Add AHCI support to u-boot
-* Patch by Gleb Natapov, 30 Aug 2003:
- new I2C driver for mpc107 bridge. Now works from flash.
+ Add AHCI support in u-boot, enable the sata disk controllers which
+ following the AHCI protocol.
-* Patch by Dave Ellis, 11 Aug 2003:
- - JFFS2: fix typo in common/cmd_jffs2.c
- - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
- - JFFS2: remove node version 0 warning
- - JFFS2: accept JFFS2 PADDING nodes
- - SXNI855T: add AM29LV800 support
- - SXNI855T: move environment from EEPROM to flash
- - SXNI855T: boot from JFFS2 in NOR or NAND flash
+ Signed-off-by:Jason Jin<jason.jin@freescale.com>
-* Patch by Bill Hargen, 11 Aug 2003:
- fixes for I2C on MPC8240
- - fix i2c_write routine
- - fix iprobe command
- - eliminates use of global variables, plus dead code, cleanup.
+commit d8ea2acf5f137cae99417df4f573d036ee384668
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Wed Aug 23 17:54:32 2006 +0800
-* Add support for USB Mass Storage Devices (BBB)
- (tested with USB memory sticks only)
+ Add dtb boot-up parameter to default boot commands.
-* Avoid flicker on TRAB's VFD
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
-* Add support for SK98xx driver
+commit b93775c2036b99baa390ea425c4771895bbc63c4
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 18:26:08 2006 -0500
-* Add PCI support for SL8245 board
+ Cleanup even more poorly introduced whitespace.
-* Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB)
- or 1 x AM29LV652 (two LV065 in one chip = 16 MB);
- Run IPB at 133 Mhz; adjust the MII clock frequency accordingly
+commit ae6241685cbcf0c79a3636530d2ceab1fb291a94
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 18:07:00 2006 -0500
-* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz)
- to allow for more accurate baudrate settings
- (error now 0.7% at 115 kbps, instead of 3.5% before)
+ Cleanup more poorly introduced whitespace.
-* Patch by Andreas Mohr, 4 Sep 2003:
- Fix a lot of spelling errors
+commit 2c33e8a1c535b3ae91cf0b284480600bf3f57c57
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 17:54:05 2006 -0500
-* Add support for PPChameleon Eval Board
+ Cleanup poorly introduced whitespace.
-* Add support for P3G4 board
+commit 80e955c7dd98f4b4fd23c2113caf75ed2b77b5b3
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 12:25:27 2006 -0500
-* Fix problem with MGT5100 FEC driver: add "early" MAC address
- initialization
+ General indent and whitespace cleanups.
-* Patch by Yuli Barcohen, 7 Aug 2003:
- check BCSR to detect if the board is configured in PCI mode
+commit ffff3ae56f5842ca3679e4ce7922b819a87aad9f
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 12:06:18 2006 -0500
-======================================================================
-Changes for U-Boot 0.4.7:
-======================================================================
+ General indent and whitespace cleanups.
-* Patch by Raghu Krishnaprasad, 7 Aug 2003:
- add support for Adder II MPC852T module
+commit 41a0e8b304d3ff55fe27a230507aac79684016ac
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue Aug 22 10:42:21 2006 -0500
-* Patch by George G. Davis, 19 Aug 2003:
- fix TI Innovator/OMAP1510 pin configs
+ Cleanup compiler warnings.
-* Patches by Kshitij, 18 Aug 2003
- - add support for arm926ejs cpu core
- - add support for TI OMAP 1610 Innovator Board
+commit 5de62c47a8628b3da4d73f7c07027f32a3342d40
+Author: Matthew McClintock <msm@freescale.com>
+Date: Tue Aug 22 09:31:59 2006 -0500
-* Patch by Yuli Barcohen, 14 Aug 2003:
- add support for bzip2 uncompression
+ Fix disable_of booting
-* Add GCC library to examples/Makefile so GCC utility functions will
- be resolved, too
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Add I2C and RTC support for RMU board using software I2C driver
- (because of better response to iprobe command); fix problem with
- "reset" command
+commit 87a449c8ac396420cb24260f717ea9e6faa82047
+Author: Matthew McClintock <msm@freescale.com>
+Date: Tue Aug 22 09:23:55 2006 -0500
-* Patch by Matthias Fuchs, 28 Aug 2003:
- Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to
- CONFIG_BOOTP_MAKS (see README).
+ Support for FDT in uImage format, error when using FDT from flash
-* Fix ICU862 environment problem
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Fix RAM size detection for RMU board
+commit 75c299c38369d01addd5e054b8a16217b70f4a86
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Tue Aug 15 15:12:55 2006 -0400
-* Implement "reset" for MGT5100/MPC5200 systems
+ Unlock cache before kernel starts up for MPC86xx
-======================================================================
-Changes for U-Boot 0.4.6:
-======================================================================
+commit 67256678f00c09b0a7f19e862e5c1847553d31bc
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Tue Aug 15 15:13:15 2006 -0400
-* Make Ethernet autonegotiation on INCA-IP work for all clock rates;
- allow selection of clock frequency as "make" target
+ Copy Global Data Pointer to r29 for DECLARE_GLOBAL_DATA_PTR
-* Implement memory autosizing code for IceCube boards
+commit 1c8f6d8fb028f156094d05f2d14298e6479364ac
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Tue Aug 15 15:12:55 2006 -0400
-* Configure network port on INCA-IP for autonegotiation
+ Unlock cache before kernel starts up for MPC86xx
-* Fix overflow problem in network timeout code
+commit 0d9ccc55edf9a7f3c5b2b6263580a6ea8d702a04
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Tue Aug 15 15:13:15 2006 -0400
-* Patch by Richard Woodruff, 8 Aug 2003:
- Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
+ Copy Global Data Pointer to r29 for DECLARE_GLOBAL_DATA_PTR
-======================================================================
-Changes for U-Boot 0.4.5:
-======================================================================
+commit 86c8e17f25e972a7e272950a0735fad84e082b88
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Aug 16 13:59:47 2006 -0500
-* Update for TQM board defaults:
- disable clocks_in_mhz, enable boot count limit
+ * Fix disable_of booting
-* Removed tools/gdb from "make all" target. Added make target "gdbtools"
- in toplevel directory instead. Removed astest.c from tools/gdb because
- it is no longer relevant.
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Fix PCI support for MPC5200 / IceCube Board
+commit 25c751e9adc86e22fe3b5b47cf2806379b575db7
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Aug 16 10:54:09 2006 -0500
-* Map ISP1362 USB OTG controller for NSCU board
+ * Support for FDT in uImage format, error when using FDT from flash
-* Patch by Brad Parker, 02 Aug 2003:
- fix sc520_cdp problems
+ Signed-off-by: Matthew McClintock <msm@freescale.com>
-* Implement Boot Cycle Detection (Req. 2.3 of OSDL CGL Reqirements)
+commit fecf1c7e4de1b2779edc18742b91c22bdc32b68b
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Mon Aug 14 15:33:38 2006 -0500
-* Allow erase command to cross flash bank boundaries
+ Fix BAT0 to actually be cacheable, non-guarded as documented.
-* Patch by Scott McNutt, 21 Jul 2003:
- Add support for LynuxWorks Kernel Downloadable Images (KDIs).
- Both LynxOS and BlueCat linux KDIs are supported.
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Patch by Richard Woodruff, 25 Jul 2003:
- use more reliable reset for OMAP/925T
+commit 40bc83559db5745681909fd7382ae509567e116d
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed Aug 9 15:32:16 2006 -0500
-* Patch by Nye Liu, 25 Jul 2003:
- fix typo in mpc8xx.h
+ Removed MPC8641HPCN DTS source file from build.
+ It is no longer linked into U-Boot; its sources are
+ now located in the kernel tree.
-* Patch by Richard Woodruff, 24 Jul 2003:
- Fixes for cmd_nand.c:
- - Fixed null dereferece which could result in incorrect ECC values.
- - Added support for devices with no Ready/Busy signal hooked up.
- - Added OMAP1510 read/write protect handling.
- - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock
- for non-JFFS2.
- - Switched default ECC to be JFFS2.
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Allow crc32 to be used at address 0x000
+commit 34c3c0e01dbf1f8cc2bd08de92f2b89ba84921eb
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:47:03 2006 -0500
-* Provide consistent interface to standalone applications to access
- the 'global_data' structure
- Provide a doc/README.standalone more useful to users/developers.
+ * Switched default PCI speed for 8540 ADS back to 33MHz
-* Make IceCube MGT5100 FEC driver work
+ * Added comments and a printf to warn that PCI-X won't
+ work at 33MHz
+ Patch by Andy Fleming 17-Mar-2006
-* Implement new mechanism to export U-Boot's functions to standalone
- applications: instead of using (PPC-specific) system calls we now
- use a jump table; please see doc/README.standalone for details
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Patch by Dave Westwood, 24 Jul 2003:
- added support for Unity OS (a proprietary OS)
+commit b6c5e1373b6ea0bb37a18e4aeecec00613d1cd39
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:46:35 2006 -0500
-* Patch by Detlev Zundel, 23 Jul 2003:
- add "imls" command to print flash table of contents
+ * Fixed a bug where 8555 PCI code used the old variable and function names Patch by Andy Fleming 17-Mar-2006
-* Fix cold boot detection for log buffer reset
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Return error for invalid length specifiers with "cp.X" etc.
+commit bf1dfffd8c26f8ecdd630a0ae4c834e751e4e452
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:46:13 2006 -0500
-* Fix startup problem on MIPS
+ * Added VIA configuration table
-* Allow for CONFIG_SPLASH_SCREEN even when no explicit
- bitmap support is configured
+ * Added support for PCI2 on CDS
+ Patch by Andy Fleming 17-Mar-2006
-* Patch by Bill Hargen, 18 Jul 2003:
- - fix endinaness problem in cpu/mpc824x/drivers/i2c/i2c1.c
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Patch by Denis Peter, 18 Jul 2003:
- - fix memory configuration for MIP405T
- - fix printout of baudrate for "loadb <loadaddr> <baudrate>"
+commit c88f9fe66b64247e5b6a38410ba315ca25596d16
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:45:41 2006 -0500
-* Cleanup of TQM82xx configurations; use "official" board types
- to make selection easier.
+ * Fixed PCI memory definitions Patch by Andy Fleming 17-Mar-2006
-* Patch by Martin Krause, 17 Jul 2003:
- add delay to get I2C working with "imm" command and s3c24x0_i2c.c
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Patch by Richard Woodruff, 17 July 03:
- - Fixed bug in OMAP1510 baud rate divisor settings.
+commit 97074ed9655309b64231bc2cee69fe85399f8055
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:45:17 2006 -0500
-* Patch by Nye Liu, 16 July 2003:
- MPC860FADS fixes:
- - add MPC86xADS support (uses MPC86xADS.h)
- - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
- o PLPRCR changes
- o BRG changes (EXTAL/XTAL restricted to 10MHz)
- o don't trust gclk() software measurement by default, depend on
- CONFIG_8xx_GCLK_FREQ
- - add DRAM SIMM not installed detection
- - use more "correct" SDRAM initialization sequence
- - allow different SDRAM sizes (8xxADS has 8M)
- - default DER is 0
- - remove unused MAMR defines from FADS860T.h (all done in fads.c)
- - rename MAMR/MBMR defines to be more consistent. Should eventually
- be merged into MxMR to better reflect the PowerQUICC datasheet.
+ * Added support for initializing second PCI bus on 85xx Patch by Andy Fleming 17-Mar-2006
-* Patch by Yuli Barcohen, 16 Jul 2003:
- support new Motorola PQ2FADS-ZU evaluation board which replaced
- MPC8260ADS and MPC8266ADS
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-======================================================================
-Changes for U-Boot 0.4.4:
-======================================================================
+commit f0e6f57f71b3c4fdd13028eb03c3f3e91926dda2
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:44:49 2006 -0500
-* Add support for IceCube board (with MGT5100 and MPC5200 CPUs)
+ * Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006
-* Add support for MGT5100 and MPC5200 processors
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Patch by Lutz Dennig, 15 Jul 2003:
- update for R360MPI board
+commit a4e11558b810ef2cddffdf7b9d86bc1130441960
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:44:23 2006 -0500
-======================================================================
-Changes for U-Boot 0.4.3:
-======================================================================
+ * Made sure the code which disables prefetch for PCI devices sets the size of the prefetch region to 0 Patch by Andy Fleming on 17-Mar-2006
-* Patches by Kshitij, 04 Jul 2003
- - added support for arm925t cpu core
- - added support for TI OMAP 1510 Innovator Board
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Patches by Martin Krause, 14 Jul 2003:
- - add I2C support for s3c2400 systems (trab board)
- - (re-) add "ping" to command table
+commit 0e16387db1d4aacd5bf35cb6d7c1942765c0347b
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:43:36 2006 -0500
-* Fix handling of "slow" POST routines
+ * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch by Jon Loeliger 17-Jan-2006
-* Patches by Yuli Barcohen, 13 Jul 2003:
- - Correct flash and JFFS2 support for MPC8260ADS
- - fix PVR values and clock generation for PowerQUICC II family
- (8270/8275/8280)
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Patch by Bernhard Kuhn, 08 Jul 2003:
- - add support for M68K targets
+commit 855e6fb073f9d04fe4a7f06c107ecbac6344ddd4
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:43:00 2006 -0500
-* Patch by Ken Chou, 3 Jul:
- - Fix PCI config table for A3000
- - Fix iobase for natsemi.c
- (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
+ * Removed the oftree.dts for stxxtx in light of the changes to the flat device tree handling code Patch by Matthew McClintock 26-June-2006
-* Allow to enable "slow" POST routines by key press on power-on
-* Fix temperature dependend switching of LCD backlight on LWMON
-* Tweak output format for LWMON
+commit 5498d90312aad9f6bdbf047986027c35b03cd163
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:42:24 2006 -0500
-* Patch by Stefan Roese, 11 Jul 2003:
- - Fix bug in CONFIG_VERSION_VARIABLE.
- - AR405 config updated.
- - OCRTC/ORSG: bsp command added.
- - ASH405 bsp update.
+ * Patch to modify ft_build.c to update flat device trees in place Patch by Matthew McClintock 26-June-2006
-======================================================================
-Changes for U-Boot 0.4.2:
-======================================================================
+commit 0267768eddc5ca7bc1865bc40c866829ac5efbfe
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:41:37 2006 -0500
-* Add support for NSCU board
+ * Modify bootm command to support booting with flat device trees Patch by Matthew McClintock 26-June-2006
-* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules
+commit 8fc8bd2cc479b6cd188fdede4010e0e052970b8a
+Author: John Traill <john.traill@freescale.com>
+Date: Wed Aug 9 14:33:50 2006 +0100
-* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML
- mirror bit flash on TQM8xxM modules
+ Add Rapidio support for the MPC8641HPCN
-* Patch by Kenneth Johansson, 30 Jun 2003:
- get rid of MK_CMD_ENTRY macro; update doc/README.command
+ Signed-off-by: John Traill <john.traill@freescale.com>
-* Patch by Seb James, 30 Jun 2003:
- Improve documentation of I2C configuration in README
+commit 91a414c7d1fb0eac912592cd995b30c9f23045c9
+Author: John Traill <john.traill@freescale.com>
+Date: Tue Aug 8 11:32:43 2006 +0100
-* Fix problems with previous log buffer "fixes"
+ Fix caslat calculation
-* Fix minor help text issues
+ Signed-off-by: John Traill <john.traill@freescale.com>
-* "log append" did not append a newline
+commit 709d3073e74153278e7904a70819bbef7df50e1a
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Aug 3 16:17:56 2006 -0500
-======================================================================
-Changes for U-Boot 0.4.1:
-======================================================================
-
-* Fix some missing commands, cleanup header files
- (autoscript, bmp, bsp, fat, mmc, nand, portio, ...)
-
-* Rewrite command lookup and help command (fix problems with bubble
- sort when sorting command name list). Minor cleanup here and there.
-
-* Merge from "stable branch", tag LABEL_2003_06_28_1800-stable:
- - Allow to call sysmon function interactively
- - PIC on LWMON board needs delay after power-on
- - Add missing RSR definitions for MPC8xx
- - Improve log buffer handling: guarantee clean reset after power-on
- - Add support for EXBITGEN board (aka "genie")
- - Add support for SL8245 board
-
-* Code cleanup:
- - remove trailing white space, trailing empty lines, C++ comments, etc.
- - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
-
-* Patches by Kenneth Johansson, 25 Jun 2003:
- - major rework of command structure
- (work done mostly by Michal Cendrowski and Joakim Kristiansen)
-
-======================================================================
-Changes for U-Boot 0.4.0:
-======================================================================
-
-* Patches by Robert Schwebel, 26 Jun 2003:
- - csb226 configuration updated
- - credits for logodl port updated
- - innokom configuration updated
- - logodl tree update, still with coding style inconsistencies
- - added OCM for ppc405 warning to README
-
-* Patch by Pantelis Antoniou, 25 Jun 2003:
- update NetVia with V2 board support
-
-* Header file cleanup for ARM
-
-* Patch by Murray Jensen, 24 Jun 2003:
- - make sure to use only U-boot provided header files
- - fix problems with ".rodata.str1.4" section as used by GCC-3.x
-
-* Patch by Stefan Roese, 24 Jun 2003:
- - Update esd ASH405 board files.
- - Update esd DASA_SIM config file.
- - Add ping command to some esd boards.
-
-* Patch by Yuli Barcohen, 23 Jun 2003:
- Update for MPC8260ADS board
-
-* Patch by Murray Jensen, 23 Jun 2003:
- - cleanup of GCC 3.x compiler warnings
-
-* Patch by Rune Torgersen, 4 Jun 2003:
- add large memory support for MPC8266ADS board
-
-* Patch by Richard Woodruff, 19 June 03:
- - Enabled standard u-boot device abstraction for ARM
- - Enabled console device for ARM
- - Initilized bi_baudrate for ARM
-
-* Patch by Bill Hargen, 23 Apr 2003:
- fix byte order for 824x I2C addresses (write op)
-
-* Patch by Murray Jensen, 20 Jun 2003:
- - hymod update
- - cleanup (especially for gcc-3.x compilers)
-
-* Patch by Tom Guilliams, 20 Jun 2003:
- added CONFIG_750FX support for IBM 750FX processors
-
-* Patch by Devin Crumb, 02 Apr 2003:
- Fix clock divider rounding problem in drivers/serial.c
-
-* Patch by Richard Woodruff, 19 June 03:
- - Fixed smc91c111 driver to sync with the u-boot environment
- (driver/smc91c111.c).
- - Added eth_init error return check in NetLoop (net/net.c).
-
-* Patch by Ken Chou, 19 June 2003:
- Added support for A3000 SBC board (Artis Microsystems Inc.)
-
-* Patches by Murray Jensen, 17 Jun 2003:
- - Hymod board database mods: add "who" field and new xilinx chip types
- - provide new "init_cmd_timeout()" function so code external to
- "common/main.c" can use the "reset_cmd_timeout()" function before
- entering the main loop
- - add DTT support for adm1021 (new file dtt/adm1021.c; config
- slightly different. see include/configs/hymod.h for an example
- (requires CONFIG_DTT_ADM1021, CONFIG_DTT_SENSORS, and
- CFG_DTT_ADM1021 defined)
- - add new "eeprom_probe()" function which has similar args and
- behaves in a similar way to "eeprom_read()" etc.
- - add 8260 FCC ethernet loopback code (new "eth_loopback_test()"
- function which is enabled by defining CONFIG_ETHER_LOOPBACK_TEST)
- - gdbtools copyright update
- - ensure that set_msr() executes the "sync" and "isync" instructions
- after the "mtmsr" instruction in cpu/mpc8260/interrupts.c
- - 8260 I/O ports fix: Open Drain should be set last when configuring
- - add SIU IRQ defines for 8260
- - allow LDSCRIPT override and OBJCFLAGS initialization: change to
- config.mk to allow board configurations to override the GNU
- linker script, selected via the LDSCRIPT, make variable, and to
- give an initial value to the OBJCFLAGS make variable
- - 8260 i2c enhancement:
- o correctly extends the timeout depending on the size of all
- queued messages for both transmit and receive
- o will not continue with receive if transmit times out
- o ensures that the error callback is done for all queued tx
- and rx messages
- o correctly detects both tx and rx timeouts, only delivers one to
- the callback, and does not overwrite an earlier error
- o logic in i2c_probe now correct
- - add "vprintf()" function so that "panic()" function can be
- technically correct
- - many Hymod board changes
-
-* Patches by Robert Schwebel, 14 Jun 2003:
- - add support for Logotronic DL datalogger board
- - cleanup serial line after kermit binary download
- - add debugX macro (debug level support)
- - update mach-types.h to latest arm.linux.org.uk master list.
-
-* Patches by David Müller, 12 Jun 2003:
- - rewrite of the S3C24X0 register definitions stuff
- - "driver" for the built-in S3C24X0 RTC
-
-* Patches by Yuli Barcohen, 12 Jun 2003:
- - Add MII support and Ethernet PHY initialization for MPC8260ADS board
- - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
- configuration word supplied by FPGA on some MPC8260ADS boards
-
-* Patch by Pantelis Antoniou, 10 Jun 2003:
- Unify status LED interface
-
-* Add support for DS12887 RTC; add RTC support for ATC board
-
-* Patch by Nicolas Lacressonniere, 11 Jun 2003:
- Modifications for Atmel AT91RM9200DK ARM920T based development kit
- - Add Atmel DataFlash support for reading and writing.
- - Add possibility to boot a Linux from DataFlash with BOOTM command.
- - Add Flash detection on Atmel AT91RM9200DK
- (between Atmel AT49BV1614 and AT49BV1614A flashes)
- - Replace old Ethernet PHY layer functions
- - Change link address
-
-* Patch by Frank Smith, 9 Jun 2003:
- use CRIT_EXCEPTION for machine check on 4xx
-
-* Patch by Detlev Zundel, 13 Jun 2003:
- added implementation of the "carinfo" command in cmd_immap.c
-
-* Fix CONFIG_NET_MULTI support in include/net.h
-
-* Patches by Kyle Harris, 13 Mar 2003:
- - Add FAT partition support
- - Add command support for FAT
- - Add command support for MMC
- ----
- - Add Intel PXA support for video
- - Add Intel PXA support for MMC
- ----
- - Enable MMC and FAT for lubbock board
- - Other misc changes for lubbock board
-
-* Patch by Robert Schwebel, April 02, 2003:
- fix for SMSC91111 driver
-
-* Patch by Vladimir Gurevich, 04 Jun 2003:
- make ppc405 ethernet driver compatible with CONFIG_NET_MULTI option
-
-* Patch by Stefan Roese, 05 Jun 2003:
- - PPC4xx: Fix bug for initial stack in data cache as pointed out by
- Thomas Schaefer (tschaefer@giga-stream.de). Now inital stack in
- data cache can be used even if the chip select is in use.
- - CFG_RX_ETH_BUFFER added to set the ethernet receive buffer count
- (see README for further description).
- - Changed config files of CONFIG_EEPRO100 boards to use the
- CFG_RX_ETH_BUFFER define.
-
-* Add support for RMU board
-
-* Add support for TQM862L at 100/50 MHz
-
-* Patch by Pantelis Antoniou, 02 Jun 2003:
- major reconstruction of networking code;
- add "ping" support (outgoing only!)
-
-* Patch by Denis Peter, 04 June 2003:
- add support for the MIP405T board
-
-* Patches by Udi Finkelstein, 2 June 2003:
- - Added support for custom keyboards, initialized by defining a
- board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
- - Added support for the RBC823 board.
- - cpu/mpc8xx/lcd.c now automatically calculates the
- Horizontal Pixel Count field.
-
-* Fix alignment problem in BOOTP (dhcp_leasetime option)
- [pointed out by Nicolas Lacressonnière, 2 Jun 2003]
-
-* Patch by Mark Rakes, 14 May 2003:
- add support for Intel e1000 gig cards.
-
-* Patch by Nye Liu, 3 Jun 2003:
- fix critical typo in MAMR definition (include/mpc8xx.h)
-
-* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.
-
-* Patch by Klaus Heydeck, 2 Jun 2003
- Minor changes for KUP4K configuration
+ Convert to mac-address in ethernet nodes.
-* Patch by Marc Singer, 29 May 2003:
- Fixed rarp boot method for IA32 and other little-endian CPUs.
+commit 71748af833ca1017edf1415be376366ff2937d17
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Fri Jul 28 12:41:35 2006 -0400
-* Patch by Marc Singer, 28 May 2003:
- Added port I/O commands.
+ Correct the irq value of DUART2
-* Patch by Matthew McClintock, 28 May 2003
- - cpu/mpc824x/start.S: fix relocation code when booting from RAM
- - minor patches for utx8245
+commit 9cb3e8816ae4d854e7dc22128c3eea3d70bb982c
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Fri Jul 28 12:41:41 2006 -0400
-* Patch by Daniel Engström, 28 May 2003:
- x86 update
+ Change the space size of PEX IO in README
-* Patch by Dave Ellis, 9 May 2003 + 27 May 2003:
- add nand flash support to SXNI855T configuration
- fix/extend nand flash support:
- - fix 'nand erase' command so does not erase bad blocks
- - fix 'nand write' command so does not write to bad blocks
- - fix nand_probe() so handles no flash detected properly
- - add doc/README.nand
- - add .jffs2 and .oob options to nand read/write
- - add 'nand bad' command to list bad blocks
- - add 'clean' option to 'nand erase' to write JFFS2 clean markers
- - make NAND read/write faster
+commit 239db37c94f7a92941c4465feceb867c609241c5
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Fri Jul 28 12:41:18 2006 -0400
-* Patch by Rune Torgersen, 23 May 2003:
- Update for MPC8266ADS board
+ Move get_board_sys_clk to board directory
-* Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length
- instead CFG_MONITOR_LEN is now only used to determine _at_compile_
- _time_ (!) if the environment is embedded within the U-Boot image,
- or in a separate flash sector.
+commit 492900b985439fbce1a118afde1e35def870db03
+Author: John Traill <john.traill@freescale.com>
+Date: Fri Jul 28 09:03:54 2006 +0100
-* Cleanup CFG_DER #defines in config files (wd maintained only)
+ Fix 8641HPCN pollution
-* Fix data abort exception handling for arm920t CPU
+commit 515ab8a62e8574e2babc6e8dcc43544ad221c5b2
+Author: John Traill <john.traill@freescale.com>
+Date: Fri Jul 28 08:16:06 2006 +0100
-* Fix alignment problems with flash driver for TRAB board
+ Fix 8641HPCN timebase
-* Patch by Donald White, 21 May 2003:
- fix calculation of base address in pci_hose_config_device()
+commit c86360b830f1eecd7a72208575dde4f57879faea
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Fri Jul 28 00:01:34 2006 +0800
-* Fix bug in command line parsing: "cmd1;cmd2" is supposed to always
- execute "cmd2", even if "cmd1" fails. Note that this is different
- to "run var1 var2" where the contents of "var2" will NOT be
- executed when a command in "var1" fails.
+ Fixed OF device tree of mpc86xxhpcn board.
-* Add zero-copy ramdisk support (requires corresponding kernel support!)
+ The changes works in with kernel irq mapping rework.
-* Patch by Kyle Harris, 20 May 2003:
- In preparation for an ixp port, rename cpu/xscale and arch-xscale
- into cpu/pxa and arch-pxa.
+ Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
-* Patch by Stefan Roese, 23 May 2003:
- - IBM PPC405EP port added.
- - CONFIG_UART1_CONSOLE added. If defined internal UART1 (and not
- UART0) is used as default U-Boot console. PPC4xx only!
- - esd ASH405 board added (PPC405EP based).
- - BUBINGA405EP board added (PPC405EP based - IBM Eval Board).
- - esd CPCI405AB board added.
- - esd PMC405 board added.
- - Update of some esd boards.
+commit bea3f28d285942bf3f7ab339ce85178ded544225
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Wed Jul 12 10:48:05 2006 -0400
-* Patch by Denis Peter, 19 Mai 2003:
- add support for the MIP405-3 board
+ Add support for reading and writing mac addresses to or from ID EEPROM.
-* Patch by Dave Ellis, 22 May 2003:
- Fix problem with only partially cleared .bss segment
+ Added code for reading and writing Mac addresses to/from ID EEPROM(0x57).
+ With attached patch, we can use command "mac/mac read/mac save/"
+ to read and write EEPROM under u-boot prompt.
-* Patch by Rune Torgersen, 12 May 2003:
- get PCI to work on a MPC8266ADS board; incorporate change to
- cpu/mpc8260/pci.c to enable overrides of PCI memory parameters
+ U-boot will calculate the checksum of EEPROM while bootup,
+ if it is right, then u-boot will check whether the mac address
+ of eTSEC0/1/2/3 is availalbe (non-zero).
-* Patch by Nye Liu, 1 May 2003:
- minor patches for the FADS8xx
+ If there is mac address availabe in EEPROM, u-boot will use it,
+ otherewise, u-boot will use the mac address defined in
+ MPC8641HPCN.h. This matches the requirement to set unique mac address
+ for each TSEC port.
-* Patch by Thomas Schäfer, 28 Apr 2003:
- Fix SPD handling for 256 ECC DIMM on Walnut
+ Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
+ Signed-off-by: York Sun <yorksun@freescale.com>
-* Add support for arbitrary bitmaps for TRAB's VFD command;
- allow to pass boot bitmap addresses in environment variables;
- allow for zero boot delay
+commit fcb28e763415e0e4e66b0f45842d1557ae198e5e
+Author: Jin Zhengxiong <Jason.Jin@freescale.com>
+Date: Thu Jul 13 10:35:10 2006 -0500
-* Patch by Christian Geißinger, 19 May 2002:
- On TRAB: wait until the dummy byte has been completely sent
+ Fixed initrd issue by define big RAM
-* Patch by David Updegraff, 22 Apr 2003:
- update for CrayL1 board
+ Signed-off-by:Jason Jin <Jason.jin@freescale.com>
-* Patch by Pantelis Antoniou, 21 Apr 2003:
- add boot support for ARTOS (a proprietary OS)
+commit e6cd2a1785d74ec3d30a86f1cb360be8de478151
+Author: Jason Jin <Jason.jin@freescale.com>
+Date: Fri Jul 7 10:01:45 2006 -0500
-* Patch by Steven Scholz, 11 Apr 2003:
- Add support for RTC DS1338
+ We made a u-boot patch to fix the hang up issue
+ when booting filesystem from ramdisk.
-* Patch by Rod Boyce, 24 Jan 2003:
- Fix counting of extended partitions in diskboot command
+ Signed-off-by:Jason Jin <Jason.jin@freescale.com>
-* Patch by Christophe Lindheimer, 20 May 2003:
- allow the use of CFG_LOADS when CFG_NO_FLASH is set
+commit 38433ccc5850ee70549af0b2bc5b920355ef5388
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:47:03 2006 -0500
-* Fix SDRAM timing on Purple board
+ * Switched default PCI speed for 8540 ADS back to 33MHz
+ * Added comments and a printf to warn that PCI-X won't
+ work at 33MHz
+ Patch by Andy Fleming 17-Mar-2006
-* Add support for CompactFlash on ATC board
- (includes support for Intel 82365 and compatible PC Card controllers,
- and Yenta-compatible PCI-to-CardBus controllers)
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Patch by Mathijs Haarman, 08 May 2003:
- Add lan91c96 driver (tested on Lubbock and custom PXA250 board only)
+commit e4c2a0eb0c3e3ffbf824800184ee42bdc99d5b19
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:46:35 2006 -0500
-* Fix problem with usage of "true" (undefined in current versions of bfd.h)
+ * Fixed a bug where 8555 PCI code used the old variable and
+ function names
+ Patch by Andy Fleming 17-Mar-2006
-* Add support for Promess ATC board
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Patch by Keith Outwater, 28 Apr 2003:
- - Miscellaneous corrections and additions to GEN860T board specific code.
- - Added GEN860_SC variant to GEN860T.
- - Miscellaneous corrections to GEN860T documentation.
- - Correct duplicate entry in U-Boot CREDITS file.
- - Add GEN860T_SC entry in MAINTAINERS file.
- - Update CREDITS file with GEN860T_SC info.
+commit cbfc7ce756b88eb26e5537bc7b625c445c6dcfac
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:46:13 2006 -0500
-* Update Smiths Aerospace addresses in MAINTAINERS file
+ * Added VIA configuration table
+ * Added support for PCI2 on CDS
+ Patch by Andy Fleming 17-Mar-2006
-* Fix error handling in hush's version of "run" command
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* LWMON extensions:
- - Splashscreen support
- - modem support
- - sysmon support
- - temperature dependend enabling of LCD
+commit 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:45:41 2006 -0500
-* Allow booting from old "PPCBoot" disk partitions
+ * Fixed PCI memory definitions
+ Patch by Andy Fleming 17-Mar-2006
-* Add support for TQM8255 Board / MPC8255 CPU
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-======================================================================
-Changes for U-Boot 0.3.1:
-======================================================================
+commit 087454609e47295443af793a282cddcd91a5f49c
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:45:17 2006 -0500
-* Make sure Block Lock Bits get cleared in R360MPI flash driver
+ * Added support for initializing second PCI bus on 85xx
+ Patch by Andy Fleming 17-Mar-2006
-* MPC823 LCD driver: Fill color map backwards, to allow for steady
- display when Linux takes over
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Patch by Erwin Rol, 27 Feb 2003:
- Add support for RTEMS (this time for real).
+commit b636aaeb6fd516a442fb611bbeeddf3077a687fb
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:44:49 2006 -0500
-* Add support for "bmp info" and "bmp display" commands to load
- bitmap images; this can be used (for example in a "preboot"
- command) to display a splash screen very quickly after poweron.
+ * Added PCI-X #defines for PCI-X initialization
+ Patch by Andy Fleming on 17-Mar-2006
-* Add support for 133 MHz clock on INCA-IP board
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Patch by Lutz Dennig, 10 Apr 2003:
- Update for R360MPI board
+commit 20abbc6fffa115690107cc942c7abf84bdc03a1b
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:44:23 2006 -0500
-* Add new meaning to "autostart" environment variable:
- If set to "no", a standalone image passed to the
- "bootm" command will be copied to the load address
- (and eventually uncompressed), but NOT be started.
- This can be used to load and uncompress arbitrary
- data.
+ * Made sure the code which disables prefetch for PCI devices
+ sets the size of the prefetch region to 0
+ Patch by Andy Fleming on 17-Mar-2006
-* Patch by Stefan Roese, 10 Apr 2003:
- Changed DHCP client to use IP address from server option field #54
- from the OFFER packet in the server option field #54 in the REQUEST
- packet. This fixes a problem using a Windows 2000 DHCP server,
- where the DHCP-server is not the TFTP-server.
+ Signed-off-by: Andy Fleming <afleming@freescale.com>
-* Set max brightness for MN11236 displays on TRAB board
+commit 40d5fa35d02df22580593bf0039ab173367e8ef0
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:43:36 2006 -0500
-* Add support for TQM862L modules
+ * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards
+ Patch by Jon Loeliger 17-Jan-2006
-======================================================================
-Changes for U-Boot 0.3.0:
-======================================================================
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Patch by Arun Dharankar, 4 Apr 2003:
- Add IDMA example code (tested on 8260 only)
+commit be7e8b0cb5a0c49dc180075b96df296a893bf146
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:43:00 2006 -0500
-* Add support for Purple Board (MIPS64 5Kc)
+ * Removed the oftree.dts for stxxtx in light of the changes
+ to the flat device tree handling code
+ Patch by Matthew McClintock 26-June-2006
-* Add support for MIPS64 5Kc CPUs
+commit 1b380ec225665e73959677f3893dc658c5925e05
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:42:24 2006 -0500
-* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS
+ * Patch to modify ft_build.c to update flat device trees in place
+ Patch by Matthew McClintock 26-June-2006
-* Patch by Denis Peter, 04 Apr 2003:
- - update MIP405-4 board
+commit 98a9c4d468a942a09ebe8979bec508017f3e4462
+Author: Matthew McClintock <msm@freescale.com>
+Date: Wed Jun 28 10:41:37 2006 -0500
-* Patch by Stefan Roese, 4 Apr 2003:
- - U-Boot version environment variable "ver" added
- (CONFIG_VERSION_VARIABLE).
- - Changed PPC405GPr version from A to B.
- - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.
+ * Modify bootm command to support booting with flat device trees
+ Patch by Matthew McClintock 26-June-2006
-* Patches by Denis Peter, 03 April 2003:
- - fix PCI IRQs on MPL boards
- - fix two more un-relocated pointer problems
+commit da012ab661fd4ab169dd7b9b32201a4df62cf34a
+Author: Jin Zhengxiong <Jason.Jin@freescale.com>
+Date: Wed Jun 28 08:43:56 2006 -0500
-* Fix behaviour of "run" command:
- - print error message iv variable does not exist
- - terminate processing of arguments in case of error
+ Change Id to symbolic name for RTL8139
-* Patches by Peter Figuli, 10 Mar 2003
- - Add support for BTUART on PXA platform
- - Add support for WEP EP250 (PXA) board
+ Signed-off-by: Jason Jin <Jason.jin@freescale.com>
-* Fix flash problems on INCA-IP; add tool to allow bruning images to
- flash using a BDI2000
+commit bc09cf3c2bfb8d54c659cbb332f79d0950982fd0
+Author: Jin Zhengxiong-R64188 <Jason.Jin@freescale.com>
+Date: Tue Jun 27 18:12:10 2006 +0800
-* Implement fix for I2C Edge Conditions problem for all boards that
- use the bit-banging driver (common/soft_i2c.c)
+ Fix RTL8139 in big endian
-* Patch by Martin Winistoerfer, 23 Mar 2003
- - Add port to MPC555/556 microcontrollers
- - Add support for cmi customer board with
- Intel 28F128J3A, 28F320J3A or 28F640J3A flash.
+ signed-off-by: Jason Jin <Jason.Jin@freescale.com>
+ signed-off-by: Wei Zhang <wei.zhang@freescale.com>
-* Patch by Rick Bronson, 28 Mar 2003:
- - fix common/cmd_nand.c
+commit fcfb9a57947fc203b99fe81ab0578f7286261f9f
+Author: Jin Zhengxiong-R64188 <Jason.Jin@freescale.com>
+Date: Tue Jun 27 18:12:23 2006 +0800
-* Patch by Arun Dharankar, 24 Mar 2003:
- - add threads / scheduler example code
+ Fix Tsec bug when no link
-* Add patches by Robert Schwebel, 31 Mar 2003:
- - add ctrl-c support for kermit download
- - align bdinfo output on ARM
- - csb226 board: bring in sync with innokom/memsetup.S
- - csb226 board: fix MDREFR handling
- - misc doc fixes / extensions
- - innokom board: cleanup, MDREFR fix in memsetup.S, config update
- - add BOOT_PROGRESS to armlinux.c
+ When tftp a non-exist file from the tftp server, u-boot will check
+ the link of all eth port. The original file will return wrong link
+ state on the no link ports.
-* Add CPU ID, version, and clock speed for INCA-IP
+ signed-off-by: Jason Jin <Jason.Jin@freescale.com>
-* Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board:
- - fix SRAM and SDRAM memory sizing
- - add status LED support
- - add MAC address for second (SCC1) ethernet port
+commit bd22c2b97514fbfb0e03bd9c72b3445e4dbd57e2
+Author: Jin Zhengxiong-R64188 <Jason.Jin@freescale.com>
+Date: Tue Jun 27 18:12:02 2006 +0800
-* Update default environment for TQM8260 board
-
-* Patch by Rick Bronson, 16 Mar 2003:
- - Add NAND flash support for reading, writing, and erasing NAND
- flash (certain forms of which are called SmartMedia).
- - Add support for Atmel AT91RM9200DK ARM920T based development kit.
-
-* Patches by Robert Schwebel, 19 Mar 2003:
- - use arm-linux-gcc as default compiler for ARM
- - fix i2c fixup code
- - fix missing baudrate setting
- - added $loadaddr / CFG_LOAD_ADDR support to loadb
- - moved "ignoring trailing characters" _before_ u-boot wants to
- print out diagnostics messages; removes bogus characters at the
- end of transmission
-
-* Patch by John Zhan, 18 Mar 2003:
- Add support for SinoVee Microsystems SC8xx boards
-
-* Patch by Rolf Offermanns, 21 Mar 2003:
- ported the dnp1110 related changes from the current armboot cvs to
- current u-boot cvs. smc91111 does not work. problem marked in
- smc91111.c, grep for "FIXME".
-
-* Patch by Brian Auld, 25 Mar 2003:
- Add support for STM flash chips on ebony board
-
-* Add PCI support for MPC8250 Boards (PM825 module)
-
-* Patch by Stefan Roese, 25 Mar 2003:
- - PCI405 update.
-
-* Patch by Stefan Roese, 20 Mar 2003:
- - CPCI4052 update (support for revision 3).
- - Set edge conditioning circuitry on PPC405GPr for compatibility
- to existing PPC405GP designs.
- - Clip udiv to 5 bits on PPC405 (serial.c).
-
-* Extend INCAIP board support:
- - add automatic RAM size detection
- - add "bdinfo" command
- - pass flash address and size to Linux kernel
- - switch to 150 MHz clock
-
-* Avoid flicker on the TRAB's VFD by synchronizing the enable with
- the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100
- boards, version 153 for Rev. 200 boards).
-
-* Patch by Vladimir Gurevich, 12 Mar 2003:
- Fix relocation problem of statically initialized string pointers
- in common/cmd_pci.c
-
-* Patch by Kai-Uwe Blöm, 12 Mar 2003:
- Cleanup & bug fixes for JFFS2 code:
- - the memory mangement was broken. It caused havoc on malloc by
- writing beyond the block boundaries.
- - the length calculation for files was wrong, sometimes resulting
- in short file reads.
- - data copying now optionally takes fragment version numbers into
- account, to avoid copying from older data.
- See doc/README.JFFS2 for details.
-
-* Patch by Josef Wagner, 12 Mar 2003:
- - 16/32 MB and 50/80 MHz support with auto-detection for IP860
- - ETH05 and BEDBUG support for CU824
- - added support for MicroSys CPC45
- - new BOOTROM/FLASH0 and DOC base for PM826
-
-* Patch by Robert Schwebel, 12 Mar 2003:
- Fix the chpart command on innokom board
-
-* Name cleanup:
- mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h
- s/PPCBoot/U-Boot/ in some files
- s/pImage/uImage/ in some files
-
-* Patch by Detlev Zundel, 15 Jan 2003:
- Fix '' command line quoting
-
-* Patch by The LEOX team, 19 Jan 2003:
- - add support for the ELPT860 board
- - add support for Dallas ds164x RTC
-
-* Patches by David Müller, 31 Jan 2003:
- - minimal setup for CardBus bridges
- - add EEPROM read/write support in the CS8900 driver
- - add support for the builtin I2C controller in the Samsung s3c24x0 chips
- - add support for MPL's VCMA9 (Samsung s3c2410 based) board
-
-* Patch by Steven Scholz, 04 Feb 2003:
- add support for RTC DS1307
+ Fix bug for io_bar size during pci scan
-* Patch by Reinhard Meyer, 5 Feb 2003:
- fix PLPRCR/SCCR init sequence on 8xx to allow for
- changes of EBDF by software
-
-* Patch by Vladimir Gurevich, 07 Feb 2003:
- "API-compatibility patch" for 4xx I2C driver
+ During the pci scan process, Some devices return bar_reponse with the
+ highest bytes 0, such as the pci bridge in uli1575 return bar_response
+ with 0xffffff, So the bar_size should be manually set under 64K.
-* TRAB fixes / extensions:
- - Restore VFD brightness as saved in environment
- - add support for Fujitsu flashes
- - make sure both buzzers are turned off (drive low level)
+ Signed-off-by: Jason Jin <jason.jin@freescale.com>
-* Patches by Robert Schwebel, 06 Mar 2003:
- - fix bug in BOOTP code (must use NetCopyIP)
- - update of CSB226 port
- - clear BSS segment on XScale
- - added support for i2c_init_board() function
- - update to the Innokom plattform
+commit fa7db9c377bc2353a17bf1d381d65a6c418728f0
+Author: Jin Zhengxiong-R64188 <Jason.Jin@freescale.com>
+Date: Tue Jun 27 18:11:54 2006 +0800
-* Extend support for redundand environments for configurations where
- environment size < sector size
+ Enable PCIE1 for MPC8641HPCN board
-* Patch by Rune Torgersen, 13 Feb 2003:
- Add support for Motorola MPC8266ADS board
+ Signed-off-by: Jason Jin <Jason.jin@freescale.com>
-* Patch by Kyle Harris, 19 Feb 2003:
- patches for the Intel lubbock board:
- memsetup.S - general cleanup (based on Robert's csb226 code)
- flash.c - overhaul, actually works now
- lubbock.c - fix init funcs to return proper value
+commit 684623ce92c5fd32e7db2d6e016945a67c5ffaba
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Jun 22 08:51:46 2006 -0500
-* Patch by Kenneth Johansson, 26 Feb 2003:
- - Fixed off by one in RFTA calculation.
- - No need to abort when LDF is lower than we can program it's only
- minimum timing so clamp it to what we can do.
- - Takes function pointer to function for reading the spd_nvram. Usefull
- for faking data or hardcode a module without the nvram.
- - fix other user for above change
- - fix some comments.
+ Fix bug in 8641hpcn reset command with no args.
-* Patches by Brian Waite, 26 Feb 2003:
- - fix port for evb64260 board
- - fix PCI for evb64260 board
- - fix PCI scan
+ Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
+ Acked-by: Jon Loeliger <jdl@freescale.com>
-* Patch by Reinhard Meyer, 1 Mar 2003:
- Add support for EMK TOP860 Module
+commit 8be429a5ddbf0ebe2d94174ba58fcfc7a24285dc
+Author: Zhang Wei <wei.zhang@freescale.com>
+Date: Tue Jun 20 17:47:15 2006 +0800
-* Patch by Yuli Barcohen, 02 Mar 2003:
- Add SPD EEPROM support for MPC8260ADS board
+ Reworked IRQ mapping in OF-tree.
-* Patch by Robert Schwebel, 21 Jan 2003:
- - Add support for Innokom board
- - Don't complain if "install" fails
- - README cleanup (remove duplicated lines)
- - Update PXA header files
+commit 0e4c2a17ca34001ed36d259f13cb88ada4611a8c
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Jun 15 21:33:37 2006 -0500
-* Add documentation for existing POST code (doc/README.POST)
+ Do not enable address translation on secondary CPUs.
+ Do not set up BATs on secondary CPUs. Let Linux do the nasty.
-* Patch by Laudney Ren, 15 Jan 2003:
- Fix handling of redundand environment in "tools/envcrc.c"
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Patch by Detlev Zundel, 28 Feb 2003:
- Add bedbug support for 824x systems
+commit 8ecc971618f56029ad99d3516f8b297a6ed58971
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed Jun 7 10:53:55 2006 -0500
-* Add support for 16 MB flash configuration of TRAB board
+ Fix a get_board_sys_clk() use-before-def warning.
-* Patch by Erwin Rol, 27 Feb 2003:
- Add support for RTEMS
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
-* Add image information to README
+commit d9bf4858fca5aa4d651b283270f77da72ebadfd5
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed Jun 7 10:52:49 2006 -0500
-* Patch by Stefan Roese, 18 Feb 2003:
- CPCIISER4 configuration updated.
+ Allow DTC path to be passed in.
-* Patch by Stefan Roese, 17 Feb 2003:
- Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port).
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
-* Patch by Stefan Roese, 13 Feb 2003:
- Add "pcidelay" environment variable (in ms, enabled via
- CONFIG_PCI_BOOTDELAY).
- PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after
- RST# to respond to configuration cycles (33MHz -> 1s).
+commit c83ae9ea6d93abbe751bf8a3396236a084e56f87
+Author: Haiying Wang <haiying.wang@freescale.com>
+Date: Tue Jun 6 16:54:29 2006 -0400
-* Fix dual PCMCIA slot support (when running with just one
- slot populated)
+ Modify the IRQ of DUART2
-* Add VFD type detection to trab board
+commit c934f655f9aeca70a5c5f88b465d9e9d57a8d22e
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed May 31 13:55:35 2006 -0500
-* extend drivers/cs8900.c driver to synchronize ethaddr environment
- variable with value in the EEPROM
+ Review cleanups.
-* Patch by Stefan Roese, 10 Feb 2003:
- Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c)
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Add support for MIPS32 4Kc CPUs
+commit cb5965fb95b77a49f4e6af95248e0c849f4af03e
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed May 31 12:44:44 2006 -0500
-* Add support for INCA-IP Board
+ White space cleanup.
+ Some 80-column cleanups.
+ Convert printf() to puts() where possible.
+ Use #include "spd_sdram.h" as needed.
+ Enhanced reset command usage message a bit.
-======================================================================
-Changes for U-Boot 0.2.2:
-======================================================================
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Add dual ethernet support on PM826
+commit 3d5c5be547445dd3bd2eb7368d80df03ea437970
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed May 31 11:39:34 2006 -0500
-* Add support for LXT971 PHY on PM826
+ Removed unneeded local_bus_init() from 8641HPCN board.
-* Patch by Tord Andersson, 16 Jan 2003:
- Fix flash sector count for TQM8xxL
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Fix I2C EEPROM problem on ICU862 board (would only write the first
- 16 bytes out of each 32 byte block)
+commit 4d3d729c16c392d2982d3266b659d333c927697d
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed May 31 11:24:28 2006 -0500
-======================================================================
-Changes for U-Boot 0.2.1:
-======================================================================
+ Moved mpc8641hpcn_board_reset() out of cpu/ into board/.
-* Add support for V37 board
- (patch by Jón Benediktsson, 11 Dec 2002)
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* Update baudrate in bd_info when it gets changed
+commit b2a941de060350ad15878d8219825f4950e9bb8e
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Wed May 31 10:07:28 2006 -0500
-* Add watchdog trigger points while waiting for serial port
- (so far only 8xx -- needed on LWMON with 100ms watchdog)
+ Remove dead debug code.
-* Improve command line tool to access the U-Boot's environment
- (figuration of the utility, using a config file)
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
-* Add single quote support for (old) command line parser
+commit 126aa70f10ba3d20e0a6f4d32328250513b77770
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue May 30 17:47:00 2006 -0500
-* Switch LWMON board default config from FRAM to EEPROM;
- in POST, EEPROM shows up on 8 addresses
+ Move mpc86xx PIXIS code to board directory
-======================================================================
-Changes for U-Boot 0.2.0:
-======================================================================
+ First cut at moving the PIXIS platform code out of
+ the 86xx cpu directory and into board/mpc8641hpcn
+ where it belongs.
-* Use 1-byte-read instead of -write for iprobe() function
- Add i2c commands to PM826 config
+ Signed-off-by: Jon Loeliger <jdl@freescale.com>
-* extend I2C POST code: check for list on known addresses
+commit 38cee12dcfcc257371c901c7e13e58ecab0a35d8
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Tue May 30 09:10:32 2006 -0500
-* Improve log buffer code; use "loglevel" to decide which messages
- to log on the console, too (like in Linux); get rid of "logstart"
+ Improve "reset" command's interaction with watchdog.
-* Add command line tool to access the U-Boot's environment
- (board-specific for TRAB now, to be fixed later)
+ "reset altbank" will reset another bank WITHOUT watch dog timer enabled
+ "reset altbank wd" will reset another bank WITH watch dog enabled
+ "diswd" will disable watch dog after u-boot boots up successfully
-* Patch by Hans-Joerg Frieden, 06 Dec 2002
- Fix misc problems with AmigaOne support
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
-* Patch by Chris Hallinan, 3 Dec 2002:
- minor cleanup to the MPC8245 EPIC driver
+commit 70205e5a6ddc8528b11db9eb4d3fa0209d9fce2a
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Tue May 30 08:51:19 2006 -0500
-* Patch by Pierre Aubert , 28 Nov 2002
- Add support for external (SIU) interrupts on MPC8xx
+ Fix two SDRAM setup bugs.
-* Patch by Pierre Aubert , 28 Nov 2002
- Fix nested syscalls bug in standalone applications
+ Fix ECC setup bug.
+ Enable 1T/2T based on number of DIMMs present.
-* Patch by David Müller, 27 Nov 2002:
- fix output of "pciinfo" command for CardBus bridge devices.
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
-* Fix bug in TQM8260 board detection - boards got stuck when board ID
- was not readable
+commit d11fec5015334deb2010e36ce00bb118cc5429a5
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Fri May 26 10:24:48 2006 -0500
-* Add LED indication for IDE activity on KUP4K board
+ Add first draft of the MPC8641HPCN doc/README.
-* Fix startup problems with VFD display on TRAB
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
-* Patch by Pierre Aubert, 20 Nov 2002
- Add driver for Epson SED13806 graphic controller.
- Add support for BMP logos in cfb_console driver.
+commit ed45d6c930b5939718a87ee12e25cf9a05978d4a
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Fri May 26 10:13:04 2006 -0500
-* Added support for both PCMCIA slots (at the same time!) on MPC8xx
+ Added pci@8000 block.
+ Updated ethernet interrupt mappings (moved up 48).
+ Cleaned up a few comments.
-* Patch by Rod Boyce, 21 Nov 2002:
- fix PCMCIA on MBX8xx board
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
-* Patch by Pierre Aubert , 21 Nov 2002
- Add CFG_CPM_POST_WORD_ADDR to make the offset of the
- bootmode word in DPRAM configurable
+commit 3033ebb20fd7c372c7bca3c9955a4692bb2240b7
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Fri May 26 10:01:16 2006 -0500
-* Patch by Daniel Engström, 18 Nov 2002:
- Fixes for x86 port (mostly strings issues)
+ Allow args on reset command.
-* Patch by Ken Chou, 18 Nov 2002:
- Fix for natsemi NIC cards (DP83815)
+ Signed-off-by: Jon Loeliger <jdl@jdl.com>
-* Patch by Pierre Aubert, 19 Nov 2002:
- fix a bug for the MII configuration, and some warnings
+commit 14e37081ff3cac7ebe6e93836523429853b6b292
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Fri May 19 13:28:39 2006 -0500
-* Patch by Thomas Frieden, 13 Nov 2002:
- Add code for AmigaOne board
- (preliminary merge to U-Boot, still WIP)
+ Change arbitration to round-robin for SMP linux.
-* Patch by Jon Diekema, 12 Nov 2002:
- - Adding URL for IEEE OUI lookup
- - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED
- being defined.
- - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and
- root-on-nfs macros are designed to switch how the default boot
- method gets defined.
+commit 9a655876e5995be80f49054e2509500e871e4d3a
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Fri May 19 13:26:34 2006 -0500
-* Patch by Daniel Engström, 13 Nov 2002:
- Add support for i386 architecture and AMD SC520 board
+ Enable dual DDR controllers and interleaving.
-* Patch by Pierre Aubert, 12 Nov 2002:
- Add support for DOS filesystem and booting from DOS floppy disk
+commit 586d1d5abd3e525f1e1d9b81e5a61a4da6b2fa3c
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Fri May 19 13:22:44 2006 -0500
-* Patch by Jim Sandoz, 07 Nov 2002:
- Increase number of network RX buffers (PKTBUFSRX in
- "include/net.h") for EEPRO100 based boards (especially SP8240)
- which showed "Receiver is not ready" errors when U-Boot was
- processing the receive buffers slower than the network controller
- was filling them.
+ Update 86xx address map and LAWBARs.
-* Patch by Andreas Oberritter, 09 Nov 2002:
- Change behaviour of NetLoop(): return -1 for errors, filesize
- otherwise; return code 0 is valid an means no file loaded - in this
- case the environment still gets updated!
+commit cccce5d0581bb0ba4602799a4b5112e58d1579cb
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Fri May 19 13:14:15 2006 -0500
-* Patches by Jon Diekema, 9 Nov 2002:
- - improve ADC/DAC clocking on the SACSng board to align
- the failing edges of LRCLK and SCLK
- - sbc8260 configuration tweaks
- - add status LED support for 82xx systems
- - wire sspi/sspo commands into command handler; improved error
- handlering
- - add timestamp support and alternate memory test to the
- SACSng configuration
+ Remove L2 Cache invalidate polling.
-* Patch by Vince Husovsky, 7 Nov 2002:
- Add "-n" to linker options to get rid of "Not enough room for
- program headers" problem
+commit f35ec68fb066cec0e36294bfe07dec2d4e8ad3a8
+Author: Jon Loeliger <jdl@jdl.com>
+Date: Fri May 19 12:33:09 2006 -0500
-* Patch by David Müller, 05 Nov 2002
- Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
- so we can use an already existing name
+ Enable 2nd CPU and I2C.
-* Patch by Pierre Aubert, 05 Nov 2002
- Hardware relatied improvments in FDC boot code
+commit bf690dcb512d34c4fceec0eb1e5c0e88a9db5d54
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Mon May 15 07:26:56 2006 -0500
-* Patch by Holger Schurig, 5 Nov 2002:
- Make the PXA really change it's frequency
+ Update interrupt mapping.
-* Patch by Pierre Aubert, 05 Nov 2002
- Add support for slave serial Spartan 2 FPGAs
+commit 6cfea33477b04b63ed47386ed1629529484c33ba
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed May 10 09:38:06 2006 -0500
-* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet
- drivers
+ Remove unneeded INIT_RAM_LOCK cache twiddling.
+ Correctly tracks r29 as global data pointer now.
-* Add support for log buffer which can be passed to Linux kernel's
- syslog mechanism; used especially for POST results.
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
-* Patch by Klaus Heydeck, 31 Oct 2002:
- Add initial support for kup4k board
+commit d4dd317b58c126a2a7e73f4764ecc1a7c97f876c
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed May 10 09:33:07 2006 -0500
-* Patch by Robert Schwebel, 04 Nov 2002:
- - use watchdog to reset PXA250 systems
- - added progress callbacks to (some of the) ARM code
- - update for Cogent CSB226 board
+ Remove unnecessary flash.c file.
-* Add support for FPS860 board
+commit 18b6c8cd8af6cc7f35180cedc4adb3236cc1a1b8
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Tue May 9 08:23:49 2006 -0500
-* Patch by Guillaume Alexandre,, 04 Nov 2002:
- Improve PCI access on 32-bits Compact PCI bus
+ Get MPC8641HPCN flash images working.
-* Fix mdelay() on TRAB - this was still the debugging version with
- seconds instead of ms.
+ Enable the CFI driver.
+ Remove bogus LAWBAR7 cruft.
+ Use correct TEXT_BASE, Fixup load script.
+ Enable SPD EEPROM during DDR setup.
+ Use generic RFC 1918 IP addresses by default.
-* Patch by Robert Schwebel, 1 Nov 2002:
- XScale related cleanup (affects all ARM boards)
+commit 5c9efb36a6b5431423f52888a0e3b4b515fe7eca
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Apr 27 10:15:16 2006 -0500
-* Cleanup of names and README.
+ Cleanup whitespaces and style issues.
+ Removed //-style comments.
+ Use 80-column lines.
+ Remove trailing whitespace.
+ Remove dead code and debug cruft.
-======================================================================
-Notes for U-Boot 0.1.0:
-======================================================================
+commit a2320a6bf8113a09544c42d160d10ac69d049a03
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Thu Apr 27 08:22:39 2006 -0500
-This is the initial version of "Das U-Boot", the Universal Boot Loader.
+ Revert bad PCI prefetch limit change.
-It is based on version 2.0.0 (the "Halloween Release") of PPCBoot.
-For information about the history of the project please see the
-PPCBoot project page at http://sourceforge.net/projects/ppcboot
+commit debb7354d1ea4f694154818df5e5b523f5c1cc1d
+Author: Jon Loeliger <jdl@freescale.com>
+Date: Wed Apr 26 17:58:56 2006 -0500
-======================================================================
+ Initial support for MPC8641 HPCN board.
--- /dev/null
+======================================================================
+Changes for U-Boot 1.1.5:
+======================================================================
+
+* Cleanup compile warnings. Prepare for release 1.1.5
+
+* Fix compile problem in include/configs/ep82xxm.h
+ (must have never been tested before!)
+
+* MCC200: Fix uninitialized variable problem in LCD driver
+
+* Add board/cpu specific NAND chip select function to 440 NDFC
+ Based on idea and implementation from Jeff Mann
+ Patch by Stefan Roese, 20 Oct 2006
+
+* Make 4xx bootup message shorter on 440EPx/GRx platforms
+ Patch by Stefan Roese, 18 Oct 2006
+
+* Add (preliminary) support for V38B board
+
+* PPC405EP: Add support for board configuration of CPC0_PCI register
+ This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE*
+ Patch by Tolunay Orkun, 07 Apr 2006
+
+* PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely.
+ - Add configuration of Open Drain GPIO Output selection
+ - Add configuration of initial value of GPIO output pins
+ Patch by Tolunay Orkun, 07 Apr 2006
+
+* Fix spelling; minor code cleanup.
+
+* Fix JFFS2 compilation problem
+ Patch by Stefan Roese, 12 Oct 2006
+
+* Cleanup of NAND update patch (remove changelog from cmd_nand.c)
+ Patch by Guido Classen, 10 Oct 2006
+
+* Several improvements to the new NAND subsystem:
+ - JFFS2 related commands implemented in mtd-utils style
+ - Support for bad blocks
+ - Bad block testing commands
+ - NAND lock commands
+ Please take a look at doc/README.nand for more details
+ Patch by Guido Classen, 10 Oct 2006
+
+* Define IH_CPU_AVR32
+ Make it possible to generate AVR32 uImage files with mkimage and
+ make cmd_bootm recognize them.
+ Patch by Haavard Skinnemoen, 22 Sep 2006
+
+* Fix buffer overflow problem in ft_build.c
+ Patch by Fredrik Roubert, 09 Oct 2006
+
+* Make bootp implementation RFC3046 compliant
+ Patch by Joakim Larsson, 27 Jun 2006
+
+* TQM5200: perform POST memory test only on STK52xx carrier board.
+ (and then only if PSC6_3 is read as "1" when booting).
+ Patch by Martin Krause, 21 Jun 2006
+
+* Move "ar" flags to config.mk to allow for silent "make -s"
+ Based on patch by Mike Frysinger, 20 Jun 2006
+
+* Coding style cleanup
+
+* Add support for EP82xxM boards
+ Patch by Aaron Sells, 20 Jun 2006
+
+* Fix comments in include/ppc440.h
+ Patch by Martin Hicks, 16 Jun 2006
+
+* Update for CAM5200 board:
+ - Map in a additional chip selects CS4 and CS5.
+ - Modify the port configration, configure six UARTs and no PCI,
+ ATA and USB.
+ - Add custom flash driver to handle specific byte swapping
+
+* Fix TLB setup for Ocotea board
+ Patch by Stefan Roese, 30 Sep 2006
+
+* Fix reset problem in sequoia sdram init code
+ Patch by Stefan Roese, 23 Sep 2006
+
+* Disable autoboot abort for FO300 when silent mode is enabled
+ (according to S1 switch setting).
+
+* Cleanup examples binaries
+
+* Add support for AMCC Rainier PPX440GRx eval board
+ Patch by Stefan Roese, 13 Sep 2006
+
+* Add NAND environment support for PPC440EPx Sequoia NAND boot config
+ Patch by Stefan Roese, 12 Sep 2006
+
+* Update NAND boot documentation
+ Patch by Stefan Roese, 12 Sep 2006
+
+* Fix alignment problem in "mtdparts" command
+
+* Add documentation on the latest build environment extensions to
+ the README file.
+
+* Remove dead code (i2o and dma) from cpu/mpc824x/drivers/ directory.
+
+* Fix LOG_DIR directory creation error.
+ Add support for automatic creation of BUILD_DIR directory.
+
+* Fix build problem cpu/ppc4xx/ndfc.c
+ Patch by Stefan Roese, 07 Sep 2006
+
+* Fix build problem with CPCI440
+ Patch by Stefan Roese, 07 Sep 2006
+
+* Change Yellowstone to use CFI write buffer
+ Patch by Stefan Roese, 07 Sep 2006
+
+* Add support for AMCC Sequoia PPC440EPx eval board
+ - Add support for PPC440EPx & PPC440GRx
+ - Add support for PPC440EP(x)/GR(x) NAND controller
+ in cpu/ppc4xx directory
+ - Add NAND boot functionality for Sequoia board,
+ please see doc/README.nand-boot-ppc440 for details
+ - This Sequoia NAND image doesn't support environment
+ in NAND for now. This will be added in a short while.
+ Patch by Stefan Roese, 07 Sep 2006
+
+* Fix mkimage -l bug with multifile images on 64bit platforms
+ Patch by David Updegraff, 06 Sep 2006
+
+* Fix build problems on sorcery board.
+
+* Fix coldfire build problems.
+ Patch by Marian Balakowicz, 01 Sep 2006
+
+* Add support for a saving build objects in a separate directory.
+ Modifications are based on the Linux kernel approach and support
+ two use cases:
+ 1) Add O= to the make command line 'make O=/tmp/build all'
+ 2) Set environement variable BUILD_DIR to point to the desired location
+ 'export BUILD_DIR=/tmp/build'
+ 'make'
+ The second approach can also be used with a MAKEALL script
+ 'export BUILD_DIR=/tmp/build'
+ './MAKEALL'
+ Command line 'O=' setting overrides the BUILD_DIR environent variable.
+ When none of the above methods is used the local build is performed
+ and the object files are placed in the source directory.
+
+* Remove the board/netstar/crcit binary from git repository.
+
+* Fix tools/updater build error.
+
+* Fix tools/easylogo build error.
+
+* Fixed problems on PRS200 board caused by adding splash screen on MCC200
+
+* Extended README entry on coding style
+
+* Added another example showing simple interrupt interception.
+
+* Added simple_strtoul(), getenv() and setenv() to the exported functions.
+ Also bumped up ABI version to reflect this change.
+
+* Added interrupt handling capabilities for mpc5xxx processors.
+ Also added Linux like BUG() macros.
+
+* Coding Style cleanup.
+ Patch by Stefano Babic, 31 Aug 2006
+
+* Add splashscreen support for MCC200 board.
+
+* Make the serial driver framework work with CONFIG_SERIAL_MULTI
+ enabled
+
+* PCIe endpoint support for AMCC Yucca 440SPe board
+ Patch by Tirumala R Marri, 26 Aug 2006
+
+* Improve DIMM detection for AMCC Yucca 440SPe board
+ Improved the memory DIMM detection for the Yucca 440SPe board for
+ the case where a memory DIMM is falsely detected as present.
+ This issue is seen on some AMCC Yucca 440SPe validation boards if
+ only one 512MB memory DIMM is installed, i.e. DIMM slot 0 is
+ populated and DIMM slot 1 is empty. In this case, U-Boot does
+ not correctly detect that there is only one DIMM memory module
+ installed and will falsely detect two DIMM memory modules are
+ present and therefore U-Boot will not calculate the correct amount
+ of total memory and u-boot will not booting up.
+ Patch by Adam Graham, 24 Aug 2006
+
+* Fix typo.
+
+* Code cleanup
+
+* Update for MCC200 / PRS200 boards:
+ - auto-adjust console device for Linux.
+ - fix typos.
+
+* Add a fix for a buggy USB device on the FO300 board.
+
+* Updates for MCC200 / PRS200 boards:
+ - support for configurations with SDRAM or DDR memory,
+ - support for highboot and lowboot
+ - adjusting environment definitions
+
+* Add support for WTK FO300 board (TQM5200 based).
+
+* Fix TQM834x hang.
+
+* Update for SC520 board.
+ Patch by David Updegraff, 02 Dec 2005
+
+* Fixed common.h spelling error.
+ Patch by Cory Tusar, 30 Nov 2005
+
+* Fix typo.
+ Patch by Andreas Engel, 28 Nov 2005
+
+* Fix fatload command on FAT32 formatted partitions.
+ Patch by Joachim Jaeger, 18 Nov 2005
+
+* Fix drivers/dm9000.c when configured in 32 bit mode.
+ Patch by Eric Benard, 17 Nov 2005
+
+* Cleanup debug code for yucca board.
+
+* MCC200: restrict addressable flash space to 32 MB
+
+* Add debug console on COM12 for MCC200 board
+
+* Fix control-c handing in CONFIG_CMDLINE_EDITING
+ Properly pass break code back from readline.
+ Patch by Roger Blofeld, 31 Jul 2006
+
+* Add commandline history support to all AMCC eval boards
+ Patch by Stefan Roese, 07 Aug 2006
+
+* Add Macronix MXLV320T flash support for AMCC Bamboo
+ Patch by Stefan Roese, 07 Aug 2006
+
+* Change "mii info" to not print an error upon missing PHY at address
+ Patch by Stefan Roese, 07 Aug 2006
+
+* Fix PCI-Express on PPC440SPe rev. A.
+
+* Fix preboot message on TQM85xx after switching to hush parser.
+
+* Adapt TQM85xx ramdisk address to Linux kernel memory map
+
+* Add initial support for PCI-Express on PPC440SPe (Yucca board).
+
+* Fix compiler warning for TRAB board.
+ Patch by Martin Krause, 07 Aug 2006
+
+* Prevent USB commands from working when USB is stopped.
+
+* Add rudimentary handling of alternate settings of USB interfaces.
+ This is in order to fix issues with some USB sticks timing out
+ during initialization. Some code readability improvements.
+
+* PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
+ AMCC suggested to set the PMU bit to 0 for best performace on
+ the PPC440 DDR controller.
+ Please see doc/README.440-DDR-performance for details.
+ Patch by Stefan Roese, 28 Jul 2006
+
+* AMCC bamboo (440EP) U-Boot image reduced to 384kbyte
+ Please see doc/README.bamboo for details.
+ Patch by Stefan Roese, 27 Jul 2006
+
+* Fix CONFIG_CMDLINE_EDITING implementation
+ Patch by Stefan Roese, 27 Jul 2006
+
+* Fix preboot message on TQM5200 after switching to hush parser.
+
+* MCC200: set default configuration to low_boot DDR,
+ and support for configurable options high_boot and/or SDRAM.
+
+* Add support for 256 MB SDRAM on CPU87
+ Patch by Josef Wagner, 25 Nov 2005
+
+* Add configuration for cam5200 board (based on TQM5200S).
+
+* More code cleanup
+
+* Disabled kvme080 board in MAKEALL because of build problems.
+
+* Code cleanup
+
+* Update NetStar board
+ Patch by Ladislav Michl, 03 Nov 2005
+
+* Make code better readable.
+ Patch by Ladislav Michl, 14 Sep 2005
+
+* Enable initrd ATAG for xm250 board.
+ Patch by Josef Wagner, 05 Sep 2005
+
+* Add readline cmdline-editing extension
+ Patch by JinHua Luo, 01 Sep 2005
+
+* Add support for friendly-arm SBC-2410X board
+ Patch by JinHua Luo, 01 Sep 2005
+
+* Fix multi-part image support on i386 platform.
+ Patch by David Updegraff, 19 Aug 2005
+
+* Add support for KVME080 board
+ Patch by Sangmoon Kim, 18 Aug 2005
+
+* Fix MIPS LE build problem
+ Patch by Matej Kupljen, 10 Aug 2005
+
+* Check argument count in "mii" command.
+ Problem pointed out by Andrew Dyer, 13 Jun 2005
+
+* Cleanup TQM5200 board configurations:
+ - make highboot configurations use environment at high end, too,
+ to avoid flash fragmentation
+ - always use redundand environment
+ - don't enable video code for modules without graphics controller
+ - provide useful (though different) mtdparts settings
+ - get rid of CONFIG_CS_AUTOCONF which was always set anyway
+
+* Extend mkconfig tool to print more useful target name
+
+* Add support for high-boot on TQM5200 and TQM5200S boards.
+ Hint: the CPLD on the TQM5200 must be programmed with a software
+ version supporting the high boot option! The new TQM5200S is
+ already supporting this option. On the TQM5200 this option will be
+ supported in configurations with MPC5200 rev B processors.
+ To actually "high boot", set jumper X30 on the STK52xx.
+ Patch by Martin Krause, 12 Jul 2006
+
+* Add support for new TQM5200 revisions
+ - Support for TQM5200S (short version without graphic controller)
+ - Support for modules with 'N' type S29GL128N Spansion flashes
+ (requires changes to flash layout)
+ - Support for MPC5200B cpu (mostly support for second SDRAM bank)
+ Patch by Martin Krause, 07 Jul 2006
+
+* Fix support for PS/2 keyboard on TQM85xx boards
+ The PS/2 keyobard driver for the TQM85xx modules only supports the
+ internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't
+ include a DUART, the TQM8560 modules can't be used with the PS/2
+ keyboard controller on the STK85xx board.
+ The PS/2 keyboard driver should work with the modules TQM8540,
+ TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet.
+ Make sure the PS/2 controller on the STK85xx is programmed. Jumper
+ settings: X66 1-2, 9-10; X61 2-3
+ Patch by Martin Krause, 21 Jun 2006
+
+* Adjust RTC century handling on STK52xx board to match Linux driver.
+ Patch by Martin Krause, 12 Jun 2006
+
+* Adjust filenames for USB update images on TRAB board.
+ During an automatic update via USB stick, U-Boot searches for
+ images with the name "firmware.img" and "kernel.img". This names
+ are now changed to "firmw_01.img" and "kernl_01.img". This is done,
+ to prevent updates of new boards (with the new macronics "c" step
+ flashes) with old, incompatible firmware or kernel versions.
+ Patch by Martin Krause, 21 Jun 2006
+
+* Bugfix in VFD routine on TRAB board.
+ Make sure upper lext pixel can be set to blue, too
+ (so far only red was possible).
+ Patch by Martin Krause, 15 Feb 2006
+
+* Enable buffered flash writes for TB5200 board.
+
+* Fix some bugs in TRAB board flash driver.
+ - increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds
+ - use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT
+ - remove "Unlock Bypass" mode, because macronix flashes do not support
+ this mode officially
+ - fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified
+ for Intel compatible flashes, not for AMD compatible.
+ Patch by Martin Krause, 15 Feb 2006
+
+* Add additional error messages to flash driver on TRAB board
+ (for erase errors and timeout errors)
+ Patch by Martin Krause, 14 Feb 2006
+
+* Add support for TB5200 board
+ The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
+ integrated in a little aluminium case.
+ Patch by Martin Krause, 8 Jun 2006
+
+* Enable buffered flash writes for TQM5200 board.
+
+* Fix problems with SanDisk Corporation Cruzer Micro USB memory stick.
+
+* Add support for TQM885D board.
+ Patch by Martin Krause, 20 Mar 2006
+
+* Fix FEC initialisation: All MII configuration is done via FEC1
+ registers, but MII_SPEED was configured according to FEC used. So
+ if only FEC2 was used, this caused the real MII_SPEED register in
+ FEC1 to stay uninitalised, leqading to "mii_send STUCK!" messages.
+ Fix: always configure MII_SPEED on FEC1 only.
+ Patch by Markus Klotzbuecher, 12 Jul 2006
+
+* Add support for SPC1920 board.
+ Patch by Markus Klotzbuecher, 12 Jul 2006
+
+* MCC200 board: support console on any one of the Quad UART ports.
+
+* Fix error in flash protection calculation on MCC200 board.
+
+* Major PCMCIA Cleanup to make code better readable and maintainable.
+ Notes:
+ - Board-dependend code for RPXLITE and RPXCLASSIC-based boards
+ placed to the drivers/rpx_pmcia.c file to avoid duplication.
+ Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c).
+ - drivers/i82365.c has been split into two parts located at
+ board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are
+ the only boards using CONFIG_82365).
+ - Changes were tested for clean build and *very* *few* boards.
+
+* Fix timer problems on AMCC yucca board.
+ Set Timer Clock Select to use CPU clock as a timer input source.
+
+* Bring yucca config more in line with other AMCC boards.
+
+* Add AMCC bamboo board to MAKEALL build script.
+
+* Fix AMCC bamboo eval board compilation errors.
+
+* Add system memory to the PCI region list for AMCC PPC44x CPUs.
+ Enabled it for Yucca board.
+
+* Cleanup config file and bootup output for Yucca board.
+
+* Fix CONFIG_440_GX define usage.
+
+* Remove autogenerated bmp_logo.h file.
+
+* Add support for AMCC 440SPe CPU based eval board (Yucca).
+
+* Call serial_initialize() before first debug() is used.
+
+* Cleanup trab board for GCC-4.x
+
+* VoiceBlue update: use new MTD flash partitioning methods, use more
+ reasonable TEXT_BASE, update default environment and enable keyed
+ autoboot.
+ Patch by Ladislav Michl, 16. Aug 2005
+
+* Add forgotten changes for the PLEB 2 Board.
+ Patch by David Snowdon, 13. Aug 2005
+
+* Add support for wrPPMC7xx/74xx boards
+ Patch by Richard Danter, 12 Aug 2005
+
+* Add support for gth2 board
+ Patch by Thomas Lange, Aug 11 2005
+
+* Add support for CONFIG_SERIAL_MULTI on MPC5xxx
+ Patch by Martin Krause, 8 Jun 2006
+
+ This patch supports two serial consoles on boards with
+ a MPC5xxx CPU. The console can be switched at runtime
+ by setting stdin, stdout and stderr to the desired serial
+ interface (serial0 or serial1). The PSCs to be used as
+ console port are definded by CONFIG_PSC_CONSOLE
+ and CONFIG_PSC_CONSOLE2.
+ See README.serial_multi for details.
+
+* Bugfix in I2C initialisation on S3C2400.
+ If the bus is blocked because of a previously interrupted
+ transfer, up to eleven clocks are generated on the I2CSCL
+ line to complete the transfer and to free the bus.
+ With this fix pin I2CSCL (PG6) is really configured as GPIO
+ so the clock pulses are really generated.
+ Patch by Martin Krause, 04 Apr 2006
+
+* Fix DDR6 errata on TQM834x boards
+ Patch by Thomas Waehner, 07 Mar 2006
+
+* Remove obsolete flash driver board/tqm5200/flash.c
+ Patch by Martin Krause, 11 Jan 2006
+
+* Update configuration for CMC-PU2 board
+ Patch by Martin Krause, 17 Nov 2005
+
+* Add support for PS/2 keyboard on TQM85xx board
+ Patch by Martin Krause, 07 Nov 2005
+
+ Tested on a STK85XX baseboard. Make sure the PS/2 controller
+ has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
+
+* Fix TRAB channel switching delay for trab_fkt.bin standalone applikation
+ In tsc2000_read_channel() the delay after setting the multiplexer
+ to a temperature channel is increased from 1,5 ms to 10 ms. This
+ is to allow the multiplexer inputs to stabilize after huge steps
+ of the input signal level.
+ Patch by Martin Krause, 08 Nov 2005
+
+* Adjust TQM5200 make targets
+ Make the automatic CS configuration the default.
+ The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB
+ and CONFIG_TQM5200_AC are removed.
+ "TQM5200_config" is now the default for STK52XX.200 base boards.
+ On a STK52XX.100 base board "TQM5200_STK100_config" must be used.
+ Patch by Martin Krause, 07 Nov 2005
+
+* Fix setting of environment variable "ver" on trab board
+ The environment variable "ver" is now set before
+ do_auto_update() is called, so that "ver" can be used
+ in USB update scripts.
+ Patch by Martin Krause, 27 Oct 2005
+
+* Fix wrong usage of udelay() in led_blink() on trab board
+ Patch by Martin Krause, 27 Oct 2005
+
+* Fix udelay bug in vfd.c for trab board
+ Patch by Martin Krause, 27 Oct 2005
+
+* Disable JFFS2 support for trab board
+ Patch by Martin Krause, 27 Oct 2005
+
+* Change mtdparts definition on trab board to match current flash map
+ Patch by Martin Krause, 27 Oct 2005
+
+* Fix memory init problems on MCC200 board
+
+* Fix IxEthDB.h to compile again
+ Patch by Stefan Roese, 14 Jun 2006
+
+* Minor cleanup for PCS440EP board
+ Patch by Stefan Roese, 13 Jun 2006
+
+* Add MCF5282 support (without preloader)
+ relocate ichache_State to ram
+ u-boot can run from internal flash
+ Add EB+MCF-EV123 board support.
+ Add m68k Boards to MAKEALL
+ Patch from Jens Scharsig, 08 Aug 2005
+
+* Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Nios II - Add EPCS Controller bootrom work-around
+ -When booting from an epcs controller, the epcs bootrom may leave the
+ slave select in an asserted state causing soft reset hang. This
+ patch ensures slave select is negated at reset.
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Update PK1C20 board
+ -Update base addresses for standard configuration
+ -Eliminate use of CACHE_BYPASS in board code
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Nios II - Fix I/O Macros and mini-app stubs
+ -Fix asm/io.h macros
+ -Eliminate use of CACHE_BYPASS in cpu code
+ -Eliminate assembler warnings
+ -Fix mini-app stubs and force no small data
+ Patch by Scott McNutt, 08 Jun 2006
+
+* Fix U-Boot environment sector protection on MCC200 board
+
+* Minor cleanup for PCS440EP board
+
+* Update PCS440EP port to fit into one flash device (incl. environment)
+ Patch by Stefan Roese, 06 Jun 2006
+
+* Add support for PCS440EP board
+ Patch by Stefan Roese, 02 Jun 2006
+
+* Fix examples/Makefile; some build targets were lost
+
+* Fix watchdog handling in CFI flash driver
+ Just use udelay() when waiting for status changes which will
+ implicitely trigger the watchdog.
+
+* Fix PCI to memory window size problems on PM82x boards
+ We use the "automatic" mode that was used for the MPC8266ADS and
+ MPC8272 boards. Eventually this should be used on all boards?]
+ Patch by Wolfgang Grandegger, 17 Jan 2006
+
+* Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone
+ Patch by Stefan Roese, 29 May 2006
+
+* Update Intel IXP4xx support
+ - Add IXP4xx NPE ethernet MAC support
+ - Add support for Intel IXDPG425 board
+ - Add support for Prodrive PDNB3 board
+ - Add IRQ support
+ Patch by Stefan Roese, 23 May 2006
+
+* Fix problem in PVR detection for 440GR
+ Patch by Stefan Roese, 18 May 2006
+
+* Fix gcc 3.4.x AFLAGS setting for m68k platform.
+
+* Enable autoboot for M5271EVB board.
+
+* Changed default ramdisk addr in yosemite/yellowstone ports
+ Patch by Stefan Roese, 15 May 2006
+
+* Fix PCMCIA support on virtlab2
+
+* Add support for VirtLab2 board
+ (needed because of differences in the PCMCIA hardware).
+
+* Minor cleanup.
+
+* Update yosemite configuration to enable flash write buffer support
+ Patch by Stefan Roese, 10 May 2006
+
+* Fix compile warnings in common/xyzModem.c
+ Patch by Stefan Roese, 10 May 2006
+
+* Add support for AMCC 440EP Rev C and 440GR Rev B
+ Patch by John Otken, 08 May 2006
+
+* OMAP 5912/OSK: update EMIFS CS1 timings:
+ Problems have been seen in the linux kernel's smc91x network driver
+ due to improper bus timings. The latest 2.6 OMAP kernels currently
+ have a workaround, but this fix belongs in u-boot.
+ Patch by Kevin Hilman, 13 Oct 2005
+
+* Fix REG_MPU_LOAD_TIMER definition in multiple OMAP ports
+ Patch by Hiroki Kaminaga, 11 Mar 2006
+
+* Update omap5912osk board support
+ - Fix OMAP support that omap5912osk compiles in current source tree
+ - Update with code from "http://omap.spectrumdigital.com/osk5912"
+ to fix problems with DDR initialization
+ - Fix timer setup
+ - Use CFI flash driver and support complete 32MB of onboard flash
+ - Add "print_cpuinfo()" and "checkboard()" functions to display
+ CPU (with frequency) and Board infos
+ Patch by Stefan Roese, 10 May 2006
+
+* Fix watchdog issues for ColdFire boards.
+
+* Add M5271EVB board support.
+
+* Make R5200 specific low level initialization board conditional.
+
+* Update CPU target identification strings for ColdFire family.
+
+* Update register definitions for MCF5271.
+
+* Fix serial console support for MCF5271.
+
+* Fixes for gcc 3.4 based m68k toolchain,
+ based on patch by Jate Sujjavanich.
+
+* Fix lowboot support on MCC200 board
+
+* Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port:
+ - Removed MPC8349ADS port
+ - Added PCI support to MPC8349ADS
+ - reworked memory map to allow mapping of all regions with BATs
+ Patch by Kumar Gala, 20 Apr 2006
+
+* Coding Style cleanup
+
+* Write RTC seconds first to maintain settings integrity per
+ Maxim/Dallas DS1306 data sheet.
+ Patch by Alan J. Luse, 02 May 2006
+
+* Scheduled for removal: strnicmp() which is unused
+
+* Update for Intel Monahans boards:
+ - support for magic key detection and handling on delta board
+ - NAND support for zylonite board + some minor cleanup
+
+* Declare load_serial_ymodem() when using CFG_CMD_LOADB.
+ Patch by Jon Loeliger, 01 May 2006
+
+* Fixed handling of bad checksums with "mkimage -l"
+
+* Added support for BC3450 board
+ Patch by Stefan Strobl, 21 Oct 2005
+
+* Update for NC650 board:
+ - Support rev1 and rev2 hardware
+ - adapt to new NAND layer
+ - add CP850 configuration based on NC650
+
+* MPC5200: enable snooping of DMA transactions on XLB even if no PCI
+ is configured; othrwise DMA accesses aren't cache coherent which
+ causes for example USB to fail.
+
+* Some code cleanup
+
+* Fix dbau1x00 boards broken by dbau1550 patch
+ PLL:s were not set for boards other than 1550.
+ Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
+ Default boot is now bootp for cards other than 1550.
+ Patch by Thomas Lange, 10 Aug 2005
+
+* Fixes common/cmd_flash.c:
+ - fix some compiler/parser error, if using m68k tool chain
+ - optical fix for protect on/off all messages, if using more
+ then one bank
+ Patch by Jens Scharsig, 28 Jul 2005
+
+* Fix Quad UART mapping on MCC200 board due to new HW revision
+
+* Fix JFFS2 support for legacy NAND driver.
+
+* Remove dependencies between DoC code and old legacy NAND driver.
+
+* Fix PM828_PCI target, for which PCI was *not* configured in.
+
+* Fix Lite5200B support: initialize SDelay register
+ See Freescale's AN3221 "MPC5200B SDRAM Initialization and
+ Configuration", 3.3.1 SDelay--MBAR + 0x0190
+
+* Changes/fixes for drivers/cfi_flash.c:
+
+ - Add Intel legacy lock/unlock support to common CFI driver
+
+ On some Intel flash's (e.g. Intel J3) legacy unlocking is
+ supported, meaning that unlocking of one sector will unlock
+ all sectors of this bank. Using this feature, unlocking
+ of all sectors upon startup (via env var "unlock=yes") will
+ get much faster.
+
+ - Fixed problem with multiple reads of envronment variable
+ "unlock" as pointed out by Reinhard Arlt & Anders Larsen.
+
+ - Removed unwanted linefeeds from "protect" command when
+ CFG_FLASH_PROTECTION is enabled.
+
+ - Changed p3p400 board to use CFG_FLASH_PROTECTION
+
+ Patch by Stefan Roese, 01 Apr 2006
+
+* Changes/fixes for drivers/cfi_flash.c:
+ - Correctly handle the cases where CFG_HZ != 1000 (several
+ XScale-based boards)
+ - Fix the timeout calculation of buffered writes (off by a
+ factor of 1000)
+ Patch by Anders Larsen, 31 Mar 2006
+
+* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)
+
+ 405 SDRAM: - The SDRAM parameters can now be defined in the board
+ config file and the 405 SDRAM controller values will
+ be calculated upon bootup (see PPChameleonEVB).
+ When those settings are not defined in the board
+ config file, the register setup will be as it is now,
+ so this implementation should not break any current
+ design using this code.
+
+ Thanks to Andrea Marson from DAVE for this patch.
+
+ 440 DDR: - Added function sdram_tr1_set to auto calculate the
+ TR1 value for the DDR.
+ - Added ECC support (see p3p440).
+
+ Patch by Stefan Roese, 17 Mar 2006
+
+* Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S
+ Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]
+
+* Add support for ymodem protocol download
+ Patch by Stefano Babic, 29 Mar 2006
+
+* Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000
+ Merge from Markus Klotzbücher's repo, 01 Apr 2006
+
+* GCC-4.x fixes: clean up global data pointer initialization for all
+ boards
+
+* Update for Delta board:
+ - redundant NAND environment
+ - misc Monahans cleanups (remove dead code etc.)
+ - DA9030 Initialization; some minimal changes to PXA I2C driver to
+ make it work with the Monahans.
+ - Make Monahans clock frequency configurable using
+ CFG_MONAHANS_RUN_MODE_OSC_RATIO and
+ CFG_MONAHANS_TURBO_RUN_MODE_RATIO.
+ Merge from Markus Klotzbücher's repo, 25 Mar 2006
+
+* Enable Quad UART om MCC200 board.
+
+* Cleanup MCC200 board configuration; omit non-existent stuff.
+
+* Add support for MPC859/866 Rev. A.0
+
+* Add command for handling DDR ECC registers on MPC8349EE MDS board.
+
+* Fix DDR ECC bit definitions for MPC83xx.
+
+* Add initial support for MPC8349E MDS board.
+
+* Add support for ECC DDR initialization on MPC83xx.
+
+* Add DMA support for MPC83xx.
+
+* Add sync in do_reset() routine for MPC83xx after RPR register
+ was written to. It is need on some targets when BAT translation
+ is enabled.
+
+* Add bit definitions for MPC83xx DDR controller registers.
+
+* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.
+
+* Correct shift offsets in icache_status and dcache_status for MPC83xx.
+
+* Add support for DS1374 RTC chip.
+
+* Add support for Lite5200B board.
+ Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006
+
+* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific
+ timer and cpu_reset code from cpu/$(CPU) into the new
+ cpu/$(CPU)/$(SOC) directories
+ Patch by Andreas Engel, 13 Mar 2006
+
+* Change max size of uncompressed uImage's to 8MByte and add
+ CFG_BOOTM_LEN to adjust this setting.
+
+ As mentioned by Robin Getz on 2005-05-24 the size of uncompressed
+ uImages was restricted to 4MBytes. This default size is now
+ increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN
+ in the board config file.
+
+ Patch by Stefan Roese, 13 Mar 2006
+
+* Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c
+ Patch by Stefan Roese, 13 Mar 2006
+
+* cpu/ppc4xx/start.S : exceptions are enabled after relocation
+ Patch by Cedric Vincent, 06 Jul 2005
+
+* au1x00_eth.c: check malloc return value and abort if it failed
+ Patch by Andrew Dyer, 26 Jul 2005
+
+* Change the sequence of events in soft_i2c.c:send_ack() to keep from
+ incorrectly generating start/stop conditions on the bus.
+ Patch by Andrew Dyer, 26 Jul 2005
+
+* Fix bug in [id]cache_status commands for MPC85xx processors;
+ should look at LSB of L1CSRn registers to determine if L1 cache is
+ enabled, not the MSB.
+ Patch by Murray Jensen, 19 Jul 2005
+
+* Fix array overflow with fw_setenv on uninitialised environment
+ Patch by Murray Jensen, 15 Jul 2005
+
+* Add support for EmbeddedPlanet EP88x boards
+ Patch by Yuli Barcohen, 13 Jul 2005
+
+* Remove board specific configuration includes from the common xilinx
+ ethernet and iic adapter code.
+ Patch by Michael Libeskind, 12 Jul 2005
+
+* Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Add (some) definitions for the MPC85xx local bus controller
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Add CPM2 I/O pin functions for MPC85xx processors
+ Patch by Murray Jensen, 08 Jul 2005
+
+* Fix compile problem
+
+* Added PCI support for MPC8349ADS board
+ Patch by Kumar Gala 11 Jan 2006
+
+* Enable address translation on MPC83xx
+ Patch by Kumar Gala, 10 Feb 2006
+
+* Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx
+ Patch by Kumar Gala, 25 Jan 2006
+
+* Fixed defines for MPC83xx SICRL register to match current specs
+ Patch by Kumar Gala, 23 Jan 2006
+
+* Only disable the MPC83xx watchdog if its enabled out of reset.
+ If its disabled out of reset SW can later enable it if so desired
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Allow config of GPIO direction & data registers at boot on 83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Enable time handling on 83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Make System IO Config Registers board configurable on MPC83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Fixed PCI indirect config ops to handle multiple PCI controllers
+ We need to adjust the bus number we are trying to access based
+ on which PCI controller its on
+ Patch by Kumar Gala, 12 Jan 2006
+
+* Report back PCI bus when doing table based device config
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added support for PCI prefetchable region and BARs
+ If a host controller sets up a region as prefetchable and
+ a device's BAR denotes it as prefetchable, allocate the
+ BAR into the prefetch region.
+
+ If a BAR is prefetchable and no prefetchable region has
+ been setup by the controller we fall back to allocating
+ the BAR into the normally memory region.
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add helper function for generic flat device tree fixups for mpc83xx
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add support for passing initrd information via flat device tree
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added OF_STDOUT_PATH and OF_SOC
+
+ OF_STDOUT_PATH specifies the path to the device the kernel can use
+ for console output
+
+ OF_SOC specifies the proper name of the SOC node if one exists.
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Allow board code to fixup the flat device tree before booting a kernel
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Added CONFIG_ options for bd_t and env in flat dev tree
+
+ CONFIG_OF_HAS_BD_T will put a copy of the bd_t
+ into the resulting flat device tree.
+
+ CONFIG_OF_HAS_UBOOT_ENV will copy the environment
+ variables from u-boot into the flat device tree
+
+ Patch by Kumar Gala, 11 Jan 2006
+
+* Add support for the DHCP vendor optional bootfile (#67).
+ Ignores the vendor TFTP server name option (#66).
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode
+ Patch by Andy Fleming, 14 Jun 2005
+
+* Fix bad register definitions for LTX971 PHY on MPC85xx boards.
+ Patch by Gerhard Jaeger, 21 Jun 2005
+
+* Add netconsole and some more commands to RPXlite_DW board
+ Patch by Sam Song, 19 Jun 2005
+
+* Fix bad declaration on pci_cfgfunc_nothing
+ Patch by Sam Song, 19 Jun 2005
+
+* Adjust "echo" as a default command
+ Patch by Sam Song, 19 Jun 2005
+
+* Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC
+ Patch by KokHow Teh, 16 Jun 2005
+
+* Add crc of data to jffs2 (in jffs2_1pass_build_lists()).
+ Patch by Rick Bronson, 15 Jun 2005
+
+* Coding Style cleanup
+
+* Avoid dereferencing NULL in find_cmd() if no valid commands were found
+ Patch by Andrew Dyer, 13 Jun 2005
+
+* Add ADI Blackfin support
+ - add support for Analog Devices Blackfin BF533 CPU
+ - add support for the ADI BF533 Stamp uClinux board
+ - add support for the ADI BF533 EZKit board
+ Patches by Richard Klingler, 11 Jun 2005
+
+* Add loads of ntohl() in image header handling
+ Patch by Steven Scholz, 10 Jun 2005
+
+* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment
+ variable to set clock
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* RPXlite configuration fixes
+ - Use correct flash sector size
+ - Use correct memory test end address
+ - Add support for bzip2 compression
+ - Various small fixes
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Memory configuration changes for ZPC.1900 board
+ - Fix SDRAM timing on both local bus and 60x bus
+ - Add support for second flash bank (SIMM)
+ - Change boot flash base
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Add support for Adder boards with 16MB SDRAM;
+ add support for second FEC on Adder87x board.
+ Patch by Yuli Barcohen, 05 Jun 2005
+
+* Fix conditional for including ks8695eth driver
+ Patch by Greg Ungerer, 04 Jun 2005
+
+* Fix Makefile: include config.mk only after CROSS_COMPILE is defined
+ Patch by Friedrich Lobenstock, 02 Jun 2005
+
+* Fix comment in common/soft_i2c.c
+ Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005
+
+* Cleanup compiler warnings.
+ Patch by Greg Ungerer, 21 May 2005
+
+* Word alignment fixes for word aligned NS16550 UART
+ Patch by Jean-Paul Saman, 01 Mar 2005
+
+ Fixes bug with UART that only supports word aligned access: removed
+ "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some
+ (broken!) versions of GCC generate byte accesses when encountering
+ the packed attribute regardless if the struct is already correctly
+ aligned for a platform. Peripherals that can only handle word
+ aligned access won't work properly when accessed with byte access.
+ The struct NS16550 is already word aligned for REG_SIZE = 4, so
+ there is no need to packed the struct in that case.
+
+* Fix behaviour if gatewayip is not set
+ Patch by Robin Gilks, 23 Dec 2004
+
+* Fix cleanup for netstart board.
+ Remove build results from repository
+
+* Some code cleanup for GCC 4.x
+
+* Fixes to support environment in NAND flash;
+ enable NAND flash based environment for delta board.
+
+* Add support for Intel Monahans CPU on Zylonite and Delta boards
+ (This is Work in Progress!)
+
+* Add support for TQM8260-AI boards.
+
+* Minor code cleanup
+
+* Merge the new NAND code (testing-NAND brach); see doc/README.nand
+ Rewrite of NAND code based on what is in 2.6.12 Linux kernel
+ Patch by Ladislav Michl, 29 Jun 2005
+
+* Add lowboot target to mcc200 board
+ Patch by Stefan Roese, 4 Mar 2006
+
+* Fix problem with flash_get_size() from CFI driver update
+ Patch by Stefan Roese, 1 Mar 2006
+
+* Make CFG_NO_FLASH work on ARM systems
+ Patch by Markus Klotzbuecher, 27 Feb 2006
+
+* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock,
+ use hush shell.
+
+* Convert mcc200 to use common CFI flash driver
+ Patch by Stefan Roese, 28 Feb 2006
+
+* Add env-variable "unlock" to handle initial state of sectors
+ (locked/unlocked).
+
+ Only the U-Boot image and it's environment is protected,
+ all other sectors are unprotected (unlocked) if flash
+ hardware protection is used (CFG_FLASH_PROTECTION) and
+ the environment variable "unlock" is set to "yes".
+
+ Patch by Stefan Roese, 28 Feb 2006
+
+* Update drivers/cfi_flash.c:
+ - find_sector() called in both versions of flash_write_cfiword()
+ Patch by Peter Pearse, 27th Feb 2006
+
+* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode
+ Patch by Jose Maria Lopez, 16 Jan 2006
+
+* Add support for AMD/Spansion Flashes in flash_write_cfibuffer
+ Patch by Alex Bastos and Thomas Schaefer, 2005-08-29
+
+* Changes/fixes for drivers/cfi_flash.c:
+ We *should* check if there are any error bits if the previous call
+ returned ERR_OK (Otherwise we will have output an error message in
+ flash_status_check() already.) The original code would only check for
+ error bits if flash_status_check() returns ERR_TIMEOUT.
+ Patch by Marcus Hall, 23 Aug 2005
+
+* Changes/fixes for drivers/cfi_flash.c:
+ - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c
+ - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c
+ Patch by Sangmoon Kim, 19 Aug 2005
+
+* Fixes for drivers/cfi_flash.c:
+ - Fix wrong timeout value usage in flash_status_check()
+ - Round write_tout up when converting to msec in flash_get_size()
+ - Remove clearing flash status at the end of flash_write_cfibuffer()
+ which sets Intel 28F640J3 flash back to command mode on CSB472
+ Patch by Tolunay Orkun, 02 July 2005
+
+* Add basic support for the SMMACO4 Board from PanDaCom.
+ Patch by Heiko Schocher, 20 Feb 2006
+
+* Add GIT version information (commid ID) to untagged U-Boot versions
+
+ As done in the linux kernel, the U-Boot version (U_BOOT_VERSION)
+ of all unreleased (untagged) U-Boot images will be automatically
+ extended upon compiletime with a part of the GIT commit ID and
+ possibly with "dirty" if uncommited changes are detected.
+
+ Here an example for the resulting version:
+ "U-Boot 1.1.4-g3457ac18-dirty"
+
+ The version is now maintained in the toplevel Makefile and the
+ version headers are autogenerated.
+
+ Patch by Stefan Roese, 9 Feb 2006
+
+* Update default environment for INKA4x00 board.
+
+* Convert CPCI750 to use common CFI flash driver
+ Patch by Reinhard Arlt, 8 Feb 2006
+
+* Various changes to esd HH405 board specific files
+ Patch by Matthias Fuchs, 07 Feb 2006
+
+* Cleanup U-Boot boot messages on ARM.
+
+ To match the U-Boot user interface on ARM platforms to the U-Boot
+ standard (as on PPC platforms), some messages with debug character
+ are removed from the default U-Boot build.
+ Enable DEBUG for lib_arm/board.c to enable debug messages.
+ New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options.
+ Patch by Stefan Roese, 24 Jan 2006
+
+* Fix various compiler warnings on ppc4xx builds (ELDK 4.0)
+ Patch by Stefan Roese, 18 Jan 2006
+
+* Add VGA support (CT69000) to CPCI750 board.
+ Insert missing __le32_to_cpu() for filesize in ext2fs_read_file().
+ Patch by Reinhard Arlt, 30 Dec 2005
+
+* PMC405 and CPCI405: Moved configuration of pci resources
+ into config file.
+ PMC405 and CPCI2DP: Added firmware download and booting via pci.
+ Patch by Matthias Fuchs, 20 Dec 2005
+
+* Add ColdFire targets to MAKEALL script
+ Patch by Zachary Landau, 26 Jan 2006
+
+* Add support for r5200 board
+ Patch by Zachary Landau, 26 Jan 2006
+
+* Add support for Freescale M5271 processor
+ Patch by Zachary Landau, 26 Jan 2006
+
+* Fix 28F256J3A support on PM520 board
+ (without bank-switching only 32 MB can be accessed)
+
+* Fix mkimage bug with multifile images created on 64 bit systems.
+
+* Add support for 28F256J3A flash (=> 64 MB) on PM520 board
+
+* Fix compiler problem with at91rm9200dk board.
+ Patch by Eugen Bigz, 19 Dec 2005
+
+======================================================================
+Changes for U-Boot 1.1.4:
+======================================================================
+
+* Changes to Yellowstone & Yosemite 440EP/GR eval boards:
+ - Changed GPIO setup to enable another address line in order to
+ address 64M of FLASH.
+ - Added function sdram_tr1_set to auto calculate the tr1 value for
+ the DDR.
+ Patch by Steven Blakeslee, 12 Dec 2005
+
+* MPC5200: Set PCI retry counter to 0 = infinite retry;
+ The default of 255 is too short for slow devices.
+ Patch by Martin Nykodym, 12 Dec 2005
+
+* Change port configuration for O2DNT (CODEC1 on PSC1).
+
+* Fix register for PCI async mode on PPC440EP
+ Patch by Youngchul Bang, 08 Dec 2005
+
+* Fix U-Boot linking problems (add .eh_frame segment to linker script)
+ This segment may be required by some libgcc.a functions
+ (like _udivdi3).
+
+* Fix DPRAM offset/size for MPC8541/8555.
+ Simplify TQM85xx Makefile handling.
+
+* Fix data overflow (typo?) in rtc/ds1302.c
+
+* Fix U-Boot compilation for MIPS boards using ELDK 4.0
+
+* Add support for TQM8541/8555 boards, TQM85xx support reworked:
+ - Support for TQM8541/8555 boards added.
+ - Complete rework of TQM8540/8560 support.
+ - Common TQM85xx code now supports all current TQM85xx platforms
+ (TQM8540/8541/8555/8560).
+ - DDR SDRAM size detection added.
+ - CAS latency default values can be overwritten by setting "serial#"
+ to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used.
+ If problems are detected with this non default CAS latency,
+ the default values will be used instead.
+ - Flash size detection added.
+ - Moved FCC ethernet driver initialization behind TSEC driver init
+ -> TSEC is first device.
+ Patch by Stefan Roese, 30 Nov 2005
+
+* Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board.
+ Patch by John Otken, 23 Nov 2005
+
+* Changed PPC44x startup message (cpu info, speed...) to common style:
+ On PPC44x platforms, the startup message generated in "cpu.c" only
+ comprised the ppc type and revision but not additional information
+ like speed etc. Those speed infos where printed in the board specific
+ code. This new implementation now prints all CPU infos in the common
+ cpu specific code. No board specific code is needed anymore and
+ therefore removed from all current 44x implementations.
+ Patch by Stefan Roese, 27 Nov 2005
+
+* Adjust TQM834x PHY addresses for latest hardware revision.
+
+* Increase malloc arena on TQM5200 board to 256 kB.
+ With 64 kb uniform flash sector size the old value of 128 kB was
+ too small.
+
+* Fix miiphy global data initialization (problem on 4xx boards when
+ no ethaddr is assigned). Initialization moved from
+ miiphy_register() to eth_initialize().
+
+ Based on initial patch for 4xx platform by Matthias Fuchs.
+
+* Remove unnnecessary #include <linux/types.h> from include/asm-*/u-boot.h
+
+* Allow use of include/image.h and include/asm-*/u-boot.h in proprietary code.
+ The COPYING file was extended to make clear that these files can be
+ used in non-GPL code, too.
+ Also, a corresponding note was placed in the headers of the affected files.
+
+* Add support for Prodrive P3P440 board:
+ - Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c
+ - CFG_FLASH_QUIET_TEST added to use the common CFI driver
+ for bank autodetection
+ Patch by Stefan Roese, 22 Nov 2005
+
+* Change all '$(...)' variable references into '${...}'
+ which makes the environment compatible with the hush shell.
+ WARNING: Support for the old '$(...)' syntax will be
+ discontinued in a later version.
+
+* Minor changes to init flags in TQM834x PCI.
+
+* Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM)
+ Patch by Stefan Roese, 15 Nov 2005
+
+* New PPC 405EP board added: CMS700
+ Added CONFIG_NET_MULTI for VOM405 board.
+ Added reset_phy() for VOM405 board.
+ Patch by Matthias Fuchs, 09 Nov 2005
+
+* Updated PCI mapping for esd CPCI2DP board.
+ Add support for error LED.
+ Patch by Matthias Fuchs, 07 Nov 2005
+
+* Fix MPC85xx PCI support (pci_register_hose() before pci config access)
+ Patch by Stefan Roese, 07 Nov 2005
+
+* Correct PPC Timebase register definitions (SPRN_TBRL...)
+ Patch by Stefan Roese, 07 Nov 2005
+
+* Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size
+ Patch by Stefan Roese, 05 Nov 2005
+
+* Additional fix for external IRQ config on Yellowstone & Yosemite
+ Patch by Stefan Roese, 03 Nov 2005
+
+* Add support for Ocotea pass 3 with 440GX Rev. F
+ Patch by Stefan Roese, 01 Nov 2005
+
+* Fix external IRQ configuration on Yellowstone & Yosemite
+ Patch by Stefan Roese, 28 Oct 2005
+
+* Add support for multiple PHYs.
+ Tested on the following boards:
+ cmcpu2 (at91rm9200/ether.c)
+ PPChameleon (ppc4xx/4xx_enet.c)
+ yukon (mpc8220/fec.c)
+ uc100 (mpc8xx/fec.c)
+ tqm834x (mpc834x/tsec.c) with EEPRO100
+ lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c)
+ Main changes include:
+ common/miiphyutil.c
+ - miiphy_register routine was added to allow multiple PHYs to be registered
+ - miiphy_read and miiphy_write are now defined in this file, and
+ require additional argument (char *devname)
+ - other miiphy_* routines also require additional device name argument
+ ../lib_i386/board.c
+ ../lib_ppc/board.c
+ Calling reset_phy() was moved to be executed *after* eth_initialize().
+ This is necessary as now some of the implementations of reset_phy()
+ may need to use miiphy_reset() which is not allowed before eth_initialize()
+ as eth_initialize registers all required miiphy_* routines.
+ Tested on IP860 and PHY initializes properly after this change.
+
+* Correct includes for flat tree builder.
+
+* Fix conflicting types (flash_write()) in trab auto_update.c.
+
+* Add PCI support for the TQM834x board.
+
+* Add missing 4xx board to MAKEALL
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Fix conflicting types (flash_write()) in esd auto_update.c
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Fix problem with sleep in NetConsole (use get_timer())
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Add NetConsole Support for AMCC eval boards
+ Patch by Stefan Roese, 20 Oct 2005
+
+* Fix NetConsole support on 4xx (only print eth link on 1st transfer)
+ Patch by Stefan Roese, 18 Oct 2005
+
+* Add fat & ext2 support to AMCC 440EP boards Yosemite & Bamboo.
+ Fix identation on ext2ls help entry.
+ Patch by Stefan Roese, 14 Oct 2005
+
+* Add support for TQM834x boards.
+ Cleanup.
+
+* Cleanup for GCC-4.x
+
+* Add documentation for Open Firmware Flat Tree and usage.
+ Patch by Pantelis Antoniou, 13 Oct 2005
+
+* Add missing files for Pantelis Antoniou's patch
+ Patch by Pantelis Antoniou, 04 Sep 2005
+
+* Fix problem in ppc4xx eth-driver without ethaddr (only without
+ CONFIG_NET_MULTI set)
+ Patch by Stefan Roese, 10 Oct 2005
+
+* Fix gzip bmp support (test if malloc fails, warning when truncated).
+ Increase CFG_VIDEO_LOGO_MAX_SIZE on HH405 board.
+ Patch by Stefan Roese, 07 Oct 2005
+
+* Add support for OF flat tree for the STXtc board.
+ Patch by Pantelis Antoniou, 04 Sep 2005
+
+* Support passing of OF flat trees to the kernel.
+ Patch by Pantelis Antoniou, 04 Sep 2005
+
+* Cleanup
+
+* Add support for NetSilicon NS7520 processor.
+ Patch by Art Shipkowski, 12 May 2005
+
+* Add support for AP1000 board.
+ Patch by James MacAulay, 07 Oct 2005
+
+* Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200
+ Patch by Anders Larsen, 07 Oct 2005
+
+ The Atmel errata #11 states that the transfer buffer descriptor
+ table must be aligned on a 16-word boundary. As it turned out, this
+ is insufficient - it seems the table must be aligned on a boundary
+ at least as large as the table itself (in Linux this is not an
+ issue - the table is aligned on a PAGE_SIZE (4096) boundary).
+
+* Fixed compilation for ARM when using a (standard) hard-FP toolchain
+ Patch by Anders Larsen, 07 Oct 2005
+
+* Cleanup warnings for cpu/arm720t & cpu/arm1136 files.
+ sed the linker scripts, rather than pre-process them.
+ Patch by Peter Pearse, 07 Oct 2005
+
+* Update make target for ARM supported boards.
+ Use lowlevel_init() instead of platformsetup() [rename].
+ Patch by Peter Pearse, 06 Oct 2005
+
+* Fix booting from serial dataflash on AT91RM9200
+ Patch by Peter Menzebach, 29 Aug 2005
+
+* Add JFFS2 support for TRAB board
+ Patch by Martin Krause, 25 Aug 2005
+
+* Remove unnecessary dependency of netconsole on CONFIG_NET_MULTI
+ Patch by Marcus Hall, 24 Aug 2005
+
+* Fix the machine-id of the Cogent csb637 board
+ Patch by Anders Larsen, 05 Oct 2005
+
+* Complete support for the KwikByte KB920x boards
+ Patch by Anders Larsen, 05 Oct 2005
+
+* Set the AT91RM9200 clock to asynchronous mode
+ Patch by Anders Larsen, 03 May 2005
+
+* Set the AT91RM9200 clock to synchronous mode
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Add support for Cogent csb637
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Fix dm9161.c initialization
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005
+ (8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5)
+
+* Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200
+ Patch by Anders Larsen, 29 Apr 2005
+
+* Fix device partition intialization for SystemACE disks.
+ Patch by Stephen Williams, 28 Apr 2005
+
+* Added support for KwikByte KB920x boards (based on AT91RM9200)
+ Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005
+
+* Add support for S29GL064M-R3 flash chip on xsengine board
+ Patch by Kurt Stremerch, 18 Apr 2005
+
+* E500 update: repoint IVPR to RAM when code is relocated
+ Patch by Kylo Ginsberg, 13 Apr 2005
+
+* Fix loop end test in lib_generic/string.c:strswab()
+ Patch by Andrew Dyer, October 10, 2005
+ Signed-off-by: Andrew Dyer <amdyer@gmail.com>
+
+* Cleanup
+
+* Update ARM Integrator boards:
+ Correct addessing errors in platform files.
+ Split off common core module data from Integrator header files to
+ include/armcoremodule.h.
+ Patch by Peter Pearse, 04 Oct 2005
+
+* Make sure only supported compiler options are used
+ Import "cc-option" shell function from kernel and
+ use it to get the correct ARM GCC options for individual CPUs
+ Patch by Peter Pearse, 30 Jun 2005
+
+* Fix 440GR to print correct cpu revision
+ Patch by Stefan Roese, 04 Oct 2005
+
+* Change board message on AMCC Yosemite & Yellowstone to common style
+ Patch by Stefan Roese, 03 Oct 2005
+
+* Fix compiler warning
+
+* Fix FEC PHY addresses for TQM85xx boards
+
+* Fix uninitialized variable problem in hush shell
+ Patch by Lars Rostock, 26 Sep 2005
+
+* Undo change of f6e20fc6ca... to include/configs/trab.h
+ (Must have been an accident?)
+
+* Add support for AT91RM9200 OHCI Controller.
+ Patch by Eric Benard, 07 Apr 2005
+
+* Update ARM mach-types.h
+ Patch by Eric Benard, 07 Apr 2005
+
+* Add support for MP2USB board.
+ Patch by Eric Benard, 07 Apr 2005
+
+* Add board support for armadillo HT1070
+ Patch by Rowel Atienza, 06 Apr 2005
+
+* Second Ethernet address enabled for MPC885ADS and MPC8272ADS.
+ Patch by Vitaly Bordug, 30 Mar 2005
+
+* Add iopset command on mpc8xx
+ Patch by Daniel Eisenhut, 25 Mar 2005
+
+* Add support for MII in eepro100 driver.
+ Patch by Gleb Natapov, 21 Mar 2005
+
+* Fixes to the Lubbock (PXA 25x) support:
+ - Resolve the FIXME with respect to saving the u-boot environment.
+ - Make the default load address land in real memory.
+ - Fix lan91c96 SMC_{in,out}{b,w,l}() macros
+ Patch by David Brownell, 10 Mar 2005
+
+* Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board
+ Patch by Marc Leeman, 04 Mar 2005
+
+* OMAP242x H4 board update
+ - fix for ES2 differences.
+ - switch to using the cfi_flash driver.
+ - fix SRAM build address.
+ - fix for GP device operation.
+ - unlock SRAM for GP devices.
+ - display more device information.
+ - fix potential deadlock in omap24xx_i2c driver.
+ - fix DLL load values to match dpllout*1 operation.
+ - fix 2nd chip select init for combo DDR device.
+ - add support for CFI Intel 28F256L18 on H4 board.
+ Patch by Richard Woodruff, 03 Mar 2005
+
+* Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h
+ Patch by Steven Scholz, 02 Mar 2005
+
+* Fix typo in eth.c
+ Patch by Ara Avanesyan, 24 Feb 2005
+
+* Remove unneeded #include <malloc.h>
+ Patch by Ladislav Michl, 22 Feb 2005
+
+* Add cramfs support for m68k
+ Patch by Zachary Landau, 21 Feb 2005
+
+* Update ep8260: Fix flash timeouts; improve clock resolution for faster UARTs
+ Patch by Jeff Angielski, 21 Feb 2005
+
+* Fix au1x00_serial baud rate calculation:
+ remove hardcoded cpu clock divisor and use register instead;
+ round up instead of truncate
+ Patch by Andrew Dyer, 15 Feb 2005
+
+* Add Xilinx Spartan3 family FPGA support
+ Patch by Kurt Stremerch, 14 Feb 2005
+
+* Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET
+ Patch by Zachary Landau, 11 Feb 2005
+
+* Fix VOH405 Support
+ Patch by Matthias Fuchs, 25 Sep 2005
+
+* Added support for PCI bridge on MPC8272ADS
+ Patch by Vitaly Bordug, Feb 09 2005
+
+* Update multicore CM9XX support for Integrator AP to allow booting from flash
+ Patch by Jean-Paul Saman, 8 Feb 2005
+
+* Fix strswab() to reliably find end of string
+ Patch by Andrew Dyer, 08 Feb 2005
+
+* Fix typos in include/ppc440.h
+ Patch by Andrew E Mileski, 04 Feb 2005
+
+* Add Vibren (was Accelent) PXA255 IDP Support
+ Patch by Cliff Brake, 04 Feb 2005
+
+* Fix tools/bmp_logo.c using incorrect offset to pixel data
+ Patch by Andrew Dyer, 31 Jan 2005
+
+* Add ARM946E cpu and core module targets; remap memory to 0x00000000
+ Patch by Peter Pearse, 2 Feb 2005
+
+* Fix error handling in tools/env/fw_env.c
+ Patch by Ara Avanesyan, 01 Feb 2005
+
+* Fix MGT5100 PSC baudrate calculation
+ Patch by Sebastian Schau, 27 Jan 2005
+
+* OMAP242x fix for GP device booting
+ - Add SRAM unlock for GP devices.
+ - Change DDR DLL unlock value to allow DPLLout*1 operation.
+ Patches by Richard Woodruff, 21 Jan 2005:
+
+* Add support for AMD's Pb1x00 eval board;
+ add MII routines to the au1x00 ethernet driver;
+ add USB ohci driver (work in progress)
+ Patch by Thomas Sailer, 20 Jan 2005
+
+* Update omap5912osk board
+ Use drivers/cfi_flash.c instead of private flash driver;
+ Remove hardcoded personalized settings from omap5912osk.h;
+ Fix spacing with (RO) marks in 'flinfo' output.
+ Patch by Michael Bendzick, 14 Jan 2005
+
+* Fix warnings for PCI code on ixp
+ Patch by Joe <lgxue@yahoo.com>, 13 Jan 2005
+
+* virtex2 fix for bogus download error messages
+ The virtex2 FPGA download code watches for init going active during
+ a download of config data as an error condition. init also goes
+ active after a configuration is finished in concert with the done
+ signal. So far, the code does not check for done active until all
+ of the configuration data is sent. If configuration data has a few
+ extra pad bytes at the end, this would cause an error message even
+ though the download had suceeded.
+ NOTE: virtex2 slave serial and spartan2 versions may still have the
+ same problem.
+ Patch by Andrew Dyer, 12 Jan 2005
+
+* Optimize flash_make_cmd in drivers/cfi_flash.c for little endian
+ Fix "WARNING: flash_make_cmd: unsuppported LittleEndian mode"
+ message when probing for nonexistent flash in little endian mode.
+ As a side effect more efficient and smaller code is generated,
+ which is always a Good Thing (TM).
+ Patch by Ladislav Michl, 24 Sep 2005
+
+* Update for TFTP using a fixed UDP port
+ Use the approved environment variable names. Added "tftpdstp" to
+ allow ports other than 69 per Tolunay Orkun's recommendation.
+ Patch by Jerry Van Baren, 12 Jan 2005
+
+* Allow to force TFTP to use a fixed UDP port
+ (Add a configuration option CONFIG_TFTP_PORT and optional env
+ variable tftpport)
+ Patch by Jerry Van Baren, 10 Jan 2005
+
+* Fix ethernet timeouts on dbau1550 and other au1x00 systems
+ Patch by Leif Lindholm, 29 Dec 2004
+
+* Cleanup: fix broken builds
+
+* Fix PHY address argument passing with mii info command
+ Patch by Andrew Dyer, 28 Dec 2004
+
+* Cleanup (PPC4xx is AMCC now)
+
+* esd CPCI2DP board added
+ Patch by Matthias Fuchs, 22 Sep 2005
+
+* esd PMC405 board updated
+ Patch by Matthias Fuchs, 22 Sep 2005
+
+* Add SM501 support to HH405 board.
+ Add support for gzip compressed bmp's (CONFIG_VIDEO_BMP_GZIP).
+ Add support for eeprom write-enable (CFG_EEPROM_WREN).
+ Patch by Stefan Roese, 22 Sep 2005
+
+* Fix autonegotiation in tsec ethernet driver
+ Patch by Stefan Roese, 21 Sep 2005
+
+* Fix bug in auto_update (trab board)
+ Patch by Martin Krause, 16 Sep 2005
+
+* Fix computation of framebuffer palette for 8bpp LCD bitmaps
+ Patch by Francesco Mandracci, 16 Sep 2005
+
+* Update configuration for INKA4x0 board
+
+* Update configuration for PM854 board
+ Based on patch by R. Loeffl, 20 Jul 2005
+
+* Add PCI support to TQM8540 and TQM8560 boards
+ Patch by Stefan Roese, 15 Sep 2005
+
+* Update AMCC Yosemite to get a consistent setup for all AMCC eval
+ boards (baudrate, environment...). Flash driver fixed.
+ Patch by Stefan Roese, 15 Sep 2005
+
+* Fix problem in 440GP ethernet driver (ebony). Add support for 2nd
+ ethernet port on ebony.
+ Patch by Stefan Roese, 7 Sep 2005
+
+* Added support for mtddevnum and mtddevname variables (mtdparts command)
+
+* Change default console baud rate for stxxtc board
+
+* Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT).
+ Patch by Stefan Roese, 31 Aug 2005
+
+* Fix default command set (don't include CFG_CMD_DISPLAY command)
+ Patch by Pantelis Antoniou, 02 Sep 2005
+
+* Cleanup
+
+* Enable SM712 driver support for HMI1001 board.
+
+* Fix problems with ld version 2.16 (dot outside sections problem)
+ Pointed out by Gerhard Jaeger, 31 Aug 2005;
+ cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html
+
+* Prepare U-Boot for gcc-4.x: fix global data pointer initialization
+
+* Adjust CS3 timings on HMI1001 board for dot matrix display under Linux
+
+* Add keyboard and dot matrix display support for HMI1001 board.
+
+* Prepare U-Boot for gcc-4.x
+
+* Fixed Bamboo port to enable running without DDR-DIMM
+ (Bamboo has also 64MB onboard DDR)
+ Patch by Stefan Roese, 24 Aug 2005
+
+* Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
+ now handling all 4xx cpu's
+ Patch by Stefan Roese, 16 Aug 2005
+
+* Fix make dependencies for at91rm9200 and ks8695 cpus
+ Patch by Steven Scholz, 23 Aug 2005
+
+* Add JFFS2 support for TQM5200 board
+
+* Add esd cpci5200 and pf5200 boards
+ Patch by Reinhard Arlt, 22 Aug 2005
+
+* Fix sysclock for TQM8540 and TQM8560 boards
+ Patch by Martin Krause, 25 Jul 2005
+
+* Initialize serial# and ethaddr from manufacturer data in EEPROM on CMC-PU2
+ Patch by Martin Krause, 08 Jun 2005
+
+* Add new board specific commands for TQM5200/STK52XX
+ - Sound commands (beep, wav, sound)
+ - Test commands (led, can, backlight, rs232)
+ Patch by Martin Krause, 02 May 2005
+
+* Change main clock on CMC-PU2 board from 207 MHz to 179 MHz
+ because of a bug in the AT91RM9200 CPU PLL
+ Patch by Martin Krause, 22 Apr 2005
+
+* Add automatic HW detection for another CMC_PU2 variant
+ Patch by Martin Krause, 20 Apr 2005
+
+* Remove CONFIG_AT91RM9200DK in CMC-PU2 configuration
+ Patch by Martin Krause, 19 Apr 2005
+
+* Fix initialization problem on TQM5200 without SM501
+ Patch by Martin Krause, 08 Apr 2005
+
+* Add RTC support for STK52XX.200
+ Patch by Martin Krause, 07 Apr 2005
+
+* Add support for IFM o2dnt board
+
+* Enable PCI on hmi1001 board
+
+* Fix return values of the jffs2 commands ls/fsload/fsinfo,
+ so we can use them to, e.g., check the existence of a file with
+ "if ls foo; then this; else that; fi" in the hush shell
+ Patch by Andreas Engel, 16 August 2005
+
+* Coding style cleanup
+
+* Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board.
+ Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005
+
+* Check return value of malloc in 440gx_enet.c
+ Patch by Travis B. Sawyer, 18 Jul 2005
+
+* Add Sandburst Metrobox and Sandburst Karef board support packages.
+ Second serial port on 440GX now defined as a system device.
+ Add 'Short Etch' code for Cicada PHY within 440gx_enet.c
+ Patch by Travis B. Sawyer, 12 Jul 2005
+
+======================================================================
+Changes for U-Boot 1.1.3:
+======================================================================
+
+* Minor code cleanup
+
+* Add forgotten new fils from latest VoiceBlue update
+
+* Make bootretry feature work with hush shell.
+ Caveat: this currently *requires* CONFIG_RESET_TO_RETRY to be set, too.
+ Patch by Andreas Engel, 19 Jul 2005
+
+* Update Hymod Board Database PHP code in "tools" directory
+ Patch by Murray Jensen, 01 Jul 2005
+
+* Make "tr" command use POSIX compliant; export HOSTOS make variable
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Fix Murray Jensen's mail address.
+ Patch by Murray Jensen, 30 Jun 2005
+
+* Preserve PHY_BMCR during a soft reset.
+ Patch by Carl Riechers, 24 Jun 2005
+
+* VoiceBlue update: eeprom tool can also store firmware version now.
+ eeprom.bin is runable by jumping at load address.
+ Patch by Ladislav Michl, 23 May 2005
+
+* Move the AT91RM9200DK to the ARM Systems list.
+ Patch by Anders Larsen, 26 Apr 2005
+
+* Eliminate calls of ARM libgcc.a helper functions _divsi3 and _modsi3
+ Patch by Anders Larsen, 26 Apr 2005
+
+* measure_gclk() is needed when DEBUG is enabled
+ Patch by Bryan O'Donoghue, 25 Apr 2005
+
+* Add UPD-Checksum code, fix problem in net.c (return instead of break)
+ Patch by Reinhard Arlt, 12 Aug 2005
+
+* esd PCI405 board updated
+ Patch by Matthias Fuchs, 28 Jul 2005
+
+* esd WUH405 and DU405 board updated
+ Patch by Matthias Fuchs, 27 Jul 2005
+
+* Fix problem in cmd_nand.c (only when defined CFG_NAND_SKIP_BAD_DOT_I)
+ Patch by Matthias Fuchs, 4 May 2005
+
+* Update AMCC Yosemite to get a consistent setup for all AMCC eval
+ boards (baudrate, environment...). Flash driver fixed.
+ Patch by Stefan Roese, 11 Aug 2005
+
+* Changed AMCC Bubinga (405EP) configuration to support 2nd eth port
+ Patch by Stefan Roese, 11 Aug 2005
+
+* Add NAND FLASH support for AMCC Bamboo 440EP eval board
+ Patch by Stefan Roese, 11 Aug 2005
+
+* Add configuration for IFM AEV FIFO board.
+ Minor coding style cleanup.
+
+* Add configuration for IFM SPI eval board
+
+* Fix CompactFlash problem on HMI1001 board
+
+* Make new "mtdparts" code build with older compilers
+ Patch by Andrea Scian, 09 Aug 2005
+
+* Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to
+ CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design
+ with the 405 defines and the linux kernel defines.
+ Patch by Stefan Roese, 08 Aug 2005
+
+* Fix compiler warnings with older GCC versions
+
+* Add common (with Linux) MTD partition scheme and "mtdparts" command
+
+ Old, obsolete and duplicated code was cleaned up and replace by the
+ new partitioning method. There are two possible approaches now:
+
+ The first one is to define a single, static partition:
+
+ #undef CONFIG_JFFS2_CMDLINE
+ #define CONFIG_JFFS2_DEV "nor0"
+ #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */
+ #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */
+ #define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+ The second method uses the mtdparts command line option and dynamic
+ partitioning:
+
+ /* mtdparts command line support */
+ #define CONFIG_JFFS2_CMDLINE
+ #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2"
+ #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
+
+ Command line of course produces bigger images, and may be inappropriate
+ for some targets, so by default it's off.
+
+* Fix build problems for PM856 Board
+
+* Fix sign extension bug in 'fpga loadb' command;
+ make 'fpga loadb' always print the file header info
+ Patch by Andrew Dyer, 11 Jan 2005
+
+* Fix errors that occur when accessing SystemACE CF
+ Patch by Jeff Angielski, 09 Jan 2005
+
+* Document switching between U-Boot and PlanetCore on RPXlite
+ by Sam Song, 24 Dec 2004
+
+* Fix PowerQUICC II mask detection.
+ Patch by Eugene Surovegin, 20 Dec 2004
+
+* Add support for Altera NIOS DK1C20 board
+ Patch by Shlomo Kut, 13 Dec 2004
+
+* Add support for ep8248 board
+ Patch by Yuli Barcohen, 12 Dec 2004
+
+ Minor code cleanup.
+
+* Fix baudrate setting for KGDB on MPC8260
+ Patch by HoJin, 11 Dec 2004
+
+* Fix 'mii help' text formatting
+ Patch by Cory Tusar, 10 Dec 2004
+
+* Fix return code of NFS command
+ Patch by Hiroshi Ito, 11 Dec 2004
+
+* Fix typo
+
+* Fix compiler warnings in cpu/ppc4xx/usbdev.c
+ Patch by Steven Blakeslee, 04 Aug 2005
+
+* Add support for AMCC Bamboo PPC440EP eval board
+ Patch by Stefan Roese, 04 Aug 2005
+
+* Patch by Jon Loeliger
+ Fix style issues primarily in 85xx and 83xx boards.
+ - C++ comments
+ - Trailing white space
+ - Indentation not by TAB
+ - Excessive amount of empty lines
+ - Trailing empty lines
+
+* Patch by Ron Alder, 11 Jul 2005
+ Add Xianghua Xiao and Lunsheng Wang's support for the
+ GDA MPC8540 EVAL board.
+
+* Patch by Eran Liberty
+ Add support for the Freescale MPC8349ADS board.
+
+* Patch by Jon Loeliger, 25 Jul 2005
+ Move the TSEC driver out of cpu/mpc85xx as it will be shared
+ by the upcoming mpc83xx family as well.
+
+* Patch by Jon Loeliger, 05 May 2005
+ Implemented support for MPC8548CDS board.
+ Added DDR II support based on SPD values for MPC85xx boards.
+ This roll-up patch also includes bugfies for the previously
+ published patches:
+ DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
+
+* Patch by Jon Loeliger, 10 Feb 2005
+ Add config option CONFIG_HAS_FEC calling out 8540 FEC features.
+
+* Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005
+ For MPC85xxCDS:
+ Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow
+ for faster flash parts.
+ Add documentation for BR/OR for FLASH.
+
+* Patch by Jon Loeliger 08 Feb 2005
+ Determine L2 Cache size dynamically on 85XX boards.
+
+* Patch by Jon Loeliger, Kumar Gala 08 Feb 2005
+ - Convert the CPM2 based functionality to use new CONFIG_CPM2
+ option rather than a myriad of CONFIG_MPC8560-like variants.
+ Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
+ Eliminates the CONFIG_MPC8560 option entirely. Distributes the
+ new CONFIG_CPM2 option to each 8260 board.
+
+* Add support for MicroSys PM856 board
+ Patch by Josef Wagner, 03 Aug 2005
+
+* Minor fixes to PM854 board
+ Patch by Josef Wagner, 03 Aug 2005
+
+* Adjust configuration of XENIAX board
+ (chip select and GPIO required for USB operation)
+
+* Fix typos in cpu/85xx/start.S which caused DataTLB exception to be
+ routed to the Watchdog handler
+ Patch by Eugene Surovegin, 18 Jun 2005
+
+* (re)enabled scsi commands do_scsi() and do_scsiboot()
+ Patch by Denis Peter, 06 Dec 2004
+
+* Fix endianess problem in TFTP / NFS default filenames
+ Patch by Hiroshi Ito, 06 Dec 2004
+
+* Ignore broadcast status bit in received frames in 8260 FCC ethernet
+ loopback test code
+ Patch by Murray Jensen, 18 Jul 2005
+
+* Fix typo in mkconfig script (used == instead of =)
+ Patch by Murray Jensen, 18 Jul 2005
+
+* Cleanup build problems on 64 bit build hosts
+
+* Update MAINTAINERS file
+
+* Patch by Stefan Roese, 01 Aug 2005:
+ - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea
+ (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup"
+ for details.
+ - Sycamore (PPC405GPr) eval board added (Walnut port is extended
+ to run on both 405GP and 405GPr eval boards).
+
+* Patch by Steven Blakeslee, 27 Jul 2005:
+ - Add support for AMCC PPC440EP/GR.
+ - Add support for AMCC Yosemite PPC440EP eval board.
+ - Add support for AMCC Yellowstone PPC440GR eval board.
+
+* Minor fixes for PPChameleon Board:
+ - fix alignment of NAND size
+ - make code do what the comment says
+
+* Implement h/w sector protection status synchronization at boot.
+ The code is provided for, and was tested on, the Yukon/Alaska
+ and PM520 boards only.
+
+ A bug in flash_real_protect() for the Yukon board was fixed by
+ adding a function that tells if two banks are on one flash chip.
+
+* Fix sysmon POST problem: check I2C error codes
+ This fixes a problem of displaying bogus voltages when the voltages
+ are so low that the I2C devices start failing while the rest of the
+ system keeps running.
+
+* Patch by Cedric Vincent, 6 Jul 2005:
+ Fix CFG_CMD_SETGETDCR handling in "common/cmd_dcr.c"
+
+* Patch by Jon Loeliger, 20 Jul 2005:
+ Add missing PCI IO port definitions.
+
+* Add CompactFlash support for HMI1001 board.
+
+* Adjust printed board ID for LWMON board.
+
+* Fix low-level OHCI transfers for ARM920t and MPC5xxx
+
+* Add new argument format for flash commands to allow for usage like
+ "erase $(addr) +$(filesize)", i. e. a size argument can be used and
+ U-Boot will automaticially find the end of the corresponding sector.
+
+* Patch by Stefan Roese, 5 Jul 2005:
+ Update uc100 board PHY setup
+
+* Patch by Stefan Roese, 1 Jul 2005:
+ Fix PHY address for CATcenter board (now correct!)
+
+* Patch by Stefan Roese, 30 Jun 2005:
+ Fix PHY addresses for PPChameleon and CATcenter boards
+ Change MAINTAINER for most esd boards
+
+* Patch by Detlev Zundel, 30 Jun 2005:
+ Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code
+
+* Fix baudrate calculation problem on MPC5200 systems
+
+* Add EEPROM and RTC support for HMI1001 board
+
+* Patch by Detlev Zundel, 20 Jun 2005:
+ Fix initialization of low active GPIO pins on inka4x0 board
+
+* Enable redundant environment, disable HW flash protection of
+ HMI1001 board
+
+* Patch by Travis Sawyer, 10 Jun 2005:
+ Initialize allocated dev and private hw structures
+ after their respective allocation in 440gx_enet.c
+
+* Patch by Steven Scholz, 10 Jun 2005:
+ Fix byteorder problems with second argument of "bootm" with
+ standalone images;
+
+* Add support for HMI1001 board
+
+* Disable "date" and "sntp" commands on TQM866M
+
+* Fix watchdog reset problems on LWMON board
+
+* Patch by Juergen Selent, 17 May 2005:
+ Add support for Funkwerk VoVPN gateway module.
+
+* Cleanup debug code for MPC8220 FEC driver
+
+* Extend burst mode RAM test program to take a loop count
+ (0 = infinite)
+
+* Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on
+ those boards that use it.
+
+* Patches by Greg Ungerer, 19 May 2005:
+ - add support for the KS8695P (ARM 922 based) CPU
+ - add support for the OpenGear CM4008, CM4116 and CM4148 boards
+
+* Patch by Steven Scholz, 19 May 2005:
+ Add support for CONFIG_SERIAL_TAG on ARM boards
+
+* Add PCI support for Sorcery board.
+ Code cleanup (especially Sorcery / Alaska / Yukon serial driver).
+
+* Fix compile problems caused by new burst mode SDRAM test;
+ make port pins to trigger logic analyzer configurable
+
+* Fix timer handling on MPC85xx systems
+
+* Fix debug code in omap5912osk flash driver
+
+* Add support for MPC8247 based "IDS8247" board.
+
+* Add support for 2 x TSEC interfaces on the TQM8540 board.
+
+* On LWMON we must use the watchdog to reset the board as the CPU
+ genereated HRESET pulse is too short to reset the external
+ circuitry.
+
+* Add test tool to exercise SDRAM accesses in burst mode
+ (as standalone program, MPC8xx/PowerPC only)
+
+* Increase CFG_MONITOR_LEN for Rattler board to match actual code
+ size.
+
+* Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of
+ March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI
+ added to support LZO and LZARI compression modes (undefined by
+ default).
+
+* Fix problem with symbolic links in JFFS2 code.
+
+* Use linker ASSERT statement to prevent undetected overlapping of
+ sections on PPChameleon board; other boards might use this, too.
+
+* Patch by Stefan Roese, 03 May 2005:
+ Update for P3G4
+ Fix problems in cmd_universe.c
+
+* Patch by Matthias Fuchs, 03 May 2005:
+ Added missing variable declaration in cmd_nand.c
+ Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram
+
+* Fix INKA4x0: use CS1 as gpio_wkup_6 output
+
+* Fix bug in the SDRAM initialization code for canmb, IceCube and
+ PM520 boards.
+ Fix PHY address for canmb board.
+
+* Cleanup serial console baudrate calculation on AT91RM9200;
+ get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition
+
+* Patch by Matthias Fuchs, 18 Apr 2005:
+ Make PCI target address spaces on PMC405 and CPCI405 boards
+ configurable via environment variables
+
+* Auto-size RAM on canmb board.
+
+* Add support for canmb board
+
+* Patch by Stefan Roese, 13 Apr 2005:
+ Update for esd apc405
+
+* Fixes for TQM8560 board:
+ - fix clock rates
+ - remove debug messages
+ - fix flash sector protection
+
+* Patch by Steven Scholz, 07 Apr 2005:
+ Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C
+
+* Patches by Steven Scholz, 07 Apr 2005:
+ Fix compiler warning in altera.c
+ Fix warning in cpu/arm920t/at91rm9200/i2c.c
+
+* Patch by Ladislav Michl, 06 Apr 2005:
+ Fix voiceblue configuration.
+
+* Patch by Stefan Roese, 06 Apr 2005:
+ Updates for OCOTEA board:
+ - Changed U-Boot size from 512kByte to 256kByte
+ - Fixed flash driver to support boot from soldered user flash
+ - Added README for switch from PIBS firmware to U-Boot
+
+* Patch by Travis Sawyer, 05 Apr 2005:
+ - Change timer frequency for ppc 440 from 10 ms to 1 ms.
+ Problem found by Andrew Wozniak.
+
+* Patch by Steven Scholz, 06 Apr 2005:
+ - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
+ - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
+
+* Patches by Robert Whaley, 29 Nov 2004:
+ - update the pxa-regs.h file for PXA27x chips
+ - add PXA27x based ADSVIX board
+ - add support for MMC on PXA27x processors
+
+* Patch by Andrew E. Mileski, 28 Nov 2004:
+ Fix PPC4xx SPD SDRAM detection bug
+
+* Patch by Hiroshi Ito, 26 Nov 2004:
+ Fix logic of "test -z" and "test -n" commands
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+ Add support for VoiceBlue board.
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+ Fix netboot_common() prototypes.
+
+* Patch by Steven Scholz, 05 Apr 2005:
+ Use i.MX watchdog timer for reset_cpu()
+
+* Patch by Steven Scholz, 05 Apr 2005:
+ Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific
+ subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/
+ (now in interupts.c)
+
+* Add support for MPC8220 based "sorcery" board.
+
+* Add support for TQM8560 board.
+
+* Add FEC support for TQM8540 board.
+ Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC
+
+* Patch by Martin Krause, 04 Apr 2005:
+ Update default configuration for CMC_PU2 board.
+
+* Patch by Steven Scholz, 04 Apr 2005:
+ - remove all references to CONFIG_INIT_CRITICAL for ARM based boards
+ - introduce two new configuration options instead:
+ CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT
+
+* Patch by Steven Scholz, 04 Apr 2005:
+ Make sure that MDIO clock does not exceed 2.5 MHz on AT91
+
+* Fix timer code for ARM systems: make sure that udelay() does not
+ reset timers so it's save to use udelay() in timeout code.
+
+* Patch by Mathias Küster, 23 Nov 2004:
+ add udelay support for the mcf5282 cpu
+
+* Patch by Tolunay Orkun, 16 November 2004:
+ fix incorrect onboard Xilinx CPLD base address
+
+* Patch by Jerry Van Baren, 08 Nov 2004:
+ - Add low-boot option for MPC8260ADS board (if lowboot is selected,
+ the jumper for the HRCW source should select flash. If lowboot is
+ not selected, the jumper for the HRCW source should select the
+ BCSR.
+ - change default load base address to 0x00400000
+
+* Patch by Yuli Barcohen, 08 Nov 2004:
+ Add support for Analogue & Micro Rattler boards.
+ Tested on Rattler8248.
+
+* Patch by Andre Renaud, 08 Nov 2004:
+ Fix watchdog support in common/lcd.c
+
+* Patch by Marc Leeman, 05 Nov 2003:
+ Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU
+ bug only affects the XPC8245 processors
+
+* Patches by Josef Wagner, 29 Oct 2004:
+ - Add support for MicroSys CPU87 board
+ - Add support for MicroSys PM854 board
+
+* Patch by Jian Zhang, 02 Nov 2004:
+ Add 16-bit NAND support
+
+* Patch by Scott McNutt, 01 Nov 2004:
+ Add missing NIOS/NIOS2 support for "iminfo" command
+
+* Patch by Detlev Zundel, 29 Oct 2004:
+ Add missing NIOS/NIOS2 support for "mkimage" tool.
+
+* Patch by David Adair, 27 Oct 2004:
+ Add missing 440GX SDRAM Controller reset
+
+* Patch by Steven Scholz, 25 Oct 2004:
+ Declare reset_cpu() in include/common.h instead locally
+
+* Patch by Yusdi Santoso, 22 Oct 2004:
+ - Add support for HIDDEN_DRAGON board
+ - fix endianess problem in driver/rtl1839.c
+
+* Patch by Allen Curtis, 21 Oct 2004:
+ support multiple serial ports
+
+* Patch by Richard Klingler, 03 Apr 2005:
+ Add call to eth_halt() in net/net.c when called functions fail
+ after eth_init() has been called.
+
+* Patch by Sam Song, 3 April 2005:
+ - Update README.Netconsole
+ - Update README
+
+* Prepare for SoC rework of ARM code:
+ - rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL
+ - rename memsetup into lowlevel_init (function name and source files)
+ Patch by Steven Scholz, 03 Apr 2005:
+ - create SoC specific directories include/asm-arm/arch-imx and
+ include/asm-arm/arch-s3c24x0
+
+* Fix problems with SNTP support;
+ enable SNTP support in some boards.
+
+* Patches by Martin Krause, 01 Apr 2005:
+ - Fix flash erase timeout on CMC_PU2
+ - Add automatic HW detection for CMC_PU2 and CMC_BASIC
+
+* Patch by Steven Scholz, 13 March 2005:
+ fix cache enabling for AT91RM9200
+
+* Patch by Masami Komiya, 30 Mar 2005:
+ add SNTP support and expand time server and time offset fields of
+ DHCP support. See doc/README.SNTP
+
+* Patch by Steven Scholz, 13 Dec 2004:
+ Fix bug in at91rm920 ethernet driver
+
+* Patch by Steven Scholz, 13 Dec 2004:
+ Remove duplicated code by merging memsetup.S files for
+ at91rm9200 boards into one cpu/at91rm9200/lowlevel.S
+
+* Patch by Detlev Zundel, 31 Mar 2005:
+ Cleanup duplicate definition of overwrite_console()
+
+* Update TQM5200 configuration;
+ prepare for Rev. 200 starter kit boards
+
+* Patch by Scott McNutt, 21 Oct 2004:
+ Add support for Nios-II EPCS Controller core.
+
+* Patch by Scott McNutt, 20 Oct 2004:
+ Nios-II cleanups:
+ - Add sysid command (Nios-II only).
+ - Locate default exception trampoline at proper offset.
+ - Implement I/O routines (readb, writeb, etc)
+ - Implement do_bootm_linux
+
+* Patches by Martin Krause, 22 Mar 2005:
+ - use TQM5200_auto as MAKEALL target for TQM5200 systems
+ - add support for SM501 graphics controller
+ - add support for graphic console on TQM5200
+ - add support for TQM5200 Rev 200
+ - cleanup, fix typo in include/configs/TQM5200.h
+
+* Patch by Manfred Baral, 17 Mar 2005:
+ Fix typo
+
+* Fix RTC configuration for PPChameleon board
+
+* Cleanup, fix typo in include/configs/TQM5200.h
+
+* Patch by Stefan Roese, 16 Mar 2005:
+ Update for esd auto_update and hh405 board
+
+* Adapt for U-Boot image size (new features enabled) on TQM5200
+
+* Update code for TQM8540 board (and 85xx in general):
+ - Change the name of the Ethernet driver: MOTO ENET -> ENET
+ - Reformat boot messages
+ - Enable redundant environment
+ - Replace the -O2 optimization flag with -mno-string
+
+* Patch by David Brownell, 10 Mar 2005:
+ Restore copyright statements in OHCI drivers.
+
+* Add support for TQM8540 board
+
+* Patch by Detlev Zundel, 14 Mar 2005:
+ NC650: changed NAND flash addressing to using UPMB
+
+* Patch by Stefan Roese, 14 Mar 2005:
+ Update for esd voh405 fpga image
+
+* INKA4x0: Allow initialization of LCD backlight dimming from
+ "brightness" environment variable.
+
+* Add port initialization for digital I/O on INKA4x0
+
+* Patch by Stefan Roese, 01 Mar 2005:
+ Update for esd boards dp405 and hub405
+
+* Fix get_partition_info() parameter error in all other calls
+ (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c).
+
+* Enable USB and IDE support for INKA4x0 board
+
+* Patch by Andrew Dyer, 28 Feb 2005:
+ fix ext2load passing an incorrect pointer to get_partition_info()
+ resulting in load failure for devices other than 0
+
+* Add support for SRAM and 2 x Quad UARTs on INKA4x0 board
+
+* Cleanup USB and partition defines
+
+* Add support for ext2 filesystems and image timestamps to TQM5200 board
+
+* Add reset code for Coral-P on INKA4x0 board
+
+* Patch by Martin Krause, 28 Jun 2004:
+ Update for TRAB board.
+
+* Fix some missing "volatile"s in MPC5xxx FEC driver
+
+* Fix cirrus voltage detection (for CPC45)
+
+* Fix byteorder problem in usbboot and scsiboot commands.
+
+* Patch by Cajus Hahn, 04 Feb 2005:
+ - don't insist on leading '/' for filename in ext2load
+ - set default partition to useful value (1) in ext2load
+
+* Patch by Andrew Dyer, 08 Jan 2005:
+ fix wrong return codes in ext2 code
+
+* Removed '--no-warn-mismatch' option from Makefile. This option
+ makes 'ld' to overlook binary objects compatibility.
+
+* Moved $(PLATFORM_LIBS) from the library group (--start-group ...
+ --end-group) outside of the group. This will make 'ld' to do
+ _multiple_ search in the library group when resolving symbol
+ references and do only a _single_ seach in libgcc.a after the group
+ search.
+
+* Fix stability problems on CPC45 board again.
+
+* Make image detection for diskboot / usbboot / scsiboot more robust
+ (also check header checksum)
+
+* Update CPC45 board configuration.
+
+* Add USB and PCI support for INKA4x0 board
+
+* Fix IDE stability problems on CPC45 board (needs 2 x EIEIO).
+
+* Code cleanup
+
+* Patch by Robin Getz, 13 Oct 2004:
+ Add standalone application to change SMC91C111 MAC addresses,
+ see examples/README.smc91111_eeprom
+
+* Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004:
+ Fix Flash support for ARM Integrator CP.
+
+* Patch by Richard Woodruff, 10 Jan 2005:
+ Update support for OMAP2420 (ARM11) and H4 board:
+ o clean up and add new types to H4 memory probe code.
+ o fix to work with internal boot.
+ o added PRCM config III operation.
+ o fix marginal flash timings.
+ o add revison ATAG usage.
+ o enable voltage scaling at power chip.
+ o fix compile error for i2c.
+
+* Fix network problem (error when receiving multiple ARP packets)
+
+* Patch by Daniel Poirot, 12 Oct 2004:
+ Add support for Wind River sbc405 board
+
+* Patch by Rainer Brestan, 12 Oct 2004:
+ Make examples/Makefile more robust
+
+* Patch by Sam Song, 11 October 2004:
+ - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board
+ - Adjust CPU:BUS frequency ratio 1:1 when core frequency
+ less than 50MHz
+
+* Patch by Sam Song, 10 Oct 2004:
+ Fix a parameter error in run_command() in main.c
+
+* Patch by Richard Woodruff, 01 Oct 2004:
+ add support for the TI OMAP2420 processor and its H4 reference
+ board
+
+* Patch by Christian Pellegrin, 24 Sep 2004:
+ Added support for NE2000 compatible (DP8390, DP83902) NICs.
+
+* Patch by Leif Lindholm, 23 Sep 2004:
+ add support for the AMD db1550 board
+
+* Patch by Travis Sawyer, 15 Sep 2004:
+ Add CONFIG_SERIAL_MULTI support for ppc4xx,
+ update README.serial_multi
+
+* Patches by David Snowdon, 07 Sep 2004:
+ - add u-boot.hex target in the top level Makefile
+ - add support for the UNSW/NICTA PLEB 2 board (pleb2)
+ - use -mtune=xscale and -march=armv5 options for PXA
+
+* Patch by Florian Schlote, 08 Sep 2004:
+ Add support for SenTec-COBRA5272-board (ColdFire).
+
+* Patch by Gleb Natapov, 07 Sep 2004:
+ mpc824x: set PCI latency timer to a sane value
+ (is 0 after reset).
+
+* Patch by Kurt Stremerch, 03 Sep 2004:
+ Add bitstream configuration option for fpga command (Xilinx only).
+
+* Patch by Kurt Stremerch, 03 Sep 2004:
+ Add Xilinx Spartan2E family FPGA support
+
+* Patch by Jeff Angielski, 02 Sep 2004:
+ Add Added support for H2 revision of the EP8260 board.
+ Fixed formatting for some of the EP8260 related source files.
+
+* Patch by Jon Loeliger, 02 Sep 2004:
+ Reset monitor size back to 256 so environment can be written
+ to flash on MPC85xx ADS and CDS releases.
+
+* Patch by Paolo Broggini, 02 Sep 2004:
+ Make BSS clearing on ARM systems more robust
+
+* Patch by Yue Hu and Joe, 01 Sep 2004:
+ - add PCI support for ixp425;
+ - add EEPRO100 suppor tfor ixdp425 board.
+
+* Fix problem with protected sector detection in driver/cfi_flash.c
+
+======================================================================
+Changes for U-Boot 1.1.2:
+======================================================================
+
+* Code cleanup, mostly for GCC-3.3.x
+
+* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to
+ pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for
+ additional ethernet addresses.
+
+* Cleanup drivers/i82365.c - avoid duplication of code
+
+* Fix bogus "cannot span across banks" flash error message
+
+* Code cleanup
+
+* Add support for CompactFlash for the CPC45 Board.
+
+* Fix problems with CMC_PU2 flash driver.
+
+* Cleanup:
+ - avoid trigraph warning in fs/ext2/ext2fs.c
+ - rename UC100 -> uc100
+
+* Add support for UC100 board
+
+* Patch by Stefan Roese, 16 Dez 2004:
+ - ext2fs support added
+ - Tundra universe support added
+ - ColdFire MCF5249 support added (no preloader needed!)
+ - MCF5249 board TASREG added
+ - PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405,
+ VOM405, WUH405
+ - some esd boards updated
+ - memory commands "mdc" and "mwc" added for cyclic read/write
+ (CONFIG_MX_CYCLIC, see README for further description)
+
+* Add support for INKA4X0 board
+
+* Patch by Steven Scholz, 12 Dec 2004:
+ Fix typo in AT91 memory setup.
+
+* Patch by Martin Krause, 27 Oct 2004:
+ - add support for "STK52xx" board (including PS/2 multiplexer)
+ - add hardware detection for TQM5200
+
+* Clean up CMC PU2 flash driver
+
+* Update MAINTAINERS file
+
+* Fix bug in MPC823 LCD driver
+
+* Fix udelay() on AT91RM9200 for delays < 1 ms.
+
+* Enable long help on CMC PU2 board;
+ fix reset issue;
+ increase CPU speed from 179 to 207 MHz.
+
+* Fix smc91111 ethernet driver for Xaeniax board (need to handle
+ unaligned tail part specially).
+
+* Update for AT91RM9200DK and CMC_PU2 boards:
+ - Enable booting directly from flash
+ - fix CMC_PU2 flash driver
+
+* Fix mkimage usage message
+
+* Map SRAM on NC650 board
+
+* Work around for Ethernet problems on Xaeniax board
+
+* Patch by TsiChung Liew, 23 Sep 2004:
+ - add support for MPC8220 CPU
+ - Add support for Alaska and Yukon boards
+
+* Fix configuration for ERIC board (needs more room)
+
+* Adjust MIPS compiler options at run-time depending on tools version
+ ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new,
+ "-mcpu=4kc" for old tools)
+
+* Add passing of the command line and memory size information to the
+ kernel on xaeniax board.
+
+* Enable NAND flash support for NC650 board.
+
+* Patch by Thomas Lange 07 Oct 2004:
+ Updated README for DBAu1x00 boards to match current status
+
+* Patch by Philippe Robin, 28 Sept 2004:
+ Fix Flash support for Versatile.
+
+* Patch by Roger Blofeld, 16 Sep 2004:
+ Fix timeout for DHCP command retry
+
+* Patch by Pantelis Antoniou, 14 Sep 2004:
+ Fix early serial hang when CONFIG_SERIAL_MULTI is defined.
+
+* Patch by Pantelis Antoniou, 14 Sep 2004:
+ Kick watchdog when bz-decompressing
+
+* Fix CFG_HZ problems on AT91RM9200 systems
+ [Remember: CFG_HZ should be 1000 on ALL systems!]
+
+* Patch by Gridish Shlomi, 30 Aug 2004:
+ - Add support to revA version of PQ27 and PQ27E.
+ - Reverted MPC8260ADS baudrate back to original 115200
+
+* Patch by Hojin, 17 Sep 2004:
+ Fix typo in cfi_flash.c
+
+* Patch by Mark Jonas, 09 September 2004:
+ mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong
+ error message
+
+* Patch by Mark Jonas, 31 August 2004:
+ Added option CFG_XLB_PIPELINING to enable XLB pipelining. This
+ improves FTP performance for MPC5200 systems. Enabled for IceCube
+ by default.
+
+* Patch by Michael Bendzick, 30 Aug 2004:
+ - Improve platform.S code for omap1510inn that detects whether code
+ is running from SDRAM or not. Patch allows SDRAM to be configured
+ if code is running out of SRAM at 0x20000000.
+
+* Patch by Frederick Klatt, 30 Aug 2004:
+ Add support for the Wind River SBC8540/SBC8560 boards
+
+* Configure SX1 board to use drivers/cfi_flash.c
+
+* Patches by Michael Bendzick, 30 Aug 2004:
+ - Configure omap1510inn board to use drivers/cfi_flash.c
+ - Make drivers/cfi_flash.c protect environment and redundant
+ environment.
+
+* Patch by Steven Scholz, 23 Jun 2004:
+ - Add script (tools/img2brec.sh) to programm U-Boot into
+ (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L
+
+* Patches by Scott McNutt, 24 Aug 2004:
+ - Add support for Altera Nios-II processors.
+ - Add support for Psyent PCI-5441 board.
+ - Add support for Psyent PK1C20 board.
+
+* Patches by Jon Loeliger, 24 Aug 2004:
+ - Add support for the MPC8541 and MPC8555 CDS boards
+ - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
+ - Convert MPC85xxADS to use common CFI flash driver
+ - Fix PCI window on MPC85xx; remove unneeded PCI initialization
+ from board_early_init_f()
+ - Provide SW workaround for PCI initialization on 85xx CDS
+
+* Patches by George G. Davis, 24 Aug 2004:
+ - Enable ramdisk/initrd tagged param support for omap1610h2_config
+ - Remove static network setup defaults from mx1ads_config
+ - update ARM boards to use constants from mach-types.h
+
+* Patch by Gary Jennejohn, 04 Oct 2004:
+ - fix I2C on at91rm9200
+ - add support for Ricoh RS5C372A RTC
+
+* Patch by Gary Jennejohn, 01 Oct 2004:
+ - add support for CMC PU2 board
+ - add support for I2C on at91rm9200
+
+* Patch by Gary Jennejohn, 28 Sep 2004:
+ fix baudrate handling on at91rm9200
+
+* Patch by Yuli Barcohen, 22 Aug 2004:
+ - remove ZPC.1900 board-specific flash driver;
+ switch the port to generic CFI driver;
+ - port clean-up
+
+* Patch by Hinko Kocevar, 21 Aug 2004:
+ Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB
+
+* Clean up tools/bmp_logo.c to not add trailing white space
+
+* Patch by Hinko Kocevar, 21 Aug 2004:
+ - Group common framebuffer functions in common/lcd.c
+ - Group common framebuffer macros and #defines in include/lcd.h
+ - Provide calc_fbsize() for video ATAG
+
+* Patch by Sam Song, 21 August 2004:
+ - Fix a typo in README
+ - Align "(RO)" output for "flinfo" after "protect on"
+ - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency
+ ratio 1:1 when core frequency less than 50MHz
+
+* Patches by Hinko Kocevar, 21 Aug 2004:
+ - fix some "use of label at end of compound statement" warnings
+ - Define type of LCD panel on lubbock board if CONFIG_LCD is used
+
+* Patch by Steven Scholz, 16 Aug 2004:
+ - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)"
+ - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0
+ - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/
+ - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/
+ into cpu/arm920t/$(SOC)/
+
+* Patches by Sean Chang, 09 Aug 2004:
+ - Added support for both 8 and 16 bit mode access to System ACE CF
+ through MPU.
+ - Fixed missing System ACE CF device during get FAT partition info
+ in fat_register_device function.
+ - Enabled System ACE CF support on ML300.
+
+* Patch by Sean Chang, 09 Aug 2004:
+ Synch defines for saveenv and do_saveenv functions so they get
+ compiled under the same statement.
+
+* Patch by Sean Chang, 09 Aug 2004:
+ - Added I2C support for ML300.
+ - Added support for ML300 to read out its environment information
+ stored on the EEPROM.
+ - Added support to use board specific parameters as part of
+ U-Boot's environment information.
+ - Updated MLD files to support configuration for new features
+ above.
+
+* Patches by Travis Sawyer, 05 Aug 2004:
+ - Remove incorrect bridge settings for eth group 6
+ - Add call to setup bridge in ppc_440x_eth_initialize
+ - Fix ppc_440x_eth_init to reset the phy only if its the
+ first time through, otherwise, just check the phy for the
+ autonegotiated speed/duplex. This allows the use of netconsole
+ - only print the speed/duplex the first time the phy is reset.
+
+* Patch by Shlomo Kut, 29 Mar 2004:
+ Add support for MKS Instruments "Quantum" board
+
+* Fix build problem with Cogent boards;
+ avoid using <asm/byteorder.h> when using the host compiler
+
+* Patch by Ganapathi C, 04 Aug 2004:
+ Fix NFS timeout issue
+
+* Patch by Yuli Barcohen, 19 Jul 2004:
+ - Fix host tools building in Cygwin environment
+ - Fix header files search order for host tools
+
+* Patch by Tom Armistead, 19 Jul 2004:
+ Fix kgdb.S support for 74xx_75x cpu
+
+* Patch by Jon Loeliger, 15 Jul 2004:
+ Fix MPC85xx I2C driver
+
+* Fix problems with CDROM drive as slave device on Lite5200 IDE bus.
+
+* Patch by Stephen Williams, 15 July 2004
+ Set the PCI class code for JSE board as part of PCI interface setup
+
+* Patch by Michael Bendzick, 15 Jul 2004:
+ Fix problem with writes with odd sizes in drivers/cfi_flash.c when
+ CFG_FLASH_USE_BUFFER_WRITE is set
+
+* Patch by Yuli Barcohen, 13 Jul 2004:
+ Allow clock setting on MPC866/MPC885 series chips according to
+ environment variable `cpuclk'
+
+* Patch by Yuli Barcohen, 20 Apr 2004:
+ Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
+
+* Patch by Vincent Dubey, 24 Sep 2004:
+ Add support for xaeniax board
+
+* Add comment about non-GPL character of standalone applications to
+ COPYING file
+
+* Fix FEC ethernet problem on NSCU board.
+
+* Patch by Gary Jennejohn, 09 Sep 2004:
+ allow to use USART1 as console port on at91rm9200dk boards
+
+* Patch by Stefan Roese, 16 Sep 2004:
+ Update AR405 board.
+
+* Fix SysClk handling for PPChameleon and CATcenter boards
+
+* Patch by Detlev Zundel, 08 Sep 2004:
+ Update etags build target
+
+* Improve NetConsole support: add support for broadcast destination
+ address and buffered input.
+
+* Cleanup compiler warnings for GCC 3.3.x and later
+
+* Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch
+
+* Add support for IDS "NC650" board
+
+* Add automatic update support for LWMON board
+
+* Clear Block Lock-Bits when erasing flash on LWMON board.
+
+* Fix return code of "fatload" command
+
+* Enable MSDOS/VFAT filesystem support for LWMON board
+
+* Patch by Martin Krause, 03 Aug 2004:
+ change timing for SM501 graphics controller on TQM5200 module
+
+* Patch by Mark Jonas, 13 July 2004:
+ - Total5200 LCD now run in little endian mode. Endianess conversion
+ is done in hardware.
+ - Removed last reference to "console" environment variable.
+
+* Patches by Lars Munch, 12 Jul 2004:
+ - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk
+ board specific
+ - split out the LXT971A PHY from ns_9750_eth.h
+ - split the dm9161 phy part out of at91rm9200_ether.c
+
+* Patch by Andreas Engel, 12 Jul 2004:
+ Replaced hardcoded PL011 clock frequency with config variable.
+ Fixed wrong CONFIG_CMD_DFL doc.
+
+* Patch by Thomas Viehweger, 09 Jun 2004:
+ make it possible to remove chpart when there is only one partition
+
+* Add support for console over UDP (compatible to Ingo Molnar's
+ netconsole patch under Linux)
+
+* Patch by Jon Loeliger, 16 Jul 2004:
+ - support larger DDR memories up to 2G on the PC8540/8560ADS and
+ STXGP3 boards
+ - Made MPC8540/8560ADS be 33Mhz PCI by default.
+ - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
+ and CONFIG_L2_INIT_RAM options.
+ - Refactor Local Bus initialization out of SDRAM setup.
+ - Re-implement new version of LBC11/DDR11 errata workarounds.
+ - Moved board specific PCI init parts out of CPU directory.
+ - Added TLB entry for PCI-1 IO Memory
+ - Updated README.mpc85xxads
+
+* Patch by Sascha Hauer, 28 Jun:
+ - add generic support for Motorola i.MX architecture
+ - add support for mx1ads, mx1fs2 and scb9328 boards
+
+* Patches by Marc Leeman, 23 Jul 2004:
+ - Add define for the PCI/Memory Buffer Configuration Register
+ - corrected comments in cpu/mpc824x/cpu_init.c
+
+* Add support for multiple serial interfaces
+ (for example to allow modem dial-in / dial-out)
+
+* Patch by Stefan Roese, 15 Jul 2004:
+ cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
+
+* Fix NSCU config; add ethernet wakeup code.
+
+* Add link for preloader for Motorola ColdFire to README.m68k
+
+* Patch by Michael Bendzick, 12 Jul 2004:
+ fix output formatting in drivers/cfi_flash.c
+
+* Patch by Mark Jonas, 02 Jul 2004:
+ Fix lowboot (again) on MPC5xxx
+
+* Patch by Curt Brune, 07 Jul 2004:
+ relocate exception vectors on arm720t if needed
+
+* Patch by George G. Davis, 06 Jul 2004:
+ - update mach-types.h to latest arm.linux.org.uk master list
+ - Set correct OMAP1610 bi_arch_number for build target
+
+* Patch by Curt Brune, 06 Jul 2004:
+ evb4510: add support for timer interrupt; cleanup
+
+* Patch by Dan Poirot, 06 Jul 2004:
+ Fix sbc8260 environment variables
+
+* Cleanup redundand "console" environment variable
+
+* Patch by Mark Jonas, 05 Jul 2004:
+ add support for the Total5100's and Total5200's LCD screen
+
+* Patches by Dan Eisenhut, 01 Jul 2004:
+ - README fixes.
+ - Move doc2000.h include to prevent compiler warning on some boards
+
+* Patch by Mark Jonas, 01 Jul 2004:
+ Added support for Total5100 and Total5200 (Rev.1 and Rev.2)
+ MGT5100 and MPC5200 based Freescale platforms.
+
+* Patch by Philippe Robin, 01 Jul 2004:
+ Add initialization for Integrator and versatile board files.
+
+* Patch by Hinko Kocevar, 01 Jun 2004:
+ Fix VFD FB allocation, add LCD FB allocation on ARM
+
+* Patch by Martin Krause, 30 Jun 2004:
+ Add support for TQM5200 board
+
+* Patch by Martin Krause, 29 Jun 2004:
+ Add loopw command: infinite write loop on address range
+
+* Patches by Yasushi Shoji, 29 Jun 2004:
+ - add empty include/asm-microblaze/processor.h
+ - add to CREDITS and MAINTAINERS
+ - add gd initialization
+ - add MicroBlaze and SUZAKU board to MAKEALL script
+ - add reset support for SUZAKU
+ - add flush_cache() for MicroBlaze
+ - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed
+ size flash memory on SUZAKU
+
+* Patch by Prakash Kumar, 27 Jun 2004:
+ Add support for the PXA250 based Intrinsyc Cerf board.
+
+* Patch by Yasushi Shoji, 27 Jun 2004:
+ fix comment in include/common.h
+
+* Rename SBC8560 into sbc8560 for consistency
+
+* Patch by Daniel Poirot, 24 Jun 2004:
+ Add support for Wind River's sbc8240 board
+
+* Patches by Yasushi Shoji, 26 Jun 2004:
+ - drivers/serial_xuartlite.c: fix "return 0" in void function
+ - add microblaze support to mkimage tool
+
+* Patch by Fred Klatt, 25 Jun 2004:
+ Add support for WindRiver's sbc8560 board
+
+* Patch by Nicolas Lacressonniere, 24 Jun 2004
+ Small Bugs fixes for "at91rm9200dk" board:
+ - Timing modifications for SPI DataFlash access
+ - Fix NAND flash detection bug
+
+* Patch by Nicolas Lacressonniere, 24 Jun 2004:
+ Add Support for Flash AT49BV6416 for AT91RM9200DK board
+
+* Patch by Jon Loeliger, 17 June 2004:
+ Completion of the 8540ADS/8560ADS updates:
+ Fix some PCI and Rapid I/O memory maps,
+ Initialize both TSEC 1 and 2,
+ Initialize SDRAM
+ Update MAINTAINER for 85xx boards and README.mpc85xxads
+
+* Patch by Yuli Barcohen, 16 Jun 2004:
+ Remove obsolete AdderII port which was superseded by unified
+ AdderII/Adder87x port
+
+* Patch by Ladislav Michl, 16 Jun 2004:
+ Fix gcc-3.3.3 warnings for smc91111.c
+
+* Patch by Stefan Roese, 02 Jul 2004:
+ - Fix bug in 405 ethernet driver; allocated data not cleared!
+ - Fix problem in 405 i2c driver; don't try to print without console!
+
+* Patch by Paul Ruhland, 11 Jun 2004:
+ Remove debug code from 'board/lpd7a40x/flash.c'
+
+* Patch by Andrea Marson, 11 Jun 2004:
+ Update for PPChameleon board:
+ - support for SysClk @ 25MHz
+ - support for Silicon Motion SM712 VGA controller
+ - some clean ups
+
+* Patches by Richard Woodruff, 10 Jun 2004:
+ - fix problems with examples/stubs.c for GCC >= 3.4
+ - fix problems with gd initialization
+
+* Patch by Curt Brune, 17 May 2004:
+ - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
+ - Add support for ESPD-Inc. EVB4510 Board
+
+* Patch by Marc Leeman, 11 May 2004:
+ Fix for MPC8245 - reading PPC Memory from another device with the
+ PPC as PCI target device corrupts data due to interenal hardware
+ buffering.
+
+* Fix "cls" command when used with splash screen
+
+* Increase NFS download timeout (now 1 min - 10 sec is to short for a
+ slow download of a big image)
+
+* Add "cls" function to MPC823 LCD driver so we can reinitialize the
+ display even after showing a bitmap
+
+* Patch by Josef Wagner, 04 Jun 2004:
+ - DDR Ram support for PM520 (MPC5200)
+ - support for different flash types (PM520)
+ - USB / IDE / CF-Card / DiskOnChip support for PM520
+ - 8 bit boot rom support for PM520/CE520
+ - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
+ - I2C and RTC support for CPC45
+ - support of new flash type (28F160C3T) for CPC45
+
+* Fix flash parameters passed to Linux for PPChameleon board
+
+* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
+
+* Patch by Paul Ruhland, 10 Jun 2004:
+ fix support for Logic SDK-LH7A404 board and clean up the
+ LH7A404 register macros.
+
+* Patch by Matthew McClintock, 10 Jun 2004:
+ Modify code to select correct serial clock on Sandpoint8245
+
+* Patch by Robert Schwebel, 10 Jun 2004:
+ Add support for Intel K3 strata flash.
+
+* Patch by Thomas Brand, 10 Jun 2004:
+ Fix "loads" command on DK1S10 board
+
+* Patch by Yuli Barcohen, 09 Jun 2004:
+ Add support for 8MB flash SIMM and JFFS2 file system on
+ Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS).
+
+* Patch by Yuli Barcohen, 09 Jun 2004:
+ Add support for Analogue&Micro Adder87x and the older AdderII board.
+
+* Patch by Ming-Len Wu, 09 Jun 2004:
+ Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
+
+* Patch by Sam Song, 09 Jun 2004:
+ - Add support for RPXlite_DW board
+ - Update FLASH driver for 4*AM29DL323DB90VI
+ - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board
+
+* Patch by Mark Jonas, 08 June 2004:
+ - Make MPC5200 boards evaluate the SVR to print processor name and
+ version in checkcpu() (cpu/mpc5xxx/cpu.c).
+
+* Patch by Kai-Uwe Bloem, 06 May 2004:
+ Fix endianess problem in cramfs code
+
+* Patch by Tom Armistead, 04 Jun 2004:
+ Add support for MAX6900 RTC
+
+* Patches by Ladislav Michl, 03 Jun 2004:
+ - fix cfi_flash.c on LE systems
+ - let 'make mrproper' delete u-boot.img as well
+ - turn printf into debug in cfi_flash.c
+
+* Patch by Kurt Stremerch, 28 May 2004:
+ Add support for Exys XSEngine board
+
+* Patch by Martin Krause, 27 May 2004:
+ Fix a MPC5xxx I2C timing issue in i2c_probe().
+
+* Patch by Leif Lindholm, 27 May 2004:
+ Fix board_init_f() for dbau1x00 board.
+
+* Patch by Imre Deak, 26 May 2004:
+ On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3).
+ Set flash base accordingly, and decide whether to do or skip board
+ specific setup steps.
+
+* Patch by Josef Baumgartner, 26 May 2004:
+ Add missing define in include/asm-m68k/global_data.h
+
+* Patch by Josef Baumgartner, 25 May 2004:
+ Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c
+
+* Patch by Paul Ruhland, 24 May 2004:
+ fix SDRAM initialization for LPD7A400 board.
+
+* Patch by Jian Zhang, 20 May 2004:
+ add support for environment in NAND flash
+
+* Patch by Yuli Barcohen, 20 May 2004:
+ Add support for Interphase iSPAN boards.
+
+* Patches by Paul Ruhland, 17 May 2004:
+ - Add I/O functions to the smc91111 ethernet driver to support the
+ Logic LPD7A40x boards.
+ - Add support for the Logic Zoom LH7A40x based SDK board(s),
+ specifically the LPD7A400.
+
+* Patches by Robert Schwebel, 15 May 2004:
+ - call MAC address reading code also for SMSC91C111;
+ - make SMSC91C111 timeout configurable, remove duplicate code
+ - fix get_timer() for PXA
+ - update doc/README.JFFS2
+ - use "bootfile" env variable also for jffs2
+
+* Patch by Tolunay Orkun, 14 May 2004:
+ Add support for Cogent CSB472 board (8MB Flash Rev)
+
+* Patch by Thomas Viehweger, 14 May 2004:
+ - flash.h: more flash types added
+ - immap_8260.h: some bits added (useful for RMII)
+ - cmd_coninfo.c: typo corrected, printf -> puts
+ - reduced size by replacing spaces with tab
+
+* Patch by Robert Schwebel, 13 May 2004:
+ Add 'imgextract' command: extract one part of a multi file image.
+
+* Patches by Jon Loeliger, 11 May 2004:
+ Dynamically handle REV1 and REV2 MPC85xx parts.
+ (Jon Loeliger, 10-May-2004).
+ New consistent memory map and Local Access Window across MPC85xx line.
+ New CCSRBAR at 0xE000_0000 now.
+ Add RAPID I/O memory map.
+ New memory map in README.MPC85xxads
+ (Kumar Gala, 10-May-2004)
+ Better board and CPU identification on MPC85xx boards at boot.
+ (Jon Loeliger, 10-May-2004)
+ SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
+ Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
+ (Jim Robertson, 10-May-2004)
+ Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
+ Supports multiple PHYs.
+ (Andy Fleming, 10-May-2004)
+ Some README.MPC85xxads updates.
+ (Kumar Gala, 10-May-2004)
+ Copyright updates for "Freescale"
+ (Andy Fleming, 10-May-2004)
+
+* Patch by Stephen Williams, 11 May 2004:
+ Add flash support for ST M29W040B
+ Reduce JSE specific flash.c to remove dead code.
+
+* Patch by Markus Pietrek, 04 May 2004:
+ Fix clear_bss code for ARM systems (all except s3c44b0 which
+ doesn't clear BSS at all?)
+
+* Fix "ping" problem on INC-IP board. Strange problem:
+ Sometimes the store word instruction hangs while writing to one of
+ the Switch registers, but only if the next instruction is 16-byte
+ aligned. Moving the instruction into a separate function somehow
+ makes the problem go away.
+
+* Patch by Rishi Bhattacharya, 08 May 2004:
+ Add support for TI OMAP5912 OSK Board
+
+* Patch by Sam Song May, 07 May 2004:
+ Fix typo of UPM table for rmu board
+
+* Patch by Pantelis Antoniou, 05 May 2004:
+ - Intracom board update.
+ - Add Codec POST.
+
+* Add support for the second Ethernet interface for the 'PPChameleon'
+ board.
+
+* Patch by Dave Peverley, 30 Apr 2004:
+ Add support for OMAP730 Perseus2 Development board
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+ Fix flash chip-select (OR0) option register setting on FADS boards.
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+ Report MII network speed and duplex setting properly when
+ auto-negotiate is not enabled.
+
+* Patch by Jarrett Redd, 29 Apr 2004:
+ Fix hang on reset on Ocotea board due to flash in wrong mode.
+
+* Patch by Dave Peverley, 29 Apr 2004:
+ add MAC address detection to smc91111 driver
+
+* Patch by David Müller, 28 Apr 2004:
+ fix typo in lib_arm/board.c
+
+* Patch by Tolunay Orkun, 20 Apr 2004:
+ - README update: add CONFIG_CSB272 and csb272_config
+ - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and
+ i2cfast environment variable
+
+* Patch by Yuli Barcohen, 19 Apr 2004:
+ - Rename DUET_ADS to MPC885ADS
+ - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
+ - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
+ - Clean up FADS family port to use the new defines
+
+* Fix PCI support on CPC45 board
+
+* Patch by Scott McNutt, 25 Apr 2004:
+ Add Nios GDB/JTAG Console support:
+ - Add stubs to support gdb via JTAG.
+ - Add support for console over JTAG.
+ - Minor cleanup.
+
+* Add support for CATcenter board (based on PPChameleon ME module)
+
+* Patch by Klaus Heydeck, 12 May 2004:
+ Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
+ load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;
+ various changes to KUP4 board specific files
+
+* Fix minor network problem on MPC5200: need some delay between
+ resetting the PHY and sending the first packet. Implemented in a
+ "natural" way by invoking the PHY reset and initialization code
+ only once after power on vs. each time the interface is brought up.
+
+* Add some limited support for low-speed devices to SL811 USB controller
+ (at least "usb reset" now passes successfully and "usb info" displays
+ correct information)
+
+* Change init sequence for multiple network interfaces: initialize
+ on-chip interfaces before external cards.
+
+* Fix memory leak in the NAND-specific JFFS2 code
+
+* Fix SL811 USB controller when attached to a USB hub
+
+* Fix config option spelling in PM520 config file
+
+* Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by
+ patches by Pantelis Antoniou, 30 Mar 2004)
+
+* Fix minor NAND JFFS2 related issue
+
+* Fixes for SL811 USB controller:
+ - implement workaround for broken memory stick
+ - improve error handling
+
+* Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better
+ cope with congested networks.
+
+======================================================================
+Changes for U-Boot 1.1.1:
+======================================================================
+
+* Patch by Travis Sawyer, 23 Apr 2004:
+ Fix VSC/CIS 8201 phy descrambler interoperability timing due to
+ errata from Vitesse Semiconductor.
+
+* Patch by Philippe Robin, 22 Apr 2004:
+ Fix ethernet configuration for "versatile" board
+
+* Patch by Kshitij Gupta, 21 Apr 2004:
+ Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards
+
+* Patch by Steven Scholz, 24 Feb 2004:
+ Fix a bug in AT91RM9200 ethernet driver:
+ The MII interface is now initialized before accessing the PHY.
+
+* Patch by John Kerl, 19 Apr 2004:
+ Use U-boot's miiphy.h for PHY register names, rather than
+ introducing a new header file.
+
+* Update pci_ids.h from linux-2.4.26
+
+* Patch by Masami Komiya, 19 Apr 2004:
+ Fix problem cause by VLAN function on little endian architecture
+ without VLAN environment
+
+* Clean up the TQM8xx_YYMHz configurations; allow to use the same
+ binary image for all clock frequencies. Implement run-time
+ optimization of flash access timing based on the actual bus
+ frequency.
+
+* Modify KUP4X board configuration to use SL811 driver for USB memory
+ sticks (including FAT / VFAT filesystem support)
+
+* Add SL811 Host Controller Interface driver for USB
+
+* Add CFG_I2C_EEPROM_ADDR_OVERFLOW desription to README
+
+* Patch by Pantelis Antoniou, 19 Apr 2004:
+ Allow to use shell style syntax (i. e. ${var} ) with standard parser.
+ Minor patches for Intracom boards.
+
+* Patch by Christian Pell, 19 Apr 2004:
+ cleanup support for CF/IDE on PCMCIA for PXA25X
+
+* Temporarily disabled John Kerl's extended MII command code because
+ "miivals.h" is missing
+
+* Patches by Mark Jonas, 13 Apr 2004:
+ - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S
+ - Add sync instructions to IceCube SDRAM init code
+ - Move SDRAM chip constants into seperate include files
+ - Unify DDR and SDR initialization code
+ - Unify all IceCube (Lite5xxx) target names
+
+* Patch by John Kerl, 16 Apr 2004:
+ Enable ranges in mii command, e.g. mii read 0-1f 0 or
+ mii read 4-7 18-1a. Also add mii dump subcommand for
+ pretty-printing standard regs 0-5.
+
+* Patch by Stephen Williams, 16 April 2004:
+ fix typo in JSE.h; update MAINTAINERS
+
+* Patch by Matthew S. McClintock, 14 Apr 2004:
+ fix initdram function for utx8245 board
+
+* Patch by Markus Pietrek, 14 Apr 2004:
+ use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag
+
+* Patch by Reinhard Meyer, 18 Apr 2004:
+ provide the IDE Reset Function for EMK 5200 boards
+
+* Patch by Masami Komiya, 12 Apr 2004:
+ fix pci_hose_write_config_{byte,word}_via_dword problems
+
+* Patch by Sangmoon Kim, 12 Apr 2004:
+ Update max RAM size for debris board
+
+* Patch by Travis Sawyer, 08 Apr 2004:
+ Add TLB entry for second DIMM slot on ocotea
+
+* Patch by Masami Komiya, 08 Apr 2004:
+ add RTL8169 network driver
+
+* Patch by Dan Malek, 07 Apr 2004:
+ - Add support for RPC/STx GP3, Motorola 8560 board
+ - Update 85xx TSEC driver so it searches MII for first available PHY
+ and uses that one.
+ - Add functions to support console MII commands.
+
+* Patch by Tolunay Orkun, 07 Apr 2004:
+ Move initialization of bi_iic_fast[]
+ from board_init_f() to board_init_r()
+
+* Patch by Yasushi Shoji, 07 Apr 2004:
+ Cleanup microblaze port
+
+* Patch by Sangmoon Kim, 07 Apr 2004:
+ Add auto SDRAM module detection for Debris board
+
+* Patch by Rune Torgersen, 06 Apr 2004:
+ - Fix some PCI problems on the MPC8266ADS board
+ - Fix the location of some PCI entries in the immap structure
+
+* Patch by Yasushi Shoji, 07 Apr 2004:
+ - add support for microblaze processors
+ - add support for AtmarkTechno "suzaku" board
+
+* Configure PPChameleon board to use redundand environment in flash
+
+* Configure PPChameleon board to use JFFS2 NAND support.
+
+* Added support for JFFS2 filesystem (read-only) on top of NAND flash
+
+* Patch by Rune Torgersen, 16 Apr 2004:
+ LBA48 fixes
+
+* Patches by Pantelis Antoniou, 16 Apr 2004:
+ - add support for a new version of an Intracom board and fix
+ various other things on others.
+ - add verify support to the crc32 command (define
+ CONFIG_CRC32_VERIFY to enable it)
+ - fix FEC driver for MPC8xx systems:
+ 1. fix compilation problems for boards that use dynamic
+ allocation of DPRAM
+ 2. shut down FEC after network transfers
+ - HUSH parser fixes:
+ 1. A new test command was added. This is a simplified version of
+ the one in the bourne shell.
+ 2. A new exit command was added which terminates the current
+ executing script.
+ 3. Fixed handing of $? (exit code of last executed command)
+ - Fix some compile problems;
+ add "once" functionality for the netretry variable
+
+* Patch by George G. Davis, 02 Apr 2004:
+ add support for Intel Assabet board
+
+* Patch by Stephen Williams, 01 Apr 2004:
+ Add support for Picture Elements JSE board
+
+* Patch by Christian Pell, 01 Apr 2004:
+ Add CompactFlash support for PXA systems.
+
+* Patches by Pantelis Antoniou, 30 Mar 2004:
+ - add auto-complete support to the U-Boot CLI
+ - add support for NETTA and NETPHONE boards; fix NETVIA board
+ - add support for the Epson 156x series of graphical displays
+ (These displays are serial and not suitable for using a normal
+ framebuffer console on them)
+ - add infrastructure needed in order to POST any DSPs in a board
+ - improve and fix various things in the MPC8xx FEC driver:
+ 1. The new 87x and 88x series of processors have two FECs,
+ and the new driver supports them both.
+ 2. Another change in the 87x/88x series is support for
+ the RMII (Reduced MII) interface. However numerous
+ changes are needed to make it work since the PHYs
+ are connected to the same lines. That means that
+ you have to address them correctly over the MII
+ interface.
+ 3. We now correctly match the MII/RMII interface
+ configuration to what the PHY reports.
+ - Fix problem when readingthe MII status register. Due to the
+ internal design of many PHYs you have to read the register
+ twice. The problem is more apparent in 10Mbit mode.
+ - add new mode ".jffs2s" for reading from a NAND device: it just
+ skips over bad blocks.
+ - add networking support for VLANs (802.1q), and CDP (Cisco
+ Discovery Protocol)
+ - some minor patches / cleanup
+
+* Patch by Yuli Barcohen, 28 Mar 2004:
+ - Add support for MPC8272 family including MPC8247/8248/8271/8272
+ - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS)
+ - Change configuration method for MPC8260ADS family
+
+* add startup code to clear the BSS of standalone applications
+
+* Fix if / elif handling bug in HUSH shell
+
+======================================================================
+Changes for U-Boot 1.1.0:
+======================================================================
+
+* Patch by Mark Jonas: Remove config.tmp files only when
+ unconfiguring the board
+
+* Adapt RMU board for bigger flash memory
+
+* Patch by Klaus Heydeck, 13 Mar 2003:
+ Add support for KUP4X Board
+
+* Patch by Pavel Bartusek, 21 Mar 2004
+ Add Reiserfs support
+
+* Patch by Hinko Kocevar, 20 Mar 2004
+ - Add auto-release for SMSC LAN91c111 driver
+ - Add save/restore of PTR and PNR regs as suggested in datasheet
+
+* Patch by Stephen Williams, 19 March 2004
+ Increase speed of sector reads from SystemACE,
+ shorten poll timeout and remove a useless reset
+
+* Patch by Tolunay Orkun, 19 Mar 2004:
+ Make GigE PHY 1000Mbps Speed/Duplex detection conditional
+ (CONFIG_PHY_GIGE)
+
+* Patch by Brad Kemp, 18 Mar 2004:
+ prevent machine checks during a PCI scan
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+ Fix string cleaning in IDE identification
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+ - Unify video mode handling for Chips & Technologies 69000 Video
+ chip and Silicon Motion SMI 712/710/810 Video chip
+ - Add selection of the video output (CRT or LCD) via 'videoout'
+ environment variable for the Silicon Motion
+ - README update
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+ include/common.h typo fix
+
+* Patches by Tolunay Orkun, 17 Mar 2004:
+ - Add support for bd->bi_iic_fast[] initialization via environment
+ variable "i2cfast" (CONFIG_I2CFAST)
+ - Add "i2cfast" u-boot environment variable support for csb272
+
+* Patch by Carl Riechers, 17 Mar 2004:
+ Ignore '\0' characters in console input for use with telnet and
+ telco pads.
+
+* Patch by Leon Kukovec, 17 Mar 2004:
+ typo fix for strswab prototype #ifdef
+
+* Patches by Thomas Viehweger, 16 Mar 2004:
+ - show PCI clock frequency on MPC8260 systems
+ - add FCC_PSMR_RMII flag for HiP7 processors
+ - in do_jffs2_fsload(), take load address from load_addr if not set
+ explicit, update load_addr otherwise
+ - replaced printf by putc/puts when no formatting is needed
+ (smaller code size, faster execution)
+
+* Patch by Phillippe Robin, 16 Mar 2004:
+ avoid dereferencing NULL pointer in lib_arm/armlinux.c
+
+* Patch by Stephen Williams, 15 Mar 2004:
+ Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation
+
+* Patch by Tolunay Orkun, 15 Mar 2004:
+ Initialize bi_opbfreq to real OPB frequency via get_OPB_freq()
+
+* Patch by Travis Sawyer, 15 Mar 2004:
+ Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port
+
+* Add start-up delay to make sure power has stabilized before
+ attempting to switch on USB on SX1 board.
+
+* Patch by Josef Wagner, 18 Mar 2004:
+ - Add support for MicroSys XM250 board (PXA255)
+ - Add support for MicroSys PM828 board (MPC8280)
+ - Add support for 32 MB Flash on PM825/826
+ - new SDRAM refresh rate for PM825/PM826
+ - added support for MicroSys PM520 (MPC5200)
+ - replaced Query by Identify command in CPU86/flash.c
+ to support 28F160F3B
+
+* Fix wrap around problem with udelay() on ARM920T
+
+* Add support for Macronix flash on TRAB board
+
+* Patch by Pierre Aubert, 15 Mar 2004:
+ Fix buffer overflow in IDE identification
+
+* Fix power-off of LCD for out-of-band temperatures on LWMON board
+
+* Remove redundand #define in IceCube.h
+
+* Patch by Steven Scholz, 27 Feb 2004:
+ - Adding get_ticks() and get_tbclk() for AT91RM9200
+ - Many white space fixes in cpu/at91rm9200/interrupts.c
+
+* Patches by Steven Scholz, 20 Feb 2004:
+ some cleanup in AT91RM9200 related code
+
+* Patches by Travis Sawyer, 12 Mar 2004:
+ - Fix Gigabit Ethernet support for 440GX
+ - Add Gigabit Ethernet Support to MII PHY utilities
+
+* Patch by Brad Kemp, 12 Mar 2004:
+ Fixes for drivers/cfi_flash.c:
+ - Better support for x8/x16 implementations
+ - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE
+ - Added defines for AMD command and address constants
+
+* Patch by Leon Kukovec, 12 Mar 2004:
+ Fix get_dentfromdir() to correctly handle deleted dentries
+
+* Patch by George G. Davis, 11 Mar 2004:
+ Remove hard coded network settings in TI OMAP1610 H2
+ default board config
+
+* Patch by George G. Davis, 11 Mar 2004:
+ add support for ADS GraphicsClient+ board.
+
+* Patch by Pierre Aubert, 11 Mar 2004:
+ - add bitmap command and splash screen support in cfb console
+ - add [optional] origin in the bitmap display command
+
+* Patch by Travis Sawyer, 11 Mar 2004:
+ Fix ocotea board early init interrupt setup.
+
+* Patch by Thomas Viehweger, 11 Mar 2004:
+ Remove redundand code; add PCI-specific bits to include/mpc8260.h
+
+* Patch by Stephan Linz, 09 Mar 2004
+ - Add support for the SSV ADNP/ESC1 (Nios Softcore)
+
+* Patch by George G. Davis, 9 Mar 2004:
+ fix recent build failure for SA1100 target
+
+* Patch by Travis Sawyer, 09 Mar 2004:
+ Support native interrupt mode for the IBM440GX.
+ Previously it was running in 440GP compatibility mode.
+
+* Patch by Philippe Robin, 09 Mar 2004:
+ Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference
+ Platform support.
+
+* Patch by Masami Komiya, 08 Mar 2004:
+ Don't overwrite server IP address or boot file name
+ when the boot server does not return values
+
+* Patch by Tolunay Orkun, 5 Mar 2004:
+ Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC
+
+* Patch by Tolunay Orkun, 5 Mar 2004:
+ Fix early board initialization for Cogent CSB272 board
+
+* Patch by Ed Okerson, 3 Mar 2004:
+ fix CFI flash writes for little endian systems
+
+* Patch by Reinhard Meyer, 01 Mar 2004:
+ generalize USB and IDE support for MPC5200 with according
+ changes to IceCube.h and TOP5200.h
+ add Am29LV256 256 MBit FLASH support for TOP5200 boards
+ add info about USB and IDE to README
+
+* Patch by Yuli Barcohen, 4 Mar 2004:
+ Fix problems with GCC 3.3.x which changed handling of global
+ variables explicitly initialized to zero (now in .bss instead of
+ .data as before).
+
+* Patch by Leon Kukovec, 02 Mar 2004:
+ add strswab() to fix IDE LBA capacity, firmware and model numbers
+ on little endian machines
+
+* Patch by Masami Komiya, 02 Mar 2004:
+ - Remove get_ticks() from NFS code
+ - Add verification of RPC transaction ID
+
+* Patch by Pierre Aubert, 02 Mar 2004:
+ cleanup for IDE and USB drivers for MPC5200
+
+* Patch by Travis Sawyer, 01 Mar 2004:
+ Ocotea:
+ - Add IBM PPC440GX Ref Platform support (Ocotea)
+ Original code by Paul Reynolds <PaulReynolds@lhsolutions.com>
+ Adapted to U-Boot and 440GX port
+ 440gx_enet.c:
+ - Add gracious handling of all Ethernet Pin Selections for 440GX
+ - Add RGMII selection for Cicada CIS8201 Gigabit PHY
+ ppc440.h:
+ - Add needed bit definitions
+ - Fix formatting
+
+* Patch by Carl Riechers, 1 Mar 2004:
+ Add PPC440GX prbdv0 divider to fix memory clock calculation.
+
+* Patch by Stephan Linz, 27 Feb 2004
+ - avoid problems for targets without NFS download support
+
+* Patch by Rune Torgersen, 27 Feb 2004:
+ - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA)
+ - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF)
+ - Added support for 64bit strtoul (CFG_64BIT_STRTOUL)
+
+* Patch by Masami Komiya, 27 Feb 2004:
+ Fix rarpboot: add autoload by NFS
+
+* Patch by Dan Eisenhut, 26 Feb 2004:
+ fix flash_write return value in saveenv
+
+* Patch by Stephan Linz, 11 Dec 2003
+ expand config.mk to avoid trigraph warnings on NIOS
+
+* Rename "BMS2003" board into "HMI10"
+
+* SX1 patches: use "serial#" for USB serial #; use redundand environment
+ storage; auto-set console on USB port (using preboot command)
+
+* Add support for SX1 mobile phone; add support for USB-based console
+ (enable with "setenv stdout usbtty; setenv stdin usbtty")
+
+* Fix LOWBOOT configuration for MPC5200 with DDR memory
+
+* Fix SDRAM timings for LITE5200 / IceCube board
+
+* Handle Auti-MDIX / connection status for INCA-IP
+
+* Fix USB problems when attempting to read 0 bytes
+
+* Patch by Travis Sawyer, 26 Feb 2004:
+ Fix broken compile for XPEDITE1K target.
+
+* Patch by Stephan Linz, 26 Feb 2004:
+ Bug fix for NFS code on NIOS targets
+
+* Patch by Stephen Williams, 26 Feb 2004:
+ Break up SystemACE reads of large block counts
+
+* Patch by Pierre Aubert, 26 Feb 2004
+ add IDE support for MPC5200
+
+* Patch by Masami Komiya, 26 Feb 2004:
+ add autoload via NFS
+
+* Patch by Stephen Williams
+ Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses
+ elsewhere in the source.
+
+* Patch by Steven Scholz, 25 Feb 2004:
+ - Timeouts in FPGA code should be based on CFG_HZ
+ - Minor cleanup in code for Altera FPGA ACEX1K
+
+* Patch by Steven Scholz, 25 Feb 2004:
+ Changed "Directory Hierarchy" section in README
+
+* Patch by Masami Komiya, 25 Feb 2004:
+ Reduce copy count in nfs_read_reply() of NFS code
+
+* Patch by Markus Pietrek, 24 Feb 2004:
+ NS9750 DevBoard added
+
+* Patch by Pierre Aubert, 24 Feb 2004
+ add USB support for MPC5200
+
+* Patch by Steven Scholz, 24 Feb 2004:
+ - fix MII commands to use values from last command
+
+* Patch by Torsten Demke, 24 Feb 2004:
+ Add support for the eXalion platform (SPSW-8240, F-30, F-300)
+
+* Patch by Rahul Shanbhag, 19 Feb 2004:
+ Fixes for for OMAP1610 board:
+ - shift some IRQ specific code to platform.S file
+ - remove duplicatewatchdog reset code from start.S
+
+* Make Auto-MDIX Support configurable on INCA-IP board
+
+* Fix license for mkimage tool
+
+* Patch by Masami Komiya, 24 Feb 2004:
+ Update NetBootFileXferSize in NFS code
+
+* Patch by Scott McNutt, 24 Feb 2004:
+ fix packet length in NFS code
+
+* Patch by Masami Komiy, 22 Feb 2004:
+ Add support for NFS for file download
+
+* Patch by Andrea Scian, 17 Feb 2004:
+ Add support for S3C44B0 processor and DAVE B2 board
+
+* Patch by Steven Scholz, 20 Feb 2004:
+ - Add support for MII commands on AT91RM9200 boards
+ - some cleanup in AT91RM9200 ethernet code
+
+* Patch by Peter Ryser, 20 Feb 2004:
+ Add support for the Xilinx ML300 platform
+
+* Patch by Stephan Linz, 17 Feb 2004:
+ Fix watchdog support for NIOS
+
+* Patch by Josh Fryman, 16 Feb 2004:
+ Fix byte-swapping for cfi_flash.c for different bus widths
+
+* Patch by Jon Diekema, 14 Jeb 2004:
+ Remove duplicate "FPGA Support" notes from the README file
+
+* Patches by Reinhard Meyer, 14 Feb 2004:
+ - update board/emk tree; use common flash driver
+ - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c
+ [adapted for other PPC CPUs -- wd]
+ - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c
+
+* Patch by Jon Diekema, 13 Feb 2004:
+ Call show_boot_progress() whenever POST "FAILED" is printed.
+
+* Patch by Nishant Kamat, 13 Feb 2004:
+ Add support for TI OMAP1610 H2 Board
+ Fixes for cpu/arm926ejs/interrupt.c
+ (based on Richard Woodruff's patch for arm925, 16 Oct 03)
+ Fix for a timer bug in OMAP1610 Innovator
+ Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2
+
+* Patches by Stephan Linz, 12 Feb 2004:
+ - add support for NIOS timer with variable period preload counter value
+ - prepare POST framework support for NIOS targets
+
+* Patch by Denis Peter, 11 Feb 2004:
+ add POST support for the MIP405 board
+
+* Patch by Laurent Mohin, 10 Feb 2004:
+ Fix buffer overflow in common/usb.c
+
+* Patch by Tolunay Orkun, 10 Feb 2004:
+ Add support for Cogent CSB272 board
+
+* Patch by Thomas Elste, 10 Feb 2004:
+ Add support for NET+50 CPU and ModNET50 board
+
+* Patch by Sam Song, 10 Feb 2004:
+ Fix typos in cfi_flash.c
+
+* Patch by Leon Kukovec, 10 Feb 2004
+ Fixed long dir entry slot id calculation in get_vfatname
+
+* Patch by Robin Gilks, 10 Feb 2004:
+ add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==,
+ !=, <>, <, >, <=, >=)
+
+* Fix problem with side effects in macros in include/usb.h
+
+* Patch by David Benson, 13 Nov 2003:
+ bug 841358 - fix TFTP download size limit
+
+* Fixing bug 850768:
+ improper flush_cache() in load_serial()
+
+* Fixing bug 834943:
+ MPC8540 - missing volatile declarations
+
+* Patch by Stephen Williams, 09 Feb 2004:
+ Add support for Xilinx SystemACE chip:
+ - New files common/cmd_ace.c and include/systemace.h
+ - Hook systemace support into cmd_fat and the partition manager
+
+* Patch by Travis Sawyer, 09 Feb 2004:
+ Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux
+
+* Patch by Travis Sawyer, 09 Feb 2004:
+ o 440GX:
+ - Fix PCI Indirect access for type 1 config cycles with ppc440.
+ - Add phymode for 440 enet
+ - fix pci pre init
+ o XPedite1K:
+ - Change board_pre_init to board_early_init_f
+ - Add user flash to bus controller setup
+ - Fix pci pre init
+ - Fix is_pci_host to check GPIO for monarch bit
+ - Force xpedite1k to pci conventional mode (via #define option)
+
+* Patch by Brad Kemp, 4 Feb 2004:
+ - handle the machine check that is generated during the PCI scans
+ on 82xx processors.
+ - define the registers used in the IMMR by the PCI subsystem.
+
+* Patch by Pierre Aubert, 03 Feb 2004:
+ cpu/mpc5xxx/start.S: copy MBAR into SPR311
+
+* Patch by Jeff Angielski, 03 Feb 2004:
+ Fix copy & paste error in cpu/mpc8260/pci.c
+
+* Patch by Reinhard Meyer, 24 Jan 2004:
+ Fix typo in cpu/mpc5xxx/pci_mpc5200.c
+
+* Add Auto-MDIX support for INCA-IP
+
+* Some code cleanup
+
+* Patch by Josef Baumgartner, 10 Feb 2004:
+ Fixes for ColdFire port
+
+* Patch by Brad Kemp, 11 Feb 2004:
+ Fix CFI flash driver problems
+
+* Make sure to use a bus clock divider of 2 only when running TQM8xxM
+ modules at CPU clock frequencies above 66 MHz.
+
+* Optimize flash programming speed for LWMON (by another 100% :-)
+
+* Patch by Jian Zhang, 3 Feb 2004:
+ - Changed the incorrect FAT12BUFSIZE
+ - data_begin in fsdata can be negative. Changed it to be short.
+
+* Patches by Stephan Linz, 30 Jan 2004:
+ 1: - board/altera/common/flash.c:flash_erase():
+ o allow interrupts befor get_timer() call
+ o check-up each erased sector and avoid unexpected timeouts
+ - board/altera/dk1c20/dk1s10.c:board_early_init_f():
+ o enclose sevenseg_set() in cpp condition
+ - remove the ASMI configuration for DK1S10_standard_32 (never present)
+ - fix some typed in mistakes in the NIOS documentation
+ 2: - split DK1C20 configuration into several header files:
+ o two new files for each NIOS CPU description
+ o U-Boot related part is remaining in DK1C20.h
+ 3: - split DK1S10 configuration into several header files:
+ o two new files for each NIOS CPU description
+ o U-Boot related part is remaining in DK1S10.h
+ 4: - Add support for the Microtronix Linux Development Kit
+ NIOS CPU configuration at the Altera Nios Development Kit,
+ Stratix Edition (DK-1S10)
+ 5: - Add documentation for the Altera Nios Development Kit,
+ Stratix Edition (DK-1S10)
+ 6: - Add support for the Nios Serial Peripharel Interface (SPI)
+ (master only)
+ 7: - Add support for the common U-Boot SPI framework at
+ RTC driver DS1306
+
+* Patch by Rahul Shanbhag, 28 Jan 2004:
+ Fix flash protection/locking handling for OMAP1610 innovator board.
+
+* Patch by Rolf Peukert, 28 Jan 2004:
+ fix flash write problems on CSB226 board (write with 32 bit bus width)
+
+* Patches by Mark Jonas, 16 Jan 2004:
+ - fix rounding error when calculating baudrates for MPC5200 PSCs
+ - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same
+ time which is not supported
+
+* Patch by Yuli Barcohen, 26 Jan 2004:
+ Allow bzip2 compression for small memory footprint boards
+
+* Patch by Brad Kemp, 21 Jan 2004:
+ Add support for CFI flash driver for both the Intel and the AMD
+ command sets.
+
+* Patch by Travis Sawyer, 20 Jan 2004:
+ Fix pci bridge auto enumeration of sibling p2p bridges.
+
+* Patch by Tolunay Orkun, 12 Jan 2004:
+ Add some delays as needed for Intel LXT971A PHY support
+
+* Patches by Stephan Linz, 09 Jan 2004:
+ - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c
+ - make DK1C20 board configuration related to ASMI conform to
+ documentation
+
+* Patch by Anders Larsen, 09 Jan 2004:
+
+ ARM memory layout fixes: the abort-stack is now set up in the
+ correct RAM area, and the BSS is zeroed out as it should be.
+
+ Furthermore, the magic variables 'armboot_end' and 'armboot_end_data'
+ of the linker scripts are replaced by '__bss_start' and '_end',
+ resp., which is a further step to eliminate unnecessary differences
+ between the implementation of the CPU architectures.
+
+* Patch by liang a lei, 9 Jan 2004:
+ Fix Intel 28F128J3 ID in include/flash.h
+
+* Patch by Masami Komiya, 09 Jan 2004:
+ add support for TB0229 board (NEC VR4131 MIPS processor)
+
+* Patch by Leon Kukovec, 12 Dec 2003:
+ changed extern __inline__ into static __inline__ in
+ include/linux/byteorder/swab.h
+
+* Patch by Travis Sawyer, 30 Dec 2003:
+ Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
+ select MDI port based on enabled EMAC device.
+ Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX
+ base PrPMC board.
+
+* Patch by Wolter Kamphuis, 15 Dec 2003:
+ made CONFIG_SILENT_CONSOLE usable on all architectures
+
+* Disable date command on TQM866M - there is no RTC on MPC866
+
+* Fix variable CPU clock for MPC859/866 systems for low CPU clocks
+
+* Implement adaptive SDRAM timing configuration based on actual CPU
+ clock frequency for INCA-IP; fix problem with board hanging when
+ switching from 150MHz to 100MHz
+
+* Add PCMCIA CS support for BMS2003 board
+
+* Add variable CPU clock for MPC859/866 systems (so far only TQM866M):
+ see doc/README.MPC866 for details;
+ implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866;
+ calculate CPU clock frequency from PLL register values.
+
+* Add support for 128 MB RAM on TQM8xxL/M modules
+
+* Fix PS/2 keyboard problem caused by statically initialized variable
+ pointing to a location in flash
+
+* Fix INCA-IP clock calculation: 400/3 = 133.3 MHz, not 130.
+
+* The PS/2 mux on the BMS2003 board needs 450 ms after power on
+ before we can access it; add delay in case we are faster (with no
+ CF card inserted)
+
+* Cleanup of some init functions
+
+* Make sure SCC Ethernet is always stopped by the time we boot Linux
+ to avoid Linux crashes by early packets coming in.
+
+* Accelerate flash accesses on LWMON board by using buffered writes
+
+* Fix typo in Makefile;
+ fix problem with PARTNUM detection
+
+* Patch by Reinhard Meyer, 09 Jan 2004:
+ - add RTC support for MPC5200 based boards (requires RTC_XTAL)
+
+* Add support for IDE LED on BMS2003 board
+ (exclusive with status LED!)
+
+* Add support for PS/2 keyboard (used with PS/2 multiplexor on
+ BMS2003 board)
+
+* Patches by Reinhard Meyer, 4 Jan 2004 + 7 Jan 2004:
+ Add common files for "emk" boards
+
+* Add a common get_ram_size() function and modify the the
+ board-specific files to invoke that common implementation.
+
+======================================================================
+Changes for U-Boot 1.0.1:
+======================================================================
+
+* Set default clock for INCA-IP to 150 MHz
+
+* Make BMS2003 use a separate config file to avoid #ifdef mess;
+ add I2C support; add support for DS1337 RTC
+
+* Add CompactFlash support for BMS2003 board
+
+* Add support for status LED on BMS2003 board
+
+* Patch by Scott McNutt, 02 Jan 2004:
+ Add support for the Nios Active Serial Memory Interface (ASMI)
+ on Cyclone devices
+
+* Patch by Andrea Marson, 16 Dec 2003:
+ Add support for the PPChameleon ME and HI modules
+
+* Patch by Yuli Barcohen, 22 Dec 2003:
+ Add support for Motorola DUET ADS board (MPC87x/88x)
+
+* Patch by Robert Schwebel, 15 Dec 2003:
+ add support for cramfs (uses JFFS2 command interface)
+
+* Patches by Stephan Linz, 11 Dec 2003:
+ - more documentation for NIOS port
+ - new struct nios_pio_t, struct nios_spi_t
+ - Reconfiguration for NIOS Development Kit DK1C20:
+ o move board related code from board/dk1c20
+ to board/altera/dk1c20
+ o create a new common source path board/altera/common
+ and move generic flash access stuff into it
+ o change/expand configuration file DK1C20.h
+ - Add support for NIOS Development Kit DK1S10
+ - Add status LED support for NIOS systems
+ - Add dual 7-segment LED support for Altera NIOS DevKits
+
+* Patch by Ronen Shitrit, 10 Dec 2003:
+ Add support for the Marvell DB64360 / DB64460 development boards
+
+* Patch by Detlev Zundel, 10 Dec 2003:
+ fix dependency problem in examples/Makefile
+
+* Patch by Denis Peter, 8 Dec 2003
+ - add support for the PATI board (MPC555)
+ - add SPI support for the MPC5xx
+
+* Patch by Anders Larsen, 08 Dec 2003:
+ add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG
+ to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target;
+ cleanup some redundand #defines
+
+* Patch by André Schwarz, 8 Dec 2003:
+ fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM):
+ - TX and RX deskriptors must be quad-word aligned
+ - does not work with only one TX deskriptor
+ - standard reset method does not work
+
+* Patch by Masami Komiya, 08 Dec 2003:
+ add RTL8139 ethernet driver
+
+* Patches by Ed Okerson, 07 Dec 2003:
+ - fix ethernet for the AU1x00 processors in little-endian mode.
+ - extend memsetup.S for the AU1x00 processors in BE and LE modes
+
+* Minor code cleanup (coding style)
+
+* Patch by Reinhard Meyer, 30 Dec 2003:
+ - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
+ - added CONFIG_PHY_ADDR to include/configs/IceCube.h,
+ - turned debug print of PHY registers into a function (called in two places)
+ - added support for EMK MPC5200 based modules
+
+* Fix MPC8xx PLPRCR_MFD_SHIFT typo
+
+* Add support for TQM866M modules
+
+* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)
+
+* Fix a few compiler warnings
+
+* Patch by Reinhard Meyer, 28 Dec 2003:
+ Add initial support for TOP5200 board
+
+* Make CPU clock on ICA-IP board controllable by a "cpuclk"
+ environment variable which can set to "100", "133", or "150". The
+ CPU clock will be configured accordingly upon next reboot. Other
+ values are ignored. In case of an invalid or undefined "cpuclk"
+ value, the compile-time default CPU clock speed will be used.
+
+* Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory
+ window that is used to access the UART registers by the Linux driver)
+
+* Patch by Reinhard Meyer, 20 Dec 2003:
+ Fix clock calculation for the MPC5200 for higher clock frequencies
+ (above 2**32 / 10 = 429.5 MHz).
+
+* Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration
+
+* Fix IceCube CLKIN configuration (it's 33.000000MHz)
+
+* Add new configuration for IceCube board with DDR memory
+
+* Update TRAB memory configurations
+
+* Add JFFS2 support for INCA-IP board
+
+* Patch by Bill Hargen, 09 Dec 2003:
+ - BUBINGA405EP: changed flash driver to protect top sector containing
+ first instruction.
+ - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM.
+ - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access).
+ - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1).
+ - 405EP: added/fixed support for "reginfo" command.
+ - 4xx: removed spurious MII error messages on "mii info" command.
+
+* Patch by Bernhard Kuhn, 28 Nov 2003:
+ add support for ColdFire CPU
+ add support for Motorola M5272C3 and M5282EVB boards
+
+* Patch by Pierre Aubert, 24 Nov 2003:
+ - add a return value for the fpga command
+ - add ide_preinit() function called in ide_init if CONFIG_IDE_PREINIT
+ is defined. If ide_preinit fails, ide_init is aborted.
+ - fix an endianess problem in fat.h
+
+* Patch by Wolter Kamphuis, 05 Dec 2003:
+ Add support for SNMC's QS850/QS823/QS860T boards
+
+* Patch by Yuli Barcohen, 3 Dec 2003:
+ "revive" U-Boot support for old Motorola MPC860ADS board
+
+* Patch by Cam(ilo?), 03 Dec 2003:
+ make examples build even with broken Montavista objcopy
+
+* Patch by Pavel Bartusek, 27 Nov 2003:
+ fix conversion problem with "bootretry" evironment variable
+
+* Patch by Andre Schwarz, 24 Nov 2003:
+ add support for mvblue (mvBlueLYNX and mvBlueBOX) boards
+
+* Patch by Pavel Bartusek, 21 Nov 2003:
+ set ZMII bridge speed on 440
+
+* Patch by Anders Larsen, 17 Nov 2003:
+ Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h
+
+* Patches by David Müller, 14 Nov 2003:
+ - board/mpl/common/common_util.c
+ * implement support for BZIP2 compressed images
+ * various cleanups (printf -> puts, ...)
+ - board/mpl/common/flash.c
+ * report correct errors to upper layers
+ * check the erase fail and VPP low bits in status reg
+ - board/mpl/vcma9/cmd_vcma9.c
+ - board/mpl/vcma9/flash.c
+ * various cleanups (printf -> puts, ...)
+ - common/cmd_usb.c
+ * fix typo in comment
+ - cpu/arm920t/usb_ohci.c
+ * support for S3C2410 is missing in #if line
+ - drivers/cs8900.c
+ * reinit some registers in case of error (cable missing, ...)
+ - fs/fat/fat.c
+ * support for USB/MMC devices is missing in #if line
+ - include/configs/MIP405.h
+ - include/configs/PIP405.h
+ * enable BZIP2 support
+ * enlarge malloc space to 1MiB because of BZIP2 support
+ - include/configs/VCMA9.h
+ * enable BZIP2 support
+ * enlarge malloc space to 1MiB because of BZIP2 support
+ * enable USB support
+ - lib_arm/armlinux.c
+ * change calling convention of ARM Linux kernel as
+ described on http://www.arm.linux.org.uk/developer/booting.php
+
+* Patch by Thomas Lange, 14 Nov 2003:
+ Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs to
+ support all these AMD boards.
+
+* Patch by Thomas Lange, 14 Nov 2003:
+ Workaround for mips au1x00 physical memory accesses (the au1x00
+ uses a 36 bit bus internally and cannot access physical memory
+ directly. Use the uncached SDRAM address instead of the physical
+ one.)
+
+* Patch by Xue Ligong (Joe), 13 Nov 2003:
+ add Realtek 8019 ethernet driver
+
+* Patch by Yuli Barcohen, 13 Nov 2003:
+ MPC826xADS/PQ2FADS cleanup
+
+* Patch by Anders Larsen, 12 Nov 2003:
+ Update README to mark the PORTIO commands non-standard
+
+* Patch by Nicolas Lacressonnière, 12 Nov 2003:
+ update for for Atmel AT91RM9200DK development kit:
+ - support for environment variables in DataFlash
+ - Atmel DataFlash AT45DB1282 support
+
+* Patch by Jeff Carr, 11 Nov 2003:
+ add support for new version of 8270 processors
+
+* Patches by George G. Davis, 05 Nov 2003:
+ - only pass the ARM linux initrd tag to the kernel when an initrd
+ is actually present
+ - update omap1510inn configuration file
+
+* Patches by Stephan Linz, 3 Nov 2003:
+ - more endianess fixes for LAN91C111 driver
+ - CFG_HZ configuration patch for NIOS Cyclone board
+
+* Patch by Stephan Linz, 28 Oct 2003:
+ fix PHY_INT_REG vs. PHY_MASK_REG bug in drivers/smc91111.c
+
+* Patch by Steven Scholz, 20 Oct 2003:
+ - make "mii info <addr>" show infor for PHY at "addr" only
+ - Endian fix for miiphy_info()
+
+* Patch by Gleb Natapov, 19 Sep 2003:
+ Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c
+
+* Patch by Anders Larsen, 17 Sep 2003:
+ Bring ARM memory layout in sync with the documentation:
+ stack and malloc-heap are now located _below_ the U-Boot code
+
+* Accelerate booting on TRAB board: read and check autoupdate image
+ headers first instead of always reading the whole images.
+
+* Fix type in MPC5XXX code (pointed out by Victor Wren)
+
+* Enabled password check on RMU board
+
+* Fix configuration problem with IceCube in LOWBOOT configuration:
+ envrionment got embedded, corrupting the image layout.
+
+* Fix NEC display names (it's 6440 [for 640x480], not 6640).
+
+* Added BMS2003 board
+ add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display
+
+* Fix flash driver for TRAB board (must use Unlock Bypass Reset
+ command to exit Unlock Bypass Mode); adjust timings for flash, SRAM
+ and CPLD
+
+* Use "-fPIC" instead of "-mrelocatable" to prevent problems with
+ recent tools
+
+* Add checksum verification to 'imls' command
+
+* Add bd_info fields needed for 4xx Linux I2C driver
+
+* Patch by Martin Krause, 4 Nov. 2003:
+ Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap)
+
+* Print used network interface when CONFIG_NET_MULTI is set
+
+* Patch by Bernhard Kuhn, 28 Oct 2003:
+ Add low boot support for MPC5200
+
+* Fix problem with dual PCMCIA support (NSCU)
+
+* Fix MPC5200 I2C initialization function
+
+======================================================================
+Changes for U-Boot 1.0.0:
+======================================================================
+
+* Fix parameter passing to standalone images with bootm command
+
+* Patch by Kyle Harris, 30 Oct 2003:
+ Fix build errors for ixdp425 board
+
+* Patch by David M. Horn, 29 Oct 2003:
+ Fixes to build under CYGWIN
+
+* Get IceCube MGT5100 working (again)
+
+* Fix problems in memory test on some boards (which was not
+ non-destructive as intended)
+
+* Patch by Gary Jennejohn, 28 Oct 2003:
+ Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack
+ to prevent stack overflow on ARM systems
+
+* Patch by Stephan Linz, 28 Oct 2003:
+ fix init sequence error for NIOS port
+
+* Allow lowercase spelling for IceCube_5200; support MPC5200LITE name
+
+* Add CONFIG_VERSION_VARIABLE to TRAB configuration
+
+* Patch by Xiao Xianghua, 23 Oct 2003:
+ small patch for mpc85xx
+
+* Fix small problem in MPC5200 I2C driver
+
+* Fix FCC3 support on ATC board
+
+* Correct header printing for multi-image files in do_bootm()
+
+* Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED
+
+* Fix PCI problems on PPChameleon board
+
+* Patch by Steven Scholz, 18 Oct 2003:
+ Fix AT91RM9200 ethernet driver
+
+* Patch by Nye Liu, 17 Oct 2003:
+ Fix typo in include/mpc8xx.h
+
+* Patch by Richard Woodruff, 16 Oct 03:
+ Fixes for cpu/arm925/interrupt.c
+ - Initialize timestamp & lastdec vars.
+ - fix timestamp overflows.
+ - fix lastdec overflow.
+ - smarter normalization to allow udelay() below 1ms to work.
+
+* Patch by Scott McNutt, 16 Oct
+ add networking support for the Altera Nios Development Kit,
+ Cyclone Edition (DK-1C20)
+
+* Patch by Jon Diekema, 14 Oct 2003:
+ add hint about doc/README.silent to README file
+
+* Add CompactFlash support for NSCU
+
+* Fix PCI problems on PPChameleonEVB
+
+* TRAB auto-update: Base decision if we have to strip the image
+ header on image type as encoded in the header
+ (include image type patch by Martin Krause, 17 Oct 2003)
+
+* Patches by Xianghua Xiao, 15 Oct 2003:
+
+ - Added Motorola CPU 8540/8560 support (cpu/85xx)
+ - Added Motorola MPC8540ADS board support (board/mpc8540ads)
+ - Added Motorola MPC8560ADS board support (board/mpc8560ads)
+
+* Fix flash timings on TRAB board
+
+* Make sure HUSH is initialized for running auto-update scripts
+
+* Make 5200 reset command _really_ reset the board, without running
+ any other code after it
+
+* Fix errors with flash erase when range spans across banks
+ that are mapped in reverse order
+
+* Fix flash mapping and display on P3G4 board
+
+* Patch by Kyle Harris, 15 Jul 2003:
+ - add support for Intel IXP425 CPU
+ - add support for IXDP425 eval board
+
+* Added config option CONFIG_SILENT_CONSOLE. See doc/README.silent
+ for more information
+
+* Patch by Steven Scholz, 10 Oct 2003
+ - Add support for Altera FPGA ACEX1K
+
+* Patches by Thomas Lange, 09 Oct 2003:
+ - fix cmd_ide.c for non ppc boards (read/write functions did not
+ add ATA base address)
+ - fix for shannon board
+ - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code
+ - Endian swap ATA identity for all big endian CPUs, not just PPC
+ - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
+ args to linux
+ - add support for dbau1x00 board (MIPS32)
+
+* Patch by Sangmoon Kim, 07 Oct 2003:
+ add support for debris board
+
+* Patch by Martin Krause, 09 Oct 2003:
+ Fixes for TRAB board
+ - /board/trab/rs485.c: correct baudrate
+ - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
+ udelay(); fix some timing problems with adc controller
+ - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power;
+ modify commands: touch and buzzer
+
+* Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE
+ (quick & dirty workaround for rogue pointer problem in get_vfatname());
+ Use direct function calls for auto_update instead of hush commands
+
+* Patch by Scott McNutt, 04 Oct 2003:
+ - add support for Altera Nios-32 CPU
+ - add support for Nios Cyclone Development Kit (DK-1C20)
+
+* Patch by Steven Scholz, 29 Sep 2003:
+ - A second parameter for bootm overwrites the load address for
+ "Standalone Application" images.
+ - bootm sets environment variable "filesize" to the resulting
+ (uncompressed) data length for "Standalone Application" images
+ when autostart is set to "no". Now you can do something like
+ if bootm $fpgadata $some_free_ram ; then
+ fpga load 0 $some_free_ram $filesize
+ fi
+
+* Patch by Denis Peter, 25 Sept 2003:
+ add support for the MIP405 Rev. C board
+
+* Patch by Yuli Barcohen, 25 Sep 2003:
+ add support for Zephyr Engineering ZPC.1900 board
+
+* Patch by Anders Larsen, 23 Sep 2003:
+ add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only
+ implemented for the x86 architecture)
+
+* Patch by Sangmoon Kim, 23 Sep 2003:
+ fix pll_pci_to_mem_multiplier table for MPC8245
+
+* Patch by Anders Larsen, 22 Sep 2003:
+ enable timed autoboot on PXA
+
+* Patch by David Müller, 22 Sep 2003:
+ - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver
+ returns correct libgcc file path
+ - "latency" reduction of busy-loop waiting to improve "U-Boot" boot
+ time on s3c24x0 systems
+
+* Patch by Jon Diekema, 19 Sep 2003:
+ - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet
+ link state to the fault LED.
+ - In NetLoop, make the Fault LED reflect the link status. The link
+ status gets updated on entry, and on timeouts.
+
+* Patch by Anders Larsen, 18 Sep 2003:
+ allow mkimage to build and run on Cygwin-hosted systems
+
+* Patch by Frank Müller, 18 Sep 2003:
+ use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in
+ cpu/mpc8xx/fec.c
+
+* Patch by Pantelis Antoniou, 16 Sep 2003:
+ add tool to compute fileds in the PLPRCR register for MPC86x
+
+* Use IH_TYPE_FILESYSTEM for TRAB "disk" images.
+
+* Fix build problems under FreeBSD
+
+* Add generic filesystem image type
+
+* Make fatload set filesize environment variable
+
+* enable basic / medium / high-end configurations for PPChameleonEVB
+ board; fix NAND code
+
+* enable TFTP client code to specify to the server the desired
+ timeout value (see RFC-2349)
+
+* Improve SDRAM setup for TRAB board
+
+* Suppress all output with splashscreen configured only if "splashimage"
+ is set
+
+* Fix problems with I2C support for mpc5200
+
+* Adapt TRAB configuration and auto_update to new memory layout
+
+* Add configuration for wtk board
+
+* Add support for the Sharp LQ065T9DR51U LCD display
+
+* Patch by Rune Torgersen, 17 Sep 2003:
+ - Fixes for MPC8266 default config
+ - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
+
+* Patches by Jon Diekema, 17 Sep 2003:
+ - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and
+ env_common.c)
+ - sbc8260 tweaks
+ - adjust "help" output
+
+* Patches by Anders Larsen, 17 Sep 2003:
+ - fix spelling errors
+ - set GD_FLG_DEVINIT flag only after device function pointers
+ are valid
+ - Allow CFG_ALT_MEMTEST on systems where address zero isn't
+ writeable
+ - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs
+ - trigger watchdog while waiting in serial driver
+
+* Add auto-update code for TRAB board using USB memory sticks,
+ support new configuration with more memory
+
+* disable MPC5200 bus pipelining as workaround for bus contention
+
+* Modify XLB arbiter priorities on MPC5200 so all devices use same
+ priority; configure critical interrupts to be handled like external
+ interrupts
+
+* Make IPB clock on MGT5100/MPC5200 configurable in board config file;
+ go back to 66 MHz for stability
+
+* Patches by Jon Diekema, 15 Sep 2003:
+ - add description for missing CFG_CMD_* entries in the README file
+ - sacsng tweaks
+
+* Patch by Gleb Natapov, 14 Sep 2003:
+ enable watchdog support for all MPC824x boards that have a watchdog
+
+* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the
+ "Non-octet Aligned Frame" errors we see at 100 Mbps
+
+* Patch by Sharad Gupta, 14 Sep 2003:
+ fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
+
+* Patch by llandre, 11 Sep 2003:
+ update configuration for PPChameleonEVB board
+
+* Patch by David Müller, 13 Sep 2003:
+ various changes to VCMA9 board specific files
+
+* Add I2C support for MGT5100 / MPC5200
+
+* Patch by Rune Torgersen, 11 Sep 2003:
+ Changed default memory option on MPC8266ADS to NOT be Page Based
+ Interleave, since this doesn't work very well with the standard
+ 16MB DIMM
+
+* Patch by George G. Davis, 12 Sep 2003:
+ fix Makefile settings for sk98 driver
+
+* Patch by Stefan Roese, 12 Sep 2003:
+ - new boards added: DP405, HUB405, PLU405, VOH405
+ - some esd boards updated
+ - cpu/ppc4xx/sdram.c: disable memory controller before setting
+ first values
+ - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems
+
+* Patch by Martin Krause, 11 Sep 2003:
+ add burn-in tests for TRAB board
+
+* Enable instruction cache on MPC5200 board
+
+* Patch by Denis Peter, 11 Sep 2003:
+ - fix USB data pointer assignment for bulk only transfer.
+ - prevent to display erased directories in FAT filesystem.
+
+* Change output format for NAND flash - make it look like for other
+ memory, too
+
+======================================================================
+Changes for U-Boot 0.4.8:
+======================================================================
+
+* Add I2C and RTC support for RMU board
+
+* Patches by Denis Peter, 9 Sep 2003:
+ add FAT support for IDE, SCSI and USB
+
+* Patches by Gleb Natapov, 2 Sep 2003:
+ - cleanup of POST code for unsupported architectures
+ - MPC824x locks way0 of data cache for use as initial RAM;
+ this patch unlocks it after relocation to RAM and invalidates
+ the locked entries.
+
+* Patch by Gleb Natapov, 30 Aug 2003:
+ new I2C driver for mpc107 bridge. Now works from flash.
+
+* Patch by Dave Ellis, 11 Aug 2003:
+ - JFFS2: fix typo in common/cmd_jffs2.c
+ - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
+ - JFFS2: remove node version 0 warning
+ - JFFS2: accept JFFS2 PADDING nodes
+ - SXNI855T: add AM29LV800 support
+ - SXNI855T: move environment from EEPROM to flash
+ - SXNI855T: boot from JFFS2 in NOR or NAND flash
+
+* Patch by Bill Hargen, 11 Aug 2003:
+ fixes for I2C on MPC8240
+ - fix i2c_write routine
+ - fix iprobe command
+ - eliminates use of global variables, plus dead code, cleanup.
+
+* Add support for USB Mass Storage Devices (BBB)
+ (tested with USB memory sticks only)
+
+* Avoid flicker on TRAB's VFD
+
+* Add support for SK98xx driver
+
+* Add PCI support for SL8245 board
+
+* Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB)
+ or 1 x AM29LV652 (two LV065 in one chip = 16 MB);
+ Run IPB at 133 Mhz; adjust the MII clock frequency accordingly
+
+* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz)
+ to allow for more accurate baudrate settings
+ (error now 0.7% at 115 kbps, instead of 3.5% before)
+
+* Patch by Andreas Mohr, 4 Sep 2003:
+ Fix a lot of spelling errors
+
+* Add support for PPChameleon Eval Board
+
+* Add support for P3G4 board
+
+* Fix problem with MGT5100 FEC driver: add "early" MAC address
+ initialization
+
+* Patch by Yuli Barcohen, 7 Aug 2003:
+ check BCSR to detect if the board is configured in PCI mode
+
+======================================================================
+Changes for U-Boot 0.4.7:
+======================================================================
+
+* Patch by Raghu Krishnaprasad, 7 Aug 2003:
+ add support for Adder II MPC852T module
+
+* Patch by George G. Davis, 19 Aug 2003:
+ fix TI Innovator/OMAP1510 pin configs
+
+* Patches by Kshitij, 18 Aug 2003
+ - add support for arm926ejs cpu core
+ - add support for TI OMAP 1610 Innovator Board
+
+* Patch by Yuli Barcohen, 14 Aug 2003:
+ add support for bzip2 uncompression
+
+* Add GCC library to examples/Makefile so GCC utility functions will
+ be resolved, too
+
+* Add I2C and RTC support for RMU board using software I2C driver
+ (because of better response to iprobe command); fix problem with
+ "reset" command
+
+* Patch by Matthias Fuchs, 28 Aug 2003:
+ Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to
+ CONFIG_BOOTP_MAKS (see README).
+
+* Fix ICU862 environment problem
+
+* Fix RAM size detection for RMU board
+
+* Implement "reset" for MGT5100/MPC5200 systems
+
+======================================================================
+Changes for U-Boot 0.4.6:
+======================================================================
+
+* Make Ethernet autonegotiation on INCA-IP work for all clock rates;
+ allow selection of clock frequency as "make" target
+
+* Implement memory autosizing code for IceCube boards
+
+* Configure network port on INCA-IP for autonegotiation
+
+* Fix overflow problem in network timeout code
+
+* Patch by Richard Woodruff, 8 Aug 2003:
+ Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
+
+======================================================================
+Changes for U-Boot 0.4.5:
+======================================================================
+
+* Update for TQM board defaults:
+ disable clocks_in_mhz, enable boot count limit
+
+* Removed tools/gdb from "make all" target. Added make target "gdbtools"
+ in toplevel directory instead. Removed astest.c from tools/gdb because
+ it is no longer relevant.
+
+* Fix PCI support for MPC5200 / IceCube Board
+
+* Map ISP1362 USB OTG controller for NSCU board
+
+* Patch by Brad Parker, 02 Aug 2003:
+ fix sc520_cdp problems
+
+* Implement Boot Cycle Detection (Req. 2.3 of OSDL CGL Reqirements)
+
+* Allow erase command to cross flash bank boundaries
+
+* Patch by Scott McNutt, 21 Jul 2003:
+ Add support for LynuxWorks Kernel Downloadable Images (KDIs).
+ Both LynxOS and BlueCat linux KDIs are supported.
+
+* Patch by Richard Woodruff, 25 Jul 2003:
+ use more reliable reset for OMAP/925T
+
+* Patch by Nye Liu, 25 Jul 2003:
+ fix typo in mpc8xx.h
+
+* Patch by Richard Woodruff, 24 Jul 2003:
+ Fixes for cmd_nand.c:
+ - Fixed null dereferece which could result in incorrect ECC values.
+ - Added support for devices with no Ready/Busy signal hooked up.
+ - Added OMAP1510 read/write protect handling.
+ - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock
+ for non-JFFS2.
+ - Switched default ECC to be JFFS2.
+
+* Allow crc32 to be used at address 0x000
+
+* Provide consistent interface to standalone applications to access
+ the 'global_data' structure
+ Provide a doc/README.standalone more useful to users/developers.
+
+* Make IceCube MGT5100 FEC driver work
+
+* Implement new mechanism to export U-Boot's functions to standalone
+ applications: instead of using (PPC-specific) system calls we now
+ use a jump table; please see doc/README.standalone for details
+
+* Patch by Dave Westwood, 24 Jul 2003:
+ added support for Unity OS (a proprietary OS)
+
+* Patch by Detlev Zundel, 23 Jul 2003:
+ add "imls" command to print flash table of contents
+
+* Fix cold boot detection for log buffer reset
+
+* Return error for invalid length specifiers with "cp.X" etc.
+
+* Fix startup problem on MIPS
+
+* Allow for CONFIG_SPLASH_SCREEN even when no explicit
+ bitmap support is configured
+
+* Patch by Bill Hargen, 18 Jul 2003:
+ - fix endinaness problem in cpu/mpc824x/drivers/i2c/i2c1.c
+
+* Patch by Denis Peter, 18 Jul 2003:
+ - fix memory configuration for MIP405T
+ - fix printout of baudrate for "loadb <loadaddr> <baudrate>"
+
+* Cleanup of TQM82xx configurations; use "official" board types
+ to make selection easier.
+
+* Patch by Martin Krause, 17 Jul 2003:
+ add delay to get I2C working with "imm" command and s3c24x0_i2c.c
+
+* Patch by Richard Woodruff, 17 July 03:
+ - Fixed bug in OMAP1510 baud rate divisor settings.
+
+* Patch by Nye Liu, 16 July 2003:
+ MPC860FADS fixes:
+ - add MPC86xADS support (uses MPC86xADS.h)
+ - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
+ o PLPRCR changes
+ o BRG changes (EXTAL/XTAL restricted to 10MHz)
+ o don't trust gclk() software measurement by default, depend on
+ CONFIG_8xx_GCLK_FREQ
+ - add DRAM SIMM not installed detection
+ - use more "correct" SDRAM initialization sequence
+ - allow different SDRAM sizes (8xxADS has 8M)
+ - default DER is 0
+ - remove unused MAMR defines from FADS860T.h (all done in fads.c)
+ - rename MAMR/MBMR defines to be more consistent. Should eventually
+ be merged into MxMR to better reflect the PowerQUICC datasheet.
+
+* Patch by Yuli Barcohen, 16 Jul 2003:
+ support new Motorola PQ2FADS-ZU evaluation board which replaced
+ MPC8260ADS and MPC8266ADS
+
+======================================================================
+Changes for U-Boot 0.4.4:
+======================================================================
+
+* Add support for IceCube board (with MGT5100 and MPC5200 CPUs)
+
+* Add support for MGT5100 and MPC5200 processors
+
+* Patch by Lutz Dennig, 15 Jul 2003:
+ update for R360MPI board
+
+======================================================================
+Changes for U-Boot 0.4.3:
+======================================================================
+
+* Patches by Kshitij, 04 Jul 2003
+ - added support for arm925t cpu core
+ - added support for TI OMAP 1510 Innovator Board
+
+* Patches by Martin Krause, 14 Jul 2003:
+ - add I2C support for s3c2400 systems (trab board)
+ - (re-) add "ping" to command table
+
+* Fix handling of "slow" POST routines
+
+* Patches by Yuli Barcohen, 13 Jul 2003:
+ - Correct flash and JFFS2 support for MPC8260ADS
+ - fix PVR values and clock generation for PowerQUICC II family
+ (8270/8275/8280)
+
+* Patch by Bernhard Kuhn, 08 Jul 2003:
+ - add support for M68K targets
+
+* Patch by Ken Chou, 3 Jul:
+ - Fix PCI config table for A3000
+ - Fix iobase for natsemi.c
+ (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
+
+* Allow to enable "slow" POST routines by key press on power-on
+* Fix temperature dependend switching of LCD backlight on LWMON
+* Tweak output format for LWMON
+
+* Patch by Stefan Roese, 11 Jul 2003:
+ - Fix bug in CONFIG_VERSION_VARIABLE.
+ - AR405 config updated.
+ - OCRTC/ORSG: bsp command added.
+ - ASH405 bsp update.
+
+======================================================================
+Changes for U-Boot 0.4.2:
+======================================================================
+
+* Add support for NSCU board
+
+* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules
+
+* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML
+ mirror bit flash on TQM8xxM modules
+
+* Patch by Kenneth Johansson, 30 Jun 2003:
+ get rid of MK_CMD_ENTRY macro; update doc/README.command
+
+* Patch by Seb James, 30 Jun 2003:
+ Improve documentation of I2C configuration in README
+
+* Fix problems with previous log buffer "fixes"
+
+* Fix minor help text issues
+
+* "log append" did not append a newline
+
+======================================================================
+Changes for U-Boot 0.4.1:
+======================================================================
+
+* Fix some missing commands, cleanup header files
+ (autoscript, bmp, bsp, fat, mmc, nand, portio, ...)
+
+* Rewrite command lookup and help command (fix problems with bubble
+ sort when sorting command name list). Minor cleanup here and there.
+
+* Merge from "stable branch", tag LABEL_2003_06_28_1800-stable:
+ - Allow to call sysmon function interactively
+ - PIC on LWMON board needs delay after power-on
+ - Add missing RSR definitions for MPC8xx
+ - Improve log buffer handling: guarantee clean reset after power-on
+ - Add support for EXBITGEN board (aka "genie")
+ - Add support for SL8245 board
+
+* Code cleanup:
+ - remove trailing white space, trailing empty lines, C++ comments, etc.
+ - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
+
+* Patches by Kenneth Johansson, 25 Jun 2003:
+ - major rework of command structure
+ (work done mostly by Michal Cendrowski and Joakim Kristiansen)
+
+======================================================================
+Changes for U-Boot 0.4.0:
+======================================================================
+
+* Patches by Robert Schwebel, 26 Jun 2003:
+ - csb226 configuration updated
+ - credits for logodl port updated
+ - innokom configuration updated
+ - logodl tree update, still with coding style inconsistencies
+ - added OCM for ppc405 warning to README
+
+* Patch by Pantelis Antoniou, 25 Jun 2003:
+ update NetVia with V2 board support
+
+* Header file cleanup for ARM
+
+* Patch by Murray Jensen, 24 Jun 2003:
+ - make sure to use only U-boot provided header files
+ - fix problems with ".rodata.str1.4" section as used by GCC-3.x
+
+* Patch by Stefan Roese, 24 Jun 2003:
+ - Update esd ASH405 board files.
+ - Update esd DASA_SIM config file.
+ - Add ping command to some esd boards.
+
+* Patch by Yuli Barcohen, 23 Jun 2003:
+ Update for MPC8260ADS board
+
+* Patch by Murray Jensen, 23 Jun 2003:
+ - cleanup of GCC 3.x compiler warnings
+
+* Patch by Rune Torgersen, 4 Jun 2003:
+ add large memory support for MPC8266ADS board
+
+* Patch by Richard Woodruff, 19 June 03:
+ - Enabled standard u-boot device abstraction for ARM
+ - Enabled console device for ARM
+ - Initilized bi_baudrate for ARM
+
+* Patch by Bill Hargen, 23 Apr 2003:
+ fix byte order for 824x I2C addresses (write op)
+
+* Patch by Murray Jensen, 20 Jun 2003:
+ - hymod update
+ - cleanup (especially for gcc-3.x compilers)
+
+* Patch by Tom Guilliams, 20 Jun 2003:
+ added CONFIG_750FX support for IBM 750FX processors
+
+* Patch by Devin Crumb, 02 Apr 2003:
+ Fix clock divider rounding problem in drivers/serial.c
+
+* Patch by Richard Woodruff, 19 June 03:
+ - Fixed smc91c111 driver to sync with the u-boot environment
+ (driver/smc91c111.c).
+ - Added eth_init error return check in NetLoop (net/net.c).
+
+* Patch by Ken Chou, 19 June 2003:
+ Added support for A3000 SBC board (Artis Microsystems Inc.)
+
+* Patches by Murray Jensen, 17 Jun 2003:
+ - Hymod board database mods: add "who" field and new xilinx chip types
+ - provide new "init_cmd_timeout()" function so code external to
+ "common/main.c" can use the "reset_cmd_timeout()" function before
+ entering the main loop
+ - add DTT support for adm1021 (new file dtt/adm1021.c; config
+ slightly different. see include/configs/hymod.h for an example
+ (requires CONFIG_DTT_ADM1021, CONFIG_DTT_SENSORS, and
+ CFG_DTT_ADM1021 defined)
+ - add new "eeprom_probe()" function which has similar args and
+ behaves in a similar way to "eeprom_read()" etc.
+ - add 8260 FCC ethernet loopback code (new "eth_loopback_test()"
+ function which is enabled by defining CONFIG_ETHER_LOOPBACK_TEST)
+ - gdbtools copyright update
+ - ensure that set_msr() executes the "sync" and "isync" instructions
+ after the "mtmsr" instruction in cpu/mpc8260/interrupts.c
+ - 8260 I/O ports fix: Open Drain should be set last when configuring
+ - add SIU IRQ defines for 8260
+ - allow LDSCRIPT override and OBJCFLAGS initialization: change to
+ config.mk to allow board configurations to override the GNU
+ linker script, selected via the LDSCRIPT, make variable, and to
+ give an initial value to the OBJCFLAGS make variable
+ - 8260 i2c enhancement:
+ o correctly extends the timeout depending on the size of all
+ queued messages for both transmit and receive
+ o will not continue with receive if transmit times out
+ o ensures that the error callback is done for all queued tx
+ and rx messages
+ o correctly detects both tx and rx timeouts, only delivers one to
+ the callback, and does not overwrite an earlier error
+ o logic in i2c_probe now correct
+ - add "vprintf()" function so that "panic()" function can be
+ technically correct
+ - many Hymod board changes
+
+* Patches by Robert Schwebel, 14 Jun 2003:
+ - add support for Logotronic DL datalogger board
+ - cleanup serial line after kermit binary download
+ - add debugX macro (debug level support)
+ - update mach-types.h to latest arm.linux.org.uk master list.
+
+* Patches by David Müller, 12 Jun 2003:
+ - rewrite of the S3C24X0 register definitions stuff
+ - "driver" for the built-in S3C24X0 RTC
+
+* Patches by Yuli Barcohen, 12 Jun 2003:
+ - Add MII support and Ethernet PHY initialization for MPC8260ADS board
+ - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
+ configuration word supplied by FPGA on some MPC8260ADS boards
+
+* Patch by Pantelis Antoniou, 10 Jun 2003:
+ Unify status LED interface
+
+* Add support for DS12887 RTC; add RTC support for ATC board
+
+* Patch by Nicolas Lacressonniere, 11 Jun 2003:
+ Modifications for Atmel AT91RM9200DK ARM920T based development kit
+ - Add Atmel DataFlash support for reading and writing.
+ - Add possibility to boot a Linux from DataFlash with BOOTM command.
+ - Add Flash detection on Atmel AT91RM9200DK
+ (between Atmel AT49BV1614 and AT49BV1614A flashes)
+ - Replace old Ethernet PHY layer functions
+ - Change link address
+
+* Patch by Frank Smith, 9 Jun 2003:
+ use CRIT_EXCEPTION for machine check on 4xx
+
+* Patch by Detlev Zundel, 13 Jun 2003:
+ added implementation of the "carinfo" command in cmd_immap.c
+
+* Fix CONFIG_NET_MULTI support in include/net.h
+
+* Patches by Kyle Harris, 13 Mar 2003:
+ - Add FAT partition support
+ - Add command support for FAT
+ - Add command support for MMC
+ ----
+ - Add Intel PXA support for video
+ - Add Intel PXA support for MMC
+ ----
+ - Enable MMC and FAT for lubbock board
+ - Other misc changes for lubbock board
+
+* Patch by Robert Schwebel, April 02, 2003:
+ fix for SMSC91111 driver
+
+* Patch by Vladimir Gurevich, 04 Jun 2003:
+ make ppc405 ethernet driver compatible with CONFIG_NET_MULTI option
+
+* Patch by Stefan Roese, 05 Jun 2003:
+ - PPC4xx: Fix bug for initial stack in data cache as pointed out by
+ Thomas Schaefer (tschaefer@giga-stream.de). Now inital stack in
+ data cache can be used even if the chip select is in use.
+ - CFG_RX_ETH_BUFFER added to set the ethernet receive buffer count
+ (see README for further description).
+ - Changed config files of CONFIG_EEPRO100 boards to use the
+ CFG_RX_ETH_BUFFER define.
+
+* Add support for RMU board
+
+* Add support for TQM862L at 100/50 MHz
+
+* Patch by Pantelis Antoniou, 02 Jun 2003:
+ major reconstruction of networking code;
+ add "ping" support (outgoing only!)
+
+* Patch by Denis Peter, 04 June 2003:
+ add support for the MIP405T board
+
+* Patches by Udi Finkelstein, 2 June 2003:
+ - Added support for custom keyboards, initialized by defining a
+ board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
+ - Added support for the RBC823 board.
+ - cpu/mpc8xx/lcd.c now automatically calculates the
+ Horizontal Pixel Count field.
+
+* Fix alignment problem in BOOTP (dhcp_leasetime option)
+ [pointed out by Nicolas Lacressonnière, 2 Jun 2003]
+
+* Patch by Mark Rakes, 14 May 2003:
+ add support for Intel e1000 gig cards.
+
+* Patch by Nye Liu, 3 Jun 2003:
+ fix critical typo in MAMR definition (include/mpc8xx.h)
+
+* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.
+
+* Patch by Klaus Heydeck, 2 Jun 2003
+ Minor changes for KUP4K configuration
+
+* Patch by Marc Singer, 29 May 2003:
+ Fixed rarp boot method for IA32 and other little-endian CPUs.
+
+* Patch by Marc Singer, 28 May 2003:
+ Added port I/O commands.
+
+* Patch by Matthew McClintock, 28 May 2003
+ - cpu/mpc824x/start.S: fix relocation code when booting from RAM
+ - minor patches for utx8245
+
+* Patch by Daniel Engström, 28 May 2003:
+ x86 update
+
+* Patch by Dave Ellis, 9 May 2003 + 27 May 2003:
+ add nand flash support to SXNI855T configuration
+ fix/extend nand flash support:
+ - fix 'nand erase' command so does not erase bad blocks
+ - fix 'nand write' command so does not write to bad blocks
+ - fix nand_probe() so handles no flash detected properly
+ - add doc/README.nand
+ - add .jffs2 and .oob options to nand read/write
+ - add 'nand bad' command to list bad blocks
+ - add 'clean' option to 'nand erase' to write JFFS2 clean markers
+ - make NAND read/write faster
+
+* Patch by Rune Torgersen, 23 May 2003:
+ Update for MPC8266ADS board
+
+* Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length
+ instead CFG_MONITOR_LEN is now only used to determine _at_compile_
+ _time_ (!) if the environment is embedded within the U-Boot image,
+ or in a separate flash sector.
+
+* Cleanup CFG_DER #defines in config files (wd maintained only)
+
+* Fix data abort exception handling for arm920t CPU
+
+* Fix alignment problems with flash driver for TRAB board
+
+* Patch by Donald White, 21 May 2003:
+ fix calculation of base address in pci_hose_config_device()
+
+* Fix bug in command line parsing: "cmd1;cmd2" is supposed to always
+ execute "cmd2", even if "cmd1" fails. Note that this is different
+ to "run var1 var2" where the contents of "var2" will NOT be
+ executed when a command in "var1" fails.
+
+* Add zero-copy ramdisk support (requires corresponding kernel support!)
+
+* Patch by Kyle Harris, 20 May 2003:
+ In preparation for an ixp port, rename cpu/xscale and arch-xscale
+ into cpu/pxa and arch-pxa.
+
+* Patch by Stefan Roese, 23 May 2003:
+ - IBM PPC405EP port added.
+ - CONFIG_UART1_CONSOLE added. If defined internal UART1 (and not
+ UART0) is used as default U-Boot console. PPC4xx only!
+ - esd ASH405 board added (PPC405EP based).
+ - BUBINGA405EP board added (PPC405EP based - IBM Eval Board).
+ - esd CPCI405AB board added.
+ - esd PMC405 board added.
+ - Update of some esd boards.
+
+* Patch by Denis Peter, 19 Mai 2003:
+ add support for the MIP405-3 board
+
+* Patch by Dave Ellis, 22 May 2003:
+ Fix problem with only partially cleared .bss segment
+
+* Patch by Rune Torgersen, 12 May 2003:
+ get PCI to work on a MPC8266ADS board; incorporate change to
+ cpu/mpc8260/pci.c to enable overrides of PCI memory parameters
+
+* Patch by Nye Liu, 1 May 2003:
+ minor patches for the FADS8xx
+
+* Patch by Thomas Schäfer, 28 Apr 2003:
+ Fix SPD handling for 256 ECC DIMM on Walnut
+
+* Add support for arbitrary bitmaps for TRAB's VFD command;
+ allow to pass boot bitmap addresses in environment variables;
+ allow for zero boot delay
+
+* Patch by Christian Geißinger, 19 May 2002:
+ On TRAB: wait until the dummy byte has been completely sent
+
+* Patch by David Updegraff, 22 Apr 2003:
+ update for CrayL1 board
+
+* Patch by Pantelis Antoniou, 21 Apr 2003:
+ add boot support for ARTOS (a proprietary OS)
+
+* Patch by Steven Scholz, 11 Apr 2003:
+ Add support for RTC DS1338
+
+* Patch by Rod Boyce, 24 Jan 2003:
+ Fix counting of extended partitions in diskboot command
+
+* Patch by Christophe Lindheimer, 20 May 2003:
+ allow the use of CFG_LOADS when CFG_NO_FLASH is set
+
+* Fix SDRAM timing on Purple board
+
+* Add support for CompactFlash on ATC board
+ (includes support for Intel 82365 and compatible PC Card controllers,
+ and Yenta-compatible PCI-to-CardBus controllers)
+
+* Patch by Mathijs Haarman, 08 May 2003:
+ Add lan91c96 driver (tested on Lubbock and custom PXA250 board only)
+
+* Fix problem with usage of "true" (undefined in current versions of bfd.h)
+
+* Add support for Promess ATC board
+
+* Patch by Keith Outwater, 28 Apr 2003:
+ - Miscellaneous corrections and additions to GEN860T board specific code.
+ - Added GEN860_SC variant to GEN860T.
+ - Miscellaneous corrections to GEN860T documentation.
+ - Correct duplicate entry in U-Boot CREDITS file.
+ - Add GEN860T_SC entry in MAINTAINERS file.
+ - Update CREDITS file with GEN860T_SC info.
+
+* Update Smiths Aerospace addresses in MAINTAINERS file
+
+* Fix error handling in hush's version of "run" command
+
+* LWMON extensions:
+ - Splashscreen support
+ - modem support
+ - sysmon support
+ - temperature dependend enabling of LCD
+
+* Allow booting from old "PPCBoot" disk partitions
+
+* Add support for TQM8255 Board / MPC8255 CPU
+
+======================================================================
+Changes for U-Boot 0.3.1:
+======================================================================
+
+* Make sure Block Lock Bits get cleared in R360MPI flash driver
+
+* MPC823 LCD driver: Fill color map backwards, to allow for steady
+ display when Linux takes over
+
+* Patch by Erwin Rol, 27 Feb 2003:
+ Add support for RTEMS (this time for real).
+
+* Add support for "bmp info" and "bmp display" commands to load
+ bitmap images; this can be used (for example in a "preboot"
+ command) to display a splash screen very quickly after poweron.
+
+* Add support for 133 MHz clock on INCA-IP board
+
+* Patch by Lutz Dennig, 10 Apr 2003:
+ Update for R360MPI board
+
+* Add new meaning to "autostart" environment variable:
+ If set to "no", a standalone image passed to the
+ "bootm" command will be copied to the load address
+ (and eventually uncompressed), but NOT be started.
+ This can be used to load and uncompress arbitrary
+ data.
+
+* Patch by Stefan Roese, 10 Apr 2003:
+ Changed DHCP client to use IP address from server option field #54
+ from the OFFER packet in the server option field #54 in the REQUEST
+ packet. This fixes a problem using a Windows 2000 DHCP server,
+ where the DHCP-server is not the TFTP-server.
+
+* Set max brightness for MN11236 displays on TRAB board
+
+* Add support for TQM862L modules
+
+======================================================================
+Changes for U-Boot 0.3.0:
+======================================================================
+
+* Patch by Arun Dharankar, 4 Apr 2003:
+ Add IDMA example code (tested on 8260 only)
+
+* Add support for Purple Board (MIPS64 5Kc)
+
+* Add support for MIPS64 5Kc CPUs
+
+* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS
+
+* Patch by Denis Peter, 04 Apr 2003:
+ - update MIP405-4 board
+
+* Patch by Stefan Roese, 4 Apr 2003:
+ - U-Boot version environment variable "ver" added
+ (CONFIG_VERSION_VARIABLE).
+ - Changed PPC405GPr version from A to B.
+ - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.
+
+* Patches by Denis Peter, 03 April 2003:
+ - fix PCI IRQs on MPL boards
+ - fix two more un-relocated pointer problems
+
+* Fix behaviour of "run" command:
+ - print error message iv variable does not exist
+ - terminate processing of arguments in case of error
+
+* Patches by Peter Figuli, 10 Mar 2003
+ - Add support for BTUART on PXA platform
+ - Add support for WEP EP250 (PXA) board
+
+* Fix flash problems on INCA-IP; add tool to allow bruning images to
+ flash using a BDI2000
+
+* Implement fix for I2C Edge Conditions problem for all boards that
+ use the bit-banging driver (common/soft_i2c.c)
+
+* Patch by Martin Winistoerfer, 23 Mar 2003
+ - Add port to MPC555/556 microcontrollers
+ - Add support for cmi customer board with
+ Intel 28F128J3A, 28F320J3A or 28F640J3A flash.
+
+* Patch by Rick Bronson, 28 Mar 2003:
+ - fix common/cmd_nand.c
+
+* Patch by Arun Dharankar, 24 Mar 2003:
+ - add threads / scheduler example code
+
+* Add patches by Robert Schwebel, 31 Mar 2003:
+ - add ctrl-c support for kermit download
+ - align bdinfo output on ARM
+ - csb226 board: bring in sync with innokom/memsetup.S
+ - csb226 board: fix MDREFR handling
+ - misc doc fixes / extensions
+ - innokom board: cleanup, MDREFR fix in memsetup.S, config update
+ - add BOOT_PROGRESS to armlinux.c
+
+* Add CPU ID, version, and clock speed for INCA-IP
+
+* Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board:
+ - fix SRAM and SDRAM memory sizing
+ - add status LED support
+ - add MAC address for second (SCC1) ethernet port
+
+* Update default environment for TQM8260 board
+
+* Patch by Rick Bronson, 16 Mar 2003:
+ - Add NAND flash support for reading, writing, and erasing NAND
+ flash (certain forms of which are called SmartMedia).
+ - Add support for Atmel AT91RM9200DK ARM920T based development kit.
+
+* Patches by Robert Schwebel, 19 Mar 2003:
+ - use arm-linux-gcc as default compiler for ARM
+ - fix i2c fixup code
+ - fix missing baudrate setting
+ - added $loadaddr / CFG_LOAD_ADDR support to loadb
+ - moved "ignoring trailing characters" _before_ u-boot wants to
+ print out diagnostics messages; removes bogus characters at the
+ end of transmission
+
+* Patch by John Zhan, 18 Mar 2003:
+ Add support for SinoVee Microsystems SC8xx boards
+
+* Patch by Rolf Offermanns, 21 Mar 2003:
+ ported the dnp1110 related changes from the current armboot cvs to
+ current u-boot cvs. smc91111 does not work. problem marked in
+ smc91111.c, grep for "FIXME".
+
+* Patch by Brian Auld, 25 Mar 2003:
+ Add support for STM flash chips on ebony board
+
+* Add PCI support for MPC8250 Boards (PM825 module)
+
+* Patch by Stefan Roese, 25 Mar 2003:
+ - PCI405 update.
+
+* Patch by Stefan Roese, 20 Mar 2003:
+ - CPCI4052 update (support for revision 3).
+ - Set edge conditioning circuitry on PPC405GPr for compatibility
+ to existing PPC405GP designs.
+ - Clip udiv to 5 bits on PPC405 (serial.c).
+
+* Extend INCAIP board support:
+ - add automatic RAM size detection
+ - add "bdinfo" command
+ - pass flash address and size to Linux kernel
+ - switch to 150 MHz clock
+
+* Avoid flicker on the TRAB's VFD by synchronizing the enable with
+ the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100
+ boards, version 153 for Rev. 200 boards).
+
+* Patch by Vladimir Gurevich, 12 Mar 2003:
+ Fix relocation problem of statically initialized string pointers
+ in common/cmd_pci.c
+
+* Patch by Kai-Uwe Blöm, 12 Mar 2003:
+ Cleanup & bug fixes for JFFS2 code:
+ - the memory mangement was broken. It caused havoc on malloc by
+ writing beyond the block boundaries.
+ - the length calculation for files was wrong, sometimes resulting
+ in short file reads.
+ - data copying now optionally takes fragment version numbers into
+ account, to avoid copying from older data.
+ See doc/README.JFFS2 for details.
+
+* Patch by Josef Wagner, 12 Mar 2003:
+ - 16/32 MB and 50/80 MHz support with auto-detection for IP860
+ - ETH05 and BEDBUG support for CU824
+ - added support for MicroSys CPC45
+ - new BOOTROM/FLASH0 and DOC base for PM826
+
+* Patch by Robert Schwebel, 12 Mar 2003:
+ Fix the chpart command on innokom board
+
+* Name cleanup:
+ mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h
+ s/PPCBoot/U-Boot/ in some files
+ s/pImage/uImage/ in some files
+
+* Patch by Detlev Zundel, 15 Jan 2003:
+ Fix '' command line quoting
+
+* Patch by The LEOX team, 19 Jan 2003:
+ - add support for the ELPT860 board
+ - add support for Dallas ds164x RTC
+
+* Patches by David Müller, 31 Jan 2003:
+ - minimal setup for CardBus bridges
+ - add EEPROM read/write support in the CS8900 driver
+ - add support for the builtin I2C controller in the Samsung s3c24x0 chips
+ - add support for MPL's VCMA9 (Samsung s3c2410 based) board
+
+* Patch by Steven Scholz, 04 Feb 2003:
+ add support for RTC DS1307
+
+* Patch by Reinhard Meyer, 5 Feb 2003:
+ fix PLPRCR/SCCR init sequence on 8xx to allow for
+ changes of EBDF by software
+
+* Patch by Vladimir Gurevich, 07 Feb 2003:
+ "API-compatibility patch" for 4xx I2C driver
+
+* TRAB fixes / extensions:
+ - Restore VFD brightness as saved in environment
+ - add support for Fujitsu flashes
+ - make sure both buzzers are turned off (drive low level)
+
+* Patches by Robert Schwebel, 06 Mar 2003:
+ - fix bug in BOOTP code (must use NetCopyIP)
+ - update of CSB226 port
+ - clear BSS segment on XScale
+ - added support for i2c_init_board() function
+ - update to the Innokom plattform
+
+* Extend support for redundand environments for configurations where
+ environment size < sector size
+
+* Patch by Rune Torgersen, 13 Feb 2003:
+ Add support for Motorola MPC8266ADS board
+
+* Patch by Kyle Harris, 19 Feb 2003:
+ patches for the Intel lubbock board:
+ memsetup.S - general cleanup (based on Robert's csb226 code)
+ flash.c - overhaul, actually works now
+ lubbock.c - fix init funcs to return proper value
+
+* Patch by Kenneth Johansson, 26 Feb 2003:
+ - Fixed off by one in RFTA calculation.
+ - No need to abort when LDF is lower than we can program it's only
+ minimum timing so clamp it to what we can do.
+ - Takes function pointer to function for reading the spd_nvram. Usefull
+ for faking data or hardcode a module without the nvram.
+ - fix other user for above change
+ - fix some comments.
+
+* Patches by Brian Waite, 26 Feb 2003:
+ - fix port for evb64260 board
+ - fix PCI for evb64260 board
+ - fix PCI scan
+
+* Patch by Reinhard Meyer, 1 Mar 2003:
+ Add support for EMK TOP860 Module
+
+* Patch by Yuli Barcohen, 02 Mar 2003:
+ Add SPD EEPROM support for MPC8260ADS board
+
+* Patch by Robert Schwebel, 21 Jan 2003:
+ - Add support for Innokom board
+ - Don't complain if "install" fails
+ - README cleanup (remove duplicated lines)
+ - Update PXA header files
+
+* Add documentation for existing POST code (doc/README.POST)
+
+* Patch by Laudney Ren, 15 Jan 2003:
+ Fix handling of redundand environment in "tools/envcrc.c"
+
+* Patch by Detlev Zundel, 28 Feb 2003:
+ Add bedbug support for 824x systems
+
+* Add support for 16 MB flash configuration of TRAB board
+
+* Patch by Erwin Rol, 27 Feb 2003:
+ Add support for RTEMS
+
+* Add image information to README
+
+* Patch by Stefan Roese, 18 Feb 2003:
+ CPCIISER4 configuration updated.
+
+* Patch by Stefan Roese, 17 Feb 2003:
+ Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port).
+
+* Patch by Stefan Roese, 13 Feb 2003:
+ Add "pcidelay" environment variable (in ms, enabled via
+ CONFIG_PCI_BOOTDELAY).
+ PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after
+ RST# to respond to configuration cycles (33MHz -> 1s).
+
+* Fix dual PCMCIA slot support (when running with just one
+ slot populated)
+
+* Add VFD type detection to trab board
+
+* extend drivers/cs8900.c driver to synchronize ethaddr environment
+ variable with value in the EEPROM
+
+* Patch by Stefan Roese, 10 Feb 2003:
+ Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c)
+
+* Add support for MIPS32 4Kc CPUs
+
+* Add support for INCA-IP Board
+
+======================================================================
+Changes for U-Boot 0.2.2:
+======================================================================
+
+* Add dual ethernet support on PM826
+
+* Add support for LXT971 PHY on PM826
+
+* Patch by Tord Andersson, 16 Jan 2003:
+ Fix flash sector count for TQM8xxL
+
+* Fix I2C EEPROM problem on ICU862 board (would only write the first
+ 16 bytes out of each 32 byte block)
+
+======================================================================
+Changes for U-Boot 0.2.1:
+======================================================================
+
+* Add support for V37 board
+ (patch by Jón Benediktsson, 11 Dec 2002)
+
+* Update baudrate in bd_info when it gets changed
+
+* Add watchdog trigger points while waiting for serial port
+ (so far only 8xx -- needed on LWMON with 100ms watchdog)
+
+* Improve command line tool to access the U-Boot's environment
+ (figuration of the utility, using a config file)
+
+* Add single quote support for (old) command line parser
+
+* Switch LWMON board default config from FRAM to EEPROM;
+ in POST, EEPROM shows up on 8 addresses
+
+======================================================================
+Changes for U-Boot 0.2.0:
+======================================================================
+
+* Use 1-byte-read instead of -write for iprobe() function
+ Add i2c commands to PM826 config
+
+* extend I2C POST code: check for list on known addresses
+
+* Improve log buffer code; use "loglevel" to decide which messages
+ to log on the console, too (like in Linux); get rid of "logstart"
+
+* Add command line tool to access the U-Boot's environment
+ (board-specific for TRAB now, to be fixed later)
+
+* Patch by Hans-Joerg Frieden, 06 Dec 2002
+ Fix misc problems with AmigaOne support
+
+* Patch by Chris Hallinan, 3 Dec 2002:
+ minor cleanup to the MPC8245 EPIC driver
+
+* Patch by Pierre Aubert , 28 Nov 2002
+ Add support for external (SIU) interrupts on MPC8xx
+
+* Patch by Pierre Aubert , 28 Nov 2002
+ Fix nested syscalls bug in standalone applications
+
+* Patch by David Müller, 27 Nov 2002:
+ fix output of "pciinfo" command for CardBus bridge devices.
+
+* Fix bug in TQM8260 board detection - boards got stuck when board ID
+ was not readable
+
+* Add LED indication for IDE activity on KUP4K board
+
+* Fix startup problems with VFD display on TRAB
+
+* Patch by Pierre Aubert, 20 Nov 2002
+ Add driver for Epson SED13806 graphic controller.
+ Add support for BMP logos in cfb_console driver.
+
+* Added support for both PCMCIA slots (at the same time!) on MPC8xx
+
+* Patch by Rod Boyce, 21 Nov 2002:
+ fix PCMCIA on MBX8xx board
+
+* Patch by Pierre Aubert , 21 Nov 2002
+ Add CFG_CPM_POST_WORD_ADDR to make the offset of the
+ bootmode word in DPRAM configurable
+
+* Patch by Daniel Engström, 18 Nov 2002:
+ Fixes for x86 port (mostly strings issues)
+
+* Patch by Ken Chou, 18 Nov 2002:
+ Fix for natsemi NIC cards (DP83815)
+
+* Patch by Pierre Aubert, 19 Nov 2002:
+ fix a bug for the MII configuration, and some warnings
+
+* Patch by Thomas Frieden, 13 Nov 2002:
+ Add code for AmigaOne board
+ (preliminary merge to U-Boot, still WIP)
+
+* Patch by Jon Diekema, 12 Nov 2002:
+ - Adding URL for IEEE OUI lookup
+ - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED
+ being defined.
+ - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and
+ root-on-nfs macros are designed to switch how the default boot
+ method gets defined.
+
+* Patch by Daniel Engström, 13 Nov 2002:
+ Add support for i386 architecture and AMD SC520 board
+
+* Patch by Pierre Aubert, 12 Nov 2002:
+ Add support for DOS filesystem and booting from DOS floppy disk
+
+* Patch by Jim Sandoz, 07 Nov 2002:
+ Increase number of network RX buffers (PKTBUFSRX in
+ "include/net.h") for EEPRO100 based boards (especially SP8240)
+ which showed "Receiver is not ready" errors when U-Boot was
+ processing the receive buffers slower than the network controller
+ was filling them.
+
+* Patch by Andreas Oberritter, 09 Nov 2002:
+ Change behaviour of NetLoop(): return -1 for errors, filesize
+ otherwise; return code 0 is valid an means no file loaded - in this
+ case the environment still gets updated!
+
+* Patches by Jon Diekema, 9 Nov 2002:
+ - improve ADC/DAC clocking on the SACSng board to align
+ the failing edges of LRCLK and SCLK
+ - sbc8260 configuration tweaks
+ - add status LED support for 82xx systems
+ - wire sspi/sspo commands into command handler; improved error
+ handlering
+ - add timestamp support and alternate memory test to the
+ SACSng configuration
+
+* Patch by Vince Husovsky, 7 Nov 2002:
+ Add "-n" to linker options to get rid of "Not enough room for
+ program headers" problem
+
+* Patch by David Müller, 05 Nov 2002
+ Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
+ so we can use an already existing name
+
+* Patch by Pierre Aubert, 05 Nov 2002
+ Hardware relatied improvments in FDC boot code
+
+* Patch by Holger Schurig, 5 Nov 2002:
+ Make the PXA really change it's frequency
+
+* Patch by Pierre Aubert, 05 Nov 2002
+ Add support for slave serial Spartan 2 FPGAs
+
+* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet
+ drivers
+
+* Add support for log buffer which can be passed to Linux kernel's
+ syslog mechanism; used especially for POST results.
+
+* Patch by Klaus Heydeck, 31 Oct 2002:
+ Add initial support for kup4k board
+
+* Patch by Robert Schwebel, 04 Nov 2002:
+ - use watchdog to reset PXA250 systems
+ - added progress callbacks to (some of the) ARM code
+ - update for Cogent CSB226 board
+
+* Add support for FPS860 board
+
+* Patch by Guillaume Alexandre,, 04 Nov 2002:
+ Improve PCI access on 32-bits Compact PCI bus
+
+* Fix mdelay() on TRAB - this was still the debugging version with
+ seconds instead of ms.
+
+* Patch by Robert Schwebel, 1 Nov 2002:
+ XScale related cleanup (affects all ARM boards)
+
+* Cleanup of names and README.
+
+======================================================================
+Notes for U-Boot 0.1.0:
+======================================================================
+
+This is the initial version of "Das U-Boot", the Universal Boot Loader.
+
+It is based on version 2.0.0 (the "Halloween Release") of PPCBoot.
+For information about the history of the project please see the
+PPCBoot project page at http://sourceforge.net/projects/ppcboot
+
+======================================================================
E: r.schwebel@pengutronix.de
D: Support for csb226, logodl and innokom boards (PXA2xx)
+N: Aaron Sells
+E: sellsa@embeddedplanet.com
+D: Support for EP82xxM
+
N: Art Shipkowski
E: art@videon-central.com
D: Support for NetSilicon NS7520
MPC8541CDS MPC8541
MPC8555CDS MPC8555
+ MPC8641HPCN MPC8641D
+
Dan Malek <dan@embeddededge.com>
STxGP3 MPC85xx
ocotea PPC440GX
p3p440 PPC440GP
pcs440ep PPC440EP
+ sequoia PPC440EPx
sycamore PPC405GPr
walnut PPC405GP
yellowstone PPC440GR
MPC8266ADS MPC8266
+
+David Updegraff <dave@cray.com>
+
+ CRAYL1 PPC4xx
+
Josef Wagner <Wagner@Microsys.de>
CPC45 MPC8245
RPXClassic MPC8xx
RPXlite MPC8xx
- CRAYL1 PPC4xx
ERIC PPC4xx
MOUSSE MPC824x
r5200 mcf52x2
+#########################################################################
+# AVR32 Systems: #
+# #
+# Maintainer Name, Email Address #
+# Board CPU #
+#########################################################################
+
+Haavard Skinnemoen <hskinnemoen@atmel.com>
+
+ ATSTK1000 AT32AP7000
+
#########################################################################
# End of MAINTAINERS list #
#########################################################################
MAKE=make
fi
-[ -d LOG ] || mkdir LOG || exit 1
+if [ "${MAKEALL_LOGDIR}" ] ; then
+ LOG_DIR=${MAKEALL_LOGDIR}
+else
+ LOG_DIR="LOG"
+fi
+
+if [ ! "${BUILD_DIR}" ] ; then
+ BUILD_DIR="."
+fi
+
+[ -d ${LOG_DIR} ] || mkdir ${LOG_DIR} || exit 1
LIST=""
#########################################################################
LIST_5xxx=" \
- BC3450 cpci5200 EVAL5200 icecube_5100 \
- icecube_5200 lite5200b mcc200 o2dnt \
- pf5200 PM520 TB5200 Total5100 \
- Total5200 Total5200_Rev2 TQM5200 TQM5200_B \
- TQM5200S \
+ BC3450 cpci5200 EVAL5200 fo300 \
+ icecube_5100 icecube_5200 lite5200b mcc200 \
+ o2dnt pf5200 PM520 TB5200 \
+ Total5100 Total5200 Total5200_Rev2 TQM5200 \
+ TQM5200_B TQM5200S v38b \
"
#########################################################################
LIST_4xx=" \
ADCIOP AP1000 AR405 ASH405 \
- bubinga CANBT CMS700 CPCI2DP \
- CPCI405 CPCI4052 CPCI405AB CPCI405DT \
- CPCI440 CPCIISER4 CRAYL1 csb272 \
- csb472 DASA_SIM DP405 DU405 \
- ebony ERIC EXBITGEN G2000 \
- HH405 HUB405 JSE KAREF \
- luan METROBOX MIP405 MIP405T \
- ML2 ml300 ocotea OCRTC \
- ORSG p3p440 PCI405 pcs440ep \
- PIP405 PLU405 PMC405 PPChameleonEVB \
- sbc405 VOH405 VOM405 W7OLMC \
- W7OLMG walnut WUH405 XPEDITE1K \
- yellowstone yosemite yucca bamboo \
+ bamboo bubinga CANBT CMS700 \
+ CPCI2DP CPCI405 CPCI4052 CPCI405AB \
+ CPCI405DT CPCI440 CPCIISER4 CRAYL1 \
+ csb272 csb472 DASA_SIM DP405 \
+ DU405 ebony ERIC EXBITGEN \
+ G2000 HH405 HUB405 JSE \
+ KAREF luan METROBOX MIP405 \
+ MIP405T ML2 ml300 ocotea \
+ OCRTC ORSG p3p440 PCI405 \
+ pcs440ep PIP405 PLU405 PMC405 \
+ PPChameleonEVB sbc405 sequoia sequoia_nand \
+ VOH405 VOM405 W7OLMC W7OLMG \
+ walnut WUH405 XPEDITE1K yellowstone \
+ yosemite yucca bamboo \
"
#########################################################################
LIST_8260=" \
atc cogent_mpc8260 CPU86 CPU87 \
- ep8248 ep8260 gw8260 hymod \
- IPHASE4539 ISPAN MPC8260ADS MPC8266ADS \
- MPC8272ADS PM826 PM828 ppmc8260 \
- Rattler8248 RPXsuper rsdproto sacsng \
- sbc8260 SCM TQM8260_AC TQM8260_AD \
- TQM8260_AE ZPC1900 \
+ ep8248 ep8260 ep82xxm gw8260 \
+ hymod IPHASE4539 ISPAN MPC8260ADS \
+ MPC8266ADS MPC8272ADS PM826 PM828 \
+ ppmc8260 Rattler8248 RPXsuper rsdproto \
+ sacsng sbc8260 SCM TQM8260_AC \
+ TQM8260_AD TQM8260_AE ZPC1900 \
"
#########################################################################
r5200 M5271EVB \
"
+#########################################################################
+## AVR32 Systems
+#########################################################################
+
+LIST_avr32="atstk1002"
+
#-----------------------------------------------------------------------
#----- for now, just run PPC by default -----
${MAKE} distclean >/dev/null
${MAKE} ${target}_config
- ${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
- ${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
+
+ ${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
+ | tee ${LOG_DIR}/$target.ERR
+
+ ${CROSS_COMPILE:-ppc_8xx-}size ${BUILD_DIR}/u-boot \
+ | tee -a ${LOG_DIR}/$target.MAKELOG
}
#-----------------------------------------------------------------------
mips|mips_el| \
nios|nios2| \
x86|I486| \
- coldfire)
+ coldfire| \
+ avr32)
for target in `eval echo '$LIST_'${arg}`
do
build_target ${target}
VERSION = 1
PATCHLEVEL = 1
-SUBLEVEL = 4
+SUBLEVEL = 6
EXTRAVERSION =
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
-VERSION_FILE = include/version_autogenerated.h
+VERSION_FILE = $(obj)include/version_autogenerated.h
HOSTARCH := $(shell uname -m | \
sed -e s/i.86/i386/ \
# Deal with colliding definitions from tcsh etc.
VENDOR=
+#########################################################################
+#
+# U-boot build supports producing a object files to the separate external
+# directory. Two use cases are supported:
+#
+# 1) Add O= to the make command line
+# 'make O=/tmp/build all'
+#
+# 2) Set environement variable BUILD_DIR to point to the desired location
+# 'export BUILD_DIR=/tmp/build'
+# 'make'
+#
+# The second approach can also be used with a MAKEALL script
+# 'export BUILD_DIR=/tmp/build'
+# './MAKEALL'
+#
+# Command line 'O=' setting overrides BUILD_DIR environent variable.
+#
+# When none of the above methods is used the local build is performed and
+# the object files are placed in the source directory.
+#
+
+ifdef O
+ifeq ("$(origin O)", "command line")
+BUILD_DIR := $(O)
+endif
+endif
+
+ifneq ($(BUILD_DIR),)
+saved-output := $(BUILD_DIR)
+
+# Attempt to create a output directory.
+$(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR})
+
+# Verify if it was successful.
+BUILD_DIR := $(shell cd $(BUILD_DIR) && /bin/pwd)
+$(if $(BUILD_DIR),,$(error output directory "$(saved-output)" does not exist))
+endif # ifneq ($(BUILD_DIR),)
+
+OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR))
+SRCTREE := $(CURDIR)
+TOPDIR := $(SRCTREE)
+LNDIR := $(OBJTREE)
+export TOPDIR SRCTREE OBJTREE
+
+MKCONFIG := $(SRCTREE)/mkconfig
+export MKCONFIG
+
+ifneq ($(OBJTREE),$(SRCTREE))
+REMOTE_BUILD := 1
+export REMOTE_BUILD
+endif
+
+# $(obj) and (src) are defined in config.mk but here in main Makefile
+# we also need them before config.mk is included which is the case for
+# some targets like unconfig, clean, clobber, distclean, etc.
+ifneq ($(OBJTREE),$(SRCTREE))
+obj := $(OBJTREE)/
+src := $(SRCTREE)/
+else
+obj :=
+src :=
+endif
+export obj src
+
#########################################################################
-TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi)
-export TOPDIR
+ifeq ($(OBJTREE)/include/config.mk,$(wildcard $(OBJTREE)/include/config.mk))
-ifeq (include/config.mk,$(wildcard include/config.mk))
# load ARCH, BOARD, and CPU configuration
-include include/config.mk
+include $(OBJTREE)/include/config.mk
export ARCH CPU BOARD VENDOR SOC
+
ifndef CROSS_COMPILE
ifeq ($(HOSTARCH),ppc)
CROSS_COMPILE =
ifeq ($(ARCH),blackfin)
CROSS_COMPILE = bfin-elf-
endif
+ifeq ($(ARCH),avr32)
+CROSS_COMPILE = avr32-
+endif
endif
endif
# load other configuration
include $(TOPDIR)/config.mk
-
#########################################################################
# U-Boot objects....order is important (i.e. start must be first)
ifeq ($(CPU),mpc85xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
+ifeq ($(CPU),mpc86xx)
+OBJS += cpu/$(CPU)/resetvec.o
+endif
ifeq ($(CPU),bf533)
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU)/cplbmgr.o cpu/$(CPU)/flush.o
endif
+OBJS := $(addprefix $(obj),$(OBJS))
+
LIBS = lib_generic/libgeneric.a
LIBS += board/$(BOARDDIR)/lib$(BOARD).a
LIBS += cpu/$(CPU)/lib$(CPU).a
LIBS += post/libpost.a post/cpu/libcpu.a
LIBS += common/libcommon.a
LIBS += $(BOARDLIBS)
+
+LIBS := $(addprefix $(obj),$(LIBS))
.PHONY : $(LIBS)
# Add GCC lib
PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
-
# The "tools" are needed early, so put this first
# Don't include stuff already done in $(LIBS)
SUBDIRS = tools \
post/cpu
.PHONY : $(SUBDIRS)
+ifeq ($(CONFIG_NAND_U_BOOT),y)
+NAND_SPL = nand_spl
+U_BOOT_NAND = $(obj)u-boot-nand.bin
+endif
+
+__OBJS := $(subst $(obj),,$(OBJS))
+__LIBS := $(subst $(obj),,$(LIBS))
+
#########################################################################
#########################################################################
-ALL = u-boot.srec u-boot.bin System.map
+ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
all: $(ALL)
-u-boot.hex: u-boot
+$(obj)u-boot.hex: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
-u-boot.srec: u-boot
+$(obj)u-boot.srec: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
-u-boot.bin: u-boot
+$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-u-boot.img: u-boot.bin
+$(obj)u-boot.img: $(obj)u-boot.bin
./tools/mkimage -A $(ARCH) -T firmware -C none \
-a $(TEXT_BASE) -e 0 \
-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
-u-boot.dis: u-boot
+$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
-u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
+$(obj)u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
- $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
- --start-group $(LIBS) --end-group $(PLATFORM_LIBS) \
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
+$(OBJS):
+ $(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
+
$(LIBS):
- $(MAKE) -C `dirname $@`
+ $(MAKE) -C $(dir $(subst $(obj),,$@))
$(SUBDIRS):
$(MAKE) -C $@ all
+$(NAND_SPL): version
+ $(MAKE) -C nand_spl/board/$(BOARDDIR) all
+
+$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin
+ cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
+
version:
@echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \
echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \
echo "\"" >> $(VERSION_FILE)
gdbtools:
- $(MAKE) -C tools/gdb || exit 1
+ $(MAKE) -C tools/gdb all || exit 1
+
+updater:
+ $(MAKE) -C tools/updater all || exit 1
+
+env:
+ $(MAKE) -C tools/env all || exit 1
depend dep:
- @for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir .depend ; done
+ for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
-tags:
- ctags -w `find $(SUBDIRS) include \
+tags ctags:
+ ctags -w -o $(OBJTREE)/ctags `find $(SUBDIRS) include \
lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
fs/cramfs fs/fat fs/fdos fs/jffs2 \
net disk rtc dtt drivers drivers/sk98lin common \
\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
etags:
- etags -a `find $(SUBDIRS) include \
+ etags -a -o $(OBJTREE)/etags `find $(SUBDIRS) include \
lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
fs/cramfs fs/fat fs/fdos fs/jffs2 \
net disk rtc dtt drivers drivers/sk98lin common \
\( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
-System.map: u-boot
+$(obj)System.map: $(obj)u-boot
@$(NM) $< | \
grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
- sort > System.map
+ sort > $(obj)System.map
#########################################################################
else
-all install u-boot u-boot.srec depend dep:
+all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
+$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
+$(SUBDIRS) version gdbtools updater env depend \
+dep tags ctags etags $(obj)System.map:
@echo "System not configured - see README" >&2
@ exit 1
endif
+.PHONY : CHANGELOG
+CHANGELOG:
+ git log --no-merges U-Boot-1_1_5.. | \
+ unexpand -a | sed -e 's/\s\s*$$//' > $@
+
#########################################################################
unconfig:
- @rm -f include/config.h include/config.mk board/*/config.tmp
+ @rm -f $(obj)include/config.h $(obj)include/config.mk \
+ $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp
#========================================================================
# PowerPC
#########################################################################
canmb_config: unconfig
- @./mkconfig -a canmb ppc mpc5xxx canmb
+ @$(MKCONFIG) -a canmb ppc mpc5xxx canmb
cmi_mpc5xx_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc5xx cmi
+ @$(MKCONFIG) $(@:_config=) ppc mpc5xx cmi
PATI_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc5xx pati mpl
+ @$(MKCONFIG) $(@:_config=) ppc mpc5xx pati mpl
#########################################################################
## MPC5xxx Systems
#########################################################################
aev_config: unconfig
- @./mkconfig -a aev ppc mpc5xxx tqm5200
+ @$(MKCONFIG) -a aev ppc mpc5xxx tqm5200
BC3450_config: unconfig
- @./mkconfig -a BC3450 ppc mpc5xxx bc3450
+ @$(MKCONFIG) -a BC3450 ppc mpc5xxx bc3450
cpci5200_config: unconfig
- @./mkconfig -a cpci5200 ppc mpc5xxx cpci5200 esd
+ @$(MKCONFIG) -a cpci5200 ppc mpc5xxx cpci5200 esd
hmi1001_config: unconfig
- @./mkconfig hmi1001 ppc mpc5xxx hmi1001
+ @$(MKCONFIG) hmi1001 ppc mpc5xxx hmi1001
Lite5200_config \
Lite5200_LOWBOOT_config \
icecube_5200_DDR_LOWBOOT_config \
icecube_5200_DDR_LOWBOOT08_config \
icecube_5100_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/icecube
+ @ >$(obj)include/config.h
@[ -z "$(findstring LOWBOOT_,$@)" ] || \
{ if [ "$(findstring DDR,$@)" ] ; \
- then echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
- else echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
+ then echo "TEXT_BASE = 0xFF800000" >$(obj)board/icecube/config.tmp ; \
+ else echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \
fi ; \
echo "... with LOWBOOT configuration" ; \
}
@[ -z "$(findstring LOWBOOT08,$@)" ] || \
- { echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
+ { echo "TEXT_BASE = 0xFF800000" >$(obj)board/icecube/config.tmp ; \
echo "... with 8 MB flash only" ; \
echo "... with LOWBOOT configuration" ; \
}
@[ -z "$(findstring DDR,$@)" ] || \
- { echo "#define CONFIG_MPC5200_DDR" >>include/config.h ; \
+ { echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h ; \
echo "... DDR memory revision" ; \
}
@[ -z "$(findstring 5200,$@)" ] || \
- { echo "#define CONFIG_MPC5200" >>include/config.h ; \
+ { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \
echo "... with MPC5200 processor" ; \
}
@[ -z "$(findstring 5100,$@)" ] || \
- { echo "#define CONFIG_MGT5100" >>include/config.h ; \
+ { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \
echo "... with MGT5100 processor" ; \
}
- @./mkconfig -a IceCube ppc mpc5xxx icecube
+ @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
+
+v38b_config: unconfig
+ @./mkconfig -a v38b ppc mpc5xxx v38b
inka4x0_config: unconfig
- @./mkconfig inka4x0 ppc mpc5xxx inka4x0
+ @$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
lite5200b_config \
lite5200b_LOWBOOT_config: unconfig
- @ >include/config.h
- @ echo "#define CONFIG_MPC5200_DDR" >>include/config.h
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/icecube
+ @ >$(obj)include/config.h
+ @ echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h
@ echo "... DDR memory revision"
- @ echo "#define CONFIG_MPC5200" >>include/config.h
- @ echo "#define CONFIG_LITE5200B" >>include/config.h
+ @ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h
+ @ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h
@[ -z "$(findstring LOWBOOT_,$@)" ] || \
- { echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \
+ { echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \
echo "... with LOWBOOT configuration" ; \
}
@ echo "... with MPC5200B processor"
- @./mkconfig -a IceCube ppc mpc5xxx icecube
+ @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
mcc200_config \
-mcc200_SDRAM \
-mcc200_highboot \
-mcc200_highboot_SDRAM: unconfig
- @ >include/config.h
+mcc200_SDRAM_config \
+mcc200_highboot_config \
+mcc200_COM12_config \
+mcc200_COM12_SDRAM_config \
+mcc200_COM12_highboot_config \
+mcc200_COM12_highboot_SDRAM_config \
+mcc200_highboot_SDRAM_config \
+prs200_config \
+prs200_DDR_config \
+prs200_highboot_config \
+prs200_highboot_DDR_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/mcc200
+ @ >$(obj)include/config.h
@[ -n "$(findstring highboot,$@)" ] || \
{ echo "... with lowboot configuration" ; \
}
@[ -z "$(findstring highboot,$@)" ] || \
- { echo "TEXT_BASE = 0xFFF00000" >board/mcc200/config.tmp ; \
+ { echo "TEXT_BASE = 0xFFF00000" >$(obj)board/mcc200/config.tmp ; \
echo "... with highboot configuration" ; \
}
@[ -n "$(findstring _SDRAM,$@)" ] || \
- { echo "... with DDR" ; \
+ { if [ -n "$(findstring mcc200,$@)" ]; \
+ then \
+ echo "... with DDR" ; \
+ else \
+ if [ -n "$(findstring _DDR,$@)" ];\
+ then \
+ echo "... with DDR" ; \
+ else \
+ echo "#define CONFIG_MCC200_SDRAM" >>$(obj)include/config.h ;\
+ echo "... with SDRAM" ; \
+ fi; \
+ fi; \
}
@[ -z "$(findstring _SDRAM,$@)" ] || \
- { echo "#define CONFIG_MCC200_SDRAM" >>include/config.h ; \
+ { echo "#define CONFIG_MCC200_SDRAM" >>$(obj)include/config.h ; \
echo "... with SDRAM" ; \
}
- @./mkconfig -a mcc200 ppc mpc5xxx mcc200
+ @[ -z "$(findstring COM12,$@)" ] || \
+ { echo "#define CONFIG_CONSOLE_COM12" >>$(obj)include/config.h ; \
+ echo "... with console on COM12" ; \
+ }
+ @[ -z "$(findstring prs200,$@)" ] || \
+ { echo "#define CONFIG_PRS200" >>$(obj)include/config.h ;\
+ }
+ @$(MKCONFIG) -n $@ -a mcc200 ppc mpc5xxx mcc200
o2dnt_config:
- @./mkconfig o2dnt ppc mpc5xxx o2dnt
+ @$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt
pf5200_config: unconfig
- @./mkconfig pf5200 ppc mpc5xxx pf5200 esd
+ @$(MKCONFIG) pf5200 ppc mpc5xxx pf5200 esd
PM520_config \
PM520_DDR_config \
PM520_ROMBOOT_config \
PM520_ROMBOOT_DDR_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring DDR,$@)" ] || \
- { echo "#define CONFIG_MPC5200_DDR" >>include/config.h ; \
+ { echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h ; \
echo "... DDR memory revision" ; \
}
@[ -z "$(findstring ROMBOOT,$@)" ] || \
- { echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
+ { echo "#define CONFIG_BOOT_ROM" >>$(obj)include/config.h ; \
echo "... booting from 8-bit flash" ; \
}
- @./mkconfig -a PM520 ppc mpc5xxx pm520
+ @$(MKCONFIG) -a PM520 ppc mpc5xxx pm520
smmaco4_config: unconfig
- @./mkconfig -a smmaco4 ppc mpc5xxx tqm5200
+ @$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200
spieval_config: unconfig
- @./mkconfig -a spieval ppc mpc5xxx tqm5200
+ @$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200
TB5200_B_config \
TB5200_config: unconfig
+ @mkdir -p $(obj)include
@[ -z "$(findstring _B,$@)" ] || \
- { echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
+ { echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \
echo "... with MPC5200B processor" ; \
}
- @./mkconfig -n $@ -a TB5200 ppc mpc5xxx tqm5200
+ @$(MKCONFIG) -n $@ -a TB5200 ppc mpc5xxx tqm5200
MINI5200_config \
EVAL5200_config \
TOP5200_config: unconfig
- @ echo "#define CONFIG_$(@:_config=) 1" >include/config.h
- @./mkconfig -n $@ -a TOP5200 ppc mpc5xxx top5200 emk
+ @mkdir -p $(obj)include
+ @ echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
+ @$(MKCONFIG) -n $@ -a TOP5200 ppc mpc5xxx top5200 emk
Total5100_config \
Total5200_config \
Total5200_lowboot_config \
Total5200_Rev2_config \
Total5200_Rev2_lowboot_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/total5200
+ @ >$(obj)include/config.h
@[ -z "$(findstring 5100,$@)" ] || \
- { echo "#define CONFIG_MGT5100" >>include/config.h ; \
+ { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \
echo "... with MGT5100 processor" ; \
}
@[ -z "$(findstring 5200,$@)" ] || \
- { echo "#define CONFIG_MPC5200" >>include/config.h ; \
+ { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \
echo "... with MPC5200 processor" ; \
}
@[ -n "$(findstring Rev,$@)" ] || \
- { echo "#define CONFIG_TOTAL5200_REV 1" >>include/config.h ; \
+ { echo "#define CONFIG_TOTAL5200_REV 1" >>$(obj)include/config.h ; \
echo "... revision 1 board" ; \
}
@[ -z "$(findstring Rev2_,$@)" ] || \
- { echo "#define CONFIG_TOTAL5200_REV 2" >>include/config.h ; \
+ { echo "#define CONFIG_TOTAL5200_REV 2" >>$(obj)include/config.h ; \
echo "... revision 2 board" ; \
}
@[ -z "$(findstring lowboot_,$@)" ] || \
- { echo "TEXT_BASE = 0xFE000000" >board/total5200/config.tmp ; \
+ { echo "TEXT_BASE = 0xFE000000" >$(obj)board/total5200/config.tmp ; \
echo "... with lowboot configuration" ; \
}
- @./mkconfig -a Total5200 ppc mpc5xxx total5200
+ @$(MKCONFIG) -a Total5200 ppc mpc5xxx total5200
-TQM5200_config \
-TQM5200_B_config \
-TQM5200_B_HIGHBOOT_config \
+cam5200_config \
+fo300_config \
+MiniFAP_config \
TQM5200S_config \
TQM5200S_HIGHBOOT_config \
-TQM5200_STK100_config \
-cam5200_config \
-MiniFAP_config: unconfig
- @ >include/config.h
- @[ -z "$(findstring MiniFAP,$@)" ] || \
- { echo "#define CONFIG_MINIFAP" >>include/config.h ; \
- echo "... TQM5200_AC on MiniFAP" ; \
- }
+TQM5200_B_config \
+TQM5200_B_HIGHBOOT_config \
+TQM5200_config \
+TQM5200_STK100_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/tqm5200
+ @ >$(obj)include/config.h
@[ -z "$(findstring cam5200,$@)" ] || \
- { echo "#define CONFIG_CAM5200" >>include/config.h ; \
- echo "#define CONFIG_TQM5200S" >>include/config.h ; \
- echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
+ { echo "#define CONFIG_CAM5200" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_TQM5200S" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \
echo "... TQM5200S on Cam5200" ; \
}
+ @[ -z "$(findstring fo300,$@)" ] || \
+ { echo "#define CONFIG_FO300" >>$(obj)include/config.h ; \
+ echo "... TQM5200 on FO300" ; \
+ }
+ @[ -z "$(findstring MiniFAP,$@)" ] || \
+ { echo "#define CONFIG_MINIFAP" >>$(obj)include/config.h ; \
+ echo "... TQM5200_AC on MiniFAP" ; \
+ }
@[ -z "$(findstring STK100,$@)" ] || \
- { echo "#define CONFIG_STK52XX_REV100" >>include/config.h ; \
+ { echo "#define CONFIG_STK52XX_REV100" >>$(obj)include/config.h ; \
echo "... on a STK52XX.100 base board" ; \
}
@[ -z "$(findstring TQM5200_B,$@)" ] || \
- { echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
+ { echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring TQM5200S,$@)" ] || \
- { echo "#define CONFIG_TQM5200S" >>include/config.h ; \
- echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
+ { echo "#define CONFIG_TQM5200S" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring HIGHBOOT,$@)" ] || \
- { echo "TEXT_BASE = 0xFFF00000" >board/tqm5200/config.tmp ; \
+ { echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \
}
- @./mkconfig -n $@ -a TQM5200 ppc mpc5xxx tqm5200
+ @$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200
#########################################################################
## MPC8xx Systems
Adder87x_config \
AdderII_config \
: unconfig
+ @mkdir -p $(obj)include
$(if $(findstring AdderII,$@), \
- @echo "#define CONFIG_MPC852T" > include/config.h)
- @./mkconfig -a Adder ppc mpc8xx adder
+ @echo "#define CONFIG_MPC852T" > $(obj)include/config.h)
+ @$(MKCONFIG) -a Adder ppc mpc8xx adder
AdderUSB_config: unconfig
@./mkconfig -a AdderUSB ppc mpc8xx adder
MPC86xADS_config \
MPC885ADS_config \
FADS860T_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx fads
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx fads
AMX860_config : unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx amx860 westel
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx amx860 westel
c2mon_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx c2mon
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx c2mon
CCM_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx CCM siemens
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx CCM siemens
cogent_mpc8xx_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx cogent
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx cogent
ELPT860_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx elpt860 LEOX
EP88x_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx ep88x
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx ep88x
ESTEEM192E_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx esteem192e
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx esteem192e
ETX094_config : unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx etx094
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx etx094
FLAGADM_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx flagadm
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx flagadm
xtract_GEN860T = $(subst _SC,,$(subst _config,,$1))
GEN860T_SC_config \
GEN860T_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring _SC,$@)" ] || \
- { echo "#define CONFIG_SC" >>include/config.h ; \
+ { echo "#define CONFIG_SC" >>$(obj)include/config.h ; \
echo "With reduced H/W feature set (SC)..." ; \
}
- @./mkconfig -a $(call xtract_GEN860T,$@) ppc mpc8xx gen860t
+ @$(MKCONFIG) -a $(call xtract_GEN860T,$@) ppc mpc8xx gen860t
GENIETV_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx genietv
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx genietv
GTH_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx gth
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx gth
hermes_config : unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx hermes
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx hermes
HMI10_config : unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx
IAD210_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx IAD210 siemens
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx IAD210 siemens
xtract_ICU862 = $(subst _100MHz,,$(subst _config,,$1))
ICU862_100MHz_config \
ICU862_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring _100MHz,$@)" ] || \
- { echo "#define CONFIG_100MHz" >>include/config.h ; \
+ { echo "#define CONFIG_100MHz" >>$(obj)include/config.h ; \
echo "... with 100MHz system clock" ; \
}
- @./mkconfig -a $(call xtract_ICU862,$@) ppc mpc8xx icu862
+ @$(MKCONFIG) -a $(call xtract_ICU862,$@) ppc mpc8xx icu862
IP860_config : unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx ip860
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx ip860
IVML24_256_config \
IVML24_128_config \
IVML24_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring IVML24_config,$@)" ] || \
- { echo "#define CONFIG_IVML24_16M" >>include/config.h ; \
+ { echo "#define CONFIG_IVML24_16M" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring IVML24_128_config,$@)" ] || \
- { echo "#define CONFIG_IVML24_32M" >>include/config.h ; \
+ { echo "#define CONFIG_IVML24_32M" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring IVML24_256_config,$@)" ] || \
- { echo "#define CONFIG_IVML24_64M" >>include/config.h ; \
+ { echo "#define CONFIG_IVML24_64M" >>$(obj)include/config.h ; \
}
- @./mkconfig -a IVML24 ppc mpc8xx ivm
+ @$(MKCONFIG) -a IVML24 ppc mpc8xx ivm
IVMS8_256_config \
IVMS8_128_config \
IVMS8_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring IVMS8_config,$@)" ] || \
- { echo "#define CONFIG_IVMS8_16M" >>include/config.h ; \
+ { echo "#define CONFIG_IVMS8_16M" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring IVMS8_128_config,$@)" ] || \
- { echo "#define CONFIG_IVMS8_32M" >>include/config.h ; \
+ { echo "#define CONFIG_IVMS8_32M" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring IVMS8_256_config,$@)" ] || \
- { echo "#define CONFIG_IVMS8_64M" >>include/config.h ; \
+ { echo "#define CONFIG_IVMS8_64M" >>$(obj)include/config.h ; \
}
- @./mkconfig -a IVMS8 ppc mpc8xx ivm
+ @$(MKCONFIG) -a IVMS8 ppc mpc8xx ivm
KUP4K_config : unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx kup4k kup
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx kup4k kup
KUP4X_config : unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx kup4x kup
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx kup4x kup
LANTEC_config : unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx lantec
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx lantec
lwmon_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx lwmon
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx lwmon
MBX_config \
MBX860T_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx mbx8xx
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx
MHPC_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx mhpc eltec
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
MVS1_config : unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx mvs1
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx mvs1
xtract_NETVIA = $(subst _V2,,$(subst _config,,$1))
NETVIA_V2_config \
NETVIA_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring NETVIA_config,$@)" ] || \
- { echo "#define CONFIG_NETVIA_VERSION 1" >>include/config.h ; \
+ { echo "#define CONFIG_NETVIA_VERSION 1" >>$(obj)include/config.h ; \
echo "... Version 1" ; \
}
@[ -z "$(findstring NETVIA_V2_config,$@)" ] || \
- { echo "#define CONFIG_NETVIA_VERSION 2" >>include/config.h ; \
+ { echo "#define CONFIG_NETVIA_VERSION 2" >>$(obj)include/config.h ; \
echo "... Version 2" ; \
}
- @./mkconfig -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia
+ @$(MKCONFIG) -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia
xtract_NETPHONE = $(subst _V2,,$(subst _config,,$1))
NETPHONE_V2_config \
NETPHONE_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring NETPHONE_config,$@)" ] || \
- { echo "#define CONFIG_NETPHONE_VERSION 1" >>include/config.h ; \
+ { echo "#define CONFIG_NETPHONE_VERSION 1" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring NETPHONE_V2_config,$@)" ] || \
- { echo "#define CONFIG_NETPHONE_VERSION 2" >>include/config.h ; \
+ { echo "#define CONFIG_NETPHONE_VERSION 2" >>$(obj)include/config.h ; \
}
- @./mkconfig -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone
+ @$(MKCONFIG) -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone
xtract_NETTA = $(subst _SWAPHOOK,,$(subst _6412,,$(subst _ISDN,,$(subst _config,,$1))))
NETTA_ISDN_config \
NETTA_6412_config \
NETTA_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring ISDN_,$@)" ] || \
- { echo "#define CONFIG_NETTA_ISDN 1" >>include/config.h ; \
+ { echo "#define CONFIG_NETTA_ISDN 1" >>$(obj)include/config.h ; \
}
@[ -n "$(findstring ISDN_,$@)" ] || \
- { echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \
+ { echo "#undef CONFIG_NETTA_ISDN" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring 6412_,$@)" ] || \
- { echo "#define CONFIG_NETTA_6412 1" >>include/config.h ; \
+ { echo "#define CONFIG_NETTA_6412 1" >>$(obj)include/config.h ; \
}
@[ -n "$(findstring 6412_,$@)" ] || \
- { echo "#undef CONFIG_NETTA_6412" >>include/config.h ; \
+ { echo "#undef CONFIG_NETTA_6412" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring SWAPHOOK_,$@)" ] || \
- { echo "#define CONFIG_NETTA_SWAPHOOK 1" >>include/config.h ; \
+ { echo "#define CONFIG_NETTA_SWAPHOOK 1" >>$(obj)include/config.h ; \
}
@[ -n "$(findstring SWAPHOOK_,$@)" ] || \
- { echo "#undef CONFIG_NETTA_SWAPHOOK" >>include/config.h ; \
+ { echo "#undef CONFIG_NETTA_SWAPHOOK" >>$(obj)include/config.h ; \
}
- @./mkconfig -a $(call xtract_NETTA,$@) ppc mpc8xx netta
+ @$(MKCONFIG) -a $(call xtract_NETTA,$@) ppc mpc8xx netta
xtract_NETTA2 = $(subst _V2,,$(subst _config,,$1))
NETTA2_V2_config \
NETTA2_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring NETTA2_config,$@)" ] || \
- { echo "#define CONFIG_NETTA2_VERSION 1" >>include/config.h ; \
+ { echo "#define CONFIG_NETTA2_VERSION 1" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring NETTA2_V2_config,$@)" ] || \
- { echo "#define CONFIG_NETTA2_VERSION 2" >>include/config.h ; \
+ { echo "#define CONFIG_NETTA2_VERSION 2" >>$(obj)include/config.h ; \
}
- @./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
+ @$(MKCONFIG) -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
NC650_Rev1_config \
NC650_Rev2_config \
CP850_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring CP850,$@)" ] || \
- { echo "#define CONFIG_CP850 1" >>include/config.h ; \
- echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
+ { echo "#define CONFIG_CP850 1" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_IDS852_REV2 1" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring Rev1,$@)" ] || \
- { echo "#define CONFIG_IDS852_REV1 1" >>include/config.h ; \
+ { echo "#define CONFIG_IDS852_REV1 1" >>$(obj)include/config.h ; \
}
@[ -z "$(findstring Rev2,$@)" ] || \
- { echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \
+ { echo "#define CONFIG_IDS852_REV2 1" >>$(obj)include/config.h ; \
}
- @./mkconfig -a NC650 ppc mpc8xx nc650
+ @$(MKCONFIG) -a NC650 ppc mpc8xx nc650
NX823_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx nx823
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx nx823
pcu_e_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx pcu_e siemens
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx pcu_e siemens
QS850_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx qs850 snmc
QS823_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx qs850 snmc
QS860T_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx qs860t snmc
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx qs860t snmc
quantum_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx quantum
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx quantum
R360MPI_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx r360mpi
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx r360mpi
RBC823_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx rbc823
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx rbc823
RPXClassic_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx RPXClassic
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx RPXClassic
RPXlite_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx RPXlite
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx RPXlite
RPXlite_DW_64_config \
RPXlite_DW_LCD_config \
RPXlite_DW_NVRAM_LCD_config \
RPXlite_DW_NVRAM_64_LCD_config \
RPXlite_DW_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring _64,$@)" ] || \
- { echo "#define RPXlite_64MHz" >>include/config.h ; \
+ { echo "#define RPXlite_64MHz" >>$(obj)include/config.h ; \
echo "... with 64MHz system clock ..."; \
}
@[ -z "$(findstring _LCD,$@)" ] || \
- { echo "#define CONFIG_LCD" >>include/config.h ; \
- echo "#define CONFIG_NEC_NL6448BC20" >>include/config.h ; \
+ { echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \
echo "... with LCD display ..."; \
}
@[ -z "$(findstring _NVRAM,$@)" ] || \
- { echo "#define CFG_ENV_IS_IN_NVRAM" >>include/config.h ; \
+ { echo "#define CFG_ENV_IS_IN_NVRAM" >>$(obj)include/config.h ; \
echo "... with ENV in NVRAM ..."; \
}
- @./mkconfig -a RPXlite_DW ppc mpc8xx RPXlite_dw
+ @$(MKCONFIG) -a RPXlite_DW ppc mpc8xx RPXlite_dw
rmu_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx rmu
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx rmu
RRvision_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx RRvision
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx RRvision
RRvision_LCD_config: unconfig
- @echo "#define CONFIG_LCD" >include/config.h
- @echo "#define CONFIG_SHARP_LQ104V7DS01" >>include/config.h
- @./mkconfig -a RRvision ppc mpc8xx RRvision
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_LCD" >$(obj)include/config.h
+ @echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h
+ @$(MKCONFIG) -a RRvision ppc mpc8xx RRvision
SM850_config : unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx
spc1920_config:
- @./mkconfig $(@:_config=) ppc mpc8xx spc1920
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx spc1920
SPD823TS_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx spd8xx
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx spd8xx
stxxtc_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx stxxtc
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx stxxtc
svm_sc8xx_config: unconfig
- @ >include/config.h
- @./mkconfig $(@:_config=) ppc mpc8xx svm_sc8xx
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx svm_sc8xx
SXNI855T_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx sixnet
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx sixnet
# EMK MPC8xx based modules
TOP860_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx top860 emk
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx top860 emk
# Play some tricks for configuration selection
# Only 855 and 860 boards may come with FEC
TQM866M_config \
TQM885D_config \
virtlab2_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring _LCD,$@)" ] || \
- { echo "#define CONFIG_LCD" >>include/config.h ; \
- echo "#define CONFIG_NEC_NL6448BC20" >>include/config.h ; \
+ { echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \
echo "... with LCD display" ; \
}
- @./mkconfig -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx
+ @$(MKCONFIG) -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx
TTTech_config: unconfig
- @echo "#define CONFIG_LCD" >include/config.h
- @echo "#define CONFIG_SHARP_LQ104V7DS01" >>include/config.h
- @./mkconfig -a TQM823L ppc mpc8xx tqm8xx
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_LCD" >$(obj)include/config.h
+ @echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h
+ @$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx
uc100_config : unconfig
- @./mkconfig $(@:_config=) ppc mpc8xx uc100
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx uc100
v37_config: unconfig
- @echo "#define CONFIG_LCD" >include/config.h
- @echo "#define CONFIG_SHARP_LQ084V1DG21" >>include/config.h
- @./mkconfig $(@:_config=) ppc mpc8xx v37
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_LCD" >$(obj)include/config.h
+ @echo "#define CONFIG_SHARP_LQ084V1DG21" >>$(obj)include/config.h
+ @$(MKCONFIG) $(@:_config=) ppc mpc8xx v37
wtk_config: unconfig
- @echo "#define CONFIG_LCD" >include/config.h
- @echo "#define CONFIG_SHARP_LQ065T9DR51U" >>include/config.h
- @./mkconfig -a TQM823L ppc mpc8xx tqm8xx
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_LCD" >$(obj)include/config.h
+ @echo "#define CONFIG_SHARP_LQ065T9DR51U" >>$(obj)include/config.h
+ @$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx
#########################################################################
## PPC4xx Systems
xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1))))))
ADCIOP_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx adciop esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd
AP1000_config:unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ap1000 amirix
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx ap1000 amirix
APC405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx apc405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx apc405 esd
AR405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ar405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx ar405 esd
ASH405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ash405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx ash405 esd
bamboo_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx bamboo amcc
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx bamboo amcc
bubinga_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx bubinga amcc
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx bubinga amcc
CANBT_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx canbt esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
CATcenter_config \
CATcenter_25_config \
CATcenter_33_config: unconfig
- @ echo "/* CATcenter uses PPChameleon Model ME */" > include/config.h
- @ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> include/config.h
+ @mkdir -p $(obj)include
+ @ echo "/* CATcenter uses PPChameleon Model ME */" > $(obj)include/config.h
+ @ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> $(obj)include/config.h
@[ -z "$(findstring _25,$@)" ] || \
- { echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \
+ { echo "#define CONFIG_PPCHAMELEON_CLK_25" >> $(obj)include/config.h ; \
echo "SysClk = 25MHz" ; \
}
@[ -z "$(findstring _33,$@)" ] || \
- { echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \
+ { echo "#define CONFIG_PPCHAMELEON_CLK_33" >> $(obj)include/config.h ; \
echo "SysClk = 33MHz" ; \
}
- @./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+ @$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
CPCI2DP_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx cpci2dp esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
CPCI405_config \
CPCI4052_config \
CPCI405DT_config \
CPCI405AB_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx cpci405 esd
- @echo "BOARD_REVISION = $(@:_config=)" >>include/config.mk
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
+ @echo "BOARD_REVISION = $(@:_config=)" >> $(obj)include/config.mk
CPCI440_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx cpci440 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci440 esd
CPCIISER4_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx cpciiser4 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd
CRAYL1_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx L1 cray
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx L1 cray
csb272_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx csb272
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx csb272
csb472_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx csb472
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx csb472
DASA_SIM_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx dasa_sim esd
DP405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx dp405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx dp405 esd
DU405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx du405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx du405 esd
ebony_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ebony amcc
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx ebony amcc
ERIC_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx eric
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx eric
EXBITGEN_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx exbitgen
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx exbitgen
G2000_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx g2000
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
HH405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx hh405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx hh405 esd
HUB405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx hub405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx hub405 esd
JSE_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx jse
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx jse
KAREF_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx karef sandburst
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx karef sandburst
luan_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx luan amcc
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
METROBOX_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx metrobox sandburst
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst
MIP405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx mip405 mpl
MIP405T_config: unconfig
- @echo "#define CONFIG_MIP405T" >include/config.h
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_MIP405T" >$(obj)include/config.h
@echo "Enable subset config for MIP405T"
- @./mkconfig -a MIP405 ppc ppc4xx mip405 mpl
+ @$(MKCONFIG) -a MIP405 ppc ppc4xx mip405 mpl
ML2_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ml2
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml2
ml300_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx
ocotea_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ocotea amcc
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc
OCRTC_config \
ORSG_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx ocrtc esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx ocrtc esd
p3p440_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx p3p440 prodrive
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx p3p440 prodrive
PCI405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx pci405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx pci405 esd
pcs440ep_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx pcs440ep
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx pcs440ep
PIP405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx pip405 mpl
PLU405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx plu405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx plu405 esd
PMC405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd
PPChameleonEVB_config \
PPChameleonEVB_BA_25_config \
PPChameleonEVB_BA_33_config \
PPChameleonEVB_ME_33_config \
PPChameleonEVB_HI_33_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring EVB_BA,$@)" ] || \
- { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \
+ { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>$(obj)include/config.h ; \
echo "... BASIC model" ; \
}
@[ -z "$(findstring EVB_ME,$@)" ] || \
- { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>include/config.h ; \
+ { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>$(obj)include/config.h ; \
echo "... MEDIUM model" ; \
}
@[ -z "$(findstring EVB_HI,$@)" ] || \
- { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \
+ { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>$(obj)include/config.h ; \
echo "... HIGH-END model" ; \
}
@[ -z "$(findstring _25,$@)" ] || \
- { echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \
+ { echo "#define CONFIG_PPCHAMELEON_CLK_25" >>$(obj)include/config.h ; \
echo "SysClk = 25MHz" ; \
}
@[ -z "$(findstring _33,$@)" ] || \
- { echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \
+ { echo "#define CONFIG_PPCHAMELEON_CLK_33" >>$(obj)include/config.h ; \
echo "SysClk = 33MHz" ; \
}
- @./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+ @$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+
+rainier_config: unconfig
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_RAINIER" > $(obj)include/config.h
+ @echo "Configuring for rainier board as subset of sequoia..."
+ @$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
+
+rainier_nand_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)nand_spl
+ @mkdir -p $(obj)board/amcc/sequoia
+ @echo "#define CONFIG_RAINIER" > $(obj)include/config.h
+ @echo "Configuring for rainier board as subset of sequoia..."
+ @echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h
+ @echo "Compile NAND boot image for sequoia"
+ @$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
+ @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
sbc405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx sbc405
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
+
+sequoia_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx sequoia amcc
+
+sequoia_nand_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)nand_spl
+ @mkdir -p $(obj)board/amcc/sequoia
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+ @echo "Compile NAND boot image for sequoia"
+ @$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
+ @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
sycamore_config: unconfig
@echo "Configuring for sycamore board as subset of walnut..."
- @./mkconfig -a walnut ppc ppc4xx walnut amcc
+ @$(MKCONFIG) -a walnut ppc ppc4xx walnut amcc
VOH405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx voh405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd
VOM405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx vom405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx vom405 esd
CMS700_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx cms700 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx cms700 esd
W7OLMC_config \
W7OLMG_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx w7o
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx w7o
walnut_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx walnut amcc
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx walnut amcc
WUH405_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx wuh405 esd
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd
XPEDITE1K_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1k
yosemite_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx yosemite amcc
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx yosemite amcc
yellowstone_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx yellowstone amcc
yucca_config: unconfig
- @./mkconfig $(@:_config=) ppc ppc4xx yucca amcc
+ @$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc
#########################################################################
## MPC8220 Systems
Alaska8220_config \
Yukon8220_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8220 alaska
+ @$(MKCONFIG) $(@:_config=) ppc mpc8220 alaska
sorcery_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8220 sorcery
+ @$(MKCONFIG) $(@:_config=) ppc mpc8220 sorcery
#########################################################################
## MPC824x Systems
xtract_82xx = $(subst _BIGFLASH,,$(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1))))))
A3000_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x a3000
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x a3000
barco_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x barco
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x barco
BMW_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x bmw
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x bmw
CPC45_config \
CPC45_ROMBOOT_config: unconfig
- @./mkconfig $(call xtract_82xx,$@) ppc mpc824x cpc45
- @cd ./include ; \
+ @$(MKCONFIG) $(call xtract_82xx,$@) ppc mpc824x cpc45
+ @cd $(obj)include ; \
if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
echo "... booting from 8-bit flash" ; \
echo "export CONFIG_BOOT_ROM" >> config.mk;
CU824_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x cu824
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x cu824
debris_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x debris etin
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x debris etin
eXalion_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x eXalion
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x eXalion
HIDDEN_DRAGON_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x hidden_dragon
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x hidden_dragon
kvme080_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x kvme080 etin
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x kvme080 etin
MOUSSE_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x mousse
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x mousse
MUSENKI_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x musenki
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x musenki
MVBLUE_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x mvblue
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x mvblue
OXC_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x oxc
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x oxc
PN62_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x pn62
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x pn62
Sandpoint8240_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x sandpoint
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x sandpoint
Sandpoint8245_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x sandpoint
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x sandpoint
sbc8240_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x sbc8240
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x sbc8240
SL8245_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x sl8245
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x sl8245
utx8245_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc824x utx8245
+ @$(MKCONFIG) $(@:_config=) ppc mpc824x utx8245
#########################################################################
## MPC8260 Systems
#########################################################################
atc_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 atc
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 atc
cogent_mpc8260_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 cogent
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 cogent
CPU86_config \
CPU86_ROMBOOT_config: unconfig
- @./mkconfig $(call xtract_82xx,$@) ppc mpc8260 cpu86
- @cd ./include ; \
+ @$(MKCONFIG) $(call xtract_82xx,$@) ppc mpc8260 cpu86
+ @cd $(obj)include ; \
if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
echo "... booting from 8-bit flash" ; \
CPU87_config \
CPU87_ROMBOOT_config: unconfig
- @./mkconfig $(call xtract_82xx,$@) ppc mpc8260 cpu87
- @cd ./include ; \
+ @$(MKCONFIG) $(call xtract_82xx,$@) ppc mpc8260 cpu87
+ @cd $(obj)include ; \
if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
echo "... booting from 8-bit flash" ; \
ep8248_config \
ep8248E_config : unconfig
- @./mkconfig ep8248 ppc mpc8260 ep8248
+ @$(MKCONFIG) ep8248 ppc mpc8260 ep8248
ep8260_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 ep8260
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 ep8260
+
+ep82xxm_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc8260 ep82xxm
gw8260_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 gw8260
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 gw8260
hymod_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 hymod
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 hymod
IDS8247_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 ids8247
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 ids8247
IPHASE4539_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 iphase4539
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 iphase4539
ISPAN_config \
ISPAN_REVB_config: unconfig
+ @mkdir -p $(obj)include
@if [ "$(findstring _REVB_,$@)" ] ; then \
- echo "#define CFG_REV_B" > include/config.h ; \
+ echo "#define CFG_REV_B" > $(obj)include/config.h ; \
fi
- @./mkconfig -a ISPAN ppc mpc8260 ispan
+ @$(MKCONFIG) -a ISPAN ppc mpc8260 ispan
MPC8260ADS_config \
MPC8260ADS_lowboot_config \
PQ2FADS-ZU_66MHz_config \
PQ2FADS-ZU_66MHz_lowboot_config \
: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/mpc8260ads
$(if $(findstring PQ2FADS,$@), \
- @echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > include/config.h, \
- @echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > include/config.h)
+ @echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > $(obj)include/config.h, \
+ @echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
$(if $(findstring MHz,$@), \
- @echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> include/config.h, \
+ @echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> $(obj)include/config.h, \
$(if $(findstring VR,$@), \
- @echo "#define CONFIG_8260_CLKIN 66000000" >> include/config.h))
+ @echo "#define CONFIG_8260_CLKIN 66000000" >> $(obj)include/config.h))
@[ -z "$(findstring lowboot_,$@)" ] || \
- { echo "TEXT_BASE = 0xFF800000" >board/mpc8260ads/config.tmp ; \
+ { echo "TEXT_BASE = 0xFF800000" >$(obj)board/mpc8260ads/config.tmp ; \
echo "... with lowboot configuration" ; \
}
- @./mkconfig -a MPC8260ADS ppc mpc8260 mpc8260ads
+ @$(MKCONFIG) -a MPC8260ADS ppc mpc8260 mpc8260ads
MPC8266ADS_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 mpc8266ads
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads
# PM825/PM826 default configuration: small (= 8 MB) Flash / boot from 64-bit flash
PM825_config \
PM826_ROMBOOT_config \
PM826_BIGFLASH_config \
PM826_ROMBOOT_BIGFLASH_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/pm826
@if [ "$(findstring PM825_,$@)" ] ; then \
- echo "#define CONFIG_PCI" >include/config.h ; \
+ echo "#define CONFIG_PCI" >$(obj)include/config.h ; \
else \
- >include/config.h ; \
+ >$(obj)include/config.h ; \
fi
@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
echo "... booting from 8-bit flash" ; \
- echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
- echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \
+ echo "#define CONFIG_BOOT_ROM" >>$(obj)include/config.h ; \
+ echo "TEXT_BASE = 0xFF800000" >$(obj)board/pm826/config.tmp ; \
if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
echo "... with 32 MB Flash" ; \
- echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \
+ echo "#define CONFIG_FLASH_32MB" >>$(obj)include/config.h ; \
fi; \
else \
echo "... booting from 64-bit flash" ; \
if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
echo "... with 32 MB Flash" ; \
- echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \
- echo "TEXT_BASE = 0x40000000" >board/pm826/config.tmp ; \
+ echo "#define CONFIG_FLASH_32MB" >>$(obj)include/config.h ; \
+ echo "TEXT_BASE = 0x40000000" >$(obj)board/pm826/config.tmp ; \
else \
- echo "TEXT_BASE = 0xFF000000" >board/pm826/config.tmp ; \
+ echo "TEXT_BASE = 0xFF000000" >$(obj)board/pm826/config.tmp ; \
fi; \
fi
- @./mkconfig -a PM826 ppc mpc8260 pm826
+ @$(MKCONFIG) -a PM826 ppc mpc8260 pm826
PM828_config \
PM828_PCI_config \
PM828_ROMBOOT_config \
PM828_ROMBOOT_PCI_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/pm826
@if [ "$(findstring _PCI_,$@)" ] ; then \
- echo "#define CONFIG_PCI" >>include/config.h ; \
+ echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
echo "... with PCI enabled" ; \
else \
- >include/config.h ; \
+ >$(obj)include/config.h ; \
fi
@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
echo "... booting from 8-bit flash" ; \
- echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
- echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \
+ echo "#define CONFIG_BOOT_ROM" >>$(obj)include/config.h ; \
+ echo "TEXT_BASE = 0xFF800000" >$(obj)board/pm826/config.tmp ; \
fi
- @./mkconfig -a PM828 ppc mpc8260 pm828
+ @$(MKCONFIG) -a PM828 ppc mpc8260 pm828
ppmc8260_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 ppmc8260
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 ppmc8260
Rattler8248_config \
Rattler_config: unconfig
+ @mkdir -p $(obj)include
$(if $(findstring 8248,$@), \
- @echo "#define CONFIG_MPC8248" > include/config.h)
- @./mkconfig -a Rattler ppc mpc8260 rattler
+ @echo "#define CONFIG_MPC8248" > $(obj)include/config.h)
+ @$(MKCONFIG) -a Rattler ppc mpc8260 rattler
RPXsuper_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 rpxsuper
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 rpxsuper
rsdproto_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 rsdproto
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 rsdproto
sacsng_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 sacsng
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 sacsng
sbc8260_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 sbc8260
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 sbc8260
SCM_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 SCM siemens
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 SCM siemens
TQM8255_AA_config \
TQM8260_AA_config \
TQM8260_AH_config \
TQM8260_AI_config \
TQM8265_AA_config: unconfig
+ @mkdir -p $(obj)include
@case "$@" in \
TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no; BMODE=8260;; \
TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no; BMODE=8260;; \
TQM8260_AI_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \
TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no; BMODE=60x;; \
esac; \
- >include/config.h ; \
+ >$(obj)include/config.h ; \
if [ "$${CTYPE}" != "MPC8260" ] ; then \
- echo "#define CONFIG_$${CTYPE}" >>include/config.h ; \
+ echo "#define CONFIG_$${CTYPE}" >>$(obj)include/config.h ; \
fi; \
- echo "#define CONFIG_$${CFREQ}MHz" >>include/config.h ; \
+ echo "#define CONFIG_$${CFREQ}MHz" >>$(obj)include/config.h ; \
echo "... with $${CFREQ}MHz system clock" ; \
if [ "$${CACHE}" == "yes" ] ; then \
- echo "#define CONFIG_L2_CACHE" >>include/config.h ; \
+ echo "#define CONFIG_L2_CACHE" >>$(obj)include/config.h ; \
echo "... with L2 Cache support" ; \
else \
- echo "#undef CONFIG_L2_CACHE" >>include/config.h ; \
+ echo "#undef CONFIG_L2_CACHE" >>$(obj)include/config.h ; \
echo "... without L2 Cache support" ; \
fi; \
if [ "$${BMODE}" == "60x" ] ; then \
- echo "#define CONFIG_BUSMODE_60x" >>include/config.h ; \
+ echo "#define CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \
echo "... with 60x Bus Mode" ; \
else \
- echo "#undef CONFIG_BUSMODE_60x" >>include/config.h ; \
+ echo "#undef CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \
echo "... without 60x Bus Mode" ; \
fi
- @./mkconfig -a TQM8260 ppc mpc8260 tqm8260
+ @$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260
VoVPN-GW_66MHz_config \
VoVPN-GW_100MHz_config: unconfig
- @echo "#define CONFIG_CLKIN_$(word 2,$(subst _, ,$@))" > include/config.h
- @./mkconfig -a VoVPN-GW ppc mpc8260 vovpn-gw funkwerk
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_CLKIN_$(word 2,$(subst _, ,$@))" > $(obj)include/config.h
+ @$(MKCONFIG) -a VoVPN-GW ppc mpc8260 vovpn-gw funkwerk
ZPC1900_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc8260 zpc1900
+ @$(MKCONFIG) $(@:_config=) ppc mpc8260 zpc1900
#########################################################################
## Coldfire
#########################################################################
cobra5272_config : unconfig
- @./mkconfig $(@:_config=) m68k mcf52x2 cobra5272
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 cobra5272
EB+MCF-EV123_config : unconfig
- @ >include/config.h
- @echo "TEXT_BASE = 0xFFE00000"|tee board/BuS/EB+MCF-EV123/textbase.mk
- @./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/BuS/EB+MCF-EV123
+ @ >$(obj)include/config.h
+ @echo "TEXT_BASE = 0xFFE00000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
+ @$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
EB+MCF-EV123_internal_config : unconfig
- @ >include/config.h
- @echo "TEXT_BASE = 0xF0000000"|tee board/BuS/EB+MCF-EV123/textbase.mk
- @./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/BuS/EB+MCF-EV123
+ @ >$(obj)include/config.h
+ @echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
+ @$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
M5271EVB_config : unconfig
- @./mkconfig $(@:_config=) m68k mcf52x2 m5271evb
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5271evb
M5272C3_config : unconfig
- @./mkconfig $(@:_config=) m68k mcf52x2 m5272c3
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5272c3
M5282EVB_config : unconfig
- @./mkconfig $(@:_config=) m68k mcf52x2 m5282evb
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb
TASREG_config : unconfig
- @./mkconfig $(@:_config=) m68k mcf52x2 tasreg esd
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd
r5200_config : unconfig
- @./mkconfig $(@:_config=) m68k mcf52x2 r5200
+ @$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200
#########################################################################
## MPC83xx Systems
#########################################################################
MPC8349ADS_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads
+ @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349ads
TQM834x_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc83xx tqm834x
+ @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x
MPC8349EMDS_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc83xx mpc8349emds
+ @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds
#########################################################################
## MPC85xx Systems
#########################################################################
MPC8540ADS_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads
MPC8540EVAL_config \
MPC8540EVAL_33_config \
MPC8540EVAL_66_config \
MPC8540EVAL_33_slave_config \
MPC8540EVAL_66_slave_config: unconfig
- @echo "" >include/config.h ; \
+ @mkdir -p $(obj)include
+ @echo "" >$(obj)include/config.h ; \
if [ "$(findstring _33_,$@)" ] ; then \
echo -n "... 33 MHz PCI" ; \
else \
- echo "#define CONFIG_SYSCLK_66M" >>include/config.h ; \
+ echo "#define CONFIG_SYSCLK_66M" >>$(obj)include/config.h ; \
echo -n "... 66 MHz PCI" ; \
fi ; \
if [ "$(findstring _slave_,$@)" ] ; then \
- echo "#define CONFIG_PCI_SLAVE" >>include/config.h ; \
+ echo "#define CONFIG_PCI_SLAVE" >>$(obj)include/config.h ; \
echo " slave" ; \
else \
echo " host" ; \
fi
- @./mkconfig -a MPC8540EVAL ppc mpc85xx mpc8540eval
+ @$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval
MPC8560ADS_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads
MPC8541CDS_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc85xx mpc8541cds cds
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds
MPC8548CDS_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc85xx mpc8548cds cds
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds
MPC8555CDS_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds
PM854_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc85xx pm854
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
PM856_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc85xx pm856
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm856
sbc8540_config \
sbc8540_33_config \
sbc8540_66_config: unconfig
+ @mkdir -p $(obj)include
@if [ "$(findstring _66_,$@)" ] ; then \
- echo "#define CONFIG_PCI_66" >>include/config.h ; \
+ echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \
echo "... 66 MHz PCI" ; \
else \
- >include/config.h ; \
+ >$(obj)include/config.h ; \
echo "... 33 MHz PCI" ; \
fi
- @./mkconfig -a SBC8540 ppc mpc85xx sbc8560
+ @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
sbc8560_config \
sbc8560_33_config \
sbc8560_66_config: unconfig
+ @mkdir -p $(obj)include
@if [ "$(findstring _66_,$@)" ] ; then \
- echo "#define CONFIG_PCI_66" >>include/config.h ; \
+ echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \
echo "... 66 MHz PCI" ; \
else \
- >include/config.h ; \
+ >$(obj)include/config.h ; \
echo "... 33 MHz PCI" ; \
fi
- @./mkconfig -a sbc8560 ppc mpc85xx sbc8560
+ @$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560
stxgp3_config: unconfig
- @./mkconfig $(@:_config=) ppc mpc85xx stxgp3
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3
TQM8540_config \
TQM8541_config \
TQM8555_config \
TQM8560_config: unconfig
+ @mkdir -p $(obj)include
@CTYPE=$(subst TQM,,$(@:_config=)); \
- >include/config.h ; \
+ >$(obj)include/config.h ; \
echo "... TQM"$${CTYPE}; \
- echo "#define CONFIG_MPC$${CTYPE}">>include/config.h; \
- echo "#define CONFIG_TQM$${CTYPE}">>include/config.h; \
- echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>include/config.h; \
- echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>include/config.h; \
- echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>include/config.h
- @./mkconfig -a TQM85xx ppc mpc85xx tqm85xx
+ echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \
+ echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
+ echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
+ echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \
+ echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>$(obj)include/config.h
+ @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx
+
+#########################################################################
+## MPC86xx Systems
+#########################################################################
+
+MPC8641HPCN_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc86xx mpc8641hpcn
+
#########################################################################
## 74xx/7xx Systems
#########################################################################
AmigaOneG3SE_config: unconfig
- @./mkconfig $(@:_config=) ppc 74xx_7xx AmigaOneG3SE MAI
+ @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx AmigaOneG3SE MAI
BAB7xx_config: unconfig
- @./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec
+ @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx bab7xx eltec
CPCI750_config: unconfig
- @./mkconfig CPCI750 ppc 74xx_7xx cpci750 esd
+ @$(MKCONFIG) CPCI750 ppc 74xx_7xx cpci750 esd
DB64360_config: unconfig
- @./mkconfig DB64360 ppc 74xx_7xx db64360 Marvell
+ @$(MKCONFIG) DB64360 ppc 74xx_7xx db64360 Marvell
DB64460_config: unconfig
- @./mkconfig DB64460 ppc 74xx_7xx db64460 Marvell
+ @$(MKCONFIG) DB64460 ppc 74xx_7xx db64460 Marvell
ELPPC_config: unconfig
- @./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec
+ @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx elppc eltec
EVB64260_config \
EVB64260_750CX_config: unconfig
- @./mkconfig EVB64260 ppc 74xx_7xx evb64260
+ @$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
P3G4_config: unconfig
- @./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
+ @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
PCIPPC2_config \
PCIPPC6_config: unconfig
- @./mkconfig $(@:_config=) ppc 74xx_7xx pcippc2
+ @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx pcippc2
ZUMA_config: unconfig
- @./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
+ @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
ppmc7xx_config: unconfig
- @./mkconfig $(@:_config=) ppc 74xx_7xx ppmc7xx
+ @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx ppmc7xx
#========================================================================
# ARM
#########################################################################
assabet_config : unconfig
- @./mkconfig $(@:_config=) arm sa1100 assabet
+ @$(MKCONFIG) $(@:_config=) arm sa1100 assabet
dnp1110_config : unconfig
- @./mkconfig $(@:_config=) arm sa1100 dnp1110
+ @$(MKCONFIG) $(@:_config=) arm sa1100 dnp1110
gcplus_config : unconfig
- @./mkconfig $(@:_config=) arm sa1100 gcplus
+ @$(MKCONFIG) $(@:_config=) arm sa1100 gcplus
lart_config : unconfig
- @./mkconfig $(@:_config=) arm sa1100 lart
+ @$(MKCONFIG) $(@:_config=) arm sa1100 lart
shannon_config : unconfig
- @./mkconfig $(@:_config=) arm sa1100 shannon
+ @$(MKCONFIG) $(@:_config=) arm sa1100 shannon
#########################################################################
## ARM92xT Systems
xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
at91rm9200dk_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
+ @$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
cmc_pu2_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
+ @$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
csb637_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t csb637 NULL at91rm9200
+ @$(MKCONFIG) $(@:_config=) arm arm920t csb637 NULL at91rm9200
mp2usb_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t mp2usb NULL at91rm9200
+ @$(MKCONFIG) $(@:_config=) arm arm920t mp2usb NULL at91rm9200
########################################################################
@board/integratorcp/split_by_variant.sh $@
kb9202_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t kb9202 NULL at91rm9200
+ @$(MKCONFIG) $(@:_config=) arm arm920t kb9202 NULL at91rm9200
lpd7a400_config \
lpd7a404_config: unconfig
- @./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
+ @$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x
mx1ads_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t mx1ads NULL imx
+ @$(MKCONFIG) $(@:_config=) arm arm920t mx1ads NULL imx
mx1fs2_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t mx1fs2 NULL imx
+ @$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx
netstar_32_config \
netstar_config: unconfig
+ @mkdir -p $(obj)include
@if [ "$(findstring _32_,$@)" ] ; then \
echo "... 32MB SDRAM" ; \
- echo "#define PHYS_SDRAM_1_SIZE SZ_32M" >>include/config.h ; \
+ echo "#define PHYS_SDRAM_1_SIZE SZ_32M" >>$(obj)include/config.h ; \
else \
echo "... 64MB SDRAM" ; \
- echo "#define PHYS_SDRAM_1_SIZE SZ_64M" >>include/config.h ; \
+ echo "#define PHYS_SDRAM_1_SIZE SZ_64M" >>$(obj)include/config.h ; \
fi
- @./mkconfig -a netstar arm arm925t netstar
+ @$(MKCONFIG) -a netstar arm arm925t netstar
omap1510inn_config : unconfig
- @./mkconfig $(@:_config=) arm arm925t omap1510inn
+ @$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn
omap5912osk_config : unconfig
- @./mkconfig $(@:_config=) arm arm926ejs omap5912osk NULL omap
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap
omap1610inn_config \
omap1610inn_cs0boot_config \
omap1610h2_cs0boot_config \
omap1610h2_cs3boot_config \
omap1610h2_cs_autoboot_config: unconfig
+ @mkdir -p $(obj)include
@if [ "$(findstring _cs0boot_, $@)" ] ; then \
- echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
+ echo "#define CONFIG_CS0_BOOT" >> .$(obj)/include/config.h ; \
echo "... configured for CS0 boot"; \
elif [ "$(findstring _cs_autoboot_, $@)" ] ; then \
- echo "#define CONFIG_CS_AUTOBOOT" >> ./include/config.h ; \
+ echo "#define CONFIG_CS_AUTOBOOT" >> $(obj)./include/config.h ; \
echo "... configured for CS_AUTO boot"; \
else \
- echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
+ echo "#define CONFIG_CS3_BOOT" >> $(obj)./include/config.h ; \
echo "... configured for CS3 boot"; \
fi;
- @./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap
+ @$(MKCONFIG) -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap
omap730p2_config \
omap730p2_cs0boot_config \
omap730p2_cs3boot_config : unconfig
+ @mkdir -p $(obj)include
@if [ "$(findstring _cs0boot_, $@)" ] ; then \
- echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
+ echo "#define CONFIG_CS0_BOOT" >> $(obj)include/config.h ; \
echo "... configured for CS0 boot"; \
else \
- echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
+ echo "#define CONFIG_CS3_BOOT" >> $(obj)include/config.h ; \
echo "... configured for CS3 boot"; \
fi;
- @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
+ @$(MKCONFIG) -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
sbc2410x_config: unconfig
- @./mkconfig $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
+ @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
scb9328_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx
+ @$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx
smdk2400_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t smdk2400 NULL s3c24x0
+ @$(MKCONFIG) $(@:_config=) arm arm920t smdk2400 NULL s3c24x0
smdk2410_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t smdk2410 NULL s3c24x0
+ @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 NULL s3c24x0
SX1_config : unconfig
- @./mkconfig $(@:_config=) arm arm925t sx1
+ @$(MKCONFIG) $(@:_config=) arm arm925t sx1
# TRAB default configuration: 8 MB Flash, 32 MB RAM
trab_config \
trab_bigram_config \
trab_bigflash_config \
trab_old_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/trab
+ @ >$(obj)include/config.h
@[ -z "$(findstring _bigram,$@)" ] || \
- { echo "#define CONFIG_FLASH_8MB" >>include/config.h ; \
- echo "#define CONFIG_RAM_32MB" >>include/config.h ; \
+ { echo "#define CONFIG_FLASH_8MB" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_RAM_32MB" >>$(obj)include/config.h ; \
echo "... with 8 MB Flash, 32 MB RAM" ; \
}
@[ -z "$(findstring _bigflash,$@)" ] || \
- { echo "#define CONFIG_FLASH_16MB" >>include/config.h ; \
- echo "#define CONFIG_RAM_16MB" >>include/config.h ; \
+ { echo "#define CONFIG_FLASH_16MB" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_RAM_16MB" >>$(obj)include/config.h ; \
echo "... with 16 MB Flash, 16 MB RAM" ; \
- echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \
+ echo "TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \
}
@[ -z "$(findstring _old,$@)" ] || \
- { echo "#define CONFIG_FLASH_8MB" >>include/config.h ; \
- echo "#define CONFIG_RAM_16MB" >>include/config.h ; \
+ { echo "#define CONFIG_FLASH_8MB" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_RAM_16MB" >>$(obj)include/config.h ; \
echo "... with 8 MB Flash, 16 MB RAM" ; \
- echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \
+ echo "TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \
}
- @./mkconfig -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0
+ @$(MKCONFIG) -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0
VCMA9_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0
+ @$(MKCONFIG) $(@:_config=) arm arm920t vcma9 mpl s3c24x0
#========================================================================
# ARM supplied Versatile development boards
voiceblue_smallflash_config \
voiceblue_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/voiceblue
@if [ "$(findstring _smallflash_,$@)" ] ; then \
echo "... boot from lower flash bank" ; \
- echo "#define VOICEBLUE_SMALL_FLASH" >>include/config.h ; \
- echo "VOICEBLUE_SMALL_FLASH=y" >board/voiceblue/config.tmp ; \
+ echo "#define VOICEBLUE_SMALL_FLASH" >>$(obj)include/config.h ; \
+ echo "VOICEBLUE_SMALL_FLASH=y" >$(obj)board/voiceblue/config.tmp ; \
else \
echo "... boot from upper flash bank" ; \
- >include/config.h ; \
- echo "VOICEBLUE_SMALL_FLASH=n" >board/voiceblue/config.tmp ; \
+ >$(obj)include/config.h ; \
+ echo "VOICEBLUE_SMALL_FLASH=n" >$(obj)board/voiceblue/config.tmp ; \
fi
- @./mkconfig -a voiceblue arm arm925t voiceblue
+ @$(MKCONFIG) -a voiceblue arm arm925t voiceblue
cm4008_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t cm4008 NULL ks8695
+ @$(MKCONFIG) $(@:_config=) arm arm920t cm4008 NULL ks8695
cm41xx_config : unconfig
- @./mkconfig $(@:_config=) arm arm920t cm41xx NULL ks8695
+ @$(MKCONFIG) $(@:_config=) arm arm920t cm41xx NULL ks8695
gth2_config : unconfig
- @ >include/config.h
- @echo "#define CONFIG_GTH2 1" >>include/config.h
- @./mkconfig -a gth2 mips mips gth2
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
+ @echo "#define CONFIG_GTH2 1" >>$(obj)include/config.h
+ @$(MKCONFIG) -a gth2 mips mips gth2
#########################################################################
## S3C44B0 Systems
#########################################################################
B2_config : unconfig
- @./mkconfig $(@:_config=) arm s3c44b0 B2 dave
+ @$(MKCONFIG) $(@:_config=) arm s3c44b0 B2 dave
#########################################################################
## ARM720T Systems
#########################################################################
armadillo_config: unconfig
- @./mkconfig $(@:_config=) arm arm720t armadillo
+ @$(MKCONFIG) $(@:_config=) arm arm720t armadillo
ep7312_config : unconfig
- @./mkconfig $(@:_config=) arm arm720t ep7312
+ @$(MKCONFIG) $(@:_config=) arm arm720t ep7312
impa7_config : unconfig
- @./mkconfig $(@:_config=) arm arm720t impa7
+ @$(MKCONFIG) $(@:_config=) arm arm720t impa7
modnet50_config : unconfig
- @./mkconfig $(@:_config=) arm arm720t modnet50
+ @$(MKCONFIG) $(@:_config=) arm arm720t modnet50
evb4510_config : unconfig
- @./mkconfig $(@:_config=) arm arm720t evb4510
+ @$(MKCONFIG) $(@:_config=) arm arm720t evb4510
#########################################################################
## XScale Systems
#########################################################################
adsvix_config : unconfig
- @./mkconfig $(@:_config=) arm pxa adsvix
+ @$(MKCONFIG) $(@:_config=) arm pxa adsvix
cerf250_config : unconfig
- @./mkconfig $(@:_config=) arm pxa cerf250
+ @$(MKCONFIG) $(@:_config=) arm pxa cerf250
cradle_config : unconfig
- @./mkconfig $(@:_config=) arm pxa cradle
+ @$(MKCONFIG) $(@:_config=) arm pxa cradle
csb226_config : unconfig
- @./mkconfig $(@:_config=) arm pxa csb226
+ @$(MKCONFIG) $(@:_config=) arm pxa csb226
delta_config :
- @./mkconfig $(@:_config=) arm pxa delta
+ @$(MKCONFIG) $(@:_config=) arm pxa delta
innokom_config : unconfig
- @./mkconfig $(@:_config=) arm pxa innokom
+ @$(MKCONFIG) $(@:_config=) arm pxa innokom
ixdp425_config : unconfig
- @./mkconfig $(@:_config=) arm ixp ixdp425
+ @$(MKCONFIG) $(@:_config=) arm ixp ixdp425
ixdpg425_config : unconfig
- @./mkconfig $(@:_config=) arm ixp ixdp425
+ @$(MKCONFIG) $(@:_config=) arm ixp ixdp425
lubbock_config : unconfig
- @./mkconfig $(@:_config=) arm pxa lubbock
+ @$(MKCONFIG) $(@:_config=) arm pxa lubbock
pleb2_config : unconfig
- @./mkconfig $(@:_config=) arm pxa pleb2
+ @$(MKCONFIG) $(@:_config=) arm pxa pleb2
logodl_config : unconfig
- @./mkconfig $(@:_config=) arm pxa logodl
+ @$(MKCONFIG) $(@:_config=) arm pxa logodl
pdnb3_config : unconfig
- @./mkconfig $(@:_config=) arm ixp pdnb3 prodrive
+ @$(MKCONFIG) $(@:_config=) arm ixp pdnb3 prodrive
pxa255_idp_config: unconfig
- @./mkconfig $(@:_config=) arm pxa pxa255_idp
+ @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
wepep250_config : unconfig
- @./mkconfig $(@:_config=) arm pxa wepep250
+ @$(MKCONFIG) $(@:_config=) arm pxa wepep250
xaeniax_config : unconfig
- @./mkconfig $(@:_config=) arm pxa xaeniax
+ @$(MKCONFIG) $(@:_config=) arm pxa xaeniax
xm250_config : unconfig
- @./mkconfig $(@:_config=) arm pxa xm250
+ @$(MKCONFIG) $(@:_config=) arm pxa xm250
xsengine_config : unconfig
- @./mkconfig $(@:_config=) arm pxa xsengine
+ @$(MKCONFIG) $(@:_config=) arm pxa xsengine
zylonite_config :
- @./mkconfig $(@:_config=) arm pxa zylonite
+ @$(MKCONFIG) $(@:_config=) arm pxa zylonite
#########################################################################
## ARM1136 Systems
#########################################################################
omap2420h4_config : unconfig
- @./mkconfig $(@:_config=) arm arm1136 omap2420h4
+ @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
#========================================================================
# i386
## AMD SC520 CDP
#########################################################################
sc520_cdp_config : unconfig
- @./mkconfig $(@:_config=) i386 i386 sc520_cdp
+ @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp
sc520_spunk_config : unconfig
- @./mkconfig $(@:_config=) i386 i386 sc520_spunk
+ @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk
sc520_spunk_rel_config : unconfig
- @./mkconfig $(@:_config=) i386 i386 sc520_spunk
+ @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk
#========================================================================
# MIPS
incaip_133MHz_config \
incaip_150MHz_config \
incaip_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring _100MHz,$@)" ] || \
- { echo "#define CPU_CLOCK_RATE 100000000" >>include/config.h ; \
+ { echo "#define CPU_CLOCK_RATE 100000000" >>$(obj)include/config.h ; \
echo "... with 100MHz system clock" ; \
}
@[ -z "$(findstring _133MHz,$@)" ] || \
- { echo "#define CPU_CLOCK_RATE 133000000" >>include/config.h ; \
+ { echo "#define CPU_CLOCK_RATE 133000000" >>$(obj)include/config.h ; \
echo "... with 133MHz system clock" ; \
}
@[ -z "$(findstring _150MHz,$@)" ] || \
- { echo "#define CPU_CLOCK_RATE 150000000" >>include/config.h ; \
+ { echo "#define CPU_CLOCK_RATE 150000000" >>$(obj)include/config.h ; \
echo "... with 150MHz system clock" ; \
}
- @./mkconfig -a $(call xtract_incaip,$@) mips mips incaip
+ @$(MKCONFIG) -a $(call xtract_incaip,$@) mips mips incaip
tb0229_config: unconfig
- @./mkconfig $(@:_config=) mips mips tb0229
+ @$(MKCONFIG) $(@:_config=) mips mips tb0229
#########################################################################
## MIPS32 AU1X00
#########################################################################
dbau1000_config : unconfig
- @ >include/config.h
- @echo "#define CONFIG_DBAU1000 1" >>include/config.h
- @./mkconfig -a dbau1x00 mips mips dbau1x00
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
+ @echo "#define CONFIG_DBAU1000 1" >>$(obj)include/config.h
+ @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
dbau1100_config : unconfig
- @ >include/config.h
- @echo "#define CONFIG_DBAU1100 1" >>include/config.h
- @./mkconfig -a dbau1x00 mips mips dbau1x00
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
+ @echo "#define CONFIG_DBAU1100 1" >>$(obj)include/config.h
+ @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
dbau1500_config : unconfig
- @ >include/config.h
- @echo "#define CONFIG_DBAU1500 1" >>include/config.h
- @./mkconfig -a dbau1x00 mips mips dbau1x00
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
+ @echo "#define CONFIG_DBAU1500 1" >>$(obj)include/config.h
+ @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
dbau1550_config : unconfig
- @ >include/config.h
- @echo "#define CONFIG_DBAU1550 1" >>include/config.h
- @./mkconfig -a dbau1x00 mips mips dbau1x00
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
+ @echo "#define CONFIG_DBAU1550 1" >>$(obj)include/config.h
+ @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
dbau1550_el_config : unconfig
- @ >include/config.h
- @echo "#define CONFIG_DBAU1550 1" >>include/config.h
- @./mkconfig -a dbau1x00 mips mips dbau1x00
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
+ @echo "#define CONFIG_DBAU1550 1" >>$(obj)include/config.h
+ @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
pb1000_config : unconfig
- @ >include/config.h
- @echo "#define CONFIG_PB1000 1" >>include/config.h
- @./mkconfig -a pb1x00 mips mips pb1x00
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
+ @echo "#define CONFIG_PB1000 1" >>$(obj)include/config.h
+ @$(MKCONFIG) -a pb1x00 mips mips pb1x00
#########################################################################
## MIPS64 5Kc
#########################################################################
purple_config : unconfig
- @./mkconfig $(@:_config=) mips mips purple
+ @$(MKCONFIG) $(@:_config=) mips mips purple
#========================================================================
# Nios
DK1C20_safe_32_config \
DK1C20_standard_32_config \
DK1C20_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring _safe_32,$@)" ] || \
- { echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \
+ { echo "#define CONFIG_NIOS_SAFE_32 1" >>$(obj)include/config.h ; \
echo "... NIOS 'safe_32' configuration" ; \
}
@[ -z "$(findstring _standard_32,$@)" ] || \
- { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
+ { echo "#define CONFIG_NIOS_STANDARD_32 1" >>$(obj)include/config.h ; \
echo "... NIOS 'standard_32' configuration" ; \
}
@[ -z "$(findstring DK1C20_config,$@)" ] || \
- { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
+ { echo "#define CONFIG_NIOS_STANDARD_32 1" >>$(obj)include/config.h ; \
echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \
}
- @./mkconfig -a DK1C20 nios nios dk1c20 altera
+ @$(MKCONFIG) -a DK1C20 nios nios dk1c20 altera
DK1S10_safe_32_config \
DK1S10_standard_32_config \
DK1S10_mtx_ldk_20_config \
DK1S10_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring _safe_32,$@)" ] || \
- { echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \
+ { echo "#define CONFIG_NIOS_SAFE_32 1" >>$(obj)include/config.h ; \
echo "... NIOS 'safe_32' configuration" ; \
}
@[ -z "$(findstring _standard_32,$@)" ] || \
- { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
+ { echo "#define CONFIG_NIOS_STANDARD_32 1" >>$(obj)include/config.h ; \
echo "... NIOS 'standard_32' configuration" ; \
}
@[ -z "$(findstring _mtx_ldk_20,$@)" ] || \
- { echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>include/config.h ; \
+ { echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>$(obj)include/config.h ; \
echo "... NIOS 'mtx_ldk_20' configuration" ; \
}
@[ -z "$(findstring DK1S10_config,$@)" ] || \
- { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
+ { echo "#define CONFIG_NIOS_STANDARD_32 1" >>$(obj)include/config.h ; \
echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \
}
- @./mkconfig -a DK1S10 nios nios dk1s10 altera
+ @$(MKCONFIG) -a DK1S10 nios nios dk1s10 altera
ADNPESC1_DNPEVA2_base_32_config \
ADNPESC1_base_32_config \
ADNPESC1_config: unconfig
- @ >include/config.h
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
@[ -z "$(findstring _DNPEVA2,$@)" ] || \
- { echo "#define CONFIG_DNPEVA2 1" >>include/config.h ; \
+ { echo "#define CONFIG_DNPEVA2 1" >>$(obj)include/config.h ; \
echo "... DNP/EVA2 configuration" ; \
}
@[ -z "$(findstring _base_32,$@)" ] || \
- { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
+ { echo "#define CONFIG_NIOS_BASE_32 1" >>$(obj)include/config.h ; \
echo "... NIOS 'base_32' configuration" ; \
}
@[ -z "$(findstring ADNPESC1_config,$@)" ] || \
- { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
+ { echo "#define CONFIG_NIOS_BASE_32 1" >>$(obj)include/config.h ; \
echo "... NIOS 'base_32' configuration (DEFAULT)" ; \
}
- @./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv
+ @$(MKCONFIG) -a ADNPESC1 nios nios adnpesc1 ssv
#########################################################################
## Nios-II
#########################################################################
EP1C20_config : unconfig
- @./mkconfig EP1C20 nios2 nios2 ep1c20 altera
+ @$(MKCONFIG) EP1C20 nios2 nios2 ep1c20 altera
EP1S10_config : unconfig
- @./mkconfig EP1S10 nios2 nios2 ep1s10 altera
+ @$(MKCONFIG) EP1S10 nios2 nios2 ep1s10 altera
EP1S40_config : unconfig
- @./mkconfig EP1S40 nios2 nios2 ep1s40 altera
+ @$(MKCONFIG) EP1S40 nios2 nios2 ep1s40 altera
PK1C20_config : unconfig
- @./mkconfig PK1C20 nios2 nios2 pk1c20 psyent
+ @$(MKCONFIG) PK1C20 nios2 nios2 pk1c20 psyent
PCI5441_config : unconfig
- @./mkconfig PCI5441 nios2 nios2 pci5441 psyent
+ @$(MKCONFIG) PCI5441 nios2 nios2 pci5441 psyent
#========================================================================
# MicroBlaze
## Microblaze
#########################################################################
suzaku_config: unconfig
- @ >include/config.h
- @echo "#define CONFIG_SUZAKU 1" >> include/config.h
- @./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
+ @mkdir -p $(obj)include
+ @ >$(obj)include/config.h
+ @echo "#define CONFIG_SUZAKU 1" >> $(obj)include/config.h
+ @$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
#########################################################################
## Blackfin
#########################################################################
ezkit533_config : unconfig
- @./mkconfig $(@:_config=) blackfin bf533 ezkit533
+ @$(MKCONFIG) $(@:_config=) blackfin bf533 ezkit533
stamp_config : unconfig
- @./mkconfig $(@:_config=) blackfin bf533 stamp
+ @$(MKCONFIG) $(@:_config=) blackfin bf533 stamp
dspstamp_config : unconfig
- @./mkconfig $(@:_config=) blackfin bf533 dsp_stamp
+ @$(MKCONFIG) $(@:_config=) blackfin bf533 dsp_stamp
+
+#========================================================================
+# AVR32
+#========================================================================
+#########################################################################
+## AT32AP7xxx
+#########################################################################
+
+atstk1002_config : unconfig
+ @./mkconfig $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000
#########################################################################
#########################################################################
#########################################################################
clean:
- find . -type f \
+ find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' \
-o -name '*.o' -o -name '*.a' \) -print \
| xargs rm -f
- rm -f examples/hello_world examples/timer \
- examples/eepro100_eeprom examples/sched \
- examples/mem_to_mem_idma2intr examples/82559_eeprom \
- examples/smc91111_eeprom \
- examples/test_burst
- rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
- rm -f tools/mpc86x_clk tools/ncb
- rm -f tools/easylogo/easylogo tools/bmp_logo
- rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
- rm -f tools/env/fw_printenv tools/env/fw_setenv
- rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
- rm -f board/netstar/eeprom board/netstar/crcek
- rm -f board/netstar/*.srec board/netstar/*.bin
- rm -f board/trab/trab_fkt board/voiceblue/eeprom
- rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
- rm -f include/bmp_logo.h
+ rm -f $(obj)examples/hello_world $(obj)examples/timer \
+ $(obj)examples/eepro100_eeprom $(obj)examples/sched \
+ $(obj)examples/mem_to_mem_idma2intr $(obj)examples/82559_eeprom \
+ $(obj)examples/smc91111_eeprom $(obj)examples/interrupt \
+ $(obj)examples/test_burst
+ rm -f $(obj)tools/img2srec $(obj)tools/mkimage $(obj)tools/envcrc \
+ $(obj)tools/gen_eth_addr
+ rm -f $(obj)tools/mpc86x_clk $(obj)tools/ncb
+ rm -f $(obj)tools/easylogo/easylogo $(obj)tools/bmp_logo
+ rm -f $(obj)tools/gdb/astest $(obj)tools/gdb/gdbcont $(obj)tools/gdb/gdbsend
+ rm -f $(obj)tools/env/fw_printenv $(obj)tools/env/fw_setenv
+ rm -f $(obj)board/cray/L1/bootscript.c $(obj)board/cray/L1/bootscript.image
+ rm -f $(obj)board/netstar/eeprom $(obj)board/netstar/crcek $(obj)board/netstar/crcit
+ rm -f $(obj)board/netstar/*.srec $(obj)board/netstar/*.bin
+ rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
+ rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
+ rm -f $(obj)include/bmp_logo.h
+ rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
clobber: clean
- find . -type f \( -name .depend \
+ find $(OBJTREE) -type f \( -name .depend \
-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
-print0 \
| xargs -0 rm -f
- rm -f $(OBJS) *.bak tags TAGS include/version_autogenerated.h
- rm -fr *.*~
- rm -f u-boot u-boot.map u-boot.hex $(ALL)
- rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
- rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c
- rm -f include/asm/proc include/asm/arch include/asm
-
+ rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS $(obj)include/version_autogenerated.h
+ rm -fr $(obj)*.*~
+ rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
+ rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c
+ rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
+ rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
+ [ ! -d $(OBJTREE)/nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
+
+ifeq ($(OBJTREE),$(SRCTREE))
mrproper \
distclean: clobber unconfig
+else
+mrproper \
+distclean: clobber unconfig
+ rm -rf $(OBJTREE)/*
+endif
backup:
F=`basename $(TOPDIR)` ; cd .. ; \
- arm925t Files specific to ARM 925 CPUs
- arm926ejs Files specific to ARM 926 CPUs
- arm1136 Files specific to ARM 1136 CPUs
+ - at32ap Files specific to Atmel AVR32 AP CPUs
- i386 Files specific to i386 CPUs
- ixp Files specific to Intel XScale IXP CPUs
- mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs
- examples Example code for standalone applications, etc.
- include Header Files
- lib_arm Files generic to ARM architecture
+- lib_avr32 Files generic to AVR32 architecture
- lib_generic Files generic to all architectures
- lib_i386 Files generic to i386 architecture
- lib_m68k Files generic to m68k architecture
----------------------
CONFIG_NIOS2
+ AVR32 based CPUs:
+ ----------------------
+ CONFIG_AT32AP
- Board Type: Define exactly one of
CONFIG_PCI5441 CONFIG_PK1C20
CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40
+ AVR32 based boards:
+ -------------------
+
+ CONFIG_ATSTK1000
+
+- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
+ Define exactly one of
+ CONFIG_ATSTK1002
+
- CPU Module Type: (if CONFIG_COGENT is defined)
Define exactly one of
Board code has addition modification that it wants to make
to the flat device tree before handing it off to the kernel
+ CONFIG_OF_BOOT_CPU
+
+ This define fills in the correct boot cpu in the boot
+ param header, the default value is zero if undefined.
+
- Serial Ports:
CFG_PL010_SERIAL
default value of 5 is used.
- Command Interpreter:
- CFG_AUTO_COMPLETE
+ CONFIG_AUTO_COMPLETE
Enable auto completion of commands using TAB.
+ Note that this feature has NOT been implemented yet
+ for the "hush" shell.
+
+
CFG_HUSH_PARSER
Define this variable to enable the "hush" shell (from
- "u-boot" is an image in ELF binary format
- "u-boot.srec" is in Motorola S-Record format
+By default the build is performed locally and the objects are saved
+in the source directory. One of the two methods can be used to change
+this behavior and build U-Boot to some external directory:
+
+1. Add O= to the make command line invocations:
+
+ make O=/tmp/build distclean
+ make O=/tmp/build NAME_config
+ make O=/tmp/build all
+
+2. Set environment variable BUILD_DIR to point to the desired location:
+
+ export BUILD_DIR=/tmp/build
+ make distclean
+ make NAME_config
+ make all
+
+Note that the command line "O=" setting overrides the BUILD_DIR environment
+variable.
+
Please be aware that the Makefiles assume you are using GNU make, so
for instance on NetBSD you might need to use "gmake" instead of
CROSS_COMPILE=' ' MAKEALL
+When using the MAKEALL script, the default behaviour is to build U-Boot
+in the source directory. This location can be changed by setting the
+BUILD_DIR environment variable. Also, for each target built, the MAKEALL
+script saves two log files (<target>.ERR and <target>.MAKEALL) in the
+<source dir>/LOG directory. This default location can be changed by
+setting the MAKEALL_LOGDIR environment variable. For example:
+
+ export BUILD_DIR=/tmp/build
+ export MAKEALL_LOGDIR=/tmp/log
+ CROSS_COMPILE=ppc_8xx- MAKEALL
+
+With the above settings build objects are saved in the /tmp/build, log
+files are saved in the /tmp/log and the source tree remains clean during
+the whole build process.
+
+
See also "U-Boot Porting Guide" below.
4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
LynxOS, pSOS, QNX, RTEMS, ARTOS;
Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS).
-* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
+* Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
- Currently supported: ARM, Intel x86, MIPS, NIOS, PowerPC).
+ Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC).
* Compression Type (uncompressed, gzip, bzip2)
* Load Address
* Entry Point
bash#
+Boot Linux and pass a flat device tree:
+-----------
+
+First, U-Boot must be compiled with the appropriate defines. See the section
+titled "Linux Kernel Interface" above for a more in depth explanation. The
+following is an example of how to start a kernel and pass an updated
+flat device tree:
+
+=> print oftaddr
+oftaddr=0x300000
+=> print oft
+oft=oftrees/mpc8540ads.dtb
+=> tftp $oftaddr $oft
+Speed: 1000, full duplex
+Using TSEC0 device
+TFTP from server 192.168.1.1; our IP address is 192.168.1.101
+Filename 'oftrees/mpc8540ads.dtb'.
+Load address: 0x300000
+Loading: #
+done
+Bytes transferred = 4106 (100a hex)
+=> tftp $loadaddr $bootfile
+Speed: 1000, full duplex
+Using TSEC0 device
+TFTP from server 192.168.1.1; our IP address is 192.168.1.2
+Filename 'uImage'.
+Load address: 0x200000
+Loading:############
+done
+Bytes transferred = 1029407 (fb51f hex)
+=> print loadaddr
+loadaddr=200000
+=> print oftaddr
+oftaddr=0x300000
+=> bootm $loadaddr - $oftaddr
+## Booting image at 00200000 ...
+ Image Name: Linux-2.6.17-dirty
+ Image Type: PowerPC Linux Kernel Image (gzip compressed)
+ Data Size: 1029343 Bytes = 1005.2 kB
+ Load Address: 00000000
+ Entry Point: 00000000
+ Verifying Checksum ... OK
+ Uncompressing Kernel Image ... OK
+Booting using flat device tree at 0x300000
+Using MPC85xx ADS machine description
+Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
+[snip]
+
+
More About U-Boot Image Types:
------------------------------
-----------------
All contributions to U-Boot should conform to the Linux kernel
-coding style; see the file "Documentation/CodingStyle" in your Linux
-kernel source directory.
-
-Please note that U-Boot is implemented in C (and to some small parts
-in Assembler); no C++ is used, so please do not use C++ style
-comments (//) in your code.
+coding style; see the file "Documentation/CodingStyle" and the script
+"scripts/Lindent" in your Linux kernel source directory. In sources
+originating from U-Boot a style corresponding to "Lindent -pcs" (adding
+spaces before parameters to function calls) is actually used.
+
+Source files originating from a different project (for example the
+MTD subsystem) are generally exempt from these guidelines and are not
+reformated to ease subsequent migration to newer versions of those
+sources.
+
+Please note that U-Boot is implemented in C (and to some small parts in
+Assembler); no C++ is used, so please do not use C++ style comments (//)
+in your code.
Please also stick to the following formatting rules:
- remove any trailing white space
--- /dev/null
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -ffixed-r5 -mno-pic -mrelax
+PLATFORM_LDFLAGS += --relax
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
+COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
-TEXT_BASE = 0xF0000000
+TEXT_BASE = 0xFFE00000
# Copyright (C) 2000, 2001, 2002, 2003
# The LEOX team <team@leox.org>, http://www.leox.org
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# LEOX.org is about the development of free hardware and software resources
# for system on chip.
#
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o flash.o
-OBJS = $(BOARD).o flash.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../menu)
+$(shell mkdir -p $(obj)../bios_emulator)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \
via686.o i8259.o ../bios_emulator/x86interface.o \
interrupts.o ps2kbd.o video.o usb_uhci.o enet.o \
../menu/cmd_menu.o cmd_boota.o nvram.o
-AOBJS = board_asm_init.o memio.o
-
-OBJS = $(COBJS) $(AOBJS)
+SOBJS = board_asm_init.o memio.o
EMUDIR = ../bios_emulator/scitech/src/x86emu/
EMUOBJ = $(EMUDIR)decode.o $(EMUDIR)ops2.o $(EMUDIR)fpu.o $(EMUDIR)prim_ops.o \
$(EMUDIR)ops.o $(EMUDIR)sys.o
-EMUSRC = $(EMUOBJ:.o=.c)
+EMUSRC = $(EMUOBJ:.o=.c)
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+EMUOBJ := $(addprefix $(obj),$(EMUOBJ))
-$(LIB): .depend $(OBJS) $(EMUSRC)
- make libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(EMUSRC)
+ make $(obj)libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE)
-rm $(LIB)
- $(AR) crv $@ $(OBJS) $(EMUOBJ)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(EMUOBJ)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
SOBJS = ../common/misc.o
-OBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
+COBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
sdram_init.o ../common/intel_flash.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
SOBJS = ../common/misc.o
-OBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
+COBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
sdram_init.o ../common/intel_flash.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o eccx.o
+COBJS = $(BOARD).o flash.o eccx.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# Copyright (C) 2004 Arabella Software Ltd.
# Yuli Barcohen <yuli@arabellasw.com>
#
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
-OBJS := $(BOARD).o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
-
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := adsvix.o pcmcia.o
+COBJS := adsvix.o pcmcia.o
SOBJS := lowlevel_init.o pxavoltage.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
-# (C) Copyright 2003-2005
+#
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o flash.o
-OBJS := $(BOARD).o flash.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001-2004
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
-
-OBJS := $(BOARD).o flash.o misc.o
+LIB = $(obj)lib$(BOARD).a
+COBJS := $(BOARD).o flash.o misc.o
SOBJS = vectors.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001-2004
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
-
-OBJS := $(BOARD).o flash.o misc.o
+LIB = $(obj)lib$(BOARD).a
+COBJS := $(BOARD).o flash.o misc.o
SOBJS = vectors.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001-2004
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
COMOBJS := ../common/AMDLV065D.o ../common/epled.o
-OBJS := $(BOARD).o $(COMOBJS)
+COBJS := $(BOARD).o $(COMOBJS)
-SOBJS =
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001-2004
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
COMOBJS := ../common/AMDLV065D.o ../common/epled.o
-OBJS := $(BOARD).o $(COMOBJS)
+COBJS := $(BOARD).o $(COMOBJS)
-SOBJS =
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001-2004
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
COMOBJS := ../common/AMDLV065D.o ../common/epled.o
-OBJS := $(BOARD).o $(COMOBJS)
+COBJS := $(BOARD).o $(COMOBJS)
-SOBJS =
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o
-OBJS += flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#include <ppc4xx.h>
#include <asm/processor.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
case FLASH_MAN_SST:
printf("SST ");
break;
+ case FLASH_MAN_MX:
+ printf ("MACRONIX ");
+ break;
default:
printf("Unknown Vendor ");
break;
case FLASH_STMW320DT:
printf ("M29W320DT (32 M, top sector)\n");
break;
+ case FLASH_MXLV320T:
+ printf ("MXLV320T (32 Mbit, top sector)\n");
+ break;
default:
printf("Unknown Chip Type\n");
break;
return (0); /* no or unknown flash */
}
- value = addr2[1]; /* device ID */
+ value = addr2[1]; /* device ID */
DEBUGF("\nFLASH DEVICEID: %x\n", value);
switch (value) {
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
+ info->size = 0x0080000; /* => 512 KiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
+ info->size = 0x0080000; /* => 512 KiB */
break;
case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
- info->size = 0x0080000; /* => 512 ko */
+ info->size = 0x0080000; /* => 512 KiB */
break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
info->flash_id += FLASH_AMD016;
info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
+ info->size = 0x00200000; /* => 2 MiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
info->flash_id += FLASH_AMDLV033C;
info->sector_count = 64;
- info->size = 0x00400000;
- break; /* => 4 MB */
+ info->size = 0x00400000; /* => 4 MiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
+ info->size = 0x00080000; /* => 512 KiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
+ info->size = 0x00080000; /* => 512 KiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
+ info->size = 0x00100000; /* => 1 MiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
+ info->size = 0x00100000; /* => 1 MiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
+ info->size = 0x00200000; /* => 2 MiB */
+ break;
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
+ info->size = 0x00200000; /* => 2 MiB */
+ break;
default:
info->flash_id = FLASH_UNKNOWN;
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
+ /* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
base + (i * 0x00010000) - 0x00030000;
}
} else {
- /* set sector offsets for top boot block type */
+ /* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
{
if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
return flash_erase_2(info, s_first, s_last);
} else {
{
if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
return write_word_2(info, dest, data);
} else {
case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
+ case (CFG_FLASH_WORD_SIZE) MX_MANUFACT:
+ info->flash_id = FLASH_MAN_MX;
+ break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
return (0); /* no or unknown flash */
}
- value = addr2[1]; /* device ID */
+ value = addr2[1]; /* device ID */
DEBUGF("\nFLASH DEVICEID: %x\n", value);
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
+ info->size = 0x00400000; break; /* => 4 MiB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
+ info->size = 0x00400000; break; /* => 4 MiB */
case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
info->flash_id += FLASH_STMW320DT;
info->sector_count = 67;
- info->size = 0x00400000; break; /* => 4 MB */
+ info->size = 0x00400000; break; /* => 4 MiB */
+
+ case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
+ info->flash_id += FLASH_MXLV320T;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
default:
info->flash_id = FLASH_UNKNOWN;
--i;
info->start[i] = base;
}
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00002000;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000a000;
+ info->start[i--] = base + info->size - 0x0000c000;
+ info->start[i--] = base + info->size - 0x0000e000;
+ info->start[i--] = base + info->size - 0x00010000;
+
+ for (; i >= 0; i--)
+ info->start[i] = base + i * 0x00010000;
} else {
if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
+ /* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
base + (i * 0x00010000) - 0x00030000;
}
} else {
- /* set sector offsets for top boot block type */
+ /* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o
-OBJS += flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
/*
-* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
#include <ppc_asm.tmpl>
#include <config.h>
/* General */
#define TLB_VALID 0x00000200
+#define _256M 0x10000000
/* Supported page sizes */
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
+#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
+#define SZ_8M 0x00000060
#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
+#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
+#define TLB2(a) ( (a)&0x00000fbf )
#define tlbtab_start\
mflr r1 ;\
tlbtab:
tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
tlbtab_end
--- /dev/null
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o sdram.o
+SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EPx Reference Platform (Sequoia) board
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID 0x00000200
+#define _256M 0x10000000
+
+/* Supported page sizes */
+
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_8M 0x00000060
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
+
+/* Storage attributes */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
+
+/* Access control */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
+
+/* Some handy macros */
+
+#define EPN(e) ((e) & 0xfffffc00)
+#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a) ( (a)&0x00000fbf )
+
+#define tlbtab_start\
+ mflr r1 ;\
+ bl 0f ;
+
+#define tlbtab_end\
+ .long 0, 0, 0 ; \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+#ifndef CONFIG_NAND_SPL
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+#else
+ tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+ /* TLB-entry for DDR SDRAM (Up to 2GB) */
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+#ifdef CFG_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+
+ /* TLB-entry for EBC */
+ tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for NAND */
+ tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+
+ /*TLB-entry PCI registers*/
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ tlbtab_end
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+ /*
+ * For NAND booting the first TLB has to be reconfigured to full size
+ * and with caching disabled after running from RAM!
+ */
+#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
+#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ .globl reconfig_tlb0
+reconfig_tlb0:
+ sync
+ isync
+ addi r4,r0,0x0000 /* TLB entry #0 */
+ lis r5,TLB00@h
+ ori r5,r5,TLB00@l
+ tlbwe r5,r4,0x0000 /* Save it out */
+ lis r5,TLB01@h
+ ori r5,r5,TLB01@l
+ tlbwe r5,r4,0x0001 /* Save it out */
+ lis r5,TLB02@h
+ ori r5,r5,TLB02@l
+ tlbwe r5,r4,0x0002 /* Save it out */
+ sync
+ isync
+ blr
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+
+/*************************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+long int initdram (int board_type)
+{
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+ volatile ulong val;
+
+ mtsdram(DDR0_02, 0x00000000);
+
+ mtsdram(DDR0_00, 0x0000190A);
+ mtsdram(DDR0_01, 0x01000000);
+ mtsdram(DDR0_03, 0x02030602);
+ mtsdram(DDR0_04, 0x13030300);
+ mtsdram(DDR0_05, 0x0202050E);
+ mtsdram(DDR0_06, 0x0104C823);
+ mtsdram(DDR0_07, 0x000D0100);
+ mtsdram(DDR0_08, 0x02360001);
+ mtsdram(DDR0_09, 0x00011D5F);
+ mtsdram(DDR0_10, 0x00000300);
+ mtsdram(DDR0_11, 0x0027C800);
+ mtsdram(DDR0_12, 0x00000003);
+ mtsdram(DDR0_14, 0x00000000);
+ mtsdram(DDR0_17, 0x19000000);
+ mtsdram(DDR0_18, 0x19191919);
+ mtsdram(DDR0_19, 0x19191919);
+ mtsdram(DDR0_20, 0x0B0B0B0B);
+ mtsdram(DDR0_21, 0x0B0B0B0B);
+ mtsdram(DDR0_22, 0x00267F0B);
+ mtsdram(DDR0_23, 0x00000000);
+ mtsdram(DDR0_24, 0x01010002);
+ mtsdram(DDR0_26, 0x5B260181);
+ mtsdram(DDR0_27, 0x0000682B);
+ mtsdram(DDR0_28, 0x00000000);
+ mtsdram(DDR0_31, 0x00000000);
+ mtsdram(DDR0_42, 0x01000006);
+ mtsdram(DDR0_43, 0x050A0200);
+ mtsdram(DDR0_44, 0x00000005);
+ mtsdram(DDR0_02, 0x00000001);
+
+ /*
+ * Wait for DCC master delay line to finish calibration
+ */
+ mfsdram(DDR0_17, val);
+ while (((val >> 8) & 0x000007f) == 0) {
+ mfsdram(DDR0_17, val);
+ }
+#endif /* #ifndef CONFIG_NAND_U_BOOT */
+
+ return (CFG_MBYTES_SDRAM << 20);
+}
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include "sequoia.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+int board_early_init_f(void)
+{
+ unsigned long sdr0_cust0;
+ unsigned long sdr0_pfc1, sdr0_pfc2;
+ register uint reg;
+
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, 0xb8400000);
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ *-------------------------------------------------------------------*/
+ /* test-only: take GPIO init from pcs440ep ???? in config file */
+ out32(GPIO0_OR, 0x00000000);
+ out32(GPIO0_TCR, 0x0000000f);
+ out32(GPIO0_OSRL, 0x50015400);
+ out32(GPIO0_OSRH, 0x550050aa);
+ out32(GPIO0_TSRL, 0x50015400);
+ out32(GPIO0_TSRH, 0x55005000);
+ out32(GPIO0_ISR1L, 0x50000000);
+ out32(GPIO0_ISR1H, 0x00000000);
+ out32(GPIO0_ISR2L, 0x00000000);
+ out32(GPIO0_ISR2H, 0x00000100);
+ out32(GPIO0_ISR3L, 0x00000000);
+ out32(GPIO0_ISR3H, 0x00000000);
+
+ out32(GPIO1_OR, 0x00000000);
+ out32(GPIO1_TCR, 0xc2000000);
+ out32(GPIO1_OSRL, 0x5c280000);
+ out32(GPIO1_OSRH, 0x00000000);
+ out32(GPIO1_TSRL, 0x0c000000);
+ out32(GPIO1_TSRH, 0x00000000);
+ out32(GPIO1_ISR1L, 0x00005550);
+ out32(GPIO1_ISR1H, 0x00000000);
+ out32(GPIO1_ISR2L, 0x00050000);
+ out32(GPIO1_ISR2H, 0x00000000);
+ out32(GPIO1_ISR3L, 0x01400000);
+ out32(GPIO1_ISR3H, 0x00000000);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic0sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000000); /* all non-critical */
+ mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+
+ /* 50MHz tmrclk */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+
+ /* clear write protects */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
+
+ /* enable Ethernet */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;
+
+ /* enable USB device */
+ *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* PCI arbiter enabled */
+ mfsdr(sdr_pci0, reg);
+ mtsdr(sdr_pci0, 0x80000000 | reg);
+
+ /* setup NAND FLASH */
+ mfsdr(SDR0_CUST0, sdr0_cust0);
+ sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ (0x80000000 >> (28 + CFG_NAND_CS));
+ mtsdr(SDR0_CUST0, sdr0_cust0);
+
+ return 0;
+}
+
+/*---------------------------------------------------------------------------+
+ | misc_init_r.
+ +---------------------------------------------------------------------------*/
+int misc_init_r(void)
+{
+ uint pbcr;
+ int size_val = 0;
+#ifdef CONFIG_440EPX
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+ char *act = getenv("usbact");
+#endif
+
+ /*
+ * FLASH stuff...
+ */
+
+ /* Re-do sizing to get full correct info */
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+ mtdcr(ebccfga, pb3cr);
+#else
+ mtdcr(ebccfga, pb0cr);
+#endif
+ pbcr = mfdcr(ebccfgd);
+ switch (gd->bd->bi_flashsize) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ case 32 << 20:
+ size_val = 5;
+ break;
+ case 64 << 20:
+ size_val = 6;
+ break;
+ case 128 << 20:
+ size_val = 7;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+ mtdcr(ebccfga, pb3cr);
+#else
+ mtdcr(ebccfga, pb0cr);
+#endif
+ mtdcr(ebccfgd, pbcr);
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ /*
+ * USB suff...
+ */
+#ifdef CONFIG_440EPX
+ if (act == NULL || strcmp(act, "hostdev") == 0) {
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+
+ /* An 8-bit/60MHz interface is the only possible alternative
+ when connecting the Device to the PHY */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+
+ /* To enable the USB 2.0 Device function through the UTMI interface */
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /*clear resets*/
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy) Device(ext phy)\n");
+
+ } else if (strcmp(act, "dev") == 0) {
+ /*-------------------PATCH-------------------------------*/
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x672c6000);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000080);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x60206000);
+
+ *(unsigned int *)(0xe0000350) = 0x00000001;
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x60306000);
+ /*-------------------PATCH-------------------------------*/
+
+ /* SDR Setting */
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+ mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
+
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
+
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
+
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /*clear resets*/
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Device(int phy)\n");
+ }
+#endif /* CONFIG_440EPX */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+#ifdef CONFIG_440EPX
+ printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
+#else
+ printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
+#endif
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+ unsigned long *mem = (unsigned long *)0;
+ const unsigned long kend = (1024 / sizeof(unsigned long));
+ unsigned long k, n;
+
+ mtmsr(0);
+
+ for (k = 0; k < CFG_MBYTES_SDRAM;
+ ++k, mem += (1024 / sizeof(unsigned long))) {
+ if ((k & 1023) == 0) {
+ printf("%3d MB\r", k / 1024);
+ }
+
+ memset(mem, 0xaaaaaaaa, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+
+ memset(mem, 0x55555555, 1024);
+ for (n = 0; n < kend; ++n) {
+ if (mem[n] != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n",
+ (uint) & mem[n]);
+ return 1;
+ }
+ }
+ }
+ printf("SDRAM test passes\n");
+ return 0;
+}
+#endif
+
+/*************************************************************************
+ * pci_pre_init
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+ unsigned long addr;
+#if 0
+ /*--------------------------------------------------------------------------+
+ * Cactus is always configured as the host & requires the
+ * PCI arbiter to be enabled ???
+ *--------------------------------------------------------------------------*/
+ unsigned long strap;
+ mfsdr(sdr_sdstp1, strap);
+ if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
+ printf("PCI: SDR0_STRP1[PAE] not set.\n");
+ printf("PCI: Configuration aborted.\n");
+ return 0;
+ }
+#endif
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB3 devices to 0.
+ | Set PLB3 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp1, addr);
+ mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb3_acr);
+ mtdcr(plb3_acr, addr | 0x80000000);
+
+ /*-------------------------------------------------------------------------+
+ | Set priority for all PLB4 devices to 0.
+ +-------------------------------------------------------------------------*/
+ mfsdr(sdr_amp0, addr);
+ mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(plb4_acr, addr);
+
+ /*-------------------------------------------------------------------------+
+ | Set Nebula PLB4 arbiter to fair mode.
+ +-------------------------------------------------------------------------*/
+ /* Segment0 */
+ addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+ addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+ addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+ addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+ mtdcr(plb0_acr, addr);
+
+ /* Segment1 */
+ addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+ addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+ addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+ addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+ mtdcr(plb1_acr, addr);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /*--------------------------------------------------------------------------+
+ * Set up Direct MMIO registers
+ *--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------+
+ | PowerPC440EPX PCI Master configuration.
+ | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +--------------------------------------------------------------------------*/
+ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
+ out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
+
+ out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+
+ /*--------------------------------------------------------------------------+
+ * Set up Configuration registers
+ *--------------------------------------------------------------------------*/
+
+ /* Program the board's subsystem id/vendor id */
+ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+ CFG_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+ /* Configure command register as bus master */
+ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+ /* 240nS PCI clock */
+ pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_write_config_word(0, PCI_ERREN, 0);
+
+ pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ * pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ unsigned short temp_short;
+
+ /*--------------------------------------------------------------------------+
+ | Write the PowerPC440 EP PCI Configuration regs.
+ | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ | Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ +--------------------------------------------------------------------------*/
+ pci_read_config_word(0, PCI_COMMAND, &temp_short);
+ pci_write_config_word(0, PCI_COMMAND,
+ temp_short | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ * is_pci_host
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ /* Cactus is always configured as host. */
+ return (1);
+}
+#endif /* defined(CONFIG_PCI) */
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*----------------------------------------------------------------------------+
+ | EBC Configuration Register - EBC0_CFG
+ +----------------------------------------------------------------------------*/
+/* External Bus Three-State Control */
+#define EBC0_CFG_EBTC_DRIVEN 0x80000000
+/* Device-Paced Time-out Disable */
+#define EBC0_CFG_PTD_ENABLED 0x00000000
+/* Ready Timeout Count */
+#define EBC0_CFG_RTC_MASK 0x38000000
+#define EBC0_CFG_RTC_16PERCLK 0x00000000
+#define EBC0_CFG_RTC_32PERCLK 0x08000000
+#define EBC0_CFG_RTC_64PERCLK 0x10000000
+#define EBC0_CFG_RTC_128PERCLK 0x18000000
+#define EBC0_CFG_RTC_256PERCLK 0x20000000
+#define EBC0_CFG_RTC_512PERCLK 0x28000000
+#define EBC0_CFG_RTC_1024PERCLK 0x30000000
+#define EBC0_CFG_RTC_2048PERCLK 0x38000000
+/* External Master Priority Low */
+#define EBC0_CFG_EMPL_LOW 0x00000000
+#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
+#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
+#define EBC0_CFG_EMPL_HIGH 0x06000000
+/* External Master Priority High */
+#define EBC0_CFG_EMPH_LOW 0x00000000
+#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
+#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
+#define EBC0_CFG_EMPH_HIGH 0x01800000
+/* Chip Select Three-State Control */
+#define EBC0_CFG_CSTC_DRIVEN 0x00400000
+/* Burst Prefetch */
+#define EBC0_CFG_BPF_ONEDW 0x00000000
+#define EBC0_CFG_BPF_TWODW 0x00100000
+#define EBC0_CFG_BPF_FOURDW 0x00200000
+/* External Master Size */
+#define EBC0_CFG_EMS_8BIT 0x00000000
+/* Power Management Enable */
+#define EBC0_CFG_PME_DISABLED 0x00000000
+#define EBC0_CFG_PME_ENABLED 0x00020000
+/* Power Management Timer */
+#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
+
+#define SDR0_USB0 0x0320 /* USB Control Register */
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ /* Align to next NAND block */
+ . = ALIGN(0x4000);
+ common/environment.o (.ppcenv)
+ /* Keep some space here for redundant env and potential bad env blocks */
+ . = ALIGN(0x10000);
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o
+COBJS = $(BOARD).o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o
+COBJS = $(BOARD).o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o cmd_yucca.o
+COBJS = $(BOARD).o flash.o cmd_yucca.o
SOBJS = init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
*************************************************************************/
.section .bootpg,"ax"
- .globl tlbtab
-tlbtab:
+/**************************************************************************
+ * TLB table for revA
+ *************************************************************************/
+ .globl tlbtabA
+tlbtabA:
+ tlbtab_start
+ tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
+
+ tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+ tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
+
+ tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbtab_end
+
+/**************************************************************************
+ * TLB table for revB
+ *
+ * Notice: revB of the 440SPe chip is very strict about PLB real addresses
+ * and ranges to be mapped for config space: it seems to only work with
+ * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
+ * set otherwise) while revA uses c_nnnn_nnnn.
+ *************************************************************************/
+ .globl tlbtabB
+tlbtabB:
tlbtab_start
tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
- tlbentry(CFG_FPGA_BASE,SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
+ tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
- tlbentry(CFG_OPER_FLASH,SZ_16M,0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+
+ tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbtab_end
* MA 02111-1307 USA
*
* Port to AMCC-440SPE Evaluation Board SOP - April 2005
+ *
+ * PCIe supporting routines derived from Linux 440SPe PCIe driver.
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <i2c.h>
+#include <asm-ppc/io.h>
+
#include "yucca.h"
+#include "../cpu/ppc4xx/440spe_pcie.h"
+
+#undef PCIE_ENDPOINT
+/* #define PCIE_ENDPOINT 1 */
void fpga_init (void);
unsigned long ppcMfcpr(unsigned long cpr_reg);
unsigned long ppcMfsdr(unsigned long sdr_reg);
+int ppc440spe_init_pcie_rootport(int port);
+void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
+
#define DEBUG_ENV
#ifdef DEBUG_ENV
#define DEBUGF(fmt,args...) printf(fmt ,##args)
static long int yucca_probe_for_dimms(void)
{
- long int dimm_installed[MAXDIMMS];
- long int dimm_num, probe_result;
- long int dimms_found = 0;
- uchar dimm_addr = IIC0_DIMM0_ADDR;
+ int dimm_installed[MAXDIMMS];
+ int dimm_num, result;
+ int dimms_found = 0;
+ uchar dimm_addr = IIC0_DIMM0_ADDR;
+ uchar dimm_spd_data[MAX_SPD_BYTES];
for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
/* check if there is a chip at the dimm address */
dimm_addr = IIC0_DIMM1_ADDR;
break;
}
- probe_result = i2c_probe(dimm_addr);
- if (probe_result == 0) {
+ result = i2c_probe(dimm_addr);
+
+ memset(dimm_spd_data, 0, MAX_SPD_BYTES * sizeof(char));
+ if (result == 0) {
+ /* read first byte of SPD data, if there is any data */
+ result = i2c_read(dimm_addr, 0, 1, dimm_spd_data, 1);
+
+ if (result == 0) {
+ result = dimm_spd_data[0];
+ result = result > MAX_SPD_BYTES ?
+ MAX_SPD_BYTES : result;
+ result = i2c_read(dimm_addr, 0, 1,
+ dimm_spd_data, result);
+ }
+ }
+
+ if ((result == 0) &&
+ (dimm_spd_data[64] == MICRON_SPD_JEDEC_ID)) {
dimm_installed[dimm_num] = TRUE;
dimms_found++;
- debug("DIMM slot %d: DDR2 SDRAM detected\n",dimm_num);
+ debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
} else {
dimm_installed[dimm_num] = FALSE;
debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#if defined(CONFIG_PCI)
/*************************************************************************
* is_pci_host
*
*
*
************************************************************************/
-#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* The yucca board is always configured as host. */
return 1;
}
+
+int yucca_pcie_card_present(int port)
+{
+ u16 reg;
+
+ reg = in_be16((u16 *)FPGA_REG1C);
+ switch(port) {
+ case 0:
+ return !(reg & FPGA_REG1C_PE0_PRSNT);
+ case 1:
+ return !(reg & FPGA_REG1C_PE1_PRSNT);
+ case 2:
+ return !(reg & FPGA_REG1C_PE2_PRSNT);
+ default:
+ return 0;
+ }
+}
+
+/*
+ * For the given slot, set rootpoint mode, send power to the slot,
+ * turn on the green LED and turn off the yellow LED, enable the clock
+ * and turn off reset.
+ */
+void yucca_setup_pcie_fpga_rootpoint(int port)
+{
+ u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
+
+ switch(port) {
+ case 0:
+ rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
+ endpoint = 0;
+ power = FPGA_REG1A_PE0_PWRON;
+ green_led = FPGA_REG1A_PE0_GLED;
+ clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
+ yellow_led = FPGA_REG1A_PE0_YLED;
+ reset_off = FPGA_REG1C_PE0_PERST;
+ break;
+ case 1:
+ rootpoint = 0;
+ endpoint = FPGA_REG1C_PE1_ENDPOINT;
+ power = FPGA_REG1A_PE1_PWRON;
+ green_led = FPGA_REG1A_PE1_GLED;
+ clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
+ yellow_led = FPGA_REG1A_PE1_YLED;
+ reset_off = FPGA_REG1C_PE1_PERST;
+ break;
+ case 2:
+ rootpoint = 0;
+ endpoint = FPGA_REG1C_PE2_ENDPOINT;
+ power = FPGA_REG1A_PE2_PWRON;
+ green_led = FPGA_REG1A_PE2_GLED;
+ clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
+ yellow_led = FPGA_REG1A_PE2_YLED;
+ reset_off = FPGA_REG1C_PE2_PERST;
+ break;
+
+ default:
+ return;
+ }
+
+ out_be16((u16 *)FPGA_REG1A,
+ ~(power | clock | green_led) &
+ (yellow_led | in_be16((u16 *)FPGA_REG1A)));
+
+ out_be16((u16 *)FPGA_REG1C,
+ ~(endpoint | reset_off) &
+ (rootpoint | in_be16((u16 *)FPGA_REG1C)));
+ /*
+ * Leave device in reset for a while after powering on the
+ * slot to give it a chance to initialize.
+ */
+ udelay(250 * 1000);
+
+ out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
+}
+/*
+ * For the given slot, set endpoint mode, send power to the slot,
+ * turn on the green LED and turn off the yellow LED, enable the clock
+ * .In end point mode reset bit is read only.
+ */
+void yucca_setup_pcie_fpga_endpoint(int port)
+{
+ u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
+
+ switch(port) {
+ case 0:
+ rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
+ endpoint = 0;
+ power = FPGA_REG1A_PE0_PWRON;
+ green_led = FPGA_REG1A_PE0_GLED;
+ clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
+ yellow_led = FPGA_REG1A_PE0_YLED;
+ reset_off = FPGA_REG1C_PE0_PERST;
+ break;
+ case 1:
+ rootpoint = 0;
+ endpoint = FPGA_REG1C_PE1_ENDPOINT;
+ power = FPGA_REG1A_PE1_PWRON;
+ green_led = FPGA_REG1A_PE1_GLED;
+ clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
+ yellow_led = FPGA_REG1A_PE1_YLED;
+ reset_off = FPGA_REG1C_PE1_PERST;
+ break;
+ case 2:
+ rootpoint = 0;
+ endpoint = FPGA_REG1C_PE2_ENDPOINT;
+ power = FPGA_REG1A_PE2_PWRON;
+ green_led = FPGA_REG1A_PE2_GLED;
+ clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
+ yellow_led = FPGA_REG1A_PE2_YLED;
+ reset_off = FPGA_REG1C_PE2_PERST;
+ break;
+
+ default:
+ return;
+ }
+
+ out_be16((u16 *)FPGA_REG1A,
+ ~(power | clock | green_led) &
+ (yellow_led | in_be16((u16 *)FPGA_REG1A)));
+
+ out_be16((u16 *)FPGA_REG1C,
+ ~(rootpoint | reset_off) &
+ (endpoint | in_be16((u16 *)FPGA_REG1C)));
+}
+
+static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
+
+void pcie_setup_hoses(void)
+{
+ struct pci_controller *hose;
+ int i, bus;
+
+ /*
+ * assume we're called after the PCIX hose is initialized, which takes
+ * bus ID 0 and therefore start numbering PCIe's from 1.
+ */
+ bus = 1;
+ for (i = 0; i <= 2; i++) {
+ /* Check for yucca card presence */
+ if (!yucca_pcie_card_present(i))
+ continue;
+
+#ifdef PCIE_ENDPOINT
+ yucca_setup_pcie_fpga_endpoint(i);
+ if (ppc440spe_init_pcie_endport(i)) {
+#else
+ yucca_setup_pcie_fpga_rootpoint(i);
+ if (ppc440spe_init_pcie_rootport(i)) {
+#endif
+ printf("PCIE%d: initialization failed\n", i);
+ continue;
+ }
+
+ hose = &pcie_hose[i];
+ hose->first_busno = bus;
+ hose->last_busno = bus;
+ bus++;
+
+ /* setup mem resource */
+ pci_set_region(hose->regions + 0,
+ CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+ CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+ CFG_PCIE_MEMSIZE,
+ PCI_REGION_MEM
+ );
+ hose->region_count = 1;
+ pci_register_hose(hose);
+
+#ifdef PCIE_ENDPOINT
+ ppc440spe_setup_pcie_endpoint(hose, i);
+ /*
+ * Reson for no scanning is endpoint can not generate
+ * upstream configuration accesses.
+ */
+#else
+ ppc440spe_setup_pcie_rootpoint(hose, i);
+ /*
+ * Config access can only go down stream
+ */
+ hose->last_busno = pci_hose_scan(hose);
+#endif
+ }
+}
#endif /* defined(CONFIG_PCI) */
int misc_init_f (void)
#define NUM_TLB_ENTRIES 64
+/* MICRON SPD JEDEC ID Code (first byte) - SPD data byte [64] */
+#define MICRON_SPD_JEDEC_ID 0x2c
+
/*----------------------------------------------------------------------------+
| TLB specific defines.
+----------------------------------------------------------------------------*/
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o
+COBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2002
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := armadillo.o flash.o
+COBJS := armadillo.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# 2004 (c) MontaVista Software, Inc.
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := assabet.o
+COBJS := assabet.o
SOBJS := setup.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := at91rm9200dk.o at45.o flash.o
+COBJS := at91rm9200dk.o at45.o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ti113x.o
+COBJS = $(BOARD).o flash.o ti113x.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o flash.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct sdram_info sdram = {
+ .phys_addr = CFG_SDRAM_BASE,
+ .row_bits = 11,
+ .col_bits = 8,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 5,
+ .txsr = 5,
+};
+
+void board_init_memories(void)
+{
+ gd->sdram_size = sdram_init(&sdram);
+}
+
+void board_init_info(void)
+{
+ gd->bd->bi_phy_id[0] = 0x10;
+ gd->bd->bi_phy_id[1] = 0x11;
+}
--- /dev/null
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS += --gc-sections
+TEXT_BASE = 0x00000000
+LDSCRIPT = $(obj)board/atmel/atstk1000/u-boot.lds
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_ATSTK1000_EXT_FLASH
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+flash_info_t flash_info[1];
+
+static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info)
+{
+ unsigned long flags;
+
+ flags = disable_interrupts();
+
+ dcache_flush_unlocked();
+
+ writew(0xaa, flash + 0x555);
+ writew(0x55, flash + 0xaaa);
+ writew(0x90, flash + 0x555);
+ info->flash_id = readl(flash);
+ writew(0xff, flash);
+
+ readw(flash);
+
+ if (flags)
+ enable_interrupts();
+}
+
+unsigned long flash_init(void)
+{
+ unsigned long addr;
+ unsigned int i;
+
+ gd->bd->bi_flashstart = CFG_FLASH_BASE;
+ gd->bd->bi_flashsize = CFG_FLASH_SIZE;
+ gd->bd->bi_flashoffset = __edata_lma - _text;
+
+ flash_info[0].size = CFG_FLASH_SIZE;
+ flash_info[0].sector_count = 135;
+
+ flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]);
+
+ for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
+ flash_info[0].start[i] = addr;
+ for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
+ flash_info[0].start[i] = addr;
+
+ return CFG_FLASH_SIZE;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+ printf("Flash: Vendor ID: 0x%02x, Product ID: 0x%02x\n",
+ info->flash_id >> 16, info->flash_id & 0xffff);
+ printf("Size: %ld MB in %d sectors\n",
+ info->size >> 10, info->sector_count);
+}
+
+int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ unsigned long flags;
+ unsigned long start_time;
+ uint16_t *fb, *sb;
+ unsigned int i;
+ int ret;
+ uint16_t status;
+
+ if ((s_first < 0) || (s_first > s_last)
+ || (s_last >= info->sector_count)) {
+ puts("Error: first and/or last sector out of range\n");
+ return ERR_INVAL;
+ }
+
+ for (i = s_first; i < s_last; i++)
+ if (info->protect[i]) {
+ printf("Error: sector %d is protected\n", i);
+ return ERR_PROTECTED;
+ }
+
+ fb = (uint16_t *)uncached(info->start[0]);
+
+ dcache_flush_unlocked();
+
+ for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
+ printf("Erasing sector %3d...", i);
+
+ sb = (uint16_t *)uncached(info->start[i]);
+
+ flags = disable_interrupts();
+
+ start_time = get_timer(0);
+
+ /* Unlock sector */
+ writew(0xaa, fb + 0x555);
+ writew(0x70, sb);
+
+ /* Erase sector */
+ writew(0xaa, fb + 0x555);
+ writew(0x55, fb + 0xaaa);
+ writew(0x80, fb + 0x555);
+ writew(0xaa, fb + 0x555);
+ writew(0x55, fb + 0xaaa);
+ writew(0x30, sb);
+
+ /* Wait for completion */
+ ret = ERR_OK;
+ do {
+ /* TODO: Timeout */
+ status = readw(sb);
+ } while ((status != 0xffff) && !(status & 0x28));
+
+ writew(0xf0, fb);
+
+ /*
+ * Make sure the command actually makes it to the bus
+ * before we re-enable interrupts.
+ */
+ readw(fb);
+
+ if (flags)
+ enable_interrupts();
+
+ if (status != 0xffff) {
+ printf("Flash erase error at address 0x%p: 0x%02x\n",
+ sb, status);
+ ret = ERR_PROG_ERROR;
+ break;
+ }
+ }
+
+ if (ctrlc())
+ printf("User interrupt!\n");
+
+ return ERR_OK;
+}
+
+int __flashprog write_buff(flash_info_t *info, uchar *src,
+ ulong addr, ulong count)
+{
+ unsigned long flags;
+ uint16_t *base, *p, *s, *end;
+ uint16_t word, status;
+ int ret = ERR_OK;
+
+ if (addr < info->start[0]
+ || (addr + count) > (info->start[0] + info->size)
+ || (addr + count) < addr) {
+ puts("Error: invalid address range\n");
+ return ERR_INVAL;
+ }
+
+ if (addr & 1 || count & 1 || (unsigned int)src & 1) {
+ puts("Error: misaligned source, destination or count\n");
+ return ERR_ALIGN;
+ }
+
+ base = (uint16_t *)uncached(info->start[0]);
+ end = (uint16_t *)uncached(addr + count);
+
+ flags = disable_interrupts();
+
+ dcache_flush_unlocked();
+ sync_write_buffer();
+
+ for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
+ p < end && !ctrlc(); p++, s++) {
+ word = *s;
+
+ writew(0xaa, base + 0x555);
+ writew(0x55, base + 0xaaa);
+ writew(0xa0, base + 0x555);
+ writew(word, p);
+
+ sync_write_buffer();
+
+ /* Wait for completion */
+ do {
+ /* TODO: Timeout */
+ status = readw(p);
+ } while ((status != word) && !(status & 0x28));
+
+ writew(0xf0, base);
+ readw(base);
+
+ if (status != word) {
+ printf("Flash write error at address 0x%p: 0x%02x\n",
+ p, status);
+ ret = ERR_PROG_ERROR;
+ break;
+ }
+ }
+
+ if (flags)
+ enable_interrupts();
+
+ return ret;
+}
+
+#endif /* CONFIG_ATSTK1000_EXT_FLASH */
--- /dev/null
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0;
+ _text = .;
+ .text : {
+ *(.text)
+ *(.text.*)
+ }
+
+ . = ALIGN(32);
+ __flashprog_start = .;
+ .flashprog : {
+ *(.flashprog)
+ }
+ . = ALIGN(32);
+ __flashprog_end = .;
+
+ . = ALIGN(8);
+ .rodata : {
+ *(.rodata)
+ *(.rodata.*)
+ }
+ _etext = .;
+
+ __data_lma = ALIGN(8);
+ . = 0x24000000;
+ _data = .;
+ .data : AT(__data_lma) {
+ *(.data)
+ *(.data.*)
+ }
+
+ . = ALIGN(4);
+ __u_boot_cmd_start = .;
+ __u_boot_cmd_lma = __data_lma + (__u_boot_cmd_start - _data);
+ .u_boot_cmd : AT(__u_boot_cmd_lma) {
+ KEEP(*(.u_boot_cmd))
+ }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(8);
+ _edata = .;
+ __edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start);
+
+ .bss : AT(__edata_lma) {
+ *(.bss)
+ *(.bss.*)
+ }
+ . = ALIGN(8);
+ _end = .;
+}
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o cmd_bc3450.o
+COBJS := $(BOARD).o cmd_bc3450.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#endif
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
-#define GPIO_PSC1_4 0x01000000UL
void init_ide_reset (void)
{
debug ("ide_reset(%d)\n", idereset);
if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
} else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2002
# James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ns16550.o serial.o m48t59y.o
+COBJS = $(BOARD).o flash.o ns16550.o serial.o m48t59y.o
SOBJS = early_init.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o pcmcia.o
+COBJS = $(BOARD).o flash.o pcmcia.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2005
+# (C) Copyright 2005-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+#ifneq ($(OBJTREE),$(SRCTREE))
+#$(shell mkdir -p $(obj)../common)
+#endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o
#../common/flash.o ../common/vpd.o ../common/am79c874.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#include "cadmus.h"
+
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+
+static void cds_pci_fixup(void *blob)
+{
+ int len;
+ u32 *map;
+ int slot;
+ int i;
+
+ map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
+
+ len /= sizeof(u32);
+
+ slot = get_pci_slot();
+
+ for (i=0;i<len;i+=7) {
+ /* We rotate the interrupt pins so that the mapping
+ * changes depending on the slot the carrier card is in.
+ */
+ map[3] = ((map[3] + slot - 2) % 4) + 1;
+
+ map+=7;
+ }
+}
+#endif
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+
+ cds_pci_fixup(blob);
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+
+/* Config the VIA chip */
+void mpc85xx_config_via(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pci_dev_t bridge;
+
+ /* Enable USB and IDE functions */
+ pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
+
+ pciauto_config_device(hose, dev);
+
+ /*
+ * Force the backplane P2P bridge to have a window
+ * open from 0x00000000-0x00001fff in PCI I/O space.
+ * This allows legacy I/O (i8259, etc) on the VIA
+ * southbridge to be accessed.
+ */
+ bridge = PCI_BDF(0,17,0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
+}
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+ /*
+ * Since the P2P window was forced to cover the fixed
+ * legacy I/O addresses, it is necessary to manually
+ * place the base addresses for the IDE and USB functions
+ * within this window.
+ */
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
+}
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
+}
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
+}
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
+}
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
+}
--- /dev/null
+#ifndef _MPC85xx_VIA_H
+void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+#endif /* _MPC85xx_VIA_H */
#
# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o \
+COBJS := $(BOARD).o \
../common/cadmus.o \
- ../common/eeprom.o
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
SOBJS := init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#include "../common/cadmus.h"
#include "../common/eeprom.h"
+#include "../common/via.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
#if defined(CONFIG_PCI)
-
-/*
- * Initialize PCI Devices, report devices found.
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it.
*/
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- } },
- { }
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
};
-#endif
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_mpc85xxcds_config_table,
+static struct pci_controller hose[] = {
+ { config_table: pci_mpc85xxcds_config_table,},
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
#endif
};
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
- pci_mpc85xx_init(&hose);
+ pci_mpc85xx_init(hose);
#endif
}
#
# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o \
+COBJS := $(BOARD).o \
../common/cadmus.o \
- ../common/eeprom.o
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
SOBJS := init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
+#include <miiphy.h>
#include "../common/cadmus.h"
#include "../common/eeprom.h"
+#include "../common/via.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
#if defined(CONFIG_PCI)
-
-/*
- * Initialize PCI Devices, report devices found.
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it.
*/
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- } },
- { }
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
};
-#endif
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_mpc85xxcds_config_table,
+static struct pci_controller hose[] = {
+ { config_table: pci_mpc85xxcds_config_table,},
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
#endif
};
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif
}
+
+int last_stage_init(void)
+{
+ unsigned short temp;
+
+ /* Change the resistors for the PHY */
+ /* This is needed to get the RGMII working for the 1.3+
+ * CDS cards */
+ if (get_board_version() == 0x13) {
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 29, 18);
+
+ miiphy_read(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, &temp);
+
+ temp = (temp & 0xf03f);
+ temp |= 2 << 9; /* 36 ohm */
+ temp |= 2 << 6; /* 39 ohm */
+
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, temp);
+
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 29, 3);
+
+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, 0x8000);
+ }
+
+ return 0;
+}
#
# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o \
+COBJS := $(BOARD).o \
../common/cadmus.o \
- ../common/eeprom.o
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
SOBJS := init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
* 0xf000_0000 0xf7ff_ffff SDRAM 128M
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
#include "../common/cadmus.h"
#include "../common/eeprom.h"
+#include "../common/via.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
}
#endif
-#if defined(CONFIG_PCI)
-
-/*
- * Initialize PCI Devices, report devices found.
+#ifdef CONFIG_PCI
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it
*/
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- } },
- { }
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}
};
-#endif
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
+
+static struct pci_controller hose[] = {
+ {
config_table: pci_mpc85xxcds_config_table,
+ },
+#ifdef CONFIG_MPC85XX_PCI2
+ { }
#endif
};
-#endif /* CONFIG_PCI */
+#endif
void
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
- pci_mpc85xx_init(&hose);
+ pci_mpc85xx_init(hose);
#endif
}
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := cerf250.o flash.o
+COBJS := cerf250.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := cm4008.o flash.o
+COBJS := cm4008.o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := cm41xx.o flash.o
+COBJS := cm41xx.o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o
+COBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de
-#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de
#
# See file CREDITS for list of people who contributed to this
# project.
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := flash.o cmi.o
-OBJS := flash.o cmi.o
-SOBJS :=
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o
-SOBJS :=
+COBJS := mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001-2003
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o plx9030.o pd67290.o
+COBJS = $(BOARD).o flash.o plx9030.o pd67290.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001-2005
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
*/
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
-
+
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
(uchar *) CFG_SDRAM_BASE);
-
+
size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL,
(uchar *) CFG_SDRAM_BASE);
-
+
psize = max(size8,max(size9,size10));
-
+
if (psize == size8) {
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
#
-# (C) Copyright 2000, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := cradle.o flash.o
+COBJS := cradle.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
# HACK: depend needs bootscript.c, which needs tools/mkimage, which is not
# built in the depend stage. So... put bootscript.o here, not in OBJS
-$(LIB): $(OBJS) $(SOBJS) bootscript.o
- $(AR) crv $@ $^
+$(LIB): $(OBJS) $(SOBJS) $(obj)bootscript.o
+ $(AR) $(ARFLAGS) $@ $^
clean:
- rm -f $(SOBJS) $(OBJS) bootscript.c bootscript.image bootscript.o
+ rm -f $(SOBJS) $(OBJS) $(obj)bootscript.c \
+ $(obj)bootscript.image $(obj)bootscript.o
distclean: clean
rm -f $(LIB) core *.bak .depend
-$(BOARD).o : $(BOARD).c bootscript.o
+$(obj)$(BOARD).o : $(src)$(BOARD).c $(obj)bootscript.o
-bootscript.c: bootscript.image
+$(obj)bootscript.c: $(obj)bootscript.image
od -t x1 -v -A x $^ | awk -f x2c.awk > $@
-bootscript.image: bootscript.hush Makefile
- -$(TOPDIR)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d bootscript.hush $@
+$(obj)bootscript.image: $(src)bootscript.hush $(src)Makefile
+ -$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $(src)bootscript.hush $@
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := csb226.o flash.o
+COBJS := csb226.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-#OBJS = $(BOARD).o flash.o
-#OBJS = $(BOARD).o strataflash.o
-OBJS = $(BOARD).o
+#COBJS = $(BOARD).o flash.o
+#COBJS = $(BOARD).o strataflash.o
+COBJS = $(BOARD).o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-#OBJS = $(BOARD).o flash.o
-#OBJS = $(BOARD).o strataflash.o
-OBJS = $(BOARD).o
+#COBJS = $(BOARD).o flash.o
+#COBJS = $(BOARD).o strataflash.o
+COBJS = $(BOARD).o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := csb637.o
+COBJS := csb637.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2002
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := B2.o flash.o
+COBJS := B2.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o nand.o
+COBJS = $(BOARD).o flash.o nand.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = lowlevel_init.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := delta.o nand.o
+COBJS := delta.o nand.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := dnp1110.o flash.o
+COBJS := dnp1110.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o
-SOBJS =
+COBJS = $(BOARD).o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o pci.o misc.o el_srom.o dc_srom.o l2cache.o
+COBJS = $(BOARD).o flash.o pci.o misc.o el_srom.o dc_srom.o l2cache.o
SOBJS = asm_init.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o
+COBJS = $(BOARD).o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o
SOBJS = asm_init.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
+COBJS := $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
*****************************************************************************/
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
-#define GPIO_PSC1_4 0x01000000UL
-
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
debug ("ide_reset(%d)\n", idereset);
if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
} else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
+COBJS = $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2002
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := ep7312.o flash.o
+COBJS := ep7312.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o mii_phy.o
+COBJS = $(BOARD).o flash.o mii_phy.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# EP82xxM series boards by Embedded Planet
+
+TEXT_BASE = 0xFFF00000
--- /dev/null
+/*
+ * Copyright (C) 2006 Embedded Planet, LLC.
+ *
+ * Support for Embedded Planet EP82xxM boards.
+ * Tested on EP82xxM (MPC8270).
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+#include <asm/m8260_pci.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
+#include <miiphy.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CFG_FCC2 1
+#define CFG_FCC3 1
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 0, 0, 0, 0, 1 }, /* PA31 */
+ /* PA30 */ { 0, 0, 0, 0, 0, 1 }, /* PA30 */
+ /* PA29 */ { 0, 0, 0, 0, 0, 1 }, /* PA29 */
+ /* PA28 */ { 0, 0, 0, 0, 0, 1 }, /* PA28 */
+ /* PA27 */ { 0, 0, 0, 0, 0, 1 }, /* PA27 */
+ /* PA26 */ { 0, 0, 0, 0, 0, 1 }, /* PA26 */
+ /* PA25 */ { 0, 0, 0, 0, 0, 1 }, /* PA25 */
+ /* PA24 */ { 0, 0, 0, 0, 0, 1 }, /* PA24 */
+ /* PA23 */ { 0, 0, 0, 0, 0, 1 }, /* PA23 */
+ /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
+ /* PA21 */ { 0, 0, 0, 0, 0, 1 }, /* PA21 */
+ /* PA20 */ { 0, 0, 0, 0, 0, 1 }, /* PA20 */
+ /* PA19 */ { 0, 0, 0, 0, 0, 1 }, /* PA19 */
+ /* PA18 */ { 0, 0, 0, 0, 0, 1 }, /* PA18 */
+ /* PA17 */ { 0, 0, 0, 0, 0, 1 }, /* PA17 */
+ /* PA16 */ { 0, 0, 0, 0, 0, 1 }, /* PA16 */
+ /* PA15 */ { 0, 0, 0, 0, 0, 1 }, /* PA15 */
+ /* PA14 */ { 0, 0, 0, 0, 0, 1 }, /* PA14 */
+ /* PA13 */ { 0, 0, 0, 0, 0, 1 }, /* PA13 */
+ /* PA12 */ { 0, 0, 0, 0, 0, 1 }, /* PA12 */
+ /* PA11 */ { 0, 0, 0, 0, 0, 1 }, /* PA11 */
+ /* PA10 */ { 0, 0, 0, 0, 0, 1 }, /* PA10 */
+ /* PA9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC2 TxD */
+ /* PA8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC2 RxD */
+ /* PA7 */ { 0, 0, 0, 0, 0, 1 }, /* PA7 */
+ /* PA6 */ { 0, 0, 0, 0, 0, 1 }, /* PA6 */
+ /* PA5 */ { 0, 0, 0, 0, 0, 1 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 0, 0, 1 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 0, 0, 1 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 0, 0, 1 }, /* PA2 */
+ /* PA1 */ { 0, 0, 0, 0, 0, 1 }, /* PA1 */
+ /* PA0 */ { 0, 0, 0, 0, 0, 1 } /* PA0 */
+ },
+
+ /* Port B */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
+ /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
+ /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 CTS# */
+ /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
+ /* PC27 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3: TXD[0] */
+ /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
+ /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
+ /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
+ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
+ /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* RxClk (CLK13) */
+ /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* TxClk (CLK14) */
+ /* PC17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* RxClk (CLK15) */
+ /* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* TxClk (CLK16) */
+ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 CD# */
+ /* PC13 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CTS# */
+ /* PC12 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CD# */
+ /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
+ /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 CD# */
+ /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
+ /* PC8 */ { 1, 1, 1, 0, 0, 0 }, /* SCC3 CTS# */
+ /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
+ /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
+ /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 1 }, /* SCC1 TXD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS# */
+ /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
+ /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
+ /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS# */
+ /* PD25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
+ /* PD24 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 TXD */
+ /* PD23 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 RTS# */
+ /* PD22 */ { 0, 0, 0, 0, 0, 1 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 0, 0, 1 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 0, 0, 1 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 0, 0, 1 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 0, 0, 1 }, /* PD18 */
+ /* PD17 */ { 0, 0, 0, 0, 0, 1 }, /* PD17 */
+ /* PD16 */ { 0, 0, 0, 0, 0, 1 }, /* PD16 */
+ /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SCL */
+ /* PD13 */ { 0, 0, 0, 0, 0, 1 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 1 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 1 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 1 }, /* PD10 */
+ /* PD9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC1 TxD */
+ /* PD8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 RxD */
+ /* PD7 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 SMSYN */
+ /* PD6 */ { 0, 0, 0, 0, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 0, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 0, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ }
+};
+
+#ifdef CONFIG_PCI
+typedef struct pci_ic_s {
+ unsigned long pci_int_stat;
+ unsigned long pci_int_mask;
+}pci_ic_t;
+#endif
+
+int board_early_init_f (void)
+{
+ vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+ bcsr[4] |= 0x30; /* Turn the LEDs off */
+
+#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
+ bcsr[6] |= 0x10;
+#endif
+#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
+ bcsr[7] |= 0x10;
+#endif
+
+#if CFG_FCC3
+ bcsr[8] |= 0xC0;
+#endif /* CFG_FCC3 */
+#if CFG_FCC2
+ bcsr[8] |= 0x30;
+#endif /* CFG_FCC2 */
+
+ return 0;
+}
+
+long int initdram(int board_type)
+{
+ /* Size in MB of SDRAM populated on board*/
+ long int msize = 256;
+
+#ifndef CFG_RAMBOOT
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8260_t *memctl = &immap->im_memctl;
+ uint psdmr = CFG_PSDMR;
+ int i;
+
+ unsigned char ramtmp;
+ unsigned char *ramptr1 = (unsigned char *)0x00000110;
+
+ memctl->memc_mptpr = CFG_MPTPR;
+
+udelay(400);
+
+ /* Initialise 60x bus SDRAM */
+ memctl->memc_psrt = CFG_PSRT;
+ memctl->memc_or1 = CFG_SDRAM_OR;
+ memctl->memc_br1 = CFG_SDRAM_BR;
+ memctl->memc_psdmr = psdmr;
+
+udelay(400);
+
+ memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+ ramtmp = *ramptr1;
+ memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+ for (i = 0; i < 8; i++) {
+ memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+ }
+ ramtmp = *ramptr1;
+ memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
+ *ramptr1 = 0xFF;
+ memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
+#endif /* !CFG_RAMBOOT */
+
+ /* Return total 60x bus SDRAM size */
+ return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+ vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+ puts("Board: ");
+ switch (bcsr[0]) {
+ case 0x0A:
+ printf("EP82xxM 1.0 CPLD revision %d\n", bcsr[1]);
+ break;
+ default:
+ printf("unknown: ID=%02X\n", bcsr[0]);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc8250_init(&hose);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8260/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# Copyright (C) 2004 Arabella Software Ltd.
# Yuli Barcohen <yuli@arabellasw.com>
#
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
-OBJS := $(BOARD).o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o ../common/pci.o
+COBJS = $(BOARD).o flash.o ../common/misc.o ../common/pci.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o strataflash.o ../common/misc.o
+COBJS = $(BOARD).o strataflash.o ../common/misc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o ../common/misc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o ../common/misc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o ../common/misc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common/xilinx_jtag)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
-OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
+COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o
+COBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o strataflash.o ../common/misc.o
+COBJS = $(BOARD).o strataflash.o ../common/misc.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
-
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+# ifneq ($(OBJTREE),$(SRCTREE))
+# $(shell mkdir -p $(obj)../common/xilinx_jtag)
+# endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
# Objects for Xilinx JTAG programming (CPLD)
# CPLD = ../common/xilinx_jtag/lenval.o \
# ../common/xilinx_jtag/micro.o \
# ../common/xilinx_jtag/ports.o
-# OBJS = $(BOARD).o flash.o $(CPLD)
-OBJS = $(BOARD).o strataflash.o
+# COBJS = $(BOARD).o flash.o $(CPLD)
+COBJS = $(BOARD).o strataflash.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
# 0x00100000 boot from RAM (for testing only)
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot high
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
-#define GPIO_PSC1_4 0x01000000UL
-
void init_ide_reset(void)
{
debug("init_ide_reset\n");
debug("ide_reset(%d)\n", idereset);
if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
} else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
debug("init_ata_reset\n");
/* Configure GPIO_WU6 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
__asm__ volatile ("sync");
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../../Marvell/common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
SOBJS = misc.o
-OBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \
+COBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \
mv_eth.o mpsc.o i2c.o \
sdram_init.o ide.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o ../common/misc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
+COBJS = $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common/xilinx_jtag)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
-OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
+COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o ../common/misc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o ../common/misc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o cmd_ocrtc.o
+COBJS = $(BOARD).o flash.o ../common/misc.o cmd_ocrtc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o cmd_pci405.o
+COBJS = $(BOARD).o flash.o ../common/misc.o cmd_pci405.o
SOBJS = writeibm.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
-# $(AR) crv $@ $(OBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+# $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+# ifneq ($(OBJTREE),$(SRCTREE))
+# $(shell mkdir -p $(obj)../common/xilinx_jtag)
+# endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
# Objects for Xilinx JTAG programming (CPLD)
# CPLD = ../common/xilinx_jtag/lenval.o \
# ../common/xilinx_jtag/micro.o \
# ../common/xilinx_jtag/ports.o
-# OBJS = $(BOARD).o flash.o $(CPLD)
-OBJS = $(BOARD).o flash.o
+# COBJS = $(BOARD).o flash.o $(CPLD)
+COBJS = $(BOARD).o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
# 0x00100000 boot from RAM (for testing only)
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot high
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
-#define GPIO_PSC1_4 0x01000000UL
-
void init_ide_reset(void)
{
debug("init_ide_reset\n");
debug("ide_reset(%d)\n", idereset);
if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
} else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
debug("init_power_switch\n");
/* Configure GPIO_WU6 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
__asm__ volatile ("sync");
debug("ide_set_reset(%d)\n", power);
if (power) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
} else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
0) {
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common/xilinx_jtag)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
-OBJS = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
+COBJS = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o ../common/misc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common/xilinx_jtag)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
-OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
+COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o ../common/misc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o phantom.o
+COBJS = $(BOARD).o flash.o phantom.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o multiverse.o
+COBJS = $(BOARD).o multiverse.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := evb4510.o flash.o
+COBJS := evb4510.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
SOBJS = misc.o
-OBJS = $(BOARD).o flash.o serial.o memory.o pci.o \
+COBJS = $(BOARD).o flash.o serial.o memory.o pci.o \
eth.o eth_addrtbl.o mpsc.o i2c.o \
sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
# Copyright (c) 2005 blackfin.uclinux.org
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ezkit533.o
+COBJS = $(BOARD).o flash.o ezkit533.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o lamp.o pcmcia.o
+COBJS = $(BOARD).o flash.o lamp.o pcmcia.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o flash.o m88e6060.o
+COBJS := $(BOARD).o flash.o m88e6060.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o strataflash.o
+COBJS = $(BOARD).o strataflash.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# 2003 (c) MontaVista Software, Inc.
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := gcplus.o flash.o
+COBJS := gcplus.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o beeper.o fpga.o ioport.o
+COBJS = $(BOARD).o flash.o beeper.o fpga.o ioport.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
+COBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2005
+# (C) Copyright 2005-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ee_access.o
+COBJS = $(BOARD).o flash.o ee_access.o
SOBJS = lowlevel_init.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := gw8260.o flash.o
+COBJS := gw8260.o flash.o
SOBJS :=
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2005
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o bsp.o eeprom.o fetch.o input.o env.o
+COBJS = $(BOARD).o flash.o bsp.o eeprom.o fetch.o input.o env.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o flash.o
+COBJS := $(BOARD).o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
# 0x00100000 boot from RAM (for testing only)
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot high
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
-#define GPIO_PSC1_4 0x01000000UL
-
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
/* Deassert reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
void ide_set_reset (int idereset)
debug ("ide_reset(%d)\n", idereset);
if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
/* Make a delay. MPC5200 spec says 25 usec min */
udelay(500000);
} else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o pcmcia.o
+COBJS = $(BOARD).o flash.o pcmcia.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2005
# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
#
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o flash.o
-OBJS = $(BOARD).o flash.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := impa7.o flash.o
+COBJS := impa7.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = lowlevel_init.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o flash.o
+COBJS := $(BOARD).o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
-#define GPIO_WKUP_7 0x80000000UL
-#define GPIO_PSC3_9 0x04000000UL
-
int misc_init_f (void)
{
uchar tmp[10];
*(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
/* Set LR mirror bit because it is low-active */
- *(vu_long *)MPC5XXX_WU_GPIO_DATA |= GPIO_WKUP_7;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WKUP_7;
/*
* Reset Coral-P graphics controller
*/
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC3_9;
return 0;
}
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
-#define GPIO_PSC1_4 0x01000000UL
-
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
/* Deassert reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
void ide_set_reset (int idereset)
debug ("ide_reset(%d)\n", idereset);
if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
/* Make a delay. MPC5200 spec says 25 usec min */
udelay(500000);
} else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := innokom.o flash.o
+COBJS := innokom.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2004
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := integratorap.o flash.o
+COBJS := integratorap.o flash.o
SOBJS := lowlevel_init.o memsetup.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
TEXT_BASE = 0x01000000
+
+ifneq ($(OBJTREE),$(SRCTREE))
+# We are building u-boot in a separate directory, use generated
+# .lds script from OBJTREE directory.
+LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds
+endif
echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil
echo " /* CM may not have TCRAM */" >> tmp.fil
fi
-mv tmp.fil ./include/config.h
+
+mkdir -p ${obj}include
+mkdir -p ${obj}board/integratorap
+mv tmp.fil ${obj}include/config.h
# ---------------------------------------------------------
# Ensure correct core object loaded first in U-Boot image
# ---------------------------------------------------------
-sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorap/u-boot.lds.template > board/integratorap/u-boot.lds
+sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' ${src}board/integratorap/u-boot.lds.template > ${obj}board/integratorap/u-boot.lds
# ---------------------------------------------------------
# Complete the configuration
# ---------------------------------------------------------
-./mkconfig -a integratorap arm $cpu integratorap;
+$MKCONFIG -a integratorap arm $cpu integratorap;
echo "Variant:: $variant with core $cpu"
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := integratorcp.o flash.o
+COBJS := integratorcp.o flash.o
SOBJS := lowlevel_init.o memsetup.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
TEXT_BASE = 0x01000000
+
+ifneq ($(OBJTREE),$(SRCTREE))
+# We are building u-boot in a separate directory, use generated
+# .lds script from OBJTREE directory.
+LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds
+endif
echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil
echo " /* CM may not have TCRAM */" >> tmp.fil
fi
-mv tmp.fil ./include/config.h
+
+mkdir -p ${obj}include
+mkdir -p ${obj}board/integratorcp
+mv tmp.fil ${obj}include/config.h
# ---------------------------------------------------------
# Ensure correct core object loaded first in U-Boot image
# ---------------------------------------------------------
-sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorcp/u-boot.lds.template > board/integratorcp/u-boot.lds
+sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' ${src}board/integratorcp/u-boot.lds.template > ${obj}board/integratorcp/u-boot.lds
# ---------------------------------------------------------
# Complete the configuration
# ---------------------------------------------------------
-./mkconfig -a integratorcp arm $cpu integratorcp;
+$MKCONFIG -a integratorcp arm $cpu integratorcp;
echo "Variant:: $variant with core $cpu"
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o flash.o
-OBJS := $(BOARD).o flash.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# Copyright (C) 2004 Arabella Software Ltd.
# Yuli Barcohen <yuli@arabellasw.com>
#
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
-OBJS := $(BOARD).o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := ixdp425.o
+COBJS := ixdp425.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
TEXT_BASE = 0x00f80000
# include NPE ethernet driver
-BOARDLIBS = cpu/ixp/npe/libnpe.a
+BOARDLIBS = $(obj)cpu/ixp/npe/libnpe.a
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# Copyright 2004 Picture Elements, Inc.
# Stephen Williams <steve@icarus.com>
#
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o sdram.o flash.o host_bridge.o
+COBJS = $(BOARD).o sdram.o flash.o host_bridge.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := kb9202.o
+COBJS := kb9202.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o kup.o
+COBJS = $(BOARD).o flash.o kup.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
+COBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
+COBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := lart.o flash.o
+COBJS := lart.o flash.o
SOBJS := flashasm.o lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := logodl.o flash.o
+COBJS := logodl.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := lpd7a40x.o flash.o
+COBJS := lpd7a40x.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := lubbock.o flash.o
+COBJS := lubbock.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o pcmcia.o
+COBJS = $(BOARD).o flash.o pcmcia.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o
+COBJS = $(BOARD).o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o vpd.o pcmcia.o
+COBJS = $(BOARD).o flash.o vpd.o pcmcia.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o lcd.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
#
-# MCC200 board:
+# MCC200, PRS200 boards:
#
# Valid values for TEXT_BASE are:
#
# 0x00100000 boot from RAM (for testing only)
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot low
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <mpc5xxx.h>
+
+#ifdef CONFIG_LCD
+
+#define SWAPPED_LCD
+/*
+ * The name of the device used for communication
+ * with the PSoC.
+ */
+#define PSOC_PSC MPC5XXX_PSC2
+#define PSOC_BAUD 500000UL
+
+#define RTS_ASSERT 1
+#define RTS_NEGATE 0
+#define CTS_ASSERT 1
+#define CTS_NEGATE 0
+
+/*
+ * Dimensions in pixels
+ */
+#define LCD_WIDTH 160
+#define LCD_HEIGHT 100
+
+/*
+ * Dimensions in bytes
+ */
+#define LCD_BUF_SIZE ((LCD_WIDTH*LCD_HEIGHT)>>3)
+
+#if LCD_BPP != LCD_MONOCHROME
+#error "MCC200 support only monochrome displays (1 bpp)!"
+#endif
+
+#define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */
+#define PSOC_WAIT_TIME 10 /* usec */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * LCD information
+ */
+vidinfo_t panel_info = {
+ LCD_WIDTH, LCD_HEIGHT, LCD_BPP
+};
+
+int lcd_line_length;
+
+int lcd_color_fg;
+int lcd_color_bg;
+
+/*
+ * Frame buffer memory information
+ */
+void *lcd_base; /* Start of framebuffer memory */
+void *lcd_console_address; /* Start of console buffer */
+
+short console_col = 0;
+short console_row = 0;
+
+/*
+ * The device we use to communicate with PSoC
+ */
+int serial_inited = 0;
+
+/*
+ * Exported functions
+ */
+void lcd_initcolregs (void);
+void lcd_ctrl_init (void *lcdbase);
+void lcd_enable (void);
+
+/*
+ * Imported functions to support the PSoC protocol
+ */
+extern int serial_init_dev (unsigned long dev_base);
+extern void serial_setrts_dev (unsigned long dev_base, int s);
+extern int serial_getcts_dev (unsigned long dev_base);
+extern void serial_putc_raw_dev(unsigned long dev_base, const char c);
+
+/*
+ * Just stubs for our driver, needed for compiling compabilty with
+ * the common LCD driver code.
+ */
+void lcd_initcolregs (void)
+{
+}
+
+void lcd_ctrl_init (void *lcdbase)
+{
+}
+
+/*
+ * Function sends the contents of the frame-buffer to the LCD
+ */
+void lcd_enable (void)
+{
+ int i, retries, fb_size;
+
+ if (!serial_inited) {
+ unsigned long baud;
+
+ baud = gd->baudrate;
+ gd->baudrate = PSOC_BAUD;
+ serial_init_dev(PSOC_PSC);
+ gd->baudrate = baud;
+ serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
+ serial_inited = 1;
+ }
+
+ /*
+ * Implement PSoC communication protocol:
+ * 1. Assert RTS, wait CTS assertion
+ * 2. Transmit data
+ * 3. Negate RTS, wait CTS negation
+ */
+
+ /* 1 */
+ serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
+ for (retries = PSOC_RETRIES; retries; retries--) {
+ if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT)
+ break;
+ udelay (PSOC_WAIT_TIME);
+ }
+ if (!retries) {
+ printf ("%s Error: PSoC doesn't respond on "
+ "RTS ASSERT\n", __FUNCTION__);
+ }
+
+ /* 2 */
+ fb_size = panel_info.vl_row * (panel_info.vl_col >> 3);
+
+#if !defined(SWAPPED_LCD)
+ for (i=0; i<fb_size; i++) {
+ serial_putc_raw_dev (PSOC_PSC, ((char *)lcd_base)[i]);
+ }
+#else
+ {
+ int x, y, pwidth;
+ char *p = (char *)lcd_base;
+
+ pwidth = ((panel_info.vl_col+7) >> 3);
+ for (y=0; y<panel_info.vl_row; y++) {
+ i = y * pwidth;
+ for (x=0; x<pwidth; x+=5) {
+ serial_putc_raw_dev (PSOC_PSC, (p[i+x+2]<<4 & 0xF0) | (p[i+x+3]>>4 & 0x0F));
+ serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F));
+ serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F));
+ serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F));
+ serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F));
+ }
+ }
+ }
+#endif
+
+ /* 3 */
+ serial_setrts_dev (PSOC_PSC, RTS_NEGATE);
+ for (retries = PSOC_RETRIES; retries; retries--) {
+ if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE)
+ break;
+ udelay (PSOC_WAIT_TIME);
+ }
+ if (!retries) {
+ printf ("%s Error: PSoC doesn't respond on "
+ "RTS NEGATE\n", __FUNCTION__);
+ }
+
+ return;
+}
+#endif /* CONFIG_LCD */
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
+#include <asm/processor.h>
/* Two MT48LC8M32B2 for 32 MB */
/* #include "mt48lc8m32b2-6-7.h" */
{
ulong dramsize = 0;
ulong dramsize2 = 0;
+ uint svr, pvr;
#ifndef CFG_RAMBOOT
ulong test1, test2;
#endif /* CFG_RAMBOOT */
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
return dramsize + dramsize2;
}
int checkboard (void)
{
+#if defined(CONFIG_PRS200)
+ puts ("Board: PRS200\n");
+#else
puts ("Board: MCC200\n");
+#endif
return 0;
}
int misc_init_r (void)
{
+ ulong flash_sup_end, snum;
+
/*
* Adjust flash start and offset to detected values
*/
(flash_info[0].start[0] - 1) + flash_info[0].size,
&flash_info[0]);
*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
+ printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
+ flash_info[0].size = 32 << 20;
+ for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
+ flash_info[0].start[snum] < flash_sup_end;
+ snum++);
+ flash_info[0].sector_count = snum;
}
return (0);
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o serial.o
+COBJS = $(BOARD).o flash.o serial.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := modnet50.o flash.o
+COBJS := modnet50.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o m48t59y.o pci.o flash.o
+COBJS = $(BOARD).o m48t59y.o pci.o flash.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := mp2usb.o flash.o
+COBJS := mp2usb.o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o flash.o
+COBJS := $(BOARD).o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
# MPC8260ADS, MPC8266ADS, and PQ2FADS-ZU/VR boards
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot high
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o flash.o
+COBJS := $(BOARD).o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o
SOBJS := init.o
#SOBJS :=
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#include <asm/immap_85xx.h>
#include <spd.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
* Initialize PCI Devices, report devices found.
*/
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc85xxads_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- } },
- { }
-};
-#endif
-
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_mpc85xxads_config_table,
-#endif
-};
+static struct pci_controller hose;
#endif /* CONFIG_PCI */
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
+
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+}
+#endif
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o flash.o
-#OBJS := $(BOARD).o flash.o $(BOARD)_slave.o
+COBJS := $(BOARD).o flash.o
+#COBJS := $(BOARD).o flash.o $(BOARD)_slave.o
SOBJS := init.o
#SOBJS :=
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o
SOBJS := init.o
#SOBJS :=
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#include <spd.h>
#include <miiphy.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
+
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+}
+#endif
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/i2c.o (.text)
cpu/mpc85xx/spd_sdram.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o pixis.o sys_eeprom.o
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+.PHONY: distclean
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude ($obj).depend
+
+#########################################################################
--- /dev/null
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Jeff Brown
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8641hpcn board
+# default CCSRBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff01000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc86xx.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xf800_0000 0xf80f_ffff CCSRBAR 1M
+ * 0xf810_0000 0xf81f_ffff PIXIS 1M
+ * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
+ *
+ * Notes:
+ * CCSRBAR don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#else
+#define LAWBAR1 0
+#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
+#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR4 ((0xf8100000>>12) & 0xffffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
+
+#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
+#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
+
+#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
+#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#else
+#define LAWBAR8 0
+#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ lis r7,CFG_CCSRBAR@h
+ ori r7,r7,CFG_CCSRBAR@l
+
+ addi r4,r7,0
+ addi r5,r7,0
+
+ /* Skip LAWAR0, start at LAWAR1 */
+ lis r6,LAWBAR1@h
+ ori r6,r6,LAWBAR1@l
+ stwu r6, 0xc28(r4)
+
+ lis r6,LAWAR1@h
+ ori r6,r6,LAWAR1@l
+ stwu r6, 0xc30(r5)
+
+ /* LAWBAR2, LAWAR2 */
+ lis r6,LAWBAR2@h
+ ori r6,r6,LAWBAR2@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR2@h
+ ori r6,r6,LAWAR2@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR3, LAWAR3 */
+ lis r6,LAWBAR3@h
+ ori r6,r6,LAWBAR3@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR3@h
+ ori r6,r6,LAWAR3@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR4, LAWAR4 */
+ lis r6,LAWBAR4@h
+ ori r6,r6,LAWBAR4@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR4@h
+ ori r6,r6,LAWAR4@l
+ stwu r6, 0x20(r5)
+ /* LAWBAR5, LAWAR5 */
+ lis r6,LAWBAR5@h
+ ori r6,r6,LAWBAR5@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR5@h
+ ori r6,r6,LAWAR5@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR6, LAWAR6 */
+ lis r6,LAWBAR6@h
+ ori r6,r6,LAWBAR6@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR6@h
+ ori r6,r6,LAWAR6@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR7, LAWAR7 */
+ lis r6,LAWBAR7@h
+ ori r6,r6,LAWBAR7@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR7@h
+ ori r6,r6,LAWAR7@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR8, LAWAR8 */
+ lis r6,LAWBAR8@h
+ ori r6,r6,LAWBAR8@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR8@h
+ ori r6,r6,LAWAR8@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR9, LAWAR9 */
+ lis r6,LAWBAR9@h
+ ori r6,r6,LAWBAR9@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR9@h
+ ori r6,r6,LAWAR9@l
+ stwu r6, 0x20(r5)
+
+ blr
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <spd.h>
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+#endif
+
+#include "pixis.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+#include "spd_sdram.h"
+#endif
+
+void sdram_init(void);
+long int fixed_sdram(void);
+
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MPC8641HPCN\n");
+
+#ifdef CONFIG_PCI
+
+ volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_pex_t *pex1 = &immap->im_pex1;
+
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+ uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+ uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
+
+ if ((io_sel == 2 || io_sel == 3 || io_sel == 5
+ || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
+ && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+ debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
+ debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
+ if (pex1->pme_msg_det) {
+ pex1->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pex1->pme_msg_det);
+ }
+ debug("\n");
+ } else {
+ puts("PCI-EXPRESS 1: Disabled\n");
+ }
+
+#else
+ puts("PCI-EXPRESS1: Disabled\n");
+#endif
+
+ return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+
+#if defined(CFG_RAMBOOT)
+ puts(" DDR: ");
+ return dram_size;
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ puts("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+long int
+fixed_sdram(void)
+{
+#if !defined(CFG_RAMBOOT)
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
+ ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode_1 = CFG_DDR_MODE_1;
+ ddr->sdram_mode_2 = CFG_DDR_MODE_2;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ ddr->sdram_data_init = CFG_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
+ ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
+ ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
+
+#if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000008D;
+ ddr->err_sbe = 0x00ff0000;
+#endif
+ asm("sync;isync");
+
+ udelay(500);
+
+#if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
+#else
+ ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
+ ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
+#endif
+ asm("sync; isync");
+
+ udelay(500);
+#endif
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_fsl86xxads_config_table[] = {
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
+ {}
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc86xxcts_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+void pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ extern void pci_mpc86xx_init(struct pci_controller *hose);
+
+ pci_mpc86xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+}
+#endif
+
+
+void
+mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ char cmd;
+ ulong val;
+ ulong corepll;
+
+ /*
+ * No args is a simple reset request.
+ */
+ if (argc <= 1) {
+ out8(PIXIS_BASE + PIXIS_RST, 0);
+ /* not reached */
+ }
+
+ cmd = argv[1][1];
+ switch (cmd) {
+ case 'f': /* reset with frequency changed */
+ if (argc < 5)
+ goto my_usage;
+ read_from_px_regs(0);
+
+ val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
+
+ corepll = strfractoint(argv[3]);
+ val = val + set_px_corepll(corepll);
+ val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
+ if (val == 3) {
+ puts("Setting registers VCFGEN0 and VCTL\n");
+ read_from_px_regs(1);
+ puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
+ set_px_go();
+ } else
+ goto my_usage;
+
+ while (1) ; /* Not reached */
+
+ case 'l':
+ if (argv[2][1] == 'f') {
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ /* reset with frequency changed */
+ val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
+
+ corepll = strfractoint(argv[4]);
+ val = val + set_px_corepll(corepll);
+ val = val + set_px_mpxpll(simple_strtoul(argv[5],
+ NULL, 10));
+ if (val == 3) {
+ puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs(1);
+ read_from_px_regs_altbank(1);
+ puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
+ set_px_go_with_watchdog();
+ } else
+ goto my_usage;
+
+ while (1) ; /* Not reached */
+
+ } else if (argv[2][1] == 'd') {
+ /*
+ * Reset from alternate bank without changing
+ * frequencies but with watchdog timer enabled.
+ */
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs_altbank(1);
+ puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
+ set_px_go_with_watchdog();
+ while (1) ; /* Not reached */
+
+ } else {
+ /*
+ * Reset from next bank without changing
+ * frequency and without watchdog timer enabled.
+ */
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ if (argc > 2)
+ goto my_usage;
+ puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs_altbank(1);
+ puts("Resetting board to boot from the other bank....\n");
+ set_px_go();
+ }
+
+ default:
+ goto my_usage;
+ }
+
+my_usage:
+ puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
+ puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
+ puts(" reset altbank [wd]\n");
+ puts("For example: reset cf 40 2.5 10\n");
+ puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
+}
+
+
+/*
+ * get_board_sys_clk
+ * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+ u8 i, go_bit, rd_clks;
+ ulong val = 0;
+
+ go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+ go_bit &= 0x01;
+
+ rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+ rd_clks &= 0x1C;
+
+ /*
+ * Only if both go bit and the SCLK bit in VCFGEN0 are set
+ * should we be using the AUX register. Remember, we also set the
+ * GO bit to boot from the alternate bank on the on-board flash
+ */
+
+ if (go_bit) {
+ if (rd_clks == 0x1c)
+ i = in8(PIXIS_BASE + PIXIS_AUX);
+ else
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ } else {
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ }
+
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33000000;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66000000;
+ break;
+ case 4:
+ val = 83000000;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 134000000;
+ break;
+ case 7:
+ val = 166000000;
+ break;
+ }
+
+ return val;
+}
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/cache.h>
+#include <mpc86xx.h>
+
+#include "pixis.h"
+
+
+/*
+ * Per table 27, page 58 of MPC8641HPCN spec.
+ */
+int set_px_sysclk(ulong sysclk)
+{
+ u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
+
+ switch (sysclk) {
+ case 33:
+ sysclk_s = 0x04;
+ sysclk_r = 0x04;
+ sysclk_v = 0x07;
+ sysclk_aux = 0x00;
+ break;
+ case 40:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x20;
+ sysclk_aux = 0x01;
+ break;
+ case 50:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x2A;
+ sysclk_aux = 0x02;
+ break;
+ case 66:
+ sysclk_s = 0x01;
+ sysclk_r = 0x04;
+ sysclk_v = 0x04;
+ sysclk_aux = 0x03;
+ break;
+ case 83:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x4B;
+ sysclk_aux = 0x04;
+ break;
+ case 100:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x5C;
+ sysclk_aux = 0x05;
+ break;
+ case 134:
+ sysclk_s = 0x06;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x3B;
+ sysclk_aux = 0x06;
+ break;
+ case 166:
+ sysclk_s = 0x06;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x4B;
+ sysclk_aux = 0x07;
+ break;
+ default:
+ printf("Unsupported SYSCLK frequency.\n");
+ return 0;
+ }
+
+ vclkh = (sysclk_s << 5) | sysclk_r;
+ vclkl = sysclk_v;
+
+ out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
+ out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
+
+ out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
+
+ return 1;
+}
+
+
+int set_px_mpxpll(ulong mpxpll)
+{
+ u8 tmp;
+ u8 val;
+
+ switch (mpxpll) {
+ case 2:
+ case 4:
+ case 6:
+ case 8:
+ case 10:
+ case 12:
+ case 14:
+ case 16:
+ val = (u8) mpxpll;
+ break;
+ default:
+ printf("Unsupported MPXPLL ratio.\n");
+ return 0;
+ }
+
+ tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
+ tmp = (tmp & 0xF0) | (val & 0x0F);
+ out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
+
+ return 1;
+}
+
+
+int set_px_corepll(ulong corepll)
+{
+ u8 tmp;
+ u8 val;
+
+ switch ((int)corepll) {
+ case 20:
+ val = 0x08;
+ break;
+ case 25:
+ val = 0x0C;
+ break;
+ case 30:
+ val = 0x10;
+ break;
+ case 35:
+ val = 0x1C;
+ break;
+ case 40:
+ val = 0x14;
+ break;
+ case 45:
+ val = 0x0E;
+ break;
+ default:
+ printf("Unsupported COREPLL ratio.\n");
+ return 0;
+ }
+
+ tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
+ tmp = (tmp & 0xE0) | (val & 0x1F);
+ out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
+
+ return 1;
+}
+
+
+void read_from_px_regs(int set)
+{
+ u8 mask = 0x1C;
+ u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+
+ if (set)
+ tmp = tmp | mask;
+ else
+ tmp = tmp & ~mask;
+ out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
+}
+
+
+void read_from_px_regs_altbank(int set)
+{
+ u8 mask = 0x04;
+ u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
+
+ if (set)
+ tmp = tmp | mask;
+ else
+ tmp = tmp & ~mask;
+ out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
+}
+
+
+void set_altbank(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
+ tmp ^= 0x40;
+
+ out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
+}
+
+
+void set_px_go(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp | 0x01;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+void set_px_go_with_watchdog(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp | 0x09;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ /* setting VCTL[WDEN] to 0 to disable watch dog */
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp &= ~0x08;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ diswd, 1, 0, disable_watchdog,
+ "diswd - Disable watchdog timer \n",
+ NULL);
+
+/*
+ * This function takes the non-integral cpu:mpx pll ratio
+ * and converts it to an integer that can be used to assign
+ * FPGA register values.
+ * input: strptr i.e. argv[2]
+ */
+
+ulong strfractoint(uchar *strptr)
+{
+ int i, j, retval;
+ int mulconst;
+ int intarr_len = 0, decarr_len = 0, no_dec = 0;
+ ulong intval = 0, decval = 0;
+ uchar intarr[3], decarr[3];
+
+ /* Assign the integer part to intarr[]
+ * If there is no decimal point i.e.
+ * if the ratio is an integral value
+ * simply create the intarr.
+ */
+ i = 0;
+ while (strptr[i] != 46) {
+ if (strptr[i] == 0) {
+ no_dec = 1;
+ break;
+ }
+ intarr[i] = strptr[i];
+ i++;
+ }
+
+ /* Assign length of integer part to intarr_len. */
+ intarr_len = i;
+ intarr[i] = '\0';
+
+ if (no_dec) {
+ /* Currently needed only for single digit corepll ratios */
+ mulconst = 10;
+ decval = 0;
+ } else {
+ j = 0;
+ i++; /* Skipping the decimal point */
+ while ((strptr[i] > 47) && (strptr[i] < 58)) {
+ decarr[j] = strptr[i];
+ i++;
+ j++;
+ }
+
+ decarr_len = j;
+ decarr[j] = '\0';
+
+ mulconst = 1;
+ for (i = 0; i < decarr_len; i++)
+ mulconst *= 10;
+ decval = simple_strtoul(decarr, NULL, 10);
+ }
+
+ intval = simple_strtoul(intarr, NULL, 10);
+ intval = intval * mulconst;
+
+ retval = intval + decval;
+
+ return retval;
+}
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+extern int set_px_sysclk(ulong sysclk);
+extern int set_px_mpxpll(ulong mpxpll);
+extern int set_px_corepll(ulong corepll);
+extern void read_from_px_regs(int set);
+extern void read_from_px_regs_altbank(int set);
+extern void set_altbank(void);
+extern void set_px_go(void);
+extern void set_px_go_with_watchdog(void);
+extern int disable_watchdog(cmd_tbl_t *cmdtp,
+ int flag, int argc, char *argv[]);
+extern ulong strfractoint(uchar *strptr);
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ * Haiying Wang (haiying.wang@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#ifdef CFG_ID_EEPROM
+typedef struct {
+ unsigned char id[4]; /* 0x0000 - 0x0003 */
+ unsigned char sn[12]; /* 0x0004 - 0x000F */
+ unsigned char errata[5]; /* 0x0010 - 0x0014 */
+ unsigned char date[7]; /* 0x0015 - 0x001a */
+ unsigned char res_1[37]; /* 0x001b - 0x003f */
+ unsigned char tab_size; /* 0x0040 */
+ unsigned char tab_flag; /* 0x0041 */
+ unsigned char mac[8][6]; /* 0x0042 - 0x0071 */
+ unsigned char res_2[126]; /* 0x0072 - 0x00ef */
+ unsigned int crc; /* 0x00f0 - 0x00f3 crc32 checksum */
+} EEPROM_data;
+
+static EEPROM_data mac_data;
+
+int mac_show(void)
+{
+ int i;
+ unsigned char ethaddr[8][18];
+
+ printf("ID %c%c%c%c\n",
+ mac_data.id[0],
+ mac_data.id[1],
+ mac_data.id[2],
+ mac_data.id[3]);
+ printf("Errata %c%c%c%c%c\n",
+ mac_data.errata[0],
+ mac_data.errata[1],
+ mac_data.errata[2],
+ mac_data.errata[3],
+ mac_data.errata[4]);
+ printf("Date %c%c%c%c%c%c%c\n",
+ mac_data.date[0],
+ mac_data.date[1],
+ mac_data.date[2],
+ mac_data.date[3],
+ mac_data.date[4],
+ mac_data.date[5],
+ mac_data.date[6]);
+ for (i = 0; i < 8; i++) {
+ sprintf(ethaddr[i],
+ "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac_data.mac[i][0],
+ mac_data.mac[i][1],
+ mac_data.mac[i][2],
+ mac_data.mac[i][3],
+ mac_data.mac[i][4],
+ mac_data.mac[i][5]);
+ printf("MAC %d %s\n", i, ethaddr[i]);
+ }
+
+ setenv("ethaddr", ethaddr[0]);
+ setenv("eth1addr", ethaddr[1]);
+ setenv("eth2addr", ethaddr[2]);
+ setenv("eth3addr", ethaddr[3]);
+
+ return 0;
+}
+
+int mac_read(void)
+{
+ int ret, length;
+ unsigned int crc = 0;
+ unsigned char dev = ID_EEPROM_ADDR, *data;
+
+ length = sizeof(EEPROM_data);
+ ret = i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length);
+ if (ret) {
+ printf("Read failed.\n");
+ return -1;
+ }
+
+ data = (unsigned char *)(&mac_data);
+ printf("Check CRC on reading ...");
+ crc = crc32(crc, data, length - 4);
+ if (crc != mac_data.crc) {
+ printf("CRC checksum is invalid, in EEPROM CRC is %x, calculated CRC is %x\n",
+ mac_data.crc, crc);
+ return -1;
+ } else {
+ printf("CRC OK\n");
+ mac_show();
+ }
+ return 0;
+}
+
+int mac_prog(void)
+{
+ int ret, i, length;
+ unsigned int crc = 0;
+ unsigned char dev = ID_EEPROM_ADDR, *ptr;
+ unsigned char *eeprom_data = (unsigned char *)(&mac_data);
+
+ for (i = 0; i < sizeof(mac_data.res_1); i++)
+ mac_data.res_1[i] = 0;
+ for (i = 0; i < sizeof(mac_data.res_2); i++)
+ mac_data.res_2[i] = 0;
+ length = sizeof(EEPROM_data);
+ crc = crc32(crc, eeprom_data, length - 4);
+ mac_data.crc = crc;
+ for (i = 0, ptr = eeprom_data; i < length; i += 8, ptr += 8) {
+ ret =
+ i2c_write(dev, i, 1, ptr,
+ (length - i) < 8 ? (length - i) : 8);
+ udelay(5000); /* 5ms write cycle timing */
+ if (ret)
+ break;
+ }
+ if (ret) {
+ printf("Programming failed.\n");
+ return -1;
+ } else {
+ printf("Programming %d bytes. Reading back ...\n", length);
+ mac_read();
+ }
+ return 0;
+}
+
+int do_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ int i;
+ char cmd = 's';
+ unsigned long long mac_val;
+
+ if (i2c_probe(ID_EEPROM_ADDR) != 0)
+ return -1;
+
+ if (argc > 1) {
+ cmd = argv[1][0];
+ switch (cmd) {
+ case 'r': /* display */
+ mac_read();
+ break;
+ case 's': /* save */
+ mac_prog();
+ break;
+ case 'i': /* id */
+ for (i = 0; i < 4; i++) {
+ mac_data.id[i] = argv[2][i];
+ }
+ break;
+ case 'n': /* serial number */
+ for (i = 0; i < 12; i++) {
+ mac_data.sn[i] = argv[2][i];
+ }
+ break;
+ case 'e': /* errata */
+ for (i = 0; i < 5; i++) {
+ mac_data.errata[i] = argv[2][i];
+ }
+ break;
+ case 'd': /* date */
+ for (i = 0; i < 7; i++) {
+ mac_data.date[i] = argv[2][i];
+ }
+ break;
+ case 'p': /* number of ports */
+ mac_data.tab_size =
+ (unsigned char)simple_strtoul(argv[2], NULL, 16);
+ break;
+ case '0': /* mac 0 */
+ case '1': /* mac 1 */
+ case '2': /* mac 2 */
+ case '3': /* mac 3 */
+ case '4': /* mac 4 */
+ case '5': /* mac 5 */
+ case '6': /* mac 6 */
+ case '7': /* mac 7 */
+ mac_val = simple_strtoull(argv[2], NULL, 16);
+ for (i = 0; i < 6; i++) {
+ mac_data.mac[cmd - '0'][i] =
+ *((unsigned char *)
+ (((unsigned int)(&mac_val)) + i + 2));
+ }
+ break;
+ case 'h': /* help */
+ default:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ break;
+ }
+ } else {
+ mac_show();
+ }
+ return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+ int length, i;
+ unsigned char dev = ID_EEPROM_ADDR;
+ unsigned char *data;
+ unsigned char ethaddr[4][18];
+ unsigned char enetvar[32];
+ unsigned int crc = 0;
+
+ length = sizeof(EEPROM_data);
+ if (i2c_read(dev, 0, 1, (unsigned char *)(&mac_data), length)) {
+ printf("Read failed.\n");
+ return -1;
+ }
+
+ data = (unsigned char *)(&mac_data);
+ crc = crc32(crc, data, length - 4);
+ if (crc != mac_data.crc) {
+ return -1;
+ } else {
+ for (i = 0; i < 4; i++) {
+ if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) {
+ sprintf(ethaddr[i],
+ "%02x:%02x:%02x:%02x:%02x:%02x",
+ mac_data.mac[i][0],
+ mac_data.mac[i][1],
+ mac_data.mac[i][2],
+ mac_data.mac[i][3],
+ mac_data.mac[i][4],
+ mac_data.mac[i][5]);
+ sprintf(enetvar,
+ i ? "eth%daddr" : "ethaddr",
+ i);
+ setenv(enetvar, ethaddr[i]);
+ }
+ }
+ }
+ return 0;
+}
+#endif /* CFG_ID_EEPROM */
--- /dev/null
+/*
+ * (C) Copyright 2004, Freescale, Inc.
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Jeff Brown
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFF00100 :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFF70000 :
+ {
+ cpu/mpc86xx/start.o (.bootpg)
+ board/mpc8641hpcn/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + 1024;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc86xx/start.o (.text)
+ board/mpc8641hpcn/init.o (.text)
+ cpu/mpc86xx/traps.o (.text)
+ cpu/mpc86xx/interrupts.o (.text)
+ cpu/mpc86xx/cpu_init.o (.text)
+ cpu/mpc86xx/cpu.o (.text)
+ cpu/mpc86xx/speed.o (.text)
+ cpu/mpc86xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
#
-# (C) Copyright 2000, 2001
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \
+COBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \
../common/usb_uhci.o ../common/memtst.o ../common/common_util.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de
-#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de
#
# See file CREDITS for list of people who contributed to this
# project.
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o
+COBJS := pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o
#### cmd_pati.o
-SOBJS :=
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o \
+COBJS = $(BOARD).o \
../common/flash.o cmd_pip405.o ../common/pci.o \
../common/isa.o ../common/kbd.o \
../common/usb_uhci.o \
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := vcma9.o flash.o cmd_vcma9.o
-OBJS += ../common/common_util.o ../common/memtst.o
+COBJS := vcma9.o flash.o cmd_vcma9.o
+COBJS += ../common/common_util.o ../common/memtst.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
-SOBJS =
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
-SOBJS =
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
# board/mx1ads/Makefile
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (c) Copyright 2004
# Techware Information Technology, Inc.
# http://www.techware.com.tw/
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := mx1ads.o syncflash.o
+COBJS := mx1ads.o syncflash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := mx1fs2.o flash.o
+COBJS := mx1fs2.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
-# (C) Copyright 2004
+# (C) Copyright 2004-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o nand.o flash.o
+COBJS = $(BOARD).o nand.o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
TEXT_BASE = 0x40700000
-BOARDLIBS = drivers/nand/libnand.a
+BOARDLIBS = $(obj)drivers/nand/libnand.a
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o phone_console.o
+COBJS = $(BOARD).o flash.o phone_console.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2005
# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
#
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := netstar.o flash.o nand.o
+COBJS := netstar.o flash.o nand.o
SOBJS := setup.o crcek.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c \
+ eeprom_start.S
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
LOAD_ADDR = 0x10400000
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
+lnk = $(if $(obj),$(obj),.)
HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include
-all: $(LIB) eeprom.srec eeprom.bin crcek.srec crcek.bin crcit
+all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \
+ $(obj)crcek.srec $(obj)crcek.bin $(obj)crcit
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) $(ARFLAGS) $@ $^
-eeprom.srec: eeprom.o eeprom_start.o
- $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
- -o $(<:.o=) -e $(<:.o=) $^ \
- -L../../examples -lstubs \
- -L../../lib_generic -lgeneric \
+$(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o
+ cd $(lnk) && $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
+ -o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \
+ -L$(obj)../../examples -lstubs \
+ -L$(obj)../../lib_generic -lgeneric \
-L$(gcclibdir) -lgcc
$(OBJCOPY) -O srec $(<:.o=) $@
-eeprom.bin: eeprom.srec
+$(obj)eeprom.bin: $(obj)eeprom.srec
$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
-crcek.srec: crcek.o
+$(obj)crcek.srec: $(obj)crcek.o
$(LD) -g -Ttext 0x00000000 \
- -o $(<:.o=) -e $(<:.o=) $^
+ -o $(<:.o=) -e crcek $^
$(OBJCOPY) -O srec $(<:.o=) $@
-crcek.bin: crcek.srec
+$(obj)crcek.bin: $(obj)crcek.srec
$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
-crcit: crcit.o crc32.o
+$(obj)crcit: $(obj)crcit.o $(obj)crc32.o
$(HOSTCC) $(HOST_CFLAGS) -o $@ $^
-crcit.o: crcit.c
- $(HOSTCC) $(HOST_CFLAGS) -c $<
+$(obj)crcit.o: crcit.c
+ $(HOSTCC) $(HOST_CFLAGS) -o $@ -c $<
-crc32.o: $(TOPDIR)/tools/crc32.c
- $(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -c $<
+$(obj)crc32.o: $(OBJTREE)/tools/crc32.c
+ $(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -o $@ -c $<
clean:
- rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin \
- crcek crcek.srec crcek.bin
+ rm -f $(SOBJS) $(OBJS) $(obj)eeprom $(obj)eeprom.srec \
+ $(obj)eeprom.bin $(obj)crcek $(obj)crcek.srec \
+ $(obj)crcek.bin
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
int board_init(void)
{
/* arch number of NetStar board */
- gd->bd->bi_arch_number = 692;
+ gd->bd->bi_arch_number = MACH_TYPE_NETSTAR;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x10000100;
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o dsp.o codec.o pcmcia.o
+COBJS = $(BOARD).o flash.o dsp.o codec.o pcmcia.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := ns9750dev.o flash.o led.o
+COBJS := ns9750dev.o flash.o led.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2005
+# (C) Copyright 2005-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o flash.o
+COBJS := $(BOARD).o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := omap1510innovator.o
+COBJS := omap1510innovator.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := omap1610innovator.o flash.o
+COBJS := omap1610innovator.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := omap2420h4.o mem.o sys_info.o
+COBJS := omap2420h4.o mem.o sys_info.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := omap5912osk.o
+COBJS := omap5912osk.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := omap730p2.o flash.o
+COBJS := omap730p2.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = memsetup.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o \
fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o
-AOBJS =
+SOBJS =
-OBJS = $(COBJS) $(AOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := pleb2.o flash.o
+COBJS := pleb2.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o flash.o
+COBJS := $(BOARD).o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot 64-bit flash
#
-# (C) Copyright 2001-2004
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot 64-bit flash
#
-# (C) Copyright 2001-2005
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o
SOBJS := init.o
#SOBJS :=
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o
SOBJS := init.o
#SOBJS :=
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o cmd_pn62.o misc.o
+COBJS = $(BOARD).o cmd_pn62.o misc.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := ppmc7xx.o pci.o flash.o
SOBJS := init.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+COBJS := ppmc7xx.o pci.o flash.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := ppmc8260.o
+COBJS := ppmc8260.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o
+COBJS = $(BOARD).o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := flash.o pdnb3.o nand.o
+COBJS := flash.o pdnb3.o nand.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
TEXT_BASE = 0x01f00000
# include NPE ethernet driver
-BOARDLIBS = cpu/ixp/npe/libnpe.a
+BOARDLIBS = $(obj)cpu/ixp/npe/libnpe.a
#
-# (C) Copyright 2001-2004
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
COMOBJS := ../common/AMDLV065D.o
-OBJS := $(BOARD).o $(COMOBJS)
+COBJS := $(BOARD).o $(COMOBJS)
-SOBJS =
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001-2004
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
COMOBJS := ../common/AMDLV065D.o
-OBJS := $(BOARD).o led.o $(COMOBJS)
+COBJS := $(BOARD).o led.o $(COMOBJS)
-SOBJS =
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o sconsole.o
+COBJS = $(BOARD).o flash.o sconsole.o
SOBJS = lowlevel_init.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2005
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := pxa_idp.o
+COBJS := pxa_idp.o
SOBJS := memsetup.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o fpga.o
+COBJS = $(BOARD).o fpga.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o pcmcia.o
+COBJS = $(BOARD).o flash.o pcmcia.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o
+COBJS = $(BOARD).o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001-2005
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o kbd.o
+COBJS = $(BOARD).o flash.o kbd.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := rpxsuper.o flash.o mii_phy.o
+COBJS := rpxsuper.o flash.o mii_phy.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := rsdproto.o flash.o
+COBJS := rsdproto.o flash.o
SOBJS := flash_asm.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
- rm -f $(LIB) core *.bak .depend
+ rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := sacsng.o flash.o clkinit.o
+COBJS := sacsng.o flash.o clkinit.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2005
# Sandburst Corporation
# Travis B. Sawyer
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
# TBS: add for debugging purposes
BUILDUSER := $(shell whoami)
# TBS: end debugging
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
+COBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
../common/sb_common.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2005
# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
#
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
# TBS: add for debugging purposes
BUILDUSER := $(shell whoami)
# TBS: end debugging
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
+COBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
../common/sb_common.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := sbc2410x.o flash.o
+COBJS := sbc2410x.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o strataflash.o
+COBJS = $(BOARD).o strataflash.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := sbc8260.o flash.o
+COBJS := sbc8260.o flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2004
+# (C) Copyright 2004-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o
SOBJS := init.o
#SOBJS :=
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/i2c.o (.text)
cpu/mpc85xx/spd_sdram.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
#
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := sc520_cdp.o flash.o
+COBJS := sc520_cdp.o flash.o
SOBJS := sc520_cdp_asm.o sc520_cdp_asm16.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
#
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := sc520_spunk.o flash.o
+COBJS := sc520_spunk.o flash.o
SOBJS := sc520_spunk_asm.o sc520_spunk_asm16.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := scb9328.o flash.o
+COBJS := scb9328.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := shannon.o flash.o
+COBJS := shannon.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+$(shell mkdir -p $(obj)../../tqm8xx)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \
+COBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \
../../tqm8xx/load_sernum_ethaddr.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o atm.o
+COBJS = $(BOARD).o flash.o atm.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+$(shell mkdir -p $(obj)../../tqm8xx/)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \
+COBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \
../../tqm8xx/load_sernum_ethaddr.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001 - 2003
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := smdk2400.o flash.o
+COBJS := smdk2400.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := smdk2410.o flash.o
+COBJS := smdk2410.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
-# (C) Copyright 2005
+#
+# (C) Copyright 2005-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
-OBJS := $(BOARD).o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
size = dramSetup ();
- return get_ram_size((ulong *)CFG_SDRAM_BASE, size);
+ return get_ram_size(CFG_SDRAM_BASE, size);
}
int checkboard (void)
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o
+COBJS = $(BOARD).o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001-2004
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o flash.o misc.o
+COBJS := $(BOARD).o flash.o misc.o
+SOBJS := vectors.o
-SOBJS = vectors.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
# Copyright (c) 2005 blackfin.uclinux.org
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o stamp.o
-SOBJS =
+COBJS = $(BOARD).o stamp.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o flash.o
+COBJS := $(BOARD).o flash.o
SOBJS := init.o
#SOBJS :=
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
pci_init_board(void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init(struct pci_controller *hose);
-
pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/i2c.o (.text)
cpu/mpc85xx/spd_sdram.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o oftree.o
+COBJS = $(BOARD).o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-%.dtb: %.dts
- dtc -f -V 0x10 -I dts -O dtb $< >$@
-
-%.c: %.dtb
- xxd -i $< \
- | sed -e "s/^unsigned char/const unsigned char/g" \
- | sed -e "s/^unsigned int/const unsigned int/g" > $@
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
+++ /dev/null
-/ {
- model = "STXXTC V1";
- compatible = "STXXTC";
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- linux,phandle = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- PowerPC,MPC870@0 {
- linux,phandle = <3>;
- name = "PowerPC,MPC870";
- device_type = "cpu";
- reg = <0>;
- clock-frequency = <0>; /* place-holder for runtime fillup */
- timebase-frequency = <0>; /* dido */
- linux,boot-cpu;
- i-cache-size = <2000>;
- d-cache-size = <2000>;
- 32-bit;
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <00000000 00000000 00000000 20000000>;
- };
-
- /* copy of the bd_t information (place-holders) */
- bd_t {
- memstart = <0>;
- memsize = <0>;
- flashstart = <0>;
- flashsize = <0>;
- flashoffset = <0>;
- sramstart = <0>;
- sramsize = <0>;
-
- immr_base = <0>;
-
- bootflags = <0>;
- ip_addr = <0>;
- enetaddr = [ 00 00 00 00 00 00 ];
- ethspeed = <0>;
- intfreq = <0>;
- busfreq = <0>;
-
- baudrate = <0>;
- };
-
-};
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2004
+# (C) Copyright 2004-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := sx1.o
+COBJS := sx1.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
# (C) Masami Komiya <mkomiya@sonare.it> 2004
#
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o vr4131-pci.o
+COBJS = $(BOARD).o flash.o vr4131-pci.o
SOBJS = lowlevel_init.o
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o sdram.o
+COBJS := $(BOARD).o sdram.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
# 0x00100000 boot from RAM (for testing only)
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot high
#
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o cmd_stk52xx.o cmd_tb5200.o
+COBJS := $(BOARD).o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
+cam5200_flash.o: cam5200_flash.c
+ $(CC) $(CFLAGS) -fno-strict-aliasing -c -o $@ $<
+
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+
+#ifdef CONFIG_CAM5200
+
+#if 0
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif
+
+#define swap16(x) __swab16(x)
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * CAM5200 is a TQM5200B based board. Additionally it also features
+ * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx
+ * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as
+ * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes
+ * access to flash chip slightly more complicated as additional byte
+ * swapping is necessary within each 16 bit wide flash 'word'.
+ *
+ * This driver's task is to handle both flash devices: 32 bit TQM5200B
+ * flash chip and 16 bit NIOS cpu flash chip. In the below
+ * flash_addr_table table we use least significant address bit to mark
+ * 16 bit flash bank and two sets of routines *_32 and *_16 to handle
+ * specifics of both flashes.
+ */
+static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
+ {CFG_BOOTCS_START, CFG_CS5_START | 1}
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word_32(flash_info_t * info, ulong dest, ulong data);
+static int write_word_16(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_32(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_16(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_32(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_16(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+ int i, k;
+ int size, erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_S29GL128N:
+ printf ("S29GL128N (256 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM320B:
+ printf ("29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf ("29LV320T (32 Mbit, top boot sect)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+
+ printf(" %08lX%s%s", info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+ return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+
+ DEBUGF("get_size: FLASH ADDR %08lx\n", addr);
+
+ /* bit 0 used for big flash marking */
+ if ((ulong)addr & 0x1)
+ return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info);
+ else
+ return flash_get_size_32(addr, info);
+}
+
+static ulong flash_get_size_32(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+ short i;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case AMD_ID_MIRROR:
+ DEBUGF("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
+ addr[14], addr[15]);
+ switch(addr[14]) {
+ case AMD_ID_GL128N_2:
+ if (addr[15] != AMD_ID_GL128N_3) {
+ DEBUGF("Chip: S29GL128N -> unknown\n");
+ info->flash_id = FLASH_UNKNOWN;
+ } else {
+ DEBUGF("Chip: S29GL128N\n");
+ info->flash_id += FLASH_S29GL128N;
+ info->sector_count = 128;
+ info->size = 0x02000000;
+ }
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return(0);
+ }
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00040000);
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_32(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (CFG_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
+ return flash_erase_16(info, s_first, s_last);
+ } else {
+ return flash_erase_32(info, s_first, s_last);
+ }
+}
+
+static int flash_erase_32(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!", prot);
+
+ printf("\n");
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_32(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+
+ for (; cnt == 0 && i < 4; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ if ((rc = write_word(info, wp, data)) != 0)
+ return (rc);
+
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i)
+ data = (data << 8) | *src++;
+
+ if ((rc = write_word(info, wp, data)) != 0)
+ return (rc);
+
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0)
+ return (0);
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
+ return write_word_16(info, dest, data);
+ } else {
+ return write_word_32(info, dest, data);
+ }
+}
+
+static int write_word_32(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i, flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data)
+ return (2);
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+ return (1);
+ }
+ }
+
+ return (0);
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+
+#undef CFG_FLASH_WORD_SIZE
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_16(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ CFG_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90009000;
+ udelay(1000);
+
+ value = swap16(addr2[0]);
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = swap16(addr2[1]); /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00002000;
+ info->start[2] = base + 0x00004000;
+ info->start[3] = base + 0x00006000;
+ info->start[4] = base + 0x00008000;
+ info->start[5] = base + 0x0000a000;
+ info->start[6] = base + 0x0000c000;
+ info->start[7] = base + 0x0000e000;
+
+ for (i = 8; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000) - 0x00070000;
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00002000;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000a000;
+ info->start[i--] = base + info->size - 0x0000c000;
+ info->start[i--] = base + info->size - 0x0000e000;
+
+ for (; i >= 0; i--)
+ info->start[i] = base + i * 0x00010000;
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_16(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CFG_FLASH_WORD_SIZE *addr =
+ (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x80008000) !=
+ (CFG_FLASH_WORD_SIZE) 0x80008000) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+static int flash_erase_16(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!", prot);
+
+ printf("\n");
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80008000;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
+ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30003000; /* sector erase */
+
+ l_sect = sect;
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_16(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+static int write_word_16(flash_info_t * info, ulong dest, ulong data)
+{
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ if ((dest2[i] & swap16(data2[i])) != swap16(data2[i]))
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA000A000;
+
+ dest2[i] = swap16(data2[i]);
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80008000) !=
+ (swap16(data2[i]) & (CFG_FLASH_WORD_SIZE) 0x80008000)) {
+
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+#endif /* CFG_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CFG_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0)
+ continue;
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+ &flash_info[i]);
+
+ flash_info[i].size = size_b[i];
+
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i+1, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+ &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH)
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#if defined(CFG_ENV_ADDR_REDUND)
+ (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#endif
+#endif
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
+#endif /* ifdef CONFIG_CAM5200 */
#include <command.h>
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
-#if defined (CONFIG_STK52XX)
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
#define DEFAULT_VOL 45
#define DEFAULT_FREQ 500
#define DEFAULT_DURATION 200
return rcode;
}
+#endif
+#if defined(CONFIG_STK52XX)
void led_init(void)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
return 0;
}
+#endif
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
/*
* return 1 on CAN initialization failure
* return 0 if no failure
return error_status;
}
+#ifndef CONFIG_FO300
static void sm501_backlight (unsigned int state)
{
if (state == BL_ON) {
*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
~((1 << 26) | (1 << 27));
}
+#endif
int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
printf ("Revision 100 of STK52XX not supported!\n");
return 1;
#endif
+#if defined(CONFIG_STK52XX)
led_init();
+#endif
can_init();
switch (argc) {
else
printf ("Error\n");
return rcode;
+#ifndef CONFIG_FO300
} else if (strncmp (argv[1], "backlight", 4) == 0) {
if (strncmp (argv[2], "on", 2) == 0) {
sm501_backlight (BL_ON);
sm501_backlight (BL_OFF);
return 0;
}
+#endif
}
break;
+#if defined(CONFIG_STK52XX)
case 4:
if (strcmp (argv[1], "led") == 0) {
return (do_led (argv));
}
break;
+#endif
default:
break;
"[channel]\n"
" - play short beep on \"l\"eft or \"r\"ight channel\n"
);
+#endif /* CONFIG_STK52XX || CONFIG_FO300 */
+#if defined(CONFIG_STK52XX)
U_BOOT_CMD(
fkt , 4, 1, cmd_fkt,
"fkt - Function test routines\n",
"fkt backlight on/off\n"
" - switch backlight on or off\n"
);
-#endif /* CONFIG_STK52XX */
+#elif defined(CONFIG_FO300)
+U_BOOT_CMD(
+ fkt , 3, 1, cmd_fkt,
+ "fkt - Function test routines\n",
+ "fkt can\n"
+ " - loopback plug for X16/X29 required\n"
+ "fkt rs232 number\n"
+ " - loopback plug(s) for X21/X22 required\n"
+);
+#endif
#endif /* CFG_CMD_BSP */
# 0x00100000 boot from RAM (for testing only)
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot low
#elif defined(CONFIG_TB5200)
# define CARRIER_NAME "TB5200"
#elif defined(CONFIG_CAM5200)
-# define CARRIER_NAME "Cam5200"
+# define CARRIER_NAME "CAM5200"
+#elif defined(CONFIG_FO300)
+# define CARRIER_NAME "FO300"
#else
-# error "Unknown carrier board"
+# error "UNKNOWN"
#endif
puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
#define SM501_GPIO_DATA_HIGH 0x00010004UL
#define SM501_GPIO_51 0x00080000UL
-#else
-#define GPIO_PSC1_4 0x01000000UL
-#endif
+#endif /* CONFIG MINIFAP */
void init_ide_reset (void)
{
}
#else
if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
} else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
#endif
}
*/
int post_hotkeys_pressed(void)
{
+#ifdef CONFIG_STK52XX
struct mpc5xxx_gpio *gpio;
gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
gpio->simple_ddr &= ~(0x20000000);
return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
+#else
+ return 0;
+#endif
}
#endif
#endif
#endif /* CONFIG_PS2MULT */
+#ifdef CONFIG_FO300
+int silent_boot (void)
+{
+ vu_long timer3_status;
+
+ /* Configure GPT3 as GPIO input */
+ *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
+
+ /* Read in TIMER_3 pin status */
+ timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
+
+#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
+ /* Force silent console mode if S1 switch
+ * is in closed position (TIMER_3 pin status is LOW). */
+ if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
+ return 1;
+#else
+ /* Force silent console mode if S1 switch
+ * is in open position (TIMER_3 pin status is HIGH). */
+ if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
+ return 1;
+#endif
+
+ return 0;
+}
+
+int board_early_init_f (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ if (silent_boot())
+ gd->flags |= GD_FLG_SILENT;
+
+ return 0;
+}
+#endif /* CONFIG_FO300 */
+
int last_stage_init (void)
{
/*
__asm__ volatile ("sync");
}
+#ifdef CONFIG_FO300
+ if (silent_boot()) {
+ setenv("bootdelay", "0");
+ disable_ctrlc(1);
+ }
+#endif
+
return 0;
}
#ifdef CONFIG_VIDEO_SM501
+#ifdef CONFIG_FO300
+#define DISPLAY_WIDTH 800
+#else
#define DISPLAY_WIDTH 640
+#endif
#define DISPLAY_HEIGHT 480
#ifdef CONFIG_VIDEO_SM501_8BPP
{0x80218, 0x000201e9},
{0x80200, 0x00013306},
#else /* panel + CRT */
+#ifdef CONFIG_FO300
+ {0x00004, 0x0},
+ {0x00048, 0x00021807},
+ {0x0004C, 0x301a0a01},
+ {0x00054, 0x1},
+ {0x00040, 0x00021807},
+ {0x00044, 0x091a0a01},
+ {0x00054, 0x0},
+ {0x80000, 0x0f013106},
+ {0x80004, 0xc428bb17},
+ {0x8000C, 0x00000000},
+ {0x80010, 0x0C800C80},
+ {0x80014, 0x03200000},
+ {0x80018, 0x01e00000},
+ {0x8001C, 0x00000000},
+ {0x80020, 0x01e00320},
+ {0x80024, 0x042a031f},
+ {0x80028, 0x0086034a},
+ {0x8002C, 0x020c01df},
+ {0x80030, 0x000201ea},
+ {0x80200, 0x00010000},
+#else
{0x00004, 0x0},
{0x00048, 0x00021807},
{0x0004C, 0x091a0a01},
{0x8002C, 0x020c01df},
{0x80030, 0x000201e9},
{0x80200, 0x00010000},
+#endif /* #ifdef CONFIG_FO300 */
#endif
{0, 0}
};
{
if (line_number == 1) {
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200)
+#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
} else if (line_number == 2) {
#if defined (CONFIG_STK52XX)
strcpy (info, " on a STK52xx carrier board");
#if defined (CONFIG_TB5200)
strcpy (info, " on a TB5200 carrier board");
#endif
+#if defined (CONFIG_FO300)
+ strcpy (info, " on a FO300 carrier board");
+#endif
#endif
}
else {
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../tqm8xx/)
+endif
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../tqm8xx/load_sernum_ethaddr.o
+COBJS = $(BOARD).o flash.o ../tqm8xx/load_sernum_ethaddr.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# Copyright 2004 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o pci.o
-OBJS = $(BOARD).o pci.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o sdram.o
+COBJS := $(BOARD).o sdram.o
SOBJS := init.o
#SOBJS :=
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
void pci_init_board (void)
{
#ifdef CONFIG_PCI
- extern void pci_mpc85xx_init (struct pci_controller *hose);
-
pci_mpc85xx_init (&hose);
#endif /* CONFIG_PCI */
}
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o load_sernum_ethaddr.o
+COBJS = $(BOARD).o flash.o load_sernum_ethaddr.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o
+COBJS := trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o
SOBJS := lowlevel_init.o
+COBJS_FKT := trab_fkt.o rs485.o tsc2000.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS_FKT:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+OBJS_FKT := $(addprefix $(obj),$(COBJS_FKT))
+
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
LOAD_ADDR = 0xc100000
#########################################################################
-all: $(LIB) trab_fkt.srec trab_fkt.bin
+all: $(LIB) $(obj)trab_fkt.srec $(obj)trab_fkt.bin
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-trab_fkt.srec: trab_fkt.o rs485.o tsc2000.o $(LIB)
- $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ $(LIB) \
- -L../../examples -lstubs \
- -L../../lib_generic -lgeneric \
+$(obj)trab_fkt.srec: $(OBJS_FKT) $(LIB)
+ $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \
+ -L$(obj)../../examples -lstubs \
+ -L$(obj)../../lib_generic -lgeneric \
-L$(gcclibdir) -lgcc
$(OBJCOPY) -O srec $(<:.o=) $@
-trab_fkt.bin: trab_fkt.srec
+$(obj)trab_fkt.bin: $(obj)trab_fkt.srec
$(OBJCOPY) -I srec -O binary $< $@
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(SOBJS) $(OBJS) $(OBJS_FKT)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
# download areas is 0C80'0000
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0x0DF40000
#endif /* CONFIG_VERSION_VARIABLE */
#ifdef CONFIG_AUTO_UPDATE
- extern int do_auto_update(void);
- /* this has priority over all else */
- do_auto_update();
+ {
+ extern int do_auto_update(void);
+ /* this has priority over all else */
+ do_auto_update();
+ }
#endif
for (i = 0; i < KEYBD_KEY_NUM; ++i) {
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-#OBJS = $(BOARD).o flash.o pcmcia.o
-OBJS = $(BOARD).o pcmcia.o
+#COBJS = $(BOARD).o flash.o pcmcia.o
+COBJS = $(BOARD).o pcmcia.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2002
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-SOBJS =
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): .depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
--- /dev/null
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o ethaddr.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MarelV38B board
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+TEXT_BASE = 0xFF000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+/* For the V38B board the pin is GPIO_PSC_6 */
+#define GPIO_PIN GPIO_PSC6_0
+
+#define NO_ERROR 0
+#define ERR_NO_NUMBER 1
+#define ERR_BAD_NUMBER 2
+
+static int is_high(void);
+static int check_device(void);
+static void io_out(int value);
+static void io_input(void);
+static void io_output(void);
+static void init_gpio(void);
+static void read_byte(unsigned char *data);
+static void write_byte(unsigned char command);
+
+void read_2501_memory(unsigned char *psernum, unsigned char *perr);
+void board_get_enetaddr(uchar *enetaddr);
+
+
+static int is_high()
+{
+ return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN);
+}
+
+static void io_out(int value)
+{
+ if (value)
+ *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN;
+ else
+ *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN;
+}
+
+static void io_input()
+{
+ *((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN;
+ udelay(3); /* allow input to settle */
+}
+
+static void io_output()
+{
+ *((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN;
+}
+
+static void init_gpio()
+{
+ *((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */
+}
+
+void read_2501_memory(unsigned char *psernum, unsigned char *perr)
+{
+#define NBYTES 28
+ unsigned char crcval, i;
+ unsigned char buf[NBYTES];
+
+ *perr = 0;
+ crcval = 0;
+
+ for (i = 0; i < NBYTES; i++)
+ buf[i] = 0;
+
+ if (!check_device())
+ *perr = ERR_NO_NUMBER;
+ else {
+ *perr = NO_ERROR;
+ write_byte(0xCC); /* skip ROM (0xCC) */
+ write_byte(0xF0); /* Read memory command 0xF0 */
+ write_byte(0x00); /* Address TA1=0, TA2=0 */
+ write_byte(0x00);
+ read_byte(&crcval); /* Read CRC of address and command */
+
+ for (i = 0; i < NBYTES; i++)
+ read_byte(&buf[i]);
+ }
+ if (strncmp((const char *) &buf[11], "MAREL IEEE 802.3", 16)) {
+ *perr = ERR_BAD_NUMBER;
+ psernum[0] = 0x00;
+ psernum[1] = 0xE0;
+ psernum[2] = 0xEE;
+ psernum[3] = 0xFF;
+ psernum[4] = 0xFF;
+ psernum[5] = 0xFF;
+ } else {
+ psernum[0] = 0x00;
+ psernum[1] = 0xE0;
+ psernum[2] = 0xEE;
+ psernum[3] = buf[7];
+ psernum[4] = buf[6];
+ psernum[5] = buf[5];
+ }
+}
+
+static int check_device()
+{
+ int found;
+
+ io_output();
+ io_out(0);
+ udelay(500); /* must be at least 480 us low pulse */
+
+ io_input();
+ udelay(60);
+
+ found = (is_high() == 0) ? 1 : 0;
+ udelay(500); /* must be at least 480 us low pulse */
+
+ return found;
+}
+
+static void write_byte(unsigned char command)
+{
+ char i;
+
+ for (i = 0; i < 8; i++) {
+ /* 1 us to 15 us low pulse starts bit slot */
+ /* Start with high pulse for 3 us */
+ io_input();
+ udelay(3);
+
+ io_out(0);
+ io_output();
+ udelay(3);
+
+ if (command & 0x01) {
+ /* 60 us high for 1-bit */
+ io_input();
+ udelay(60);
+ } else
+ /* 60 us low for 0-bit */
+ udelay(60);
+ /* Leave pin as input */
+ io_input();
+
+ command = command >> 1;
+ }
+}
+
+static void read_byte(unsigned char *data)
+{
+ unsigned char i, rdat = 0;
+
+ for (i = 0; i < 8; i++) {
+ /* read one bit from one-wire device */
+
+ /* 1 - 15 us low starts bit slot */
+ io_out(0);
+ io_output();
+ udelay(0);
+
+ /* allow line to be pulled high */
+ io_input();
+
+ /* delay 10 us */
+ udelay(10);
+
+ /* now sample input status */
+ if (is_high())
+ rdat = (rdat >> 1) | 0x80;
+ else
+ rdat = rdat >> 1;
+
+ udelay(60); /* at least 60 us */
+ }
+ /* copy the return value */
+ *data = rdat;
+}
+
+void board_get_enetaddr(uchar *enetaddr)
+{
+ unsigned char sn[6], err = NO_ERROR;
+
+ init_gpio();
+
+ read_2501_memory(sn, &err);
+
+ if (err == NO_ERROR) {
+ sprintf((char *)enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
+ sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
+ printf("MAC address: %s\n", enetaddr);
+ setenv("ethaddr", (char *)enetaddr);
+ } else {
+ sprintf((char *)enetaddr, "00:01:02:03:04:05");
+ printf("Error reading MAC address.\n");
+ printf("Setting default to %s\n", enetaddr);
+ setenv("ethaddr", (char *)enetaddr);
+ }
+}
--- /dev/null
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc5xxx/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+
+
+#ifndef CFG_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+#endif /* SDRAM_DDR */
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+#endif /* !CFG_RAMBOOT */
+
+
+long int initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ uint svr, pvr;
+
+#ifndef CFG_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+#endif /* SDRAM_DDR */
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else
+ dramsize = test2;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0)
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ else
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+ /* find RAM size using SDRAM CS1 only */
+ if (!dramsize)
+ sdram_start(0);
+ test2 = test1 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ if (!dramsize) {
+ sdram_start(1);
+ test2 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ }
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else
+ dramsize2 = test2;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20))
+ dramsize2 = 0;
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0)
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ else
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+
+#else /* CFG_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13)
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ else
+ dramsize2 = 0;
+
+#endif /* CFG_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ *(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
+ return dramsize + dramsize2;
+}
+
+
+int checkboard (void)
+{
+ puts("Board: MarelV38B\n");
+ return 0;
+}
+
+
+int board_early_init_r(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write access for the
+ * detection process. Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+
+#ifdef CONFIG_HW_WATCHDOG
+ /*
+ * Enable and configure the direction (output) of PSC3_9 - watchdog
+ * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
+ * Manual.
+ */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
+#endif /* CONFIG_HW_WATCHDOG */
+
+ /*
+ * Enable GPIO_WKUP_7 to "read the status of the actual power
+ * situation". Default direction is input, so no need to set it
+ * explicitly.
+ */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
+ return 0;
+}
+
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+void init_ide_reset(void)
+{
+ debug("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+ /* Deassert reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+
+
+void ide_set_reset(int idereset)
+{
+ debug("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+ /* Make a delay. MPC5200 spec says 25 usec min */
+ udelay(500000);
+ } else
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ /*
+ * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
+ * we need a positive or negative transition on WDI i.e., our PSC3_9.
+ */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
+}
+#endif /* CONFIG_HW_WATCHDOG */
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := versatile.o flash.o
+COBJS := versatile.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
# ---------------------------------------------------------
# Set up the Versatile type define
# ---------------------------------------------------------
+
+mkdir -p ${obj}include
variant=PB926EJ-S
if [ "$1" == "" ]
then
echo "$0:: No parameters - using versatilepb_config"
- echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h
+ echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h
variant=PB926EJ-S
else
case "$1" in
versatilepb_config | \
versatile_config)
- echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h
+ echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h
;;
versatileab_config)
- echo "#define CONFIG_ARCH_VERSATILE_AB" > ./include/config.h
+ echo "#define CONFIG_ARCH_VERSATILE_AB" > ${obj}include/config.h
variant=AB926EJ-S
;;
*)
echo "$0:: Unrecognised config - using versatilepb_config"
- echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h
+ echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h
variant=PB926EJ-S
;;
# ---------------------------------------------------------
# Complete the configuration
# ---------------------------------------------------------
-./mkconfig -a versatile arm arm926ejs versatile NULL versatile
+$MKCONFIG -a versatile arm arm926ejs versatile NULL versatile
echo "Variant:: $variant"
-# (C) Copyright 2000-2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de
#
# (C) Copyright 2005
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := voiceblue.o
+COBJS := voiceblue.o
SOBJS := setup.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c eeprom_start.S
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
LOAD_ADDR = 0x10400000
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
+lnk = $(if $(obj),$(obj),.)
-all: $(LIB) eeprom.srec eeprom.bin
+all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-eeprom.srec: eeprom.o eeprom_start.o
- $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
- -o $(<:.o=) -e $(<:.o=) $^ \
- -L../../examples -lstubs \
- -L../../lib_generic -lgeneric \
+$(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o
+ cd $(lnk) && $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
+ -o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \
+ -L$(obj)../../examples -lstubs \
+ -L$(obj)../../lib_generic -lgeneric \
-L$(gcclibdir) -lgcc
$(OBJCOPY) -O srec $(<:.o=) $@
-eeprom.bin: eeprom.srec
+$(obj)eeprom.bin: $(obj)eeprom.srec
$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
clean:
- rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin
+ rm -f $(SOBJS) $(OBJS) $(obj)eeprom \
+ $(obj)eeprom.srec $(obj)eeprom.bin \
+ $(obj)eeprom.o $(obj)eeprom_start.o
+
distclean: clean
rm -f $(LIB) core config.tmp *.bak .depend
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
# entry 1000'8000 (mem base + reserved)
#
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifeq ($(VOICEBLUE_SMALL_FLASH),y)
# We load ourself to internal SRAM at 2001'2000
*((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa;
/* arch number of VoiceBlue board */
- /* TODO: use define from asm/mach-types.h */
- gd->bd->bi_arch_number = 218;
+ gd->bd->bi_arch_number = MACH_TYPE_VOICEBLUE;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x10000100;
{
*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff;
- /* Take the Ethernet controller out of reset and wait
- * for the EEPROM load to complete. */
+ /* Take the Ethernet controller out of reset and wait
+ * for the EEPROM load to complete. */
*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80;
udelay(10); /* doesn't work before interrupt_init call */
*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80;
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2001
# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
#
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \
+COBJS = $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \
watchdog.o
SOBJS = init.o post1.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := wepep250.o flash.o
+COBJS := wepep250.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o flash.o
+COBJS = $(BOARD).o flash.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := xaeniax.o flash.o
+COBJS := xaeniax.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
+#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+$(shell mkdir -p $(obj)../xilinx_enet)
+$(shell mkdir -p $(obj)../xilinx_iic)
+endif
-CFLAGS += -I../ml300 -I../common -I../xilinx_enet -I../xilinx_iic
+INCS := -I../ml300 -I../common -I../xilinx_enet -I../xilinx_iic
+CFLAGS += $(INCS)
+HOST_CFLAGS += $(INCS)
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o \
+COBJS = $(BOARD).o \
serial.o \
../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := xm250.o flash.o
+COBJS := xm250.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2002-2004
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS = $(BOARD).o
-OBJS +=flash.o
+COBJS = $(BOARD).o flash.o
SOBJS = init.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := xsengine.o flash.o
+COBJS := xsengine.o flash.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := $(BOARD).o
+COBJS := $(BOARD).o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
+
include $(TOPDIR)/config.mk
-LIB = lib$(BOARD).a
+LIB = $(obj)lib$(BOARD).a
-OBJS := zylonite.o nand.o
+COBJS := zylonite.o nand.o
SOBJS := lowlevel_init.o
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
#TEXT_BASE = 0xa1700000
#TEXT_BASE = 0xa3080000
TEXT_BASE = 0xa3008000
-
-BOARDLIBS = drivers/nand/libnand.a
#
-# (C) Copyright 2004
+# (C) Copyright 2004-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = libcommon.a
+LIB = $(obj)libcommon.a
AOBJS =
memsize.o miiphybb.o miiphyutil.o \
s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
usb.o usb_kbd.o usb_storage.o \
- virtex2.o xilinx.o crc16.o xyzModem.o
+ virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o
-OBJS = $(AOBJS) $(COBJS)
+SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
CPPFLAGS += -I..
all: $(LIB) $(AOBJS)
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
-environment.o: environment.c ../tools/envcrc
+$(obj)environment.o: $(src)environment.c $(obj)../tools/envcrc
$(CC) $(AFLAGS) -Wa,--no-warn \
- -DENV_CRC=$(shell ../tools/envcrc) \
- -c -o $@ environment.c
+ -DENV_CRC=$(shell $(obj)../tools/envcrc) \
+ -c -o $@ $(src)environment.c
-../tools/envcrc:
+$(obj)../tools/envcrc:
$(MAKE) -C ../tools
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440SP)
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
print_str ("procfreq", strmhz(buf, bd->bi_procfreq));
print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq));
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
U_BOOT_CMD(
- reset, 1, 0, do_reset,
+ reset, CFG_MAXARGS, 1, do_reset,
"reset - Perform RESET of the CPU\n",
NULL
);
if (hdr->ih_arch != IH_CPU_NIOS2)
#elif defined(__blackfin__)
if (hdr->ih_arch != IH_CPU_BLACKFIN)
+#elif defined(__avr32__)
+ if (hdr->ih_arch != IH_CPU_AVR32)
#else
# error Unknown CPU type
#endif
"[addr [arg ...]]\n - boot application image stored in memory\n"
"\tpassing arguments 'arg ...'; when booting a Linux kernel,\n"
"\t'arg' can be the address of an initrd image\n"
+#ifdef CONFIG_OF_FLAT_TREE
+ "\tWhen booting a Linux kernel which requires a flat device-tree\n"
+ "\ta third argument is required which is the address of the of the\n"
+ "\tdevice-tree blob. To boot that kernel without an initrd image,\n"
+ "\tuse a '-' for the second argument. If you do not pass a third\n"
+ "\ta bd_info struct will be passed instead\n"
+#endif
);
#ifdef CONFIG_SILENT_CONSOLE
}
#endif /* CONFIG_SILENT_CONSOLE */
-#ifdef CONFIG_OF_FLAT_TREE
-extern const unsigned char oftree_dtb[];
-extern const unsigned int oftree_dtb_len;
-#endif
-
#ifdef CONFIG_PPC
-static void
+static void __attribute__((noinline))
do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
int argc, char *argv[],
ulong addr,
void (*kernel)(bd_t *, ulong, ulong, ulong, ulong);
image_header_t *hdr = &header;
#ifdef CONFIG_OF_FLAT_TREE
- char *of_flat_tree;
+ char *of_flat_tree = NULL;
+ ulong of_data = 0;
#endif
if ((s = getenv ("initrd_high")) != NULL) {
/*
* Check if there is an initrd image
*/
+
+#ifdef CONFIG_OF_FLAT_TREE
+ /* Look for a '-' which indicates to ignore the ramdisk argument */
+ if (argc >= 3 && strcmp(argv[2], "-") == 0) {
+ debug ("Skipping initrd\n");
+ len = data = 0;
+ }
+ else
+#endif
if (argc >= 3) {
+ debug ("Not skipping initrd\n");
SHOW_BOOT_PROGRESS (9);
addr = simple_strtoul(argv[2], NULL, 16);
len = data = 0;
}
+#ifdef CONFIG_OF_FLAT_TREE
+ if(argc > 3) {
+ of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16);
+ hdr = (image_header_t *)of_flat_tree;
+
+ if (*(ulong *)of_flat_tree == OF_DT_HEADER) {
+#ifndef CFG_NO_FLASH
+ if (addr2info((ulong)of_flat_tree) != NULL)
+ of_data = (ulong)of_flat_tree;
+#endif
+ } else if (ntohl(hdr->ih_magic) == IH_MAGIC) {
+ printf("## Flat Device Tree Image at %08lX\n", hdr);
+ print_image_hdr(hdr);
+
+ if ((ntohl(hdr->ih_load) < ((unsigned long)hdr + ntohl(hdr->ih_size) + sizeof(hdr))) &&
+ ((ntohl(hdr->ih_load) + ntohl(hdr->ih_size)) > (unsigned long)hdr)) {
+ printf ("ERROR: Load address overwrites Flat Device Tree uImage\n");
+ return;
+ }
+
+ printf(" Verifying Checksum ... ");
+ memmove (&header, (char *)hdr, sizeof(image_header_t));
+ checksum = ntohl(header.ih_hcrc);
+ header.ih_hcrc = 0;
+
+ if(checksum != crc32(0, (uchar *)&header, sizeof(image_header_t))) {
+ printf("ERROR: Flat Device Tree header checksum is invalid\n");
+ return;
+ }
+
+ checksum = ntohl(hdr->ih_dcrc);
+ addr = (ulong)((uchar *)(hdr) + sizeof(image_header_t));
+ len = ntohl(hdr->ih_size);
+
+ if(checksum != crc32(0, (uchar *)addr, len)) {
+ printf("ERROR: Flat Device Tree checksum is invalid\n");
+ return;
+ }
+ printf("OK\n");
+
+ if (ntohl(hdr->ih_type) != IH_TYPE_FLATDT) {
+ printf ("ERROR: uImage not Flat Device Tree type\n");
+ return;
+ }
+ if (ntohl(hdr->ih_comp) != IH_COMP_NONE) {
+ printf("ERROR: uImage is not uncompressed\n");
+ return;
+ }
+ if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
+ printf ("ERROR: uImage data is not a flat device tree\n");
+ return;
+ }
+
+ memmove((void *)ntohl(hdr->ih_load),
+ (void *)(of_flat_tree + sizeof(image_header_t)),
+ ntohl(hdr->ih_size));
+ of_flat_tree = (char *)ntohl(hdr->ih_load);
+ } else {
+ printf ("Did not find a flat flat device tree at address %08lX\n", of_flat_tree);
+ return;
+ }
+ printf (" Booting using flat device tree at 0x%x\n",
+ of_flat_tree);
+ } else if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1]) && (len_ptr[2])) {
+ u_long tail = ntohl(len_ptr[0]) % 4;
+ int i;
+
+ /* skip kernel length, initrd length, and terminator */
+ of_data = (ulong)(&len_ptr[3]);
+ /* skip any additional image length fields */
+ for (i=2; len_ptr[i]; ++i)
+ of_data += 4;
+ /* add kernel length, and align */
+ of_data += ntohl(len_ptr[0]);
+ if (tail) {
+ of_data += 4 - tail;
+ }
+
+ /* add initrd length, and align */
+ tail = ntohl(len_ptr[1]) % 4;
+ of_data += ntohl(len_ptr[1]);
+ if (tail) {
+ of_data += 4 - tail;
+ }
+
+ if (((struct boot_param_header *)of_data)->magic != OF_DT_HEADER) {
+ printf ("ERROR: image is not a flat device tree\n");
+ return;
+ }
+
+ if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) {
+ printf ("ERROR: flat device tree size does not agree with image\n");
+ return;
+ }
+
+ } else if (getenv("disable_of") == NULL) {
+ printf ("ERROR: bootm needs flat device tree as third argument\n");
+ return;
+ }
+#endif
if (!data) {
debug ("No initrd\n");
}
initrd_end = 0;
}
-#ifdef CONFIG_OF_FLAT_TREE
- if (initrd_start == 0)
- of_flat_tree = (char *)(((ulong)kbd - OF_FLAT_TREE_MAX_SIZE -
- sizeof(bd_t)) & ~0xF);
- else
- of_flat_tree = (char *)((initrd_start - OF_FLAT_TREE_MAX_SIZE -
- sizeof(bd_t)) & ~0xF);
-#endif
-
debug ("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)kernel);
*/
(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
-#else
- ft_setup(of_flat_tree, OF_FLAT_TREE_MAX_SIZE, kbd, initrd_start, initrd_end);
+#else /* CONFIG_OF_FLAT_TREE */
+ /* move of_flat_tree if needed */
+ if (of_data) {
+ ulong of_start, of_len;
+ of_len = ((struct boot_param_header *)of_data)->totalsize;
+ /* provide extra 8k pad */
+ if (initrd_start)
+ of_start = initrd_start - of_len - 8192;
+ else
+ of_start = (ulong)kbd - of_len - 8192;
+ of_start &= ~(4096 - 1); /* align on page */
+ debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
+ of_data, of_data + of_len - 1, of_len, of_len);
+
+ of_flat_tree = (char *)of_start;
+ printf (" Loading Device Tree to %08lx, end %08lx ... ",
+ of_start, of_start + of_len - 1);
+ memmove ((void *)of_start, (void *)of_data, of_len);
+ }
+
+ ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
/* ft_dump_blob(of_flat_tree); */
#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
if (getenv("disable_of") != NULL)
(*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end,
cmd_start, cmd_end);
- else
+ else {
+ ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
+ /* ft_dump_blob(of_flat_tree); */
(*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
-
-#endif
+ }
+#endif /* CONFIG_OF_FLAT_TREE */
}
#endif /* CONFIG_PPC */
case IH_CPU_INVALID: arch = "Invalid CPU"; break;
case IH_CPU_ALPHA: arch = "Alpha"; break;
case IH_CPU_ARM: arch = "ARM"; break;
+ case IH_CPU_AVR32: arch = "AVR32"; break;
case IH_CPU_I386: arch = "Intel x86"; break;
case IH_CPU_IA64: arch = "IA64"; break;
case IH_CPU_MIPS: arch = "MIPS"; break;
case IH_TYPE_MULTI: type = "Multi-File Image"; break;
case IH_TYPE_FIRMWARE: type = "Firmware"; break;
case IH_TYPE_SCRIPT: type = "Script"; break;
+ case IH_TYPE_FLATDT: type = "Flat Device Tree"; break;
default: type = "Unknown Image"; break;
}
#if defined(CONFIG_4xx) && (CONFIG_COMMANDS & CFG_CMD_SETGETDCR)
+unsigned long get_dcr (unsigned short);
+unsigned long set_dcr (unsigned short, unsigned long);
+
/* =======================================================================
* Interpreter command to retrieve an AMCC PPC 4xx Device Control Register
* =======================================================================
*/
int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
- unsigned long get_dcr (unsigned short);
- unsigned long set_dcr (unsigned short, unsigned long);
unsigned short dcrn; /* Device Control Register Num */
unsigned long value;
return 0;
}
+/* =======================================================================
+ * Interpreter command to retrieve an register value through AMCC PPC 4xx
+ * Device Control Register inderect addressing.
+ * =======================================================================
+ */
+int do_getidcr (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned short adr_dcrn; /* Device Control Register Num for Address */
+ unsigned short dat_dcrn; /* Device Control Register Num for Data */
+ unsigned short offset; /* Register's offset */
+ unsigned long value; /* Register's value */
+ char *ptr = NULL;
+ char buf[80];
+
+ /* Validate arguments */
+ if (argc < 3) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ /* Find out whether ther is '.' (dot) symbol in the first parameter. */
+ strncpy (buf, argv[1], sizeof(buf)-1);
+ buf[sizeof(buf)-1] = 0; /* will guarantee zero-end string */
+ ptr = strchr (buf, '.');
+
+ if (ptr != NULL) {
+ /* First parameter has format adr_dcrn.dat_dcrn */
+ *ptr++ = 0; /* erase '.', create zero-end string */
+ adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16);
+ dat_dcrn = (unsigned short) simple_strtoul (ptr, NULL, 16);
+ } else {
+ /*
+ * First parameter has format adr_dcrn; dat_dcrn will be
+ * calculated as adr_dcrn+1.
+ */
+ adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16);
+ dat_dcrn = adr_dcrn+1;
+ }
+
+ /* Register's offset */
+ offset = (unsigned short) simple_strtoul (argv[2], NULL, 16);
+
+ /* Disable interrupts */
+ disable_interrupts ();
+ /* Set offset */
+ set_dcr (adr_dcrn, offset);
+ /* get data */
+ value = get_dcr (dat_dcrn);
+ /* Enable interrupts */
+ enable_interrupts ();
+
+ printf ("%04x.%04x-%04x Read %08lx\n", adr_dcrn, dat_dcrn, offset, value);
+
+ return 0;
+}
+
+/* =======================================================================
+ * Interpreter command to update an register value through AMCC PPC 4xx
+ * Device Control Register inderect addressing.
+ * =======================================================================
+ */
+int do_setidcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned short adr_dcrn; /* Device Control Register Num for Address */
+ unsigned short dat_dcrn; /* Device Control Register Num for Data */
+ unsigned short offset; /* Register's offset */
+ unsigned long value; /* Register's value */
+ char *ptr = NULL;
+ char buf[80];
+
+ /* Validate arguments */
+ if (argc < 4) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ /* Find out whether ther is '.' (dot) symbol in the first parameter. */
+ strncpy (buf, argv[1], sizeof(buf)-1);
+ buf[sizeof(buf)-1] = 0; /* will guarantee zero-end string */
+ ptr = strchr (buf, '.');
+
+ if (ptr != NULL) {
+ /* First parameter has format adr_dcrn.dat_dcrn */
+ *ptr++ = 0; /* erase '.', create zero-end string */
+ adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16);
+ dat_dcrn = (unsigned short) simple_strtoul (ptr, NULL, 16);
+ } else {
+ /*
+ * First parameter has format adr_dcrn; dat_dcrn will be
+ * calculated as adr_dcrn+1.
+ */
+ adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16);
+ dat_dcrn = adr_dcrn+1;
+ }
+
+ /* Register's offset */
+ offset = (unsigned short) simple_strtoul (argv[2], NULL, 16);
+ /* New value */
+ value = (unsigned long) simple_strtoul (argv[3], NULL, 16);
+
+ /* Disable interrupts */
+ disable_interrupts ();
+ /* Set offset */
+ set_dcr (adr_dcrn, offset);
+ /* set data */
+ set_dcr (dat_dcrn, value);
+ /* Enable interrupts */
+ enable_interrupts ();
+
+ printf ("%04x.%04x-%04x Write %08lx\n", adr_dcrn, dat_dcrn, offset, value);
+
+ return 0;
+}
+
/***************************************************/
U_BOOT_CMD(
"dcrn - set a DCR's value.\n"
);
+U_BOOT_CMD(
+ getidcr, 3, 1, do_getidcr,
+ "getidcr - Get a register value via indirect DCR addressing\n",
+ "adr_dcrn[.dat_dcrn] offset - write offset to adr_dcrn, read value from dat_dcrn.\n"
+);
+
+U_BOOT_CMD(
+ setidcr, 4, 1, do_setidcr,
+ "setidcr - Set a register value via indirect DCR addressing\n",
+ "adr_dcrn[.dat_dcrn] offset value - write offset to adr_dcrn, write value to dat_dcrn.\n"
+);
+
#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */
part_num = 0;
list_for_each(pentry, &dev->parts) {
part = list_entry(pentry, struct part_info, link);
- printf(" %d: %-22s\t0x%08x\t0x%08x\t%d\n",
+ printf("%2d: %-20s0x%08x\t0x%08x\t%d\n",
part_num, part->name, part->size,
part->offset, part->mask_flags);
* Given partition identifier in form of <dev_type><dev_num>,<part_num> find
* corresponding device and verify partition number.
*
- * @param id string describing device and partition
+ * @param id string describing device and partition or partition name
* @param dev pointer to the requested device (output)
* @param part_num verified partition number (output)
* @param part pointer to requested partition (output)
int find_dev_and_part(const char *id, struct mtd_device **dev,
u8 *part_num, struct part_info **part)
{
+ struct list_head *dentry, *pentry;
u8 type, dnum, pnum;
const char *p;
DEBUGF("--- find_dev_and_part ---\nid = %s\n", id);
+ list_for_each(dentry, &devices) {
+ *part_num = 0;
+ *dev = list_entry(dentry, struct mtd_device, link);
+ list_for_each(pentry, &(*dev)->parts) {
+ *part = list_entry(pentry, struct part_info, link);
+ if (strcmp((*part)->name, id) == 0)
+ return 0;
+ (*part_num)++;
+ }
+ }
+
p = id;
*dev = NULL;
*part = NULL;
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CFG_ID_EEPROM
+
+extern int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+U_BOOT_CMD(
+ mac, 3, 1, do_mac,
+ "mac - display and program the system ID and MAC addresses in EEPROM\n",
+ "[read|save|id|num|errata|date|ports|0|1|2|3|4|5|6|7]\n"
+ "read\n"
+ " - show content of mac\n"
+ "mac save\n"
+ " - save to the EEPROM\n"
+ "mac id\n"
+ " - program system id\n"
+ "mac num\n"
+ " - program system serial number\n"
+ "mac errata\n"
+ " - program errata data\n"
+ "mac date\n"
+ " - program data date\n"
+ "mac ports\n"
+ " - program the number of ports\n"
+ "mac 0\n"
+ " - program the MAC address for port 0\n"
+ "mac 1\n"
+ " - program the MAC address for port 1\n"
+ "mac 2\n"
+ " - program the MAC address for port 2\n"
+ "mac 3\n"
+ " - program the MAC address for port 3\n"
+ "mac 4\n"
+ " - program the MAC address for port 4\n"
+ "mac 5\n"
+ " - program the MAC address for port 5\n"
+ "mac 6\n"
+ " - program the MAC address for port 6\n"
+ "mac 7\n"
+ " - program the MAC address for port 7\n"
+);
+#endif /* CFG_ID_EEPROM */
miiphy_speed (devname, j),
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
- } else {
- puts ("Error reading info from the PHY\n");
}
}
} else if (op == 'r') {
miiphy_speed (devname, j),
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
- } else {
- puts ("Error reading info from the PHY\n");
}
}
} else if (op[0] == 'r') {
#include <jffs2/jffs2.h>
#include <nand.h>
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+
+/* parition handling routines */
+int mtdparts_init(void);
+int id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *dev_num);
+int find_dev_and_part(const char *id, struct mtd_device **dev,
+ u8 *part_num, struct part_info **part);
+#endif
+
extern nand_info_t nand_info[]; /* info for NAND chips */
static int nand_dump_oob(nand_info_t *nand, ulong off)
/* ------------------------------------------------------------------------- */
-static void
-arg_off_size(int argc, char *argv[], ulong *off, ulong *size, ulong totsize)
+static inline int str2long(char *p, ulong *num)
{
- *off = 0;
- *size = 0;
-
-#if defined(CONFIG_JFFS2_NAND) && defined(CFG_JFFS_CUSTOM_PART)
- if (argc >= 1 && strcmp(argv[0], "partition") == 0) {
- int part_num;
- struct part_info *part;
- const char *partstr;
-
- if (argc >= 2)
- partstr = argv[1];
- else
- partstr = getenv("partition");
+ char *endptr;
- if (partstr)
- part_num = (int)simple_strtoul(partstr, NULL, 10);
- else
- part_num = 0;
+ *num = simple_strtoul(p, &endptr, 16);
+ return (*p != '\0' && *endptr == '\0') ? 1 : 0;
+}
- part = jffs2_part_info(part_num);
- if (part == NULL) {
- printf("\nInvalid partition %d\n", part_num);
- return;
+static int
+arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size)
+{
+ int idx = nand_curr_device;
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+ struct mtd_device *dev;
+ struct part_info *part;
+ u8 pnum;
+
+ if (argc >= 1 && !(str2long(argv[0], off))) {
+ if ((mtdparts_init() == 0) &&
+ (find_dev_and_part(argv[0], &dev, &pnum, &part) == 0)) {
+ if (dev->id->type != MTD_DEV_TYPE_NAND) {
+ puts("not a NAND device\n");
+ return -1;
+ }
+ *off = part->offset;
+ if (argc >= 2) {
+ if (!(str2long(argv[1], size))) {
+ printf("'%s' is not a number\n", argv[1]);
+ return -1;
+ }
+ if (*size > part->size)
+ *size = part->size;
+ } else {
+ *size = part->size;
+ }
+ idx = dev->id->num;
+ *nand = nand_info[idx];
+ goto out;
}
- *size = part->size;
- *off = (ulong)part->offset;
- } else
+ }
#endif
- {
- if (argc >= 1)
- *off = (ulong)simple_strtoul(argv[0], NULL, 16);
- else
- *off = 0;
- if (argc >= 2)
- *size = (ulong)simple_strtoul(argv[1], NULL, 16);
- else
- *size = totsize - *off;
+ if (argc >= 1) {
+ if (!(str2long(argv[0], off))) {
+ printf("'%s' is not a number\n", argv[0]);
+ return -1;
+ }
+ } else {
+ *off = 0;
+ }
+ if (argc >= 2) {
+ if (!(str2long(argv[1], size))) {
+ printf("'%s' is not a number\n", argv[1]);
+ return -1;
+ }
+ } else {
+ *size = nand->size - *off;
}
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+out:
+#endif
+ printf("device %d ", idx);
+ if (*size == nand->size)
+ puts("whole chip\n");
+ else
+ printf("offset 0x%x, size 0x%x\n", *off, *size);
+ return 0;
}
int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
ulong addr, off, size;
char *cmd, *s;
nand_info_t *nand;
+ int quiet = 0;
+ const char *quiet_str = getenv("quiet");
/* at least two arguments please */
if (argc < 2)
goto usage;
+ if (quiet_str)
+ quiet = simple_strtoul(quiet_str, NULL, 0) != 0;
+
cmd = argv[1];
if (strcmp(cmd, "info") == 0) {
printf("Device %d: %s", dev, nand_info[dev].name);
puts("... is now current device\n");
nand_curr_device = dev;
+
+#ifdef CFG_NAND_SELECT_DEVICE
+ /*
+ * Select the chip in the board/cpu specific driver
+ */
+ board_nand_select_device(nand_info[dev].priv, dev);
+#endif
+
return 0;
}
if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 &&
strncmp(cmd, "dump", 4) != 0 &&
- strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0)
+ strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 &&
+ strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 &&
+ strcmp(cmd, "biterr") != 0 &&
+ strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 )
goto usage;
/* the following commands operate on the current device */
return 0;
}
- if (strcmp(cmd, "erase") == 0) {
- arg_off_size(argc - 2, argv + 2, &off, &size, nand->size);
- if (off == 0 && size == 0)
+ /*
+ * Syntax is:
+ * 0 1 2 3 4
+ * nand erase [clean] [off size]
+ */
+ if (strcmp(cmd, "erase") == 0 || strcmp(cmd, "scrub") == 0) {
+ nand_erase_options_t opts;
+ /* "clean" at index 2 means request to write cleanmarker */
+ int clean = argc > 2 && !strcmp("clean", argv[2]);
+ int o = clean ? 3 : 2;
+ int scrub = !strcmp(cmd, "scrub");
+
+ printf("\nNAND %s: ", scrub ? "scrub" : "erase");
+ /* skip first two or three arguments, look for offset and size */
+ if (arg_off_size(argc - o, argv + o, nand, &off, &size) != 0)
return 1;
- printf("\nNAND erase: device %d offset 0x%x, size 0x%x ",
- nand_curr_device, off, size);
- ret = nand_erase(nand, off, size);
+ memset(&opts, 0, sizeof(opts));
+ opts.offset = off;
+ opts.length = size;
+ opts.jffs2 = clean;
+ opts.quiet = quiet;
+
+ if (scrub) {
+ puts("Warning: "
+ "scrub option will erase all factory set "
+ "bad blocks!\n"
+ " "
+ "There is no reliable way to recover them.\n"
+ " "
+ "Use this command only for testing purposes "
+ "if you\n"
+ " "
+ "are sure of what you are doing!\n"
+ "\nReally scrub this NAND flash? <y/N>\n");
+
+ if (getc() == 'y' && getc() == '\r') {
+ opts.scrub = 1;
+ } else {
+ puts("scrub aborted\n");
+ return -1;
+ }
+ }
+ ret = nand_erase_opts(nand, &opts);
printf("%s\n", ret ? "ERROR" : "OK");
return ret == 0 ? 0 : 1;
/* read write */
if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
+ int read;
+
if (argc < 4)
goto usage;
-/*
- s = strchr(cmd, '.');
- clean = CLEAN_NONE;
- if (s != NULL) {
- if (strcmp(s, ".jffs2") == 0 || strcmp(s, ".e") == 0
- || strcmp(s, ".i"))
- clean = CLEAN_JFFS2;
- }
-*/
+
addr = (ulong)simple_strtoul(argv[2], NULL, 16);
- arg_off_size(argc - 3, argv + 3, &off, &size, nand->size);
- if (off == 0 && size == 0)
+ read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
+ printf("\nNAND %s: ", read ? "read" : "write");
+ if (arg_off_size(argc - 3, argv + 3, nand, &off, &size) != 0)
return 1;
- i = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
- printf("\nNAND %s: device %d offset %u, size %u ... ",
- i ? "read" : "write", nand_curr_device, off, size);
-
- if (i)
- ret = nand_read(nand, off, &size, (u_char *)addr);
- else
- ret = nand_write(nand, off, &size, (u_char *)addr);
+ s = strchr(cmd, '.');
+ if (s != NULL &&
+ (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) {
+ if (read) {
+ /* read */
+ nand_read_options_t opts;
+ memset(&opts, 0, sizeof(opts));
+ opts.buffer = (u_char*) addr;
+ opts.length = size;
+ opts.offset = off;
+ opts.quiet = quiet;
+ ret = nand_read_opts(nand, &opts);
+ } else {
+ /* write */
+ nand_write_options_t opts;
+ memset(&opts, 0, sizeof(opts));
+ opts.buffer = (u_char*) addr;
+ opts.length = size;
+ opts.offset = off;
+ /* opts.forcejffs2 = 1; */
+ opts.pad = 1;
+ opts.blockalign = 1;
+ opts.quiet = quiet;
+ ret = nand_write_opts(nand, &opts);
+ }
+ } else {
+ if (read)
+ ret = nand_read(nand, off, &size, (u_char *)addr);
+ else
+ ret = nand_write(nand, off, &size, (u_char *)addr);
+ }
printf(" %d bytes %s: %s\n", size,
- i ? "read" : "written", ret ? "ERROR" : "OK");
+ read ? "read" : "written", ret ? "ERROR" : "OK");
return ret == 0 ? 0 : 1;
}
+
+ if (strcmp(cmd, "markbad") == 0) {
+ addr = (ulong)simple_strtoul(argv[2], NULL, 16);
+
+ int ret = nand->block_markbad(nand, addr);
+ if (ret == 0) {
+ printf("block 0x%08lx successfully marked as bad\n",
+ (ulong) addr);
+ return 0;
+ } else {
+ printf("block 0x%08lx NOT marked as bad! ERROR %d\n",
+ (ulong) addr, ret);
+ }
+ return 1;
+ }
+ if (strcmp(cmd, "biterr") == 0) {
+ /* todo */
+ return 1;
+ }
+
+ if (strcmp(cmd, "lock") == 0) {
+ int tight = 0;
+ int status = 0;
+ if (argc == 3) {
+ if (!strcmp("tight", argv[2]))
+ tight = 1;
+ if (!strcmp("status", argv[2]))
+ status = 1;
+ }
+
+ if (status) {
+ ulong block_start = 0;
+ ulong off;
+ int last_status = -1;
+
+ struct nand_chip *nand_chip = nand->priv;
+ /* check the WP bit */
+ nand_chip->cmdfunc (nand, NAND_CMD_STATUS, -1, -1);
+ printf("device is %swrite protected\n",
+ (nand_chip->read_byte(nand) & 0x80 ?
+ "NOT " : "" ) );
+
+ for (off = 0; off < nand->size; off += nand->oobblock) {
+ int s = nand_get_lock_status(nand, off);
+
+ /* print message only if status has changed
+ * or at end of chip
+ */
+ if (off == nand->size - nand->oobblock
+ || (s != last_status && off != 0)) {
+
+ printf("%08x - %08x: %8d pages %s%s%s\n",
+ block_start,
+ off-1,
+ (off-block_start)/nand->oobblock,
+ ((last_status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""),
+ ((last_status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""),
+ ((last_status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : ""));
+ }
+
+ last_status = s;
+ }
+ } else {
+ if (!nand_lock(nand, tight)) {
+ puts("NAND flash successfully locked\n");
+ } else {
+ puts("Error locking NAND flash\n");
+ return 1;
+ }
+ }
+ return 0;
+ }
+
+ if (strcmp(cmd, "unlock") == 0) {
+ if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0)
+ return 1;
+
+ if (!nand_unlock(nand, off, size)) {
+ puts("NAND flash successfully unlocked\n");
+ } else {
+ puts("Error unlocking NAND flash, "
+ "write and erase will probably fail\n");
+ return 1;
+ }
+ return 0;
+ }
+
usage:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
"nand - NAND sub-system\n",
"info - show available NAND devices\n"
"nand device [dev] - show or set current device\n"
- "nand read[.jffs2] - addr off size\n"
- "nand write[.jffs2] - addr off size - read/write `size' bytes starting\n"
+ "nand read[.jffs2] - addr off|partition size\n"
+ "nand write[.jffs2] - addr off|partiton size - read/write `size' bytes starting\n"
" at offset `off' to/from memory address `addr'\n"
"nand erase [clean] [off size] - erase `size' bytes from\n"
" offset `off' (entire device if not specified)\n"
"nand dump[.oob] off - dump page\n"
"nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n"
"nand markbad off - mark bad block at offset (UNSAFE)\n"
- "nand biterr off - make a bit error at offset (UNSAFE)\n");
+ "nand biterr off - make a bit error at offset (UNSAFE)\n"
+ "nand lock [tight] [status] - bring nand to lock state or display locked pages\n"
+ "nand unlock [offset] [size] - unlock section\n");
-int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
+ ulong offset, ulong addr, char *cmd)
{
- char *boot_device = NULL;
- char *ep;
- int dev;
int r;
- ulong addr, cnt, offset = 0;
+ char *ep;
+ ulong cnt;
image_header_t *hdr;
- nand_info_t *nand;
-
- switch (argc) {
- case 1:
- addr = CFG_LOAD_ADDR;
- boot_device = getenv("bootdevice");
- break;
- case 2:
- addr = simple_strtoul(argv[1], NULL, 16);
- boot_device = getenv("bootdevice");
- break;
- case 3:
- addr = simple_strtoul(argv[1], NULL, 16);
- boot_device = argv[2];
- break;
- case 4:
- addr = simple_strtoul(argv[1], NULL, 16);
- boot_device = argv[2];
- offset = simple_strtoul(argv[3], NULL, 16);
- break;
- default:
- printf("Usage:\n%s\n", cmdtp->usage);
- SHOW_BOOT_PROGRESS(-1);
- return 1;
- }
-
- if (!boot_device) {
- puts("\n** No boot device **\n");
- SHOW_BOOT_PROGRESS(-1);
- return 1;
- }
- dev = simple_strtoul(boot_device, &ep, 16);
-
- if (dev < 0 || dev >= CFG_MAX_NAND_DEVICE || !nand_info[dev].name) {
- printf("\n** Device %d not available\n", dev);
- SHOW_BOOT_PROGRESS(-1);
- return 1;
- }
-
- nand = &nand_info[dev];
- printf("\nLoading from device %d: %s (offset 0x%lx)\n",
- dev, nand->name, offset);
+ printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
cnt = nand->oobblock;
r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
- printf("** Read error on %d\n", dev);
+ puts("** Read error\n");
SHOW_BOOT_PROGRESS(-1);
return 1;
}
r = nand_read(nand, offset, &cnt, (u_char *) addr);
if (r) {
- printf("** Read error on %d\n", dev);
+ puts("** Read error\n");
SHOW_BOOT_PROGRESS(-1);
return 1;
}
char *local_args[2];
extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
- local_args[0] = argv[0];
+ local_args[0] = cmd;
local_args[1] = NULL;
printf("Automatic boot of image at addr 0x%08lx ...\n", addr);
return 0;
}
-U_BOOT_CMD(nboot, 4, 1, do_nandboot,
- "nboot - boot from NAND device\n", "loadAddr dev\n");
+int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ char *boot_device = NULL;
+ int idx;
+ ulong addr, offset = 0;
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+ struct mtd_device *dev;
+ struct part_info *part;
+ u8 pnum;
+
+ if (argc >= 2) {
+ char *p = (argc == 2) ? argv[1] : argv[2];
+ if (!(str2long(p, &addr)) && (mtdparts_init() == 0) &&
+ (find_dev_and_part(p, &dev, &pnum, &part) == 0)) {
+ if (dev->id->type != MTD_DEV_TYPE_NAND) {
+ puts("Not a NAND device\n");
+ return 1;
+ }
+ if (argc > 3)
+ goto usage;
+ if (argc == 3)
+ addr = simple_strtoul(argv[2], NULL, 16);
+ else
+ addr = CFG_LOAD_ADDR;
+ return nand_load_image(cmdtp, &nand_info[dev->id->num],
+ part->offset, addr, argv[0]);
+ }
+ }
+#endif
+ switch (argc) {
+ case 1:
+ addr = CFG_LOAD_ADDR;
+ boot_device = getenv("bootdevice");
+ break;
+ case 2:
+ addr = simple_strtoul(argv[1], NULL, 16);
+ boot_device = getenv("bootdevice");
+ break;
+ case 3:
+ addr = simple_strtoul(argv[1], NULL, 16);
+ boot_device = argv[2];
+ break;
+ case 4:
+ addr = simple_strtoul(argv[1], NULL, 16);
+ boot_device = argv[2];
+ offset = simple_strtoul(argv[3], NULL, 16);
+ break;
+ default:
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+usage:
+#endif
+ printf("Usage:\n%s\n", cmdtp->usage);
+ SHOW_BOOT_PROGRESS(-1);
+ return 1;
+ }
+
+ if (!boot_device) {
+ puts("\n** No boot device **\n");
+ SHOW_BOOT_PROGRESS(-1);
+ return 1;
+ }
+
+ idx = simple_strtoul(boot_device, NULL, 16);
+
+ if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) {
+ printf("\n** Device %d not available\n", idx);
+ SHOW_BOOT_PROGRESS(-1);
+ return 1;
+ }
+
+ return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]);
+}
+
+U_BOOT_CMD(nboot, 4, 1, do_nandboot,
+ "nboot - boot from NAND device\n",
+ "[partition] | [[[loadAddr] dev] offset]\n");
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
return 1;
}
- printf ("\nNAND %s: device %d offset %ld, size %ld ... ",
+ printf ("\nNAND %s: device %d offset %ld, size %ld ...\n",
(cmd & NANDRW_READ) ? "read" : "write",
curr_device, off, size);
ulong size = simple_strtoul(argv[3 + clean], NULL, 16);
int ret;
- printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
+ printf ("\nNAND erase: device %d offset %ld, size %ld ...\n",
curr_device, off, size);
ret = nand_legacy_erase (nand_dev_desc + curr_device,
U_BOOT_CMD(
nand, 5, 1, do_nand,
- "nand - NAND sub-system\n",
+ "nand - legacy NAND sub-system\n",
"info - show available NAND devices\n"
"nand device [dev] - show or set current device\n"
"nand read[.jffs2[s]] addr off size\n"
name = argv[1];
+ if (strchr(name, '=')) {
+ printf ("## Error: illegal character '=' in variable name \"%s\"\n", name);
+ return 1;
+ }
+
/*
* search if variable with this name already exists
*/
#else
#define SCSI_DEV_ID CONFIG_SCSI_DEV_ID
#endif
+#elif defined CONFIG_SATA_ULI5288
+
+#define SCSI_VEND_ID 0x10b9
+#define SCSI_DEV_ID 0x5288
+
#else
-#error CONFIG_SCSI_SYM53C8XX must be defined
+#error no scsi device defined
#endif
* (C) Copyright 2004
* Jian Zhang, Texas Instruments, jzhang@ti.com.
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
/* local functions */
+#if !defined(ENV_IS_EMBEDDED)
static void use_default(void);
+#endif
DECLARE_GLOBAL_DATA_PTR;
* Mark it OK for now. env_relocate() in env_common.c
* will call our relocate function which will does
* the real validation.
+ *
+ * When using a NAND boot image (like sequoia_nand), the environment
+ * can be embedded or attached to the U-Boot image in NAND flash. This way
+ * the SPL loads not only the U-Boot image from NAND but also the
+ * environment.
*/
int env_init(void)
{
+#if defined(ENV_IS_EMBEDDED)
+ ulong total;
+ int crc1_ok = 0, crc2_ok = 0;
+ env_t *tmp_env1, *tmp_env2;
+
+ total = CFG_ENV_SIZE;
+
+ tmp_env1 = env_ptr;
+ tmp_env2 = (env_t *)((ulong)env_ptr + CFG_ENV_SIZE);
+
+ crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
+ crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
+
+ if (!crc1_ok && !crc2_ok)
+ gd->env_valid = 0;
+ else if(crc1_ok && !crc2_ok)
+ gd->env_valid = 1;
+ else if(!crc1_ok && crc2_ok)
+ gd->env_valid = 2;
+ else {
+ /* both ok - check serial */
+ if(tmp_env1->flags == 255 && tmp_env2->flags == 0)
+ gd->env_valid = 2;
+ else if(tmp_env2->flags == 255 && tmp_env1->flags == 0)
+ gd->env_valid = 1;
+ else if(tmp_env1->flags > tmp_env2->flags)
+ gd->env_valid = 1;
+ else if(tmp_env2->flags > tmp_env1->flags)
+ gd->env_valid = 2;
+ else /* flags are equal - almost impossible */
+ gd->env_valid = 1;
+ }
+
+ if (gd->env_valid == 1)
+ env_ptr = tmp_env1;
+ else if (gd->env_valid == 2)
+ env_ptr = tmp_env2;
+#else /* ENV_IS_EMBEDDED */
gd->env_addr = (ulong)&default_environment[0];
gd->env_valid = 1;
+#endif /* ENV_IS_EMBEDDED */
return (0);
}
}
#endif /* CFG_ENV_OFFSET_REDUND */
+#if !defined(ENV_IS_EMBEDDED)
static void use_default()
{
puts ("*** Warning - bad CRC or NAND, using default environment\n\n");
gd->env_valid = 1;
}
+#endif
#endif /* CFG_ENV_IS_IN_NAND */
defined(CONFIG_RRVISION) || \
defined(CONFIG_TRAB) || \
defined(CONFIG_PPCHAMELEONEVB) || \
- defined(CONFIG_M5271EVB)) && \
+ defined(CONFIG_M5271EVB) || \
+ defined(CONFIG_NAND_U_BOOT)) && \
defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
/* XXX - This only works with GNU C */
# define __PPCENV__ __attribute__ ((section(".ppcenv")))
gd->jt[XF_get_version] = (void *) get_version;
gd->jt[XF_malloc] = (void *) malloc;
gd->jt[XF_free] = (void *) free;
- gd->jt[XF_get_timer] = (void *)get_timer;
- gd->jt[XF_udelay] = (void *)udelay;
+ gd->jt[XF_getenv] = (void *) getenv;
+ gd->jt[XF_setenv] = (void *) setenv;
+ gd->jt[XF_get_timer] = (void *) get_timer;
+ gd->jt[XF_simple_strtoul] = (void *) simple_strtoul;
+ gd->jt[XF_udelay] = (void *) udelay;
#if defined(CONFIG_I386) || defined(CONFIG_PPC)
gd->jt[XF_install_hdlr] = (void *) irq_install_handler;
gd->jt[XF_free_hdlr] = (void *) irq_free_handler;
/*
* OF flat tree builder
+ * Written by: Pantelis Antoniou <pantelis.antoniou@gmail.com>
+ * Updated by: Matthew McClintock <msm@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
*/
#include <common.h>
#include <ft_build.h>
+#undef DEBUG
+
/* align addr on a size boundary - adjust address up if needed -- Cort */
#define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1)))
+#ifndef CONFIG_OF_BOOT_CPU
+#define CONFIG_OF_BOOT_CPU 0
+#endif
+#define SIZE_OF_RSVMAP_ENTRY (2*sizeof(u64))
static void ft_put_word(struct ft_cxt *cxt, u32 v)
{
- if (cxt->overflow) /* do nothing */
- return;
-
- /* check for overflow */
- if (cxt->p + 4 > cxt->pstr) {
- cxt->overflow = 1;
- return;
- }
+ memmove(cxt->p + sizeof(u32), cxt->p, cxt->p_end - cxt->p);
*(u32 *) cxt->p = cpu_to_be32(v);
- cxt->p += 4;
+ cxt->p += sizeof(u32);
+ cxt->p_end += sizeof(u32);
}
static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz)
{
- u8 *p;
+ int aligned_size = ((u8 *)_ALIGN((unsigned long)cxt->p + sz,
+ sizeof(u32))) - cxt->p;
- if (cxt->overflow) /* do nothing */
- return;
-
- /* next pointer pos */
- p = (u8 *) _ALIGN((unsigned long)cxt->p + sz, 4);
+ memmove(cxt->p + aligned_size, cxt->p, cxt->p_end - cxt->p);
- /* check for overflow */
- if (p > cxt->pstr) {
- cxt->overflow = 1;
- return;
- }
+ /* make sure the last bytes are zeroed */
+ memset(cxt->p + aligned_size - (aligned_size % sizeof(u32)), 0,
+ (aligned_size % sizeof(u32)));
memcpy(cxt->p, data, sz);
- if ((sz & 3) != 0)
- memset(cxt->p + sz, 0, 4 - (sz & 3));
- cxt->p = p;
+
+ cxt->p += aligned_size;
+ cxt->p_end += aligned_size;
}
void ft_begin_node(struct ft_cxt *cxt, const char *name)
{
u8 *p;
- p = cxt->pstr;
- while (p < cxt->pstr_begin) {
- if (strcmp(p, name) == 0)
- return p - cxt->p_begin;
- p += strlen(p) + 1;
+ p = cxt->p;
+ while (p < cxt->p_end) {
+ if (strcmp((char *)p, name) == 0)
+ return p - cxt->p;
+ p += strlen((char *)p) + 1;
}
return -1;
void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz)
{
- int len, off;
-
- if (cxt->overflow)
- return;
-
- len = strlen(name) + 1;
+ int off = 0;
off = lookup_string(cxt, name);
if (off == -1) {
- /* check if we have space */
- if (cxt->p + 12 + sz + len > cxt->pstr) {
- cxt->overflow = 1;
- return;
- }
-
- cxt->pstr -= len;
- memcpy(cxt->pstr, name, len);
- off = cxt->pstr - cxt->p_begin;
+ memcpy(cxt->p_end, name, strlen(name) + 1);
+ off = cxt->p_end - cxt->p;
+ cxt->p_end += strlen(name) + 1;
}
/* now put offset from beginning of *STRUCTURE* */
{
u32 v = cpu_to_be32((u32) val);
- ft_prop(cxt, name, &v, 4);
+ ft_prop(cxt, name, &v, sizeof(u32));
}
-/* start construction of the flat OF tree */
-void ft_begin(struct ft_cxt *cxt, void *blob, int max_size)
+/* pick up and start working on a tree in place */
+void ft_init_cxt(struct ft_cxt *cxt, void *blob)
{
struct boot_param_header *bph = blob;
- u32 off;
- /* clear the cxt */
memset(cxt, 0, sizeof(*cxt));
cxt->bph = bph;
- cxt->max_size = max_size;
-
- /* zero everything in the header area */
- memset(bph, 0, sizeof(*bph));
-
- bph->magic = cpu_to_be32(OF_DT_HEADER);
- bph->version = cpu_to_be32(0x10);
- bph->last_comp_version = cpu_to_be32(0x10);
+ bph->boot_cpuid_phys = CONFIG_OF_BOOT_CPU;
- /* start pointers */
- cxt->pres_begin = (u8 *) _ALIGN((unsigned long)(bph + 1), 8);
- cxt->pres = cxt->pres_begin;
-
- off = (unsigned long)cxt->pres_begin - (unsigned long)bph;
- bph->off_mem_rsvmap = cpu_to_be32(off);
-
- ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
- ((u64 *) cxt->pres)[1] = 0;
+ /* find beginning and end of reserve map table (zeros in last entry) */
+ cxt->p_rsvmap = (u8 *)bph + bph->off_mem_rsvmap;
+ while ( ((uint64_t *)cxt->p_rsvmap)[0] != 0 &&
+ ((uint64_t *)cxt->p_rsvmap)[1] != 0 ) {
+ cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY;
+ }
- cxt->p_anchor = cxt->pres + 16; /* over the terminator */
+ cxt->p_start = (u8 *)bph + bph->off_dt_struct;
+ cxt->p_end = (u8 *)bph + bph->totalsize;
+ cxt->p = (u8 *)bph + bph->off_dt_strings;
}
/* add a reserver physical area to the rsvmap */
-void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size)
+void ft_add_rsvmap(struct ft_cxt *cxt, u64 physstart, u64 physend)
{
- ((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */
- ((u64 *) cxt->pres)[1] = cpu_to_be64(size);
-
- cxt->pres += 16; /* advance */
-
- ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */
- ((u64 *) cxt->pres)[1] = 0;
-
- /* keep track of size */
- cxt->res_size = cxt->pres + 16 - cxt->pres_begin;
-
- cxt->p_anchor = cxt->pres + 16; /* over the terminator */
+ memmove(cxt->p_rsvmap + SIZE_OF_RSVMAP_ENTRY, cxt->p_rsvmap,
+ cxt->p_end - cxt->p_rsvmap);
+
+ ((u64 *)cxt->p_rsvmap)[0] = cpu_to_be64(physstart);
+ ((u64 *)cxt->p_rsvmap)[1] = cpu_to_be64(physend);
+ ((u64 *)cxt->p_rsvmap)[2] = 0;
+ ((u64 *)cxt->p_rsvmap)[3] = 0;
+
+ cxt->p_rsvmap += SIZE_OF_RSVMAP_ENTRY;
+ cxt->p_start += SIZE_OF_RSVMAP_ENTRY;
+ cxt->p += SIZE_OF_RSVMAP_ENTRY;
+ cxt->p_end += SIZE_OF_RSVMAP_ENTRY;
}
-void ft_begin_tree(struct ft_cxt *cxt)
+void ft_end_tree(struct ft_cxt *cxt)
{
- cxt->p_begin = cxt->p_anchor;
- cxt->pstr_begin = (char *)cxt->bph + cxt->max_size; /* point at the end */
-
- cxt->p = cxt->p_begin;
- cxt->pstr = cxt->pstr_begin;
+ ft_put_word(cxt, OF_DT_END);
}
-int ft_end_tree(struct ft_cxt *cxt)
-{
+/* update the boot param header with correct values */
+void ft_finalize_tree(struct ft_cxt *cxt) {
struct boot_param_header *bph = cxt->bph;
- int off, sz, sz1;
- u32 tag, v;
- u8 *p;
-
- ft_put_word(cxt, OF_DT_END);
-
- if (cxt->overflow)
- return -ENOMEM;
-
- /* size of the areas */
- cxt->struct_size = cxt->p - cxt->p_begin;
- cxt->strings_size = cxt->pstr_begin - cxt->pstr;
-
- /* the offset we must move */
- off = (cxt->pstr_begin - cxt->p_begin) - cxt->strings_size;
-
- /* the new strings start */
- cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
-
- /* move the whole string area */
- memmove(cxt->pstr_begin, cxt->pstr, cxt->strings_size);
- /* now perform the fixup of the strings */
- p = cxt->p_begin;
- while ((tag = be32_to_cpu(*(u32 *) p)) != OF_DT_END) {
- p += 4;
-
- if (tag == OF_DT_BEGIN_NODE) {
- p = (u8 *) _ALIGN((unsigned long)p + strlen(p) + 1, 4);
- continue;
- }
-
- if (tag == OF_DT_END_NODE || tag == OF_DT_NOP)
- continue;
-
- if (tag != OF_DT_PROP)
- return -EINVAL;
-
- sz = be32_to_cpu(*(u32 *) p);
- p += 4;
-
- v = be32_to_cpu(*(u32 *) p);
- v -= off;
- *(u32 *) p = cpu_to_be32(v); /* move down */
- p += 4;
-
- p = (u8 *) _ALIGN((unsigned long)p + sz, 4);
- }
-
- /* fix sizes */
- p = (char *)cxt->bph;
- sz = (cxt->pstr_begin + cxt->strings_size) - p;
- sz1 = _ALIGN(sz, 16); /* align at 16 bytes */
- if (sz != sz1)
- memset(p + sz, 0, sz1 - sz);
- bph->totalsize = cpu_to_be32(sz1);
- bph->off_dt_struct = cpu_to_be32(cxt->p_begin - p);
- bph->off_dt_strings = cpu_to_be32(cxt->pstr_begin - p);
-
- /* the new strings start */
- cxt->pstr_begin = cxt->p_begin + cxt->struct_size;
- cxt->pstr = cxt->pstr_begin + cxt->strings_size;
-
- return 0;
+ bph->totalsize = cxt->p_end - (u8 *)bph;
+ bph->off_dt_struct = cxt->p_start - (u8 *)bph;
+ bph->off_dt_strings = cxt->p - (u8 *)bph;
+ bph->dt_strings_size = cxt->p_end - cxt->p;
}
-/**********************************************************************/
-
static inline int isprint(int c)
{
return c >= 0x20 && c <= 0x7e;
return;
if (is_printable_string(data, len)) {
- printf(" = \"%s\"", (char *)data);
+ puts(" = \"");
+ puts(data);
+ puts("\"");
return;
}
switch (len) {
case 1: /* byte */
- printf(" = <0x%02x>", (*(u8 *) data) & 0xff);
+ printf(" = <%02x>", (*(u8 *) data) & 0xff);
break;
case 2: /* half-word */
- printf(" = <0x%04x>", be16_to_cpu(*(u16 *) data) & 0xffff);
+ printf(" = <%04x>", be16_to_cpu(*(u16 *) data) & 0xffff);
break;
case 4: /* word */
- printf(" = <0x%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
+ printf(" = <%x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU);
break;
case 8: /* double-word */
- printf(" = <0x%16llx>", be64_to_cpu(*(uint64_t *) data));
+ printf(" = <%qx>", be64_to_cpu(*(uint64_t *) data));
break;
default: /* anything else... hexdump */
printf(" = [");
if (addr == 0 && size == 0)
break;
- printf("/memreserve/ 0x%llx 0x%llx;\n", addr, size);
+ printf("/memreserve/ %qx %qx;\n", addr, size);
}
p = p_struct;
}
if (tag != OF_DT_PROP) {
- fprintf(stderr, "%*s ** Unknown tag 0x%08x\n",
- depth * shift, "", tag);
+ fprintf(stderr, "%*s ** Unknown tag 0x%08x at 0x%x\n",
+ depth * shift, "", tag, --p);
break;
}
sz = be32_to_cpu(*p++);
void ft_backtrack_node(struct ft_cxt *cxt)
{
- if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
- return; /* XXX only for node */
-
- cxt->p -= 4;
-}
-
-/* note that the root node of the blob is "peeled" off */
-void ft_merge_blob(struct ft_cxt *cxt, void *blob)
-{
- struct boot_param_header *bph = (struct boot_param_header *)blob;
- u32 *p_struct = (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct));
- u32 *p_strings =
- (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings));
- u32 tag, *p;
- char *s, *t;
- int depth, sz;
-
- if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE)
- return; /* XXX only for node */
-
- cxt->p -= 4;
-
- depth = 0;
- p = p_struct;
- while ((tag = be32_to_cpu(*p++)) != OF_DT_END) {
-
- /* printf("tag: 0x%08x (%d) - %d\n", tag, p - p_struct, depth); */
-
- if (tag == OF_DT_BEGIN_NODE) {
- s = (char *)p;
- p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4);
-
- if (depth++ > 0)
- ft_begin_node(cxt, s);
-
- continue;
- }
-
- if (tag == OF_DT_END_NODE) {
- ft_end_node(cxt);
- if (--depth == 0)
- break;
- continue;
- }
-
- if (tag == OF_DT_NOP)
- continue;
+ int i = 4;
- if (tag != OF_DT_PROP)
- break;
+ while (be32_to_cpu(*(u32 *) (cxt->p - i)) != OF_DT_END_NODE)
+ i += 4;
- sz = be32_to_cpu(*p++);
- s = (char *)p_strings + be32_to_cpu(*p++);
- t = (char *)p;
- p = (u32 *) _ALIGN((unsigned long)p + sz, 4);
+ memmove (cxt->p - i, cxt->p, cxt->p_end - cxt->p);
- ft_prop(cxt, s, t, sz);
- }
+ cxt->p_end -= i;
+ cxt->p -= i;
}
void *ft_get_prop(void *bphp, const char *propname, int *szp)
/********************************************************************/
-extern unsigned char oftree_dtb[];
-extern unsigned int oftree_dtb_len;
-
/* Function that returns a character from the environment */
extern uchar(*env_get_char) (int);
};
#endif
-void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end)
+void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end)
{
u32 *p;
int len;
return;
}
- ft_begin(&cxt, blob, size);
+#ifdef DEBUG
+ printf ("recieved oftree\n");
+ ft_dump_blob(blob);
+#endif
+
+ ft_init_cxt(&cxt, blob);
if (initrd_start && initrd_end)
ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1);
- ft_begin_tree(&cxt);
-
- ft_begin_node(&cxt, "");
-
- ft_end_node(&cxt);
-
- /* copy RO tree */
- ft_merge_blob(&cxt, oftree_dtb);
-
/* back into root */
ft_backtrack_node(&cxt);
#endif
ft_begin_node(&cxt, "chosen");
-
ft_prop_str(&cxt, "name", "chosen");
+
ft_prop_str(&cxt, "bootargs", getenv("bootargs"));
ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */
if (initrd_start && initrd_end) {
ft_end_node(&cxt); /* end root */
ft_end_tree(&cxt);
-
- /*
- printf("merged OF-tree\n");
- ft_dump_blob(blob);
- */
+ ft_finalize_tree(&cxt);
#ifdef CONFIG_OF_HAS_BD_T
/* paste the bd_t at the end of the flat tree */
ft_board_setup(blob, bd);
#endif
- /*
- printf("final OF-tree\n");
- ft_dump_blob(blob);
- */
+ /* in case the size changed in the platform code */
+ ft_finalize_tree(&cxt);
+#ifdef DEBUG
+ printf("final OF-tree\n");
+ ft_dump_blob(blob);
+#endif
}
-
#endif
*/
int lcd_display_bitmap(ulong bmp_image, int x, int y)
{
+#if !defined(CONFIG_MCC200)
ushort *cmap;
+#endif
ushort i, j;
uchar *fb;
bmp_image_t *bmp=(bmp_image_t *)bmp_image;
uchar *bmap;
ushort padded_line;
unsigned long width, height;
+ unsigned long pwidth = panel_info.vl_col;
unsigned colors,bpix;
unsigned long compression;
#if defined(CONFIG_PXA250)
debug ("Display-bmp: %d x %d with %d colors\n",
(int)width, (int)height, (int)colors);
+#if !defined(CONFIG_MCC200)
+ /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
if (bpix==8) {
#if defined(CONFIG_PXA250)
cmap = (ushort *)fbi->palette;
#endif
}
}
+#endif
+
+ /*
+ * BMP format for Monochrome assumes that the state of a
+ * pixel is described on a per Bit basis, not per Byte.
+ * So, in case of Monochrome BMP we should align widths
+ * on a byte boundary and convert them from Bit to Byte
+ * units.
+ * Probably, PXA250 and MPC823 process 1bpp BMP images in
+ * their own ways, so make the converting to be MCC200
+ * specific.
+ */
+#if defined(CONFIG_MCC200)
+ if (bpix==1)
+ {
+ width = ((width + 7) & ~7) >> 3;
+ x = ((x + 7) & ~7) >> 3;
+ pwidth= ((pwidth + 7) & ~7) >> 3;
+ }
+#endif
padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
- if ((x + width)>panel_info.vl_col)
- width = panel_info.vl_col - x;
+ if ((x + width)>pwidth)
+ width = pwidth - x;
if ((y + height)>panel_info.vl_row)
height = panel_info.vl_row - y;
for (j = 0; j < width ; j++)
#if defined(CONFIG_PXA250)
*(fb++)=*(bmap++);
-#elif defined(CONFIG_MPC823)
+#elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
*(fb++)=255-*(bmap++);
#endif
bmap += (width - padded_line);
{
int abort = 0;
uint64_t etime = endtick(bootdelay);
- struct
- {
+ struct {
char* str;
u_int len;
int retry;
}
- delaykey [] =
- {
+ delaykey [] = {
{ str: getenv ("bootdelaykey"), retry: 1 },
{ str: getenv ("bootdelaykey2"), retry: 1 },
{ str: getenv ("bootstopkey"), retry: 0 },
#ifdef CONFIG_BOOT_RETRY_TIME
/***************************************************************************
- * initialise command line timeout
+ * initialize command line timeout
*/
void init_cmd_timeout(void)
{
* Author: Janghoon Lyu <nandy@mizi.com>
*/
-#if 1 /* avoid redundand code -- wd */
#define putnstr(str,n) do { \
printf ("%.*s", n, str); \
} while (0)
-#else
-void putnstr(const char *str, size_t n)
-{
- if (str == NULL)
- return;
-
- while (n && *str != '\0') {
- putc(*str);
- str++;
- n--;
- }
-}
-#endif
#define CTL_CH(c) ((c) - 'a' + 1)
#ifdef CONFIG_CMDLINE_EDITING
char *p = console_buffer;
unsigned int len=MAX_CMDBUF_SIZE;
+ int rc;
static int initted = 0;
if (!initted) {
puts (prompt);
- cread_line(p, &len);
- return len;
+ rc = cread_line(p, &len);
+ return rc < 0 ? rc : len;
#else
char *p = console_buffer;
int n = 0; /* buffer index */
{
char c, prev;
const char *varname_start = NULL;
- int inputcnt = strlen (input);
+ int inputcnt = strlen (input);
int outputcnt = CFG_CBSIZE;
- int state = 0; /* 0 = waiting for '$' */
- /* 1 = waiting for '(' or '{' */
- /* 2 = waiting for ')' or '}' */
- /* 3 = waiting for ''' */
+ int state = 0; /* 0 = waiting for '$' */
+
+ /* 1 = waiting for '(' or '{' */
+ /* 2 = waiting for ')' or '}' */
+ /* 3 = waiting for ''' */
#ifdef DEBUG_PARSER
char *output_start = output;
- printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen(input), input);
+ printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen (input),
+ input);
#endif
- prev = '\0'; /* previous character */
+ prev = '\0'; /* previous character */
while (inputcnt && outputcnt) {
- c = *input++;
- inputcnt--;
-
- if (state!=3) {
- /* remove one level of escape characters */
- if ((c == '\\') && (prev != '\\')) {
- if (inputcnt-- == 0)
- break;
- prev = c;
c = *input++;
- }
- }
-
- switch (state) {
- case 0: /* Waiting for (unescaped) $ */
- if ((c == '\'') && (prev != '\\')) {
- state = 3;
- break;
- }
- if ((c == '$') && (prev != '\\')) {
- state++;
- } else {
- *(output++) = c;
- outputcnt--;
+ inputcnt--;
+
+ if (state != 3) {
+ /* remove one level of escape characters */
+ if ((c == '\\') && (prev != '\\')) {
+ if (inputcnt-- == 0)
+ break;
+ prev = c;
+ c = *input++;
+ }
}
- break;
- case 1: /* Waiting for ( */
- if (c == '(' || c == '{') {
- state++;
- varname_start = input;
- } else {
- state = 0;
- *(output++) = '$';
- outputcnt--;
-
- if (outputcnt) {
+
+ switch (state) {
+ case 0: /* Waiting for (unescaped) $ */
+ if ((c == '\'') && (prev != '\\')) {
+ state = 3;
+ break;
+ }
+ if ((c == '$') && (prev != '\\')) {
+ state++;
+ } else {
*(output++) = c;
outputcnt--;
}
- }
- break;
- case 2: /* Waiting for ) */
- if (c == ')' || c == '}') {
- int i;
- char envname[CFG_CBSIZE], *envval;
- int envcnt = input-varname_start-1; /* Varname # of chars */
-
- /* Get the varname */
- for (i = 0; i < envcnt; i++) {
- envname[i] = varname_start[i];
- }
- envname[i] = 0;
-
- /* Get its value */
- envval = getenv (envname);
+ break;
+ case 1: /* Waiting for ( */
+ if (c == '(' || c == '{') {
+ state++;
+ varname_start = input;
+ } else {
+ state = 0;
+ *(output++) = '$';
+ outputcnt--;
- /* Copy into the line if it exists */
- if (envval != NULL)
- while ((*envval) && outputcnt) {
- *(output++) = *(envval++);
+ if (outputcnt) {
+ *(output++) = c;
outputcnt--;
}
- /* Look for another '$' */
- state = 0;
- }
- break;
- case 3: /* Waiting for ' */
- if ((c == '\'') && (prev != '\\')) {
- state = 0;
- } else {
- *(output++) = c;
- outputcnt--;
+ }
+ break;
+ case 2: /* Waiting for ) */
+ if (c == ')' || c == '}') {
+ int i;
+ char envname[CFG_CBSIZE], *envval;
+ int envcnt = input - varname_start - 1; /* Varname # of chars */
+
+ /* Get the varname */
+ for (i = 0; i < envcnt; i++) {
+ envname[i] = varname_start[i];
+ }
+ envname[i] = 0;
+
+ /* Get its value */
+ envval = getenv (envname);
+
+ /* Copy into the line if it exists */
+ if (envval != NULL)
+ while ((*envval) && outputcnt) {
+ *(output++) = *(envval++);
+ outputcnt--;
+ }
+ /* Look for another '$' */
+ state = 0;
+ }
+ break;
+ case 3: /* Waiting for ' */
+ if ((c == '\'') && (prev != '\\')) {
+ state = 0;
+ } else {
+ *(output++) = c;
+ outputcnt--;
+ }
+ break;
}
- break;
- }
- prev = c;
+ prev = c;
}
if (outputcnt)
#ifdef DEBUG_PARSER
printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",
- strlen(output_start), output_start);
+ strlen (output_start), output_start);
#endif
}
* MA 02111-1307 USA
*/
+#include <config.h>
+#ifdef __PPC__
+/*
+ * At least on G2 PowerPC cores, sequential accesses to non-existent
+ * memory must be synchronized.
+ */
+# include <asm/io.h> /* for sync() */
+#else
+# define sync() /* nothing */
+#endif
/*
* Check memory range for valid RAM. A simple memory test determines
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
+ sync ();
save[i++] = *addr;
+ sync ();
*addr = ~cnt;
}
addr = base;
+ sync ();
save[i] = *addr;
+ sync ();
*addr = 0;
+ sync ();
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function.
*/
+ sync ();
*addr = save[i];
for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
addr = base + cnt;
+ sync ();
*addr = save[--i];
}
return (0);
static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
{
int j; /* counter */
-#ifndef CONFIG_EP8248
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
{
short rdreg; /* register working value */
int j; /* counter */
-#ifndef CONFIG_EP8248
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
unsigned char reg, unsigned short value)
{
int j; /* counter */
-#ifndef CONFIG_EP8248
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
-#if defined(CONFIG_UART1_CONSOLE)
+#if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL)
+#if (CONFIG_CONS_INDEX==1)
+ return &eserial1_device;
+#elif (CONFIG_CONS_INDEX==2)
+ return &eserial2_device;
+#elif (CONFIG_CONS_INDEX==3)
+ return &eserial3_device;
+#elif (CONFIG_CONS_INDEX==4)
+ return &eserial4_device;
+#else
+#error "Bad CONFIG_CONS_INDEX."
+#endif
+#elif defined(CONFIG_UART1_CONSOLE)
return &serial1_device;
#else
return &serial0_device;
serial_register(&serial1_device);
#endif
+#if defined(CFG_NS16550_SERIAL)
+#if defined(CFG_NS16550_COM1)
+ serial_register(&eserial1_device);
+#endif
+#if defined(CFG_NS16550_COM2)
+ serial_register(&eserial2_device);
+#endif
+#if defined(CFG_NS16550_COM3)
+ serial_register(&eserial3_device);
+#endif
+#if defined(CFG_NS16550_COM4)
+ serial_register(&eserial4_device);
+#endif
+#endif /* CFG_NS16550_SERIAL */
serial_assign (default_serial_console ()->name);
}
}
+#ifdef CONFIG_USB_BIN_FIXUP
+/*
+ * Some USB storage devices queried for SCSI identification data respond with
+ * binary strings, which if output to the console freeze the terminal. The
+ * workaround is to modify the vendor and product strings read from such
+ * device with proper values (as reported by 'usb info').
+ *
+ * Vendor and product length limits are taken from the definition of
+ * block_dev_desc_t in include/part.h.
+ */
+static void usb_bin_fixup(struct usb_device_descriptor descriptor,
+ unsigned char vendor[],
+ unsigned char product[]) {
+ const unsigned char max_vendor_len = 40;
+ const unsigned char max_product_len = 20;
+ if (descriptor.idVendor == 0x0424 && descriptor.idProduct == 0x223a) {
+ strncpy ((char *)vendor, "SMSC", max_vendor_len);
+ strncpy ((char *)product, "Flash Media Cntrller", max_product_len);
+ }
+}
+#endif /* CONFIG_USB_BIN_FIXUP */
+
#define USB_MAX_READ_BLK 20
unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, unsigned long *buffer)
dev_desc->vendor[8] = 0;
dev_desc->product[16] = 0;
dev_desc->revision[4] = 0;
+#ifdef CONFIG_USB_BIN_FIXUP
+ usb_bin_fixup(dev->descriptor, dev_desc->vendor, dev_desc->product);
+#endif /* CONFIG_USB_BIN_FIXUP */
USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n",usb_stor_buf[2],usb_stor_buf[3]);
if(usb_test_unit_ready(pccb,ss)) {
printf("Device NOT ready\n Request Sense returned %02X %02X %02X\n",pccb->sense_buf[2],pccb->sense_buf[12],pccb->sense_buf[13]);
#define BSP 0x08
#define NAK 0x15
#define CAN 0x18
-#define EOF 0x1A /* ^Z for DOS officionados */
+#define EOF 0x1A /* ^Z for DOS officionados */
#define USE_YMODEM_LENGTH
/* Data & state local to the protocol */
-static struct {
+static struct
+{
#ifdef REDBOOT
- hal_virtual_comm_table_t* __chan;
+ hal_virtual_comm_table_t *__chan;
#else
- int *__chan;
+ int *__chan;
#endif
- unsigned char pkt[1024], *bufp;
- unsigned char blk,cblk,crc1,crc2;
- unsigned char next_blk; /* Expected block */
- int len, mode, total_retries;
- int total_SOH, total_STX, total_CAN;
- bool crc_mode, at_eof, tx_ack;
+ unsigned char pkt[1024], *bufp;
+ unsigned char blk, cblk, crc1, crc2;
+ unsigned char next_blk; /* Expected block */
+ int len, mode, total_retries;
+ int total_SOH, total_STX, total_CAN;
+ bool crc_mode, at_eof, tx_ack;
#ifdef USE_YMODEM_LENGTH
- unsigned long file_length, read_length;
+ unsigned long file_length, read_length;
#endif
} xyz;
-#define xyzModem_CHAR_TIMEOUT 2000 /* 2 seconds */
+#define xyzModem_CHAR_TIMEOUT 2000 /* 2 seconds */
#define xyzModem_MAX_RETRIES 20
#define xyzModem_MAX_RETRIES_WITH_CRC 10
-#define xyzModem_CAN_COUNT 3 /* Wait for 3 CAN before quitting */
+#define xyzModem_CAN_COUNT 3 /* Wait for 3 CAN before quitting */
-#ifndef REDBOOT /*SB */
+#ifndef REDBOOT /*SB */
typedef int cyg_int32;
-int CYGACC_COMM_IF_GETC_TIMEOUT (char chan,char *c) {
+int
+CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c)
+{
#define DELAY 20
- unsigned long counter=0;
- while (!tstc() && (counter < xyzModem_CHAR_TIMEOUT*1000/DELAY)) {
- udelay(DELAY);
- counter++;
- }
- if (tstc()) {
- *c=getc();
- return 1;
- }
- return 0;
+ unsigned long counter = 0;
+ while (!tstc () && (counter < xyzModem_CHAR_TIMEOUT * 1000 / DELAY))
+ {
+ udelay (DELAY);
+ counter++;
+ }
+ if (tstc ())
+ {
+ *c = getc ();
+ return 1;
+ }
+ return 0;
}
-void CYGACC_COMM_IF_PUTC(char x,char y) {
- putc(y);
+void
+CYGACC_COMM_IF_PUTC (char x, char y)
+{
+ putc (y);
}
/* Validate a hex character */
__inline__ static bool
-_is_hex(char c)
+_is_hex (char c)
{
- return (((c >= '0') && (c <= '9')) ||
- ((c >= 'A') && (c <= 'F')) ||
- ((c >= 'a') && (c <= 'f')));
+ return (((c >= '0') && (c <= '9')) ||
+ ((c >= 'A') && (c <= 'F')) || ((c >= 'a') && (c <= 'f')));
}
/* Convert a single hex nibble */
__inline__ static int
-_from_hex(char c)
+_from_hex (char c)
{
- int ret = 0;
-
- if ((c >= '0') && (c <= '9')) {
- ret = (c - '0');
- } else if ((c >= 'a') && (c <= 'f')) {
- ret = (c - 'a' + 0x0a);
- } else if ((c >= 'A') && (c <= 'F')) {
- ret = (c - 'A' + 0x0A);
+ int ret = 0;
+
+ if ((c >= '0') && (c <= '9'))
+ {
+ ret = (c - '0');
+ }
+ else if ((c >= 'a') && (c <= 'f'))
+ {
+ ret = (c - 'a' + 0x0a);
}
- return ret;
+ else if ((c >= 'A') && (c <= 'F'))
+ {
+ ret = (c - 'A' + 0x0A);
+ }
+ return ret;
}
/* Convert a character to lower case */
__inline__ static char
-_tolower(char c)
+_tolower (char c)
{
- if ((c >= 'A') && (c <= 'Z')) {
- c = (c - 'A') + 'a';
+ if ((c >= 'A') && (c <= 'Z'))
+ {
+ c = (c - 'A') + 'a';
}
- return c;
+ return c;
}
/* Parse (scan) a number */
bool
-parse_num(char *s, unsigned long *val, char **es, char *delim)
+parse_num (char *s, unsigned long *val, char **es, char *delim)
{
- bool first = true;
- int radix = 10;
- char c;
- unsigned long result = 0;
- int digit;
-
- while (*s == ' ') s++;
- while (*s) {
- if (first && (s[0] == '0') && (_tolower(s[1]) == 'x')) {
- radix = 16;
- s += 2;
- }
- first = false;
- c = *s++;
- if (_is_hex(c) && ((digit = _from_hex(c)) < radix)) {
- /* Valid digit */
+ bool first = true;
+ int radix = 10;
+ char c;
+ unsigned long result = 0;
+ int digit;
+
+ while (*s == ' ')
+ s++;
+ while (*s)
+ {
+ if (first && (s[0] == '0') && (_tolower (s[1]) == 'x'))
+ {
+ radix = 16;
+ s += 2;
+ }
+ first = false;
+ c = *s++;
+ if (_is_hex (c) && ((digit = _from_hex (c)) < radix))
+ {
+ /* Valid digit */
#ifdef CYGPKG_HAL_MIPS
- /* FIXME: tx49 compiler generates 0x2539018 for MUL which */
- /* isn't any good. */
- if (16 == radix)
- result = result << 4;
- else
- result = 10 * result;
- result += digit;
+ /* FIXME: tx49 compiler generates 0x2539018 for MUL which */
+ /* isn't any good. */
+ if (16 == radix)
+ result = result << 4;
+ else
+ result = 10 * result;
+ result += digit;
#else
- result = (result * radix) + digit;
+ result = (result * radix) + digit;
#endif
- } else {
- if (delim != (char *)0) {
- /* See if this character is one of the delimiters */
- char *dp = delim;
- while (*dp && (c != *dp)) dp++;
- if (*dp) break; /* Found a good delimiter */
- }
- return false; /* Malformatted number */
- }
+ }
+ else
+ {
+ if (delim != (char *) 0)
+ {
+ /* See if this character is one of the delimiters */
+ char *dp = delim;
+ while (*dp && (c != *dp))
+ dp++;
+ if (*dp)
+ break; /* Found a good delimiter */
+ }
+ return false; /* Malformatted number */
+ }
}
- *val = result;
- if (es != (char **)0) {
- *es = s;
+ *val = result;
+ if (es != (char **) 0)
+ {
+ *es = s;
}
- return true;
+ return true;
}
#endif
* messages.
*/
static int
-zm_dprintf(char *fmt, ...)
+zm_dprintf (char *fmt, ...)
{
- int cur_console;
- va_list args;
+ int cur_console;
+ va_list args;
- va_start(args, fmt);
+ va_start (args, fmt);
#ifdef REDBOOT
- cur_console = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
- CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
+ cur_console =
+ CYGACC_CALL_IF_SET_CONSOLE_COMM
+ (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM (1);
#endif
- diag_vprintf(fmt, args);
+ diag_vprintf (fmt, args);
#ifdef REDBOOT
- CYGACC_CALL_IF_SET_CONSOLE_COMM(cur_console);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM (cur_console);
#endif
}
static void
-zm_flush(void)
+zm_flush (void)
{
}
*/
#define FINAL
#ifdef FINAL
-static char *zm_out = (char *)0x00380000;
-static char *zm_out_start = (char *)0x00380000;
+static char *zm_out = (char *) 0x00380000;
+static char *zm_out_start = (char *) 0x00380000;
#else
static char zm_buf[8192];
-static char *zm_out=zm_buf;
+static char *zm_out = zm_buf;
static char *zm_out_start = zm_buf;
#endif
static int
-zm_dprintf(char *fmt, ...)
+zm_dprintf (char *fmt, ...)
{
- int len;
- va_list args;
+ int len;
+ va_list args;
- va_start(args, fmt);
- len = diag_vsprintf(zm_out, fmt, args);
- zm_out += len;
- return len;
+ va_start (args, fmt);
+ len = diag_vsprintf (zm_out, fmt, args);
+ zm_out += len;
+ return len;
}
static void
-zm_flush(void)
+zm_flush (void)
{
#ifdef REDBOOT
- char *p = zm_out_start;
- while (*p) mon_write_char(*p++);
+ char *p = zm_out_start;
+ while (*p)
+ mon_write_char (*p++);
#endif
- zm_out = zm_out_start;
+ zm_out = zm_out_start;
}
#endif
static void
-zm_dump_buf(void *buf, int len)
+zm_dump_buf (void *buf, int len)
{
#ifdef REDBOOT
- diag_vdump_buf_with_offset(zm_dprintf, buf, len, 0);
+ diag_vdump_buf_with_offset (zm_dprintf, buf, len, 0);
#else
#endif
static unsigned char *zm_bp;
static void
-zm_new(void)
+zm_new (void)
{
- zm_bp = zm_buf;
+ zm_bp = zm_buf;
}
static void
-zm_save(unsigned char c)
+zm_save (unsigned char c)
{
- *zm_bp++ = c;
+ *zm_bp++ = c;
}
static void
-zm_dump(int line)
+zm_dump (int line)
{
- zm_dprintf("Packet at line: %d\n", line);
- zm_dump_buf(zm_buf, zm_bp-zm_buf);
+ zm_dprintf ("Packet at line: %d\n", line);
+ zm_dump_buf (zm_buf, zm_bp - zm_buf);
}
#define ZM_DEBUG(x) x
/* Wait for the line to go idle */
static void
-xyzModem_flush(void)
+xyzModem_flush (void)
{
- int res;
- char c;
- while (true) {
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c);
- if (!res) return;
+ int res;
+ char c;
+ while (true)
+ {
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, &c);
+ if (!res)
+ return;
}
}
static int
-xyzModem_get_hdr(void)
+xyzModem_get_hdr (void)
{
- char c;
- int res;
- bool hdr_found = false;
- int i, can_total, hdr_chars;
- unsigned short cksum;
-
- ZM_DEBUG(zm_new());
- /* Find the start of a header */
- can_total = 0;
- hdr_chars = 0;
-
- if (xyz.tx_ack) {
- CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
- xyz.tx_ack = false;
+ char c;
+ int res;
+ bool hdr_found = false;
+ int i, can_total, hdr_chars;
+ unsigned short cksum;
+
+ ZM_DEBUG (zm_new ());
+ /* Find the start of a header */
+ can_total = 0;
+ hdr_chars = 0;
+
+ if (xyz.tx_ack)
+ {
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK);
+ xyz.tx_ack = false;
}
- while (!hdr_found) {
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c);
- ZM_DEBUG(zm_save(c));
- if (res) {
- hdr_chars++;
- switch (c) {
- case SOH:
- xyz.total_SOH++;
- case STX:
- if (c == STX) xyz.total_STX++;
- hdr_found = true;
- break;
- case CAN:
- xyz.total_CAN++;
- ZM_DEBUG(zm_dump(__LINE__));
- if (++can_total == xyzModem_CAN_COUNT) {
- return xyzModem_cancel;
- } else {
- /* Wait for multiple CAN to avoid early quits */
- break;
- }
- case EOT:
- /* EOT only supported if no noise */
- if (hdr_chars == 1) {
- CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
- ZM_DEBUG(zm_dprintf("ACK on EOT #%d\n", __LINE__));
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_eof;
- }
- default:
- /* Ignore, waiting for start of header */
- ;
- }
- } else {
- /* Data stream timed out */
- xyzModem_flush(); /* Toss any current input */
- ZM_DEBUG(zm_dump(__LINE__));
- CYGACC_CALL_IF_DELAY_US((cyg_int32)250000);
- return xyzModem_timeout;
- }
+ while (!hdr_found)
+ {
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, &c);
+ ZM_DEBUG (zm_save (c));
+ if (res)
+ {
+ hdr_chars++;
+ switch (c)
+ {
+ case SOH:
+ xyz.total_SOH++;
+ case STX:
+ if (c == STX)
+ xyz.total_STX++;
+ hdr_found = true;
+ break;
+ case CAN:
+ xyz.total_CAN++;
+ ZM_DEBUG (zm_dump (__LINE__));
+ if (++can_total == xyzModem_CAN_COUNT)
+ {
+ return xyzModem_cancel;
+ }
+ else
+ {
+ /* Wait for multiple CAN to avoid early quits */
+ break;
+ }
+ case EOT:
+ /* EOT only supported if no noise */
+ if (hdr_chars == 1)
+ {
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK);
+ ZM_DEBUG (zm_dprintf ("ACK on EOT #%d\n", __LINE__));
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_eof;
+ }
+ default:
+ /* Ignore, waiting for start of header */
+ ;
+ }
+ }
+ else
+ {
+ /* Data stream timed out */
+ xyzModem_flush (); /* Toss any current input */
+ ZM_DEBUG (zm_dump (__LINE__));
+ CYGACC_CALL_IF_DELAY_US ((cyg_int32) 250000);
+ return xyzModem_timeout;
+ }
}
- /* Header found, now read the data */
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.blk);
- ZM_DEBUG(zm_save(xyz.blk));
- if (!res) {
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_timeout;
+ /* Header found, now read the data */
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.blk);
+ ZM_DEBUG (zm_save (xyz.blk));
+ if (!res)
+ {
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_timeout;
}
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.cblk);
- ZM_DEBUG(zm_save(xyz.cblk));
- if (!res) {
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_timeout;
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.cblk);
+ ZM_DEBUG (zm_save (xyz.cblk));
+ if (!res)
+ {
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_timeout;
}
- xyz.len = (c == SOH) ? 128 : 1024;
- xyz.bufp = xyz.pkt;
- for (i = 0; i < xyz.len; i++) {
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c);
- ZM_DEBUG(zm_save(c));
- if (res) {
- xyz.pkt[i] = c;
- } else {
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_timeout;
- }
+ xyz.len = (c == SOH) ? 128 : 1024;
+ xyz.bufp = xyz.pkt;
+ for (i = 0; i < xyz.len; i++)
+ {
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, &c);
+ ZM_DEBUG (zm_save (c));
+ if (res)
+ {
+ xyz.pkt[i] = c;
+ }
+ else
+ {
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_timeout;
+ }
}
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.crc1);
- ZM_DEBUG(zm_save(xyz.crc1));
- if (!res) {
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_timeout;
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.crc1);
+ ZM_DEBUG (zm_save (xyz.crc1));
+ if (!res)
+ {
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_timeout;
}
- if (xyz.crc_mode) {
- res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.crc2);
- ZM_DEBUG(zm_save(xyz.crc2));
- if (!res) {
- ZM_DEBUG(zm_dump(__LINE__));
- return xyzModem_timeout;
- }
+ if (xyz.crc_mode)
+ {
+ res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.crc2);
+ ZM_DEBUG (zm_save (xyz.crc2));
+ if (!res)
+ {
+ ZM_DEBUG (zm_dump (__LINE__));
+ return xyzModem_timeout;
+ }
}
- ZM_DEBUG(zm_dump(__LINE__));
- /* Validate the message */
- if ((xyz.blk ^ xyz.cblk) != (unsigned char)0xFF) {
- ZM_DEBUG(zm_dprintf("Framing error - blk: %x/%x/%x\n", xyz.blk, xyz.cblk, (xyz.blk ^ xyz.cblk)));
- ZM_DEBUG(zm_dump_buf(xyz.pkt, xyz.len));
- xyzModem_flush();
- return xyzModem_frame;
+ ZM_DEBUG (zm_dump (__LINE__));
+ /* Validate the message */
+ if ((xyz.blk ^ xyz.cblk) != (unsigned char) 0xFF)
+ {
+ ZM_DEBUG (zm_dprintf
+ ("Framing error - blk: %x/%x/%x\n", xyz.blk, xyz.cblk,
+ (xyz.blk ^ xyz.cblk)));
+ ZM_DEBUG (zm_dump_buf (xyz.pkt, xyz.len));
+ xyzModem_flush ();
+ return xyzModem_frame;
}
- /* Verify checksum/CRC */
- if (xyz.crc_mode) {
- cksum = cyg_crc16(xyz.pkt, xyz.len);
- if (cksum != ((xyz.crc1 << 8) | xyz.crc2)) {
- ZM_DEBUG(zm_dprintf("CRC error - recvd: %02x%02x, computed: %x\n",
- xyz.crc1, xyz.crc2, cksum & 0xFFFF));
- return xyzModem_cksum;
- }
- } else {
- cksum = 0;
- for (i = 0; i < xyz.len; i++) {
- cksum += xyz.pkt[i];
- }
- if (xyz.crc1 != (cksum & 0xFF)) {
- ZM_DEBUG(zm_dprintf("Checksum error - recvd: %x, computed: %x\n", xyz.crc1, cksum & 0xFF));
- return xyzModem_cksum;
- }
+ /* Verify checksum/CRC */
+ if (xyz.crc_mode)
+ {
+ cksum = cyg_crc16 (xyz.pkt, xyz.len);
+ if (cksum != ((xyz.crc1 << 8) | xyz.crc2))
+ {
+ ZM_DEBUG (zm_dprintf ("CRC error - recvd: %02x%02x, computed: %x\n",
+ xyz.crc1, xyz.crc2, cksum & 0xFFFF));
+ return xyzModem_cksum;
+ }
}
- /* If we get here, the message passes [structural] muster */
- return 0;
+ else
+ {
+ cksum = 0;
+ for (i = 0; i < xyz.len; i++)
+ {
+ cksum += xyz.pkt[i];
+ }
+ if (xyz.crc1 != (cksum & 0xFF))
+ {
+ ZM_DEBUG (zm_dprintf
+ ("Checksum error - recvd: %x, computed: %x\n", xyz.crc1,
+ cksum & 0xFF));
+ return xyzModem_cksum;
+ }
+ }
+ /* If we get here, the message passes [structural] muster */
+ return 0;
}
int
-xyzModem_stream_open(connection_info_t *info, int *err)
+xyzModem_stream_open (connection_info_t * info, int *err)
{
#ifdef REDBOOT
- int console_chan;
+ int console_chan;
#endif
- int stat = 0;
- int retries = xyzModem_MAX_RETRIES;
- int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC;
+ int stat = 0;
+ int retries = xyzModem_MAX_RETRIES;
+ int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC;
/* ZM_DEBUG(zm_out = zm_out_start); */
#ifdef xyzModem_zmodem
- if (info->mode == xyzModem_zmodem) {
- *err = xyzModem_noZmodem;
- return -1;
+ if (info->mode == xyzModem_zmodem)
+ {
+ *err = xyzModem_noZmodem;
+ return -1;
}
#endif
#ifdef REDBOOT
- /* Set up the I/O channel. Note: this allows for using a different port in the future */
- console_chan = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
- if (info->chan >= 0) {
- CYGACC_CALL_IF_SET_CONSOLE_COMM(info->chan);
- } else {
- CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan);
+ /* Set up the I/O channel. Note: this allows for using a different port in the future */
+ console_chan =
+ CYGACC_CALL_IF_SET_CONSOLE_COMM
+ (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ if (info->chan >= 0)
+ {
+ CYGACC_CALL_IF_SET_CONSOLE_COMM (info->chan);
}
- xyz.__chan = CYGACC_CALL_IF_CONSOLE_PROCS();
+ else
+ {
+ CYGACC_CALL_IF_SET_CONSOLE_COMM (console_chan);
+ }
+ xyz.__chan = CYGACC_CALL_IF_CONSOLE_PROCS ();
- CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan);
- CYGACC_COMM_IF_CONTROL(*xyz.__chan, __COMMCTL_SET_TIMEOUT, xyzModem_CHAR_TIMEOUT);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM (console_chan);
+ CYGACC_COMM_IF_CONTROL (*xyz.__chan, __COMMCTL_SET_TIMEOUT,
+ xyzModem_CHAR_TIMEOUT);
#else
/* TODO: CHECK ! */
- int dummy;
- xyz.__chan=&dummy;
+ int dummy;
+ xyz.__chan = &dummy;
#endif
- xyz.len = 0;
- xyz.crc_mode = true;
- xyz.at_eof = false;
- xyz.tx_ack = false;
- xyz.mode = info->mode;
- xyz.total_retries = 0;
- xyz.total_SOH = 0;
- xyz.total_STX = 0;
- xyz.total_CAN = 0;
+ xyz.len = 0;
+ xyz.crc_mode = true;
+ xyz.at_eof = false;
+ xyz.tx_ack = false;
+ xyz.mode = info->mode;
+ xyz.total_retries = 0;
+ xyz.total_SOH = 0;
+ xyz.total_STX = 0;
+ xyz.total_CAN = 0;
#ifdef USE_YMODEM_LENGTH
- xyz.read_length = 0;
- xyz.file_length = 0;
+ xyz.read_length = 0;
+ xyz.file_length = 0;
#endif
- CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
- if (xyz.mode == xyzModem_xmodem) {
- /* X-modem doesn't have an information header - exit here */
- xyz.next_blk = 1;
- return 0;
+ if (xyz.mode == xyzModem_xmodem)
+ {
+ /* X-modem doesn't have an information header - exit here */
+ xyz.next_blk = 1;
+ return 0;
}
- while (retries-- > 0) {
- stat = xyzModem_get_hdr();
- if (stat == 0) {
- /* Y-modem file information header */
- if (xyz.blk == 0) {
+ while (retries-- > 0)
+ {
+ stat = xyzModem_get_hdr ();
+ if (stat == 0)
+ {
+ /* Y-modem file information header */
+ if (xyz.blk == 0)
+ {
#ifdef USE_YMODEM_LENGTH
- /* skip filename */
- while (*xyz.bufp++);
- /* get the length */
- parse_num((char *)xyz.bufp, &xyz.file_length, NULL, " ");
+ /* skip filename */
+ while (*xyz.bufp++);
+ /* get the length */
+ parse_num ((char *) xyz.bufp, &xyz.file_length, NULL, " ");
#endif
- /* The rest of the file name data block quietly discarded */
- xyz.tx_ack = true;
- }
- xyz.next_blk = 1;
- xyz.len = 0;
- return 0;
- } else
- if (stat == xyzModem_timeout) {
- if (--crc_retries <= 0) xyz.crc_mode = false;
- CYGACC_CALL_IF_DELAY_US(5*100000); /* Extra delay for startup */
- CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
- xyz.total_retries++;
- ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__));
- }
- if (stat == xyzModem_cancel) {
- break;
- }
+ /* The rest of the file name data block quietly discarded */
+ xyz.tx_ack = true;
+ }
+ xyz.next_blk = 1;
+ xyz.len = 0;
+ return 0;
+ }
+ else if (stat == xyzModem_timeout)
+ {
+ if (--crc_retries <= 0)
+ xyz.crc_mode = false;
+ CYGACC_CALL_IF_DELAY_US (5 * 100000); /* Extra delay for startup */
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
+ xyz.total_retries++;
+ ZM_DEBUG (zm_dprintf ("NAK (%d)\n", __LINE__));
+ }
+ if (stat == xyzModem_cancel)
+ {
+ break;
+ }
}
- *err = stat;
- ZM_DEBUG(zm_flush());
- return -1;
+ *err = stat;
+ ZM_DEBUG (zm_flush ());
+ return -1;
}
int
-xyzModem_stream_read(char *buf, int size, int *err)
+xyzModem_stream_read (char *buf, int size, int *err)
{
- int stat, total, len;
- int retries;
-
- total = 0;
- stat = xyzModem_cancel;
- /* Try and get 'size' bytes into the buffer */
- while (!xyz.at_eof && (size > 0)) {
- if (xyz.len == 0) {
- retries = xyzModem_MAX_RETRIES;
- while (retries-- > 0) {
- stat = xyzModem_get_hdr();
- if (stat == 0) {
- if (xyz.blk == xyz.next_blk) {
- xyz.tx_ack = true;
- ZM_DEBUG(zm_dprintf("ACK block %d (%d)\n", xyz.blk, __LINE__));
- xyz.next_blk = (xyz.next_blk + 1) & 0xFF;
+ int stat, total, len;
+ int retries;
+
+ total = 0;
+ stat = xyzModem_cancel;
+ /* Try and get 'size' bytes into the buffer */
+ while (!xyz.at_eof && (size > 0))
+ {
+ if (xyz.len == 0)
+ {
+ retries = xyzModem_MAX_RETRIES;
+ while (retries-- > 0)
+ {
+ stat = xyzModem_get_hdr ();
+ if (stat == 0)
+ {
+ if (xyz.blk == xyz.next_blk)
+ {
+ xyz.tx_ack = true;
+ ZM_DEBUG (zm_dprintf
+ ("ACK block %d (%d)\n", xyz.blk, __LINE__));
+ xyz.next_blk = (xyz.next_blk + 1) & 0xFF;
#if defined(xyzModem_zmodem) || defined(USE_YMODEM_LENGTH)
- if (xyz.mode == xyzModem_xmodem || xyz.file_length == 0) {
+ if (xyz.mode == xyzModem_xmodem || xyz.file_length == 0)
+ {
#else
- if (1) {
+ if (1)
+ {
#endif
- /* Data blocks can be padded with ^Z (EOF) characters */
- /* This code tries to detect and remove them */
- if ((xyz.bufp[xyz.len-1] == EOF) &&
- (xyz.bufp[xyz.len-2] == EOF) &&
- (xyz.bufp[xyz.len-3] == EOF)) {
- while (xyz.len && (xyz.bufp[xyz.len-1] == EOF)) {
- xyz.len--;
- }
- }
- }
+ /* Data blocks can be padded with ^Z (EOF) characters */
+ /* This code tries to detect and remove them */
+ if ((xyz.bufp[xyz.len - 1] == EOF) &&
+ (xyz.bufp[xyz.len - 2] == EOF) &&
+ (xyz.bufp[xyz.len - 3] == EOF))
+ {
+ while (xyz.len
+ && (xyz.bufp[xyz.len - 1] == EOF))
+ {
+ xyz.len--;
+ }
+ }
+ }
#ifdef USE_YMODEM_LENGTH
- /*
- * See if accumulated length exceeds that of the file.
- * If so, reduce size (i.e., cut out pad bytes)
- * Only do this for Y-modem (and Z-modem should it ever
- * be supported since it can fall back to Y-modem mode).
- */
- if (xyz.mode != xyzModem_xmodem && 0 != xyz.file_length) {
- xyz.read_length += xyz.len;
- if (xyz.read_length > xyz.file_length) {
- xyz.len -= (xyz.read_length - xyz.file_length);
- }
- }
+ /*
+ * See if accumulated length exceeds that of the file.
+ * If so, reduce size (i.e., cut out pad bytes)
+ * Only do this for Y-modem (and Z-modem should it ever
+ * be supported since it can fall back to Y-modem mode).
+ */
+ if (xyz.mode != xyzModem_xmodem && 0 != xyz.file_length)
+ {
+ xyz.read_length += xyz.len;
+ if (xyz.read_length > xyz.file_length)
+ {
+ xyz.len -= (xyz.read_length - xyz.file_length);
+ }
+ }
#endif
- break;
- } else if (xyz.blk == ((xyz.next_blk - 1) & 0xFF)) {
- /* Just re-ACK this so sender will get on with it */
- CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
- continue; /* Need new header */
- } else {
- stat = xyzModem_sequence;
- }
- }
- if (stat == xyzModem_cancel) {
- break;
- }
- if (stat == xyzModem_eof) {
- CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
- ZM_DEBUG(zm_dprintf("ACK (%d)\n", __LINE__));
- if (xyz.mode == xyzModem_ymodem) {
- CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
- xyz.total_retries++;
- ZM_DEBUG(zm_dprintf("Reading Final Header\n"));
- stat = xyzModem_get_hdr();
- CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK);
- ZM_DEBUG(zm_dprintf("FINAL ACK (%d)\n", __LINE__));
- }
- xyz.at_eof = true;
- break;
- }
- CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
- xyz.total_retries++;
- ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__));
- }
- if (stat < 0) {
- *err = stat;
- xyz.len = -1;
- return total;
- }
- }
- /* Don't "read" data from the EOF protocol package */
- if (!xyz.at_eof) {
- len = xyz.len;
- if (size < len) len = size;
- memcpy(buf, xyz.bufp, len);
- size -= len;
- buf += len;
- total += len;
- xyz.len -= len;
- xyz.bufp += len;
- }
+ break;
+ }
+ else if (xyz.blk == ((xyz.next_blk - 1) & 0xFF))
+ {
+ /* Just re-ACK this so sender will get on with it */
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK);
+ continue; /* Need new header */
+ }
+ else
+ {
+ stat = xyzModem_sequence;
+ }
+ }
+ if (stat == xyzModem_cancel)
+ {
+ break;
+ }
+ if (stat == xyzModem_eof)
+ {
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK);
+ ZM_DEBUG (zm_dprintf ("ACK (%d)\n", __LINE__));
+ if (xyz.mode == xyzModem_ymodem)
+ {
+ CYGACC_COMM_IF_PUTC (*xyz.__chan,
+ (xyz.crc_mode ? 'C' : NAK));
+ xyz.total_retries++;
+ ZM_DEBUG (zm_dprintf ("Reading Final Header\n"));
+ stat = xyzModem_get_hdr ();
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK);
+ ZM_DEBUG (zm_dprintf ("FINAL ACK (%d)\n", __LINE__));
+ }
+ xyz.at_eof = true;
+ break;
+ }
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
+ xyz.total_retries++;
+ ZM_DEBUG (zm_dprintf ("NAK (%d)\n", __LINE__));
+ }
+ if (stat < 0)
+ {
+ *err = stat;
+ xyz.len = -1;
+ return total;
+ }
+ }
+ /* Don't "read" data from the EOF protocol package */
+ if (!xyz.at_eof)
+ {
+ len = xyz.len;
+ if (size < len)
+ len = size;
+ memcpy (buf, xyz.bufp, len);
+ size -= len;
+ buf += len;
+ total += len;
+ xyz.len -= len;
+ xyz.bufp += len;
+ }
}
- return total;
+ return total;
}
void
-xyzModem_stream_close(int *err)
+xyzModem_stream_close (int *err)
{
- diag_printf("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n",
- xyz.crc_mode ? "CRC" : "Cksum",
- xyz.total_SOH, xyz.total_STX, xyz.total_CAN,
- xyz.total_retries);
- ZM_DEBUG(zm_flush());
+ diag_printf
+ ("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n",
+ xyz.crc_mode ? "CRC" : "Cksum", xyz.total_SOH, xyz.total_STX,
+ xyz.total_CAN, xyz.total_retries);
+ ZM_DEBUG (zm_flush ());
}
/* Need to be able to clean out the input buffer, so have to take the */
/* getc */
-void xyzModem_stream_terminate(bool abort, int (*getc)(void))
+void
+xyzModem_stream_terminate (bool abort, int (*getc) (void))
{
int c;
- if (abort) {
- ZM_DEBUG(zm_dprintf("!!!! TRANSFER ABORT !!!!\n"));
- switch (xyz.mode) {
+ if (abort)
+ {
+ ZM_DEBUG (zm_dprintf ("!!!! TRANSFER ABORT !!!!\n"));
+ switch (xyz.mode)
+ {
case xyzModem_xmodem:
case xyzModem_ymodem:
/* The X/YMODEM Spec seems to suggest that multiple CAN followed by an equal */
/* number of Backspaces is a friendly way to get the other end to abort. */
- CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
- CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP);
+ CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP);
/* Now consume the rest of what's waiting on the line. */
- ZM_DEBUG(zm_dprintf("Flushing serial line.\n"));
- xyzModem_flush();
- xyz.at_eof = true;
- break;
+ ZM_DEBUG (zm_dprintf ("Flushing serial line.\n"));
+ xyzModem_flush ();
+ xyz.at_eof = true;
+ break;
#ifdef xyzModem_zmodem
case xyzModem_zmodem:
/* Might support it some day I suppose. */
#endif
- break;
- }
- } else {
- ZM_DEBUG(zm_dprintf("Engaging cleanup mode...\n"));
+ break;
+ }
+ }
+ else
+ {
+ ZM_DEBUG (zm_dprintf ("Engaging cleanup mode...\n"));
/*
* Consume any trailing crap left in the inbuffer from
* previous recieved blocks. Since very few files are an exact multiple
* of the transfer block size, there will almost always be some gunk here.
* If we don't eat it now, RedBoot will think the user typed it.
*/
- ZM_DEBUG(zm_dprintf("Trailing gunk:\n"));
- while ((c = (*getc)()) > -1) ;
- ZM_DEBUG(zm_dprintf("\n"));
+ ZM_DEBUG (zm_dprintf ("Trailing gunk:\n"));
+ while ((c = (*getc) ()) > -1);
+ ZM_DEBUG (zm_dprintf ("\n"));
/*
* Make a small delay to give terminal programs like minicom
* time to get control again after their file transfer program
* exits.
*/
- CYGACC_CALL_IF_DELAY_US((cyg_int32)250000);
- }
+ CYGACC_CALL_IF_DELAY_US ((cyg_int32) 250000);
+ }
}
char *
-xyzModem_error(int err)
+xyzModem_error (int err)
{
- switch (err) {
+ switch (err)
+ {
case xyzModem_access:
- return "Can't access file";
- break;
+ return "Can't access file";
+ break;
case xyzModem_noZmodem:
- return "Sorry, zModem not available yet";
- break;
+ return "Sorry, zModem not available yet";
+ break;
case xyzModem_timeout:
- return "Timed out";
- break;
+ return "Timed out";
+ break;
case xyzModem_eof:
- return "End of file";
- break;
+ return "End of file";
+ break;
case xyzModem_cancel:
- return "Cancelled";
- break;
+ return "Cancelled";
+ break;
case xyzModem_frame:
- return "Invalid framing";
- break;
+ return "Invalid framing";
+ break;
case xyzModem_cksum:
- return "CRC/checksum error";
- break;
+ return "CRC/checksum error";
+ break;
case xyzModem_sequence:
- return "Block sequence error";
- break;
+ return "Block sequence error";
+ break;
default:
- return "Unknown error";
- break;
+ return "Unknown error";
+ break;
}
}
/*
* RedBoot interface
*/
-#if 0 /* SB */
-GETC_IO_FUNCS(xyzModem_io, xyzModem_stream_open, xyzModem_stream_close,
- xyzModem_stream_terminate, xyzModem_stream_read, xyzModem_error);
-RedBoot_load(xmodem, xyzModem_io, false, false, xyzModem_xmodem);
-RedBoot_load(ymodem, xyzModem_io, false, false, xyzModem_ymodem);
+#if 0 /* SB */
+GETC_IO_FUNCS (xyzModem_io, xyzModem_stream_open, xyzModem_stream_close,
+ xyzModem_stream_terminate, xyzModem_stream_read,
+ xyzModem_error);
+RedBoot_load (xmodem, xyzModem_io, false, false, xyzModem_xmodem);
+RedBoot_load (ymodem, xyzModem_io, false, false, xyzModem_ymodem);
#endif
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#########################################################################
+ifneq ($(OBJTREE),$(SRCTREE))
+ifeq ($(CURDIR),$(SRCTREE))
+dir :=
+else
+dir := $(subst $(SRCTREE)/,,$(CURDIR))
+endif
+
+obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/)
+src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/)
+
+$(shell mkdir -p $(obj))
+else
+obj :=
+src :=
+endif
+
# clean the slate ...
PLATFORM_RELFLAGS =
PLATFORM_CPPFLAGS =
OBJDUMP = $(CROSS_COMPILE)objdump
RANLIB = $(CROSS_COMPILE)RANLIB
+ifneq (,$(findstring s,$(MAKEFLAGS)))
+ARFLAGS = cr
+else
+ARFLAGS = crv
+endif
RELFLAGS= $(PLATFORM_RELFLAGS)
DBGFLAGS= -g # -DDEBUG
OPTFLAGS= -Os #-fomit-frame-pointer
ifndef LDSCRIPT
#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
+ifeq ($(CONFIG_NAND_U_BOOT),y)
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+else
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
endif
+endif
OBJCFLAGS += --gap-fill=0xff
gccincdir := $(shell $(CC) -print-file-name=include)
CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
-D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \
- -I$(TOPDIR)/include \
- -fno-builtin -ffreestanding -nostdinc -isystem \
- $(gccincdir) -pipe $(PLATFORM_CPPFLAGS)
+
+ifneq ($(OBJTREE),$(SRCTREE))
+CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include
+endif
+
+CPPFLAGS += -I$(TOPDIR)/include
+CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \
+ -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS)
ifdef BUILD_TAG
CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \
endif
endif
-AFLAGS_DEBUG := -Wa,-gstabs
+# $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
+# option to the assembler.
+AFLAGS_DEBUG :=
# turn jbsr into jsr for m68k
ifeq ($(ARCH),m68k)
#########################################################################
+ifndef REMOTE_BUILD
+
%.s: %.S
- $(CPP) $(AFLAGS) -o $@ $(CURDIR)/$<
+ $(CPP) $(AFLAGS) -o $@ $<
%.o: %.S
- $(CC) $(AFLAGS) -c -o $@ $(CURDIR)/$<
+ $(CC) $(AFLAGS) -c -o $@ $<
%.o: %.c
$(CC) $(CFLAGS) -c -o $@ $<
+else
+
+$(obj)%.s: %.S
+ $(CPP) $(AFLAGS) -o $@ $<
+$(obj)%.o: %.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+$(obj)%.o: %.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+endif
+
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-ASOBJS = cache.o kgdb.o io.o
-OBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o
+SOBJS = cache.o kgdb.o io.o
+COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
-all: .depend $(START) $(ASOBJS) $(LIB)
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(ASOBJS) $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = interrupts.o cpu.o
+COBJS = interrupts.o cpu.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = serial.o serial_netarm.o interrupts.o cpu.o
+COBJS = serial.o serial_netarm.o interrupts.o cpu.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = cpu.o interrupts.o
+COBJS = cpu.o interrupts.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2005
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(SOC).a
+LIB = $(obj)lib$(SOC).a
-OBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \
+COBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \
lxt972.o serial.o usb.o
SOBJS = lowlevel_init.o
-all: .depend $(LIB)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(SOC).a
+LIB = $(obj)lib$(SOC).a
-OBJS = generic.o interrupts.o serial.o speed.o
+COBJS = generic.o interrupts.o serial.o speed.o
-all: .depend $(LIB)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2005
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(SOC).a
+LIB = $(obj)lib$(SOC).a
-OBJS = interrupts.o serial.o
+COBJS = interrupts.o serial.o
SOBJS = lowlevel_init.o
-all: .depend $(LIB)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(SOC).a
+LIB = $(obj)lib$(SOC).a
-OBJS = i2c.o interrupts.o serial.o speed.o \
+COBJS = i2c.o interrupts.o serial.o speed.o \
usb.o
-all: .depend $(LIB)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = interrupts.o cpu.o omap925.o
+COBJS = interrupts.o cpu.o omap925.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#include <command.h>
#include <arm925t.h>
-ushort gpioreserved;
-
-void gpioreserve(ushort mask)
-{
- gpioreserved |= mask;
-}
-
-void gpiosetdir(ushort mask, ushort in)
-{
- *(ushort *)GPIO_DIR_CONTROL_REG = (*(ushort *)GPIO_DIR_CONTROL_REG & ~mask) | (in & mask);
-}
-
-
-void gpiosetout(ushort mask, ushort out)
-{
- ushort *r_ptr, r_val;
-
- r_ptr = (ushort *)GPIO_DATA_OUTPUT_REG; /* set pointer */
- r_val = *r_ptr & ~mask; /* get previous val, clear bits we want to change */
- r_val |= (out & mask); /* set specified bits in value + plus origional ones */
- *r_ptr = r_val; /* write it out */
-/*
- * gcc screwed this one up :(.
- *
- * *(ushort *)GPIO_DATA_OUTPUT_REG = (*(ushort *)GPIO_DATA_OUTPUT_REG & ~mask) | (out & mask);
- */
-
-}
-
-void gpioinit(void)
-{
-}
-
-
#define MIF_CONFIG_REG 0xFFFECC0C
#define FLASH_GLOBAL_CTRL_NWP 1
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = interrupts.o cpu.o cpuinfo.o
+COBJS = interrupts.o cpu.o cpuinfo.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2005
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(SOC).a
+LIB = $(obj)lib$(SOC).a
-OBJS = timer.o
+COBJS = timer.o
SOBJS = reset.o
-all: .depend $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2005
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(SOC).a
+LIB = $(obj)lib$(SOC).a
-OBJS = timer.o
+COBJS = timer.o
SOBJS = reset.o
-all: .depend $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = interrupts.o cpu.o
+COBJS = interrupts.o cpu.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = interrupts.o cpu.o
+COBJS = interrupts.o cpu.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2005-2006 Atmel Corporation.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(CPU).a
+
+START := start.o
+SOBJS := entry.o
+COBJS := cpu.o hsdramc.o exception.o cache.o
+COBJS += interrupts.o device.o pm.o pio.o
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(SOC).a
+
+COBJS := hebi.o devices.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+#include "../sm.h"
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+const struct clock_domain chip_clock[] = {
+ [CLOCK_CPU] = {
+ .reg = SM_PM_CPU_MASK,
+ .id = CLOCK_CPU,
+ .bridge = NO_DEVICE,
+ },
+ [CLOCK_HSB] = {
+ .reg = SM_PM_HSB_MASK,
+ .id = CLOCK_HSB,
+ .bridge = NO_DEVICE,
+ },
+ [CLOCK_PBA] = {
+ .reg = SM_PM_PBA_MASK,
+ .id = CLOCK_PBA,
+ .bridge = DEVICE_PBA_BRIDGE,
+ },
+ [CLOCK_PBB] = {
+ .reg = SM_PM_PBB_MASK,
+ .id = CLOCK_PBB,
+ .bridge = DEVICE_PBB_BRIDGE,
+ },
+};
+
+static const struct resource hebi_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 0 },
+ },
+ }, {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 13 },
+ },
+ }, {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 14 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 27, DEVICE_PIOE, GPIO_FUNC_A, 0 },
+ },
+ },
+};
+static const struct resource pba_bridge_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 1 },
+ }
+ }, {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ /* HSB-HSB Bridge */
+ .clock = { CLOCK_HSB, 4 },
+ },
+ },
+};
+static const struct resource pbb_bridge_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 2 },
+ },
+ },
+};
+static const struct resource hramc_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 3 },
+ },
+ },
+};
+static const struct resource pioa_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 10 },
+ },
+ },
+};
+static const struct resource piob_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 11 },
+ },
+ },
+};
+static const struct resource pioc_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 12 },
+ },
+ },
+};
+static const struct resource piod_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 13 },
+ },
+ },
+};
+static const struct resource pioe_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 14 },
+ },
+ },
+};
+static const struct resource sm_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 0 },
+ },
+ },
+};
+static const struct resource intc_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 1 },
+ },
+ },
+};
+static const struct resource hmatrix_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 2 },
+ },
+ },
+};
+#if defined(CFG_HPDC)
+static const struct resource hpdc_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 16 },
+ },
+ },
+};
+#endif
+#if defined(CFG_MACB0)
+static const struct resource macb0_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 8 },
+ },
+ }, {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 6 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 19, DEVICE_PIOC, GPIO_FUNC_A, 0 },
+ },
+ },
+};
+#endif
+#if defined(CFG_MACB1)
+static const struct resource macb1_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 9 },
+ },
+ }, {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 7 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 12, DEVICE_PIOC, GPIO_FUNC_B, 19 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 14, DEVICE_PIOD, GPIO_FUNC_B, 2 },
+ },
+ },
+};
+#endif
+#if defined(CFG_LCDC)
+static const struct resource lcdc_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 7 },
+ },
+ },
+};
+#endif
+#if defined(CFG_USART0)
+static const struct resource usart0_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 3 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_B, 8 },
+ },
+ },
+};
+#endif
+#if defined(CFG_USART1)
+static const struct resource usart1_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 4 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 2, DEVICE_PIOA, GPIO_FUNC_A, 17 },
+ },
+ },
+};
+#endif
+#if defined(CFG_USART2)
+static const struct resource usart2_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 5 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 26 },
+ },
+ },
+};
+#endif
+#if defined(CFG_USART3)
+static const struct resource usart3_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBA, 6 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 17 },
+ },
+ },
+};
+#endif
+#if defined(CFG_MMCI)
+static const struct resource mmci_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_PBB, 9 },
+ },
+ }, {
+ .type = RESOURCE_GPIO,
+ .u = {
+ .gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 10 },
+ },
+ },
+};
+#endif
+#if defined(CFG_DMAC)
+static const struct resource dmac_resource[] = {
+ {
+ .type = RESOURCE_CLOCK,
+ .u = {
+ .clock = { CLOCK_HSB, 10 },
+ },
+ },
+};
+#endif
+
+const struct device chip_device[] = {
+ [DEVICE_HEBI] = {
+ .regs = (void *)HSMC_BASE,
+ .nr_resources = ARRAY_SIZE(hebi_resource),
+ .resource = hebi_resource,
+ },
+ [DEVICE_PBA_BRIDGE] = {
+ .nr_resources = ARRAY_SIZE(pba_bridge_resource),
+ .resource = pba_bridge_resource,
+ },
+ [DEVICE_PBB_BRIDGE] = {
+ .nr_resources = ARRAY_SIZE(pbb_bridge_resource),
+ .resource = pbb_bridge_resource,
+ },
+ [DEVICE_HRAMC] = {
+ .nr_resources = ARRAY_SIZE(hramc_resource),
+ .resource = hramc_resource,
+ },
+ [DEVICE_PIOA] = {
+ .regs = (void *)PIOA_BASE,
+ .nr_resources = ARRAY_SIZE(pioa_resource),
+ .resource = pioa_resource,
+ },
+ [DEVICE_PIOB] = {
+ .regs = (void *)PIOB_BASE,
+ .nr_resources = ARRAY_SIZE(piob_resource),
+ .resource = piob_resource,
+ },
+ [DEVICE_PIOC] = {
+ .regs = (void *)PIOC_BASE,
+ .nr_resources = ARRAY_SIZE(pioc_resource),
+ .resource = pioc_resource,
+ },
+ [DEVICE_PIOD] = {
+ .regs = (void *)PIOD_BASE,
+ .nr_resources = ARRAY_SIZE(piod_resource),
+ .resource = piod_resource,
+ },
+ [DEVICE_PIOE] = {
+ .regs = (void *)PIOE_BASE,
+ .nr_resources = ARRAY_SIZE(pioe_resource),
+ .resource = pioe_resource,
+ },
+ [DEVICE_SM] = {
+ .regs = (void *)SM_BASE,
+ .nr_resources = ARRAY_SIZE(sm_resource),
+ .resource = sm_resource,
+ },
+ [DEVICE_INTC] = {
+ .regs = (void *)INTC_BASE,
+ .nr_resources = ARRAY_SIZE(intc_resource),
+ .resource = intc_resource,
+ },
+ [DEVICE_HMATRIX] = {
+ .regs = (void *)HMATRIX_BASE,
+ .nr_resources = ARRAY_SIZE(hmatrix_resource),
+ .resource = hmatrix_resource,
+ },
+#if defined(CFG_HPDC)
+ [DEVICE_HPDC] = {
+ .nr_resources = ARRAY_SIZE(hpdc_resource),
+ .resource = hpdc_resource,
+ },
+#endif
+#if defined(CFG_MACB0)
+ [DEVICE_MACB0] = {
+ .regs = (void *)MACB0_BASE,
+ .nr_resources = ARRAY_SIZE(macb0_resource),
+ .resource = macb0_resource,
+ },
+#endif
+#if defined(CFG_MACB1)
+ [DEVICE_MACB1] = {
+ .regs = (void *)MACB1_BASE,
+ .nr_resources = ARRAY_SIZE(macb1_resource),
+ .resource = macb1_resource,
+ },
+#endif
+#if defined(CFG_LCDC)
+ [DEVICE_LCDC] = {
+ .nr_resources = ARRAY_SIZE(lcdc_resource),
+ .resource = lcdc_resource,
+ },
+#endif
+#if defined(CFG_USART0)
+ [DEVICE_USART0] = {
+ .regs = (void *)USART0_BASE,
+ .nr_resources = ARRAY_SIZE(usart0_resource),
+ .resource = usart0_resource,
+ },
+#endif
+#if defined(CFG_USART1)
+ [DEVICE_USART1] = {
+ .regs = (void *)USART1_BASE,
+ .nr_resources = ARRAY_SIZE(usart1_resource),
+ .resource = usart1_resource,
+ },
+#endif
+#if defined(CFG_USART2)
+ [DEVICE_USART2] = {
+ .regs = (void *)USART2_BASE,
+ .nr_resources = ARRAY_SIZE(usart2_resource),
+ .resource = usart2_resource,
+ },
+#endif
+#if defined(CFG_USART3)
+ [DEVICE_USART3] = {
+ .regs = (void *)USART3_BASE,
+ .nr_resources = ARRAY_SIZE(usart3_resource),
+ .resource = usart3_resource,
+ },
+#endif
+#if defined(CFG_MMCI)
+ [DEVICE_MMCI] = {
+ .regs = (void *)MMCI_BASE,
+ .nr_resources = ARRAY_SIZE(mmci_resource),
+ .resource = mmci_resource,
+ },
+#endif
+#if defined(CFG_DMAC)
+ [DEVICE_DMAC] = {
+ .regs = (void *)DMAC_BASE,
+ .nr_resources = ARRAY_SIZE(dmac_resource),
+ .resource = dmac_resource,
+ },
+#endif
+};
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/hmatrix2.h>
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+void cpu_enable_sdram(void)
+{
+ const struct device *hmatrix;
+
+ hmatrix = get_device(DEVICE_HMATRIX);
+
+ /* Set the SDRAM_ENABLE bit in the HEBI SFR */
+ hmatrix2_writel(hmatrix, SFR4, 1 << 1);
+}
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/cacheflush.h>
+
+void dcache_clean_range(volatile void *start, size_t size)
+{
+ unsigned long v, begin, end, linesz;
+
+ linesz = CFG_DCACHE_LINESZ;
+
+ /* You asked for it, you got it */
+ begin = (unsigned long)start & ~(linesz - 1);
+ end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+ for (v = begin; v < end; v += linesz)
+ dcache_clean_line((void *)v);
+
+ sync_write_buffer();
+}
+
+void dcache_invalidate_range(volatile void *start, size_t size)
+{
+ unsigned long v, begin, end, linesz;
+
+ linesz = CFG_DCACHE_LINESZ;
+
+ /* You asked for it, you got it */
+ begin = (unsigned long)start & ~(linesz - 1);
+ end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+ for (v = begin; v < end; v += linesz)
+ dcache_invalidate_line((void *)v);
+}
+
+void dcache_flush_range(volatile void *start, size_t size)
+{
+ unsigned long v, begin, end, linesz;
+
+ linesz = CFG_DCACHE_LINESZ;
+
+ /* You asked for it, you got it */
+ begin = (unsigned long)start & ~(linesz - 1);
+ end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+ for (v = begin; v < end; v += linesz)
+ dcache_flush_line((void *)v);
+
+ sync_write_buffer();
+}
+
+void icache_invalidate_range(volatile void *start, size_t size)
+{
+ unsigned long v, begin, end, linesz;
+
+ linesz = CFG_ICACHE_LINESZ;
+
+ /* You asked for it, you got it */
+ begin = (unsigned long)start & ~(linesz - 1);
+ end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+
+ for (v = begin; v < end; v += linesz)
+ icache_invalidate_line((void *)v);
+}
+
+/*
+ * This is called after loading something into memory. We need to
+ * make sure that everything that was loaded is actually written to
+ * RAM, and that the icache will look for it. Cleaning the dcache and
+ * invalidating the icache will do the trick.
+ */
+void flush_cache (unsigned long start_addr, unsigned long size)
+{
+ dcache_clean_range((void *)start_addr, size);
+ icache_invalidate_range((void *)start_addr, size);
+}
--- /dev/null
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -mcpu=ap7000
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+
+#include <asm/io.h>
+#include <asm/sections.h>
+#include <asm/sysreg.h>
+
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+#include "hsmc3.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cpu_init(void)
+{
+ const struct device *hebi;
+ extern void _evba(void);
+ char *p;
+
+ gd->cpu_hz = CFG_OSC0_HZ;
+
+ /* fff03400: 00010001 04030402 00050005 10011103 */
+ hebi = get_device(DEVICE_HEBI);
+ hsmc3_writel(hebi, MODE0, 0x00031103);
+ hsmc3_writel(hebi, CYCLE0, 0x000c000d);
+ hsmc3_writel(hebi, PULSE0, 0x0b0a0906);
+ hsmc3_writel(hebi, SETUP0, 0x00010002);
+
+ pm_init();
+
+ sysreg_write(EVBA, (unsigned long)&_evba);
+ asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
+ gd->console_uart = get_device(CFG_CONSOLE_UART_DEV);
+
+ /* Lock everything that mess with the flash in the icache */
+ for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ);
+ p += CFG_ICACHE_LINESZ)
+ asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory");
+
+ return 0;
+}
+
+void prepare_to_boot(void)
+{
+ /* Flush both caches and the write buffer */
+ asm volatile("cache %0[4], 010\n\t"
+ "cache %0[0], 000\n\t"
+ "sync 0" : : "r"(0) : "memory");
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ /* This will reset the CPU core, caches, MMU and all internal busses */
+ __builtin_mtdr(8, 1 << 13); /* set DC:DBE */
+ __builtin_mtdr(8, 1 << 30); /* set DC:RES */
+
+ /* Flush the pipeline before we declare it a failure */
+ asm volatile("sub pc, pc, -4");
+
+ return -1;
+}
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/arch/platform.h>
+
+#include "sm.h"
+
+struct device_state {
+ int refcount;
+};
+
+static struct device_state device_state[NR_DEVICES];
+
+static int claim_resource(const struct resource *res)
+{
+ int ret = 0;
+
+ switch (res->type) {
+ case RESOURCE_GPIO:
+ ret = gpio_set_func(res->u.gpio.gpio_dev,
+ res->u.gpio.start,
+ res->u.gpio.nr_pins,
+ res->u.gpio.func);
+ break;
+ case RESOURCE_CLOCK:
+ ret = pm_enable_clock(res->u.clock.id, res->u.clock.index);
+ break;
+ }
+
+ return ret;
+}
+
+static void free_resource(const struct resource *res)
+{
+ switch (res->type) {
+ case RESOURCE_GPIO:
+ gpio_free(res->u.gpio.gpio_dev, res->u.gpio.start,
+ res->u.gpio.nr_pins);
+ break;
+ case RESOURCE_CLOCK:
+ pm_disable_clock(res->u.clock.id, res->u.clock.index);
+ break;
+ }
+}
+
+static int init_dev(const struct device *dev)
+{
+ unsigned int i;
+ int ret = 0;
+
+ for (i = 0; i < dev->nr_resources; i++) {
+ ret = claim_resource(&dev->resource[i]);
+ if (ret)
+ goto cleanup;
+ }
+
+ return 0;
+
+cleanup:
+ while (i--)
+ free_resource(&dev->resource[i]);
+
+ return ret;
+}
+
+const struct device *get_device(enum device_id devid)
+{
+ struct device_state *devstate;
+ const struct device *dev;
+ unsigned long flags;
+ int initialized = 0;
+ int ret = 0;
+
+ devstate = &device_state[devid];
+ dev = &chip_device[devid];
+
+ flags = disable_interrupts();
+ if (devstate->refcount++)
+ initialized = 1;
+ if (flags)
+ enable_interrupts();
+
+ if (!initialized)
+ ret = init_dev(dev);
+
+ return ret ? NULL : dev;
+}
+
+void put_device(const struct device *dev)
+{
+ struct device_state *devstate;
+ unsigned long devid, flags;
+
+ devid = (unsigned long)(dev - chip_device) / sizeof(struct device);
+ devstate = &device_state[devid];
+
+ flags = disable_interrupts();
+ devstate--;
+ if (!devstate) {
+ unsigned int i;
+ for (i = 0; i < dev->nr_resources; i++)
+ free_resource(&dev->resource[i]);
+ }
+ if (flags)
+ enable_interrupts();
+}
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <asm/sysreg.h>
+#include <asm/ptrace.h>
+
+ .section .text.exception,"ax"
+ .global _evba
+ .type _evba,@function
+ .align 10
+_evba:
+ .irp x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
+ .align 2
+ rjmp unknown_exception
+ .endr
+
+ .global timer_interrupt_handler
+ .type timer_interrupt_handler,@function
+ .align 2
+timer_interrupt_handler:
+ /*
+ * Increment timer_overflow and re-write COMPARE with 0xffffffff.
+ *
+ * We're running at interrupt level 3, so we don't need to save
+ * r8-r12 or lr to the stack.
+ */
+ mov r8, lo(timer_overflow)
+ orh r8, hi(timer_overflow)
+ ld.w r9, r8[0]
+ mov r10, -1
+ mtsr SYSREG_COMPARE, r10
+ sub r9, -1
+ st.w r8[0], r9
+ rete
+
+ .type unknown_exception, @function
+unknown_exception:
+ pushm r0-r12
+ sub r8, sp, REG_R12 - REG_R0 - 4
+ mov r9, lr
+ mfsr r10, SYSREG_RAR_EX
+ mfsr r11, SYSREG_RSR_EX
+ pushm r8-r11
+ mfsr r12, SYSREG_ECR
+ mov r11, sp
+ rcall do_unknown_exception
+1: rjmp 1b
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/sysreg.h>
+#include <asm/ptrace.h>
+
+static const char * const cpu_modes[8] = {
+ "Application", "Supervisor", "Interrupt level 0", "Interrupt level 1",
+ "Interrupt level 2", "Interrupt level 3", "Exception", "NMI"
+};
+
+static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
+{
+ unsigned long p;
+ int i;
+
+ printf("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
+
+ for (p = bottom & ~31; p < top; ) {
+ printf("%04lx: ", p & 0xffff);
+
+ for (i = 0; i < 8; i++, p += 4) {
+ unsigned int val;
+
+ if (p < bottom || p >= top)
+ printf(" ");
+ else {
+ val = *(unsigned long *)p;
+ printf("%08x ", val);
+ }
+ }
+ printf("\n");
+ }
+}
+
+void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
+{
+ unsigned int mode;
+
+ printf("\n *** Unhandled exception %u at PC=0x%08lx\n", ecr, regs->pc);
+
+ switch (ecr) {
+ case ECR_BUS_ERROR_WRITE:
+ case ECR_BUS_ERROR_READ:
+ printf("Bus error at address 0x%08lx\n",
+ sysreg_read(BEAR));
+ break;
+ case ECR_TLB_MULTIPLE:
+ case ECR_ADDR_ALIGN_X:
+ case ECR_PROTECTION_X:
+ case ECR_ADDR_ALIGN_R:
+ case ECR_ADDR_ALIGN_W:
+ case ECR_PROTECTION_R:
+ case ECR_PROTECTION_W:
+ case ECR_DTLB_MODIFIED:
+ case ECR_TLB_MISS_X:
+ case ECR_TLB_MISS_R:
+ case ECR_TLB_MISS_W:
+ printf("MMU exception at address 0x%08lx\n",
+ sysreg_read(TLBEAR));
+ break;
+ }
+
+ printf(" pc: %08lx lr: %08lx sp: %08lx r12: %08lx\n",
+ regs->pc, regs->lr, regs->sp, regs->r12);
+ printf(" r11: %08lx r10: %08lx r9: %08lx r8: %08lx\n",
+ regs->r11, regs->r10, regs->r9, regs->r8);
+ printf(" r7: %08lx r6: %08lx r5: %08lx r4: %08lx\n",
+ regs->r7, regs->r6, regs->r5, regs->r4);
+ printf(" r3: %08lx r2: %08lx r1: %08lx r0: %08lx\n",
+ regs->r3, regs->r2, regs->r1, regs->r0);
+ printf("Flags: %c%c%c%c%c\n",
+ regs->sr & SR_Q ? 'Q' : 'q',
+ regs->sr & SR_V ? 'V' : 'v',
+ regs->sr & SR_N ? 'N' : 'n',
+ regs->sr & SR_Z ? 'Z' : 'z',
+ regs->sr & SR_C ? 'C' : 'c');
+ printf("Mode bits: %c%c%c%c%c%c%c%c%c\n",
+ regs->sr & SR_H ? 'H' : 'h',
+ regs->sr & SR_R ? 'R' : 'r',
+ regs->sr & SR_J ? 'J' : 'j',
+ regs->sr & SR_EM ? 'E' : 'e',
+ regs->sr & SR_I3M ? '3' : '.',
+ regs->sr & SR_I2M ? '2' : '.',
+ regs->sr & SR_I1M ? '1' : '.',
+ regs->sr & SR_I0M ? '0' : '.',
+ regs->sr & SR_GM ? 'G' : 'g');
+ mode = (regs->sr >> SYSREG_M0_OFFSET) & 7;
+ printf("CPU Mode: %s\n", cpu_modes[mode]);
+
+ /* Avoid exception loops */
+ if (regs->sp >= CFG_INIT_SP_ADDR
+ || regs->sp < (CFG_INIT_SP_ADDR - CONFIG_STACKSIZE))
+ printf("\nStack pointer seems bogus, won't do stack dump\n");
+ else
+ dump_mem("\nStack: ", regs->sp, CFG_INIT_SP_ADDR);
+
+ panic("Unhandled exception\n");
+}
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CFG_HSDRAMC
+#include <asm/io.h>
+#include <asm/sdram.h>
+
+#include <asm/arch/platform.h>
+
+#include "hsdramc1.h"
+
+struct hsdramc {
+ const struct device *hebi;
+ void *regs;
+};
+
+static struct hsdramc hsdramc;
+
+unsigned long sdram_init(const struct sdram_info *info)
+{
+ unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
+ unsigned long sdram_size;
+ unsigned long tmp;
+ unsigned long bus_hz;
+ unsigned int i;
+
+ hsdramc.hebi = get_device(DEVICE_HEBI);
+ if (!hsdramc.hebi)
+ return 0;
+
+ /* FIXME: Both of these lines are complete hacks */
+ hsdramc.regs = hsdramc.hebi->regs + 0x400;
+ bus_hz = pm_get_clock_freq(hsdramc.hebi->resource[0].u.clock.id);
+
+ cpu_enable_sdram();
+
+ tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
+ | HSDRAMC1_BF(NR, info->row_bits - 11)
+ | HSDRAMC1_BF(NB, info->bank_bits - 1)
+ | HSDRAMC1_BF(CAS, info->cas)
+ | HSDRAMC1_BF(TWR, info->twr)
+ | HSDRAMC1_BF(TRC, info->trc)
+ | HSDRAMC1_BF(TRP, info->trp)
+ | HSDRAMC1_BF(TRCD, info->trcd)
+ | HSDRAMC1_BF(TRAS, info->tras)
+ | HSDRAMC1_BF(TXSR, info->txsr));
+
+#ifdef CFG_SDRAM_16BIT
+ tmp |= HSDRAMC1_BIT(DBW);
+ sdram_size = 1 << (info->row_bits + info->col_bits
+ + info->bank_bits + 1);
+#else
+ sdram_size = 1 << (info->row_bits + info->col_bits
+ + info->bank_bits + 2);
+#endif
+
+ hsdramc1_writel(&hsdramc, CR, tmp);
+
+ /*
+ * Initialization sequence for SDRAM, from the data sheet:
+ *
+ * 1. A minimum pause of 200 us is provided to precede any
+ * signal toggle.
+ */
+ udelay(200);
+
+ /*
+ * 2. A Precharge All command is issued to the SDRAM
+ */
+ hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
+ hsdramc1_readl(&hsdramc, MR);
+ writel(0, sdram);
+
+ /*
+ * 3. Eight auto-refresh (CBR) cycles are provided
+ */
+ hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_AUTO_REFRESH);
+ hsdramc1_readl(&hsdramc, MR);
+ for (i = 0; i < 8; i++)
+ writel(0, sdram);
+
+ /*
+ * 4. A mode register set (MRS) cycle is issued to program
+ * SDRAM parameters, in particular CAS latency and burst
+ * length.
+ *
+ * CAS from info struct, burst length 1, serial burst type
+ */
+ hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_LOAD_MODE);
+ hsdramc1_readl(&hsdramc, MR);
+ writel(0, sdram + (info->cas << 4));
+
+ /*
+ * 5. A Normal Mode command is provided, 3 clocks after tMRD
+ * is met.
+ *
+ * From the timing diagram, it looks like tMRD is 3
+ * cycles...try a dummy read from the peripheral bus.
+ */
+ hsdramc1_readl(&hsdramc, MR);
+ hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_NORMAL);
+ hsdramc1_readl(&hsdramc, MR);
+ writel(0, sdram);
+
+ /*
+ * 6. Write refresh rate into SDRAMC refresh timer count
+ * register (refresh rate = timing between refresh cycles).
+ *
+ * 15.6 us is a typical value for a burst of length one
+ */
+ hsdramc1_writel(&hsdramc, TR, (156 * (bus_hz / 1000)) / 10000);
+
+ printf("SDRAM: %u MB at address 0x%08lx\n",
+ sdram_size >> 20, info->phys_addr);
+
+ printf("Testing SDRAM...");
+ for (i = 0; i < sdram_size / 4; i++)
+ sdram[i] = i;
+
+ for (i = 0; i < sdram_size / 4; i++) {
+ tmp = sdram[i];
+ if (tmp != i) {
+ printf("FAILED at address 0x%08lx\n",
+ info->phys_addr + i * 4);
+ printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
+ return 0;
+ }
+ }
+
+ puts("OK\n");
+
+ return sdram_size;
+}
+
+#endif /* CFG_HSDRAMC */
--- /dev/null
+/*
+ * Register definitions for SDRAM Controller
+ */
+#ifndef __ASM_AVR32_HSDRAMC1_H__
+#define __ASM_AVR32_HSDRAMC1_H__
+
+/* HSDRAMC1 register offsets */
+#define HSDRAMC1_MR 0x0000
+#define HSDRAMC1_TR 0x0004
+#define HSDRAMC1_CR 0x0008
+#define HSDRAMC1_HSR 0x000c
+#define HSDRAMC1_LPR 0x0010
+#define HSDRAMC1_IER 0x0014
+#define HSDRAMC1_IDR 0x0018
+#define HSDRAMC1_IMR 0x001c
+#define HSDRAMC1_ISR 0x0020
+#define HSDRAMC1_MDR 0x0024
+#define HSDRAMC1_VERSION 0x00fc
+
+/* Bitfields in MR */
+#define HSDRAMC1_MODE_OFFSET 0
+#define HSDRAMC1_MODE_SIZE 3
+
+/* Bitfields in TR */
+#define HSDRAMC1_COUNT_OFFSET 0
+#define HSDRAMC1_COUNT_SIZE 12
+
+/* Bitfields in CR */
+#define HSDRAMC1_NC_OFFSET 0
+#define HSDRAMC1_NC_SIZE 2
+#define HSDRAMC1_NR_OFFSET 2
+#define HSDRAMC1_NR_SIZE 2
+#define HSDRAMC1_NB_OFFSET 4
+#define HSDRAMC1_NB_SIZE 1
+#define HSDRAMC1_CAS_OFFSET 5
+#define HSDRAMC1_CAS_SIZE 2
+#define HSDRAMC1_DBW_OFFSET 7
+#define HSDRAMC1_DBW_SIZE 1
+#define HSDRAMC1_TWR_OFFSET 8
+#define HSDRAMC1_TWR_SIZE 4
+#define HSDRAMC1_TRC_OFFSET 12
+#define HSDRAMC1_TRC_SIZE 4
+#define HSDRAMC1_TRP_OFFSET 16
+#define HSDRAMC1_TRP_SIZE 4
+#define HSDRAMC1_TRCD_OFFSET 20
+#define HSDRAMC1_TRCD_SIZE 4
+#define HSDRAMC1_TRAS_OFFSET 24
+#define HSDRAMC1_TRAS_SIZE 4
+#define HSDRAMC1_TXSR_OFFSET 28
+#define HSDRAMC1_TXSR_SIZE 4
+
+/* Bitfields in HSR */
+#define HSDRAMC1_DA_OFFSET 0
+#define HSDRAMC1_DA_SIZE 1
+
+/* Bitfields in LPR */
+#define HSDRAMC1_LPCB_OFFSET 0
+#define HSDRAMC1_LPCB_SIZE 2
+#define HSDRAMC1_PASR_OFFSET 4
+#define HSDRAMC1_PASR_SIZE 3
+#define HSDRAMC1_TCSR_OFFSET 8
+#define HSDRAMC1_TCSR_SIZE 2
+#define HSDRAMC1_DS_OFFSET 10
+#define HSDRAMC1_DS_SIZE 2
+#define HSDRAMC1_TIMEOUT_OFFSET 12
+#define HSDRAMC1_TIMEOUT_SIZE 2
+
+/* Bitfields in IDR */
+#define HSDRAMC1_RES_OFFSET 0
+#define HSDRAMC1_RES_SIZE 1
+
+/* Bitfields in MDR */
+#define HSDRAMC1_MD_OFFSET 0
+#define HSDRAMC1_MD_SIZE 2
+
+/* Bitfields in VERSION */
+#define HSDRAMC1_VERSION_OFFSET 0
+#define HSDRAMC1_VERSION_SIZE 12
+#define HSDRAMC1_MFN_OFFSET 16
+#define HSDRAMC1_MFN_SIZE 3
+
+/* Constants for MODE */
+#define HSDRAMC1_MODE_NORMAL 0
+#define HSDRAMC1_MODE_NOP 1
+#define HSDRAMC1_MODE_BANKS_PRECHARGE 2
+#define HSDRAMC1_MODE_LOAD_MODE 3
+#define HSDRAMC1_MODE_AUTO_REFRESH 4
+#define HSDRAMC1_MODE_EXT_LOAD_MODE 5
+#define HSDRAMC1_MODE_POWER_DOWN 6
+
+/* Constants for NC */
+#define HSDRAMC1_NC_8_COLUMN_BITS 0
+#define HSDRAMC1_NC_9_COLUMN_BITS 1
+#define HSDRAMC1_NC_10_COLUMN_BITS 2
+#define HSDRAMC1_NC_11_COLUMN_BITS 3
+
+/* Constants for NR */
+#define HSDRAMC1_NR_11_ROW_BITS 0
+#define HSDRAMC1_NR_12_ROW_BITS 1
+#define HSDRAMC1_NR_13_ROW_BITS 2
+
+/* Constants for NB */
+#define HSDRAMC1_NB_TWO_BANKS 0
+#define HSDRAMC1_NB_FOUR_BANKS 1
+
+/* Constants for CAS */
+#define HSDRAMC1_CAS_ONE_CYCLE 1
+#define HSDRAMC1_CAS_TWO_CYCLES 2
+
+/* Constants for DBW */
+#define HSDRAMC1_DBW_32_BITS 0
+#define HSDRAMC1_DBW_16_BITS 1
+
+/* Constants for TIMEOUT */
+#define HSDRAMC1_TIMEOUT_AFTER_END 0
+#define HSDRAMC1_TIMEOUT_64_CYC_AFTER_END 1
+#define HSDRAMC1_TIMEOUT_128_CYC_AFTER_END 2
+
+/* Constants for MD */
+#define HSDRAMC1_MD_SDRAM 0
+#define HSDRAMC1_MD_LOW_POWER_SDRAM 1
+
+/* Bit manipulation macros */
+#define HSDRAMC1_BIT(name) \
+ (1 << HSDRAMC1_##name##_OFFSET)
+#define HSDRAMC1_BF(name,value) \
+ (((value) & ((1 << HSDRAMC1_##name##_SIZE) - 1)) \
+ << HSDRAMC1_##name##_OFFSET)
+#define HSDRAMC1_BFEXT(name,value) \
+ (((value) >> HSDRAMC1_##name##_OFFSET) \
+ & ((1 << HSDRAMC1_##name##_SIZE) - 1))
+#define HSDRAMC1_BFINS(name,value,old) \
+ (((old) & ~(((1 << HSDRAMC1_##name##_SIZE) - 1) \
+ << HSDRAMC1_##name##_OFFSET)) \
+ | HSDRAMC1_BF(name,value))
+
+/* Register access macros */
+#define hsdramc1_readl(port,reg) \
+ readl((port)->regs + HSDRAMC1_##reg)
+#define hsdramc1_writel(port,reg,value) \
+ writel((value), (port)->regs + HSDRAMC1_##reg)
+
+#endif /* __ASM_AVR32_HSDRAMC1_H__ */
--- /dev/null
+/*
+ * Register definitions for Static Memory Controller
+ */
+#ifndef __CPU_AT32AP_HSMC3_H__
+#define __CPU_AT32AP_HSMC3_H__
+
+/* HSMC3 register offsets */
+#define HSMC3_SETUP0 0x0000
+#define HSMC3_PULSE0 0x0004
+#define HSMC3_CYCLE0 0x0008
+#define HSMC3_MODE0 0x000c
+#define HSMC3_SETUP1 0x0010
+#define HSMC3_PULSE1 0x0014
+#define HSMC3_CYCLE1 0x0018
+#define HSMC3_MODE1 0x001c
+#define HSMC3_SETUP2 0x0020
+#define HSMC3_PULSE2 0x0024
+#define HSMC3_CYCLE2 0x0028
+#define HSMC3_MODE2 0x002c
+#define HSMC3_SETUP3 0x0030
+#define HSMC3_PULSE3 0x0034
+#define HSMC3_CYCLE3 0x0038
+#define HSMC3_MODE3 0x003c
+#define HSMC3_SETUP4 0x0040
+#define HSMC3_PULSE4 0x0044
+#define HSMC3_CYCLE4 0x0048
+#define HSMC3_MODE4 0x004c
+#define HSMC3_SETUP5 0x0050
+#define HSMC3_PULSE5 0x0054
+#define HSMC3_CYCLE5 0x0058
+#define HSMC3_MODE5 0x005c
+
+/* Bitfields in SETUP0 */
+#define HSMC3_NWE_SETUP_OFFSET 0
+#define HSMC3_NWE_SETUP_SIZE 6
+#define HSMC3_NCS_WR_SETUP_OFFSET 8
+#define HSMC3_NCS_WR_SETUP_SIZE 6
+#define HSMC3_NRD_SETUP_OFFSET 16
+#define HSMC3_NRD_SETUP_SIZE 6
+#define HSMC3_NCS_RD_SETUP_OFFSET 24
+#define HSMC3_NCS_RD_SETUP_SIZE 6
+
+/* Bitfields in PULSE0 */
+#define HSMC3_NWE_PULSE_OFFSET 0
+#define HSMC3_NWE_PULSE_SIZE 7
+#define HSMC3_NCS_WR_PULSE_OFFSET 8
+#define HSMC3_NCS_WR_PULSE_SIZE 7
+#define HSMC3_NRD_PULSE_OFFSET 16
+#define HSMC3_NRD_PULSE_SIZE 7
+#define HSMC3_NCS_RD_PULSE_OFFSET 24
+#define HSMC3_NCS_RD_PULSE_SIZE 7
+
+/* Bitfields in CYCLE0 */
+#define HSMC3_NWE_CYCLE_OFFSET 0
+#define HSMC3_NWE_CYCLE_SIZE 9
+#define HSMC3_NRD_CYCLE_OFFSET 16
+#define HSMC3_NRD_CYCLE_SIZE 9
+
+/* Bitfields in MODE0 */
+#define HSMC3_READ_MODE_OFFSET 0
+#define HSMC3_READ_MODE_SIZE 1
+#define HSMC3_WRITE_MODE_OFFSET 1
+#define HSMC3_WRITE_MODE_SIZE 1
+#define HSMC3_EXNW_MODE_OFFSET 4
+#define HSMC3_EXNW_MODE_SIZE 2
+#define HSMC3_BAT_OFFSET 8
+#define HSMC3_BAT_SIZE 1
+#define HSMC3_DBW_OFFSET 12
+#define HSMC3_DBW_SIZE 2
+#define HSMC3_TDF_CYCLES_OFFSET 16
+#define HSMC3_TDF_CYCLES_SIZE 4
+#define HSMC3_TDF_MODE_OFFSET 20
+#define HSMC3_TDF_MODE_SIZE 1
+#define HSMC3_PMEN_OFFSET 24
+#define HSMC3_PMEN_SIZE 1
+#define HSMC3_PS_OFFSET 28
+#define HSMC3_PS_SIZE 2
+
+/* Bitfields in MODE1 */
+#define HSMC3_PD_OFFSET 28
+#define HSMC3_PD_SIZE 2
+
+/* Constants for READ_MODE */
+#define HSMC3_READ_MODE_NCS_CONTROLLED 0
+#define HSMC3_READ_MODE_NRD_CONTROLLED 1
+
+/* Constants for WRITE_MODE */
+#define HSMC3_WRITE_MODE_NCS_CONTROLLED 0
+#define HSMC3_WRITE_MODE_NWE_CONTROLLED 1
+
+/* Constants for EXNW_MODE */
+#define HSMC3_EXNW_MODE_DISABLED 0
+#define HSMC3_EXNW_MODE_RESERVED 1
+#define HSMC3_EXNW_MODE_FROZEN 2
+#define HSMC3_EXNW_MODE_READY 3
+
+/* Constants for BAT */
+#define HSMC3_BAT_BYTE_SELECT 0
+#define HSMC3_BAT_BYTE_WRITE 1
+
+/* Constants for DBW */
+#define HSMC3_DBW_8_BITS 0
+#define HSMC3_DBW_16_BITS 1
+#define HSMC3_DBW_32_BITS 2
+
+/* Bit manipulation macros */
+#define HSMC3_BIT(name) \
+ (1 << HSMC3_##name##_OFFSET)
+#define HSMC3_BF(name,value) \
+ (((value) & ((1 << HSMC3_##name##_SIZE) - 1)) \
+ << HSMC3_##name##_OFFSET)
+#define HSMC3_BFEXT(name,value) \
+ (((value) >> HSMC3_##name##_OFFSET) \
+ & ((1 << HSMC3_##name##_SIZE) - 1))
+#define HSMC3_BFINS(name,value,old)\
+ (((old) & ~(((1 << HSMC3_##name##_SIZE) - 1) \
+ << HSMC3_##name##_OFFSET)) \
+ | HSMC3_BF(name,value))
+
+/* Register access macros */
+#define hsmc3_readl(port,reg) \
+ readl((port)->regs + HSMC3_##reg)
+#define hsmc3_writel(port,reg,value) \
+ writel((value), (port)->regs + HSMC3_##reg)
+
+#endif /* __CPU_AT32AP_HSMC3_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/div64.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/sysreg.h>
+
+#include <asm/arch/platform.h>
+
+#define HANDLER_MASK 0x00ffffff
+#define INTLEV_SHIFT 30
+#define INTLEV_MASK 0x00000003
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Incremented whenever COUNT reaches 0xffffffff by timer_interrupt_handler */
+volatile unsigned long timer_overflow;
+
+/*
+ * Instead of dividing by get_tbclk(), multiply by this constant and
+ * right-shift the result by 32 bits.
+ */
+static unsigned long tb_factor;
+
+static const struct device *intc_dev;
+
+unsigned long get_tbclk(void)
+{
+ return gd->cpu_hz;
+}
+
+unsigned long long get_ticks(void)
+{
+ unsigned long lo, hi_now, hi_prev;
+
+ do {
+ hi_prev = timer_overflow;
+ lo = sysreg_read(COUNT);
+ hi_now = timer_overflow;
+ } while (hi_prev != hi_now);
+
+ return ((unsigned long long)hi_now << 32) | lo;
+}
+
+void reset_timer(void)
+{
+ sysreg_write(COUNT, 0);
+ cpu_sync_pipeline(); /* process any pending interrupts */
+ timer_overflow = 0;
+}
+
+unsigned long get_timer(unsigned long base)
+{
+ u64 now = get_ticks();
+
+ now *= tb_factor;
+ return (unsigned long)(now >> 32) - base;
+}
+
+void set_timer(unsigned long t)
+{
+ unsigned long long ticks = t;
+ unsigned long lo, hi, hi_new;
+
+ ticks = (ticks * get_tbclk()) / CFG_HZ;
+ hi = ticks >> 32;
+ lo = ticks & 0xffffffffUL;
+
+ do {
+ timer_overflow = hi;
+ sysreg_write(COUNT, lo);
+ hi_new = timer_overflow;
+ } while (hi_new != hi);
+}
+
+/*
+ * For short delays only. It will overflow after a few seconds.
+ */
+void udelay(unsigned long usec)
+{
+ unsigned long now, end;
+
+ now = sysreg_read(COUNT);
+
+ end = ((usec * (get_tbclk() / 10000)) + 50) / 100;
+ end += now;
+
+ while (now > end)
+ now = sysreg_read(COUNT);
+
+ while (now < end)
+ now = sysreg_read(COUNT);
+}
+
+static int set_interrupt_handler(unsigned int nr, void (*handler)(void),
+ unsigned int priority)
+{
+ unsigned long intpr;
+ unsigned long handler_addr = (unsigned long)handler;
+
+ if ((handler_addr & HANDLER_MASK) != handler_addr
+ || (priority & INTLEV_MASK) != priority)
+ return -EINVAL;
+
+ intpr = (handler_addr & HANDLER_MASK);
+ intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT;
+ writel(intpr, intc_dev->regs + 4 * nr);
+
+ return 0;
+}
+
+void timer_init(void)
+{
+ extern void timer_interrupt_handler(void);
+ u64 tmp;
+
+ sysreg_write(COUNT, 0);
+
+ tmp = (u64)CFG_HZ << 32;
+ tmp += gd->cpu_hz / 2;
+ do_div(tmp, gd->cpu_hz);
+ tb_factor = (u32)tmp;
+
+ intc_dev = get_device(DEVICE_INTC);
+
+ if (!intc_dev
+ || set_interrupt_handler(0, &timer_interrupt_handler, 3))
+ return;
+
+ /* For all practical purposes, this gives us an overflow interrupt */
+ sysreg_write(COMPARE, 0xffffffff);
+}
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+
+#include "pio2.h"
+
+struct pio_state {
+ const struct device *dev;
+ u32 alloc_mask;
+};
+
+static struct pio_state pio_state[CFG_NR_PIOS];
+
+int gpio_set_func(enum device_id gpio_devid, unsigned int start,
+ unsigned int nr_pins, enum gpio_func func)
+{
+ const struct device *gpio;
+ struct pio_state *state;
+ u32 mask;
+
+ state = &pio_state[gpio_devid - DEVICE_PIOA];
+
+ gpio = get_device(gpio_devid);
+ if (!gpio)
+ return -EBUSY;
+
+ state->dev = gpio;
+ mask = ((1 << nr_pins) - 1) << start;
+
+ if (mask & state->alloc_mask) {
+ put_device(gpio);
+ return -EBUSY;
+ }
+ state->alloc_mask |= mask;
+
+ switch (func) {
+ case GPIO_FUNC_GPIO:
+ /* TODO */
+ return -EINVAL;
+ case GPIO_FUNC_A:
+ pio2_writel(gpio, ASR, mask);
+ pio2_writel(gpio, PDR, mask);
+ pio2_writel(gpio, PUDR, mask);
+ break;
+ case GPIO_FUNC_B:
+ pio2_writel(gpio, BSR, mask);
+ pio2_writel(gpio, PDR, mask);
+ pio2_writel(gpio, PUDR, mask);
+ break;
+ }
+
+ return 0;
+}
+
+void gpio_free(enum device_id gpio_devid, unsigned int start,
+ unsigned int nr_pins)
+{
+ const struct device *gpio;
+ struct pio_state *state;
+ u32 mask;
+
+ state = &pio_state[gpio_devid - DEVICE_PIOA];
+ gpio = state->dev;
+ mask = ((1 << nr_pins) - 1) << start;
+
+ pio2_writel(gpio, ODR, mask);
+ pio2_writel(gpio, PER, mask);
+
+ state->alloc_mask &= ~mask;
+ put_device(gpio);
+}
--- /dev/null
+/*
+ * Register definitions for Parallel Input/Output Controller
+ */
+#ifndef __CPU_AT32AP_PIO2_H__
+#define __CPU_AT32AP_PIO2_H__
+
+/* PIO2 register offsets */
+#define PIO2_PER 0x0000
+#define PIO2_PDR 0x0004
+#define PIO2_PSR 0x0008
+#define PIO2_OER 0x0010
+#define PIO2_ODR 0x0014
+#define PIO2_OSR 0x0018
+#define PIO2_IFER 0x0020
+#define PIO2_IFDR 0x0024
+#define PIO2_ISFR 0x0028
+#define PIO2_SODR 0x0030
+#define PIO2_CODR 0x0034
+#define PIO2_ODSR 0x0038
+#define PIO2_PDSR 0x003c
+#define PIO2_IER 0x0040
+#define PIO2_IDR 0x0044
+#define PIO2_IMR 0x0048
+#define PIO2_ISR 0x004c
+#define PIO2_MDER 0x0050
+#define PIO2_MDDR 0x0054
+#define PIO2_MDSR 0x0058
+#define PIO2_PUDR 0x0060
+#define PIO2_PUER 0x0064
+#define PIO2_PUSR 0x0068
+#define PIO2_ASR 0x0070
+#define PIO2_BSR 0x0074
+#define PIO2_ABSR 0x0078
+#define PIO2_OWER 0x00a0
+#define PIO2_OWDR 0x00a4
+#define PIO2_OWSR 0x00a8
+
+/* Register access macros */
+#define pio2_readl(port,reg) \
+ readl((port)->regs + PIO2_##reg)
+#define pio2_writel(port,reg,value) \
+ writel((value), (port)->regs + PIO2_##reg)
+
+#endif /* __CPU_AT32AP_PIO2_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CFG_POWER_MANAGER
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#include <asm/arch/memory-map.h>
+#include <asm/arch/platform.h>
+
+#include "sm.h"
+
+/* Sanity checks */
+#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
+ || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \
+ || (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
+# error Constraint fCPU >= fHSB >= fPB{A,B} violated
+#endif
+#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
+# error Invalid PLL multiplier and/or divider
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clock_domain_state {
+ const struct device *bridge;
+ unsigned long freq;
+ u32 mask;
+};
+static struct clock_domain_state ckd_state[NR_CLOCK_DOMAINS];
+
+int pm_enable_clock(enum clock_domain_id id, unsigned int index)
+{
+ const struct clock_domain *ckd = &chip_clock[id];
+ struct clock_domain_state *state = &ckd_state[id];
+
+ if (ckd->bridge != NO_DEVICE) {
+ state->bridge = get_device(ckd->bridge);
+ if (!state->bridge)
+ return -EBUSY;
+ }
+
+ state->mask |= 1 << index;
+ if (gd->sm)
+ writel(state->mask, gd->sm->regs + ckd->reg);
+
+ return 0;
+}
+
+void pm_disable_clock(enum clock_domain_id id, unsigned int index)
+{
+ const struct clock_domain *ckd = &chip_clock[id];
+ struct clock_domain_state *state = &ckd_state[id];
+
+ state->mask &= ~(1 << index);
+ if (gd->sm)
+ writel(state->mask, gd->sm->regs + ckd->reg);
+
+ if (ckd->bridge)
+ put_device(state->bridge);
+}
+
+unsigned long pm_get_clock_freq(enum clock_domain_id domain)
+{
+ return ckd_state[domain].freq;
+}
+
+void pm_init(void)
+{
+ uint32_t cksel = 0;
+ unsigned long main_clock;
+
+ /* Make sure we don't disable any device we're already using */
+ get_device(DEVICE_HRAMC);
+ get_device(DEVICE_HEBI);
+
+ /* Enable the PICO as well */
+ ckd_state[CLOCK_CPU].mask |= 1;
+
+ gd->sm = get_device(DEVICE_SM);
+ if (!gd->sm)
+ panic("Unable to claim system manager device!\n");
+
+ /* Disable any devices that haven't been explicitly claimed */
+ sm_writel(gd->sm, PM_PBB_MASK, ckd_state[CLOCK_PBB].mask);
+ sm_writel(gd->sm, PM_PBA_MASK, ckd_state[CLOCK_PBA].mask);
+ sm_writel(gd->sm, PM_HSB_MASK, ckd_state[CLOCK_HSB].mask);
+ sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask);
+
+#ifdef CONFIG_PLL
+ /* Initialize the PLL */
+ main_clock = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL;
+
+ sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
+ | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
+ | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
+ | SM_BF(PLLOPT, CFG_PLL0_OPT)
+ | SM_BF(PLLOSC, 0)
+ | SM_BIT(PLLEN)));
+
+ /* Wait for lock */
+ while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ;
+#else
+ main_clock = CFG_OSC0_HZ;
+#endif
+
+ /* Set up clocks for the CPU and all peripheral buses */
+ if (CFG_CLKDIV_CPU) {
+ cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
+ ckd_state[CLOCK_CPU].freq = main_clock / (1 << CFG_CLKDIV_CPU);
+ } else {
+ ckd_state[CLOCK_CPU].freq = main_clock;
+ }
+ if (CFG_CLKDIV_HSB) {
+ cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
+ ckd_state[CLOCK_HSB].freq = main_clock / (1 << CFG_CLKDIV_HSB);
+ } else {
+ ckd_state[CLOCK_HSB].freq = main_clock;
+ }
+ if (CFG_CLKDIV_PBA) {
+ cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
+ ckd_state[CLOCK_PBA].freq = main_clock / (1 << CFG_CLKDIV_PBA);
+ } else {
+ ckd_state[CLOCK_PBA].freq = main_clock;
+ }
+ if (CFG_CLKDIV_PBB) {
+ cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
+ ckd_state[CLOCK_PBB].freq = main_clock / (1 << CFG_CLKDIV_PBB);
+ } else {
+ ckd_state[CLOCK_PBB].freq = main_clock;
+ }
+ sm_writel(gd->sm, PM_CKSEL, cksel);
+
+ /* CFG_HZ currently depends on cpu_hz */
+ gd->cpu_hz = ckd_state[CLOCK_CPU].freq;
+
+#ifdef CONFIG_PLL
+ /* Use PLL0 as main clock */
+ sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL));
+#endif
+}
+
+#endif /* CFG_POWER_MANAGER */
--- /dev/null
+/*
+ * Register definitions for System Manager
+ */
+#ifndef __CPU_AT32AP_SM_H__
+#define __CPU_AT32AP_SM_H__
+
+/* SM register offsets */
+#define SM_PM_MCCTRL 0x0000
+#define SM_PM_CKSEL 0x0004
+#define SM_PM_CPU_MASK 0x0008
+#define SM_PM_HSB_MASK 0x000c
+#define SM_PM_PBA_MASK 0x0010
+#define SM_PM_PBB_MASK 0x0014
+#define SM_PM_PLL0 0x0020
+#define SM_PM_PLL1 0x0024
+#define SM_PM_VCTRL 0x0030
+#define SM_PM_VMREF 0x0034
+#define SM_PM_VMV 0x0038
+#define SM_PM_IER 0x0040
+#define SM_PM_IDR 0x0044
+#define SM_PM_IMR 0x0048
+#define SM_PM_ISR 0x004c
+#define SM_PM_ICR 0x0050
+#define SM_PM_GCCTRL 0x0060
+#define SM_RTC_CTRL 0x0080
+#define SM_RTC_VAL 0x0084
+#define SM_RTC_TOP 0x0088
+#define SM_RTC_IER 0x0090
+#define SM_RTC_IDR 0x0094
+#define SM_RTC_IMR 0x0098
+#define SM_RTC_ISR 0x009c
+#define SM_RTC_ICR 0x00a0
+#define SM_WDT_CTRL 0x00b0
+#define SM_WDT_CLR 0x00b4
+#define SM_WDT_EXT 0x00b8
+#define SM_RC_RCAUSE 0x00c0
+#define SM_EIM_IER 0x0100
+#define SM_EIM_IDR 0x0104
+#define SM_EIM_IMR 0x0108
+#define SM_EIM_ISR 0x010c
+#define SM_EIM_ICR 0x0110
+#define SM_EIM_MODE 0x0114
+#define SM_EIM_EDGE 0x0118
+#define SM_EIM_LEVEL 0x011c
+#define SM_EIM_TEST 0x0120
+#define SM_EIM_NMIC 0x0124
+
+/* Bitfields in PM_CKSEL */
+#define SM_CPUSEL_OFFSET 0
+#define SM_CPUSEL_SIZE 3
+#define SM_CPUDIV_OFFSET 7
+#define SM_CPUDIV_SIZE 1
+#define SM_HSBSEL_OFFSET 8
+#define SM_HSBSEL_SIZE 3
+#define SM_HSBDIV_OFFSET 15
+#define SM_HSBDIV_SIZE 1
+#define SM_PBASEL_OFFSET 16
+#define SM_PBASEL_SIZE 3
+#define SM_PBADIV_OFFSET 23
+#define SM_PBADIV_SIZE 1
+#define SM_PBBSEL_OFFSET 24
+#define SM_PBBSEL_SIZE 3
+#define SM_PBBDIV_OFFSET 31
+#define SM_PBBDIV_SIZE 1
+
+/* Bitfields in PM_PLL0 */
+#define SM_PLLEN_OFFSET 0
+#define SM_PLLEN_SIZE 1
+#define SM_PLLOSC_OFFSET 1
+#define SM_PLLOSC_SIZE 1
+#define SM_PLLOPT_OFFSET 2
+#define SM_PLLOPT_SIZE 3
+#define SM_PLLDIV_OFFSET 8
+#define SM_PLLDIV_SIZE 8
+#define SM_PLLMUL_OFFSET 16
+#define SM_PLLMUL_SIZE 8
+#define SM_PLLCOUNT_OFFSET 24
+#define SM_PLLCOUNT_SIZE 6
+#define SM_PLLTEST_OFFSET 31
+#define SM_PLLTEST_SIZE 1
+
+/* Bitfields in PM_VCTRL */
+#define SM_VAUTO_OFFSET 0
+#define SM_VAUTO_SIZE 1
+#define SM_PM_VCTRL_VAL_OFFSET 8
+#define SM_PM_VCTRL_VAL_SIZE 7
+
+/* Bitfields in PM_VMREF */
+#define SM_REFSEL_OFFSET 0
+#define SM_REFSEL_SIZE 4
+
+/* Bitfields in PM_VMV */
+#define SM_PM_VMV_VAL_OFFSET 0
+#define SM_PM_VMV_VAL_SIZE 8
+
+/* Bitfields in PM_ICR */
+#define SM_LOCK0_OFFSET 0
+#define SM_LOCK0_SIZE 1
+#define SM_LOCK1_OFFSET 1
+#define SM_LOCK1_SIZE 1
+#define SM_WAKE_OFFSET 2
+#define SM_WAKE_SIZE 1
+#define SM_VOK_OFFSET 3
+#define SM_VOK_SIZE 1
+#define SM_VMRDY_OFFSET 4
+#define SM_VMRDY_SIZE 1
+#define SM_CKRDY_OFFSET 5
+#define SM_CKRDY_SIZE 1
+
+/* Bitfields in PM_GCCTRL */
+#define SM_OSCSEL_OFFSET 0
+#define SM_OSCSEL_SIZE 1
+#define SM_PLLSEL_OFFSET 1
+#define SM_PLLSEL_SIZE 1
+#define SM_CEN_OFFSET 2
+#define SM_CEN_SIZE 1
+#define SM_CPC_OFFSET 3
+#define SM_CPC_SIZE 1
+#define SM_DIVEN_OFFSET 4
+#define SM_DIVEN_SIZE 1
+#define SM_DIV_OFFSET 8
+#define SM_DIV_SIZE 8
+
+/* Bitfields in RTC_CTRL */
+#define SM_PCLR_OFFSET 1
+#define SM_PCLR_SIZE 1
+#define SM_TOPEN_OFFSET 2
+#define SM_TOPEN_SIZE 1
+#define SM_CLKEN_OFFSET 3
+#define SM_CLKEN_SIZE 1
+#define SM_PSEL_OFFSET 8
+#define SM_PSEL_SIZE 16
+
+/* Bitfields in RTC_VAL */
+#define SM_RTC_VAL_VAL_OFFSET 0
+#define SM_RTC_VAL_VAL_SIZE 31
+
+/* Bitfields in RTC_TOP */
+#define SM_RTC_TOP_VAL_OFFSET 0
+#define SM_RTC_TOP_VAL_SIZE 32
+
+/* Bitfields in RTC_ICR */
+#define SM_TOPI_OFFSET 0
+#define SM_TOPI_SIZE 1
+
+/* Bitfields in WDT_CTRL */
+#define SM_KEY_OFFSET 24
+#define SM_KEY_SIZE 8
+
+/* Bitfields in RC_RCAUSE */
+#define SM_POR_OFFSET 0
+#define SM_POR_SIZE 1
+#define SM_BOD_OFFSET 1
+#define SM_BOD_SIZE 1
+#define SM_EXT_OFFSET 2
+#define SM_EXT_SIZE 1
+#define SM_WDT_OFFSET 3
+#define SM_WDT_SIZE 1
+#define SM_NTAE_OFFSET 4
+#define SM_NTAE_SIZE 1
+#define SM_SERP_OFFSET 5
+#define SM_SERP_SIZE 1
+
+/* Bitfields in EIM_EDGE */
+#define SM_INT0_OFFSET 0
+#define SM_INT0_SIZE 1
+#define SM_INT1_OFFSET 1
+#define SM_INT1_SIZE 1
+#define SM_INT2_OFFSET 2
+#define SM_INT2_SIZE 1
+#define SM_INT3_OFFSET 3
+#define SM_INT3_SIZE 1
+
+/* Bitfields in EIM_LEVEL */
+
+/* Bitfields in EIM_TEST */
+#define SM_TESTEN_OFFSET 31
+#define SM_TESTEN_SIZE 1
+
+/* Bitfields in EIM_NMIC */
+#define SM_EN_OFFSET 0
+#define SM_EN_SIZE 1
+
+/* Bit manipulation macros */
+#define SM_BIT(name) \
+ (1 << SM_##name##_OFFSET)
+#define SM_BF(name,value) \
+ (((value) & ((1 << SM_##name##_SIZE) - 1)) \
+ << SM_##name##_OFFSET)
+#define SM_BFEXT(name,value) \
+ (((value) >> SM_##name##_OFFSET) \
+ & ((1 << SM_##name##_SIZE) - 1))
+#define SM_BFINS(name,value,old) \
+ (((old) & ~(((1 << SM_##name##_SIZE) - 1) \
+ << SM_##name##_OFFSET)) \
+ | SM_BF(name,value))
+
+/* Register access macros */
+#define sm_readl(port,reg) \
+ readl((port)->regs + SM_##reg)
+#define sm_writel(port,reg,value) \
+ writel((value), (port)->regs + SM_##reg)
+
+#endif /* __CPU_AT32AP_SM_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <asm/sysreg.h>
+
+#ifndef PART_SPECIFIC_BOOTSTRAP
+# define PART_SPECIFIC_BOOTSTRAP
+#endif
+
+#define SYSREG_MMUCR_I_OFFSET 2
+#define SYSREG_MMUCR_S_OFFSET 4
+
+#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
+#define CPUCR_INIT (SYSREG_BIT(BI) | SYSREG_BIT(BE) \
+ | SYSREG_BIT(FE) | SYSREG_BIT(RE) \
+ | SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
+
+ .text
+ .global _start
+_start:
+ PART_SPECIFIC_BOOTSTRAP
+
+ /* Reset the Status Register */
+ mov r0, lo(SR_INIT)
+ orh r0, hi(SR_INIT)
+ mtsr SYSREG_SR, r0
+
+ /* Reset CPUCR and invalidate the BTB */
+ mov r2, CPUCR_INIT
+ mtsr SYSREG_CPUCR, r2
+
+ /* Flush the caches */
+ mov r1, 0
+ cache r1[4], 8
+ cache r1[0], 0
+ sync 0
+
+ /* Reset the MMU to default settings */
+ mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
+ mtsr SYSREG_MMUCR, r0
+
+ /* Internal RAM should not need any initialization. We might
+ have to initialize external RAM here if the part doesn't
+ have internal RAM (or we may use the data cache) */
+
+ /* Jump to cacheable segment */
+ lddpc pc, 1f
+
+ .align 2
+1: .long 2f
+
+2: lddpc sp, sp_init
+
+ /*
+ * Relocate the data section and initialize .bss. Everything
+ * is guaranteed to be at least doubleword aligned by the
+ * linker script.
+ */
+ lddpc r12, .Ldata_vma
+ lddpc r11, .Ldata_lma
+ lddpc r10, .Ldata_end
+ sub r10, r12
+4: ld.d r8, r11++
+ sub r10, 8
+ st.d r12++, r8
+ brne 4b
+
+ mov r8, 0
+ mov r9, 0
+ lddpc r10, .Lbss_end
+ sub r10, r12
+4: sub r10, 8
+ st.d r12++, r8
+ brne 4b
+
+ /* Initialize the GOT pointer */
+ lddpc r6, got_init
+3: rsub r6, pc
+ ld.w pc, r6[start_u_boot@got]
+
+ .align 2
+ .type sp_init,@object
+sp_init:
+ .long CFG_INIT_SP_ADDR
+got_init:
+ .long 3b - _GLOBAL_OFFSET_TABLE_
+.Ldata_lma:
+ .long __data_lma
+.Ldata_vma:
+ .long _data
+.Ldata_end:
+ .long _edata
+.Lbss_end:
+ .long _end
#
# Copyright (c) 2005 blackfin.uclinux.org
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o start1.o interrupt.o cache.o cplbhdlr.o cplbmgr.o flush.o
-OBJS = cpu.o traps.o ints.o serial.o interrupts.o
+COBJS = cpu.o traps.o ints.o serial.o interrupts.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
#
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o start16.o reset.o
COBJS = serial.o interrupts.o cpu.o timer.o sc520.o
-AOBJS = sc520_asm.o
+SOBJS = sc520_asm.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
-all: .depend $(START) $(LIB)
+all: $(obj).depend $(START) $(LIB)
-$(LIB): $(COBJS) $(AOBJS)
- $(AR) crv $@ $(COBJS) $(AOBJS)
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(COBJS:.o=.c) $(AOBJS:.o=.S)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) $(AOBJS:.o=.S) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#include <common.h>
#include <config.h>
#include <pci.h>
+#ifdef CONFIG_SC520_SSI
#include <ssi.h>
+#endif
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/ic/sc520.h>
u32 dram_present=0;
u32 dram_ctrl;
-
+#ifdef CFG_SDRAM_DRCTMCTL
+ /* these memory control registers are set up in the assember part,
+ * in sc520_asm.S, during 'mem_init'. If we muck with them here,
+ * after we are running a stack in RAM, we have troubles. Besides,
+ * these refresh and delay values are better ? simply specified
+ * outright in the include/configs/{cfg} file since the HW designer
+ * simply dictates it.
+ */
+#else
int val;
int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
} else {
val = 3; /* 62.4us */
}
+
write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
val = read_mmcr_byte(SC520_DRCTMCTL);
val |= 1;
}
write_mmcr_byte(SC520_DRCTMCTL, val);
-
+#endif
/* We read-back the configuration of the dram
* controller that the assembly code wrote */
dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
-
bd->bi_dram[0].start = 0;
if (dram_ctrl & 0x80) {
/* bank 0 enabled */
{
int i;
-# if 0
+# if 1
printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
#endif
if (irq < 0 || irq > 15) {
.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */
.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */
.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */
+.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */
.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */
.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
incl %edi
loop cleanuplp
+#if defined CFG_SDRAM_DRCTMCTL
+ /* just have your hardware desinger _GIVE_ you what you need here! */
+ movl $DRCTMCTL, %edi
+ movb $CFG_SDRAM_DRCTMCTL,%al
+ movb (%edi), %al
+#else
#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T)
/* set the CAS latency now since it is hard to do
* when we run from the RAM */
orb $0x10, %al
#endif
movb %al, (%edi)
+#endif
#endif
movl $DRCCTL, %edi /* DRAM Control register */
movb $0x3,%al /* Load mode register cmd */
shll $22, %eax
movl %eax, %ebx
-done: movl %ebx, %eax
+done:
+ movl %ebx, %eax
+
+#if CFG_SDRAM_ECC_ENABLE
+ /* A nominal memory test: just a byte at each address line */
+ movl %eax, %ecx
+ shrl $0x1, %ecx
+ movl $0x1, %edi
+memtest0:
+ movb $0xa5, (%edi)
+ cmpb $0xa5, (%edi)
+ jne out
+ shrl $1, %ecx
+ andl %ecx,%ecx
+ jz set_ecc
+ shll $1, %edi
+ jmp memtest0
+
+set_ecc:
+ /* clear all ram with a memset */
+ movl %eax, %ecx
+ xorl %esi, %esi
+ xorl %edi, %edi
+ xorl %eax, %eax
+ shrl $2, %ecx
+ cld
+ rep stosl
+ /* enable read, write buffers */
+ movb $0x11, %al
+ movl $DBCTL, %edi
+ movb %al, (%edi)
+ /* enable NMI mapping for ECC */
+ movl $ECCINT, %edi
+ mov $0x10, %al
+ movb %al, (%edi)
+ /* Turn on ECC */
+ movl $ECCCTL, %edi
+ mov $0x05, %al
+ movb %al, (%edi)
+#endif
+out:
+ movl %ebx, %eax
jmp *%ebp
-
#endif /* CONFIG_SC520 */
#
-# (C) Copyright 2000, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = serial.o interrupts.o cpu.o timer.o pci.o
+COBJS = serial.o interrupts.o cpu.o timer.o pci.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
include $(TOPDIR)/config.mk
-LIB := libnpe.a
+LIB := $(obj)libnpe.a
-CFLAGS += -I$(TOPDIR)/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB
+LOCAL_CFLAGS += -I$(TOPDIR)/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB
+CFLAGS += $(LOCAL_CFLAGS)
+HOST_CFLAGS += $(LOCAL_CFLAGS)
-OBJS := npe.o \
+COBJS := npe.o \
miiphy.o \
IxOsalBufferMgt.o \
IxOsalIoMem.o \
IxNpeMhSolicitedCbMgr.o \
IxNpeMhUnsolicitedCbMgr.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
all: $(LIB)
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
+
+#########################################################################
#
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = cpu.o speed.o interrupts.o serial.o
+COBJS = cpu.o speed.o interrupts.o serial.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# CFLAGS += -DET_DEBUG
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START =
-OBJS = serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o
+COBJS = serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#else
fecp->fec_hash_table_high = 0;
fecp->fec_hash_table_low = 0;
+#endif
#endif
/* Set maximum receive buffer size.
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
+#if defined(CONFIG_M5282)
/* Initialize RAMBAR1: locate SRAM and validate it */
move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
movec %d0, %RAMBAR0
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
+#endif
#endif
/* if we come from a pre-loader we have no exception table and
* therefore no VBR to set
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = cpu.o interrupts.o
+COBJS = cpu.o interrupts.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \
+COBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \
cpu.o interrupts.o incaip_clock.o
SOBJS = incaip_wdt.o cache.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2003
# Martin Winistoerfer, martinwinistoerfer@gmx.ch.
#
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
+
+START = start.o
+COBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o
-START = start.S
-OBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
-all: .depend $(START) $(LIB)
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
-OBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \
+SOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
+COBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \
loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o
-all: .depend $(START) $(ASOBJS) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(ASOBJS) $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
- defined(CONFIG_TQM5200)
+ defined(CONFIG_TQM5200) || defined(CONFIG_V38B)
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
# else
/*
+ * (C) Copyright 2006
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de
+ *
* (C) Copyright -2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* MA 02111-1307 USA
*/
-/*
- * interrupts.c - just enough support for the decrementer/timer
+/* this section was ripped out of arch/ppc/syslib/mpc52xx_pic.c in the
+ * Linux 2.6 source with the following copyright.
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
*/
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
-int interrupt_init_cpu (ulong *decrementer_count)
+struct irq_action {
+ interrupt_handler_t *handler;
+ void *arg;
+ ulong count;
+};
+
+static struct irq_action irq_handlers[NR_IRQS];
+
+static struct mpc5xxx_intr *intr;
+static struct mpc5xxx_sdma *sdma;
+
+static void mpc5xxx_ic_disable(unsigned int irq)
+{
+ u32 val;
+
+ if (irq == MPC5XXX_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << 11);
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC5XXX_IRQ1) {
+ BUG();
+ } else if (irq <= MPC5XXX_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1)));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC5XXX_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE);
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void mpc5xxx_ic_enable(unsigned int irq)
+{
+ u32 val;
+
+ if (irq == MPC5XXX_IRQ0) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << 11;
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC5XXX_IRQ1) {
+ BUG();
+ } else if (irq <= MPC5XXX_IRQ3) {
+ val = in_be32(&intr->ctrl);
+ val |= 1 << (10 - (irq - MPC5XXX_IRQ1));
+ out_be32(&intr->ctrl, val);
+ } else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
+ val = in_be32(&intr->main_mask);
+ val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)));
+ out_be32(&intr->main_mask, val);
+ } else if (irq < MPC5XXX_PERP_IRQ_BASE) {
+ val = in_be32(&sdma->IntMask);
+ val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
+ out_be32(&sdma->IntMask, val);
+ } else {
+ val = in_be32(&intr->per_mask);
+ val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)));
+ out_be32(&intr->per_mask, val);
+ }
+}
+
+static void mpc5xxx_ic_ack(unsigned int irq)
+{
+ u32 val;
+
+ /*
+ * Only some irqs are reset here, others in interrupting hardware.
+ */
+
+ switch (irq) {
+ case MPC5XXX_IRQ0:
+ val = in_be32(&intr->ctrl);
+ val |= 0x08000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC5XXX_CCS_IRQ:
+ val = in_be32(&intr->enc_status);
+ val |= 0x00000400;
+ out_be32(&intr->enc_status, val);
+ break;
+ case MPC5XXX_IRQ1:
+ val = in_be32(&intr->ctrl);
+ val |= 0x04000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC5XXX_IRQ2:
+ val = in_be32(&intr->ctrl);
+ val |= 0x02000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ case MPC5XXX_IRQ3:
+ val = in_be32(&intr->ctrl);
+ val |= 0x01000000;
+ out_be32(&intr->ctrl, val);
+ break;
+ default:
+ if (irq >= MPC5XXX_SDMA_IRQ_BASE
+ && irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) {
+ out_be32(&sdma->IntPend,
+ 1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
+ }
+ break;
+ }
+}
+
+static void mpc5xxx_ic_disable_and_ack(unsigned int irq)
+{
+ mpc5xxx_ic_disable(irq);
+ mpc5xxx_ic_ack(irq);
+}
+
+static void mpc5xxx_ic_end(unsigned int irq)
+{
+ mpc5xxx_ic_enable(irq);
+}
+
+void mpc5xxx_init_irq(void)
+{
+ u32 intr_ctrl;
+
+ /* Remap the necessary zones */
+ intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
+ sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA);
+
+ /* Disable all interrupt sources. */
+ out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
+ out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
+ out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
+ out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
+ intr_ctrl = in_be32(&intr->ctrl);
+ intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
+ 0x00ff0000 | /* IRQ 0-3 level sensitive low active */
+ 0x00001000 | /* MEE master external enable */
+ 0x00000000 | /* 0 means disable IRQ 0-3 */
+ 0x00000001; /* CEb route critical normally */
+ out_be32(&intr->ctrl, intr_ctrl);
+
+ /* Zero a bunch of the priority settings. */
+ out_be32(&intr->per_pri1, 0);
+ out_be32(&intr->per_pri2, 0);
+ out_be32(&intr->per_pri3, 0);
+ out_be32(&intr->main_pri1, 0);
+ out_be32(&intr->main_pri2, 0);
+}
+
+int mpc5xxx_get_irq(struct pt_regs *regs)
+{
+ u32 status;
+ int irq = -1;
+
+ status = in_be32(&intr->enc_status);
+
+ if (status & 0x00000400) { /* critical */
+ irq = (status >> 8) & 0x3;
+ if (irq == 2) /* high priority peripheral */
+ goto peripheral;
+ irq += MPC5XXX_CRIT_IRQ_BASE;
+ } else if (status & 0x00200000) { /* main */
+ irq = (status >> 16) & 0x1f;
+ if (irq == 4) /* low priority peripheral */
+ goto peripheral;
+ irq += MPC5XXX_MAIN_IRQ_BASE;
+ } else if (status & 0x20000000) { /* peripheral */
+ peripheral:
+ irq = (status >> 24) & 0x1f;
+ if (irq == 0) { /* bestcomm */
+ status = in_be32(&sdma->IntPend);
+ irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1;
+ } else
+ irq += MPC5XXX_PERP_IRQ_BASE;
+ }
+
+ return irq;
+}
+
+/****************************************************************************/
+
+int interrupt_init_cpu(ulong * decrementer_count)
{
*decrementer_count = get_tbclk() / CFG_HZ;
+ mpc5xxx_init_irq();
+
return (0);
}
/*
* Handle external interrupts
*/
-void
-external_interrupt(struct pt_regs *regs)
+void external_interrupt(struct pt_regs *regs)
{
- puts("external_interrupt (oops!)\n");
+ int irq, unmask = 1;
+
+ irq = mpc5xxx_get_irq(regs);
+
+ mpc5xxx_ic_disable_and_ack(irq);
+
+ enable_interrupts();
+
+ if (irq_handlers[irq].handler != NULL)
+ (*irq_handlers[irq].handler) (irq_handlers[irq].arg);
+ else {
+ printf("\nBogus External Interrupt IRQ %d\n", irq);
+ /*
+ * turn off the bogus interrupt, otherwise it
+ * might repeat forever
+ */
+ unmask = 0;
+ }
+
+ if (unmask)
+ mpc5xxx_ic_end(irq);
}
-void
-timer_interrupt_cpu (struct pt_regs *regs)
+void timer_interrupt_cpu(struct pt_regs *regs)
{
/* nothing to do here */
return;
* Install and free a interrupt handler.
*/
-void
-irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
{
+ if (irq < 0 || irq >= NR_IRQS) {
+ printf("irq_install_handler: bad irq number %d\n", irq);
+ return;
+ }
+ if (irq_handlers[irq].handler != NULL)
+ printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
+ (ulong) handler, (ulong) irq_handlers[irq].handler);
+
+ irq_handlers[irq].handler = handler;
+ irq_handlers[irq].arg = arg;
+
+ mpc5xxx_ic_enable(irq);
}
-void
-irq_free_handler(int vec)
+void irq_free_handler(int irq)
{
+ if (irq < 0 || irq >= NR_IRQS) {
+ printf("irq_free_handler: bad irq number %d\n", irq);
+ return;
+ }
+
+ mpc5xxx_ic_disable(irq);
+ irq_handlers[irq].handler = NULL;
+ irq_handlers[irq].arg = NULL;
}
/****************************************************************************/
-void
-do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
+void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
- puts("IRQ related functions are unimplemented currently.\n");
+ int irq, re_enable;
+ u32 intr_ctrl;
+ char *irq_config[] = { "level sensitive, active high",
+ "edge sensitive, rising active edge",
+ "edge sensitive, falling active edge",
+ "level sensitive, active low"
+ };
+
+ re_enable = disable_interrupts();
+
+ intr_ctrl = in_be32(&intr->ctrl);
+ printf("Interrupt configuration:\n");
+
+ for (irq = 0; irq <= 3; irq++) {
+ printf("IRQ%d: %s\n", irq,
+ irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]);
+ }
+
+ puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n");
+
+ for (irq = 0; irq < NR_IRQS; irq++)
+ if (irq_handlers[irq].handler != NULL)
+ printf("%02d %08lx %08lx %ld\n", irq,
+ (ulong) irq_handlers[irq].handler,
+ (ulong) irq_handlers[irq].arg,
+ irq_handlers[irq].count);
+
+ if (re_enable)
+ enable_interrupts();
}
+#endif
psc->psc_buffer_8 = c;
}
+#if defined(CONFIG_SERIAL_MULTI)
+void serial_putc_raw_dev(unsigned long dev_base, const char c)
+#else
+void serial_putc_raw(const char c)
+#endif
+{
+#if defined(CONFIG_SERIAL_MULTI)
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+#else
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
+ /* Wait for last character to go. */
+ while (!(psc->psc_status & PSC_SR_TXEMP))
+ ;
+
+ psc->psc_buffer_8 = c;
+}
+
+
#if defined(CONFIG_SERIAL_MULTI)
void serial_puts_dev (unsigned long dev_base, const char *s)
#else
psc->ctlr = div & 0xff;
}
+#if defined(CONFIG_SERIAL_MULTI)
+void serial_setrts_dev (unsigned long dev_base, int s)
+#else
+void serial_setrts(int s)
+#endif
+{
+#if defined(CONFIG_SERIAL_MULTI)
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+#else
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
+
+ if (s) {
+ /* Assert RTS (become LOW) */
+ psc->op1 = 0x1;
+ }
+ else {
+ /* Negate RTS (become HIGH) */
+ psc->op0 = 0x1;
+ }
+}
+
+#if defined(CONFIG_SERIAL_MULTI)
+int serial_getcts_dev (unsigned long dev_base)
+#else
+int serial_getcts(void)
+#endif
+{
+#if defined(CONFIG_SERIAL_MULTI)
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+#else
+ volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
+#endif
+
+ return (psc->ip & 0x1) ? 0 : 1;
+}
+
#if defined(CONFIG_SERIAL_MULTI)
int serial0_init(void)
{
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-ASOBJS = io.o fec_dma_tasks.o
-OBJS = cpu.o cpu_init.o dramSetup.o fec.o i2c.o \
+SOBJS = io.o fec_dma_tasks.o
+COBJS = cpu.o cpu_init.o dramSetup.o fec.o i2c.o \
interrupts.o loadtask.o speed.o \
traps.o uart.o pci.o
-all: .depend $(START) $(ASOBJS) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(ASOBJS) $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
hose->region_count = 3;
hose->cfg_addr = &(xcpci->cfg_adr);
- hose->cfg_data = CONFIG_PCI_CFG_BUS;
+ hose->cfg_data = (volatile unsigned char *)CONFIG_PCI_CFG_BUS;
pci_set_ops(hose,
mpc8220_pci_read_config_byte,
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)drivers/epic)
+$(shell mkdir -p $(obj)drivers/i2c)
+endif
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
-START = start.S
-OBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \
- drivers/epic/epic1.o drivers/i2c/i2c.o pci.o bedbug_603e.o
+START = start.o
+COBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \
+ drivers/epic/epic1.o drivers/i2c/i2c.o pci.o
+COBJS_LN = bedbug_603e.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
-bedbug_603e.c:
- ln -s ../mpc8260/bedbug_603e.c bedbug_603e.c
+$(obj)bedbug_603e.c:
+ ln -s $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
+++ /dev/null
-##########################################################################
-#
-# Copyright Motorola, Inc. 1997
-# ALL RIGHTS RESERVED
-#
-# You are hereby granted a copyright license to use, modify, and
-# distribute the SOFTWARE so long as this entire notice is retained
-# without alteration in any modified and/or redistributed versions,
-# and that such modified versions are clearly identified as such.
-# No licenses are granted by implication, estoppel or otherwise under
-# any patents or trademarks of Motorola, Inc.
-#
-# The SOFTWARE is provided on an "AS IS" basis and without warranty.
-# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS
-# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED
-# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
-# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
-# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS
-# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS.
-#
-# To the maximum extent permitted by applicable law, IN NO EVENT SHALL
-# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
-# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
-# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR
-# INABILITY TO USE THE SOFTWARE.
-#
-############################################################################
-TARGET = libdma.a
-
-DEBUG = -DDMADBG
-LST = -Hanno -S
-OPTIM =
-CC = /risc/tools/pkgs/metaware/bin/hcppc
-CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc
-CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM)
-PREP = $(CC) $(CFLAGS) -P
-
-# Assembler used to build the .s files (for the board version)
-
-ASOPT = -big_si -c
-ASDEBUG = -l -fm
-AS = /risc/tools/pkgs/metaware/bin/asppc
-
-# Linker to bring .o files together into an executable.
-
-LKOPT = -Bbase=0 -q -r -Qn
-LKCMD =
-LINK = /risc/tools/pkgs/metaware/bin/ldppc $(LKCMD) $(LKOPT)
-
-# DOS Utilities
-
-DEL = rm
-COPY = cp
-LIST = ls
-
-OBJECTS = dma1.o dma2.o
-
-all: $(TARGET)
-
-$(TARGET): $(OBJECTS)
- $(LINK) $(OBJECTS) -o $@
-
-objects: dma1.o
-
-clean:
- $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS)
-
-.s.o:
- $(DEL) -f $*.i
- $(PREP) -Hasmcpp $<
- $(AS) $(ASOPT) $*.i
-# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst
-
-.c.o:
- $(CCobj) $<
-
-.c.s:
- $(CCobj) $(LST) $<
-
-dma1.o: dma_export.h dma.h dma1.c
-
-dma2.o: dma.h dma2.s
+++ /dev/null
-##########################################################################
-#
-# makefile_pc for use with mksnt tools drivers/dma
-#
-# Copyright Motorola, Inc. 1997
-# ALL RIGHTS RESERVED
-#
-# You are hereby granted a copyright license to use, modify, and
-# distribute the SOFTWARE so long as this entire notice is retained
-# without alteration in any modified and/or redistributed versions,
-# and that such modified versions are clearly identified as such.
-# No licenses are granted by implication, estoppel or otherwise under
-# any patents or trademarks of Motorola, Inc.
-#
-# The SOFTWARE is provided on an "AS IS" basis and without warranty.
-# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS
-# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED
-# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
-# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
-# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS
-# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS.
-#
-# To the maximum extent permitted by applicable law, IN NO EVENT SHALL
-# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
-# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
-# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR
-# INABILITY TO USE THE SOFTWARE.
-#
-############################################################################
-TARGET = libdma.a
-
-DEBUG = -DDMADBG
-LST = -Hanno -S
-OPTIM =
-CC = m:/old_tools/tools/hcppc/bin/hcppc
-CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc
-CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM)
-PREP = $(CC) $(CFLAGS) -P
-
-# Assembler used to build the .s files (for the board version)
-
-ASOPT = -big_si -c
-ASDEBUG = -l -fm
-AS = m:/old_tools/tools/hcppc/bin/asppc
-
-# Linker to bring .o files together into an executable.
-
-LKOPT = -Bbase=0 -q -r -Qn
-LKCMD =
-LINK = m:/old_tools/tools/hcppc/bin/ldppc $(LKCMD) $(LKOPT)
-
-# DOS Utilities
-
-DEL = rm
-COPY = cp
-LIST = ls
-
-OBJECTS = dma1.o dma2.o
-
-all: $(TARGET)
-
-$(TARGET): $(OBJECTS)
- $(LINK) $(OBJECTS) -o $@
-
-objects: dma1.o
-
-clean:
- $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS)
-
-.s.o:
- $(DEL) -f $*.i
- $(PREP) -Hasmcpp $<
- $(AS) $(ASOPT) $*.i
-# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst
-
-.c.o:
- $(CCobj) $<
-
-.c.s:
- $(CCobj) $(LST) $<
-
-dma1.o: dma_export.h dma.h dma1.c
- $(CCobj) $<
-
-dma2.o: dma.h dma2.s
- $(DEL) -f $*.i
- $(PREP) -Hasmcpp $<
- $(AS) $(ASOPT) $*.i
+++ /dev/null
-CONTENT:
-
- dma.h
- dma1.c
- dma2.s
-
-WHAT ARE THESE FILES:
-
-These files contain MPC8240 (Kahlua) DMA controller
-driver routines. The driver routines are not
-written for any specific operating system.
-They serves the purpose of code sample, and
-jump-start for using the MPC8240 DMA controller.
-
-For the reason of correctness of C language
-syntax, these files are compiled by Metaware
-C compiler and assembler.
-
-ENDIAN NOTATION:
-
-The algorithm is designed for big-endian mode,
-software is responsible for byte swapping.
-
-USAGE:
-
-1. The host system that is running on MPC8240
- or using MPC8240 as I/O device shall link
- the files listed here. The memory location
- of driver routines shall take into account of
- that driver routines need to run in supervisor
- mode and they process DMA controller interrupt.
-
-2. The host system is responsible for configuring
- the MPC8240 including Embedded Utilities Memory
- Block. Since the DMA controller on MPC8240 can
- be accessed by either local 603e core or the host
- that MPC8240 serves as I/O processor through host
- PCI configuration, it is important that the local
- processor uses EUMBBAR to access its local DMA
- controller while the PCI master uses I/O
- processor's PCSRBAR to access the DMA controller
- on I/O device.
-
- To qualify whether is EUMBBAR or PCSRBAR, one
- additional parameter is requied from the host
- system, LOCAL or REMOTE so that the base value
- can be correctly interpreted.
-
-3. If the host system is also using the EPIC unit
- on MPC8240, the system can register the
- DMA_ISR with the EPIC including other
- desired resources.
-
- If the host system does not using the EPIC unit
- on MPC8240, DMA_ISR function can be called for
- each desired time interval.
-
- In both cases, the host system is free to
- provide its own interrupt service routine.
-
-4. To start a direct mode DMA transaction,
- use DMA_Bld_Curr with the start parameter
- set to 1.
-
- To start a chaining mode DMA transaction,
- the application shall build descriptors
- in memory first, next, use DMA_Bld_Desp
- with the start parameter set to 1.
-
-5. DMA_Start function clears, then sets the CS
- bit of DMA mode register.
-
- DMA_Halt function clears the CS bit of DMA
- mode register.
-
- These functions can be used to start and
- halt the DMA transaction.
-
- If the chaining descriptors has been
- modified since the last time a DMA
- transaction started, use DMA_Chn_Cnt
- function to let DMA controller process
- the modified descriptor chain without
- stopping or disturbing the current DMA
- transaction.
-
- It is the host system's responsibility of
- setting up the correct DMA transfer mode
- and pass the correct memory address parameters.
-
-6. It is the host system's responsibility of
- queueing the DMA I/O request. The host
- system can call the DMA_ISR with its own
- desired interrupt service subroutines to
- handle each individual interrupt and queued
- DMA I/O requests.
-
-7. The DMA driver routines contains a set
- of utilities, Set and Get, for host system
- to query and modify the desired DMA registers.
+++ /dev/null
-#ifndef DMA_H
-#define DMA_H
-/*******************************************************
- *
- * copyright @ Motorola 1999
- *
- *******************************************************/
-#define NUM_DMA_REG 7
-#define DMA_MR_REG 0
-#define DMA_SR_REG 1
-#define DMA_CDAR_REG 2
-#define DMA_SAR_REG 3
-#define DMA_DAR_REG 4
-#define DMA_BCR_REG 5
-#define DMA_NDAR_REG 6
-
-typedef enum _dmastatus
-{
- DMASUCCESS = 0x1000,
- DMALMERROR,
- DMAPERROR,
- DMACHNBUSY,
- DMAEOSINT,
- DMAEOCAINT,
- DMAINVALID,
- DMANOEVENT,
-} DMAStatus;
-
-typedef enum _location
-{
- LOCAL = 0, /* local processor accesses on board DMA,
- local processor's eumbbar is required */
- REMOTE = 1, /* PCI master accesses DMA on I/O board,
- I/O processor's pcsrbar is required */
-} LOCATION;
-
-typedef enum dma_mr_bit
-{
- IRQS = 0x00080000,
- PDE = 0x00040000,
- DAHTS = 0x00030000,
- SAHTS = 0x0000c000,
- DAHE = 0x00002000,
- SAHE = 0x00001000,
- PRC = 0x00000c00,
- EIE = 0x00000080,
- EOTIE = 0x00000040,
- DL = 0x00000008,
- CTM = 0x00000004,
- CC = 0x00000002,
- CS = 0x00000001,
-} DMA_MR_BIT;
-
-typedef enum dma_sr_bit
-{
- LME = 0x00000080,
- PE = 0x00000010,
- CB = 0x00000004,
- EOSI = 0x00000002,
- EOCAI = 0x00000001,
-} DMA_SR_BIT;
-
-/* structure for DMA Mode Register */
-typedef struct _dma_mr
-{
- unsigned int reserved0 : 12;
- unsigned int irqs : 1;
- unsigned int pde : 1;
- unsigned int dahts : 2;
- unsigned int sahts : 2;
- unsigned int dahe : 1;
- unsigned int sahe : 1;
- unsigned int prc : 2;
- unsigned int reserved1 : 1;
- unsigned int eie : 1;
- unsigned int eotie : 1;
- unsigned int reserved2 : 3;
- unsigned int dl : 1;
- unsigned int ctm : 1;
- /* if chaining mode is enabled, any time, user can modify the
- * descriptor and does not need to halt the current DMA transaction.
- * Set CC bit, enable DMA to process the modified descriptors
- * Hardware will clear this bit each time, DMA starts.
- */
- unsigned int cc : 1;
- /* cs bit has dua role, halt the current DMA transaction and
- * (re)start DMA transaction. In chaining mode, if the descriptor
- * needs modification, cs bit shall be used not the cc bit.
- * Hardware will not set/clear this bit each time DMA transaction
- * stops or starts. Software shall do it.
- *
- * cs bit shall not be used to halt chaining DMA transaction for
- * modifying the descriptor. That is the role of CC bit.
- */
- unsigned int cs : 1;
-} DMA_MR;
-
-/* structure for DMA Status register */
-typedef struct _dma_sr
-{
- unsigned int reserved0 : 24;
- unsigned int lme : 1;
- unsigned int reserved1 : 2;
- unsigned int pe : 1;
- unsigned int reserved2 : 1;
- unsigned int cb : 1;
- unsigned int eosi : 1;
- unsigned int eocai : 1;
-} DMA_SR;
-
-/* structure for DMA current descriptor address register */
-typedef struct _dma_cdar
-{
- unsigned int cda : 27;
- unsigned int snen : 1;
- unsigned int eosie : 1;
- unsigned int ctt : 2;
- unsigned int eotd : 1;
-} DMA_CDAR;
-
-/* structure for DMA byte count register */
-typedef struct _dma_bcr
-{
- unsigned int reserved : 6;
- unsigned int bcr : 26;
-} DMA_BCR;
-
-/* structure for DMA Next Descriptor Address register */
-typedef struct _dma_ndar
-{
- unsigned int nda : 27;
- unsigned int ndsnen : 1;
- unsigned int ndeosie: 1;
- unsigned int ndctt : 2;
- unsigned int eotd : 1;
-} DMA_NDAR;
-
-/* structure for DMA current transaction info */
-typedef struct _dma_curr
-{
- unsigned int src_addr;
- unsigned int dest_addr;
- unsigned int byte_cnt;
-} DMA_CURR;
-
-/************************* Kernel API********************
- * Kernel APIs are used to interface with O.S. kernel.
- * They are the functions required by O.S. kernel to
- * provide I/O service.
- ********************************************************/
-
-/**************DMA Device Control Functions ********/
-
-/**
- * Note:
- *
- * In all following functions, the host (KAHLUA) processor has a
- * choice of accessing on board local DMA (LOCAL),
- * or DMA on a distributed KAHLUA (REMOTE). In either case,
- * the caller shall pass the configured embedded utility memory
- * block base address relative to the DMA. If LOCAL DMA is used,
- * this parameter shall be EUMBBAR, if REMOTE is used, the
- * parameter shall be the corresponding PCSRBAR.
- **/
-
-/**************************************************************
- * function: DMA_Get_Stat
- *
- * description: return the content of status register of
- * the given DMA channel
- * if error, return DMAINVALID. Otherwise return
- * DMASUCCESS.
- *
- **************************************************************/
-static DMAStatus DMA_Get_Stat( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_SR * );
-
-/**************************************************************
- * function: DMA_Get_Mode
- *
- * description: return the content of mode register of the
- * given DMA channel
- * if error, return DMAINVALID. Otherwise return DMASUCCESS.
- *
- **************************************************************/
-static DMAStatus DMA_Get_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR * );
-
-/**************************************************************
- * function: DMA_Set_Mode
- *
- * description: Set a new mode to a given DMA channel
- * return DMASUCCESS if success, otherwise return DMACHNINVALID
- *
- * note: It is not a good idea of changing the DMA mode during
- * the middle of a transaction.
- **************************************************************/
-static DMAStatus DMA_Set_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR mode );
-
-/*************************************************************
- * function: DMA_ISR
- *
- * description: DMA interrupt service routine
- * return DMAStatus based on the status
- *
- *************************************************************/
-static DMAStatus DMA_ISR( unsigned int eumbbar,
- unsigned int channel,
- DMAStatus (*lme_func)( unsigned int, unsigned int, DMAStatus ),
- DMAStatus (*pe_func) ( unsigned int, unsigned int, DMAStatus ),
- DMAStatus (*eosi_func)( unsigned int, unsigned int, DMAStatus ),
- DMAStatus (*eocai_func)(unsigned int, unsigned int, DMAStatus ));
-
-static DMAStatus dma_error_func( unsigned int, unsigned int, DMAStatus );
-
-/********************* DMA I/O function ********************/
-
-/************************************************************
- * function: DMA_Start
- *
- * description: start a given DMA channel transaction
- * return DMASUCCESS if success, otherwise return DMACHNINVALID
- *
- * note: this function will clear DMA_MR(CC) first, then
- * set DMA_MR(CC).
- ***********************************************************/
-static DMAStatus DMA_Start( LOCATION, unsigned int eumbbar,unsigned int channel );
-
-/***********************************************************
- * function: DMA_Halt
- *
- * description: halt the current dma transaction on the specified
- * channel.
- * return DMASUCCESS if success, otherwise return DMACHNINVALID
- *
- * note: if the specified DMA channel is idle, nothing happens
- *************************************************************/
-static DMAStatus DMA_Halt( LOCATION, unsigned int eumbbar,unsigned int channel );
-
-/*************************************************************
- * function: DMA_Chn_Cnt
- *
- * description: set the DMA_MR(CC) bit for a given channel
- * that is in chaining mode.
- * return DMASUCCESS if successfule, otherwise return DMACHNINVALID
- *
- * note: if the given channel is not in chaining mode, nothing
- * happen.
- *
- *************************************************************/
-static DMAStatus DMA_Chn_Cnt( LOCATION, unsigned int eumbbar,unsigned int channel );
-
-/*********************** App. API ***************************
- * App. API are the APIs Kernel provides for the application
- * level program
- ************************************************************/
-/**************************************************************
- * function: DMA_Bld_Curr
- *
- * description: set current src, dest, byte count registers
- * according to the desp for a given channel
- *
- * if the given channel is busy, no change made,
- * return DMACHNBUSY.
- *
- * otherwise return DMASUCCESS.
- *
- * note:
- **************************************************************/
-static DMAStatus DMA_Bld_Curr( LOCATION,
- unsigned int eumbbar,
- unsigned int channel,
- DMA_CURR desp );
-
-/**************************************************************
- * function: DMA_Poke_Curr
- *
- * description: poke the current src, dest, byte count registers
- * for a given channel.
- *
- * return DMASUCCESS if no error otherwise return DMACHNERROR
- *
- * note: Due to the undeterministic parallelism, in chaining
- * mode, the value returned by this function shall
- * be taken as reference when the query is made rather
- * than the absolute snapshot when the value is returned.
- **************************************************************/
-static DMAStatus DMA_Poke_Curr( LOCATION,
- unsigned int eumbbar,
- unsigned int channel,
- DMA_CURR* desp );
-
-/**************************************************************
- * function: DMA_Bld_Desp
- *
- * description: set current descriptor address register
- * according to the desp for a given channel
- *
- * if the given channel is busy return DMACHNBUSY
- * and no change made, otherwise return DMASUCCESS.
- *
- * note:
- **************************************************************/
-static DMAStatus DMA_Bld_Desp( LOCATION host,
- unsigned int eumbbar,
- unsigned int channel,
- DMA_CDAR desp );
-
-/**************************************************************
- * function: DMA_Poke_Desp
- *
- * description: poke the current descriptor address register
- * for a given channel
- *
- * return DMASUCCESS if no error otherwise return
- * DMAINVALID
- *
- * note: Due to the undeterministic parallellism of DMA operation,
- * the value returned by this function shall be taken as
- * the most recently used descriptor when the last time
- * DMA starts a chaining mode operation.
- **************************************************************/
-static DMAStatus DMA_Poke_Desp( LOCATION,
- unsigned int eumbbar,
- unsigned int channel,
- DMA_CDAR *desp );
-
-#endif
+++ /dev/null
-/************************************************************
- *
- * copyright @ Motorola, 1999
- *
- * App. API
- *
- * App. API are the APIs Kernel provides for the application
- * level program
- *
- ************************************************************/
-#include "dma_export.h"
-#include "dma.h"
-
-/* Define a macro to use an optional application-layer print function, if
- * one was passed to the library during initialization. If there was no
- * function pointer passed, this protects against referencing a NULL pointer.
- * Also define The global variable that holds the passed pointer.
- */
-#define PRINT if ( app_print ) app_print
-static int (*app_print)(char *,...);
-
-/* Set by call to get_eumbbar during DMA_Initialize.
- * This could be globally available to the library, but there is
- * an advantage to passing it as a parameter: it is already in a register
- * and doesn't have to be loaded from memory. Also, that is the way the
- * library was already implemented and I don't want to change it without
- * a more detailed analysis.
- * It is being set as a global variable during initialization to hide it from
- * the DINK application layer, because it is Kahlua-specific. I think that
- * get_eumbbar, load_runtime_reg, and store_runtime_reg should be defined in
- * a Kahlua-specific library dealing with the embedded utilities memory block.
- * Right now, get_eumbbar is defined in dink32/kahlua.s. The other two are
- * defined in dink32/drivers/i2c/i2c2.s, drivers/dma/dma2.s, etc.
- */
-static unsigned int Global_eumbbar = 0;
-extern unsigned int get_eumbbar();
-
-
-extern unsigned int load_runtime_reg( unsigned int eumbbar, unsigned int reg );
-#pragma Alias( load_runtime_reg, "load_runtime_reg" );
-
-extern void store_runtime_reg( unsigned int eumbbar, unsigned int reg, unsigned int val );
-#pragma Alias( store_runtime_reg, "store_runtime_reg" );
-
-unsigned int dma_reg_tb[][14] = {
- /* local DMA registers */
- {
- /* DMA_0_MR */ 0x00001100,
- /* DMA_0_SR */ 0x00001104,
- /* DMA_0_CDAR */ 0x00001108,
- /* DMA_0_SAR */ 0x00001110,
- /* DMA_0_DAR */ 0x00001118,
- /* DMA_0_BCR */ 0x00001120,
- /* DMA_0_NDAR */ 0x00001124,
- /* DMA_1_MR */ 0x00001200,
- /* DMA_1_SR */ 0x00001204,
- /* DMA_1_CDAR */ 0x00001208,
- /* DMA_1_SAR */ 0x00001210,
- /* DMA_1_DAR */ 0x00001218,
- /* DMA_1_BCR */ 0x00001220,
- /* DMA_1_NDAR */ 0x00001224,
- },
- /* remote DMA registers */
- {
- /* DMA_0_MR */ 0x00000100,
- /* DMA_0_SR */ 0x00000104,
- /* DMA_0_CDAR */ 0x00000108,
- /* DMA_0_SAR */ 0x00000110,
- /* DMA_0_DAR */ 0x00000118,
- /* DMA_0_BCR */ 0x00000120,
- /* DMA_0_NDAR */ 0x00000124,
- /* DMA_1_MR */ 0x00000200,
- /* DMA_1_SR */ 0x00000204,
- /* DMA_1_CDAR */ 0x00000208,
- /* DMA_1_SAR */ 0x00000210,
- /* DMA_1_DAR */ 0x00000218,
- /* DMA_1_BCR */ 0x00000220,
- /* DMA_1_NDAR */ 0x00000224,
- },
-};
-
-/* API functions */
-
-/* Initialize DMA unit with the following:
- * optional pointer to application layer print function
- *
- * These parameters may be added:
- * ???
- * Interrupt enables, modes, etc. are set for each transfer.
- *
- * This function must be called before DMA unit can be used.
- */
-extern
-DMA_Status DMA_Initialize( int (*p)(char *,...))
-{
- DMAStatus status;
- /* establish the pointer, if there is one, to the application's "printf" */
- app_print = p;
-
- /* If this is the first call, get the embedded utilities memory block
- * base address. I'm not sure what to do about error handling here:
- * if a non-zero value is returned, accept it.
- */
- if ( Global_eumbbar == 0)
- Global_eumbbar = get_eumbbar();
- if ( Global_eumbbar == 0)
- {
- PRINT( "DMA_Initialize: can't find EUMBBAR\n" );
- return DMA_ERROR;
- }
-
- return DMA_SUCCESS;
-}
-
-
-/* Perform the DMA transfer, only direct mode is currently implemented.
- * At this point, I think it would be better to define a different
- * function for chaining mode.
- * Also, I'm not sure if it is appropriate to have the "generic" API
- * accept snoop and int_steer parameters. The DINK user interface allows
- * them, so for now I'll leave them.
- *
- * int_steer controls DMA interrupt steering to PCI or local processor
- * type is the type of transfer: M2M, M2P, P2M, P2P
- * source is the source address of the data
- * dest is the destination address of the data
- * len is the length of data to transfer
- * channel is the DMA channel to use for the transfer
- * snoop is the snoop enable control
- */
-extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer,
- DMA_TRANSFER_TYPE type,
- unsigned int source,
- unsigned int dest,
- unsigned int len,
- DMA_CHANNEL channel,
- DMA_SNOOP_MODE snoop)
-{
- DMA_MR md;
- DMA_CDAR cdar;
- /* it's inappropriate for curr to be a struct, but I'll leave it */
- DMA_CURR curr;
-
- DMAStatus stat;
-
- /* The rest of this code was moved from device.c test_dma to here.
- * It needs to be cleaned up and validated, but at least it is removed
- * from the application and API. Most of the mode is left hard coded.
- * This should be changed after the final API is defined and the user
- * application has a way to control the transfer.
- *
- */
-
- if ( DMA_Get_Mode( LOCAL, Global_eumbbar, channel, &md ) != DMASUCCESS )
- {
- return DMA_ERROR;
- }
-
- md.irqs = int_steer;
- md.pde = 0;
- md.dahts = 3; /* 8 - byte */
- md.sahts = 3; /* 8 - byte */
- md.dahe = 0;
- md.sahe = 0;
- md.prc = 0;
- /* if steering interrupts to local processor, use polling mode */
- if ( int_steer == DMA_INT_STEER_PCI )
- {
- md.eie = 1;
- md.eotie = 1;
- } else {
- md.eie = 0;
- md.eotie = 0;
- }
- md.dl = 0;
- md.ctm = 1; /* direct mode */
- md.cc = 0;
-
- /* validate the length range */
- if (len > 0x3ffffff )
- {
- PRINT( "dev DMA: length of transfer too large: %d\n", len );
- return DMA_ERROR;
- }
-
- /* inappropriate to use a struct, but leave as is for now */
- curr.src_addr = source;
- curr.dest_addr = dest;
- curr.byte_cnt = len;
-
- (void)DMA_Poke_Desp( LOCAL, Global_eumbbar, channel, &cdar );
- cdar.snen = snoop;
- cdar.ctt = type;
-
- if ( ( stat = DMA_Bld_Desp( LOCAL, Global_eumbbar, channel, cdar ))
- != DMASUCCESS ||
- ( stat = DMA_Bld_Curr( LOCAL, Global_eumbbar, channel, curr ))
- != DMASUCCESS ||
- ( stat = DMA_Set_Mode( LOCAL, Global_eumbbar, channel, md ))
- != DMASUCCESS ||
- ( stat = DMA_Start( LOCAL, Global_eumbbar, channel ))
- != DMASUCCESS )
- {
- if ( stat == DMACHNBUSY )
- {
- PRINT( "dev DMA: channel %d busy.\n", channel );
- }
- else
- {
- PRINT( "dev DMA: invalid channel request.\n", channel );
- }
-
- return DMA_ERROR;
- }
-
-/* Since we are interested at the DMA performace right now,
- we are going to do as less as possible to burden the
- 603e core.
-
- if you have epic enabled or don't care the return from
- DMA operation, you can just return SUCCESS.
-
- if you don't have epic enabled and care the DMA result,
- you can use the polling method below.
-
- Note: I'll attempt to activate the code for handling polling.
- */
-
-#if 0
- /* if steering interrupt to local processor, let it handle results */
- if ( int_steer == DMA_INT_STEER_LOCAL )
- {
- return DMA_SUCCESS;
- }
-
- /* polling since interrupt goes to PCI */
- do
- {
- stat = DMA_ISR( Global_eumbbar, channel, dma_error_func,
- dma_error_func, dma_error_func, dma_error_func );
- }
- while ( stat == DMANOEVENT );
-#endif
-
- return DMA_SUCCESS;
-}
-
-/* DMA library internal functions */
-
-/**
- * Note:
- *
- * In all following functions, the host (KAHLUA) processor has a
- * choice of accessing on board local DMA (LOCAL),
- * or DMA on a distributed KAHLUA (REMOTE). In either case,
- * the caller shall pass the configured embedded utility memory
- * block base address relative to the DMA. If LOCAL DMA is used,
- * this parameter shall be EUMBBAR, if REMOTE is used, the
- * parameter shall be the corresponding PCSRBAR.
- **/
-
-/**************************************************************
- * function: DMA_Get_Stat
- *
- * description: return the content of status register of
- * the given DMA channel
- *
- * if error, reserved0 field all 1s.
- **************************************************************/
-static
-DMAStatus DMA_Get_Stat( LOCATION host, unsigned int eumbbar, unsigned int channel, DMA_SR *stat )
-{
- unsigned int tmp;
-
- if ( channel != 0 && channel != 1 || stat == 0 )
- {
- return DMAINVALID;
- }
-
- tmp = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SR_REG] );
-#ifdef DMADBG0
- PRINT( "%s(%d): %s DMA %d (0x%08x) stat = 0x%08x\n", __FILE__, __LINE__,
- ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SR_REG], tmp );
-#endif
-
- stat->reserved0 = ( tmp & 0xffffff00 ) >> 8;
- stat->lme = ( tmp & 0x00000080 ) >> 7;
- stat->reserved1 = ( tmp & 0x00000060 ) >> 5;
- stat->pe = ( tmp & 0x00000010 ) >> 4;
- stat->reserved2 = ( tmp & 0x00000008 ) >> 3;
- stat->cb = ( tmp & 0x00000004 ) >> 2;
- stat->eosi = ( tmp & 0x00000002 ) >> 1;
- stat->eocai = ( tmp & 0x00000001 );
-
- return DMASUCCESS;
-}
-
-/**************************************************************
- * function: DMA_Get_Mode
- *
- * description: return the content of mode register of the
- * given DMA channel
- *
- * if error, return DMAINVALID, otherwise return
- * DMASUCCESS
- **************************************************************/
-static
-DMAStatus DMA_Get_Mode( LOCATION host, unsigned eumbbar, unsigned int channel, DMA_MR *mode )
-{
- unsigned int tmp;
- if ( channel != 0 && channel != 1 || mode == 0 )
- {
- return DMAINVALID;
- }
-
- tmp = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_MR_REG] );
-
-#ifdef DMADBG0
- PRINT( "%s(%d): %s DMA %d (0x%08x) mode = 0x%08x\n", __FILE__, __LINE__,
- ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_MR_REG], tmp );
-#endif
-
- mode->reserved0 = (tmp & 0xfff00000) >> 20;
- mode->irqs = (tmp & 0x00080000) >> 19;
- mode->pde = (tmp & 0x00040000) >> 18;
- mode->dahts = (tmp & 0x00030000) >> 16;
- mode->sahts = (tmp & 0x0000c000) >> 14;
- mode->dahe = (tmp & 0x00002000) >> 13;
- mode->sahe = (tmp & 0x00001000) >> 12;
- mode->prc = (tmp & 0x00000c00) >> 10;
- mode->reserved1 = (tmp & 0x00000200) >> 9;
- mode->eie = (tmp & 0x00000100) >> 8;
- mode->eotie = (tmp & 0x00000080) >> 7;
- mode->reserved2 = (tmp & 0x00000070) >> 4;
- mode->dl = (tmp & 0x00000008) >> 3;
- mode->ctm = (tmp & 0x00000004) >> 2;
- mode->cc = (tmp & 0x00000002) >> 1;
- mode->cs = (tmp & 0x00000001);
-
- return DMASUCCESS;
-}
-
-/**************************************************************
- * function: DMA_Set_Mode
- *
- * description: Set a new mode to a given DMA channel
- *
- * note: It is not a good idea of changing the DMA mode during
- * the middle of a transaction.
- **************************************************************/
-static
-DMAStatus DMA_Set_Mode( LOCATION host, unsigned eumbbar, unsigned int channel, DMA_MR mode )
-{
- unsigned int tmp;
- if ( channel != 0 && channel != 1 )
- {
- return DMAINVALID;
- }
-
- tmp = ( mode.reserved0 & 0xfff ) << 20;
- tmp |= ( ( mode.irqs & 0x1 ) << 19);
- tmp |= ( ( mode.pde & 0x1 ) << 18 );
- tmp |= ( ( mode.dahts & 0x3 ) << 16 );
- tmp |= ( ( mode.sahts & 0x3 ) << 14 );
- tmp |= ( ( mode.dahe & 0x1 ) << 13 );
- tmp |= ( ( mode.sahe & 0x1 ) << 12 );
- tmp |= ( ( mode.prc & 0x3 ) << 10 );
- tmp |= ( ( mode.reserved1 & 0x1 ) << 9 );
- tmp |= ( ( mode.eie & 0x1 ) << 8 );
- tmp |= ( ( mode.eotie & 0x1 ) << 7 );
- tmp |= ( ( mode.reserved2 & 0x7 ) << 4 );
- tmp |= ( ( mode.dl & 0x1 ) << 3 );
- tmp |= ( ( mode.ctm & 0x1 ) << 2 );
- tmp |= ( ( mode.cc & 0x1 ) << 1 ) ;
- tmp |= ( mode.cs & 0x1 );
-
- store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], tmp );
- return DMASUCCESS;
-}
-
-/************************************************************
- * function: DMA_Start
- *
- * description: start a given DMA channel transaction
- * return DMASUCCESS if success otherwise return
- * DMAStatus value
- *
- * note: this function will clear DMA_MR(CC) first, then
- * set DMA_MR(CC).
- ***********************************************************/
-static
-DMAStatus DMA_Start( LOCATION host, unsigned int eumbbar, unsigned int channel )
-{
- DMA_SR stat;
- unsigned int mode;
-
- if ( channel != 0 && channel != 1 )
- {
- return DMAINVALID;
- }
-
- if ( DMA_Get_Stat( host, eumbbar, channel, &stat ) != DMASUCCESS )
- {
- return DMAINVALID;
- }
-
- if ( stat.cb == 1 )
- {
- /* DMA is not free */
- return DMACHNBUSY;
- }
-
- mode = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG] );
- /* clear DMA_MR(CS) */
- mode &= 0xfffffffe;
- store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode );
-
- /* set DMA_MR(CS) */
- mode |= CS;
- store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode );
- return DMASUCCESS;
-}
-
-/***********************************************************
- * function: DMA_Halt
- *
- * description: halt the current dma transaction on the specified
- * channel.
- * return DMASUCCESS if success otherwise return DMAINVALID
- *
- * note: if the specified DMA channel is idle, nothing happens
- *************************************************************/
-static
-DMAStatus DMA_Halt( LOCATION host, unsigned int eumbbar, unsigned int channel )
-{
- unsigned int mode;
- if ( channel != 0 && channel != 1 )
- {
- return DMAINVALID;
- }
-
- mode = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG]);
-
- /* clear DMA_MR(CS) */
- mode &= 0xfffffffe;
- store_runtime_reg(eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode );
- return DMASUCCESS;
-}
-
-/*************************************************************
- * function: DMA_Chn_Cnt
- *
- * description: set the DMA_MR(CC) bit for a given channel
- * that is in chaining mode.
- * return DMASUCCESS if successfule, otherwise return
- * DMAINVALID.
- *
- * note: if the given channel is not in chaining mode, nothing
- * happen.
- *
- *************************************************************/
-static
-DMAStatus DMA_Chn_Cnt( LOCATION host, unsigned int eumbbar, unsigned int channel )
-{
- DMA_MR mode;
- if ( channel != 0 && channel != 1 )
- {
- return DMAINVALID;
- }
-
- if ( DMA_Get_Mode( host, eumbbar, channel, &mode ) != DMASUCCESS )
- {
- return DMAINVALID;
- }
-
- if ( mode.ctm == 0 )
- {
- /* either illegal mode or not chaining mode */
- return DMAINVALID;
- }
-
- mode.cc = 1;
- return DMA_Set_Mode( host, eumbbar, channel, mode );
-}
-
-/**************************************************************
- * function: DMA_Bld_Desp
- *
- * description: set current descriptor address register
- * according to the desp for a given channel
- *
- * if the given channel is busy return DMACHNBUSY
- * and no change made, otherwise return DMASUCCESS.
- *
- * note:
- **************************************************************/
-static
-DMAStatus DMA_Bld_Desp( LOCATION host,
- unsigned int eumbbar,
- unsigned int channel,
- DMA_CDAR desp )
-{
- DMA_SR status;
- unsigned int temp;
-
- if ( channel != 0 && channel != 1 )
- {
- /* channel number out of range */
- return DMAINVALID;
- }
-
- if ( DMA_Get_Stat( host, eumbbar, channel, &status ) != DMASUCCESS )
- {
- return DMAINVALID;
- }
-
- if ( status.cb == 1 )
- {
- /* channel busy */
- return DMACHNBUSY;
- }
-
- temp = ( desp.cda & 0x7ffffff ) << 5;
- temp |= (( desp.snen & 0x1 ) << 4 );
- temp |= (( desp.eosie & 0x1 ) << 3 );
- temp |= (( desp.ctt & 0x3 ) << 1 );
- temp |= ( desp.eotd & 0x1 );
-
- store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], temp );
-
-#ifdef DMADBG0
- PRINT( "%s(%d): %s DMA %d (0x%08x) cdar := 0x%08x\n", __FILE__, __LINE__,
- ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], temp );
-#endif
-
- return DMASUCCESS;
-}
-
-/**************************************************************
- * function: DMA_Poke_Desp
- *
- * description: poke the current descriptor address register
- * for a given channel
- *
- * return DMASUCCESS if no error
- *
- * note: Due to the undeterministic parallellism of DMA operation,
- * the value returned by this function shall be taken as
- * the most recently used descriptor when the last time
- * DMA starts a chaining mode operation.
- **************************************************************/
-static
-DMAStatus DMA_Poke_Desp( LOCATION host,
- unsigned int eumbbar,
- unsigned int channel,
- DMA_CDAR *desp )
-{
- unsigned int cdar;
- if ( channel != 0 && channel != 1 || desp == 0 )
- {
- return DMAINVALID;
- }
-
- cdar = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG] );
-
-#ifdef DMADBG0
- PRINT( "%s(%d): %s DMA %d (0x%08x) cdar : 0x%08x\n", __FILE__, __LINE__,
- ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], cdar );
-#endif
-
-
- desp->cda = ( cdar & 0xffffffe0 ) >> 5;
- desp->snen = ( cdar & 0x00000010 ) >> 4;
- desp->eosie = ( cdar & 0x00000008 ) >> 3;
- desp->ctt = ( cdar & 0x00000006 ) >> 1;
- desp->eotd = ( cdar & 0x00000001 );
-
- return DMASUCCESS;
-}
-
-/**************************************************************
- * function: DMA_Bld_Curr
- *
- * description: set current src, dest, byte count registers
- * according to the desp for a given channel
- * return DMASUCCESS if no error.
- *
- * note:
- **************************************************************/
-static
-DMAStatus DMA_Bld_Curr( LOCATION host,
- unsigned int eumbbar,
- unsigned int channel,
- DMA_CURR desp )
-{
- DMA_SR status;
- if ( channel != 0 && channel != 1 )
- {
- /* channel number out of range */
- return DMAINVALID;
- }
-
- if ( DMA_Get_Stat( host, eumbbar, channel, &status ) != DMASUCCESS )
- {
- return DMAINVALID;
- }
-
- if ( status.cb == 1 )
- {
- /* channel busy */
- return DMACHNBUSY;
- }
-
- desp.byte_cnt &= 0x03ffffff; /* upper 6-bits are 0s */
-
- store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SAR_REG], desp.src_addr );
-#ifdef DMADBG0
- PRINT( "%s(%d): %s DMA %d (0x%08x) src := 0x%08x\n", __FILE__, __LINE__,
- ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.src_addr );
-#endif
-
- store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_DAR_REG], desp.dest_addr );
-#ifdef DMADBG0
- PRINT( "%s(%d): %s DMA %d (0x%08x) dest := 0x%08x\n", __FILE__, __LINE__,
- ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.dest_addr );
-#endif
-
- store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_BCR_REG], desp.byte_cnt );
-#ifdef DMADBG0
- PRINT( "%s(%d): %s DMA %d (0x%08x) count := 0x%08x\n", __FILE__, __LINE__,
- ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.byte_cnt );
-#endif
-
-
- return DMASUCCESS;
-
-}
-
-/**************************************************************
- * function: DMA_Poke_Curr
- *
- * description: poke the current src, dest, byte count registers
- * for a given channel.
- *
- * return DMASUCCESS if no error
- *
- * note: Due to the undeterministic parallelism, in chaining
- * mode, the value returned by this function shall
- * be taken as reference when the query is made rather
- * than the absolute snapshot when the value is returned.
- **************************************************************/
-static
-DMAStatus DMA_Poke_Curr( LOCATION host,
- unsigned int eumbbar,
- unsigned int channel,
- DMA_CURR* desp )
-{
- if ( channel != 0 && channel != 1 || desp == 0 )
- {
- return DMAINVALID;
- }
-
- desp->src_addr = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SAR_REG] );
-#ifdef DMADBG0
- PRINT( "%s(%d): %s DMA %d (0x%08x) src : 0x%08x\n", __FILE__, __LINE__,
- ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->src_addr );
-#endif
-
- desp->dest_addr = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_DAR_REG] );
-#ifdef DMADBG0
- PRINT( "%s(%d): %s DMA %d (0x%08x) dest : 0x%08x\n", __FILE__, __LINE__,
- ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->dest_addr );
-#endif
-
- desp->byte_cnt = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_BCR_REG] );
-#ifdef DMADBG0
- PRINT( "%s(%d): %s DMA %d (0x%08x) count : 0x%08x\n", __FILE__, __LINE__,
- ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->byte_cnt );
-#endif
-
-
- return DMASUCCESS;
-}
-
-/*****************************************************************
- * function: dma_error_func
- *
- * description: display the error information
- *
- * note: This seems like a highly convoluted way to handle messages,
- * but I'll leave it as it was in device.c when I moved it into the
- * DMA library source.
- ****************************************************************/
-static
-DMAStatus dma_error_func( unsigned int eumbbar, unsigned int chn, DMAStatus err)
-{
- unsigned char *msg[] =
- {
- "Local Memory Error",
- "PCI Error",
- "Channel Busy",
- "End-of-Segment Interrupt",
- "End-of-Chain/Direct Interrupt",
- };
-
- if ( err >= DMALMERROR && err <= DMAEOCAINT )
- {
- PRINT( "DMA Status: channel %d %s\n", chn, msg[err-DMASUCCESS-1] );
- }
-
- return err;
-
-}
-
-/*************************************************************
- * function: DMA_ISR
- *
- * description: DMA interrupt service routine
- * return DMAStatus value based on
- * the status
- *
- *************************************************************/
-static
-DMAStatus DMA_ISR( unsigned int eumbbar,
- unsigned int channel,
- DMAStatus (*lme_func)( unsigned int, unsigned int, DMAStatus ),
- DMAStatus (*pe_func) ( unsigned int, unsigned int, DMAStatus ),
- DMAStatus (*eosi_func)( unsigned int, unsigned int, DMAStatus ),
- DMAStatus (*eocai_func)(unsigned int, unsigned int, DMAStatus ))
-{
-
- DMA_SR stat;
- DMAStatus rval = DMANOEVENT;
- unsigned int temp;
-
- if ( channel != 0 && channel != 1 )
- {
- return DMAINVALID;
- }
-
- if ( DMA_Get_Stat( LOCAL, eumbbar, channel, &stat ) != DMASUCCESS )
- {
- return DMAINVALID;
- }
-
- if ( stat.lme == 1 )
- {
- /* local memory error */
- rval = DMALMERROR;
- if ( lme_func != 0 )
- {
- rval = (*lme_func)(eumbbar, channel, DMALMERROR );
- }
-
- }
- else if ( stat.pe == 1 )
- {
- /* PCI error */
- rval = DMAPERROR;
- if ( pe_func != 0 )
- {
- rval = (*pe_func)(eumbbar, channel, DMAPERROR );
- }
-
- }
- else if ( stat.eosi == 1 )
- {
- /* end-of-segment interrupt */
- rval = DMAEOSINT;
- if ( eosi_func != 0 )
- {
- rval = (*eosi_func)(eumbbar, channel, DMAEOSINT );
- }
- }
- else
- {
- /* End-of-chain/direct interrupt */
- rval = DMAEOCAINT;
- if ( eocai_func != 0 )
- {
- rval = (*eocai_func)(eumbbar, channel, DMAEOCAINT );
- }
- }
-
- temp = ( stat.reserved0 & 0xffffff ) << 8;
- temp |= ( ( stat.lme & 0x1 ) << 7 ); /* write one to clear */
- temp |= ( ( stat.reserved1 & 0x3 ) << 5 );
- temp |= ( ( stat.pe & 0x1 ) << 4 ); /* write one to clear */
- temp |= ( ( stat.reserved2 & 0x1 ) << 3 );
- temp |= ( ( stat.cb & 0x1 ) << 2 ); /* write one to clear */
- temp |= ( ( stat.eosi & 0x1 ) << 1 ); /* write one to clear */
- temp |= ( stat.eocai & 0x1 ); /* write one to clear */
-
- store_runtime_reg( eumbbar, dma_reg_tb[LOCAL][channel*NUM_DMA_REG + DMA_SR_REG], temp );
-
-#ifdef DMADBG0
- PRINT( "%s(%d): DMA channel %d SR := 0x%08x\n", __FILE__, __LINE__, channel, temp );
-#endif
-
- return rval;
-}
+++ /dev/null
-/**************************************
- *
- * copyright @ Motorola, 1999
- *
- **************************************/
-
-/**********************************************************
- * function: load_runtime_reg
- *
- * input: r3 - value of eumbbar
- * r4 - register offset in embedded utility space
- *
- * output: r3 - register content
- **********************************************************/
- .text
- .align 2
- .global load_runtime_reg
-
-load_runtime_reg:
-
- lwbrx r3,r4,r3
- sync
-
- bclr 20, 0
-
-/****************************************************************
- * function: store_runtime_reg
- *
- * input: r3 - value of eumbbar
- * r4 - register offset in embedded utility space
- * r5 - new value to be stored
- *
- ****************************************************************/
- .text
- .align 2
- .global store_runtime_reg
-store_runtime_reg:
-
- stwbrx r5, r4, r3
- sync
-
- bclr 20,0
+++ /dev/null
-#ifndef DMA_EXPORT_H
-#define DMA_EXPORT_H
-
-/****************************************************
- * $Id:
- *
- * Copyright Motorola 1999
- *
- * $Log:
- *
- ****************************************************/
-
-/* These are the defined return values for the DMA_* functions.
- * Any non-zero value indicates failure. Failure modes can be added for
- * more detailed error reporting.
- */
-typedef enum _dma_status
-{
- DMA_SUCCESS = 0,
- DMA_ERROR,
-} DMA_Status;
-
-/* These are the defined channel transfer types. */
-typedef enum _dma_transfer_types
-{
- DMA_M2M = 0, /* local memory to local memory */
- DMA_M2P = 1, /* local memory to PCI */
- DMA_P2M = 2, /* PCI to local memory */
- DMA_P2P = 3, /* PCI to PCI */
-} DMA_TRANSFER_TYPE;
-
-typedef enum _dma_interrupt_steer
-{
- DMA_INT_STEER_LOCAL = 0, /* steer DMA int to local processor */
- DMA_INT_STEER_PCI = 1, /* steer DMA int to PCI bus through INTA_ */
-} DMA_INTERRUPT_STEER;
-
-typedef enum _dma_channel
-{
- DMA_CHN_0 = 0, /* kahlua has two dma channels: 0 and 1 */
- DMA_CHN_1 = 1,
-} DMA_CHANNEL;
-
-typedef enum _dma_snoop_mode
-{
- DMA_SNOOP_DISABLE = 0,
- DMA_SNOOP_ENABLE = 1,
-} DMA_SNOOP_MODE;
-
-/******************** App. API ********************
- * The application API is for user level application
- * to use the functionality provided by DMA driver.
- * This is a "generic" DMA interface, it should contain
- * nothing specific to the Kahlua implementation.
- * Only the generic functions are exported by the library.
- *
- * Note: Its App.s responsibility to swap the data
- * byte. In our API, we currently transfer whatever
- * we are given - Big/Little Endian. This could
- * become part of the DMA config, though.
- **************************************************/
-
-
-/* Initialize DMA unit with the following:
- * optional pointer to application layer print function
- *
- * These parameters may be added:
- * ???
- * Interrupt enables, modes, etc. are set for each transfer.
- *
- * This function must be called before DMA unit can be used.
- */
-extern DMA_Status DMA_Initialize(
- int (*app_print_function)(char *,...)); /* pointer to optional "printf"
- * provided by application
- */
-
-/* Perform the DMA transfer, only direct mode is currently implemented.
- * At this point, I think it would be better to define a different
- * function for chaining mode.
- * Also, I'm not sure if it is appropriate to have the "generic" API
- * accept snoop and int_steer parameters. The DINK user interface allows
- * them, so for now I'll leave them.
- *
- * int_steer controls DMA interrupt steering to PCI or local processor
- * type is the type of transfer: M2M, M2P, P2M, P2P
- * source is the source address of the data
- * dest is the destination address of the data
- * len is the length of data to transfer
- * channel is the DMA channel to use for the transfer
- * snoop is the snoop enable control
- */
-extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer,
- DMA_TRANSFER_TYPE type,
- unsigned int source,
- unsigned int dest,
- unsigned int len,
- DMA_CHANNEL channel,
- DMA_SNOOP_MODE snoop);
-#endif
+++ /dev/null
-#ifndef DMA_EXPORT_H
-#define DMA_EXPORT_H
-
-/****************************************************
- * $Id:
- *
- * Copyright Motorola 1999
- *
- * $Log:
- *
- ****************************************************/
-
-/* These are the defined return values for the DMA_* functions.
- * Any non-zero value indicates failure. Failure modes can be added for
- * more detailed error reporting.
- */
-typedef enum _dma_status
-{
- DMA_SUCCESS = 0,
- DMA_ERROR,
-} DMA_Status;
-
-/* These are the defined channel transfer types. */
-typedef enum _dma_transfer_types
-{
- DMA_M2M = 0, /* local memory to local memory */
- DMA_M2P = 1, /* local memory to PCI */
- DMA_P2M = 2, /* PCI to local memory */
- DMA_P2P = 3, /* PCI to PCI */
-} DMA_TRANSFER_TYPE;
-
-typedef enum _dma_interrupt_steer
-{
- DMA_INT_STEER_LOCAL = 0, /* steer DMA int to local processor */
- DMA_INT_STEER_PCI = 1, /* steer DMA int to PCI bus through INTA_ */
-} DMA_INTERRUPT_STEER;
-
-typedef enum _dma_channel
-{
- DMA_CHN_0 = 0, /* kahlua has two dma channels: 0 and 1 */
- DMA_CHN_1 = 1,
-} DMA_CHANNEL;
-
-typedef enum _dma_snoop_mode
-{
- DMA_SNOOP_DISABLE = 0,
- DMA_SNOOP_ENABLE = 1,
-} DMA_SNOOP_MODE;
-
-/******************** App. API ********************
- * The application API is for user level application
- * to use the functionality provided by DMA driver.
- * This is a "generic" DMA interface, it should contain
- * nothing specific to the Kahlua implementation.
- * Only the generic functions are exported by the library.
- *
- * Note: Its App.s responsibility to swap the data
- * byte. In our API, we currently transfer whatever
- * we are given - Big/Little Endian. This could
- * become part of the DMA config, though.
- **************************************************/
-
-
-/* Initialize DMA unit with the following:
- * optional pointer to application layer print function
- *
- * These parameters may be added:
- * ???
- * Interrupt enables, modes, etc. are set for each transfer.
- *
- * This function must be called before DMA unit can be used.
- */
-extern DMA_Status DMA_Initialize(
- int (*app_print_function)(char *,...)); /* pointer to optional "printf"
- * provided by application
- */
-
-/* Perform the DMA transfer, only direct mode is currently implemented.
- * At this point, I think it would be better to define a different
- * function for chaining mode.
- * Also, I'm not sure if it is appropriate to have the "generic" API
- * accept snoop and int_steer parameters. The DINK user interface allows
- * them, so for now I'll leave them.
- *
- * int_steer controls DMA interrupt steering to PCI or local processor
- * type is the type of transfer: M2M, M2P, P2M, P2P
- * source is the source address of the data
- * dest is the destination address of the data
- * len is the length of data to transfer
- * channel is the DMA channel to use for the transfer
- * snoop is the snoop enable control
- */
-extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer,
- DMA_TRANSFER_TYPE type,
- unsigned int source,
- unsigned int dest,
- unsigned int len,
- DMA_CHANNEL channel,
- DMA_SNOOP_MODE snoop);
-#endif
+++ /dev/null
-#ifndef I2O_H
-#define I2O_H
-/*********************************************************
- *
- * copyright @ Motorola, 1999
- *********************************************************/
-
-#define I2O_REG_OFFSET 0x0004
-
-#define PCI_CFG_CLA 0x0B
-#define PCI_CFG_SCL 0x0A
-#define PCI_CFG_PIC 0x09
-
-#define I2O_IMR0 0x0050
-#define I2O_IMR1 0x0054
-#define I2O_OMR0 0x0058
-#define I2O_OMR1 0x005C
-
-#define I2O_ODBR 0x0060
-#define I2O_IDBR 0x0068
-
-#define I2O_OMISR 0x0030
-#define I2O_OMIMR 0x0034
-#define I2O_IMISR 0x0100
-#define I2O_IMIMR 0x0104
-
-/* accessable to PCI master but local processor */
-#define I2O_IFQPR 0x0040
-#define I2O_OFQPR 0x0044
-
-/* accessable to local processor */
-#define I2O_IFHPR 0x0120
-#define I2O_IFTPR 0x0128
-#define I2O_IPHPR 0x0130
-#define I2O_IPTPR 0x0138
-#define I2O_OFHPR 0x0140
-#define I2O_OFTPR 0x0148
-#define I2O_OPHPR 0x0150
-#define I2O_OPTPR 0x0158
-#define I2O_MUCR 0x0164
-#define I2O_QBAR 0x0170
-
-#define I2O_NUM_MSG 2
-
-typedef enum _i2o_status
-{
- I2OSUCCESS = 0,
- I2OINVALID,
- I2OMSGINVALID,
- I2ODBINVALID,
- I2OQUEINVALID,
- I2OQUEEMPTY,
- I2OQUEFULL,
- I2ONOEVENT,
-} I2OSTATUS;
-
-typedef enum _queue_size
-{
- QSIZE_4K = 0x02,
- QSIZE_8K = 0x04,
- QSIZE_16K = 0x08,
- QSIZE_32K = 0x10,
- QSIZe_64K = 0x20,
-} QUEUE_SIZE;
-
-typedef enum _location
-{
- LOCAL = 0, /* used by local processor to access its own on board device,
- local processor's eumbbar is required */
- REMOTE, /* used by PCI master to access the devices on its PCI device,
- device's pcsrbar is required */
-} LOCATION;
-
-/* door bell */
-typedef enum _i2o_in_db
-{
- IN_DB = 1,
- MC, /* machine check */
-} I2O_IN_DB;
-
-/* I2O PCI configuration identification */
-typedef struct _i2o_iop
-{
- unsigned int base_class : 8;
- unsigned int sub_class : 8;
- unsigned int prg_code : 8;
-} I2OIOP;
-
-/* I2O Outbound Message Interrupt Status Register */
-typedef struct _i2o_om_stat
-{
- unsigned int rsvd0 : 26;
- unsigned int opqi : 1;
- unsigned int rsvd1 : 1;
- unsigned int odi : 1;
- unsigned int rsvd2 : 1;
- unsigned int om1i : 1;
- unsigned int om0i : 1;
-} I2OOMSTAT;
-
-/* I2O inbound Message Interrupt Status Register */
-typedef struct _i2o_im_stat
-{
- unsigned int rsvd0 : 23;
- unsigned int ofoi : 1;
- unsigned int ipoi : 1;
- unsigned int rsvd1 : 1;
- unsigned int ipqi : 1;
- unsigned int mci : 1;
- unsigned int idi : 1;
- unsigned int rsvd2 : 1;
- unsigned int im1i : 1;
- unsigned int im0i : 1;
-} I2OIMSTAT;
-
-/**
- Enable the interrupt associated with in/out bound msg
-
- Inbound message interrupt generated by PCI master and serviced by local processor
- local processor needs to enable its inbound interrupts it wants to handle (LOCAL)
-
- Outbound message interrupt generated by local processor and serviced by PCI master
- PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE)
- **/
-extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ); /* b'1' - msg 0
- * b'10'- msg 1
- * b'11'- both
- */
-
-/**
- Disable the interrupt associated with in/out bound msg
-
- local processor needs to disable its inbound interrupts it is not interested (LOCAL)
-
- PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE)
- **/
-extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ); /* b'1' - msg 0
- * b'10'- msg 1
- * b'11'- both
- */
-
-/**
- Read the msg register either from local inbound msg 0/1,
- or an outbound msg 0/1 of devices.
-
- If it is not local, pcsrbar must be passed to the function.
- Otherwise eumbbar is passed.
-
- If it is remote, outbound msg of the device is read.
- Otherwise local inbound msg is read.
- **/
-extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int *msg );
-
-/**
- Write to nth Msg register either on local outbound msg 0/1,
- or aninbound msg 0/1 of devices
-
- If it is not local, pcsrbar must be passed to the function.
- Otherwise eumbbar is passed.
-
- If it is remote, inbound msg on the device is written.
- Otherwise local outbound msg is written.
- **/
-extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int msg );
-
-/**
- Enable the In/Out DoorBell Interrupt
-
- InDoorBell interrupt is generated by PCI master and serviced by local processor
- local processor needs to enable its inbound doorbell interrupts it wants to handle
-
- OutDoorbell interrupt is generated by local processor and serviced by PCI master
- PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle
- **/
-extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
-
-/**
- Disable the In/Out DoorBell Interrupt
-
- local processor needs to disable its inbound doorbell interrupts it is not interested
-
- PCI master needs to disable outbound doorbell interrupts of devices it is not interested
-
- **/
-extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
-
-/**
- Read a local indoorbell register, or an outdoorbell of devices.
- Reading a doorbell register, the register will be cleared.
-
- If it is not local, pcsrbar must be passed to the function.
- Otherwise eumbbar is passed.
-
- If it is remote, outdoorbell register on the device is read.
- Otherwise local in doorbell is read
- **/
-extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */
- unsigned int base); /* pcsrbar/eumbbar */
-
-/**
- Write to a local outdoorbell register, or an indoorbell register of devices.
-
- If it is not local, pcsrbar must be passed to the function.
- Otherwise eumbbar is passed.
-
- If it is remote, in doorbell register on the device is written.
- Otherwise local out doorbell is written
- **/
-extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int msg ); /* in / out */
-
-/**
- Read the outbound msg unit interrupt status of devices. Reading an interrupt status register,
- the register will be cleared.
-
- The outbound interrupt status is AND with the outbound
- interrupt mask. The result is returned.
-
- PCI master must pass the pcsrbar to the function.
- **/
-extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * );
-
-/**
- Read the inbound msg unit interrupt status. Reading an interrupt status register,
- the register will be cleared.
-
- The inbound interrupt status is AND with the inbound
- interrupt mask. The result is returned.
-
- Local process must pass its eumbbar to the function.
-**/
-extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * );
-
-/**
- Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR,
- MUCR.
- **/
-extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
- QUEUE_SIZE,
- unsigned int qba);/* queue base address that must be aligned at 1M */
-/**
- Enable the circular queue
- **/
-extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar );
-
-/**
- Disable the circular queue
- **/
-extern void I2OFIFODisable( unsigned int eumbbar );
-
-/**
- Enable the circular queue interrupt
- PCI master enables outbound FIFO interrupt of device
- Device enables its inbound FIFO interrupt
- **/
-extern void I2OFIFOIntEnable( LOCATION, unsigned int base );
-
-/**
- Disable the circular queue interrupt
- PCI master disables outbound FIFO interrupt of device
- Device disables its inbound FIFO interrupt
- **/
-extern void I2OFIFOIntDisable( LOCATION, unsigned int base );
-
-/**
- Enable the circular queue overflow interrupt
- **/
-extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar );
-
-/**
- Disable the circular queue overflow interrupt
- **/
-extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar );
-
-/**
- Allocate a free msg frame from free FIFO.
-
- PCI Master allocates a free msg frame through inbound queue port of device(IFQPR)
- while local processor allocates a free msg frame from outbound free queue(OFTPR)
-
- Unless both free queues are initialized, allocating a free MF will return 0xffffffff
- **/
-extern I2OSTATUS I2OFIFOAlloc( LOCATION,
- unsigned int base,
- void **pMsg);
-/**
- Free a used msg frame back to free queue
- PCI Master frees a MFA through outbound queue port of device(OFQPR)
- while local processor frees a MFA into its inbound free queue(IFHPR)
-
- Used msg frame does not need to be recycled in the order they
- read
-
- This function has to be called by PCI master to initialize Inbound free queue
- and by device to initialize Outbound free queue before I2OFIFOAlloc can be used.
- **/
-extern I2OSTATUS I2OFIFOFree( LOCATION,
- unsigned int base,
- void *pMsg );
-
-/**
- Post a msg into FIFO
- PCI Master posts a msg through inbound queue port of device(IFQPR)
- while local processor post a msg into its outbound post queue(OPHPR)
-
- The total number of msg must be less than the max size of the queue
- Otherwise queue overflow interrupt will assert.
- **/
-extern I2OSTATUS I2OFIFOPost( LOCATION,
- unsigned int base,
- void *pMsg );
-
-/**
- Read a msg from FIFO
- PCI Master reads a msg through outbound queue port of device(OFQPR)
- while local processor reads a msg from its inbound post queue(IPTPR)
- **/
-extern I2OSTATUS I2OFIFOGet( LOCATION,
- unsigned int base,
- void **pMsg );
-
-/**
- Get the I2O PCI configuration identification register
- **/
-extern I2OSTATUS I2OPCIConfigGet( LOCATION,
- unsigned int base,
- I2OIOP *);
-
-#endif
+++ /dev/null
-##########################################################################
-#
-# Copyright Motorola, Inc. 1997
-# ALL RIGHTS RESERVED
-#
-# You are hereby granted a copyright license to use, modify, and
-# distribute the SOFTWARE so long as this entire notice is retained
-# without alteration in any modified and/or redistributed versions,
-# and that such modified versions are clearly identified as such.
-# No licenses are granted by implication, estoppel or otherwise under
-# any patents or trademarks of Motorola, Inc.
-#
-# The SOFTWARE is provided on an "AS IS" basis and without warranty.
-# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS
-# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED
-# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
-# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
-# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS
-# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS.
-#
-# To the maximum extent permitted by applicable law, IN NO EVENT SHALL
-# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
-# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
-# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR
-# INABILITY TO USE THE SOFTWARE.
-#
-############################################################################
-TARGET = libi2o.a
-
-#DEBUG = -g
-DEBUG =
-LST = -Hanno -S
-OPTIM =
-CC = /risc/tools/pkgs/metaware/bin/hcppc
-CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc
-CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM)
-PREP = $(CC) $(CFLAGS) -P
-
-# Assembler used to build the .s files (for the board version)
-
-ASOPT = -big_si -c
-ASDEBUG = -l -fm
-AS = /risc/tools/pkgs/metaware/bin/asppc
-
-# Linker to bring .o files together into an executable.
-
-LKOPT = -Bbase=0 -Qn -q -r
-LKCMD =
-LINK = /risc/tools/pkgs/metaware/bin/ldppc $(LKCMD) $(LKOPT)
-
-# DOS Utilities
-
-DEL = rm
-COPY = cp
-LIST = ls
-
-OBJECTS = i2o1.o i2o2.o
-
-all: $(TARGET)
-
-$(TARGET): $(OBJECTS)
- $(LINK) $(OBJECTS) -o $@
-
-objects: i2o1.o
-
-clean:
- $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS)
-
-.s.o:
- $(DEL) -f $*.i
- $(PREP) -Hasmcpp $<
- $(AS) $(ASOPT) $*.i
-# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst
-
-.c.o:
- $(CCobj) $<
-
-.c.s:
- $(CCobj) $(LST) $<
-
-i2o1.o: i2o.h i2o1.c
-
-i2o2.o: i2o.h i2o2.s
+++ /dev/null
-##########################################################################
-#
-# makefile_pc for use with PC mksnt tools dink32/drivers/i2o
-#
-# Copyright Motorola, Inc. 1997
-# ALL RIGHTS RESERVED
-#
-# You are hereby granted a copyright license to use, modify, and
-# distribute the SOFTWARE so long as this entire notice is retained
-# without alteration in any modified and/or redistributed versions,
-# and that such modified versions are clearly identified as such.
-# No licenses are granted by implication, estoppel or otherwise under
-# any patents or trademarks of Motorola, Inc.
-#
-# The SOFTWARE is provided on an "AS IS" basis and without warranty.
-# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS
-# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED
-# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
-# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
-# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS
-# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS.
-#
-# To the maximum extent permitted by applicable law, IN NO EVENT SHALL
-# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
-# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
-# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR
-# INABILITY TO USE THE SOFTWARE.
-#
-############################################################################
-TARGET = libi2o.a
-
-#DEBUG = -g
-DEBUG =
-LST = -Hanno -S
-OPTIM =
-CC = m:/old_tools/tools/hcppc/bin/hcppc
-CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc
-CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM)
-PREP = $(CC) $(CFLAGS) -P
-
-# Assembler used to build the .s files (for the board version)
-
-ASOPT = -big_si -c
-ASDEBUG = -l -fm
-AS = m:/old_tools/tools/hcppc/bin/asppc
-
-# Linker to bring .o files together into an executable.
-
-LKOPT = -Bbase=0 -Qn -q -r
-LKCMD =
-LINK = m:/old_tools/tools/hcppc/bin/ldppc $(LKCMD) $(LKOPT)
-
-# DOS Utilities
-
-DEL = rm
-COPY = cp
-LIST = ls
-
-OBJECTS = i2o1.o i2o2.o
-
-all: $(TARGET)
-
-$(TARGET): $(OBJECTS)
- $(LINK) $(OBJECTS) -o $@
-
-objects: i2o1.o
-
-clean:
- $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS)
-
-.s.o:
- $(DEL) -f $*.i
- $(PREP) -Hasmcpp $<
- $(AS) $(ASOPT) $*.i
-# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst
-
-.c.o:
- $(CCobj) $<
-
-.c.s:
- $(CCobj) $(LST) $<
-
-i2o1.o: i2o.h i2o1.c
- $(CCobj) $<
-
-i2o2.o: i2o.h i2o2.s
- $(DEL) -f $*.i
- $(PREP) -Hasmcpp $<
- $(AS) $(ASOPT) $*.i
+++ /dev/null
-#ifndef I2O_H
-#define I2O_H
-/*********************************************************
- *
- * copyright @ Motorola, 1999
- *
- *********************************************************/
-
-#define I2O_REG_OFFSET 0x0004
-
-#define PCI_CFG_CLA 0x0B
-#define PCI_CFG_SCL 0x0A
-#define PCI_CFG_PIC 0x09
-
-#define I2O_IMR0 0x0050
-#define I2O_IMR1 0x0054
-#define I2O_OMR0 0x0058
-#define I2O_OMR1 0x005C
-
-#define I2O_ODBR 0x0060
-#define I2O_IDBR 0x0068
-
-#define I2O_OMISR 0x0030
-#define I2O_OMIMR 0x0034
-#define I2O_IMISR 0x0100
-#define I2O_IMIMR 0x0104
-
-/* accessable to PCI master but local processor */
-#define I2O_IFQPR 0x0040
-#define I2O_OFQPR 0x0044
-
-/* accessable to local processor */
-#define I2O_IFHPR 0x0120
-#define I2O_IFTPR 0x0128
-#define I2O_IPHPR 0x0130
-#define I2O_IPTPR 0x0138
-#define I2O_OFHPR 0x0140
-#define I2O_OFTPR 0x0148
-#define I2O_OPHPR 0x0150
-#define I2O_OPTPR 0x0158
-#define I2O_MUCR 0x0164
-#define I2O_QBAR 0x0170
-
-#define I2O_NUM_MSG 2
-
-typedef enum _i2o_status
-{
- I2OSUCCESS = 0,
- I2OINVALID,
- I2OMSGINVALID,
- I2ODBINVALID,
- I2OQUEINVALID,
- I2OQUEEMPTY,
- I2OQUEFULL,
- I2ONOEVENT,
-} I2OSTATUS;
-
-typedef enum _queue_size
-{
- QSIZE_4K = 0x02,
- QSIZE_8K = 0x04,
- QSIZE_16K = 0x08,
- QSIZE_32K = 0x10,
- QSIZe_64K = 0x20,
-} QUEUE_SIZE;
-
-typedef enum _location
-{
- LOCAL = 0, /* used by local processor to access its own on board device,
- local processor's eumbbar is required */
- REMOTE, /* used by PCI master to access the devices on its PCI device,
- device's pcsrbar is required */
-} LOCATION;
-
-/* door bell */
-typedef enum _i2o_in_db
-{
- IN_DB = 1,
- MC, /* machine check */
-} I2O_IN_DB;
-
-/* I2O PCI configuration identification */
-typedef struct _i2o_iop
-{
- unsigned int base_class : 8;
- unsigned int sub_class : 8;
- unsigned int prg_code : 8;
-} I2OIOP;
-
-/* I2O Outbound Message Interrupt Status Register */
-typedef struct _i2o_om_stat
-{
- unsigned int rsvd0 : 26;
- unsigned int opqi : 1;
- unsigned int rsvd1 : 1;
- unsigned int odi : 1;
- unsigned int rsvd2 : 1;
- unsigned int om1i : 1;
- unsigned int om0i : 1;
-} I2OOMSTAT;
-
-/* I2O inbound Message Interrupt Status Register */
-typedef struct _i2o_im_stat
-{
- unsigned int rsvd0 : 23;
- unsigned int ofoi : 1;
- unsigned int ipoi : 1;
- unsigned int rsvd1 : 1;
- unsigned int ipqi : 1;
- unsigned int mci : 1;
- unsigned int idi : 1;
- unsigned int rsvd2 : 1;
- unsigned int im1i : 1;
- unsigned int im0i : 1;
-} I2OIMSTAT;
-
-/**
- Enable the interrupt associated with in/out bound msg
-
- Inbound message interrupt generated by PCI master and serviced by local processor
- local processor needs to enable its inbound interrupts it wants to handle (LOCAL)
-
- Outbound message interrupt generated by local processor and serviced by PCI master
- PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE)
- **/
-extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ); /* b'1' - msg 0
- * b'10'- msg 1
- * b'11'- both
- */
-
-/**
- Disable the interrupt associated with in/out bound msg
-
- local processor needs to disable its inbound interrupts it is not interested (LOCAL)
-
- PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE)
- **/
-extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ); /* b'1' - msg 0
- * b'10'- msg 1
- * b'11'- both
- */
-
-/**
- Read the msg register either from local inbound msg 0/1,
- or an outbound msg 0/1 of devices.
-
- If it is not local, pcsrbar must be passed to the function.
- Otherwise eumbbar is passed.
-
- If it is remote, outbound msg of the device is read.
- Otherwise local inbound msg is read.
- **/
-extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int *msg );
-
-/**
- Write to nth Msg register either on local outbound msg 0/1,
- or aninbound msg 0/1 of devices
-
- If it is not local, pcsrbar must be passed to the function.
- Otherwise eumbbar is passed.
-
- If it is remote, inbound msg on the device is written.
- Otherwise local outbound msg is written.
- **/
-extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int msg );
-
-/**
- Enable the In/Out DoorBell Interrupt
-
- InDoorBell interrupt is generated by PCI master and serviced by local processor
- local processor needs to enable its inbound doorbell interrupts it wants to handle
-
- OutDoorbell interrupt is generated by local processor and serviced by PCI master
- PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle
- **/
-extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
-
-/**
- Disable the In/Out DoorBell Interrupt
-
- local processor needs to disable its inbound doorbell interrupts it is not interested
-
- PCI master needs to disable outbound doorbell interrupts of devices it is not interested
-
- **/
-extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
-
-/**
- Read a local indoorbell register, or an outdoorbell of devices.
- Reading a doorbell register, the register will be cleared.
-
- If it is not local, pcsrbar must be passed to the function.
- Otherwise eumbbar is passed.
-
- If it is remote, outdoorbell register on the device is read.
- Otherwise local in doorbell is read
- **/
-extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */
- unsigned int base); /* pcsrbar/eumbbar */
-
-/**
- Write to a local outdoorbell register, or an indoorbell register of devices.
-
- If it is not local, pcsrbar must be passed to the function.
- Otherwise eumbbar is passed.
-
- If it is remote, in doorbell register on the device is written.
- Otherwise local out doorbell is written
- **/
-extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int msg ); /* in / out */
-
-/**
- Read the outbound msg unit interrupt status of devices. Reading an interrupt status register,
- the register will be cleared.
-
- The outbound interrupt status is AND with the outbound
- interrupt mask. The result is returned.
-
- PCI master must pass the pcsrbar to the function.
- **/
-extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * );
-
-/**
- Read the inbound msg unit interrupt status. Reading an interrupt status register,
- the register will be cleared.
-
- The inbound interrupt status is AND with the inbound
- interrupt mask. The result is returned.
-
- Local process must pass its eumbbar to the function.
-**/
-extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * );
-
-/**
- Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR,
- MUCR.
- **/
-extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
- QUEUE_SIZE,
- unsigned int qba);/* queue base address that must be aligned at 1M */
-/**
- Enable the circular queue
- **/
-extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar );
-
-/**
- Disable the circular queue
- **/
-extern void I2OFIFODisable( unsigned int eumbbar );
-
-/**
- Enable the circular queue interrupt
- PCI master enables outbound FIFO interrupt of device
- Device enables its inbound FIFO interrupt
- **/
-extern void I2OFIFOIntEnable( LOCATION, unsigned int base );
-
-/**
- Disable the circular queue interrupt
- PCI master disables outbound FIFO interrupt of device
- Device disables its inbound FIFO interrupt
- **/
-extern void I2OFIFOIntDisable( LOCATION, unsigned int base );
-
-/**
- Enable the circular queue overflow interrupt
- **/
-extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar );
-
-/**
- Disable the circular queue overflow interrupt
- **/
-extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar );
-
-/**
- Allocate a free msg frame from free FIFO.
-
- PCI Master allocates a free msg frame through inbound queue port of device(IFQPR)
- while local processor allocates a free msg frame from outbound free queue(OFTPR)
-
- Unless both free queues are initialized, allocating a free MF will return 0xffffffff
- **/
-extern I2OSTATUS I2OFIFOAlloc( LOCATION,
- unsigned int base,
- void **pMsg);
-/**
- Free a used msg frame back to free queue
- PCI Master frees a MFA through outbound queue port of device(OFQPR)
- while local processor frees a MFA into its inbound free queue(IFHPR)
-
- Used msg frame does not need to be recycled in the order they
- read
-
- This function has to be called by PCI master to initialize Inbound free queue
- and by device to initialize Outbound free queue before I2OFIFOAlloc can be used.
- **/
-extern I2OSTATUS I2OFIFOFree( LOCATION,
- unsigned int base,
- void *pMsg );
-
-/**
- Post a msg into FIFO
- PCI Master posts a msg through inbound queue port of device(IFQPR)
- while local processor post a msg into its outbound post queue(OPHPR)
-
- The total number of msg must be less than the max size of the queue
- Otherwise queue overflow interrupt will assert.
- **/
-extern I2OSTATUS I2OFIFOPost( LOCATION,
- unsigned int base,
- void *pMsg );
-
-/**
- Read a msg from FIFO
- PCI Master reads a msg through outbound queue port of device(OFQPR)
- while local processor reads a msg from its inbound post queue(IPTPR)
- **/
-extern I2OSTATUS I2OFIFOGet( LOCATION,
- unsigned int base,
- void **pMsg );
-
-/**
- Get the I2O PCI configuration identification register
- **/
-extern I2OSTATUS I2OPCIConfigGet( LOCATION,
- unsigned int base,
- I2OIOP *);
-
-#endif
+++ /dev/null
-/*********************************************************
- * $Id
- *
- * copyright @ Motorola, 1999
- *********************************************************/
-#include "i2o.h"
-
-extern unsigned int load_runtime_reg( unsigned int eumbbar, unsigned int reg );
-#pragma Alias( load_runtime_reg, "load_runtime_reg" );
-
-extern void store_runtime_reg( unsigned int eumbbar, unsigned int reg, unsigned int val );
-#pragma Alias( store_runtime_reg, "store_runtime_reg" );
-
-typedef struct _fifo_stat
-{
- QUEUE_SIZE qsz;
- unsigned int qba;
-} FIFOSTAT;
-
-FIFOSTAT fifo_stat = { QSIZE_4K, 0xffffffff };
-
-/**********************************************************************************
- * function: I2OMsgEnable
- *
- * description: Enable the interrupt associated with in/out bound msg
- * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID.
- *
- * All previously enabled interrupts are preserved.
- * note:
- * Inbound message interrupt generated by PCI master and serviced by local processor
- * Outbound message interrupt generated by local processor and serviced by PCI master
- *
- * local processor needs to enable its inbound interrupts it wants to handle(LOCAL)
- * PCI master needs to enable the outbound interrupts of devices it wants to handle(REMOTE)
- ************************************************************************************/
-I2OSTATUS I2OMsgEnable ( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ) /* b'1' - msg 0
- * b'10'- msg 1
- * b'11'- both
- */
-{
- unsigned int reg, val;
- if ( ( n & 0x3 ) == 0 )
- {
- /* neither msg 0, nor msg 1 */
- return I2OMSGINVALID;
- }
-
- n = (~n) & 0x3;
- /* LOCATION - REMOTE : enable outbound message of device, pcsrbar as base
- * LOCAL : enable local inbound message, eumbbar as base
- */
- reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR );
- val = load_runtime_reg( base, reg );
-
- val &= 0xfffffffc; /* masked out the msg interrupt bits */
- val |= n; /* LSB are the one we want */
- store_runtime_reg( base, reg, val );
-
- return I2OSUCCESS;
-}
-
-/*********************************************************************************
- * function: I2OMsgDisable
- *
- * description: Disable the interrupt associated with in/out bound msg
- * Other previously enabled interrupts are preserved.
- * return I2OSUCCESS if no error otherwise return I2OMSGINVALID
- *
- * note:
- * local processor needs to disable its inbound interrupts it is not interested(LOCAL)
- * PCI master needs to disable outbound interrupts of devices it is not interested(REMOTE)
- *********************************************************************************/
-I2OSTATUS I2OMsgDisable( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ) /* b'1' - msg 0
- * b'10'- msg 1
- * b'11'- both
- */
-{
- unsigned int reg, val;
-
- if ( ( n & 0x3 ) == 0 )
- {
- /* neither msg 0, nor msg 1 */
- return I2OMSGINVALID;
- }
-
- /* LOCATION - REMOTE : disable outbound message interrupt of device, pcsrbar as base
- * LOCAL : disable local inbound message interrupt, eumbbar as base
- */
- reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR );
- val = load_runtime_reg( base, reg );
-
- val &= 0xfffffffc; /* masked out the msg interrupt bits */
- val |= ( n & 0x3 );
- store_runtime_reg( base, reg, val );
-
- return I2OSUCCESS;
-
-}
-
-/**************************************************************************
- * function: I2OMsgGet
- *
- * description: Local processor reads the nth Msg register from its inbound msg,
- * or a PCI Master reads nth outbound msg from device
- *
- * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID.
- *
- * note:
- * If it is not local, pcsrbar must be passed to the function. Otherwise eumbbar is passed.
- * If it is remote, outbound msg on the device is read; otherwise local inbound msg is read
- *************************************************************************/
-I2OSTATUS I2OMsgGet ( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int *msg )
-{
- if ( n >= I2O_NUM_MSG || msg == 0 )
- {
- return I2OMSGINVALID;
- }
-
- if ( loc == REMOTE )
- {
- /* read the outbound msg of the device, pcsrbar as base */
- *msg = load_runtime_reg( base, I2O_OMR0+n*I2O_REG_OFFSET );
- }
- else
- {
- /* read the inbound msg sent by PCI master, eumbbar as base */
- *msg = load_runtime_reg( base, I2O_IMR0+n*I2O_REG_OFFSET );
- }
-
- return I2OSUCCESS;
-}
-
-/***************************************************************
- * function: I2OMsgPost
- *
- * description: Kahlua writes to its nth outbound msg register
- * PCI master writes to nth inbound msg register of device
- *
- * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID.
- *
- * note:
- * If it is not local, pcsrbar must be passed to the function. Otherwise eumbbar is passed.
- *
- * If it is remote, inbound msg on the device is written; otherwise local outbound msg is written
- ***************************************************************/
-I2OSTATUS I2OMsgPost( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int msg )
-{
- if ( n >= I2O_NUM_MSG )
- {
- return I2OMSGINVALID;
- }
-
- if ( loc == REMOTE )
- {
- /* write to the inbound msg register of the device, pcsrbar as base */
- store_runtime_reg( base, I2O_IMR0+n*I2O_REG_OFFSET, msg );
- }
- else
- {
- /* write to the outbound msg register for PCI master to read, eumbbar as base */
- store_runtime_reg( base, I2O_OMR0+n*I2O_REG_OFFSET, msg );
- }
-
- return I2OSUCCESS;
-}
-
-/***********************************************************************
- * function: I2ODBEnable
- *
- * description: Local processor enables it's inbound doorbell interrupt
- * PCI master enables outbound doorbell interrupt of devices
- * Other previously enabled interrupts are preserved.
- * Return I2OSUCCESS if no error otherwise return I2ODBINVALID
- *
- * note:
- * In DoorBell interrupt is generated by PCI master and serviced by local processor
- * Out Doorbell interrupt is generated by local processor and serviced by PCI master
- *
- * Out Doorbell interrupt is generated by local processor and serviced by PCI master
- * PCI master needs to enable the outbound doorbell interrupts of device it wants to handle
- **********************************************************************/
-I2OSTATUS I2ODBEnable( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
-{
-
- /* LOCATION - REMOTE : PCI master initializes outbound doorbell message of device
- * LOCAL : Kahlua initializes its inbound doorbell message
- */
- unsigned int val;
-
- if ( loc == LOCAL && ( in_db & 0x3 ) == 0 )
- {
- return I2ODBINVALID;
- }
-
- if ( loc == REMOTE )
- {
- /* pcsrbar is base */
- val = load_runtime_reg( base, I2O_OMIMR );
- val &= 0xfffffff7;
- store_runtime_reg( base, I2O_OMIMR , val );
- }
- else
- {
- /* eumbbar is base */
- val = load_runtime_reg( base, I2O_IMIMR);
- in_db = ( (~in_db) & 0x3 ) << 3;
- val = ( val & 0xffffffe7) | in_db;
- store_runtime_reg( base, I2O_IMIMR, val );
- }
-
- return I2OSUCCESS;
-}
-
-/**********************************************************************************
- * function: I2ODBDisable
- *
- * description: local processor disables its inbound DoorBell Interrupt
- * PCI master disables outbound DoorBell interrupt of device
- * Other previously enabled interrupts are preserved.
- * return I2OSUCCESS if no error.Otherwise return I2ODBINVALID
- *
- * note:
- * local processor needs to disable its inbound doorbell interrupts it is not interested
- *
- * PCI master needs to disable outbound doorbell interrupts of device it is not interested
- ************************************************************************************/
-I2OSTATUS I2ODBDisable( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
-{
- /* LOCATION - REMOTE : handle device's out bound message initialization
- * LOCAL : handle local in bound message initialization
- */
- unsigned int val;
-
- if ( loc == LOCAL && ( in_db & 0x3 ) == 0 )
- {
- return I2ODBINVALID;
- }
-
- if ( loc == REMOTE )
- {
- /* pcsrbar is the base */
- val = load_runtime_reg( base, I2O_OMIMR );
- val |= 0x8;
- store_runtime_reg( base, I2O_OMIMR, val );
- }
- else
- {
- val = load_runtime_reg( base, I2O_IMIMR);
- in_db = ( in_db & 0x3 ) << 3;
- val |= in_db;
- store_runtime_reg( base, I2O_IMIMR, val );
- }
-
- return I2OSUCCESS;
-}
-
-/**********************************************************************************
- * function: I2ODBGet
- *
- * description: Local processor reads its in doorbell register,
- * PCI master reads the outdoorbell register of device.
- * After a doorbell register is read, the whole register will be cleared.
- * Otherwise, HW keeps generating interrupt.
- *
- * note:
- * If it is not local, pcsrbar must be passed to the function.
- * Otherwise eumbbar is passed.
- *
- * If it is remote, out doorbell register on the device is read.
- * Otherwise local in doorbell is read
- *
- * If the register is not cleared by write to it, any remaining bit of b'1's
- * will cause interrupt pending.
- *********************************************************************************/
-unsigned int I2ODBGet( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base) /* pcsrbar/eumbbar */
-{
- unsigned int msg, val;
-
- if ( loc == REMOTE )
- {
- /* read outbound doorbell register of device, pcsrbar is the base */
- val = load_runtime_reg( base, I2O_ODBR );
- msg = val & 0xe0000000;
- store_runtime_reg( base, I2O_ODBR, val ); /* clear the register */
- }
- else
- {
- /* read the inbound doorbell register, eumbbar is the base */
- val = load_runtime_reg( base, I2O_IDBR );
- store_runtime_reg( base, I2O_IDBR, val ); /* clear the register */
- msg = val;
- }
-
- return msg;
-}
-
-/**********************************************************************
- * function: I2ODBPost
- *
- * description: local processor writes to a outbound doorbell register,
- * PCI master writes to the inbound doorbell register of device
- *
- * note:
- * If it is not local, pcsrbar must be passed to the function.
- * Otherwise eumbbar is passed.
- *
- * If it is remote, in doorbell register on the device is written.
- * Otherwise local out doorbell is written
- *********************************************************************/
-void I2ODBPost( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int msg ) /* in / out */
-{
- if ( loc == REMOTE )
- {
- /* write to inbound doorbell register of device, pcsrbar is the base */
- store_runtime_reg( base, I2O_IDBR, msg );
- }
- else
- {
- /* write to local outbound doorbell register, eumbbar is the base */
- store_runtime_reg( base, I2O_ODBR, msg & 0x1fffffff );
- }
-
-}
-
-/********************************************************************
- * function: I2OOutMsgStatGet
- *
- * description: PCI master reads device's outbound msg unit interrupt status.
- * Reading an interrupt status register,
- * the register will be cleared.
- *
- * The value of the status register is AND with the outbound
- * interrupt mask and result is returned.
- *
- * note:
- * pcsrbar must be passed to the function.
- ********************************************************************/
-I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT *val )
-{
- unsigned int stat;
- unsigned int mask;
-
- if ( val == 0 )
- {
- return I2OINVALID;
- }
-
- /* read device's outbound status */
- stat = load_runtime_reg( pcsrbar, I2O_OMISR );
- mask = load_runtime_reg( pcsrbar, I2O_OMIMR );
- store_runtime_reg( pcsrbar, I2O_OMISR, stat & 0xffffffd7);
-
- stat &= mask;
- val->rsvd0 = ( stat & 0xffffffc0 ) >> 6;
- val->opqi = ( stat & 0x00000020 ) >> 5;
- val->rsvd1 = ( stat & 0x00000010 ) >> 4;
- val->odi = ( stat & 0x00000008 ) >> 3;
- val->rsvd2 = ( stat & 0x00000004 ) >> 2;
- val->om1i = ( stat & 0x00000002 ) >> 1;
- val->om0i = ( stat & 0x00000001 );
-
- return I2OSUCCESS;
-}
-
-/********************************************************************
- * function: I2OInMsgStatGet
- *
- * description: Local processor reads its inbound msg unit interrupt status.
- * Reading an interrupt status register,
- * the register will be cleared.
- *
- * The inbound msg interrupt status is AND with the inbound
- * msg interrupt mask and result is returned.
- *
- * note:
- * eumbbar must be passed to the function.
- ********************************************************************/
-I2OSTATUS I2OInMsgStatGet(unsigned int eumbbar, I2OIMSTAT *val)
-{
- unsigned int stat;
- unsigned int mask;
-
- if ( val == 0 )
- {
- return I2OINVALID;
- }
-
- /* read device's outbound status */
- stat = load_runtime_reg( eumbbar, I2O_OMISR );
- mask = load_runtime_reg( eumbbar, I2O_OMIMR );
- store_runtime_reg( eumbbar, I2O_OMISR, stat & 0xffffffe7 );
-
- stat &= mask;
- val->rsvd0 = ( stat & 0xfffffe00 ) >> 9;
- val->ofoi = ( stat & 0x00000100 ) >> 8;
- val->ipoi = ( stat & 0x00000080 ) >> 7;
- val->rsvd1 = ( stat & 0x00000040 ) >> 6;
- val->ipqi = ( stat & 0x00000020 ) >> 5;
- val->mci = ( stat & 0x00000010 ) >> 4;
- val->idi = ( stat & 0x00000008 ) >> 3;
- val->rsvd2 = ( stat & 0x00000004 ) >> 2;
- val->im1i = ( stat & 0x00000002 ) >> 1;
- val->im0i = ( stat & 0x00000001 );
-
- return I2OSUCCESS;
-
-}
-
-/***********************************************************
- * function: I2OFIFOInit
- *
- * description: Configure the I2O FIFO, including QBAR,
- * IFHPR/IFTPR, IPHPR/IPTPR, OFHPR/OFTPR,
- * OPHPR/OPTPR, MUCR.
- *
- * return I2OSUCCESS if no error,
- * otherwise return I2OQUEINVALID
- *
- * note: It is NOT this driver's responsibility of initializing
- * MFA blocks, i.e., FIFO queue itself. The MFA blocks
- * must be initialized before I2O unit can be used.
- ***********************************************************/
-I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
- QUEUE_SIZE sz, /* value of CQS of MUCR */
- unsigned int qba) /* queue base address that must be aligned at 1M */
-{
-
- if ( ( qba & 0xfffff ) != 0 )
- {
- /* QBA must be aligned at 1Mbyte boundary */
- return I2OQUEINVALID;
- }
-
- store_runtime_reg( eumbbar, I2O_QBAR, qba );
- store_runtime_reg( eumbbar, I2O_MUCR, (unsigned int)sz );
- store_runtime_reg( eumbbar, I2O_IFHPR, qba );
- store_runtime_reg( eumbbar, I2O_IFTPR, qba );
- store_runtime_reg( eumbbar, I2O_IPHPR, qba + 1 * ( sz << 11 ));
- store_runtime_reg( eumbbar, I2O_IPTPR, qba + 1 * ( sz << 11 ));
- store_runtime_reg( eumbbar, I2O_OFHPR, qba + 2 * ( sz << 11 ));
- store_runtime_reg( eumbbar, I2O_OFTPR, qba + 2 * ( sz << 11 ));
- store_runtime_reg( eumbbar, I2O_OPHPR, qba + 3 * ( sz << 11 ));
- store_runtime_reg( eumbbar, I2O_OPTPR, qba + 3 * ( sz << 11 ));
-
- fifo_stat.qsz = sz;
- fifo_stat.qba = qba;
-
- return I2OSUCCESS;
-}
-
-/**************************************************
- * function: I2OFIFOEnable
- *
- * description: Enable the circular queue
- * return I2OSUCCESS if no error.
- * Otherwise I2OQUEINVALID is returned.
- *
- * note:
- *************************************************/
-I2OSTATUS I2OFIFOEnable( unsigned int eumbbar )
-{
- unsigned int val;
-
- if ( fifo_stat.qba == 0xfffffff )
- {
- return I2OQUEINVALID;
- }
-
- val = load_runtime_reg( eumbbar, I2O_MUCR );
- store_runtime_reg( eumbbar, I2O_MUCR, val | 0x1 );
-
- return I2OSUCCESS;
-}
-
-/**************************************************
- * function: I2OFIFODisable
- *
- * description: Disable the circular queue
- *
- * note:
- *************************************************/
-void I2OFIFODisable( unsigned int eumbbar )
-{
- if ( fifo_stat.qba == 0xffffffff )
- {
- /* not enabled */
- return;
- }
-
- unsigned int val = load_runtime_reg( eumbbar, I2O_MUCR );
- store_runtime_reg( eumbbar, I2O_MUCR, val & 0xfffffffe );
-}
-
-/****************************************************
- * function: I2OFIFOAlloc
- *
- * description: Allocate a free MFA from free FIFO.
- * return I2OSUCCESS if no error.
- * return I2OQUEEMPTY if no more free MFA.
- * return I2OINVALID on other errors.
- *
- * A free MFA must be allocated before a
- * message can be posted.
- *
- * note:
- * PCI Master allocates a free MFA from inbound queue of device
- * (pcsrbar is the base,) through the inbound queue port of device
- * while local processor allocates a free MFA from its outbound
- * queue (eumbbar is the base.)
- *
- ****************************************************/
-I2OSTATUS I2OFIFOAlloc( LOCATION loc,
- unsigned int base,
- void **pMsg )
-{
- I2OSTATUS stat = I2OSUCCESS;
- void *pHdr, *pTil;
-
- if ( pMsg == 0 || *pMsg == 0 || fifo_stat.qba == 0xffffffff )
- {
- /* not configured */
- return I2OQUEINVALID;
- }
-
- if ( loc == REMOTE )
- {
- /* pcsrbar is the base and read the inbound free tail ptr */
- pTil = (void *)load_runtime_reg( base, I2O_IFQPR );
- if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
- {
- stat = I2OQUEEMPTY;
- }
- else
- {
- *pMsg = pTil;
- }
- }
- else
- {
- /* eumbbar is the base and read the outbound free tail ptr */
- pHdr = (void *)load_runtime_reg( base, I2O_OFHPR ); /* queue head */
- pTil = (void *)load_runtime_reg( base, I2O_OFTPR ); /* queue tail */
-
- /* check underflow */
- if ( pHdr == pTil )
- {
- /* hdr and til point to the same fifo item, no free MFA */
- stat = I2OQUEEMPTY;
- }
- else
- {
- /* update OFTPR */
- *pMsg = (void *)(*(unsigned char *)pTil);
- pTil = (void *)((unsigned int)pTil + 4);
- if ( (unsigned int)pTil == fifo_stat.qba + ( 4 * ( fifo_stat.qsz << 11 ) ) )
- {
- /* reach the upper limit */
- pTil = (void *)(fifo_stat.qba + ( 3 * (fifo_stat.qsz << 11) ));
- }
- store_runtime_reg( base, I2O_OFTPR, (unsigned int)pTil );
- }
- }
-
- return stat;
-}
-
-/******************************************************
- * function: I2OFIFOFree
- *
- * description: Free a used MFA back to free queue after
- * use.
- * return I2OSUCCESS if no error.
- * return I2OQUEFULL if inbound free queue
- * overflow
- *
- * note: PCI Master frees a MFA into device's outbound queue
- * (OFQPR) while local processor frees a MFA into its
- * inbound queue (IFHPR).
- *****************************************************/
-I2OSTATUS I2OFIFOFree( LOCATION loc,
- unsigned int base,
- void *pMsg )
-{
- void **pHdr, **pTil;
- I2OSTATUS stat = I2OSUCCESS;
-
- if ( fifo_stat.qba == 0xffffffff || pMsg == 0 )
- {
- return I2OQUEINVALID;
- }
-
- if ( loc == REMOTE )
- {
- /* pcsrbar is the base */
- store_runtime_reg( base, I2O_OFQPR, (unsigned int)pMsg );
- }
- else
- {
- /* eumbbar is the base */
- pHdr = (void **)load_runtime_reg( base, I2O_IFHPR );
- pTil = (void **)load_runtime_reg( base, I2O_IFTPR );
-
- /* store MFA */
- *pHdr = pMsg;
-
- /* update IFHPR */
- pHdr += 4;
-
- if ( (unsigned int)pHdr == fifo_stat.qba + ( fifo_stat.qsz << 11 ) )
- {
- /* reach the upper limit */
- pHdr = (void **)fifo_stat.qba;
- }
-
- /* check inbound free queue overflow */
- if ( pHdr != pTil )
- {
- store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr);
- }
- else
- {
- stat = I2OQUEFULL;
- }
-
- }
-
- return stat;
-
-}
-
-/*********************************************
- * function: I2OFIFOPost
- *
- * description: Post a msg into FIFO post queue
- * the value of msg must be the one
- * returned by I2OFIFOAlloc
- *
- * note: PCI Master posts a msg into device's inbound queue
- * (IFQPR) while local processor post a msg into device's
- * outbound queue (OPHPR)
- *********************************************/
-I2OSTATUS I2OFIFOPost( LOCATION loc,
- unsigned int base,
- void *pMsg )
-{
- void **pHdr, **pTil;
- I2OSTATUS stat = I2OSUCCESS;
-
- if ( fifo_stat.qba == 0xffffffff || pMsg == 0 )
- {
- return I2OQUEINVALID;
- }
-
- if ( loc == REMOTE )
- {
- /* pcsrbar is the base */
- store_runtime_reg( base, I2O_IFQPR, (unsigned int)pMsg );
- }
- else
- {
- /* eumbbar is the base */
- pHdr = (void **)load_runtime_reg( base, I2O_OPHPR );
- pTil = (void **)load_runtime_reg( base, I2O_OPTPR );
-
- /* store MFA */
- *pHdr = pMsg;
-
- /* update IFHPR */
- pHdr += 4;
-
- if ( (unsigned int)pHdr == fifo_stat.qba + 3 * ( fifo_stat.qsz << 11 ) )
- {
- /* reach the upper limit */
- pHdr = (void **)(fifo_stat.qba + 2 * ( fifo_stat.qsz << 11 ) );
- }
-
- /* check post queue overflow */
- if ( pHdr != pTil )
- {
- store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr);
- }
- else
- {
- stat = I2OQUEFULL;
- }
- }
-
- return stat;
-}
-
-/************************************************
- * function: I2OFIFOGet
- *
- * description: Read a msg from FIFO
- * This function should be called
- * only when there is a corresponding
- * msg interrupt.
- *
- * note: PCI Master reads a msg from device's outbound queue
- * (OFQPR) while local processor reads a msg from device's
- * inbound queue (IPTPR)
- ************************************************/
-I2OSTATUS I2OFIFOGet( LOCATION loc,
- unsigned int base,
- void **pMsg )
-{
- I2OSTATUS stat = I2OSUCCESS;
- void *pHdr, *pTil;
-
- if ( pMsg == 0 || *pMsg == 0 || fifo_stat.qba == 0xffffffff )
- {
- /* not configured */
- return I2OQUEINVALID;
- }
-
- if ( loc == REMOTE )
- {
- /* pcsrbar is the base */
- pTil = (void *)load_runtime_reg( base, I2O_OFQPR );
- if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
- {
- stat = I2OQUEEMPTY;
- }
- else
- {
- *pMsg = pTil;
- }
- }
- else
- {
- /* eumbbar is the base and read the outbound free tail ptr */
- pHdr = (void *)load_runtime_reg( base, I2O_IPHPR ); /* queue head */
- pTil = (void *)load_runtime_reg( base, I2O_IPTPR ); /* queue tail */
-
- /* check underflow */
- if ( pHdr == pTil )
- {
- /* no free MFA */
- stat = I2OQUEEMPTY;
- }
- else
- {
- /* update OFTPR */
- *pMsg = (void *)(*(unsigned char *)pTil);
- pTil = (void *)((unsigned int)pTil + 4);
- if ( (unsigned int)pTil == fifo_stat.qba + 2 * ( fifo_stat.qsz << 11 ) )
- {
- /* reach the upper limit */
- pTil = (void *)(fifo_stat.qba + 1 * (fifo_stat.qsz << 11) );
- }
-
- store_runtime_reg( base, I2O_IPTPR, (unsigned int)pTil );
- }
- }
-
- return stat;
-}
-
-/********************************************************
- * function: I2OIOP
- *
- * description: Get the I2O PCI configuration identification
- * register.
- *
- * note: PCI master should pass pcsrbar while local processor
- * should pass eumbbar.
- *********************************************************/
-I2OSTATUS I2OPCIConfigGet( LOCATION loc,
- unsigned int base,
- I2OIOP * val)
-{
- unsigned int tmp;
- if ( val == 0 )
- {
- return I2OINVALID;
- }
- tmp = load_runtime_reg( base, PCI_CFG_CLA );
- val->base_class = ( tmp & 0xFF) << 16;
- tmp = load_runtime_reg( base, PCI_CFG_SCL );
- val->sub_class= ( (tmp & 0xFF) << 8 );
- tmp = load_runtime_reg( base, PCI_CFG_PIC );
- val->prg_code = (tmp & 0xFF);
- return I2OSUCCESS;
-}
-
-/*********************************************************
- * function: I2OFIFOIntEnable
- *
- * description: Enable the circular post queue interrupt
- *
- * note:
- * PCI master enables outbound FIFO interrupt of device
- * pscrbar is the base
- * Device enables its inbound FIFO interrupt
- * eumbbar is the base
- *******************************************************/
-void I2OFIFOIntEnable( LOCATION loc, unsigned int base )
-{
- unsigned int reg, val;
-
- /* LOCATION - REMOTE : enable outbound message of device, pcsrbar as base
- * LOCAL : enable local inbound message, eumbbar as base
- */
- reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR );
- val = load_runtime_reg( base, reg );
-
- val &= 0xffffffdf; /* clear the msg interrupt bits */
- store_runtime_reg( base, reg, val );
-
-}
-
-/****************************************************
- * function: I2OFIFOIntDisable
- *
- * description: Disable the circular post queue interrupt
- *
- * note:
- * PCI master disables outbound FIFO interrupt of device
- * (pscrbar is the base)
- * Device disables its inbound FIFO interrupt
- * (eumbbar is the base)
- *****************************************************/
-void I2OFIFOIntDisable( LOCATION loc, unsigned int base )
-{
-
- /* LOCATION - REMOTE : disable outbound message interrupt of device, pcsrbar as base
- * LOCAL : disable local inbound message interrupt, eumbbar as base
- */
- unsigned int reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR );
- unsigned int val = load_runtime_reg( base, reg );
-
- val |= 0x00000020; /* masked out the msg interrupt bits */
- store_runtime_reg( base, reg, val );
-
-}
-
-/*********************************************************
- * function: I2OFIFOOverflowIntEnable
- *
- * description: Enable the circular queue overflow interrupt
- *
- * note:
- * Device enables its inbound FIFO post overflow interrupt
- * and outbound free overflow interrupt.
- * eumbbar is the base
- *******************************************************/
-void I2OFIFOOverflowIntEnable( unsigned int eumbbar )
-{
- unsigned int val = load_runtime_reg( eumbbar, I2O_IMIMR );
-
- val &= 0xfffffe7f; /* clear the two overflow interrupt bits */
- store_runtime_reg( eumbbar, I2O_IMIMR, val );
-
-}
-
-/****************************************************
- * function: I2OFIFOOverflowIntDisable
- *
- * description: Disable the circular queue overflow interrupt
- *
- * note:
- * Device disables its inbound post FIFO overflow interrupt
- * and outbound free FIFO overflow interrupt
- * (eumbbar is the base)
- *****************************************************/
-void I2OFIFOOverflowIntDisable( unsigned int eumbbar )
-{
-
- unsigned int val = load_runtime_reg( eumbbar, I2O_IMIMR );
-
- val |= 0x00000180; /* masked out the msg overflow interrupt bits */
- store_runtime_reg( eumbbar, I2O_IMIMR, val );
-}
+++ /dev/null
-/**************************************
- *
- * copyright @ Motorola, 1999
- *
- **************************************/
-
-/**********************************************************
- * function: load_runtime_reg
- *
- * input: r3 - value of eumbbar
- * r4 - register offset in embedded utility space
- *
- * output: r3 - register content
- **********************************************************/
- .text
- .align 2
- .global load_runtime_reg
-
-load_runtime_reg:
-
- xor r5,r5,r5
- or r5,r5,r3 /* save eumbbar */
-
- lwbrx r3,r4,r5
- sync
-
- bclr 20, 0
-
-/****************************************************************
- * function: store_runtime_reg
- *
- * input: r3 - value of eumbbar
- * r4 - register offset in embedded utility space
- * r5 - new value to be stored
- *
- ****************************************************************/
- .text
- .align 2
- .global store_runtime_reg
-store_runtime_reg:
-
- xor r0,r0,r0
-
- stwbrx r5, r4, r3
- sync
-
- bclr 20,0
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o kgdb.o
-OBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
+COBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \
bedbug_603e.o pci.o spi.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS) kgdb.o
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(obj)kgdb.o
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# Copyright 2004 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
-
-START = start.o \
- resetvec.o
+LIB = $(obj)lib$(CPU).a
-COBJS = traps.o \
- cpu.o \
- cpu_init.o \
- speed.o \
- interrupts.o \
- i2c.o \
- spd_sdram.o
+START = start.o resetvec.o
+COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
+ i2c.o spd_sdram.o
-OBJS = $(COBJS)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
-all: .depend $(START) $(LIB)
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2002,2003 Motorola Inc.
# Xianghua Xiao,X.Xiao@motorola.com
#
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o resetvec.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
- pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o
-OBJS = $(COBJS)
+ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
-all: .depend $(START) $(LIB)
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#include <command.h>
#include <asm/cache.h>
-/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
int checkcpu (void)
{
return dma_check();
}
#endif
+
+
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_cpu_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ ulong clock;
+ int len;
+
+ clock = bd->bi_busfreq;
+ p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+#if defined(CONFIG_MPC85XX_TSEC1)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
+ memcpy(p, bd->bi_enetaddr, 6);
+#endif
+
+#if defined(CONFIG_HAS_ETH1)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
+ memcpy(p, bd->bi_enet1addr, 6);
+#endif
+
+#if defined(CONFIG_HAS_ETH2)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
+ memcpy(p, bd->bi_enet2addr, 6);
+#endif
+
+#if defined(CONFIG_HAS_ETH3)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
+ memcpy(p, bd->bi_enet3addr, 6);
+#endif
+
+}
+#endif
DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_CPM2
static void config_8560_ioports (volatile immap_t * immr)
{
+++ /dev/null
-/*
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao <x.xiao@motorola.com>
- * Adapted for Motorola 85xx chip.
- *
- * (C) Copyright 2003
- * Gleb Natapov <gnatapov@mrv.com>
- * Some bits are taken from linux driver writen by adrian@humboldt.co.uk
- *
- * Hardware I2C driver for MPC107 PCI bridge.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_HARD_I2C
-#include <i2c.h>
-
-#define TIMEOUT (CFG_HZ/4)
-
-#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3000))
-
-#define I2CADR &I2C_Addr[0]
-#define I2CFDR &I2C_Addr[4]
-#define I2CCCR &I2C_Addr[8]
-#define I2CCSR &I2C_Addr[12]
-#define I2CCDR &I2C_Addr[16]
-#define I2CDFSRR &I2C_Addr[20]
-
-#define I2C_READ 1
-#define I2C_WRITE 0
-
-void
-i2c_init(int speed, int slaveadd)
-{
- /* stop I2C controller */
- writeb(0x0, I2CCCR);
-
- /* set clock */
- writeb(0x3f, I2CFDR);
-
- /* set default filter */
- writeb(0x10,I2CDFSRR);
-
- /* write slave address */
- writeb(slaveadd, I2CADR);
-
- /* clear status register */
- writeb(0x0, I2CCSR);
-
- /* start I2C controller */
- writeb(MPC85xx_I2CCR_MEN, I2CCCR);
-}
-
-static __inline__ int
-i2c_wait4bus (void)
-{
- ulong timeval = get_timer (0);
-
- while (readb(I2CCSR) & MPC85xx_I2CSR_MBB) {
- if (get_timer (timeval) > TIMEOUT) {
- return -1;
- }
- }
-
- return 0;
-}
-
-static __inline__ int
-i2c_wait (int write)
-{
- u32 csr;
- ulong timeval = get_timer (0);
-
- do {
- csr = readb(I2CCSR);
-
- if (!(csr & MPC85xx_I2CSR_MIF))
- continue;
-
- writeb(0x0, I2CCSR);
-
- if (csr & MPC85xx_I2CSR_MAL) {
- debug("i2c_wait: MAL\n");
- return -1;
- }
-
- if (!(csr & MPC85xx_I2CSR_MCF)) {
- debug("i2c_wait: unfinished\n");
- return -1;
- }
-
- if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) {
- debug("i2c_wait: No RXACK\n");
- return -1;
- }
-
- return 0;
- } while (get_timer (timeval) < TIMEOUT);
-
- debug("i2c_wait: timed out\n");
- return -1;
-}
-
-static __inline__ int
-i2c_write_addr (u8 dev, u8 dir, int rsta)
-{
- writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX |
- (rsta?MPC85xx_I2CCR_RSTA:0),
- I2CCCR);
-
- writeb((dev << 1) | dir, I2CCDR);
-
- if (i2c_wait (I2C_WRITE) < 0)
- return 0;
-
- return 1;
-}
-
-static __inline__ int
-__i2c_write (u8 *data, int length)
-{
- int i;
-
- writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX,
- I2CCCR);
-
- for (i=0; i < length; i++) {
- writeb(data[i], I2CCDR);
-
- if (i2c_wait (I2C_WRITE) < 0)
- break;
- }
-
- return i;
-}
-
-static __inline__ int
-__i2c_read (u8 *data, int length)
-{
- int i;
-
- writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
- ((length == 1) ? MPC85xx_I2CCR_TXAK : 0),
- I2CCCR);
-
- /* dummy read */
- readb(I2CCDR);
-
- for (i=0; i < length; i++) {
- if (i2c_wait (I2C_READ) < 0)
- break;
-
- /* Generate ack on last next to last byte */
- if (i == length - 2)
- writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
- MPC85xx_I2CCR_TXAK,
- I2CCCR);
-
- /* Generate stop on last byte */
- if (i == length - 1)
- writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR);
-
- data[i] = readb(I2CCDR);
- }
-
- return i;
-}
-
-int
-i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
-{
- int i = 0;
- u8 *a = (u8*)&addr;
-
- if (i2c_wait4bus () < 0)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
- goto exit;
-
- if (__i2c_write (&a[4 - alen], alen) != alen)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_READ, 1) == 0)
- goto exit;
-
- i = __i2c_read (data, length);
-
- exit:
- writeb(MPC85xx_I2CCR_MEN, I2CCCR);
-
- return !(i == length);
-}
-
-int
-i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
-{
- int i = 0;
- u8 *a = (u8*)&addr;
-
- if (i2c_wait4bus () < 0)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
- goto exit;
-
- if (__i2c_write (&a[4 - alen], alen) != alen)
- goto exit;
-
- i = __i2c_write (data, length);
-
- exit:
- writeb(MPC85xx_I2CCR_MEN, I2CCCR);
-
- return !(i == length);
-}
-
-int i2c_probe (uchar chip)
-{
- int tmp;
-
- /*
- * Try to read the first location of the chip. The underlying
- * driver doesn't appear to support sending just the chip address
- * and looking for an <ACK> back.
- */
- udelay(10000);
- return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
-}
-
-uchar i2c_reg_read (uchar i2c_addr, uchar reg)
-{
- uchar buf[1];
-
- i2c_read (i2c_addr, reg, 1, buf, 1);
-
- return (buf[0]);
-}
-
-void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
-{
- i2c_write (i2c_addr, reg, 1, &val, 1);
-}
-
-#endif /* CONFIG_HARD_I2C */
#include <asm/cpm_85xx.h>
#include <pci.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
#if defined(CONFIG_PCI)
+static struct pci_controller *pci_hose;
+
void
-pci_mpc85xx_init(struct pci_controller *hose)
+pci_mpc85xx_init(struct pci_controller *board_hose)
{
+ u16 reg16;
+ u32 dev;
+
volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
volatile ccsr_pcix_t *pcix = &immap->im_pcix;
+#ifdef CONFIG_MPC85XX_PCI2
+ volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
+#endif
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ struct pci_controller * hose;
- u16 reg16;
+ pci_hose = board_hose;
+
+ hose = &pci_hose[0];
hose->first_busno = 0;
hose->last_busno = 0xff;
- pci_set_region(hose->regions + 0,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- pci_set_region(hose->regions + 1,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 2;
-
pci_setup_indirect(hose,
(CFG_IMMR+0x8000),
(CFG_IMMR+0x8004));
+ /*
+ * Hose scan.
+ */
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+
+ if (!(gur->pordevsr & PORDEVSR_PCI)) {
+ /* PCI-X init */
+ if (CONFIG_SYS_CLK_FREQ < 66000000)
+ printf("PCI-X will only work at 66 MHz\n");
+
+ reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+ pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
+ }
+
pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
pcix->potear1 = 0x00000000;
- pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+ pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
pcix->powbear1 = 0x00000000;
- pcix->powar1 = 0x8004401c; /* 512M MEM space */
+ pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
+ POWAR_MEM_WRITE | POWAR_MEM_512M);
- pcix->potar2 = 0x00000000;
+ pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
pcix->potear2 = 0x00000000;
- pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
+ pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
pcix->powbear2 = 0x00000000;
- pcix->powar2 = 0x80088017; /* 16M IO space */
+ pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
+ POWAR_IO_WRITE | POWAR_IO_1M);
pcix->pitar1 = 0x00000000;
pcix->piwbar1 = 0x00000000;
- pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
- * Snoop R/W, 2G */
+ pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
+ PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
- /*
- * Hose scan.
- */
- pci_register_hose(hose);
+ pcix->powar3 = 0;
+ pcix->powar4 = 0;
+ pcix->piwar2 = 0;
+ pcix->piwar3 = 0;
- pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+ pci_set_region(hose->regions + 0,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
- /*
- * Clear non-reserved bits in status register.
- */
- pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
- pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 2;
+
+ pci_register_hose(hose);
#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
/*
#endif
hose->last_busno = pci_hose_scan(hose);
+
+#ifdef CONFIG_MPC85XX_PCI2
+ hose = &pci_hose[1];
+
+ hose->first_busno = pci_hose[0].last_busno + 1;
+ hose->last_busno = 0xff;
+
+ pci_setup_indirect(hose,
+ (CFG_IMMR+0x9000),
+ (CFG_IMMR+0x9004));
+
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+
+ pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff;
+ pcix2->potear1 = 0x00000000;
+ pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
+ pcix2->powbear1 = 0x00000000;
+ pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
+ POWAR_MEM_WRITE | POWAR_MEM_512M);
+
+ pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
+ pcix2->potear2 = 0x00000000;
+ pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
+ pcix2->powbear2 = 0x00000000;
+ pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
+ POWAR_IO_WRITE | POWAR_IO_1M);
+
+ pcix2->pitar1 = 0x00000000;
+ pcix2->piwbar1 = 0x00000000;
+ pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
+ PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
+
+ pcix2->powar3 = 0;
+ pcix2->powar4 = 0;
+ pcix2->piwar2 = 0;
+ pcix2->piwar3 = 0;
+
+ pci_set_region(hose->regions + 0,
+ CFG_PCI2_MEM_BASE,
+ CFG_PCI2_MEM_PHYS,
+ CFG_PCI2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ pci_set_region(hose->regions + 1,
+ CFG_PCI2_IO_BASE,
+ CFG_PCI2_IO_PHYS,
+ CFG_PCI2_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 2;
+
+ /*
+ * Hose scan.
+ */
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+#endif
}
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = pci_hose[0].first_busno;
+ p[1] = pci_hose[0].last_busno;
+ }
+
+#ifdef CONFIG_MPC85XX_PCI2
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = pci_hose[1].first_busno;
+ p[1] = pci_hose[1].last_busno;
+ }
+#endif
+}
+#endif /* CONFIG_OF_FLAT_TREE */
#endif /* CONFIG_PCI */
800,
900,
250,
- 330, /* FIXME: Is 333 better/valid? */
- 660, /* FIXME: Is 667 better/valid? */
+ 330,
+ 660,
750,
0, /* undefined */
0 /* undefined */
}
+/*
+ * Determine Refresh Rate. Ignore self refresh bit on DDR I.
+ * Table from SPD Spec, Byte 12, converted to picoseconds and
+ * filled in with "default" normal values.
+ */
+unsigned int determine_refresh_rate(unsigned int spd_refresh)
+{
+ unsigned int refresh_time_ns[8] = {
+ 15625000, /* 0 Normal 1.00x */
+ 3900000, /* 1 Reduced .25x */
+ 7800000, /* 2 Extended .50x */
+ 31300000, /* 3 Extended 2.00x */
+ 62500000, /* 4 Extended 4.00x */
+ 125000000, /* 5 Extended 8.00x */
+ 15625000, /* 6 Normal 1.00x filler */
+ 15625000, /* 7 Normal 1.00x filler */
+ };
+
+ return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
+}
+
+
long int
spd_sdram(void)
{
unsigned int rank_density;
unsigned int odt_rd_cfg, odt_wr_cfg;
unsigned int odt_cfg, mode_odt_enable;
+ unsigned int refresh_clk;
+#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
+ unsigned char clk_adjust;
+#endif
unsigned int dqs_cfg;
unsigned char twr_clk, twtr_clk, twr_auto_clk;
unsigned int tCKmin_ps, tCKmax_ps;
ddr->sdram_mode_2 = 0;
debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
-
/*
- * Determine Refresh Rate. Ignore self refresh bit on DDR I.
- * Table from SPD Spec, Byte 12, converted to picoseconds and
- * filled in with "default" normal values.
+ * Determine Refresh Rate.
*/
- {
- unsigned int refresh_clk;
- unsigned int refresh_time_ns[8] = {
- 15625000, /* 0 Normal 1.00x */
- 3900000, /* 1 Reduced .25x */
- 7800000, /* 2 Extended .50x */
- 31300000, /* 3 Extended 2.00x */
- 62500000, /* 4 Extended 4.00x */
- 125000000, /* 5 Extended 8.00x */
- 15625000, /* 6 Normal 1.00x filler */
- 15625000, /* 7 Normal 1.00x filler */
- };
-
- refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]);
+ refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
- /*
- * Set BSTOPRE to 0x100 for page mode
- * If auto-charge is used, set BSTOPRE = 0
- */
- ddr->sdram_interval =
- (0
- | (refresh_clk & 0x3fff) << 16
- | 0x100
- );
- debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
- }
+ /*
+ * Set BSTOPRE to 0x100 for page mode
+ * If auto-charge is used, set BSTOPRE = 0
+ */
+ ddr->sdram_interval =
+ (0
+ | (refresh_clk & 0x3fff) << 16
+ | 0x100
+ );
+ debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
/*
* Is this an ECC DDR chip?
#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
- {
- unsigned char clk_adjust;
-
- /*
- * Setup the clock control.
- * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
- * SDRAM_CLK_CNTL[5-7] = Clock Adjust
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- if (spd.mem_type == SPD_MEMTYPE_DDR) {
- clk_adjust = 0x6;
- } else {
- clk_adjust = 0x7;
- }
+ /*
+ * Setup the clock control.
+ * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
+ * SDRAM_CLK_CNTL[5-7] = Clock Adjust
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR)
+ clk_adjust = 0x6;
+ else
+ clk_adjust = 0x7;
- ddr->sdram_clk_cntl = (0
+ ddr->sdram_clk_cntl = (0
| 0x80000000
| (clk_adjust << 23)
);
- debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
- }
+ debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
#endif
/*
}
}
- /* 8K */
- dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
- /* 16K */
- dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
- /* 32K */
- dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
- /* 64K */
- dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
- /* 128k */
- dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
- /* 256k */
- dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
- /* 512k */
- dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
- /* 1M */
- dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
- /* 2M */
- dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
- /* 4M */
- dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
+ dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
+ dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
+ dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
+ dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
+ dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
+ dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
+ dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
+ dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
+ dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
+ dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
--- /dev/null
+#
+# (C) Copyright 2002,2003 Motorola Inc.
+# Xianghua Xiao,X.Xiao@motorola.com
+#
+# (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port)
+# Jeff Brown
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).a
+
+START = start.o #resetvec.o
+SOBJS = cache.o
+COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
+ pci.o pcie_indirect.o spd_sdram.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(ASOBJS) $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#include <config.h>
+#include <mpc86xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#ifndef CACHE_LINE_SIZE
+# define CACHE_LINE_SIZE L1_CACHE_BYTES
+#endif
+
+#if CACHE_LINE_SIZE == 128
+#define LG_CACHE_LINE_SIZE 7
+#elif CACHE_LINE_SIZE == 32
+#define LG_CACHE_LINE_SIZE 5
+#elif CACHE_LINE_SIZE == 16
+#define LG_CACHE_LINE_SIZE 4
+#elif CACHE_LINE_SIZE == 8
+#define LG_CACHE_LINE_SIZE 3
+#else
+# error "Invalid cache line size!"
+#endif
+
+/*
+ * Most of this code is taken from 74xx_7xx/cache.S
+ * and then cleaned up a bit
+ */
+
+/*
+ * Invalidate L1 instruction cache.
+ */
+_GLOBAL(invalidate_l1_instruction_cache)
+ /* use invalidate-all bit in HID0 */
+ mfspr r3,HID0
+ ori r3,r3,HID0_ICFI
+ mtspr HID0,r3
+ isync
+ blr
+
+/*
+ * Invalidate L1 data cache.
+ */
+_GLOBAL(invalidate_l1_data_cache)
+ mfspr r3,HID0
+ ori r3,r3,HID0_DCFI
+ mtspr HID0,r3
+ isync
+ blr
+
+/*
+ * Flush data cache.
+ */
+_GLOBAL(flush_data_cache)
+ lis r3,0
+ lis r5,CACHE_LINE_SIZE
+flush:
+ cmp 0,1,r3,r5
+ bge done
+ lwz r5,0(r3)
+ lis r5,CACHE_LINE_SIZE
+ addi r3,r3,0x4
+ b flush
+done:
+ blr
+/*
+ * Write any modified data cache blocks out to memory
+ * and invalidate the corresponding instruction cache blocks.
+ * This is a no-op on the 601.
+ *
+ * flush_icache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(flush_icache_range)
+ li r5,CACHE_LINE_SIZE-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,LG_CACHE_LINE_SIZE
+ beqlr
+ mtctr r4
+ mr r6,r3
+1: dcbst 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ sync /* wait for dcbst's to get to ram */
+ mtctr r4
+2: icbi 0,r6
+ addi r6,r6,CACHE_LINE_SIZE
+ bdnz 2b
+ sync /* additional sync needed on g4 */
+ isync
+ blr
+/*
+ * Write any modified data cache blocks out to memory.
+ * Does not invalidate the corresponding cache lines (especially for
+ * any corresponding instruction cache).
+ *
+ * clean_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(clean_dcache_range)
+ li r5,CACHE_LINE_SIZE-1
+ andc r3,r3,r5 /* align r3 down to cache line */
+ subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
+ add r4,r4,r5 /* r4 += cache_line_size-1 */
+ srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
+ beqlr /* if r4 == 0 return */
+ mtctr r4 /* ctr = r4 */
+
+ sync
+1: dcbst 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ sync /* wait for dcbst's to get to ram */
+ blr
+
+/*
+ * Write any modified data cache blocks out to memory
+ * and invalidate the corresponding instruction cache blocks.
+ *
+ * flush_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(flush_dcache_range)
+ li r5,CACHE_LINE_SIZE-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,LG_CACHE_LINE_SIZE
+ beqlr
+ mtctr r4
+
+ sync
+1: dcbf 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ sync /* wait for dcbf's to get to ram */
+ blr
+
+/*
+ * Like above, but invalidate the D-cache. This is used by the 8xx
+ * to invalidate the cache so the PPC core doesn't get stale data
+ * from the CPM (no cache snooping here :-).
+ *
+ * invalidate_dcache_range(unsigned long start, unsigned long stop)
+ */
+_GLOBAL(invalidate_dcache_range)
+ li r5,CACHE_LINE_SIZE-1
+ andc r3,r3,r5
+ subf r4,r3,r4
+ add r4,r4,r5
+ srwi. r4,r4,LG_CACHE_LINE_SIZE
+ beqlr
+ mtctr r4
+
+ sync
+1: dcbi 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ sync /* wait for dcbi's to get to ram */
+ blr
+
+/*
+ * Flush a particular page from the data cache to RAM.
+ * Note: this is necessary because the instruction cache does *not*
+ * snoop from the data cache.
+ *
+ * void __flush_page_to_ram(void *page)
+ */
+_GLOBAL(__flush_page_to_ram)
+ rlwinm r3,r3,0,0,19 /* Get page base address */
+ li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
+ mtctr r4
+ mr r6,r3
+0: dcbst 0,r3 /* Write line to ram */
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 0b
+ sync
+ mtctr r4
+1: icbi 0,r6
+ addi r6,r6,CACHE_LINE_SIZE
+ bdnz 1b
+ sync
+ isync
+ blr
+
+/*
+ * Flush a particular page from the instruction cache.
+ * Note: this is necessary because the instruction cache does *not*
+ * snoop from the data cache.
+ *
+ * void __flush_icache_page(void *page)
+ */
+_GLOBAL(__flush_icache_page)
+ li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
+ mtctr r4
+1: icbi 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ sync
+ isync
+ blr
+
+/*
+ * Clear a page using the dcbz instruction, which doesn't cause any
+ * memory traffic (except to write out any cache lines which get
+ * displaced). This only works on cacheable memory.
+ */
+_GLOBAL(clear_page)
+ li r0,4096/CACHE_LINE_SIZE
+ mtctr r0
+1: dcbz 0,r3
+ addi r3,r3,CACHE_LINE_SIZE
+ bdnz 1b
+ blr
+
+/*
+ * Enable L1 Instruction cache
+ */
+_GLOBAL(icache_enable)
+ mfspr r3, HID0
+ li r5, HID0_ICFI|HID0_ILOCK
+ andc r3, r3, r5
+ ori r3, r3, HID0_ICE
+ ori r5, r3, HID0_ICFI
+ mtspr HID0, r5
+ mtspr HID0, r3
+ isync
+ blr
+
+/*
+ * Disable L1 Instruction cache
+ */
+_GLOBAL(icache_disable)
+ mfspr r3, HID0
+ li r5, 0
+ ori r5, r5, HID0_ICE
+ andc r3, r3, r5
+ mtspr HID0, r3
+ isync
+ blr
+
+/*
+ * Is instruction cache enabled?
+ */
+_GLOBAL(icache_status)
+ mfspr r3, HID0
+ andi. r3, r3, HID0_ICE
+ blr
+
+
+_GLOBAL(l1dcache_enable)
+ mfspr r3, HID0
+ li r5, HID0_DCFI|HID0_DLOCK
+ andc r3, r3, r5
+ mtspr HID0, r3 /* no invalidate, unlock */
+ ori r3, r3, HID0_DCE
+ ori r5, r3, HID0_DCFI
+ mtspr HID0, r5 /* enable + invalidate */
+ mtspr HID0, r3 /* enable */
+ sync
+ blr
+
+/*
+ * Enable data cache(s) - L1 and optionally L2
+ * Calls l2cache_enable. LR saved in r5
+ */
+_GLOBAL(dcache_enable)
+ mfspr r3, HID0
+ li r5, HID0_DCFI|HID0_DLOCK
+ andc r3, r3, r5
+ mtspr HID0, r3 /* no invalidate, unlock */
+ ori r3, r3, HID0_DCE
+ ori r5, r3, HID0_DCFI
+ mtspr HID0, r5 /* enable + invalidate */
+ mtspr HID0, r3 /* enable */
+ sync
+#ifdef CFG_L2
+ mflr r5
+ bl l2cache_enable /* uses r3 and r4 */
+ sync
+ mtlr r5
+#endif
+ blr
+
+
+/*
+ * Disable data cache(s) - L1 and optionally L2
+ * Calls flush_data_cache and l2cache_disable_no_flush.
+ * LR saved in r4
+ */
+_GLOBAL(dcache_disable)
+ mflr r4 /* save link register */
+ bl flush_data_cache /* uses r3 and r5 */
+ sync
+ mfspr r3, HID0
+ li r5, HID0_DCFI|HID0_DLOCK
+ andc r3, r3, r5
+ mtspr HID0, r3 /* no invalidate, unlock */
+ li r5, HID0_DCE|HID0_DCFI
+ andc r3, r3, r5 /* no enable, no invalidate */
+ mtspr HID0, r3
+ sync
+#ifdef CFG_L2
+ bl l2cache_disable_no_flush /* uses r3 */
+#endif
+ mtlr r4 /* restore link register */
+ blr
+
+/*
+ * Is data cache enabled?
+ */
+_GLOBAL(dcache_status)
+ mfspr r3, HID0
+ andi. r3, r3, HID0_DCE
+ blr
+
+/*
+ * Invalidate L2 cache using L2I, assume L2 is enabled
+ */
+_GLOBAL(l2cache_invalidate)
+ mfspr r3, l2cr
+ rlwinm. r3, r3, 0, 0, 0
+ beq 1f
+
+ mfspr r3, l2cr
+ rlwinm r3, r3, 0, 1, 31
+
+#ifdef CONFIG_ALTIVEC
+ dssall
+#endif
+ sync
+ mtspr l2cr, r3
+ sync
+1: mfspr r3, l2cr
+ oris r3, r3, L2CR_L2I@h
+ mtspr l2cr, r3
+
+invl2:
+ mfspr r3, l2cr
+ andi. r3, r3, L2CR_L2I@h
+ bne invl2
+ blr
+
+/*
+ * Enable L2 cache
+ * Calls l2cache_invalidate. LR is saved in r4
+ */
+_GLOBAL(l2cache_enable)
+ mflr r4 /* save link register */
+ bl l2cache_invalidate /* uses r3 */
+ sync
+ lis r3, L2_ENABLE@h
+ ori r3, r3, L2_ENABLE@l
+ mtspr l2cr, r3
+ isync
+ mtlr r4 /* restore link register */
+ blr
+
+/*
+ * Disable L2 cache
+ * Calls flush_data_cache. LR is saved in r4
+ */
+_GLOBAL(l2cache_disable)
+ mflr r4 /* save link register */
+ bl flush_data_cache /* uses r3 and r5 */
+ sync
+ mtlr r4 /* restore link register */
+l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
+ lis r3, L2_INIT@h
+ ori r3, r3, L2_INIT@l
+ mtspr l2cr, r3
+ isync
+ blr
--- /dev/null
+#
+# (C) Copyright 2004 Freescale Semiconductor.
+# Jeff Brown
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/cache.h>
+#include <mpc86xx.h>
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+#ifdef CONFIG_MPC8641HPCN
+extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag,
+ int argc, char *argv[]);
+#endif
+
+
+int
+checkcpu(void)
+{
+ sys_info_t sysinfo;
+ uint pvr, svr;
+ uint ver;
+ uint major, minor;
+ uint lcrr; /* local bus clock ratio register */
+ uint clkdiv; /* clock divider portion of lcrr */
+
+ puts("Freescale PowerPC\n");
+
+ pvr = get_pvr();
+ ver = PVR_VER(pvr);
+ major = PVR_MAJ(pvr);
+ minor = PVR_MIN(pvr);
+
+ puts("CPU:\n");
+ puts(" Core: ");
+
+ switch (ver) {
+ case PVR_VER(PVR_86xx):
+ puts("E600");
+ break;
+ default:
+ puts("Unknown");
+ break;
+ }
+ printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
+
+ svr = get_svr();
+ ver = SVR_VER(svr);
+ major = SVR_MAJ(svr);
+ minor = SVR_MIN(svr);
+
+ puts(" System: ");
+ switch (ver) {
+ case SVR_8641:
+ if (SVR_SUBVER(svr) == 1) {
+ puts("8641D");
+ } else {
+ puts("8641");
+ }
+ break;
+ default:
+ puts("Unknown");
+ break;
+ }
+ printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
+
+ get_sys_info(&sysinfo);
+
+ puts(" Clocks: ");
+ printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
+ printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
+ printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
+
+#if defined(CFG_LBC_LCRR)
+ lcrr = CFG_LBC_LCRR;
+#else
+ {
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+ lcrr = lbc->lcrr;
+ }
+#endif
+ clkdiv = lcrr & 0x0f;
+ if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
+ printf("LBC:%4lu MHz\n",
+ sysinfo.freqSystemBus / 1000000 / clkdiv);
+ } else {
+ printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
+ }
+
+ puts(" L2: ");
+ if (get_l2cr() & 0x80000000)
+ puts("Enabled\n");
+ else
+ puts("Disabled\n");
+
+ return 0;
+}
+
+
+static inline void
+soft_restart(unsigned long addr)
+{
+#ifndef CONFIG_MPC8641HPCN
+
+ /*
+ * SRR0 has system reset vector, SRR1 has default MSR value
+ * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
+ */
+
+ __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
+ __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
+ __asm__ __volatile__ ("mtspr 27, 4");
+ __asm__ __volatile__ ("rfi");
+
+#else /* CONFIG_MPC8641HPCN */
+
+ out8(PIXIS_BASE + PIXIS_RST, 0);
+
+#endif /* !CONFIG_MPC8641HPCN */
+
+ while (1) ; /* not reached */
+}
+
+
+/*
+ * No generic way to do board reset. Simply call soft_reset.
+ */
+void
+do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+#ifndef CONFIG_MPC8641HPCN
+
+#ifdef CFG_RESET_ADDRESS
+ ulong addr = CFG_RESET_ADDRESS;
+#else
+ /*
+ * note: when CFG_MONITOR_BASE points to a RAM address,
+ * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
+ * address. Better pick an address known to be invalid on your
+ * system and assign it to CFG_RESET_ADDRESS.
+ */
+ ulong addr = CFG_MONITOR_BASE - sizeof(ulong);
+#endif
+
+ /* flush and disable I/D cache */
+ __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
+ __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
+ __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
+ __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 4");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 5");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
+
+ soft_restart(addr);
+
+#else /* CONFIG_MPC8641HPCN */
+
+ mpc8641_reset_board(cmdtp, flag, argc, argv);
+
+#endif /* !CONFIG_MPC8641HPCN */
+
+ while (1) ; /* not reached */
+}
+
+
+/*
+ * Get timebase clock frequency
+ */
+unsigned long
+get_tbclk(void)
+{
+ sys_info_t sys_info;
+
+ get_sys_info(&sys_info);
+ return (sys_info.freqSystemBus + 3L) / 4L;
+}
+
+
+#if defined(CONFIG_WATCHDOG)
+void
+watchdog_reset(void)
+{
+}
+#endif /* CONFIG_WATCHDOG */
+
+
+#if defined(CONFIG_DDR_ECC)
+void
+dma_init(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_dma_t *dma = &immap->im_dma;
+
+ dma->satr0 = 0x00040000;
+ dma->datr0 = 0x00040000;
+ asm("sync; isync");
+}
+
+uint
+dma_check(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile uint status = dma->sr0;
+
+ /* While the channel is busy, spin */
+ while ((status & 4) == 4) {
+ status = dma->sr0;
+ }
+
+ if (status != 0) {
+ printf("DMA Error: status = %x\n", status);
+ }
+ return status;
+}
+
+int
+dma_xfer(void *dest, uint count, void *src)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_dma_t *dma = &immap->im_dma;
+
+ dma->dar0 = (uint) dest;
+ dma->sar0 = (uint) src;
+ dma->bcr0 = count;
+ dma->mr0 = 0xf000004;
+ asm("sync;isync");
+ dma->mr0 = 0xf000005;
+ asm("sync;isync");
+ return dma_check();
+}
+
+#endif /* CONFIG_DDR_ECC */
+
+
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_cpu_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ ulong clock;
+ int len;
+
+ clock = bd->bi_busfreq;
+ p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+ p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
+ if (p != NULL)
+ *p = cpu_to_be32(clock);
+
+#if defined(CONFIG_MPC86XX_TSEC1)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
+ memcpy(p, bd->bi_enetaddr, 6);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC2)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
+ memcpy(p, bd->bi_enet1addr, 6);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC3)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
+ memcpy(p, bd->bi_enet2addr, 6);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC4)
+ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
+ memcpy(p, bd->bi_enet3addr, 6);
+#endif
+
+}
+#endif
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * cpu_init.c - low level cpu init
+ */
+
+#include <common.h>
+#include <mpc86xx.h>
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map
+ * initialize a bunch of registers
+ */
+
+void cpu_init_f(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+
+ /* Clear initial global data */
+ memset ((void *) gd, 0, sizeof (gd_t));
+
+ /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
+ * addresses - these have to be modified later when FLASH size
+ * has been determined
+ */
+
+#if defined(CFG_OR0_REMAP)
+ memctl->or0 = CFG_OR0_REMAP;
+#endif
+#if defined(CFG_OR1_REMAP)
+ memctl->or1 = CFG_OR1_REMAP;
+#endif
+
+ /* now restrict to preliminary range */
+#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
+ memctl->br0 = CFG_BR0_PRELIM;
+ memctl->or0 = CFG_OR0_PRELIM;
+#endif
+
+#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
+ memctl->or1 = CFG_OR1_PRELIM;
+ memctl->br1 = CFG_BR1_PRELIM;
+#endif
+
+#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
+ memctl->or2 = CFG_OR2_PRELIM;
+ memctl->br2 = CFG_BR2_PRELIM;
+#endif
+
+#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
+ memctl->or3 = CFG_OR3_PRELIM;
+ memctl->br3 = CFG_BR3_PRELIM;
+#endif
+
+#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
+ memctl->or4 = CFG_OR4_PRELIM;
+ memctl->br4 = CFG_BR4_PRELIM;
+#endif
+
+#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
+ memctl->or5 = CFG_OR5_PRELIM;
+ memctl->br5 = CFG_BR5_PRELIM;
+#endif
+
+#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
+ memctl->or6 = CFG_OR6_PRELIM;
+ memctl->br6 = CFG_BR6_PRELIM;
+#endif
+
+#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
+ memctl->or7 = CFG_OR7_PRELIM;
+ memctl->br7 = CFG_BR7_PRELIM;
+#endif
+
+ /* enable the timebase bit in HID0 */
+ set_hid0(get_hid0() | 0x4000000);
+
+ /* enable SYNCBE | ABE bits in HID1 */
+ set_hid1(get_hid1() | 0x00000C00);
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 (440 port)
+ * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
+ *
+ * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port)
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc86xx.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <ppc_asm.tmpl>
+
+unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */
+unsigned long timestamp;
+
+
+static __inline__ unsigned long get_msr(void)
+{
+ unsigned long msr;
+
+ asm volatile ("mfmsr %0":"=r" (msr):);
+
+ return msr;
+}
+
+static __inline__ void set_msr(unsigned long msr)
+{
+ asm volatile ("mtmsr %0"::"r" (msr));
+}
+
+static __inline__ unsigned long get_dec(void)
+{
+ unsigned long val;
+
+ asm volatile ("mfdec %0":"=r" (val):);
+
+ return val;
+}
+
+static __inline__ void set_dec(unsigned long val)
+{
+ if (val)
+ asm volatile ("mtdec %0"::"r" (val));
+}
+
+/* interrupt is not supported yet */
+int interrupt_init_cpu(unsigned *decrementer_count)
+{
+ return 0;
+}
+
+int interrupt_init(void)
+{
+ int ret;
+
+ /* call cpu specific function from $(CPU)/interrupts.c */
+ ret = interrupt_init_cpu(&decrementer_count);
+
+ if (ret)
+ return ret;
+
+ decrementer_count = get_tbclk() / CFG_HZ;
+ debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n",
+ (get_tbclk() / 1000000),
+ decrementer_count);
+
+ set_dec(decrementer_count);
+
+ set_msr(get_msr() | MSR_EE);
+
+ debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n",
+ get_msr(),
+ get_dec());
+
+ return 0;
+}
+
+void enable_interrupts(void)
+{
+ set_msr(get_msr() | MSR_EE);
+}
+
+/* returns flag if MSR_EE was set before */
+int disable_interrupts(void)
+{
+ ulong msr = get_msr();
+
+ set_msr(msr & ~MSR_EE);
+ return (msr & MSR_EE) != 0;
+}
+
+void increment_timestamp(void)
+{
+ timestamp++;
+}
+
+/*
+ * timer_interrupt - gets called when the decrementer overflows,
+ * with interrupts disabled.
+ * Trivial implementation - no need to be really accurate.
+ */
+void timer_interrupt_cpu(struct pt_regs *regs)
+{
+ /* nothing to do here */
+}
+
+void timer_interrupt(struct pt_regs *regs)
+{
+ /* call cpu specific function from $(CPU)/interrupts.c */
+ timer_interrupt_cpu(regs);
+
+ timestamp++;
+
+ ppcDcbf(×tamp);
+
+ /* Restore Decrementer Count */
+ set_dec(decrementer_count);
+
+#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
+ if ((timestamp % (CFG_WATCHDOG_FREQ)) == 0)
+ WATCHDOG_RESET();
+#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_STATUS_LED
+ status_led_tick(timestamp);
+#endif /* CONFIG_STATUS_LED */
+
+#ifdef CONFIG_SHOW_ACTIVITY
+ board_show_activity(timestamp);
+#endif /* CONFIG_SHOW_ACTIVITY */
+
+}
+
+void reset_timer(void)
+{
+ timestamp = 0;
+}
+
+ulong get_timer(ulong base)
+{
+ return timestamp - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+/*
+ * Install and free a interrupt handler. Not implemented yet.
+ */
+
+void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+{
+}
+
+void irq_free_handler(int vec)
+{
+}
+
+/*
+ * irqinfo - print information about PCI devices,not implemented.
+ */
+int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ printf("\nInterrupt-unsupported:\n");
+
+ return 0;
+}
+
+/*
+ * Handle external interrupts
+ */
+void external_interrupt(struct pt_regs *regs)
+{
+ puts("external_interrupt (oops!)\n");
+}
--- /dev/null
+/*
+ * Copyright (C) Freescale Semiconductor,Inc.
+ * 2005, 2006. All rights reserved.
+ *
+ * Ed Swarthout (ed.swarthout@freescale.com)
+ * Jason Jin (Jason.jin@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCIE Configuration space access support for PCIE Bridge
+ */
+#include <common.h>
+#include <pci.h>
+
+#if defined(CONFIG_PCI)
+void
+pci_mpc86xx_init(struct pci_controller *hose)
+{
+ volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+ volatile ccsr_pex_t *pcie1 = &immap->im_pex1;
+ u16 temp16;
+ u32 temp32;
+
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+ uint pcie1_host = (host1_agent == 2) || (host1_agent == 3);
+ uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1);
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+
+ if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 ||
+ io_sel == 7 || io_sel == 0xf)
+ && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+ printf("PCI-EXPRESS 1: Configured as %s \n",
+ pcie1_agent ? "Agent" : "Host");
+ if (pcie1_agent)
+ return; /*Don't scan bus when configured as agent */
+ printf(" Scanning PCIE bus");
+ debug("0x%08x=0x%08x ",
+ &pcie1->pme_msg_det,
+ pcie1->pme_msg_det);
+ if (pcie1->pme_msg_det) {
+ pcie1->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pcie1->pme_msg_det);
+ }
+ debug("\n");
+ } else {
+ printf("PCI-EXPRESS 1 disabled!\n");
+ return;
+ }
+
+ /*
+ * Set first_bus=0 only skipped B0:D0:F0 which is
+ * a reserved device in M1575, but make it easy for
+ * most of the scan process.
+ */
+ hose->first_busno = 0x00;
+ hose->last_busno = 0xfe;
+
+ pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
+
+ pci_hose_read_config_word(hose,
+ PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16);
+ temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ pci_hose_write_config_word(hose,
+ PCI_BDF(0, 0, 0), PCI_COMMAND, temp16);
+
+ pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(hose,
+ PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80);
+
+ pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
+ &temp32);
+ temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
+ pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS,
+ temp32);
+
+ pcie1->powar1 = 0;
+ pcie1->powar2 = 0;
+ pcie1->piwar1 = 0;
+ pcie1->piwar1 = 0;
+
+ pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+ pcie1->powar1 = 0x8004401c; /* 512M MEM space */
+ pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
+ pcie1->potear1 = 0x00000000;
+
+ pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
+ pcie1->powar2 = 0x80088017; /* 16M IO space */
+ pcie1->potar2 = 0x00000000;
+ pcie1->potear2 = 0x00000000;
+
+ pcie1->pitar1 = 0x00000000;
+ pcie1->piwbar1 = 0x00000000;
+ /* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */
+ pcie1->piwar1 = 0xa0f5501e;
+
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+ debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno);
+ debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno);
+
+ printf("....PCIE1 scan & enumeration done\n");
+}
+#endif /* CONFIG_PCI */
--- /dev/null
+/*
+ * Support for indirect PCI bridges.
+ *
+ * Copyright (c) Freescale Semiconductor, Inc.
+ * 2006. All rights reserved.
+ *
+ * Jason Jin <Jason.jin@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * partly derived from
+ * arch/powerpc/platforms/86xx/mpc86xx_pcie.c
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_PCI
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#define PCI_CFG_OUT out_be32
+#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
+
+static int
+indirect_read_config_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ int len,
+ u32 *val)
+{
+ int bus = PCI_BUS(dev);
+
+ volatile unsigned char *cfg_data;
+ u32 temp;
+
+ PEX_FIX;
+ if (bus == 0xff) {
+ PCI_CFG_OUT(hose->cfg_addr,
+ dev | (offset & 0xfc) | 0x80000001);
+ } else {
+ PCI_CFG_OUT(hose->cfg_addr,
+ dev | (offset & 0xfc) | 0x80000000);
+ }
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+ cfg_data = hose->cfg_data;
+ PEX_FIX;
+ temp = in_le32((u32 *) cfg_data);
+ switch (len) {
+ case 1:
+ *val = (temp >> (((offset & 3)) * 8)) & 0xff;
+ break;
+ case 2:
+ *val = (temp >> (((offset & 3)) * 8)) & 0xffff;
+ break;
+ default:
+ *val = temp;
+ break;
+ }
+
+ return 0;
+}
+
+static int
+indirect_write_config_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ int len,
+ u32 val)
+{
+ int bus = PCI_BUS(dev);
+ volatile unsigned char *cfg_data;
+ u32 temp;
+
+ PEX_FIX;
+ if (bus == 0xff) {
+ PCI_CFG_OUT(hose->cfg_addr,
+ dev | (offset & 0xfc) | 0x80000001);
+ } else {
+ PCI_CFG_OUT(hose->cfg_addr,
+ dev | (offset & 0xfc) | 0x80000000);
+ }
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
+ cfg_data = hose->cfg_data;
+ switch (len) {
+ case 1:
+ PEX_FIX;
+ temp = in_le32((u32 *) cfg_data);
+ temp = (temp & ~(0xff << ((offset & 3) * 8))) |
+ (val << ((offset & 3) * 8));
+ PEX_FIX;
+ out_le32((u32 *) cfg_data, temp);
+ break;
+ case 2:
+ PEX_FIX;
+ temp = in_le32((u32 *) cfg_data);
+ temp = (temp & ~(0xffff << ((offset & 3) * 8)));
+ temp |= (val << ((offset & 3) * 8));
+ PEX_FIX;
+ out_le32((u32 *) cfg_data, temp);
+ break;
+ default:
+ PEX_FIX;
+ out_le32((u32 *) cfg_data, val);
+ break;
+ }
+ PEX_FIX;
+ return 0;
+}
+
+static int
+indirect_read_config_byte_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ u8 *val)
+{
+ u32 val32;
+ indirect_read_config_pcie(hose, dev, offset, 1, &val32);
+ *val = (u8) val32;
+ return 0;
+}
+
+static int
+indirect_read_config_word_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ u16 *val)
+{
+ u32 val32;
+ indirect_read_config_pcie(hose, dev, offset, 2, &val32);
+ *val = (u16) val32;
+ return 0;
+}
+
+static int
+indirect_read_config_dword_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ u32 *val)
+{
+ return indirect_read_config_pcie(hose, dev, offset, 4, val);
+}
+
+static int
+indirect_write_config_byte_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ u8 val)
+{
+ return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val);
+}
+
+static int
+indirect_write_config_word_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ unsigned short val)
+{
+ return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val);
+}
+
+static int
+indirect_write_config_dword_pcie(struct pci_controller *hose,
+ pci_dev_t dev,
+ int offset,
+ u32 val)
+{
+ return indirect_write_config_pcie(hose, dev, offset, 4, val);
+}
+
+void
+pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
+{
+ pci_set_ops(hose,
+ indirect_read_config_byte_pcie,
+ indirect_read_config_word_pcie,
+ indirect_read_config_dword_pcie,
+ indirect_write_config_byte_pcie,
+ indirect_write_config_word_pcie,
+ indirect_write_config_dword_pcie);
+
+ hose->cfg_addr = (unsigned int *)cfg_addr;
+ hose->cfg_data = (unsigned char *)cfg_data;
+}
+
+#endif /* CONFIG_PCI */
--- /dev/null
+ .section .resetvec,"ax"
+ b _start
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <spd.h>
+#include <asm/mmu.h>
+
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void dma_init(void);
+extern uint dma_check(void);
+extern int dma_xfer(void *dest, uint count, void *src);
+#endif
+
+#ifdef CONFIG_SPD_EEPROM
+
+#ifndef CFG_READ_SPD
+#define CFG_READ_SPD i2c_read
+#endif
+
+/*
+ * Only one of the following three should be 1; others should be 0
+ * By default the cache line interleaving is selected if
+ * the CONFIG_DDR_INTERLEAVE flag is defined
+ */
+#define CFG_PAGE_INTERLEAVING 0
+#define CFG_BANK_INTERLEAVING 0
+#define CFG_SUPER_BANK_INTERLEAVING 0
+
+/*
+ * Convert picoseconds into clock cycles (rounding up if needed).
+ */
+
+int
+picos_to_clk(int picos)
+{
+ int clks;
+
+ clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
+ if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+ clks++;
+ }
+
+ return clks;
+}
+
+
+/*
+ * Calculate the Density of each Physical Rank.
+ * Returned size is in bytes.
+ *
+ * Study these table from Byte 31 of JEDEC SPD Spec.
+ *
+ * DDR I DDR II
+ * Bit Size Size
+ * --- ----- ------
+ * 7 high 512MB 512MB
+ * 6 256MB 256MB
+ * 5 128MB 128MB
+ * 4 64MB 16GB
+ * 3 32MB 8GB
+ * 2 16MB 4GB
+ * 1 2GB 2GB
+ * 0 low 1GB 1GB
+ *
+ * Reorder Table to be linear by stripping the bottom
+ * 2 or 5 bits off and shifting them up to the top.
+ */
+
+unsigned int
+compute_banksize(unsigned int mem_type, unsigned char row_dens)
+{
+ unsigned int bsize;
+
+ if (mem_type == SPD_MEMTYPE_DDR) {
+ /* Bottom 2 bits up to the top. */
+ bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
+ debug("DDR: DDR I rank density = 0x%08x\n", bsize);
+ } else {
+ /* Bottom 5 bits up to the top. */
+ bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
+ debug("DDR: DDR II rank density = 0x%08x\n", bsize);
+ }
+ return bsize;
+}
+
+
+/*
+ * Convert a two-nibble BCD value into a cycle time.
+ * While the spec calls for nano-seconds, picos are returned.
+ *
+ * This implements the tables for bytes 9, 23 and 25 for both
+ * DDR I and II. No allowance for distinguishing the invalid
+ * fields absent for DDR I yet present in DDR II is made.
+ * (That is, cycle times of .25, .33, .66 and .75 ns are
+ * allowed for both DDR II and I.)
+ */
+
+unsigned int
+convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
+{
+ /*
+ * Table look up the lower nibble, allow DDR I & II.
+ */
+ unsigned int tenths_ps[16] = {
+ 0,
+ 100,
+ 200,
+ 300,
+ 400,
+ 500,
+ 600,
+ 700,
+ 800,
+ 900,
+ 250,
+ 330,
+ 660,
+ 750,
+ 0, /* undefined */
+ 0 /* undefined */
+ };
+
+ unsigned int whole_ns = (spd_val & 0xF0) >> 4;
+ unsigned int tenth_ns = spd_val & 0x0F;
+ unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
+
+ return ps;
+}
+
+
+/*
+ * Determine Refresh Rate. Ignore self refresh bit on DDR I.
+ * Table from SPD Spec, Byte 12, converted to picoseconds and
+ * filled in with "default" normal values.
+ */
+unsigned int determine_refresh_rate(unsigned int spd_refresh)
+{
+ unsigned int refresh_time_ns[8] = {
+ 15625000, /* 0 Normal 1.00x */
+ 3900000, /* 1 Reduced .25x */
+ 7800000, /* 2 Extended .50x */
+ 31300000, /* 3 Extended 2.00x */
+ 62500000, /* 4 Extended 4.00x */
+ 125000000, /* 5 Extended 8.00x */
+ 15625000, /* 6 Normal 1.00x filler */
+ 15625000, /* 7 Normal 1.00x filler */
+ };
+
+ return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
+}
+
+
+long int
+spd_init(unsigned char i2c_address, unsigned int ddr_num,
+ unsigned int dimm_num, unsigned int start_addr)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ spd_eeprom_t spd;
+ unsigned int n_ranks;
+ unsigned int rank_density;
+ unsigned int odt_rd_cfg, odt_wr_cfg;
+ unsigned int odt_cfg, mode_odt_enable;
+ unsigned int refresh_clk;
+#ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
+ unsigned char clk_adjust;
+#endif
+ unsigned int dqs_cfg;
+ unsigned char twr_clk, twtr_clk, twr_auto_clk;
+ unsigned int tCKmin_ps, tCKmax_ps;
+ unsigned int max_data_rate;
+ unsigned int busfreq;
+ unsigned int memsize;
+ unsigned char caslat, caslat_ctrl;
+ unsigned int trfc, trfc_clk, trfc_low, trfc_high;
+ unsigned int trcd_clk;
+ unsigned int trtp_clk;
+ unsigned char cke_min_clk;
+ unsigned char add_lat;
+ unsigned char wr_lat;
+ unsigned char wr_data_delay;
+ unsigned char four_act;
+ unsigned char cpo;
+ unsigned char burst_len;
+ unsigned int mode_caslat;
+ unsigned char d_init;
+ unsigned int tCycle_ps, modfreq;
+
+ if (ddr_num == 1)
+ ddr = &immap->im_ddr1;
+ else
+ ddr = &immap->im_ddr2;
+
+ /*
+ * Read SPD information.
+ */
+ debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address);
+ memset((void *)&spd, 0, sizeof(spd));
+ CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd));
+
+ /*
+ * Check for supported memory module types.
+ */
+ if (spd.mem_type != SPD_MEMTYPE_DDR &&
+ spd.mem_type != SPD_MEMTYPE_DDR2) {
+ debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n"
+ " Fundamental memory type is 0x%0x\n",
+ dimm_num,
+ ddr_num,
+ spd.mem_type);
+ return 0;
+ }
+
+ debug("\nFound memory of type 0x%02lx ", spd.mem_type);
+ if (spd.mem_type == SPD_MEMTYPE_DDR)
+ debug("DDR I\n");
+ else
+ debug("DDR II\n");
+
+ /*
+ * These test gloss over DDR I and II differences in interpretation
+ * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
+ * are not supported on DDR I; and not encoded on DDR II.
+ *
+ * Also note that the 8548 controller can support:
+ * 12 <= nrow <= 16
+ * and
+ * 8 <= ncol <= 11 (still, for DDR)
+ * 6 <= ncol <= 9 (for FCRAM)
+ */
+ if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
+ printf("DDR: Unsupported number of Row Addr lines: %d.\n",
+ spd.nrow_addr);
+ return 0;
+ }
+ if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
+ printf("DDR: Unsupported number of Column Addr lines: %d.\n",
+ spd.ncol_addr);
+ return 0;
+ }
+
+ /*
+ * Determine the number of physical banks controlled by
+ * different Chip Select signals. This is not quite the
+ * same as the number of DIMM modules on the board. Feh.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ n_ranks = spd.nrows;
+ } else {
+ n_ranks = (spd.nrows & 0x7) + 1;
+ }
+
+ debug("DDR: number of ranks = %d\n", n_ranks);
+
+ if (n_ranks > 2) {
+ printf("DDR: Only 2 chip selects are supported: %d\n",
+ n_ranks);
+ return 0;
+ }
+
+ /*
+ * Adjust DDR II IO voltage biasing. It just makes it work.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ gur->ddrioovcr = (0
+ | 0x80000000 /* Enable */
+ | 0x10000000 /* VSEL to 1.8V */
+ );
+ }
+
+ /*
+ * Determine the size of each Rank in bytes.
+ */
+ rank_density = compute_banksize(spd.mem_type, spd.row_dens);
+
+ debug("Start address for this controller is 0x%08lx\n", start_addr);
+
+ /*
+ * ODT configuration recommendation from DDR Controller Chapter.
+ */
+ odt_rd_cfg = 0; /* Never assert ODT */
+ odt_wr_cfg = 0; /* Never assert ODT */
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
+ }
+
+#ifdef CONFIG_DDR_INTERLEAVE
+
+ if (dimm_num != 1) {
+ printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num);
+ return 0;
+ } else {
+ /*
+ * Since interleaved memory only uses CS0, the
+ * memory sticks have to be identical in size and quantity
+ * of ranks. That essentially gives double the size on
+ * one rank, i.e on CS0 for both controllers put together.
+ * Confirm this???
+ */
+ rank_density *= 2;
+
+ /*
+ * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
+ */
+ start_addr = 0;
+ ddr->cs0_bnds = (start_addr >> 8)
+ | (((start_addr + rank_density - 1) >> 24));
+ /*
+ * Default interleaving mode to cache-line interleaving.
+ */
+ ddr->cs0_config = ( 1 << 31
+#if (CFG_PAGE_INTERLEAVING == 1)
+ | (PAGE_INTERLEAVING)
+#elif (CFG_BANK_INTERLEAVING == 1)
+ | (BANK_INTERLEAVING)
+#elif (CFG_SUPER_BANK_INTERLEAVING == 1)
+ | (SUPER_BANK_INTERLEAVING)
+#else
+ | (CACHE_LINE_INTERLEAVING)
+#endif
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+
+ debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
+ debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
+
+ /*
+ * Adjustment for dual rank memory to get correct memory
+ * size (return value of this function).
+ */
+ if (n_ranks == 2) {
+ n_ranks = 1;
+ rank_density /= 2;
+ } else {
+ rank_density /= 2;
+ }
+ }
+#else /* CONFIG_DDR_INTERLEAVE */
+
+ if (dimm_num == 1) {
+ /*
+ * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
+ */
+ ddr->cs0_bnds = (start_addr >> 8)
+ | (((start_addr + rank_density - 1) >> 24));
+
+ ddr->cs0_config = ( 1 << 31
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+
+ debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
+ debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
+
+ if (n_ranks == 2) {
+ /*
+ * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
+ * second 256 Meg
+ */
+ ddr->cs1_bnds = (((start_addr + rank_density) >> 8)
+ | (( start_addr + 2*rank_density - 1)
+ >> 24));
+ ddr->cs1_config = ( 1<<31
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+ debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
+ debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
+ }
+
+ } else {
+ /*
+ * This is the 2nd DIMM slot for this controller
+ */
+ /*
+ * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
+ */
+ ddr->cs2_bnds = (start_addr >> 8)
+ | (((start_addr + rank_density - 1) >> 24));
+
+ ddr->cs2_config = ( 1 << 31
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+
+ debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds);
+ debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config);
+
+ if (n_ranks == 2) {
+ /*
+ * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
+ * second 256 Meg
+ */
+ ddr->cs3_bnds = (((start_addr + rank_density) >> 8)
+ | (( start_addr + 2*rank_density - 1)
+ >> 24));
+ ddr->cs3_config = ( 1<<31
+ | (odt_rd_cfg << 20)
+ | (odt_wr_cfg << 16)
+ | (spd.nrow_addr - 12) << 8
+ | (spd.ncol_addr - 8) );
+ debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds);
+ debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config);
+ }
+ }
+#endif /* CONFIG_DDR_INTERLEAVE */
+
+ /*
+ * Find the largest CAS by locating the highest 1 bit
+ * in the spd.cas_lat field. Translate it to a DDR
+ * controller field value:
+ *
+ * CAS Lat DDR I DDR II Ctrl
+ * Clocks SPD Bit SPD Bit Value
+ * ------- ------- ------- -----
+ * 1.0 0 0001
+ * 1.5 1 0010
+ * 2.0 2 2 0011
+ * 2.5 3 0100
+ * 3.0 4 3 0101
+ * 3.5 5 0110
+ * 4.0 4 0111
+ * 4.5 1000
+ * 5.0 5 1001
+ */
+ caslat = __ilog2(spd.cas_lat);
+ if ((spd.mem_type == SPD_MEMTYPE_DDR)
+ && (caslat > 5)) {
+ printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
+ return 0;
+
+ } else if (spd.mem_type == SPD_MEMTYPE_DDR2
+ && (caslat < 2 || caslat > 5)) {
+ printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
+ spd.cas_lat);
+ return 0;
+ }
+ debug("DDR: caslat SPD bit is %d\n", caslat);
+
+ /*
+ * Calculate the Maximum Data Rate based on the Minimum Cycle time.
+ * The SPD clk_cycle field (tCKmin) is measured in tenths of
+ * nanoseconds and represented as BCD.
+ */
+ tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
+ debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
+
+ /*
+ * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
+ */
+ max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
+ debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
+
+
+ /*
+ * Adjust the CAS Latency to allow for bus speeds that
+ * are slower than the DDR module.
+ */
+ busfreq = get_bus_freq(0) / 1000000; /* MHz */
+ tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle3);
+ modfreq = 2 * 1000 * 1000 / tCycle_ps;
+
+ if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) {
+ printf("DDR: platform frequency too low for correct DDR2 controller operation\n");
+ return 0;
+ } else if (busfreq < 90) {
+ printf("DDR: platform frequency too low for correct DDR1 operation\n");
+ return 0;
+ }
+
+ if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) {
+ caslat -= 2;
+ } else {
+ tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2);
+ modfreq = 2 * 1000 * 1000 / tCycle_ps;
+ if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1))))
+ caslat -= 1;
+ else if (busfreq > max_data_rate) {
+ printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
+ busfreq, max_data_rate);
+ return 0;
+ }
+ }
+
+ /*
+ * Empirically set ~MCAS-to-preamble override for DDR 2.
+ * Your milage will vary.
+ */
+ cpo = 0;
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ if (busfreq <= 333) {
+ cpo = 0x7;
+ } else if (busfreq <= 400) {
+ cpo = 0x9;
+ } else {
+ cpo = 0xa;
+ }
+ }
+
+ /*
+ * Convert caslat clocks to DDR controller value.
+ * Force caslat_ctrl to be DDR Controller field-sized.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ caslat_ctrl = (caslat + 1) & 0x07;
+ } else {
+ caslat_ctrl = (2 * caslat - 1) & 0x0f;
+ }
+
+ debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
+ caslat, caslat_ctrl);
+
+ /*
+ * Timing Config 0.
+ * Avoid writing for DDR I. The new PQ38 DDR controller
+ * dreams up non-zero default values to be backwards compatible.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+ unsigned char taxpd_clk = 8; /* By the book. */
+ unsigned char tmrd_clk = 2; /* By the book. */
+ unsigned char act_pd_exit = 2; /* Empirical? */
+ unsigned char pre_pd_exit = 6; /* Empirical? */
+
+ ddr->timing_cfg_0 = (0
+ | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
+ | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
+ | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
+ | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
+ );
+ debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
+
+ }
+
+
+ /*
+ * Some Timing Config 1 values now.
+ * Sneak Extended Refresh Recovery in here too.
+ */
+
+ /*
+ * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
+ * use conservative value.
+ * For DDR II, they are bytes 36 and 37, in quarter nanos.
+ */
+
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ twr_clk = 3; /* Clocks */
+ twtr_clk = 1; /* Clocks */
+ } else {
+ twr_clk = picos_to_clk(spd.twr * 250);
+ twtr_clk = picos_to_clk(spd.twtr * 250);
+ }
+
+ /*
+ * Calculate Trfc, in picos.
+ * DDR I: Byte 42 straight up in ns.
+ * DDR II: Byte 40 and 42 swizzled some, in ns.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ trfc = spd.trfc * 1000; /* up to ps */
+ } else {
+ unsigned int byte40_table_ps[8] = {
+ 0,
+ 250,
+ 330,
+ 500,
+ 660,
+ 750,
+ 0,
+ 0
+ };
+
+ trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
+ + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
+ }
+ trfc_clk = picos_to_clk(trfc);
+
+ /*
+ * Trcd, Byte 29, from quarter nanos to ps and clocks.
+ */
+ trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
+
+ /*
+ * Convert trfc_clk to DDR controller fields. DDR I should
+ * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
+ * 8548 controller has an extended REFREC field of three bits.
+ * The controller automatically adds 8 clocks to this value,
+ * so preadjust it down 8 first before splitting it up.
+ */
+ trfc_low = (trfc_clk - 8) & 0xf;
+ trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
+
+ /*
+ * Sneak in some Extended Refresh Recovery.
+ */
+ ddr->ext_refrec = (trfc_high << 16);
+ debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+
+ ddr->timing_cfg_1 =
+ (0
+ | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
+ | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
+ | (trcd_clk << 20) /* ACTTORW */
+ | (caslat_ctrl << 16) /* CASLAT */
+ | (trfc_low << 12) /* REFEC */
+ | ((twr_clk & 0x07) << 8) /* WRRREC */
+ | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
+ | ((twtr_clk & 0x07) << 0) /* WRTORD */
+ );
+
+ debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
+
+
+ /*
+ * Timing_Config_2
+ * Was: 0x00000800;
+ */
+
+ /*
+ * Additive Latency
+ * For DDR I, 0.
+ * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
+ * which comes from Trcd, and also note that:
+ * add_lat + caslat must be >= 4
+ */
+ add_lat = 0;
+ if (spd.mem_type == SPD_MEMTYPE_DDR2
+ && (odt_wr_cfg || odt_rd_cfg)
+ && (caslat < 4)) {
+ add_lat = 4 - caslat;
+ if (add_lat >= trcd_clk) {
+ add_lat = trcd_clk - 1;
+ }
+ }
+
+ /*
+ * Write Data Delay
+ * Historically 0x2 == 4/8 clock delay.
+ * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
+ */
+ wr_data_delay = 3;
+
+ /*
+ * Write Latency
+ * Read to Precharge
+ * Minimum CKE Pulse Width.
+ * Four Activate Window
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ /*
+ * This is a lie. It should really be 1, but if it is
+ * set to 1, bits overlap into the old controller's
+ * otherwise unused ACSM field. If we leave it 0, then
+ * the HW will magically treat it as 1 for DDR 1. Oh Yea.
+ */
+ wr_lat = 0;
+
+ trtp_clk = 2; /* By the book. */
+ cke_min_clk = 1; /* By the book. */
+ four_act = 1; /* By the book. */
+
+ } else {
+ wr_lat = caslat - 1;
+
+ /* Convert SPD value from quarter nanos to picos. */
+ trtp_clk = picos_to_clk(spd.trtp * 250);
+
+ cke_min_clk = 3; /* By the book. */
+ four_act = picos_to_clk(37500); /* By the book. 1k pages? */
+ }
+
+ ddr->timing_cfg_2 = (0
+ | ((add_lat & 0x7) << 28) /* ADD_LAT */
+ | ((cpo & 0x1f) << 23) /* CPO */
+ | ((wr_lat & 0x7) << 19) /* WR_LAT */
+ | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
+ | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
+ | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
+ | ((four_act & 0x1f) << 0) /* FOUR_ACT */
+ );
+
+ debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
+
+
+ /*
+ * Determine the Mode Register Set.
+ *
+ * This is nominally part specific, but it appears to be
+ * consistent for all DDR I devices, and for all DDR II devices.
+ *
+ * caslat must be programmed
+ * burst length is always 4
+ * burst type is sequential
+ *
+ * For DDR I:
+ * operating mode is "normal"
+ *
+ * For DDR II:
+ * other stuff
+ */
+
+ mode_caslat = 0;
+
+ /*
+ * Table lookup from DDR I or II Device Operation Specs.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ if (1 <= caslat && caslat <= 4) {
+ unsigned char mode_caslat_table[4] = {
+ 0x5, /* 1.5 clocks */
+ 0x2, /* 2.0 clocks */
+ 0x6, /* 2.5 clocks */
+ 0x3 /* 3.0 clocks */
+ };
+ mode_caslat = mode_caslat_table[caslat - 1];
+ } else {
+ puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
+ "2.5 and 3.0 clocks are supported.\n");
+ return 0;
+ }
+
+ } else {
+ if (2 <= caslat && caslat <= 5) {
+ mode_caslat = caslat;
+ } else {
+ puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
+ "4.0 and 5.0 clocks are supported.\n");
+ return 0;
+ }
+ }
+
+ /*
+ * Encoded Burst Length of 4.
+ */
+ burst_len = 2; /* Fiat. */
+
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ twr_auto_clk = 0; /* Historical */
+ } else {
+ /*
+ * Determine tCK max in picos. Grab tWR and convert to picos.
+ * Auto-precharge write recovery is:
+ * WR = roundup(tWR_ns/tCKmax_ns).
+ *
+ * Ponder: Is twr_auto_clk different than twr_clk?
+ */
+ tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
+ twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
+ }
+
+ /*
+ * Mode Reg in bits 16 ~ 31,
+ * Extended Mode Reg 1 in bits 0 ~ 15.
+ */
+ mode_odt_enable = 0x0; /* Default disabled */
+ if (odt_wr_cfg || odt_rd_cfg) {
+ /*
+ * Bits 6 and 2 in Extended MRS(1)
+ * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
+ * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
+ */
+ mode_odt_enable = 0x40; /* 150 Ohm */
+ }
+
+ ddr->sdram_mode_1 =
+ (0
+ | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
+ | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
+ | (twr_auto_clk << 9) /* Write Recovery Autopre */
+ | (mode_caslat << 4) /* caslat */
+ | (burst_len << 0) /* Burst length */
+ );
+
+ debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1);
+
+ /*
+ * Clear EMRS2 and EMRS3.
+ */
+ ddr->sdram_mode_2 = 0;
+ debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
+
+ /*
+ * Determine Refresh Rate.
+ */
+ refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
+
+ /*
+ * Set BSTOPRE to 0x100 for page mode
+ * If auto-charge is used, set BSTOPRE = 0
+ */
+ ddr->sdram_interval =
+ (0
+ | (refresh_clk & 0x3fff) << 16
+ | 0x100
+ );
+ debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
+
+
+ /*
+ * Is this an ECC DDR chip?
+ * But don't mess with it if the DDR controller will init mem.
+ */
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ if (spd.config == 0x02) {
+ ddr->err_disable = 0x0000000d;
+ ddr->err_sbe = 0x00ff0000;
+ }
+ debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
+ debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
+#endif
+
+ asm volatile("sync;isync");
+ udelay(500);
+
+ /*
+ * SDRAM Cfg 2
+ */
+
+ /*
+ * When ODT is enabled, Chap 9 suggests asserting ODT to
+ * internal IOs only during reads.
+ */
+ odt_cfg = 0;
+ if (odt_rd_cfg | odt_wr_cfg) {
+ odt_cfg = 0x2; /* ODT to IOs during reads */
+ }
+
+ /*
+ * Try to use differential DQS with DDR II.
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR) {
+ dqs_cfg = 0; /* No Differential DQS for DDR I */
+ } else {
+ dqs_cfg = 0x1; /* Differential DQS for DDR II */
+ }
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Use the DDR controller to auto initialize memory.
+ */
+ d_init = 1;
+ ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
+ debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
+#else
+ /*
+ * Memory will be initialized via DMA, or not at all.
+ */
+ d_init = 0;
+#endif
+
+ ddr->sdram_cfg_2 = (0
+ | (dqs_cfg << 26) /* Differential DQS */
+ | (odt_cfg << 21) /* ODT */
+ | (d_init << 4) /* D_INIT auto init DDR */
+ );
+
+ debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
+
+
+#ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
+ /*
+ * Setup the clock control.
+ * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
+ * SDRAM_CLK_CNTL[5-7] = Clock Adjust
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ if (spd.mem_type == SPD_MEMTYPE_DDR)
+ clk_adjust = 0x6;
+ else
+ clk_adjust = 0x7;
+
+ ddr->sdram_clk_cntl = (0
+ | 0x80000000
+ | (clk_adjust << 23)
+ );
+ debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
+#endif
+
+ /*
+ * Figure out memory size in Megabytes.
+ */
+ debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density);
+ memsize = n_ranks * rank_density / 0x100000;
+ return memsize;
+}
+
+
+unsigned int enable_ddr(unsigned int ddr_num)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ spd_eeprom_t spd1,spd2;
+ volatile ccsr_ddr_t *ddr;
+ unsigned sdram_cfg_1;
+ unsigned char sdram_type, mem_type, config, mod_attr;
+ unsigned char d_init;
+ unsigned int no_dimm1=0, no_dimm2=0;
+
+ /* Set up pointer to enable the current ddr controller */
+ if (ddr_num == 1)
+ ddr = &immap->im_ddr1;
+ else
+ ddr = &immap->im_ddr2;
+
+ /*
+ * Read both dimm slots and decide whether
+ * or not to enable this controller.
+ */
+ memset((void *)&spd1,0,sizeof(spd1));
+ memset((void *)&spd2,0,sizeof(spd2));
+
+ if (ddr_num == 1) {
+ CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
+ 0, 1, (uchar *) &spd1, sizeof(spd1));
+ CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
+ 0, 1, (uchar *) &spd2, sizeof(spd2));
+ } else {
+ CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
+ 0, 1, (uchar *) &spd1, sizeof(spd1));
+ CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
+ 0, 1, (uchar *) &spd2, sizeof(spd2));
+ }
+
+ /*
+ * Check for supported memory module types.
+ */
+ if (spd1.mem_type != SPD_MEMTYPE_DDR
+ && spd1.mem_type != SPD_MEMTYPE_DDR2) {
+ no_dimm1 = 1;
+ } else {
+ debug("\nFound memory of type 0x%02lx ",spd1.mem_type );
+ if (spd1.mem_type == SPD_MEMTYPE_DDR)
+ debug("DDR I\n");
+ else
+ debug("DDR II\n");
+ }
+
+ if (spd2.mem_type != SPD_MEMTYPE_DDR &&
+ spd2.mem_type != SPD_MEMTYPE_DDR2) {
+ no_dimm2 = 1;
+ } else {
+ debug("\nFound memory of type 0x%02lx ",spd2.mem_type );
+ if (spd2.mem_type == SPD_MEMTYPE_DDR)
+ debug("DDR I\n");
+ else
+ debug("DDR II\n");
+ }
+
+#ifdef CONFIG_DDR_INTERLEAVE
+ if (no_dimm1) {
+ printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n");
+ return 0;
+ }
+#endif
+
+ /*
+ * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn
+ */
+ if (no_dimm1 && no_dimm2) {
+ printf("No memory modules found for DDR controller %d!!\n", ddr_num);
+ return 0;
+ } else {
+ mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type;
+
+ /*
+ * Figure out the settings for the sdram_cfg register.
+ * Build up the entire register in 'sdram_cfg' before
+ * writing since the write into the register will
+ * actually enable the memory controller; all settings
+ * must be done before enabling.
+ *
+ * sdram_cfg[0] = 1 (ddr sdram logic enable)
+ * sdram_cfg[1] = 1 (self-refresh-enable)
+ * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
+ * 010 DDR 1 SDRAM
+ * 011 DDR 2 SDRAM
+ */
+ sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
+ sdram_cfg_1 = (0
+ | (1 << 31) /* Enable */
+ | (1 << 30) /* Self refresh */
+ | (sdram_type << 24) /* SDRAM type */
+ );
+
+ /*
+ * sdram_cfg[3] = RD_EN - registered DIMM enable
+ * A value of 0x26 indicates micron registered
+ * DIMMS (micron.com)
+ */
+ mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr;
+ if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) {
+ sdram_cfg_1 |= 0x10000000; /* RD_EN */
+ }
+
+#if defined(CONFIG_DDR_ECC)
+
+ config = no_dimm2 ? spd1.config : spd2.config;
+
+ /*
+ * If the user wanted ECC (enabled via sdram_cfg[2])
+ */
+ if (config == 0x02) {
+ ddr->err_disable = 0x00000000;
+ asm volatile("sync;isync;");
+ ddr->err_sbe = 0x00ff0000;
+ ddr->err_int_en = 0x0000000d;
+ sdram_cfg_1 |= 0x20000000; /* ECC_EN */
+ }
+#endif
+
+ /*
+ * Set 1T or 2T timing based on 1 or 2 modules
+ */
+ {
+ if (!(no_dimm1 || no_dimm2)) {
+ /*
+ * 2T timing,because both DIMMS are present.
+ * Enable 2T timing by setting sdram_cfg[16].
+ */
+ sdram_cfg_1 |= 0x8000; /* 2T_EN */
+ }
+ }
+
+ /*
+ * 200 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ */
+ udelay(200);
+
+ /*
+ * Go!
+ */
+ ddr->sdram_cfg_1 = sdram_cfg_1;
+
+ asm volatile("sync;isync");
+ udelay(500);
+
+ debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1);
+
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR: memory initializing\n");
+
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+ udelay(1000);
+ }
+ debug("DDR: memory initialized\n\n");
+#endif
+
+ debug("Enabled DDR Controller %d\n", ddr_num);
+ return 1;
+ }
+}
+
+
+long int
+spd_sdram(void)
+{
+ int memsize_ddr1_dimm1 = 0;
+ int memsize_ddr1_dimm2 = 0;
+ int memsize_ddr2_dimm1 = 0;
+ int memsize_ddr2_dimm2 = 0;
+ int memsize_total = 0;
+ int memsize_ddr1 = 0;
+ int memsize_ddr2 = 0;
+ unsigned int ddr1_enabled = 0;
+ unsigned int ddr2_enabled = 0;
+ unsigned int law_size_ddr1;
+ unsigned int law_size_ddr2;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+
+#ifdef CONFIG_DDR_INTERLEAVE
+ unsigned int law_size_interleaved;
+ volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
+ volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
+
+ memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
+ 1, 1,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr1_dimm1;
+
+ memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
+ 2, 1,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr2_dimm1;
+
+ if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) {
+ if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1)
+ memsize_total -= memsize_ddr1_dimm1;
+ else
+ memsize_total -= memsize_ddr2_dimm1;
+ debug("Total memory available for interleaving 0x%08lx\n",
+ memsize_total * 1024 * 1024);
+ debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n");
+ ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
+ ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
+ debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds);
+ debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds);
+ }
+
+ ddr1_enabled = enable_ddr(1);
+ ddr2_enabled = enable_ddr(2);
+
+ /*
+ * Both controllers need to be enabled for interleaving.
+ */
+ if (ddr1_enabled && ddr2_enabled) {
+ law_size_interleaved = 19 + __ilog2(memsize_total);
+
+ /*
+ * Set up LAWBAR for DDR 1 space.
+ */
+ mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
+ mcm->lawar1 = (LAWAR_EN
+ | LAWAR_TRGT_IF_DDR_INTERLEAVED
+ | (LAWAR_SIZE & law_size_interleaved));
+ debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
+ debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
+ debug("Interleaved memory size is 0x%08lx\n", memsize_total);
+
+#ifdef CONFIG_DDR_INTERLEAVE
+#if (CFG_PAGE_INTERLEAVING == 1)
+ printf("Page ");
+#elif (CFG_BANK_INTERLEAVING == 1)
+ printf("Bank ");
+#elif (CFG_SUPER_BANK_INTERLEAVING == 1)
+ printf("Super-bank ");
+#else
+ printf("Cache-line ");
+#endif
+#endif
+ printf("Interleaved");
+ return memsize_total * 1024 * 1024;
+ } else {
+ printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n");
+ return 0;
+ }
+
+#else
+ /*
+ * Call spd_sdram() routine to init ddr1 - pass I2c address,
+ * controller number, dimm number, and starting address.
+ */
+ memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
+ 1, 1,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr1_dimm1;
+
+ memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
+ 1, 2,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr1_dimm2;
+
+ /*
+ * Enable the DDR controller - pass ddr controller number.
+ */
+ ddr1_enabled = enable_ddr(1);
+
+ /* Keep track of memory to be addressed by DDR1 */
+ memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2;
+
+ /*
+ * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
+ */
+ if (ddr1_enabled) {
+ law_size_ddr1 = 19 + __ilog2(memsize_ddr1);
+
+ /*
+ * Set up LAWBAR for DDR 1 space.
+ */
+ mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
+ mcm->lawar1 = (LAWAR_EN
+ | LAWAR_TRGT_IF_DDR1
+ | (LAWAR_SIZE & law_size_ddr1));
+ debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
+ debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
+ }
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
+ 2, 1,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr2_dimm1;
+
+ memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4,
+ 2, 2,
+ (unsigned int)memsize_total * 1024*1024);
+ memsize_total += memsize_ddr2_dimm2;
+
+ ddr2_enabled = enable_ddr(2);
+
+ /* Keep track of memory to be addressed by DDR2 */
+ memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2;
+
+ if (ddr2_enabled) {
+ law_size_ddr2 = 19 + __ilog2(memsize_ddr2);
+
+ /*
+ * Set up LAWBAR for DDR 2 space.
+ */
+ if (ddr1_enabled)
+ mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
+ & 0xfffff);
+ else
+ mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
+
+ mcm->lawar8 = (LAWAR_EN
+ | LAWAR_TRGT_IF_DDR2
+ | (LAWAR_SIZE & law_size_ddr2));
+ debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
+ debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
+ }
+#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
+
+ debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
+ memsize_ddr1, memsize_ddr2);
+
+ /*
+ * If neither DDR controller is enabled return 0.
+ */
+ if (!ddr1_enabled && !ddr2_enabled)
+ return 0;
+
+ printf("Non-interleaved");
+ return memsize_total * 1024 * 1024;
+
+#endif /* CONFIG_DDR_INTERLEAVE */
+}
+
+
+#endif /* CONFIG_SPD_EEPROM */
+
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+
+/*
+ * Initialize all of memory for ECC, then enable errors.
+ */
+
+void
+ddr_enable_ecc(unsigned int dram_size)
+{
+ uint *p = 0;
+ uint i = 0;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr1= &immap->im_ddr1;
+
+ dma_init();
+
+ for (*p = 0; p < (uint *)(8 * 1024); p++) {
+ if (((unsigned int)p & 0x1f) == 0) {
+ ppcDcbz((unsigned long) p);
+ }
+ *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
+ if (((unsigned int)p & 0x1c) == 0x1c) {
+ ppcDcbf((unsigned long) p);
+ }
+ }
+
+ dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
+ dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
+ dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
+ dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
+ dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
+ dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
+ dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
+ dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
+ dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
+ dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
+
+ for (i = 1; i < dram_size / 0x800000; i++) {
+ dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
+ }
+
+ /*
+ * Enable errors for ECC.
+ */
+ debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
+ ddr1->err_disable = 0x00000000;
+ asm volatile("sync;isync");
+ debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
+}
+
+#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc86xx.h>
+#include <asm/processor.h>
+
+
+void get_sys_info(sys_info_t *sysInfo)
+{
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint plat_ratio, e600_ratio;
+
+ plat_ratio = (gur->porpllsr) & 0x0000003e;
+ plat_ratio >>= 1;
+
+ switch (plat_ratio) {
+ case 0x0:
+ sysInfo->freqSystemBus = 16 * CONFIG_SYS_CLK_FREQ;
+ break;
+ case 0x02:
+ case 0x03:
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ case 0x08:
+ case 0x09:
+ case 0x0a:
+ case 0x0c:
+ case 0x10:
+ sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+ break;
+ default:
+ sysInfo->freqSystemBus = 0;
+ break;
+ }
+
+ e600_ratio = (gur->porpllsr) & 0x003f0000;
+ e600_ratio >>= 16;
+
+ switch (e600_ratio) {
+ case 0x10:
+ sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus;
+ break;
+ case 0x19:
+ sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus / 2;
+ break;
+ case 0x20:
+ sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus;
+ break;
+ case 0x39:
+ sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus / 2;
+ break;
+ case 0x28:
+ sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus;
+ break;
+ case 0x1d:
+ sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus / 2;
+ break;
+ default:
+ sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
+ break;
+ }
+}
+
+
+/*
+ * Measure CPU clock speed (core clock GCLK1, GCLK2)
+ * (Approx. GCLK frequency in Hz)
+ */
+
+int get_clocks(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ sys_info_t sys_info;
+
+ get_sys_info(&sys_info);
+ gd->cpu_clk = sys_info.freqProcessor;
+ gd->bus_clk = sys_info.freqSystemBus;
+
+ if (gd->cpu_clk != 0)
+ return 0;
+ else
+ return 1;
+}
+
+
+/*
+ * get_bus_freq
+ * Return system bus freq in Hz
+ */
+
+ulong get_bus_freq(ulong dummy)
+{
+ ulong val;
+ sys_info_t sys_info;
+
+ get_sys_info(&sys_info);
+ val = sys_info.freqSystemBus;
+
+ return val;
+}
--- /dev/null
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
+ *
+ *
+ * The processor starts at 0xfff00100 and the code is executed
+ * from flash. The code is organized to be at an other address
+ * in memory, but as long we don't jump around before relocating.
+ * board_init lies at a quite high address and when the cpu has
+ * jumped there, everything is ok.
+ */
+#include <config.h>
+#include <mpc86xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+/* We don't want the MMU yet.
+*/
+#undef MSR_KERNEL
+/* Machine Check and Recoverable Interr. */
+#define MSR_KERNEL ( MSR_ME | MSR_RI )
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r14 to access the GOT
+ */
+ START_GOT
+ GOT_ENTRY(_GOT2_TABLE_)
+ GOT_ENTRY(_FIXUP_TABLE_)
+
+ GOT_ENTRY(_start)
+ GOT_ENTRY(_start_of_vectors)
+ GOT_ENTRY(_end_of_vectors)
+ GOT_ENTRY(transfer_to_handler)
+
+ GOT_ENTRY(__init_end)
+ GOT_ENTRY(_end)
+ GOT_ENTRY(__bss_start)
+ END_GOT
+
+/*
+ * r3 - 1st arg to board_init(): IMMP pointer
+ * r4 - 2nd arg to board_init(): boot flag
+ */
+ .text
+ .long 0x27051956 /* U-Boot Magic Number */
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
+
+ . = EXC_OFF_SYS_RESET
+ .globl _start
+_start:
+ li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
+ b boot_cold
+ sync
+
+ . = EXC_OFF_SYS_RESET + 0x10
+
+ .globl _start_warm
+_start_warm:
+ li r21, BOOTFLAG_WARM /* Software reboot */
+ b boot_warm
+ sync
+
+ /* the boot code is located below the exception table */
+
+ .globl _start_of_vectors
+_start_of_vectors:
+
+/* Machine check */
+ STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception. */
+ STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. */
+ STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+ STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
+
+/* Alignment exception. */
+ . = 0x600
+Alignment:
+ EXCEPTION_PROLOG
+ mfspr r4,DAR
+ stw r4,_DAR(r21)
+ mfspr r5,DSISR
+ stw r5,_DSISR(r21)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ li r20,MSR_KERNEL
+ rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
+ lwz r6,GOT(transfer_to_handler)
+ mtlr r6
+ blrl
+.L_Alignment:
+ .long AlignmentException - _start + EXC_OFF_SYS_RESET
+ .long int_return - _start + EXC_OFF_SYS_RESET
+
+/* Program check exception */
+ . = 0x700
+ProgramCheck:
+ EXCEPTION_PROLOG
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ li r20,MSR_KERNEL
+ rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
+ lwz r6,GOT(transfer_to_handler)
+ mtlr r6
+ blrl
+.L_ProgramCheck:
+ .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
+ .long int_return - _start + EXC_OFF_SYS_RESET
+
+ STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+
+ /* I guess we could implement decrementer, and may have
+ * to someday for timekeeping.
+ */
+ STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
+ STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
+ STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
+ STD_EXCEPTION(0xc00, SystemCall, UnknownException)
+ STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+ STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
+ STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+ STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
+ STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
+ STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
+ STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
+ STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
+ STD_EXCEPTION(0x1500, Reserved5, UnknownException)
+ STD_EXCEPTION(0x1600, Reserved6, UnknownException)
+ STD_EXCEPTION(0x1700, Reserved7, UnknownException)
+ STD_EXCEPTION(0x1800, Reserved8, UnknownException)
+ STD_EXCEPTION(0x1900, Reserved9, UnknownException)
+ STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
+ STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
+ STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
+
+ .globl _end_of_vectors
+_end_of_vectors:
+
+ . = 0x2000
+
+boot_cold:
+boot_warm:
+
+ /* if this is a multi-core system we need to check which cpu
+ * this is, if it is not cpu 0 send the cpu to the linux reset
+ * vector */
+#if (CONFIG_NUM_CPUS > 1)
+ mfspr r0, MSSCR0
+ andi. r0, r0, 0x0020
+ rlwinm r0,r0,27,31,31
+ mtspr PIR, r0
+ beq 1f
+
+ bl secondary_cpu_setup
+#endif
+
+ /* disable everything */
+1: li r0, 0
+ mtspr HID0, r0
+ sync
+ mtmsr 0
+ bl invalidate_bats
+ sync
+
+#ifdef CFG_L2
+ /* init the L2 cache */
+ addis r3, r0, L2_INIT@h
+ ori r3, r3, L2_INIT@l
+ mtspr l2cr, r3
+ /* invalidate the L2 cache */
+ bl l2cache_invalidate
+ sync
+#endif
+
+ /*
+ * Calculate absolute address in FLASH and jump there
+ *------------------------------------------------------*/
+ lis r3, CFG_MONITOR_BASE@h
+ ori r3, r3, CFG_MONITOR_BASE@l
+ addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
+ mtlr r3
+ blr
+
+in_flash:
+ /* let the C-code set up the rest */
+ /* */
+ /* Be careful to keep code relocatable ! */
+ /*------------------------------------------------------*/
+ /* perform low-level init */
+
+ /* enable extended addressing */
+ bl enable_ext_addr
+
+ /* setup the bats */
+ bl setup_bats
+ sync
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /* setup ccsrbar */
+ bl setup_ccsrbar
+#endif
+
+ /* Fix for SMP linux - Changing arbitration to round-robin */
+ lis r3, CFG_CCSRBAR@h
+ ori r3, r3, 0x1000
+ xor r4, r4, r4
+ li r4, 0x1000
+ stw r4, 0(r3)
+
+ /* setup the law entries */
+ bl law_entry
+ sync
+
+ /* Don't use this feature due to bug in 8641D PD4 */
+ /* Disable ERD_DIS */
+ lis r3, CFG_CCSRBAR@h
+ ori r3, r3, 0x1008
+ lwz r4, 0(r3)
+ oris r4, r4, 0x4000
+ stw r4, 0(r3)
+ sync
+
+#if (EMULATOR_RUN == 1)
+ /* On the emulator we want to adjust these ASAP */
+ /* otherwise things are sloooow */
+ /* Setup OR0 (LALE FIX)*/
+ lis r3, CFG_CCSRBAR@h
+ ori r3, r3, 0x5004
+ li r4, 0x0FF3
+ stw r4, 0(r3)
+ sync
+
+ /* Setup LCRR */
+ lis r3, CFG_CCSRBAR@h
+ ori r3, r3, 0x50D4
+ lis r4, 0x8000
+ ori r4, r4, 0x0002
+ stw r4, 0(r3)
+ sync
+#endif
+#if 1
+ /* make sure timer enabled in guts register too */
+ lis r3, CFG_CCSRBAR@h
+ oris r3,r3, 0xE
+ ori r3,r3,0x0070
+ lwz r4, 0(r3)
+ lis r5,0xFFFC
+ ori r5,r5,0x5FFF
+ and r4,r4,r5
+ stw r4,0(r3)
+#endif
+ /*
+ * Cache must be enabled here for stack-in-cache trick.
+ * This means we need to enable the BATS.
+ * Cache should be turned on after BATs, since by default
+ * everything is write-through.
+ */
+
+ /* enable address translation */
+ bl enable_addr_trans
+ sync
+
+ /* enable and invalidate the data cache */
+/* bl l1dcache_enable */
+ bl dcache_enable
+ sync
+
+#if 1
+ bl icache_enable
+#endif
+
+#ifdef CFG_INIT_RAM_LOCK
+ bl lock_ram_in_cache
+ sync
+#endif
+
+ /* set up the stack pointer in our newly created
+ * cache-ram (r1) */
+ lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
+ ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
+
+ li r0, 0 /* Make room for stack frame header and */
+ stwu r0, -4(r1) /* clear final stack frame so that */
+ stwu r0, -4(r1) /* stack backtraces terminate cleanly */
+
+ GET_GOT /* initialize GOT access */
+
+ /* run low-level CPU init code (from Flash) */
+ bl cpu_init_f
+ sync
+
+#ifdef RUN_DIAG
+
+ /* Sri: Code to run the diagnostic automatically */
+
+ /* Load PX_AUX register address in r4 */
+ lis r4, 0xf810
+ ori r4, r4, 0x6
+ /* Load contents of PX_AUX in r3 bits 24 to 31*/
+ lbz r3, 0(r4)
+
+ /* Mask and obtain the bit in r3 */
+ rlwinm. r3, r3, 0, 24, 24
+ /* If not zero, jump and continue with u-boot */
+ bne diag_done
+
+ /* Load back contents of PX_AUX in r3 bits 24 to 31 */
+ lbz r3, 0(r4)
+ /* Set the MSB of the register value */
+ ori r3, r3, 0x80
+ /* Write value in r3 back to PX_AUX */
+ stb r3, 0(r4)
+
+ /* Get the address to jump to in r3*/
+ lis r3, CFG_DIAG_ADDR@h
+ ori r3, r3, CFG_DIAG_ADDR@l
+
+ /* Load the LR with the branch address */
+ mtlr r3
+
+ /* Branch to diagnostic */
+ blr
+
+diag_done:
+#endif
+
+/* bl l2cache_enable */
+ mr r3, r21
+
+ /* r3: BOOTFLAG */
+ /* run 1st part of board init code (from Flash) */
+ bl board_init_f
+ sync
+
+ /* NOTREACHED */
+
+ .globl invalidate_bats
+invalidate_bats:
+
+ /* invalidate BATs */
+ mtspr IBAT0U, r0
+ mtspr IBAT1U, r0
+ mtspr IBAT2U, r0
+ mtspr IBAT3U, r0
+ mtspr IBAT4U, r0
+ mtspr IBAT5U, r0
+ mtspr IBAT6U, r0
+ mtspr IBAT7U, r0
+
+ isync
+ mtspr DBAT0U, r0
+ mtspr DBAT1U, r0
+ mtspr DBAT2U, r0
+ mtspr DBAT3U, r0
+ mtspr DBAT4U, r0
+ mtspr DBAT5U, r0
+ mtspr DBAT6U, r0
+ mtspr DBAT7U, r0
+
+ isync
+ sync
+ blr
+
+
+ /* setup_bats - set them up to some initial state */
+ .globl setup_bats
+setup_bats:
+
+ addis r0, r0, 0x0000
+
+ /* IBAT 0 */
+ addis r4, r0, CFG_IBAT0L@h
+ ori r4, r4, CFG_IBAT0L@l
+ addis r3, r0, CFG_IBAT0U@h
+ ori r3, r3, CFG_IBAT0U@l
+ mtspr IBAT0L, r4
+ mtspr IBAT0U, r3
+ isync
+
+ /* DBAT 0 */
+ addis r4, r0, CFG_DBAT0L@h
+ ori r4, r4, CFG_DBAT0L@l
+ addis r3, r0, CFG_DBAT0U@h
+ ori r3, r3, CFG_DBAT0U@l
+ mtspr DBAT0L, r4
+ mtspr DBAT0U, r3
+ isync
+
+ /* IBAT 1 */
+ addis r4, r0, CFG_IBAT1L@h
+ ori r4, r4, CFG_IBAT1L@l
+ addis r3, r0, CFG_IBAT1U@h
+ ori r3, r3, CFG_IBAT1U@l
+ mtspr IBAT1L, r4
+ mtspr IBAT1U, r3
+ isync
+
+ /* DBAT 1 */
+ addis r4, r0, CFG_DBAT1L@h
+ ori r4, r4, CFG_DBAT1L@l
+ addis r3, r0, CFG_DBAT1U@h
+ ori r3, r3, CFG_DBAT1U@l
+ mtspr DBAT1L, r4
+ mtspr DBAT1U, r3
+ isync
+
+ /* IBAT 2 */
+ addis r4, r0, CFG_IBAT2L@h
+ ori r4, r4, CFG_IBAT2L@l
+ addis r3, r0, CFG_IBAT2U@h
+ ori r3, r3, CFG_IBAT2U@l
+ mtspr IBAT2L, r4
+ mtspr IBAT2U, r3
+ isync
+
+ /* DBAT 2 */
+ addis r4, r0, CFG_DBAT2L@h
+ ori r4, r4, CFG_DBAT2L@l
+ addis r3, r0, CFG_DBAT2U@h
+ ori r3, r3, CFG_DBAT2U@l
+ mtspr DBAT2L, r4
+ mtspr DBAT2U, r3
+ isync
+
+ /* IBAT 3 */
+ addis r4, r0, CFG_IBAT3L@h
+ ori r4, r4, CFG_IBAT3L@l
+ addis r3, r0, CFG_IBAT3U@h
+ ori r3, r3, CFG_IBAT3U@l
+ mtspr IBAT3L, r4
+ mtspr IBAT3U, r3
+ isync
+
+ /* DBAT 3 */
+ addis r4, r0, CFG_DBAT3L@h
+ ori r4, r4, CFG_DBAT3L@l
+ addis r3, r0, CFG_DBAT3U@h
+ ori r3, r3, CFG_DBAT3U@l
+ mtspr DBAT3L, r4
+ mtspr DBAT3U, r3
+ isync
+
+ /* IBAT 4 */
+ addis r4, r0, CFG_IBAT4L@h
+ ori r4, r4, CFG_IBAT4L@l
+ addis r3, r0, CFG_IBAT4U@h
+ ori r3, r3, CFG_IBAT4U@l
+ mtspr IBAT4L, r4
+ mtspr IBAT4U, r3
+ isync
+
+ /* DBAT 4 */
+ addis r4, r0, CFG_DBAT4L@h
+ ori r4, r4, CFG_DBAT4L@l
+ addis r3, r0, CFG_DBAT4U@h
+ ori r3, r3, CFG_DBAT4U@l
+ mtspr DBAT4L, r4
+ mtspr DBAT4U, r3
+ isync
+
+ /* IBAT 5 */
+ addis r4, r0, CFG_IBAT5L@h
+ ori r4, r4, CFG_IBAT5L@l
+ addis r3, r0, CFG_IBAT5U@h
+ ori r3, r3, CFG_IBAT5U@l
+ mtspr IBAT5L, r4
+ mtspr IBAT5U, r3
+ isync
+
+ /* DBAT 5 */
+ addis r4, r0, CFG_DBAT5L@h
+ ori r4, r4, CFG_DBAT5L@l
+ addis r3, r0, CFG_DBAT5U@h
+ ori r3, r3, CFG_DBAT5U@l
+ mtspr DBAT5L, r4
+ mtspr DBAT5U, r3
+ isync
+
+ /* IBAT 6 */
+ addis r4, r0, CFG_IBAT6L@h
+ ori r4, r4, CFG_IBAT6L@l
+ addis r3, r0, CFG_IBAT6U@h
+ ori r3, r3, CFG_IBAT6U@l
+ mtspr IBAT6L, r4
+ mtspr IBAT6U, r3
+ isync
+
+ /* DBAT 6 */
+ addis r4, r0, CFG_DBAT6L@h
+ ori r4, r4, CFG_DBAT6L@l
+ addis r3, r0, CFG_DBAT6U@h
+ ori r3, r3, CFG_DBAT6U@l
+ mtspr DBAT6L, r4
+ mtspr DBAT6U, r3
+ isync
+
+ /* IBAT 7 */
+ addis r4, r0, CFG_IBAT7L@h
+ ori r4, r4, CFG_IBAT7L@l
+ addis r3, r0, CFG_IBAT7U@h
+ ori r3, r3, CFG_IBAT7U@l
+ mtspr IBAT7L, r4
+ mtspr IBAT7U, r3
+ isync
+
+ /* DBAT 7 */
+ addis r4, r0, CFG_DBAT7L@h
+ ori r4, r4, CFG_DBAT7L@l
+ addis r3, r0, CFG_DBAT7U@h
+ ori r3, r3, CFG_DBAT7U@l
+ mtspr DBAT7L, r4
+ mtspr DBAT7U, r3
+ isync
+
+1:
+ addis r3, 0, 0x0000
+ addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
+ isync
+
+tlblp:
+ tlbie r3
+ sync
+ addi r3, r3, 0x1000
+ cmp 0, 0, r3, r5
+ blt tlblp
+
+ blr
+
+ .globl enable_addr_trans
+enable_addr_trans:
+ /* enable address translation */
+ mfmsr r5
+ ori r5, r5, (MSR_IR | MSR_DR)
+ mtmsr r5
+ isync
+ blr
+
+ .globl disable_addr_trans
+disable_addr_trans:
+ /* disable address translation */
+ mflr r4
+ mfmsr r3
+ andi. r0, r3, (MSR_IR | MSR_DR)
+ beqlr
+ andc r3, r3, r0
+ mtspr SRR0, r4
+ mtspr SRR1, r3
+ rfi
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+ .globl transfer_to_handler
+transfer_to_handler:
+ stw r22,_NIP(r21)
+ lis r22,MSR_POW@h
+ andc r23,r23,r22
+ stw r23,_MSR(r21)
+ SAVE_GPR(7, r21)
+ SAVE_4GPRS(8, r21)
+ SAVE_8GPRS(12, r21)
+ SAVE_8GPRS(24, r21)
+ mflr r23
+ andi. r24,r23,0x3f00 /* get vector offset */
+ stw r24,TRAP(r21)
+ li r22,0
+ stw r22,RESULT(r21)
+ mtspr SPRG2,r22 /* r1 is now kernel sp */
+ lwz r24,0(r23) /* virtual address of handler */
+ lwz r23,4(r23) /* where to go when done */
+ mtspr SRR0,r24
+ mtspr SRR1,r20
+ mtlr r23
+ SYNC
+ rfi /* jump to handler, enable MMU */
+
+int_return:
+ mfmsr r28 /* Disable interrupts */
+ li r4,0
+ ori r4,r4,MSR_EE
+ andc r28,r28,r4
+ SYNC /* Some chip revs need this... */
+ mtmsr r28
+ SYNC
+ lwz r2,_CTR(r1)
+ lwz r0,_LINK(r1)
+ mtctr r2
+ mtlr r0
+ lwz r2,_XER(r1)
+ lwz r0,_CCR(r1)
+ mtspr XER,r2
+ mtcrf 0xFF,r0
+ REST_10GPRS(3, r1)
+ REST_10GPRS(13, r1)
+ REST_8GPRS(23, r1)
+ REST_GPR(31, r1)
+ lwz r2,_NIP(r1) /* Restore environment */
+ lwz r0,_MSR(r1)
+ mtspr SRR0,r2
+ mtspr SRR1,r0
+ lwz r0,GPR0(r1)
+ lwz r2,GPR2(r1)
+ lwz r1,GPR1(r1)
+ SYNC
+ rfi
+
+ .globl dc_read
+dc_read:
+ blr
+
+ .globl get_pvr
+get_pvr:
+ mfspr r3, PVR
+ blr
+
+ .globl get_svr
+get_svr:
+ mfspr r3, SVR
+ blr
+
+
+/*
+ * Function: in8
+ * Description: Input 8 bits
+ */
+ .globl in8
+in8:
+ lbz r3,0x0000(r3)
+ blr
+
+/*
+ * Function: out8
+ * Description: Output 8 bits
+ */
+ .globl out8
+out8:
+ stb r4,0x0000(r3)
+ blr
+
+/*
+ * Function: out16
+ * Description: Output 16 bits
+ */
+ .globl out16
+out16:
+ sth r4,0x0000(r3)
+ blr
+
+/*
+ * Function: out16r
+ * Description: Byte reverse and output 16 bits
+ */
+ .globl out16r
+out16r:
+ sthbrx r4,r0,r3
+ blr
+
+/*
+ * Function: out32
+ * Description: Output 32 bits
+ */
+ .globl out32
+out32:
+ stw r4,0x0000(r3)
+ blr
+
+/*
+ * Function: out32r
+ * Description: Byte reverse and output 32 bits
+ */
+ .globl out32r
+out32r:
+ stwbrx r4,r0,r3
+ blr
+
+/*
+ * Function: in16
+ * Description: Input 16 bits
+ */
+ .globl in16
+in16:
+ lhz r3,0x0000(r3)
+ blr
+
+/*
+ * Function: in16r
+ * Description: Input 16 bits and byte reverse
+ */
+ .globl in16r
+in16r:
+ lhbrx r3,r0,r3
+ blr
+
+/*
+ * Function: in32
+ * Description: Input 32 bits
+ */
+ .globl in32
+in32:
+ lwz 3,0x0000(3)
+ blr
+
+/*
+ * Function: in32r
+ * Description: Input 32 bits and byte reverse
+ */
+ .globl in32r
+in32r:
+ lwbrx r3,r0,r3
+ blr
+
+/*
+ * Function: ppcDcbf
+ * Description: Data Cache block flush
+ * Input: r3 = effective address
+ * Output: none.
+ */
+ .globl ppcDcbf
+ppcDcbf:
+ dcbf r0,r3
+ blr
+
+/*
+ * Function: ppcDcbi
+ * Description: Data Cache block Invalidate
+ * Input: r3 = effective address
+ * Output: none.
+ */
+ .globl ppcDcbi
+ppcDcbi:
+ dcbi r0,r3
+ blr
+
+/*
+ * Function: ppcDcbz
+ * Description: Data Cache block zero.
+ * Input: r3 = effective address
+ * Output: none.
+ */
+ .globl ppcDcbz
+ppcDcbz:
+ dcbz r0,r3
+ blr
+
+/*
+ * Function: ppcSync
+ * Description: Processor Synchronize
+ * Input: none.
+ * Output: none.
+ */
+ .globl ppcSync
+ppcSync:
+ sync
+ blr
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+ .globl relocate_code
+relocate_code:
+
+ mr r1, r3 /* Set new stack pointer */
+ mr r9, r4 /* Save copy of Global Data pointer */
+ mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
+ mr r10, r5 /* Save copy of Destination Address */
+
+ mr r3, r5 /* Destination Address */
+ lis r4, CFG_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CFG_MONITOR_BASE@l
+ lwz r5, GOT(__init_end)
+ sub r5, r5, r4
+ li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+
+ /*
+ * Fix GOT pointer:
+ *
+ * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ *
+ * Offset:
+ */
+ sub r15, r10, r4
+
+ /* First our own GOT */
+ add r14, r14, r15
+ /* then the one used by the C code */
+ add r30, r30, r15
+
+ /*
+ * Now relocate code
+ */
+#ifdef CONFIG_ECC
+ bl board_relocate_rom
+ sync
+ mr r3, r10 /* Destination Address */
+ lis r4, CFG_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CFG_MONITOR_BASE@l
+ lwz r5, GOT(__init_end)
+ sub r5, r5, r4
+ li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+#else
+ cmplw cr1,r3,r4
+ addi r0,r5,3
+ srwi. r0,r0,2
+ beq cr1,4f /* In place copy is not necessary */
+ beq 7f /* Protect against 0 count */
+ mtctr r0
+ bge cr1,2f
+
+ la r8,-4(r4)
+ la r7,-4(r3)
+1: lwzu r0,4(r8)
+ stwu r0,4(r7)
+ bdnz 1b
+ b 4f
+
+2: slwi r0,r0,2
+ add r8,r4,r0
+ add r7,r3,r0
+3: lwzu r0,-4(r8)
+ stwu r0,-4(r7)
+ bdnz 3b
+#endif
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4: cmpwi r6,0
+ add r5,r3,r5
+ beq 7f /* Always flush prefetch queue in any case */
+ subi r0,r6,1
+ andc r3,r3,r0
+ mr r4,r3
+5: dcbst 0,r4
+ add r4,r4,r6
+ cmplw r4,r5
+ blt 5b
+ sync /* Wait for all dcbst to complete on bus */
+ mr r4,r3
+6: icbi 0,r4
+ add r4,r4,r6
+ cmplw r4,r5
+ blt 6b
+7: sync /* Wait for all icbi to complete on bus */
+ isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+ addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+ mtlr r0
+ blr
+
+in_ram:
+#ifdef CONFIG_ECC
+ bl board_init_ecc
+#endif
+ /*
+ * Relocation Function, r14 point to got2+0x8000
+ *
+ * Adjust got2 pointers, no need to check for 0, this code
+ * already puts a few entries in the table.
+ */
+ li r0,__got2_entries@sectoff@l
+ la r3,GOT(_GOT2_TABLE_)
+ lwz r11,GOT(_GOT2_TABLE_)
+ mtctr r0
+ sub r11,r3,r11
+ addi r3,r3,-4
+1: lwzu r0,4(r3)
+ add r0,r0,r11
+ stw r0,0(r3)
+ bdnz 1b
+
+ /*
+ * Now adjust the fixups and the pointers to the fixups
+ * in case we need to move ourselves again.
+ */
+2: li r0,__fixup_entries@sectoff@l
+ lwz r3,GOT(_FIXUP_TABLE_)
+ cmpwi r0,0
+ mtctr r0
+ addi r3,r3,-4
+ beq 4f
+3: lwzu r4,4(r3)
+ lwzux r0,r4,r11
+ add r0,r0,r11
+ stw r10,0(r3)
+ stw r0,0(r4)
+ bdnz 3b
+4:
+/* clear_bss: */
+ /*
+ * Now clear BSS segment
+ */
+ lwz r3,GOT(__bss_start)
+ lwz r4,GOT(_end)
+
+ cmplw 0, r3, r4
+ beq 6f
+
+ li r0, 0
+5:
+ stw r0, 0(r3)
+ addi r3, r3, 4
+ cmplw 0, r3, r4
+ bne 5b
+6:
+ mr r3, r9 /* Init Date pointer */
+ mr r4, r10 /* Destination Address */
+ bl board_init_r
+
+ /* not reached - end relocate_code */
+/*-----------------------------------------------------------------------*/
+
+ /*
+ * Copy exception vector code to low memory
+ *
+ * r3: dest_addr
+ * r7: source address, r8: end address, r9: target address
+ */
+ .globl trap_init
+trap_init:
+ lwz r7, GOT(_start)
+ lwz r8, GOT(_end_of_vectors)
+
+ li r9, 0x100 /* reset vector always at 0x100 */
+
+ cmplw 0, r7, r8
+ bgelr /* return if r7>=r8 - just in case */
+
+ mflr r4 /* save link register */
+1:
+ lwz r0, 0(r7)
+ stw r0, 0(r9)
+ addi r7, r7, 4
+ addi r9, r9, 4
+ cmplw 0, r7, r8
+ bne 1b
+
+ /*
+ * relocate `hdlr' and `int_return' entries
+ */
+ li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+ li r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 2b
+
+ li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+ bl trap_reloc
+
+ li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+ bl trap_reloc
+
+ li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+ li r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 3b
+
+ li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
+ li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 4b
+
+ /* enable execptions from RAM vectors */
+ mfmsr r7
+ li r8,MSR_IP
+ andc r7,r7,r8
+ mtmsr r7
+
+ mtlr r4 /* restore link register */
+ blr
+
+ /*
+ * Function: relocate entries for one exception vector
+ */
+trap_reloc:
+ lwz r0, 0(r7) /* hdlr ... */
+ add r0, r0, r3 /* ... += dest_addr */
+ stw r0, 0(r7)
+
+ lwz r0, 4(r7) /* int_return ... */
+ add r0, r0, r3 /* ... += dest_addr */
+ stw r0, 4(r7)
+
+ sync
+ isync
+
+ blr
+
+.globl enable_ext_addr
+enable_ext_addr:
+ mfspr r0, HID0
+ lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
+ ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
+ mtspr HID0, r0
+ sync
+ isync
+ blr
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+.globl setup_ccsrbar
+setup_ccsrbar:
+ /* Special sequence needed to update CCSRBAR itself */
+ lis r4, CFG_CCSRBAR_DEFAULT@h
+ ori r4, r4, CFG_CCSRBAR_DEFAULT@l
+
+ lis r5, CFG_CCSRBAR@h
+ ori r5, r5, CFG_CCSRBAR@l
+ srwi r6,r5,12
+ stw r6, 0(r4)
+ isync
+
+ lis r5, 0xffff
+ ori r5,r5,0xf000
+ lwz r5, 0(r5)
+ isync
+
+ lis r3, CFG_CCSRBAR@h
+ lwz r5, CFG_CCSRBAR@l(r3)
+ isync
+
+ blr
+#endif
+
+#ifdef CFG_INIT_RAM_LOCK
+lock_ram_in_cache:
+ /* Allocate Initial RAM in data cache.
+ */
+ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+ li r2, ((CFG_INIT_RAM_END & ~31) + \
+ (CFG_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r2
+1:
+ dcbz r0, r3
+ addi r3, r3, 32
+ bdnz 1b
+#if 1
+/* Lock the data cache */
+ mfspr r0, HID0
+ ori r0, r0, 0x1000
+ sync
+ mtspr HID0, r0
+ sync
+ blr
+#endif
+#if 0
+ /* Lock the first way of the data cache */
+ mfspr r0, LDSTCR
+ ori r0, r0, 0x0080
+#if defined(CONFIG_ALTIVEC)
+ dssall
+#endif
+ sync
+ mtspr LDSTCR, r0
+ sync
+ isync
+ blr
+#endif
+
+.globl unlock_ram_in_cache
+unlock_ram_in_cache:
+ /* invalidate the INIT_RAM section */
+ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+ li r2, ((CFG_INIT_RAM_END & ~31) + \
+ (CFG_INIT_RAM_ADDR & 31) + 31) / 32
+ mtctr r2
+1: icbi r0, r3
+ addi r3, r3, 32
+ bdnz 1b
+ sync /* Wait for all icbi to complete on bus */
+ isync
+#if 1
+/* Unlock the data cache and invalidate it */
+ mfspr r0, HID0
+ li r3,0x1000
+ andc r0,r0,r3
+ li r3,0x0400
+ or r0,r0,r3
+ sync
+ mtspr HID0, r0
+ sync
+ blr
+#endif
+#if 0
+ /* Unlock the first way of the data cache */
+ mfspr r0, LDSTCR
+ li r3,0x0080
+ andc r0,r0,r3
+#ifdef CONFIG_ALTIVEC
+ dssall
+#endif
+ sync
+ mtspr LDSTCR, r0
+ sync
+ isync
+ li r3,0x0400
+ or r0,r0,r3
+ sync
+ mtspr HID0, r0
+ sync
+ blr
+#endif
+#endif
+
+/* If this is a multi-cpu system then we need to handle the
+ * 2nd cpu. The assumption is that the 2nd cpu is being
+ * held in boot holdoff mode until the 1st cpu unlocks it
+ * from Linux. We'll do some basic cpu init and then pass
+ * it to the Linux Reset Vector.
+ * Sri: Much of this initialization is not required. Linux
+ * rewrites the bats, and the sprs and also enables the L1 cache.
+ */
+#if (CONFIG_NUM_CPUS > 1)
+.globl secondary_cpu_setup
+secondary_cpu_setup:
+ /* Do only core setup on all cores except cpu0 */
+ bl invalidate_bats
+ sync
+ bl enable_ext_addr
+
+#ifdef CFG_L2
+ /* init the L2 cache */
+ addis r3, r0, L2_INIT@h
+ ori r3, r3, L2_INIT@l
+ sync
+ mtspr l2cr, r3
+#ifdef CONFIG_ALTIVEC
+ dssall
+#endif
+ /* invalidate the L2 cache */
+ bl l2cache_invalidate
+ sync
+#endif
+
+ /* enable and invalidate the data cache */
+ bl dcache_enable
+ sync
+
+ /* enable and invalidate the instruction cache*/
+ bl icache_enable
+ sync
+
+ /* TBEN in HID0 */
+ mfspr r4, HID0
+ oris r4, r4, 0x0400
+ mtspr HID0, r4
+ sync
+ isync
+
+ /*SYNCBE|ABE in HID1*/
+ mfspr r4, HID1
+ ori r4, r4, 0x0C00
+ mtspr HID1, r4
+ sync
+ isync
+
+ lis r3, CONFIG_LINUX_RESET_VEC@h
+ ori r3, r3, CONFIG_LINUX_RESET_VEC@l
+ mtlr r3
+ blr
+
+ /* Never Returns, Running in Linux Now */
+#endif
--- /dev/null
+/*
+ * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
+ *
+ * Modified by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras (paulus@cs.anu.edu.au)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware exceptions
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+int (*debugger_exception_handler)(struct pt_regs *) = 0;
+#endif
+
+/* Returns 0 if exception not found and fixup otherwise. */
+extern unsigned long search_exception_table(unsigned long);
+
+#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
+
+/*
+ * Trap & Exception support
+ */
+
+void
+print_backtrace(unsigned long *sp)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ int cnt = 0;
+ unsigned long i;
+
+ printf("Call backtrace: ");
+ while (sp) {
+ if ((uint) sp > END_OF_MEM)
+ break;
+
+ i = sp[1];
+ if (cnt++ % 7 == 0)
+ printf("\n");
+ printf("%08lX ", i);
+ if (cnt > 32)
+ break;
+ sp = (unsigned long *)*sp;
+ }
+ printf("\n");
+}
+
+void
+show_regs(struct pt_regs *regs)
+{
+ int i;
+
+ printf("NIP: %08lX XER: %08lX LR: %08lX REGS:"
+ " %p TRAP: %04lx DAR: %08lX\n",
+ regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+ printf("MSR: %08lx EE: %01x PR: %01x FP:"
+ " %01x ME: %01x IR/DR: %01x%01x\n",
+ regs->msr, regs->msr & MSR_EE ? 1 : 0,
+ regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
+ regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
+ regs->msr & MSR_DR ? 1 : 0);
+
+ printf("\n");
+ for (i = 0; i < 32; i++) {
+ if ((i % 8) == 0) {
+ printf("GPR%02d: ", i);
+ }
+
+ printf("%08lX ", regs->gpr[i]);
+ if ((i % 8) == 7) {
+ printf("\n");
+ }
+ }
+}
+
+
+void
+_exception(int signr, struct pt_regs *regs)
+{
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
+}
+
+void
+MachineCheckException(struct pt_regs *regs)
+{
+ unsigned long fixup;
+
+ /* Probing PCI using config cycles cause this exception
+ * when a device is not present. Catch it and return to
+ * the PCI exception handler.
+ */
+ if ((fixup = search_exception_table(regs->nip)) != 0) {
+ regs->nip = fixup;
+ return;
+ }
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler) (regs))
+ return;
+#endif
+
+ printf("Machine check in kernel mode.\n");
+ printf("Caused by (from msr): ");
+ printf("regs %p ", regs);
+ switch (regs->msr & 0x000F0000) {
+ case (0x80000000 >> 12):
+ printf("Machine check signal - probably due to mm fault\n"
+ "with mmu off\n");
+ break;
+ case (0x80000000 >> 13):
+ printf("Transfer error ack signal\n");
+ break;
+ case (0x80000000 >> 14):
+ printf("Data parity signal\n");
+ break;
+ case (0x80000000 >> 15):
+ printf("Address parity signal\n");
+ break;
+ default:
+ printf("Unknown values in msr\n");
+ }
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("machine check");
+}
+
+void
+AlignmentException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler) (regs))
+ return;
+#endif
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Alignment Exception");
+}
+
+void
+ProgramCheckException(struct pt_regs *regs)
+{
+ unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
+ int i, j;
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler) (regs))
+ return;
+#endif
+ show_regs(regs);
+
+ p = (unsigned char *)((unsigned long)p & 0xFFFFFFE0);
+ p -= 32;
+ for (i = 0; i < 256; i += 16) {
+ printf("%08x: ", (unsigned int)p + i);
+ for (j = 0; j < 16; j++) {
+ printf("%02x ", p[i + j]);
+ }
+ printf("\n");
+ }
+
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Program Check Exception");
+}
+
+void
+SoftEmuException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler) (regs))
+ return;
+#endif
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Software Emulation Exception");
+}
+
+void
+UnknownException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler) (regs))
+ return;
+#endif
+ printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+ regs->nip, regs->msr, regs->trap);
+ _exception(0, regs);
+}
+
+/*
+ * Probe an address by reading.
+ * If not present, return -1,
+ * otherwise return 0.
+ */
+int
+addr_probe(uint *addr)
+{
+ return 0;
+}
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# CFLAGS += -DET_DEBUG
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o kgdb.o
-OBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \
+COBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \
fec.o i2c.o interrupts.o lcd.o scc.o \
serial.o speed.o spi.o \
traps.o upatch.o video.o
SOBJS = plprcr_write.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS) kgdb.o
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(obj)kgdb.o
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-AOBJS = traps.o
-OBJS = cpu.o interrupts.o serial.o asmi.o spi.o
+SOBJS = traps.o
+COBJS = cpu.o interrupts.o serial.o asmi.o spi.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
-$(LIB): $(OBJS) $(AOBJS)
- $(AR) crv $@ $(OBJS) $(AOBJS)
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-AOBJS = exceptions.o
-OBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o
+SOBJS = exceptions.o
+COBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
-$(LIB): $(OBJS) $(AOBJS)
- $(AR) crv $@ $(OBJS) $(AOBJS)
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
-
hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCI_PNP */
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
-#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
+#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
+ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
#endif
hose->last_busno = pci_hose_scan(hose);
}
}
-
void pci_init_board(void)
{
pci_440_init (&ppc440_hose);
+#if defined(CONFIG_440SPE)
+ pcie_setup_hoses();
+#endif
}
#endif /* CONFIG_440 & CONFIG_PCI */
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (c) 2005 Cisco Systems. All rights reserved.
+ * Roland Dreier <rolandd@cisco.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/processor.h>
+#include <asm-ppc/io.h>
+#include <ppc4xx.h>
+#include <common.h>
+#include <pci.h>
+
+#include "440spe_pcie.h"
+
+#if defined(CONFIG_440SPE)
+#if defined(CONFIG_PCI)
+
+enum {
+ PTYPE_ENDPOINT = 0x0,
+ PTYPE_LEGACY_ENDPOINT = 0x1,
+ PTYPE_ROOT_PORT = 0x4,
+
+ LNKW_X1 = 0x1,
+ LNKW_X4 = 0x4,
+ LNKW_X8 = 0x8
+};
+
+static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
+ int offset, int len, u32 *val) {
+
+ *val = 0;
+ /*
+ * 440SPE implements only one function per port
+ */
+ if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
+ return 0;
+
+ devfn = PCI_BDF(0,0,0);
+ offset += devfn << 4;
+
+ switch (len) {
+ case 1:
+ *val = in_8(hose->cfg_data + offset);
+ break;
+ case 2:
+ *val = in_le16((u16 *)(hose->cfg_data + offset));
+ break;
+ default:
+ *val = in_le32((u32 *)(hose->cfg_data + offset));
+ break;
+ }
+ return 0;
+}
+
+static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
+ int offset, int len, u32 val) {
+
+ /*
+ * 440SPE implements only one function per port
+ */
+ if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
+ return 0;
+
+ devfn = PCI_BDF(0,0,0);
+ offset += devfn << 4;
+
+ switch (len) {
+ case 1:
+ out_8(hose->cfg_data + offset, val);
+ break;
+ case 2:
+ out_le16((u16 *)(hose->cfg_data + offset), val);
+ break;
+ default:
+ out_le32((u32 *)(hose->cfg_data + offset), val);
+ break;
+ }
+ return 0;
+}
+
+int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
+{
+ u32 v;
+ int rv;
+
+ rv = pcie_read_config(hose, dev, offset, 1, &v);
+ *val = (u8)v;
+ return rv;
+}
+
+int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
+{
+ u32 v;
+ int rv;
+
+ rv = pcie_read_config(hose, dev, offset, 2, &v);
+ *val = (u16)v;
+ return rv;
+}
+
+int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
+{
+ u32 v;
+ int rv;
+
+ rv = pcie_read_config(hose, dev, offset, 3, &v);
+ *val = (u32)v;
+ return rv;
+}
+
+int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
+{
+ return pcie_write_config(hose,(u32)dev,offset,1,val);
+}
+
+int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
+{
+ return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
+}
+
+int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
+{
+ return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
+}
+
+static void ppc440spe_setup_utl(u32 port) {
+
+ volatile void *utl_base = NULL;
+
+ /*
+ * Map UTL registers
+ */
+ switch (port) {
+ case 0:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
+ break;
+
+ case 1:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
+ break;
+
+ case 2:
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
+ mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
+ break;
+ }
+ utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
+
+ /*
+ * Set buffer allocations and then assert VRB and TXE.
+ */
+ out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
+ out_be32(utl_base + PEUTL_INTR, 0x02000000);
+ out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
+ out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
+ out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
+ out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
+ out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
+ out_be32(utl_base + PEUTL_PCTL, 0x80800066);
+}
+
+static int check_error(void)
+{
+ u32 valPE0, valPE1, valPE2;
+ int err = 0;
+
+ /* SDR0_PEGPLLLCT1 reset */
+ if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
+ printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
+ }
+
+ valPE0 = SDR_READ(PESDR0_RCSSET);
+ valPE1 = SDR_READ(PESDR1_RCSSET);
+ valPE2 = SDR_READ(PESDR2_RCSSET);
+
+ /* SDR0_PExRCSSET rstgu */
+ if (!(valPE0 & 0x01000000) ||
+ !(valPE1 & 0x01000000) ||
+ !(valPE2 & 0x01000000)) {
+ printf("PCIE: SDR0_PExRCSSET rstgu error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET rstdl */
+ if (!(valPE0 & 0x00010000) ||
+ !(valPE1 & 0x00010000) ||
+ !(valPE2 & 0x00010000)) {
+ printf("PCIE: SDR0_PExRCSSET rstdl error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET rstpyn */
+ if ((valPE0 & 0x00001000) ||
+ (valPE1 & 0x00001000) ||
+ (valPE2 & 0x00001000)) {
+ printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET hldplb */
+ if ((valPE0 & 0x10000000) ||
+ (valPE1 & 0x10000000) ||
+ (valPE2 & 0x10000000)) {
+ printf("PCIE: SDR0_PExRCSSET hldplb error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET rdy */
+ if ((valPE0 & 0x00100000) ||
+ (valPE1 & 0x00100000) ||
+ (valPE2 & 0x00100000)) {
+ printf("PCIE: SDR0_PExRCSSET rdy error\n");
+ err = -1;
+ }
+
+ /* SDR0_PExRCSSET shutdown */
+ if ((valPE0 & 0x00000100) ||
+ (valPE1 & 0x00000100) ||
+ (valPE2 & 0x00000100)) {
+ printf("PCIE: SDR0_PExRCSSET shutdown error\n");
+ err = -1;
+ }
+ return err;
+}
+
+/*
+ * Initialize PCI Express core
+ */
+int ppc440spe_init_pcie(void)
+{
+ int time_out = 20;
+
+ /* Set PLL clock receiver to LVPECL */
+ SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
+
+ if (check_error())
+ return -1;
+
+ if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
+ {
+ printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
+ SDR_READ(PESDR0_PLLLCT2));
+ return -1;
+ }
+ /* De-assert reset of PCIe PLL, wait for lock */
+ SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
+ udelay(3);
+
+ while (time_out) {
+ if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
+ time_out--;
+ udelay(1);
+ } else
+ break;
+ }
+ if (!time_out) {
+ printf("PCIE: VCO output not locked\n");
+ return -1;
+ }
+ return 0;
+}
+
+/*
+ * Yucca board as End point and root point setup
+ * and
+ * testing inbound and out bound windows
+ *
+ * YUCCA board can be plugged into another yucca board or you can get PCI-E
+ * cable which can be used to setup loop back from one port to another port.
+ * Please rememeber that unless there is a endpoint plugged in to root port it
+ * will not initialize. It is the same in case of endpoint , unless there is
+ * root port attached it will not initialize.
+ *
+ * In this release of software all the PCI-E ports are configured as either
+ * endpoint or rootpoint.In future we will have support for selective ports
+ * setup as endpoint and root point in single board.
+ *
+ * Once your board came up as root point , you can verify by reading
+ * /proc/bus/pci/devices. Where you can see the configuration registers
+ * of end point device attached to the port.
+ *
+ * Enpoint cofiguration can be verified by connecting Yucca board to any
+ * host or another yucca board. Then try to scan the device. In case of
+ * linux use "lspci" or appripriate os command.
+ *
+ * How do I verify the inbound and out bound windows ?(yucca to yucca)
+ * in this configuration inbound and outbound windows are setup to access
+ * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address
+ * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000,
+ * This is waere your POM(PLB out bound memory window) mapped. then
+ * read the data from other yucca board's u-boot prompt at address
+ * 0x9000 0000(SRAM). Data should match.
+ * In case of inbound , write data to u-boot command prompt at 0xb000 0000
+ * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check
+ * data at 0x9000 0000(SRAM).Data should match.
+ */
+int ppc440spe_init_pcie_rootport(int port)
+{
+ static int core_init;
+ volatile u32 val = 0;
+ int attempts;
+
+ if (!core_init) {
+ ++core_init;
+ if (ppc440spe_init_pcie())
+ return -1;
+ }
+
+ /*
+ * Initialize various parts of the PCI Express core for our port:
+ *
+ * - Set as a root port and enable max width
+ * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
+ * - Set up UTL configuration.
+ * - Increase SERDES drive strength to levels suggested by AMCC.
+ * - De-assert RSTPYN, RSTDL and RSTGU.
+ *
+ * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
+ * default setting 0x11310000. The register has new fields,
+ * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
+ * hang.
+ */
+ switch (port) {
+ case 0:
+ SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
+
+ SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
+ if (!ppc440spe_revB())
+ SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
+ SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
+ SDR_WRITE(PESDR0_RCSSET,
+ (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ break;
+
+ case 1:
+ SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
+ SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
+ if (!ppc440spe_revB())
+ SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
+ SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
+ SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
+ SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
+ SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
+ SDR_WRITE(PESDR1_RCSSET,
+ (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ break;
+
+ case 2:
+ SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
+ SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
+ if (!ppc440spe_revB())
+ SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
+ SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
+ SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
+ SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
+ SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
+ SDR_WRITE(PESDR2_RCSSET,
+ (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ break;
+ }
+ /*
+ * Notice: the following delay has critical impact on device
+ * initialization - if too short (<50ms) the link doesn't get up.
+ */
+ mdelay(100);
+
+ switch (port) {
+ case 0:
+ val = SDR_READ(PESDR0_RCSSTS);
+ break;
+ case 1:
+ val = SDR_READ(PESDR1_RCSSTS);
+ break;
+ case 2:
+ val = SDR_READ(PESDR2_RCSSTS);
+ break;
+ }
+
+ if (val & (1 << 20)) {
+ printf("PCIE%d: PGRST failed %08x\n", port, val);
+ return -1;
+ }
+
+ /*
+ * Verify link is up
+ */
+ val = 0;
+ switch (port) {
+ case 0:
+ val = SDR_READ(PESDR0_LOOP);
+ break;
+ case 1:
+ val = SDR_READ(PESDR1_LOOP);
+ break;
+ case 2:
+ val = SDR_READ(PESDR2_LOOP);
+ break;
+ }
+ if (!(val & 0x00001000)) {
+ printf("PCIE%d: link is not up.\n", port);
+ return -1;
+ }
+
+ /*
+ * Setup UTL registers - but only on revA!
+ * We use default settings for revB chip.
+ */
+ if (!ppc440spe_revB())
+ ppc440spe_setup_utl(port);
+
+ /*
+ * We map PCI Express configuration access into the 512MB regions
+ *
+ * NOTICE: revB is very strict about PLB real addressess and ranges to
+ * be mapped for config space; it seems to only work with d_nnnn_nnnn
+ * range (hangs the core upon config transaction attempts when set
+ * otherwise) while revA uses c_nnnn_nnnn.
+ *
+ * For revA:
+ * PCIE0: 0xc_4000_0000
+ * PCIE1: 0xc_8000_0000
+ * PCIE2: 0xc_c000_0000
+ *
+ * For revB:
+ * PCIE0: 0xd_0000_0000
+ * PCIE1: 0xd_2000_0000
+ * PCIE2: 0xd_4000_0000
+ */
+
+ switch (port) {
+ case 0:
+ if (ppc440spe_revB()) {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
+ } else {
+ /* revA */
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
+ }
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
+ break;
+
+ case 1:
+ if (ppc440spe_revB()) {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
+ } else {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
+ }
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
+ break;
+
+ case 2:
+ if (ppc440spe_revB()) {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
+ } else {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
+ }
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
+ break;
+ }
+
+ /*
+ * Check for VC0 active and assert RDY.
+ */
+ attempts = 10;
+ switch (port) {
+ case 0:
+ while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printf("PCIE0: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+ SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
+ break;
+ case 1:
+ while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printf("PCIE1: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+
+ SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
+ break;
+ case 2:
+ while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printf("PCIE2: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+
+ SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
+ break;
+ }
+ mdelay(100);
+
+ return 0;
+}
+
+int ppc440spe_init_pcie_endport(int port)
+{
+ static int core_init;
+ volatile u32 val = 0;
+ int attempts;
+
+ if (!core_init) {
+ ++core_init;
+ if (ppc440spe_init_pcie())
+ return -1;
+ }
+
+ /*
+ * Initialize various parts of the PCI Express core for our port:
+ *
+ * - Set as a end port and enable max width
+ * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
+ * - Set up UTL configuration.
+ * - Increase SERDES drive strength to levels suggested by AMCC.
+ * - De-assert RSTPYN, RSTDL and RSTGU.
+ *
+ * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
+ * default setting 0x11310000. The register has new fields,
+ * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
+ * hang.
+ */
+ switch (port) {
+ case 0:
+ SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12);
+
+ SDR_WRITE(PESDR0_UTLSET1, 0x20222222);
+ if (!ppc440spe_revB())
+ SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
+ SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
+ SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
+ SDR_WRITE(PESDR0_RCSSET,
+ (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ break;
+
+ case 1:
+ SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
+ SDR_WRITE(PESDR1_UTLSET1, 0x20222222);
+ if (!ppc440spe_revB())
+ SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
+ SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
+ SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
+ SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
+ SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
+ SDR_WRITE(PESDR1_RCSSET,
+ (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ break;
+
+ case 2:
+ SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
+ SDR_WRITE(PESDR2_UTLSET1, 0x20222222);
+ if (!ppc440spe_revB())
+ SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
+ SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
+ SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
+ SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
+ SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
+ SDR_WRITE(PESDR2_RCSSET,
+ (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ break;
+ }
+ /*
+ * Notice: the following delay has critical impact on device
+ * initialization - if too short (<50ms) the link doesn't get up.
+ */
+ mdelay(100);
+
+ switch (port) {
+ case 0: val = SDR_READ(PESDR0_RCSSTS); break;
+ case 1: val = SDR_READ(PESDR1_RCSSTS); break;
+ case 2: val = SDR_READ(PESDR2_RCSSTS); break;
+ }
+
+ if (val & (1 << 20)) {
+ printf("PCIE%d: PGRST failed %08x\n", port, val);
+ return -1;
+ }
+
+ /*
+ * Verify link is up
+ */
+ val = 0;
+ switch (port)
+ {
+ case 0:
+ val = SDR_READ(PESDR0_LOOP);
+ break;
+ case 1:
+ val = SDR_READ(PESDR1_LOOP);
+ break;
+ case 2:
+ val = SDR_READ(PESDR2_LOOP);
+ break;
+ }
+ if (!(val & 0x00001000)) {
+ printf("PCIE%d: link is not up.\n", port);
+ return -1;
+ }
+
+ /*
+ * Setup UTL registers - but only on revA!
+ * We use default settings for revB chip.
+ */
+ if (!ppc440spe_revB())
+ ppc440spe_setup_utl(port);
+
+ /*
+ * We map PCI Express configuration access into the 512MB regions
+ *
+ * NOTICE: revB is very strict about PLB real addressess and ranges to
+ * be mapped for config space; it seems to only work with d_nnnn_nnnn
+ * range (hangs the core upon config transaction attempts when set
+ * otherwise) while revA uses c_nnnn_nnnn.
+ *
+ * For revA:
+ * PCIE0: 0xc_4000_0000
+ * PCIE1: 0xc_8000_0000
+ * PCIE2: 0xc_c000_0000
+ *
+ * For revB:
+ * PCIE0: 0xd_0000_0000
+ * PCIE1: 0xd_2000_0000
+ * PCIE2: 0xd_4000_0000
+ */
+ switch (port) {
+ case 0:
+ if (ppc440spe_revB()) {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
+ } else {
+ /* revA */
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
+ }
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
+ break;
+
+ case 1:
+ if (ppc440spe_revB()) {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
+ } else {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
+ }
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
+ break;
+
+ case 2:
+ if (ppc440spe_revB()) {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
+ } else {
+ mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
+ mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
+ }
+ mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
+ break;
+ }
+
+ /*
+ * Check for VC0 active and assert RDY.
+ */
+ attempts = 10;
+ switch (port) {
+ case 0:
+ while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printf("PCIE0: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+ SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
+ break;
+ case 1:
+ while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printf("PCIE1: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+
+ SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
+ break;
+ case 2:
+ while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
+ if (!(attempts--)) {
+ printf("PCIE2: VC0 not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+
+ SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
+ break;
+ }
+ mdelay(100);
+
+ return 0;
+}
+
+void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
+{
+ volatile void *mbase = NULL;
+ volatile void *rmbase = NULL;
+
+ pci_set_ops(hose,
+ pcie_read_config_byte,
+ pcie_read_config_word,
+ pcie_read_config_dword,
+ pcie_write_config_byte,
+ pcie_write_config_word,
+ pcie_write_config_dword);
+
+ switch (port) {
+ case 0:
+ mbase = (u32 *)CFG_PCIE0_XCFGBASE;
+ rmbase = (u32 *)CFG_PCIE0_CFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
+ break;
+ case 1:
+ mbase = (u32 *)CFG_PCIE1_XCFGBASE;
+ rmbase = (u32 *)CFG_PCIE1_CFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
+ break;
+ case 2:
+ mbase = (u32 *)CFG_PCIE2_XCFGBASE;
+ rmbase = (u32 *)CFG_PCIE2_CFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
+ break;
+ }
+
+ /*
+ * Set bus numbers on our root port
+ */
+ out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
+ out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
+ out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
+
+ /*
+ * Set up outbound translation to hose->mem_space from PLB
+ * addresses at an offset of 0xd_0000_0000. We set the low
+ * bits of the mask to 11 to turn off splitting into 8
+ * subregions and to enable the outbound translation.
+ */
+ out_le32(mbase + PECFG_POM0LAH, 0x00000000);
+ out_le32(mbase + PECFG_POM0LAL, 0x00000000);
+
+ switch (port) {
+ case 0:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+ case 1:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE));
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+ case 2:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE));
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+ }
+
+ /* Set up 16GB inbound memory window at 0 */
+ out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
+ out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
+ out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
+ out_le32(mbase + PECFG_BAR0LMPA, 0);
+
+ out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
+ out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
+ out_le32(mbase + PECFG_PIM0LAL, 0);
+ out_le32(mbase + PECFG_PIM0LAH, 0);
+ out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
+ out_le32(mbase + PECFG_PIM1LAH, 0x00000004);
+ out_le32(mbase + PECFG_PIMEN, 0x1);
+
+ /* Enable I/O, Mem, and Busmaster cycles */
+ out_le16((u16 *)(mbase + PCI_COMMAND),
+ in_le16((u16 *)(mbase + PCI_COMMAND)) |
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ printf("PCIE:%d successfully set as rootpoint\n",port);
+}
+
+int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
+{
+ volatile void *mbase = NULL;
+ int attempts = 0;
+
+ pci_set_ops(hose,
+ pcie_read_config_byte,
+ pcie_read_config_word,
+ pcie_read_config_dword,
+ pcie_write_config_byte,
+ pcie_write_config_word,
+ pcie_write_config_dword);
+
+ switch (port) {
+ case 0:
+ mbase = (u32 *)CFG_PCIE0_XCFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
+ break;
+ case 1:
+ mbase = (u32 *)CFG_PCIE1_XCFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
+ break;
+ case 2:
+ mbase = (u32 *)CFG_PCIE2_XCFGBASE;
+ hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
+ break;
+ }
+
+ /*
+ * Set up outbound translation to hose->mem_space from PLB
+ * addresses at an offset of 0xd_0000_0000. We set the low
+ * bits of the mask to 11 to turn off splitting into 8
+ * subregions and to enable the outbound translation.
+ */
+ out_le32(mbase + PECFG_POM0LAH, 0x00001ff8);
+ out_le32(mbase + PECFG_POM0LAL, 0x00001000);
+
+ switch (port) {
+ case 0:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE);
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+ case 1:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE));
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+ case 2:
+ mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
+ mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
+ port * CFG_PCIE_MEMSIZE));
+ mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
+ mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
+ ~(CFG_PCIE_MEMSIZE - 1) | 3);
+ break;
+ }
+
+ /* Set up 16GB inbound memory window at 0 */
+ out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
+ out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
+ out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
+ out_le32(mbase + PECFG_BAR0LMPA, 0);
+ out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
+ out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */
+ out_le32(mbase + PECFG_PIMEN, 0x1);
+
+ /* Enable I/O, Mem, and Busmaster cycles */
+ out_le16((u16 *)(mbase + PCI_COMMAND),
+ in_le16((u16 *)(mbase + PCI_COMMAND)) |
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
+ out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
+ attempts = 10;
+ switch (port) {
+ case 0:
+ while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) {
+ if (!(attempts--)) {
+ printf("PCIE0: BMEN is not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+ break;
+ case 1:
+ while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) {
+ if (!(attempts--)) {
+ printf("PCIE1: BMEN is not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+ break;
+ case 2:
+ while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) {
+ if (!(attempts--)) {
+ printf("PCIE2: BMEN is not active\n");
+ return -1;
+ }
+ mdelay(1000);
+ }
+ break;
+ }
+ printf("PCIE:%d successfully set as endpoint\n",port);
+
+ return 0;
+}
+#endif /* CONFIG_PCI */
+#endif /* CONFIG_440SPE */
--- /dev/null
+/*
+ * Copyright (c) 2005 Cisco Systems. All rights reserved.
+ * Roland Dreier <rolandd@cisco.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <ppc4xx.h>
+#ifndef __440SPE_PCIE_H
+#define __440SPE_PCIE_H
+
+#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);})
+
+#define DCRN_SDR0_CFGADDR 0x00e
+#define DCRN_SDR0_CFGDATA 0x00f
+
+#define DCRN_PCIE0_BASE 0x100
+#define DCRN_PCIE1_BASE 0x120
+#define DCRN_PCIE2_BASE 0x140
+#define PCIE0 DCRN_PCIE0_BASE
+#define PCIE1 DCRN_PCIE1_BASE
+#define PCIE2 DCRN_PCIE2_BASE
+
+#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
+#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
+#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
+#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
+#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
+#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
+#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
+#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
+#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
+#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
+#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
+#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
+#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
+#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
+
+/*
+ * System DCRs (SDRs)
+ */
+#define PESDR0_PLLLCT1 0x03a0
+#define PESDR0_PLLLCT2 0x03a1
+#define PESDR0_PLLLCT3 0x03a2
+
+#define PESDR0_UTLSET1 0x0300
+#define PESDR0_UTLSET2 0x0301
+#define PESDR0_DLPSET 0x0302
+#define PESDR0_LOOP 0x0303
+#define PESDR0_RCSSET 0x0304
+#define PESDR0_RCSSTS 0x0305
+#define PESDR0_HSSL0SET1 0x0306
+#define PESDR0_HSSL0SET2 0x0307
+#define PESDR0_HSSL0STS 0x0308
+#define PESDR0_HSSL1SET1 0x0309
+#define PESDR0_HSSL1SET2 0x030a
+#define PESDR0_HSSL1STS 0x030b
+#define PESDR0_HSSL2SET1 0x030c
+#define PESDR0_HSSL2SET2 0x030d
+#define PESDR0_HSSL2STS 0x030e
+#define PESDR0_HSSL3SET1 0x030f
+#define PESDR0_HSSL3SET2 0x0310
+#define PESDR0_HSSL3STS 0x0311
+#define PESDR0_HSSL4SET1 0x0312
+#define PESDR0_HSSL4SET2 0x0313
+#define PESDR0_HSSL4STS 0x0314
+#define PESDR0_HSSL5SET1 0x0315
+#define PESDR0_HSSL5SET2 0x0316
+#define PESDR0_HSSL5STS 0x0317
+#define PESDR0_HSSL6SET1 0x0318
+#define PESDR0_HSSL6SET2 0x0319
+#define PESDR0_HSSL6STS 0x031a
+#define PESDR0_HSSL7SET1 0x031b
+#define PESDR0_HSSL7SET2 0x031c
+#define PESDR0_HSSL7STS 0x031d
+#define PESDR0_HSSCTLSET 0x031e
+#define PESDR0_LANE_ABCD 0x031f
+#define PESDR0_LANE_EFGH 0x0320
+
+#define PESDR1_UTLSET1 0x0340
+#define PESDR1_UTLSET2 0x0341
+#define PESDR1_DLPSET 0x0342
+#define PESDR1_LOOP 0x0343
+#define PESDR1_RCSSET 0x0344
+#define PESDR1_RCSSTS 0x0345
+#define PESDR1_HSSL0SET1 0x0346
+#define PESDR1_HSSL0SET2 0x0347
+#define PESDR1_HSSL0STS 0x0348
+#define PESDR1_HSSL1SET1 0x0349
+#define PESDR1_HSSL1SET2 0x034a
+#define PESDR1_HSSL1STS 0x034b
+#define PESDR1_HSSL2SET1 0x034c
+#define PESDR1_HSSL2SET2 0x034d
+#define PESDR1_HSSL2STS 0x034e
+#define PESDR1_HSSL3SET1 0x034f
+#define PESDR1_HSSL3SET2 0x0350
+#define PESDR1_HSSL3STS 0x0351
+#define PESDR1_HSSCTLSET 0x0352
+#define PESDR1_LANE_ABCD 0x0353
+
+#define PESDR2_UTLSET1 0x0370
+#define PESDR2_UTLSET2 0x0371
+#define PESDR2_DLPSET 0x0372
+#define PESDR2_LOOP 0x0373
+#define PESDR2_RCSSET 0x0374
+#define PESDR2_RCSSTS 0x0375
+#define PESDR2_HSSL0SET1 0x0376
+#define PESDR2_HSSL0SET2 0x0377
+#define PESDR2_HSSL0STS 0x0378
+#define PESDR2_HSSL1SET1 0x0379
+#define PESDR2_HSSL1SET2 0x037a
+#define PESDR2_HSSL1STS 0x037b
+#define PESDR2_HSSL2SET1 0x037c
+#define PESDR2_HSSL2SET2 0x037d
+#define PESDR2_HSSL2STS 0x037e
+#define PESDR2_HSSL3SET1 0x037f
+#define PESDR2_HSSL3SET2 0x0380
+#define PESDR2_HSSL3STS 0x0381
+#define PESDR2_HSSCTLSET 0x0382
+#define PESDR2_LANE_ABCD 0x0383
+
+/*
+ * UTL register offsets
+ */
+#define PEUTL_PBBSZ 0x20
+#define PEUTL_OPDBSZ 0x68
+#define PEUTL_IPHBSZ 0x70
+#define PEUTL_IPDBSZ 0x78
+#define PEUTL_OUTTR 0x90
+#define PEUTL_INTR 0x98
+#define PEUTL_PCTL 0xa0
+#define PEUTL_RCIRQEN 0xb8
+
+/*
+ * Config space register offsets
+ */
+#define PECFG_BAR0LMPA 0x210
+#define PECFG_BAR0HMPA 0x214
+#define PECFG_BAR1MPA 0x218
+#define PECFG_BAR2MPA 0x220
+
+#define PECFG_PIMEN 0x33c
+#define PECFG_PIM0LAL 0x340
+#define PECFG_PIM0LAH 0x344
+#define PECFG_PIM1LAL 0x348
+#define PECFG_PIM1LAH 0x34c
+#define PECFG_PIM01SAL 0x350
+#define PECFG_PIM01SAH 0x354
+
+#define PECFG_POM0LAL 0x380
+#define PECFG_POM0LAH 0x384
+
+#define SDR_READ(offset) ({\
+ mtdcr(DCRN_SDR0_CFGADDR, offset); \
+ mfdcr(DCRN_SDR0_CFGDATA);})
+
+#define SDR_WRITE(offset, data) ({\
+ mtdcr(DCRN_SDR0_CFGADDR, offset); \
+ mtdcr(DCRN_SDR0_CFGDATA,data);})
+
+int ppc440spe_init_pcie(void);
+int ppc440spe_init_pcie_rootport(int port);
+void yucca_setup_pcie_fpga_rootpoint(int port);
+void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port);
+int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port);
+int yucca_pcie_card_present(int port);
+int pcie_hose_scan(struct pci_controller *hose, int bus);
+#endif /* __440SPE_PCIE_H */
#define BI_PHYMODE_NONE 0
#define BI_PHYMODE_ZMII 1
#define BI_PHYMODE_RGMII 2
+#define BI_PHYMODE_GMII 3
+#define BI_PHYMODE_RTBI 4
+#define BI_PHYMODE_TBI 5
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define BI_PHYMODE_SMII 6
+#define BI_PHYMODE_MII 7
+#endif
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
+#endif
/*-----------------------------------------------------------------------------+
* Global variables. TX and RX descriptors and buffers.
{
EMAC_4XX_HW_PST hw_p = dev->priv;
uint32_t failsafe = 10000;
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
unsigned long mfr;
#endif
}
/* EMAC RESET */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
- mfr |= 0x08000000;
+ mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
mtsdr(sdr_mfr, mfr);
#endif
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
- mfr &= ~0x08000000;
+ mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
mtsdr(sdr_mfr, mfr);
#endif
out32 (RGMII_FER, rmiifer);
return ((int)pfc1);
-
}
#endif /* CONFIG_440_GX */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
+{
+ unsigned long zmiifer=0x0;
+
+ /*
+ * Right now only 2*RGMII is supported. Please extend when needed.
+ * sr - 2006-08-29
+ */
+ switch (1) {
+ case 0:
+ /* 1 x GMII port */
+ out32 (ZMII_FER, 0x00);
+ out32 (RGMII_FER, 0x00000037);
+ bis->bi_phymode[0] = BI_PHYMODE_GMII;
+ bis->bi_phymode[1] = BI_PHYMODE_NONE;
+ break;
+ case 1:
+ /* 2 x RGMII ports */
+ out32 (ZMII_FER, 0x00);
+ out32 (RGMII_FER, 0x00000055);
+ bis->bi_phymode[0] = BI_PHYMODE_RGMII;
+ bis->bi_phymode[1] = BI_PHYMODE_RGMII;
+ break;
+ case 2:
+ /* 2 x SMII ports */
+
+ break;
+ default:
+ break;
+ }
+
+ /* Ensure we setup mdio for this devnum and ONLY this devnum */
+ zmiifer = in32 (ZMII_FER);
+ zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
+ out32 (ZMII_FER, zmiifer);
+
+ return ((int)0x0);
+}
+#endif /* CONFIG_440EPX */
+
static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
{
int i, j;
unsigned mode_reg;
unsigned short devnum;
unsigned short reg_short;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
sys_info_t sysinfo;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
int ethgroup = -1;
#endif
#endif
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
unsigned long mfr;
#endif
return -1;
}
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info (&sysinfo);
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
-#elif defined(CONFIG_440GX)
+#elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
#elif defined(CONFIG_440GP)
/* set RMII mode */
__asm__ volatile ("eieio");
/* reset emac so we have access to the phy */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
- mfr |= 0x08000000;
+ mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
mtsdr(sdr_mfr, mfr);
#endif
udelay (1000);
failsafe--;
}
+ if (failsafe <= 0)
+ printf("\nProblem resetting EMAC!\n");
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
- mfr &= ~0x08000000;
+ mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
mtsdr(sdr_mfr, mfr);
#endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
* otherwise, just check the speeds & feeds
*/
if (hw_p->first_init == 0) {
+#if defined(CONFIG_88E1111_CLK_DELAY)
+ /*
+ * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs
+ * the "RGMII transmit timing control" and "RGMII receive
+ * timing control" bits set, so that Gbit communication works
+ * without problems.
+ * Also set the "Transmitter disable" to 1 to enable the
+ * transmitter.
+ * After setting these bits a soft-reset must occur for this
+ * change to become active.
+ */
+ miiphy_read (dev->name, reg, 0x14, ®_short);
+ reg_short |= (1 << 7) | (1 << 1) | (1 << 0);
+ miiphy_write (dev->name, reg, 0x14, reg_short);
+#endif
+#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */
+ miiphy_write (dev->name, reg, 0x14, 0x0ce3);
+ miiphy_write (dev->name, reg, 0x18, 0x4101);
+ miiphy_write (dev->name, reg, 0x09, 0x0e00);
+ miiphy_write (dev->name, reg, 0x04, 0x01e1);
+#endif
miiphy_reset (dev->name, reg);
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+
#if defined(CONFIG_CIS8201_PHY)
/*
* Cicada 8201 PHY needs to have an extended register whacked
* for RGMII mode.
*/
- if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
+ if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
#if defined(CONFIG_CIS8201_SHORT_ETCH)
miiphy_write (dev->name, reg, 23, 0x1300);
#else
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
-#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
+#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_mfr, reg);
if (speed == 100) {
reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
else if (speed == 100)
reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
- else
+ else if (speed == 10)
reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
-
+ else {
+ printf("Error in RGMII Speed\n");
+ return -1;
+ }
out32 (RGMII_SSR, reg);
}
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+ if (speed == 1000)
+ reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
+ else if (speed == 100)
+ reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
+ else if (speed == 10)
+ reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
+ else {
+ printf("Error in RGMII Speed\n");
+ return -1;
+ }
+ out32 (RGMII_SSR, reg);
+#endif
+
/* set the Mal configuration reg */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
#else
/* set speed */
if (speed == _1000BASET) {
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
unsigned long pfc1;
+
mfsdr (sdr_pfc1, pfc1);
pfc1 |= SDR0_PFC1_EM_1000;
mtsdr (sdr_pfc1, pfc1);
#define UIC0SR uic0sr
#endif
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define UICMSR_ETHX uic0msr
+#define UICSR_ETHX uic0sr
+#else
+#define UICMSR_ETHX uic1msr
+#define UICSR_ETHX uic1sr
+#endif
+
int enetInt (struct eth_device *dev)
{
int serviced;
unsigned long emac_isr = 0;
unsigned long mal_rx_eob;
unsigned long my_uic0msr, my_uic1msr;
+ unsigned long my_uicmsr_ethx;
#if defined(CONFIG_440GX)
unsigned long my_uic2msr;
#if defined(CONFIG_440GX)
my_uic2msr = mfdcr (uic2msr);
#endif
+ my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
+
if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
- && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
+ && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
+ && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
/* not for us */
return (rc);
}
mal_isr = mfdcr (malesr);
/* look for mal error */
if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
- mal_err (dev, mal_isr, my_uic0msr,
- MAL_UIC_DEF, MAL_UIC_ERR);
+ mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
serviced = 1;
rc = 0;
}
/* port by port dispatch of emac interrupts */
if (hw_p->devnum == 0) {
- if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
+ if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
- mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+ mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+ mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
return (rc); /* we had errors so get out */
}
}
#if !defined(CONFIG_440SP)
if (hw_p->devnum == 1) {
- if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
+ if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
- mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+ mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+ mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
return (rc); /* we had errors so get out */
}
}
mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
switch (hw_p->devnum) {
case 0:
- mtdcr (uic1sr, UIC_ETH0);
+ mtdcr (UICSR_ETHX, UIC_ETH0);
break;
case 1:
- mtdcr (uic1sr, UIC_ETH1);
+ mtdcr (UICSR_ETHX, UIC_ETH1);
break;
#if defined (CONFIG_440GX)
case 2:
if (0 == virgin) {
/* set the MAL IER ??? names may change with new spec ??? */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
mal_ier =
MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o resetvec.o kgdb.o
-AOBJS = dcr.o
-COBJS = 405gp_pci.o 4xx_enet.o \
+SOBJS = dcr.o
+COBJS = 405gp_pci.o 440spe_pcie.o 4xx_enet.o \
bedbug_405.o commproc.o \
cpu.o cpu_init.o i2c.o interrupts.o \
- miiphy.o sdram.o serial.o \
- spd_sdram.o speed.o traps.o \
- usb_ohci.o usbdev.o usb.o
+ miiphy.o ndfc.o sdram.o serial.o \
+ spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o usb.o
-OBJS = $(AOBJS) $(COBJS)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
-all: .depend $(START) $(LIB)
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
DECLARE_GLOBAL_DATA_PTR;
#endif
-
#if defined(CONFIG_440)
#define FREQ_EBC (sys_info.freqEPB)
#else
#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
#endif
-#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_405GP) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define PCI_ASYNC
return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
#endif
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
unsigned long val;
mfsdr(sdr_sdstp1, val);
return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
#endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
- defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
- defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long val;
mfsdr(sdr_sdstp1, val);
}
#endif
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define I2C_BOOTROM
{
#if defined(CONFIG_405EP)
return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
-#endif
-
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
- defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
- defined(CONFIG_440SPE)
+#else
unsigned long val;
mfsdr(sdr_sdcs, val);
return (val & SDR0_SDCS_SDD);
#endif
}
+
+#if defined(CONFIG_440GX)
+#define SDR0_PINSTP_SHIFT 29
+static char *bootstrap_str[] = {
+ "EBC (16 bits)",
+ "EBC (8 bits)",
+ "EBC (32 bits)",
+ "EBC (8 bits)",
+ "PCI",
+ "I2C (Addr 0x54)",
+ "Reserved",
+ "I2C (Addr 0x50)",
+};
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define SDR0_PINSTP_SHIFT 30
+static char *bootstrap_str[] = {
+ "EBC (8 bits)",
+ "PCI",
+ "I2C (Addr 0x54)",
+ "I2C (Addr 0x50)",
+};
+#endif
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define SDR0_PINSTP_SHIFT 29
+static char *bootstrap_str[] = {
+ "EBC (8 bits)",
+ "PCI",
+ "NAND (8 bits)",
+ "EBC (16 bits)",
+ "EBC (16 bits)",
+ "I2C (Addr 0x54)",
+ "PCI",
+ "I2C (Addr 0x52)",
+};
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_PINSTP_SHIFT 29
+static char *bootstrap_str[] = {
+ "EBC (8 bits)",
+ "EBC (16 bits)",
+ "EBC (16 bits)",
+ "NAND (8 bits)",
+ "PCI",
+ "I2C (Addr 0x54)",
+ "PCI",
+ "I2C (Addr 0x52)",
+};
+#endif
+
+#if defined(SDR0_PINSTP_SHIFT)
+static int bootstrap_option(void)
+{
+ unsigned long val;
+
+ mfsdr(sdr_pinstp, val);
+ return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
+}
+#endif /* SDR0_PINSTP_SHIFT */
#endif
char buf[32];
#if !defined(CONFIG_IOP480)
+ char addstr[64] = "";
sys_info_t sys_info;
puts ("CPU: ");
#endif /* CONFIG_440GR */
#endif /* CONFIG_440 */
+ case PVR_440EPX1_RA:
+ puts("EPx Rev. A");
+ strcpy(addstr, "Security/Kasumi support");
+ break;
+
+ case PVR_440EPX2_RA:
+ puts("EPx Rev. A");
+ strcpy(addstr, "No Security/Kasumi support");
+ break;
+
+ case PVR_440GRX1_RA:
+ puts("GRx Rev. A");
+ strcpy(addstr, "Security/Kasumi support");
+ break;
+
+ case PVR_440GRX2_RA:
+ puts("GRx Rev. A");
+ strcpy(addstr, "No Security/Kasumi support");
+ break;
+
case PVR_440SP_RA:
puts("SP Rev. A");
break;
sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
FREQ_EBC / 1000000);
+ if (addstr[0] != 0)
+ printf(" %s\n", addstr);
+
#if defined(I2C_BOOTROM)
printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
-#endif
+#if defined(SDR0_PINSTP_SHIFT)
+ printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
+ printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
+#endif /* SDR0_PINSTP_SHIFT */
+#endif /* I2C_BOOTROM */
#if defined(CONFIG_PCI)
printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
return 0;
}
+#if defined (CONFIG_440SPE)
+int ppc440spe_revB() {
+ unsigned int pvr;
+
+ pvr = get_pvr();
+ if (pvr == PVR_440SPe_RB)
+ return 1;
+ else
+ return 0;
+}
+#endif
/* ------------------------------------------------------------------------- */
/*
* GPIO0 setup (select GPIO or alternate function)
*/
- out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
+#if defined(CFG_GPIO0_OR)
+ out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
+#endif
+#if defined(CFG_GPIO0_ODR)
+ out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
+#endif
+ out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
- out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
+ out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
- out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
+ out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
- out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
+ out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
/*
* Set EMAC noise filter bits
void uic1_interrupt( void * parms); /* UIC1 handler */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
static struct irq_action irq_vecs2[32]; /* For UIC2 */
void uic2_interrupt( void * parms); /* UIC2 handler */
#endif /* CONFIG_440GX CONFIG_440SPE */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
static struct irq_action irq_vecs3[32]; /* For UIC3 */
void uic3_interrupt( void * parms); /* UIC3 handler */
#endif /* CONFIG_440SPE */
irq_vecs1[vec].handler = NULL;
irq_vecs1[vec].arg = NULL;
irq_vecs1[vec].count = 0;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
irq_vecs2[vec].handler = NULL;
irq_vecs2[vec].arg = NULL;
irq_vecs2[vec].count = 0;
#endif /* CONFIG_440GX */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
irq_vecs3[vec].handler = NULL;
irq_vecs3[vec].arg = NULL;
irq_vecs3[vec].count = 0;
} /* external_interrupt CONFIG_440GX */
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+void external_interrupt(struct pt_regs *regs)
+{
+ ulong uic_msr;
+
+ /*
+ * Read masked interrupt status register to determine interrupt source
+ */
+ /* 440 SPe uses base uic register */
+ uic_msr = mfdcr(uic0msr);
+
+ if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
+ uic1_interrupt(0);
+
+ if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
+ uic2_interrupt(0);
+
+ if (uic_msr & ~(UICB0_ALL))
+ uic0_interrupt(0);
+
+ mtdcr(uic0sr, uic_msr);
+
+ return;
+
+} /* external_interrupt CONFIG_440EPX & CONFIG_440GRX */
+
#elif defined(CONFIG_440SPE)
void external_interrupt(struct pt_regs *regs)
{
}
#endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* Handler for UIC0 interrupt */
void uic0_interrupt( void * parms)
{
}
#endif /* defined(CONFIG_440) */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* Handler for UIC2 interrupt */
void uic2_interrupt( void * parms)
{
int i = vec;
#if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64)) {
i = vec - 32;
irqa = irq_vecs1;
irqa[i].arg = arg;
#if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
else if (vec > 63)
int i = vec;
#if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64)) {
irqa = irq_vecs1;
i = vec - 32;
#endif
#if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
else if (vec > 63)
printf("\n");
#endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
printf ("\nUIC 2\n");
printf ("Nr Routine Arg Count\n");
}
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
#else
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
#endif
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
+ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
sta_reg = sta_reg | (addr << 5); /* Phy address */
sta_reg = 0;
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
#else
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
#endif
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
+ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
#endif
sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */
--- /dev/null
+/*
+ * Overview:
+ * Platform independend driver for NDFC (NanD Flash Controller)
+ * integrated into EP440 cores
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Based on original work by
+ * Thomas Gleixner
+ * Copyright 2006 IBM
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \
+ (defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
+
+#include <nand.h>
+#include <linux/mtd/ndfc.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+
+static u8 hwctl = 0;
+
+static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+ switch (cmd) {
+ case NAND_CTL_SETCLE:
+ hwctl |= 0x1;
+ break;
+
+ case NAND_CTL_CLRCLE:
+ hwctl &= ~0x1;
+ break;
+
+ case NAND_CTL_SETALE:
+ hwctl |= 0x2;
+ break;
+
+ case NAND_CTL_CLRALE:
+ hwctl &= ~0x2;
+ break;
+ }
+}
+
+static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
+
+ if (hwctl & 0x1)
+ out8(base + NDFC_CMD, byte);
+ else if (hwctl & 0x2)
+ out8(base + NDFC_ALE, byte);
+ else
+ out8(base + NDFC_DATA, byte);
+}
+
+static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
+
+ return (in8(base + NDFC_DATA));
+}
+
+static int ndfc_dev_ready(struct mtd_info *mtdinfo)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
+
+ while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
+ ;
+
+ return 1;
+}
+
+#ifndef CONFIG_NAND_SPL
+/*
+ * Don't use these speedup functions in NAND boot image, since the image
+ * has to fit into 4kByte.
+ */
+
+/*
+ * Speedups for buffer read/write/verify
+ *
+ * NDFC allows 32bit read/write of data. So we can speed up the buffer
+ * functions. No further checking, as nand_base will always read/write
+ * page aligned.
+ */
+static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
+ uint32_t *p = (uint32_t *) buf;
+
+ for (;len > 0; len -= 4)
+ *p++ = in32(base + NDFC_DATA);
+}
+
+static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
+ uint32_t *p = (uint32_t *) buf;
+
+ for (; len > 0; len -= 4)
+ out32(base + NDFC_DATA, *p++);
+}
+
+static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
+ uint32_t *p = (uint32_t *) buf;
+
+ for (; len > 0; len -= 4)
+ if (*p++ != in32(base + NDFC_DATA))
+ return -1;
+
+ return 0;
+}
+#endif /* #ifndef CONFIG_NAND_SPL */
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+ /*
+ * Don't use "chip" to address the NAND device,
+ * generate the cs from the address where it is encoded.
+ */
+ int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
+ ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
+
+ /* Set NandFlash Core Configuration Register */
+ /* 1col x 2 rows */
+ out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
+}
+
+void board_nand_init(struct nand_chip *nand)
+{
+ int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
+ ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
+
+ nand->eccmode = NAND_ECC_SOFT;
+
+ nand->hwcontrol = ndfc_hwcontrol;
+ nand->read_byte = ndfc_read_byte;
+ nand->write_byte = ndfc_write_byte;
+ nand->dev_ready = ndfc_dev_ready;
+
+#ifndef CONFIG_NAND_SPL
+ nand->write_buf = ndfc_write_buf;
+ nand->read_buf = ndfc_read_buf;
+ nand->verify_buf = ndfc_verify_buf;
+#else
+ /*
+ * Setup EBC (CS0 only right now)
+ */
+ mtdcr(ebccfga, xbcfg);
+ mtdcr(ebccfgd, 0xb8400000);
+
+ mtebc(pb0cr, CFG_EBC_PB0CR);
+ mtebc(pb0ap, CFG_EBC_PB0AP);
+#endif
+
+ /*
+ * Select required NAND chip in NDFC
+ */
+ board_nand_select_device(nand, cs);
+ out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222);
+}
+
+#endif
#endif /* CONFIG_IOP480 */
/*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
+ defined(CONFIG_440)
#if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
#else
#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
#endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define CR0_MASK 0xdfffffff
-#define CR0_EXTCLK_ENA 0x00800000
-#define CR0_UDIV_POS 0
-#else
+#if defined(CONFIG_440GP)
#define CR0_MASK 0x3fff0000
#define CR0_EXTCLK_ENA 0x00600000
#define CR0_UDIV_POS 16
-#endif /* CONFIG_440GX */
+#define UDIV_SUBTRACT 1
+#define UART0_SDR cntrl0
+#define MFREG(a, d) d = mfdcr(a)
+#define MTREG(a, d) mtdcr(a, d)
+#else /* #if defined(CONFIG_440GP) */
+/* all other 440 PPC's access clock divider via sdr register */
+#define CR0_MASK 0xdfffffff
+#define CR0_EXTCLK_ENA 0x00800000
+#define CR0_UDIV_POS 0
+#define UDIV_SUBTRACT 0
+#define UART0_SDR sdr_uart0
+#define UART1_SDR sdr_uart1
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPe)
+#define UART2_SDR sdr_uart2
+#endif
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRx)
+#define UART3_SDR sdr_uart3
+#endif
+#define MFREG(a, d) mfsdr(a, d)
+#define MTREG(a, d) mtsdr(a, d)
+#endif /* #if defined(CONFIG_440GP) */
#elif defined(CONFIG_405EP)
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
#if defined(CONFIG_UART1_CONSOLE)
#define ACTING_UART0_BASE UART1_BASE
#define ACTING_UART1_BASE UART0_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
- defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
- defined(CONFIG_440SPE)
-#define UART0_SDR sdr_uart1
-#define UART1_SDR sdr_uart0
-#endif /* CONFIG_440GX */
#else
#define ACTING_UART0_BASE UART0_BASE
#define ACTING_UART1_BASE UART1_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
- defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
- defined(CONFIG_440SPE)
-#define UART0_SDR sdr_uart0
-#define UART1_SDR sdr_uart1
-#endif /* CONFIG_440GX */
+#endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+#define UART_BASE dev_base
+#else
+#define UART_BASE ACTING_UART0_BASE
#endif
#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
*pbdiv = div/udiv;
}
-#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
+#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
/*
* Minimal serial functions needed to use one of the SMC ports
unsigned long tmp;
#endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
- defined(CONFIG_440SPE)
-#if defined(CONFIG_SERIAL_MULTI)
- if (UART0_BASE == dev_base) {
- mfsdr(UART0_SDR,reg);
- reg &= ~CR0_MASK;
- } else {
- mfsdr(UART1_SDR,reg);
- reg &= ~CR0_MASK;
- }
-#else
- mfsdr(UART0_SDR,reg);
+ MFREG(UART0_SDR, reg);
reg &= ~CR0_MASK;
-#endif
-#else
- reg = mfdcr(cntrl0) & ~CR0_MASK;
-#endif /* CONFIG_440GX */
+
#ifdef CFG_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
- defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
- defined(CONFIG_440SPE)
- reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
-#if defined(CONFIG_SERIAL_MULTI)
- if (UART0_BASE == dev_base) {
- mtsdr (UART0_SDR,reg);
- } else {
- mtsdr (UART1_SDR,reg);
- }
-#else
- mtsdr (UART0_SDR,reg);
+ reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
+
+ /*
+ * Configure input clock to baudrate generator for all
+ * available serial ports here
+ */
+ MTREG(UART0_SDR, reg);
+#if defined(UART1_SDR)
+ MTREG(UART1_SDR, reg);
#endif
-#else
- reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
- mtdcr (cntrl0, reg);
+#if defined(UART2_SDR)
+ MTREG(UART2_SDR, reg);
#endif
-
-#if defined(CONFIG_SERIAL_MULTI)
- out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
- out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
- out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
- out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
- out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
- out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in8 (dev_base + UART_LSR); /* clear line status */
- val = in8 (dev_base + UART_RBR); /* read receive buffer */
- out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
- out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
-#else
- out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
- out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
- out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
- out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
- out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
- out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
- val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
- out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
- out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
+#if defined(UART3_SDR)
+ MTREG(UART3_SDR, reg);
#endif
+
+ out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
+ out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
+ out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */
+ out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
+ out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */
+ out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
+ val = in8(UART_BASE + UART_LSR); /* clear line status */
+ val = in8(UART_BASE + UART_RBR); /* read receive buffer */
+ out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */
+ out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */
+
return (0);
}
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
-#if defined(CONFIG_SERIAL_MULTI)
- out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
- out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
- out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
- out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
- out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
- out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in8 (dev_base + UART_LSR); /* clear line status */
- val = in8 (dev_base + UART_RBR); /* read receive buffer */
- out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
- out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
-#else
- out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
- out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
- out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
- out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
- out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
- out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
- val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
- out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
- out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
-#endif
+ out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
+ out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
+ out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */
+ out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
+ out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */
+ out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
+ val = in8(UART_BASE + UART_LSR); /* clear line status */
+ val = in8(UART_BASE + UART_RBR); /* read receive buffer */
+ out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */
+ out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */
+
return (0);
}
void serial_setbrg (void)
#endif
{
- unsigned long tmp;
- unsigned long clk;
- unsigned long udiv;
- unsigned short bdiv;
-
-#ifdef CFG_EXT_SERIAL_CLOCK
- clk = CFG_EXT_SERIAL_CLOCK;
-#else
- clk = gd->cpu_clk;
-#endif
-
-#ifdef CONFIG_405EP
- udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
-#else
- udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
-#endif /* CONFIG_405EP */
-
-#if !defined(CFG_EXT_SERIAL_CLOCK) && \
- ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
- defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
- defined(CONFIG_440SPE) )
- serial_divs (gd->baudrate, &udiv, &bdiv);
- tmp = udiv << CR0_UDIV_POS; /* set the UART divisor */
-#if defined(CONFIG_SERIAL_MULTI)
- if (UART0_BASE == dev_base) {
- mtsdr (UART0_SDR, tmp);
- } else {
- mtsdr (UART1_SDR, tmp);
- }
-#else
- mtsdr (UART0_SDR, tmp);
-#endif
-
-#else
-
- tmp = gd->baudrate * udiv * 16;
- bdiv = (clk + tmp / 2) / tmp;
-#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
-
#if defined(CONFIG_SERIAL_MULTI)
- out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
- out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
- out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
- out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
+ serial_init_dev(dev_base);
#else
- out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
- out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
- out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
- out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
+ serial_init();
#endif
}
/* check THRE bit, wait for transmiter available */
for (i = 1; i < 3500; i++) {
-#if defined(CONFIG_SERIAL_MULTI)
- if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
-#else
- if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
-#endif
+ if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20)
break;
udelay (100);
}
-#if defined(CONFIG_SERIAL_MULTI)
- out8 (dev_base + UART_THR, c); /* put character out */
-#else
- out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
-#endif
+ out8 (UART_BASE + UART_THR, c); /* put character out */
}
#if defined(CONFIG_SERIAL_MULTI)
#if defined(CONFIG_HW_WATCHDOG)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
#endif /* CONFIG_HW_WATCHDOG */
-#if defined(CONFIG_SERIAL_MULTI)
- status = in8 (dev_base + UART_LSR);
-#else
- status = in8 (ACTING_UART0_BASE + UART_LSR);
-#endif
+ status = in8 (UART_BASE + UART_LSR);
if ((status & asyncLSRDataReady1) != 0x0) {
break;
}
asyncLSROverrunError1 |
asyncLSRParityError1 |
asyncLSRBreakInterrupt1 )) != 0) {
-#if defined(CONFIG_SERIAL_MULTI)
- out8 (dev_base + UART_LSR,
-#else
- out8 (ACTING_UART0_BASE + UART_LSR,
-#endif
+ out8 (UART_BASE + UART_LSR,
asyncLSRFramingError1 |
asyncLSROverrunError1 |
asyncLSRParityError1 |
asyncLSRBreakInterrupt1);
}
}
-#if defined(CONFIG_SERIAL_MULTI)
- return (0x000000ff & (int) in8 (dev_base));
-#else
- return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
-#endif
+ return (0x000000ff & (int) in8 (UART_BASE));
}
#if defined(CONFIG_SERIAL_MULTI)
{
unsigned char status;
-#if defined(CONFIG_SERIAL_MULTI)
- status = in8 (dev_base + UART_LSR);
-#else
- status = in8 (ACTING_UART0_BASE + UART_LSR);
-#endif
+ status = in8 (UART_BASE + UART_LSR);
if ((status & asyncLSRDataReady1) != 0x0) {
return (1);
}
asyncLSROverrunError1 |
asyncLSRParityError1 |
asyncLSRBreakInterrupt1 )) != 0) {
-#if defined(CONFIG_SERIAL_MULTI)
- out8 (dev_base + UART_LSR,
-#else
- out8 (ACTING_UART0_BASE + UART_LSR,
-#endif
+ out8 (UART_BASE + UART_LSR,
asyncLSRFramingError1 |
asyncLSROverrunError1 |
asyncLSRParityError1 |
#elif defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
void get_sys_info (sys_info_t *sysInfo)
{
unsigned long temp;
.extern ext_bus_cntlr_init
.extern sdram_init
+#ifdef CONFIG_NAND_U_BOOT
+ .extern reconfig_tlb0
+#endif
/*
* Set up GOT: Global Offset Table
*
* Use r14 to access the GOT
*/
+#if !defined(CONFIG_NAND_SPL)
START_GOT
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(_end)
GOT_ENTRY(__bss_start)
END_GOT
+#endif /* CONFIG_NAND_SPL */
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+ /*
+ * NAND U-Boot image is started from offset 0
+ */
+ .text
+ bl reconfig_tlb0
+ GET_GOT
+ bl cpu_init_f /* run low-level CPU init code (from Flash) */
+ bl board_init_f
+#endif
/*
* 440 Startup -- on reset only the top 4k of the effective
*/
#if defined(CONFIG_440)
+#if !defined(CONFIG_NAND_SPL)
.section .bootpg,"ax"
+#endif
.globl _start_440
/**************************************************************************/
_start_440:
+ /*--------------------------------------------------------------------+
+ | 440EPX BUP Change - Hardware team request
+ +--------------------------------------------------------------------*/
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+ sync
+ nop
+ nop
+#endif
/*----------------------------------------------------------------+
| Core bug fix. Clear the esr
+-----------------------------------------------------------------*/
mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* NOTE: 440GX adds machine check status regs */
+ /* NOTE: 440GX adds machine check status regs */
+#if defined(CONFIG_440) && !defined(CONFIG_440GP)
mtspr mcsrr0,r0
mtspr mcsrr1,r0
- mfspr r1, mcsr
+ mfspr r1,mcsr
mtspr mcsr,r1
#endif
+
+ /*----------------------------------------------------------------*/
+ /* CCR0 init */
+ /*----------------------------------------------------------------*/
+ /* Disable store gathering & broadcast, guarantee inst/data
+ * cache block touch, force load/store alignment
+ * (see errata 1.12: 440_33)
+ */
+ lis r1,0x0030 /* store gathering & broadcast disable */
+ ori r1,r1,0x6000 /* cache touch */
+ mtspr ccr0,r1
+
/*----------------------------------------------------------------*/
/* Initialize debug */
/*----------------------------------------------------------------*/
+ mfspr r1,dbcr0
+ andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
+ bne skip_debug_init /* if set, don't clear debug register */
mtspr dbcr0,r0
mtspr dbcr1,r0
mtspr dbcr2,r0
mfspr r1,dbsr
mtspr dbsr,r1 /* Clear all valid bits */
-
- /*----------------------------------------------------------------*/
- /* CCR0 init */
- /*----------------------------------------------------------------*/
- /* Disable store gathering & broadcast, guarantee inst/data
- * cache block touch, force load/store alignment
- * (see errata 1.12: 440_33)
- */
- lis r1,0x0030 /* store gathering & broadcast disable */
- ori r1,r1,0x6000 /* cache touch */
- mtspr ccr0,r1
+skip_debug_init:
#if defined (CONFIG_440SPE)
/*----------------------------------------------------------------+
/*----------------------------------------------------------------*/
/* TLB entry setup -- step thru tlbtab */
/*----------------------------------------------------------------*/
+#if defined(CONFIG_440SPE)
+ /*----------------------------------------------------------------*/
+ /* We have different TLB tables for revA and rev B of 440SPe */
+ /*----------------------------------------------------------------*/
+ mfspr r1, PVR
+ lis r0,0x5342
+ ori r0,r0,0x1891
+ cmpw r7,r1,r0
+ bne r7,..revA
+ bl tlbtabB
+ b ..goon
+..revA:
+ bl tlbtabA
+..goon:
+#else
bl tlbtab /* Get tlbtab pointer */
+#endif
mr r5,r0
li r1,0x003f /* 64 TLB entries max */
mtctr r1
/*----------------------------------------------------------------*/
/* Continue from 'normal' start */
/*----------------------------------------------------------------*/
-2: bl 3f
+2:
+
+#if defined(CONFIG_NAND_SPL)
+ /*
+ * Enable internal SRAM
+ */
+ lis r2,0x7fff
+ ori r2,r2,0xffff
+ mfdcr r1,isram0_dpc
+ and r1,r1,r2 /* Disable parity check */
+ mtdcr isram0_dpc,r1
+ mfdcr r1,isram0_pmeg
+ and r1,r1,r2 /* Disable pwr mgmt */
+ mtdcr isram0_pmeg,r1
+
+ /*
+ * Copy SPL from cache into internal SRAM
+ */
+ li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
+ mtctr r4
+ lis r2,CFG_NAND_BOOT_SPL_SRC@h
+ ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
+ lis r3,CFG_NAND_BOOT_SPL_DST@h
+ ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
+spl_loop:
+ lwzu r4,4(r2)
+ stwu r4,4(r3)
+ bdnz spl_loop
+
+ /*
+ * Jump to code in RAM
+ */
+ bl 00f
+00: mflr r10
+ lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
+ ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
+ sub r10,r10,r3
+ addi r10,r10,28
+ mtlr r10
+ blr
+
+start_ram:
+ sync
+ isync
+#endif
+
+ bl 3f
b _start
3: li r0,0
* r3 - 1st arg to board_init(): IMMP pointer
* r4 - 2nd arg to board_init(): boot flag
*/
+#ifndef CONFIG_NAND_SPL
.text
.long 0x27051956 /* U-Boot Magic Number */
.globl version_string
* location (0x100) is where the CriticalInput Execption should be.
*/
. = EXC_OFF_SYS_RESET
+#endif
.globl _start
_start:
/* Setup the internal SRAM */
/*----------------------------------------------------------------*/
li r0,0
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+#ifdef CFG_INIT_RAM_DCACHE
/* Clear Dcache to use as RAM */
addis r3,r0,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
dcbz r0,r3
addi r3,r3,32
bdnz ..d_ag
-#else
-#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#endif /* CFG_INIT_RAM_DCACHE */
+
+ /* 440EP & 440GR are only 440er PPC's without internal SRAM */
+#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
+ /* not all PPC's have internal SRAM usable as L2-cache */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
- mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
- li r2,0x7fff
+ lis r2,0x7fff
ori r2,r2,0xffff
mfdcr r1,isram0_dpc
and r1,r1,r2 /* Disable parity check */
mtdcr isram0_dpc,r1
mfdcr r1,isram0_pmeg
- andis. r1,r1,r2 /* Disable pwr mgmt */
+ and r1,r1,r2 /* Disable pwr mgmt */
mtdcr isram0_pmeg,r1
lis r1,0x8000 /* BAS = 8000_0000 */
lis r1, 0x0003
ori r1,r1, 0x0984 /* fourth 64k */
mtdcr isram0_sb3cr,r1
-#else
+#elif defined(CONFIG_440GP)
ori r1,r1,0x0380 /* 8k rw */
mtdcr isram0_sb0cr,r1
+ mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
#endif
-#endif
+#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
/*----------------------------------------------------------------*/
/* Setup the stack in internal SRAM */
stwu r1,-8(r1) /* Save back chain and move SP */
stw r0,+12(r1) /* Save return addr (underflow vect) */
+#ifdef CONFIG_NAND_SPL
+ bl nand_boot /* will not return */
+#else
GET_GOT
bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
+#endif
#endif /* CONFIG_440 */
/*----------------------------------------------------------------------- */
+#ifndef CONFIG_NAND_SPL
/*****************************************************************************/
.globl _start_of_vectors
_start_of_vectors:
lwz r1,GPR1(r1)
SYNC
rfci
+#endif /* CONFIG_NAND_SPL */
/* Cache functions.
*/
/*------------------------------------------------------------------------------*/
+#ifndef CONFIG_NAND_SPL
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
*/
.globl relocate_code
relocate_code:
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SPE)
/*
* On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
* to speed up the boot process. Now this cache needs to be disabled.
cmplw 0, r7, r8
blt 4b
-#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE)
+#if !defined(CONFIG_440)
addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
mtmsr r7 /* change MSR */
#else
- bl __440gx_msr_set
- b __440gx_msr_continue
+ bl __440_msr_set
+ b __440_msr_continue
-__440gx_msr_set:
+__440_msr_set:
addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
mtspr srr1,r7
mflr r7
mtspr srr0,r7
rfi
-__440gx_msr_continue:
+__440_msr_continue:
#endif
mtlr r4 /* restore link register */
stw r0, 4(r7)
blr
+#endif /* CONFIG_NAND_SPL */
/**************************************************************************/
mtdcr ebccfgd,r3
#endif
- addi r3,0,CPC0_PCI_HOST_CFG_EN
+#ifndef CFG_CPC0_PCI
+ li r3,CPC0_PCI_HOST_CFG_EN
#ifdef CONFIG_BUBINGA
/*
!-----------------------------------------------------------------------
beq ..pci_cfg_set /* if not set, then bypass reg write*/
#endif
ori r3,r3,CPC0_PCI_ARBIT_EN
+#else /* CFG_CPC0_PCI */
+ li r3,CFG_CPC0_PCI
+#endif /* CFG_CPC0_PCI */
..pci_cfg_set:
mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
#define m16_swap(x) swap_16(x)
#define m32_swap(x) swap_32(x)
-#ifdef CONFIG_440EP
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
#define ohci_cpu_to_le16(x) (x)
#define ohci_cpu_to_le32(x) (x)
#else
gohci.disabled = 1;
gohci.sleeping = 0;
gohci.irq = -1;
- gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
+#if defined(CONFIG_440EP)
+ gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
+#elif defined(CONFIG_440EPX)
+ gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
+#endif
gohci.flags = 0;
gohci.slot_name = "ppc440";
#include <common.h>
#include <asm/processor.h>
-#ifdef CONFIG_440EP
+#if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && (CONFIG_COMMANDS & CFG_CMD_USB)
#include <usb.h>
#include "usbdev.h"
return 0;
}
+#if defined(CONFIG_440EPX)
+void usb_dev_init()
+{
+ printf("USB 2.0 Device init\n");
+
+ /*usb dev init */
+ *(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */
+
+ /*enable interrupts */
+ *(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f;
+
+ irq_install_handler(VECNUM_HSB2D, (interrupt_handler_t *) usbInt,
+ NULL);
+}
+#else
void usb_dev_init()
{
#ifdef USB_2_0_DEVICE
irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt,
NULL);
}
+#endif
-#endif /*CONFIG_440EP */
+#endif /* CONFIG_440EP || CONFIG_440EPX */
#ifndef _VECNUMS_H_
#define _VECNUMS_H_
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+/* UIC 0 */
+#define VECNUM_U0 0 /* UART 0 */
+#define VECNUM_U1 1 /* UART 1 */
+#define VECNUM_IIC0 2 /* IIC */
+#define VECNUM_KRD 3 /* Kasumi Ready for data */
+#define VECNUM_KDA 4 /* Kasumi Data Available */
+#define VECNUM_PCRW 5 /* PCI command register write */
+#define VECNUM_PPM 6 /* PCI power management */
+#define VECNUM_IIC1 7 /* IIC */
+#define VECNUM_SPI 8 /* SPI */
+#define VECNUM_EPCISER 9 /* External PCI SERR */
+#define VECNUM_MTE 10 /* MAL TXEOB */
+#define VECNUM_MRE 11 /* MAL RXEOB */
+#define VECNUM_D0 12 /* DMA channel 0 */
+#define VECNUM_D1 13 /* DMA channel 1 */
+#define VECNUM_D2 14 /* DMA channel 2 */
+#define VECNUM_D3 15 /* DMA channel 3 */
+#define VECNUM_UD0 16 /* UDMA irq 0 */
+#define VECNUM_UD1 17 /* UDMA irq 1 */
+#define VECNUM_UD2 18 /* UDMA irq 2 */
+#define VECNUM_UD3 19 /* UDMA irq 3 */
+#define VECNUM_HSB2D 20 /* USB2.0 Device */
+#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */
+#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */
+#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */
+#define VECNUM_EIP94 23 /* Security EIP94 */
+#define VECNUM_ETH0 24 /* Emac 0 */
+#define VECNUM_ETH1 25 /* Emac 1 */
+#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */
+#define VECNUM_EIR4 27 /* External interrupt 4 */
+#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */
+#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */
+#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
+#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
+
+/* UIC 1 */
+#define VECNUM_MS (32 + 0) /* MAL SERR */
+#define VECNUM_MTDE (32 + 1) /* MAL TXDE */
+#define VECNUM_MRDE (32 + 2) /* MAL RXDE */
+#define VECNUM_U2 (32 + 3) /* UART 2 */
+#define VECNUM_U3 (32 + 4) /* UART 3 */
+#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */
+#define VECNUM_NDFC (32 + 6) /* NDFC */
+#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */
+#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */
+#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */
+#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */
+#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */
+#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */
+#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */
+#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */
+#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */
+#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */
+#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */
+#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */
+#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */
+#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */
+#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */
+#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */
+#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */
+#define VECNUM_SRE (32 + 24) /* Serial ROM error */
+#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */
+#define VECNUM_RSVD0 (32 + 26) /* Reserved */
+#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */
+#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */
+#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
+#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */
+#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */
+
+#define VECNUM_TXDE VECNUM_MTDE
+#define VECNUM_RXDE VECNUM_MRDE
+
+/* UIC 2 */
+#define VECNUM_EIR5 (62 + 0) /* External interrupt 5 */
+#define VECNUM_EIR6 (62 + 1) /* External interrupt 6 */
+#define VECNUM_OPB (62 + 2) /* OPB to PLB bridge int stat */
+#define VECNUM_EIR2 (62 + 3) /* External interrupt 2 */
+#define VECNUM_EIR3 (62 + 4) /* External interrupt 3 */
+#define VECNUM_DDR2 (62 + 5) /* DDR2 sdram */
+#define VECNUM_MCTX0 (62 + 6) /* MAl intp coalescence TX0 */
+#define VECNUM_MCTX1 (62 + 7) /* MAl intp coalescence TX1 */
+#define VECNUM_MCTR0 (62 + 8) /* MAl intp coalescence TR0 */
+#define VECNUM_MCTR1 (62 + 9) /* MAl intp coalescence TR1 */
+
+#elif defined(CONFIG_440SPE)
+
/* UIC 0 */
#define VECNUM_U0 0 /* UART0 */
#define VECNUM_U1 1 /* UART1 */
#
-# (C) Copyright 2000, 2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o usb.o
+COBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o usb.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = serial.o interrupts.o cpu.o
+COBJS = serial.o interrupts.o cpu.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o
-OBJS = serial.o interrupts.o cpu.o
+COBJS = serial.o interrupts.o cpu.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#CFLAGS += -DET_DEBUG -DDEBUG
-LIB = libdisk.a
+LIB = $(obj)libdisk.a
-OBJS = part.o part_mac.o part_dos.o part_iso.o part_amiga.o
+COBJS = part.o part_mac.o part_dos.o part_iso.o part_amiga.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
-$(LIB): $(START) $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
--- /dev/null
+From: Haavard Skinnemoen <hskinnemoen@atmel.com>
+Date: Wed, 30 Aug 2006 17:01:46 +0200
+Subject: [PATCH] AVR32 architecture support
+
+This patch adds common infrastructure code for the Atmel AVR32
+architecture.
+
+AVR32 is a new high-performance 32-bit RISC microprocessor core,
+designed for cost-sensitive embedded applications, with particular
+emphasis on low power consumption and high code density. The AVR32
+architecture is not binary compatible with earlier 8-bit AVR
+architectures.
+
+The AVR32 architecture, including the instruction set, is described
+by the AVR32 Architecture Manual, available from
+
+http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf
+
+A GNU toolchain with support for AVR32 is included with the ATSTK1000
+BSP, which can be downloaded as an ISO image from
+
+http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918
+
+Alternatively, you can build it yourself by following the
+Getting Started guide at avr32linux.org, which also provides links
+to the necessary sources and patches you need to download:
+
+http://avr32linux.org/twiki/bin/view/Main/GettingStarted
+
+The AVR32 ports of u-boot, the Linux kernel, the GNU toolchain and
+other associated software are actively supported by Atmel Corporation.
+
+Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk
SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
+ In order to use PCI-X (only in the first PCI slot. The one with
+ the RIO connector), you need to set SW1[4] (config) to 1 (off).
+ Also, configure the board to run PCI at 66 MHz.
2. MEMORY MAP TO WORK WITH LINUX KERNEL
--- /dev/null
+Freescale MPC8641HPCN board
+===========================
+
+Created 05/24/2006 Haiying Wang
+-------------------------------
+
+1. Building U-Boot
+------------------
+The 86xx HPCN code base is known to compile using:
+ Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
+
+ $ make MPC8641HPCN_config
+ Configuring for MPC8641HPCN board...
+
+ $ make
+
+
+2. Switch and Jumper Setting
+----------------------------
+Jumpers:
+ J14 Pins 1-2 (near plcc32 socket)
+
+Switches:
+ SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1
+ 01100 :: CORE = 2.5:1
+ 10000 :: CORE = 3:1
+ 11100 :: CORE = 3.5:1
+ 10100 :: CORE = 4:1
+ 01110 :: CORE = 4.5:1
+ SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz
+ 001 :: SYSCLK = 40MHz
+
+ SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X
+ 0100 :: 4X
+ 0110 :: 6X
+ 1000 :: 8X
+ 1010 :: 10X
+ 1100 :: 12X
+ 1110 :: 14X
+ 0000 :: 16X
+ SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus
+
+ SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V
+ 0100000 :: VCORE = 1.11V
+ SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
+ 1 :: VCC_PLAT = 1.0V
+
+ SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root
+ SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq
+ SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX
+
+ SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash
+ 0 :: boot from PromJet
+ SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower
+ halves (virtual banks)
+ 0 :: normal
+ SW5(3) = 0 CFG_FLASHWP = 0 :: not protected
+ SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4
+ 1:1 for PD6
+ SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined
+ SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined
+
+ SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff
+ SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation
+ SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ
+ SW6(6) = 1 CFG_SERROM_ADDR= 1 ::
+ SW6(7) = 1 CFG_MEMDEBUG = 1 ::
+ SW6(8) = 1 CFG_DDRDEBUG = 1 ::
+
+ SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
+ SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
+ SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
+ SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
+ SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
+ SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
+ SW8(7) = 1 ACPWR = 1 :: non-battery
+ SW8(8) = 0 CFG_IDWP = 0 :: write enable
+
+
+3. Flash U-Boot
+---------------
+The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves.
+It is possible to use either half to boot using u-boot. Switch 5 bit 2
+is used for this purpose.
+
+0xFF800000 to 0xFFBFFFFF - 4MB
+0xFFC00000 to 0xFFFFFFFF - 4MB
+When this bit is 0, U-Boot is at 0xFFF00000.
+When this bit is 1, U-Boot is at 0xFFB00000.
+
+Use the above mentioned flash commands to program the other half, and
+use switch 5, bit 2 to alternate between the halves. Note: The booting
+version of U-Boot will always be at 0xFFF00000.
+
+To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
+
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase fff00000 ffffffff
+ cp.b 1000000 fff00100 80000
+
+To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
+
+ tftp 1000000 u-boot.bin
+ erase ffb00000 ffbfffff
+ cp.b 1000000 ffb00100 80000
+
+
+4. Memory Map
+-------------
+
+ Memory Range Device Size
+ ------------ ------ ----
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
+ 0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M
+ 0xf800_0000 0xf80f_ffff CCSR 1M
+ 0xf810_0000 0xf81f_ffff PIXIS 1M
+ 0xf840_0000 0xf840_3fff Stack space 32K
+ 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 16M
+ 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M
+ 0xfe00_0000 0xfeff_ffff Flash(alternate)16M
+ 0xff00_0000 0xffff_ffff Flash(boot bank)16M
NAND FLASH commands and notes
-
See NOTE below!!!
-
# (C) Copyright 2003
# Dave Ellis, SIXNET, dge@sixnetio.com
#
nand device num
Make device `num' the current device and print information about it.
- nand erase off size
- nand erase clean [off size]
- Erase `size' bytes starting at offset `off'. Only complete erase
- blocks can be erased.
+ nand erase off|partition size
+ nand erase clean [off|partition size]
+ Erase `size' bytes starting at offset `off'. Alternatively partition
+ name can be specified, in this case size will be eventually limited
+ to not exceed partition size (this behaviour applies also to read
+ and write commands). Only complete erase blocks can be erased.
+
+ If `erase' is specified without an offset or size, the entire flash
+ is erased. If `erase' is specified with partition but without an
+ size, the entire partition is erased.
If `clean' is specified, a JFFS2-style clean marker is written to
- each block after it is erased. If `clean' is specified without an
- offset or size, the entire flash is erased.
+ each block after it is erased.
This command will not erase blocks that are marked bad. There is
a debug option in cmd_nand.c to allow bad blocks to be erased.
nand info
Print information about all of the NAND devices found.
- nand read addr ofs size
+ nand read addr ofs|partition size
Read `size' bytes from `ofs' in NAND flash to `addr'. If a page
cannot be read because it is marked bad or an uncorrectable data
error is found the command stops with an error.
- nand read.jffs2 addr ofs size
+ nand read.jffs2 addr ofs|partition size
Like `read', but the data for blocks that are marked bad is read as
0xff. This gives a readable JFFS2 image that can be processed by
the JFFS2 commands such as ls and fsload.
- nand read.oob addr ofs size
+ nand read.oob addr ofs|partition size
Read `size' bytes from the out-of-band data area corresponding to
`ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
data for one 512-byte page or 2 256-byte pages. There is no check
for bad blocks or ECC errors.
- nand write addr ofs size
+ nand write addr ofs|partition size
Write `size' bytes from `addr' to `ofs' in NAND flash. If a page
cannot be written because it is marked bad or the write fails the
command stops with an error.
- nand write.jffs2 addr ofs size
+ nand write.jffs2 addr ofs|partition size
Like `write', but blocks that are marked bad are skipped and the
is written to the next block instead. This allows writing writing
a JFFS2 image, as long as the image is short enough to fit even
produced by mkfs.jffs2 should work well, but loading an image copied
from another flash is going to be trouble if there are any bad blocks.
- nand write.oob addr ofs size
+ nand write.oob addr ofs|partition size
Write `size' bytes from `addr' to the out-of-band data area
corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
of data for one 512-byte page or 2 256-byte pages. There is no check
The consequence of this is that the legacy NAND can't be removed from
the tree until the DoC is ported to use the new NAND support (or boards
with DoC will break).
+
+
+Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
+
+JFFS2 related commands:
+
+ implement "nand erase clean" and old "nand erase"
+ using both the new code which is able to skip bad blocks
+ "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
+
+ "nand write.jffs2"
+ like "nand write" but skip found bad eraseblocks
+
+ "nand read.jffs2"
+ like "nand read" but skip found bad eraseblocks
+
+Miscellaneous and testing commands:
+ "markbad [offset]"
+ create an artificial bad block (for testing bad block handling)
+
+ "scrub [offset length]"
+ like "erase" but don't skip bad block. Instead erase them.
+ DANGEROUS!!! Factory set bad blocks will be lost. Use only
+ to remove artificial bad blocks created with the "markbad" command.
+
+
+NAND locking command (for chips with active LOCKPRE pin)
+
+ "nand lock"
+ set NAND chip to lock state (all pages locked)
+
+ "nand lock tight"
+ set NAND chip to lock tight state (software can't change locking anymore)
+
+ "nand lock status"
+ displays current locking status of all pages
+
+ "nand unlock [offset] [size]"
+ unlock consecutive area (can be called multiple times for different areas)
+
+
+I have tested the code with board containing 128MiB NAND large page chips
+and 32MiB small page chips.
--- /dev/null
+-----------------------------
+NAND boot on PPC440 platforms
+-----------------------------
+
+This document describes the U-Boot NAND boot feature as it
+is implemented for the AMCC Sequoia (PPC440EPx) board.
+
+The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
+completely without NOR FLASH. This can be done by using the NAND
+boot feature of the 440 NAND flash controller (NDFC).
+
+Here a short desciption of the different boot stages:
+
+a) IPL (Initial Program Loader, integrated inside CPU)
+------------------------------------------------------
+Will load first 4k from NAND (SPL) into cache and execute it from there.
+
+b) SPL (Secondary Program Loader)
+---------------------------------
+Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+controller and the NAND controller so that the special U-Boot image can be
+loaded from NAND to SDRAM.
+This special image is build in the directory "nand_spl".
+
+c) NUB (NAND U-Boot)
+--------------------
+This NAND U-Boot (NUB) is a special U-Boot version which can be started
+from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+
+On 440EPx the SPL is copied to internal SRAM before the NAND controller
+is set up. While still running from cache, I experienced problems accessing
+the NAND controller.
+
+
+Example: Build and install NAND boot image for Sequoia (440EPx):
+
+a) Configure for sequoia with NAND boot support:
+# make sequoia_nand_config
+
+b) Build image(s)
+# make
+
+This will generate the SPL image in the "nand_spl" directory:
+nand_spl/u-boot-spl.bin
+Also another image is created spanning a whole NAND block (16kBytes):
+nand_spl/u-boot-spl-16k.bin
+The main NAND U-Boot image is generated in the toplevel directory:
+u-boot.bin
+A combined image of u-boot-spl-16k.bin and u-boot.bin is also created:
+u-boot-nand.bin
+
+This image should be programmed at offset 0 in the NAND flash:
+
+# tftp 100000 /tftpboot/sequoia/u-boot-nand.bin
+# nand erase 0 60000
+# nand write 100000 0 60000
+
+
+September 07 2006, Stefan Roese <sr@denx.de>
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# CFLAGS += -DET_DEBUG -DDEBUG
-LIB = libdrivers.a
+LIB = $(obj)libdrivers.a
-OBJS = 3c589.o 5701rls.o ali512x.o \
+COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
e1000.o eepro100.o \
serial.o serial_max3100.o \
serial_pl010.o serial_pl011.o serial_xuartlite.o \
sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
- status_led.o sym53c8xx.o \
+ status_led.o sym53c8xx.o ahci.o \
ti_pci1410a.o tigon3.o tsec.o \
usb_ohci.o \
usbdcore.o usbdcore_ep0.o usbdcore_mpc8xx.o usbdcore_omap1510.o \
videomodes.o w83c553f.o \
ks8695eth.o \
pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \
- rpx_pcmcia.o
+ rpx_pcmcia.o \
+ fsl_i2c.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
--- /dev/null
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Author: Jason Jin<Jason.jin@freescale.com>
+ * Zhang Wei<wei.zhang@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * with the reference on libata and ahci drvier in kernel
+ *
+ */
+#include <common.h>
+
+#ifdef CONFIG_SCSI_AHCI
+
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <scsi.h>
+#include <ata.h>
+#include <linux/ctype.h>
+#include <ahci.h>
+
+struct ahci_probe_ent *probe_ent = NULL;
+hd_driveid_t *ataid[AHCI_MAX_PORTS];
+
+#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
+
+
+static inline u32 ahci_port_base(u32 base, u32 port)
+{
+ return base + 0x100 + (port * 0x80);
+}
+
+
+static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
+ unsigned int port_idx)
+{
+ base = ahci_port_base(base, port_idx);
+
+ port->cmd_addr = base;
+ port->scr_addr = base + PORT_SCR;
+}
+
+
+#define msleep(a) udelay(a * 1000)
+#define ssleep(a) msleep(a * 1000)
+
+static int waiting_for_cmd_completed(volatile u8 *offset,
+ int timeout_msec,
+ u32 sign)
+{
+ int i;
+ u32 status;
+
+ for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
+ msleep(1);
+
+ return (i < timeout_msec) ? 0 : -1;
+}
+
+
+static int ahci_host_init(struct ahci_probe_ent *probe_ent)
+{
+ pci_dev_t pdev = probe_ent->dev;
+ volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
+ u32 tmp, cap_save;
+ u16 tmp16;
+ int i, j;
+ volatile u8 *port_mmio;
+ unsigned short vendor;
+
+ cap_save = readl(mmio + HOST_CAP);
+ cap_save &= ((1 << 28) | (1 << 17));
+ cap_save |= (1 << 27);
+
+ /* global controller reset */
+ tmp = readl(mmio + HOST_CTL);
+ if ((tmp & HOST_RESET) == 0)
+ writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
+
+ /* reset must complete within 1 second, or
+ * the hardware should be considered fried.
+ */
+ ssleep(1);
+
+ tmp = readl(mmio + HOST_CTL);
+ if (tmp & HOST_RESET) {
+ debug("controller reset failed (0x%x)\n", tmp);
+ return -1;
+ }
+
+ writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
+ writel(cap_save, mmio + HOST_CAP);
+ writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
+
+ pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
+
+ if (vendor == PCI_VENDOR_ID_INTEL) {
+ u16 tmp16;
+ pci_read_config_word(pdev, 0x92, &tmp16);
+ tmp16 |= 0xf;
+ pci_write_config_word(pdev, 0x92, tmp16);
+ }
+
+ probe_ent->cap = readl(mmio + HOST_CAP);
+ probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
+ probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
+
+ debug("cap 0x%x port_map 0x%x n_ports %d\n",
+ probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
+
+ for (i = 0; i < probe_ent->n_ports; i++) {
+ probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
+ port_mmio = (u8 *) probe_ent->port[i].port_mmio;
+ ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
+
+ /* make sure port is not active */
+ tmp = readl(port_mmio + PORT_CMD);
+ if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
+ PORT_CMD_FIS_RX | PORT_CMD_START)) {
+ tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
+ PORT_CMD_FIS_RX | PORT_CMD_START);
+ writel_with_flush(tmp, port_mmio + PORT_CMD);
+
+ /* spec says 500 msecs for each bit, so
+ * this is slightly incorrect.
+ */
+ msleep(500);
+ }
+
+ writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
+
+ j = 0;
+ while (j < 100) {
+ msleep(10);
+ tmp = readl(port_mmio + PORT_SCR_STAT);
+ if ((tmp & 0xf) == 0x3)
+ break;
+ j++;
+ }
+
+ tmp = readl(port_mmio + PORT_SCR_ERR);
+ debug("PORT_SCR_ERR 0x%x\n", tmp);
+ writel(tmp, port_mmio + PORT_SCR_ERR);
+
+ /* ack any pending irq events for this port */
+ tmp = readl(port_mmio + PORT_IRQ_STAT);
+ debug("PORT_IRQ_STAT 0x%x\n", tmp);
+ if (tmp)
+ writel(tmp, port_mmio + PORT_IRQ_STAT);
+
+ writel(1 << i, mmio + HOST_IRQ_STAT);
+
+ /* set irq mask (enables interrupts) */
+ writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
+
+ /*register linkup ports */
+ tmp = readl(port_mmio + PORT_SCR_STAT);
+ debug("Port %d status: 0x%x\n", i, tmp);
+ if ((tmp & 0xf) == 0x03)
+ probe_ent->link_port_map |= (0x01 << i);
+ }
+
+ tmp = readl(mmio + HOST_CTL);
+ debug("HOST_CTL 0x%x\n", tmp);
+ writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
+ tmp = readl(mmio + HOST_CTL);
+ debug("HOST_CTL 0x%x\n", tmp);
+
+ pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
+ tmp |= PCI_COMMAND_MASTER;
+ pci_write_config_word(pdev, PCI_COMMAND, tmp16);
+
+ return 0;
+}
+
+
+static void ahci_print_info(struct ahci_probe_ent *probe_ent)
+{
+ pci_dev_t pdev = probe_ent->dev;
+ volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
+ u32 vers, cap, impl, speed;
+ const char *speed_s;
+ u16 cc;
+ const char *scc_s;
+
+ vers = readl(mmio + HOST_VERSION);
+ cap = probe_ent->cap;
+ impl = probe_ent->port_map;
+
+ speed = (cap >> 20) & 0xf;
+ if (speed == 1)
+ speed_s = "1.5";
+ else if (speed == 2)
+ speed_s = "3";
+ else
+ speed_s = "?";
+
+ pci_read_config_word(pdev, 0x0a, &cc);
+ if (cc == 0x0101)
+ scc_s = "IDE";
+ else if (cc == 0x0106)
+ scc_s = "SATA";
+ else if (cc == 0x0104)
+ scc_s = "RAID";
+ else
+ scc_s = "unknown";
+
+ printf("AHCI %02x%02x.%02x%02x "
+ "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
+ (vers >> 24) & 0xff,
+ (vers >> 16) & 0xff,
+ (vers >> 8) & 0xff,
+ vers & 0xff,
+ ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
+
+ printf("flags: "
+ "%s%s%s%s%s%s"
+ "%s%s%s%s%s%s%s\n",
+ cap & (1 << 31) ? "64bit " : "",
+ cap & (1 << 30) ? "ncq " : "",
+ cap & (1 << 28) ? "ilck " : "",
+ cap & (1 << 27) ? "stag " : "",
+ cap & (1 << 26) ? "pm " : "",
+ cap & (1 << 25) ? "led " : "",
+ cap & (1 << 24) ? "clo " : "",
+ cap & (1 << 19) ? "nz " : "",
+ cap & (1 << 18) ? "only " : "",
+ cap & (1 << 17) ? "pmp " : "",
+ cap & (1 << 15) ? "pio " : "",
+ cap & (1 << 14) ? "slum " : "",
+ cap & (1 << 13) ? "part " : "");
+}
+
+static int ahci_init_one(pci_dev_t pdev)
+{
+ u32 iobase, vendor;
+ int rc;
+
+ memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
+
+ probe_ent = malloc(sizeof(probe_ent));
+ memset(probe_ent, 0, sizeof(probe_ent));
+ probe_ent->dev = pdev;
+
+ pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase);
+ iobase &= ~0xf;
+
+ probe_ent->host_flags = ATA_FLAG_SATA
+ | ATA_FLAG_NO_LEGACY
+ | ATA_FLAG_MMIO
+ | ATA_FLAG_PIO_DMA
+ | ATA_FLAG_NO_ATAPI;
+ probe_ent->pio_mask = 0x1f;
+ probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
+
+ probe_ent->mmio_base = iobase;
+
+ /* Take from kernel:
+ * JMicron-specific fixup:
+ * make sure we're in AHCI mode
+ */
+ pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
+ if (vendor == 0x197b)
+ pci_write_config_byte(pdev, 0x41, 0xa1);
+
+ /* initialize adapter */
+ rc = ahci_host_init(probe_ent);
+ if (rc)
+ goto err_out;
+
+ ahci_print_info(probe_ent);
+
+ return 0;
+
+ err_out:
+ return rc;
+}
+
+
+#define MAX_DATA_BYTE_COUNT (4*1024*1024)
+
+static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
+{
+ struct ahci_ioports *pp = &(probe_ent->port[port]);
+ struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
+ u32 sg_count;
+ int i;
+
+ sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
+ if (sg_count > AHCI_MAX_SG) {
+ printf("Error:Too much sg!\n");
+ return -1;
+ }
+
+ for (i = 0; i < sg_count; i++) {
+ ahci_sg->addr =
+ cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
+ ahci_sg->addr_hi = 0;
+ ahci_sg->flags_size = cpu_to_le32(0x3fffff &
+ (buf_len < MAX_DATA_BYTE_COUNT
+ ? (buf_len - 1)
+ : (MAX_DATA_BYTE_COUNT - 1)));
+ ahci_sg++;
+ buf_len -= MAX_DATA_BYTE_COUNT;
+ }
+
+ return sg_count;
+}
+
+
+static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
+{
+ pp->cmd_slot->opts = cpu_to_le32(opts);
+ pp->cmd_slot->status = 0;
+ pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
+ pp->cmd_slot->tbl_addr_hi = 0;
+}
+
+
+static void ahci_set_feature(u8 port)
+{
+ struct ahci_ioports *pp = &(probe_ent->port[port]);
+ volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ u32 cmd_fis_len = 5; /* five dwords */
+ u8 fis[20];
+
+ /*set feature */
+ memset(fis, 0, 20);
+ fis[0] = 0x27;
+ fis[1] = 1 << 7;
+ fis[2] = ATA_CMD_SETF;
+ fis[3] = SETFEATURES_XFER;
+ fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
+
+ memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
+ ahci_fill_cmd_slot(pp, cmd_fis_len);
+ writel(1, port_mmio + PORT_CMD_ISSUE);
+ readl(port_mmio + PORT_CMD_ISSUE);
+
+ if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
+ printf("set feature error!\n");
+ }
+}
+
+
+static int ahci_port_start(u8 port)
+{
+ struct ahci_ioports *pp = &(probe_ent->port[port]);
+ volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ u32 port_status;
+ u32 mem;
+
+ debug("Enter start port: %d\n", port);
+ port_status = readl(port_mmio + PORT_SCR_STAT);
+ debug("Port %d status: %x\n", port, port_status);
+ if ((port_status & 0xf) != 0x03) {
+ printf("No Link on this port!\n");
+ return -1;
+ }
+
+ mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
+ if (!mem) {
+ free(pp);
+ printf("No mem for table!\n");
+ return -ENOMEM;
+ }
+
+ mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
+ memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
+
+ /*
+ * First item in chunk of DMA memory: 32-slot command table,
+ * 32 bytes each in size
+ */
+ pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
+ debug("cmd_slot = 0x%x\n", pp->cmd_slot);
+ mem += (AHCI_CMD_SLOT_SZ + 224);
+
+ /*
+ * Second item: Received-FIS area
+ */
+ pp->rx_fis = mem;
+ mem += AHCI_RX_FIS_SZ;
+
+ /*
+ * Third item: data area for storing a single command
+ * and its scatter-gather table
+ */
+ pp->cmd_tbl = mem;
+ debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
+
+ mem += AHCI_CMD_TBL_HDR;
+ pp->cmd_tbl_sg = (struct ahci_sg *)mem;
+
+ writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
+
+ writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+
+ writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
+ PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
+ PORT_CMD_START, port_mmio + PORT_CMD);
+
+ debug("Exit start port %d\n", port);
+
+ return 0;
+}
+
+
+static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
+ int buf_len)
+{
+
+ struct ahci_ioports *pp = &(probe_ent->port[port]);
+ volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ u32 opts;
+ u32 port_status;
+ int sg_count;
+
+ debug("Enter get_ahci_device_data: for port %d\n", port);
+
+ if (port > probe_ent->n_ports) {
+ printf("Invaild port number %d\n", port);
+ return -1;
+ }
+
+ port_status = readl(port_mmio + PORT_SCR_STAT);
+ if ((port_status & 0xf) != 0x03) {
+ debug("No Link on port %d!\n", port);
+ return -1;
+ }
+
+ memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
+
+ sg_count = ahci_fill_sg(port, buf, buf_len);
+ opts = (fis_len >> 2) | (sg_count << 16);
+ ahci_fill_cmd_slot(pp, opts);
+
+ writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
+
+ if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
+ printf("timeout exit!\n");
+ return -1;
+ }
+ debug("get_ahci_device_data: %d byte transferred.\n",
+ pp->cmd_slot->status);
+
+ return 0;
+}
+
+
+static char *ata_id_strcpy(u16 *target, u16 *src, int len)
+{
+ int i;
+ for (i = 0; i < len / 2; i++)
+ target[i] = le16_to_cpu(src[i]);
+ return (char *)target;
+}
+
+
+static void dump_ataid(hd_driveid_t *ataid)
+{
+ debug("(49)ataid->capability = 0x%x\n", ataid->capability);
+ debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
+ debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
+ debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
+ debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
+ debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
+ debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
+ debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
+ debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
+ debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
+ debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
+ debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
+ debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
+ debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
+ debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
+}
+
+
+/*
+ * SCSI INQUIRY command operation.
+ */
+static int ata_scsiop_inquiry(ccb *pccb)
+{
+ u8 hdr[] = {
+ 0,
+ 0,
+ 0x5, /* claim SPC-3 version compatibility */
+ 2,
+ 95 - 4,
+ };
+ u8 fis[20];
+ u8 *tmpid;
+ u8 port;
+
+ /* Clean ccb data buffer */
+ memset(pccb->pdata, 0, pccb->datalen);
+
+ memcpy(pccb->pdata, hdr, sizeof(hdr));
+
+ if (pccb->datalen <= 35)
+ return 0;
+
+ memset(fis, 0, 20);
+ /* Construct the FIS */
+ fis[0] = 0x27; /* Host to device FIS. */
+ fis[1] = 1 << 7; /* Command FIS. */
+ fis[2] = ATA_CMD_IDENT; /* Command byte. */
+
+ /* Read id from sata */
+ port = pccb->target;
+ if (!(tmpid = malloc(sizeof(hd_driveid_t))))
+ return -ENOMEM;
+
+ if (get_ahci_device_data(port, (u8 *) & fis, 20,
+ tmpid, sizeof(hd_driveid_t))) {
+ debug("scsi_ahci: SCSI inquiry command failure.\n");
+ return -EIO;
+ }
+
+ if (ataid[port])
+ free(ataid[port]);
+ ataid[port] = (hd_driveid_t *) tmpid;
+
+ memcpy(&pccb->pdata[8], "ATA ", 8);
+ ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
+ ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
+
+ dump_ataid(ataid[port]);
+ return 0;
+}
+
+
+/*
+ * SCSI READ10 command operation.
+ */
+static int ata_scsiop_read10(ccb * pccb)
+{
+ u64 lba = 0;
+ u32 len = 0;
+ u8 fis[20];
+
+ lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
+ | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
+ len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
+
+ /* For 10-byte and 16-byte SCSI R/W commands, transfer
+ * length 0 means transfer 0 block of data.
+ * However, for ATA R/W commands, sector count 0 means
+ * 256 or 65536 sectors, not 0 sectors as in SCSI.
+ *
+ * WARNING: one or two older ATA drives treat 0 as 0...
+ */
+ if (!len)
+ return 0;
+ memset(fis, 0, 20);
+
+ /* Construct the FIS */
+ fis[0] = 0x27; /* Host to device FIS. */
+ fis[1] = 1 << 7; /* Command FIS. */
+ fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
+
+ /* LBA address, only support LBA28 in this driver */
+ fis[4] = pccb->cmd[5];
+ fis[5] = pccb->cmd[4];
+ fis[6] = pccb->cmd[3];
+ fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
+
+ /* Sector Count */
+ fis[12] = pccb->cmd[8];
+ fis[13] = pccb->cmd[7];
+
+ /* Read from ahci */
+ if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
+ pccb->pdata, pccb->datalen)) {
+ debug("scsi_ahci: SCSI READ10 command failure.\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+
+/*
+ * SCSI READ CAPACITY10 command operation.
+ */
+static int ata_scsiop_read_capacity10(ccb *pccb)
+{
+ u8 buf[8];
+
+ if (!ataid[pccb->target]) {
+ printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
+ "\tNo ATA info!\n"
+ "\tPlease run SCSI commmand INQUIRY firstly!\n");
+ return -EPERM;
+ }
+
+ memset(buf, 0, 8);
+
+ *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity);
+
+ buf[6] = 512 >> 8;
+ buf[7] = 512 & 0xff;
+
+ memcpy(pccb->pdata, buf, 8);
+
+ return 0;
+}
+
+
+/*
+ * SCSI TEST UNIT READY command operation.
+ */
+static int ata_scsiop_test_unit_ready(ccb *pccb)
+{
+ return (ataid[pccb->target]) ? 0 : -EPERM;
+}
+
+
+int scsi_exec(ccb *pccb)
+{
+ int ret;
+
+ switch (pccb->cmd[0]) {
+ case SCSI_READ10:
+ ret = ata_scsiop_read10(pccb);
+ break;
+ case SCSI_RD_CAPAC:
+ ret = ata_scsiop_read_capacity10(pccb);
+ break;
+ case SCSI_TST_U_RDY:
+ ret = ata_scsiop_test_unit_ready(pccb);
+ break;
+ case SCSI_INQUIRY:
+ ret = ata_scsiop_inquiry(pccb);
+ break;
+ default:
+ printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
+ return FALSE;
+ }
+
+ if (ret) {
+ debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
+ return FALSE;
+ }
+ return TRUE;
+
+}
+
+
+void scsi_low_level_init(int busdevfunc)
+{
+ int i;
+ u32 linkmap;
+
+ ahci_init_one(busdevfunc);
+
+ linkmap = probe_ent->link_port_map;
+
+ for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) {
+ if (((linkmap >> i) & 0x01)) {
+ if (ahci_port_start((u8) i)) {
+ printf("Can not start port %d\n", i);
+ continue;
+ }
+ ahci_set_feature((u8) i);
+ }
+ }
+}
+
+
+void scsi_bus_reset(void)
+{
+ /*Not implement*/
+}
+
+
+void scsi_print_error(ccb * pccb)
+{
+ /*The ahci error info can be read in the ahci driver*/
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_ATMEL_USART
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+
+#include "atmel_usart.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void serial_setbrg(void)
+{
+ unsigned long divisor;
+ unsigned long usart_hz;
+
+ /*
+ * Master Clock
+ * Baud Rate = --------------
+ * 16 * CD
+ */
+ usart_hz = pm_get_clock_freq(gd->console_uart->resource[0].u.clock.id);
+ divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
+ usart3_writel(gd->console_uart, BRGR, USART3_BF(CD, divisor));
+}
+
+int serial_init(void)
+{
+ usart3_writel(gd->console_uart, CR,
+ USART3_BIT(RSTRX) | USART3_BIT(RSTTX));
+
+ serial_setbrg();
+
+ usart3_writel(gd->console_uart, CR,
+ USART3_BIT(RXEN) | USART3_BIT(TXEN));
+ usart3_writel(gd->console_uart, MR,
+ USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
+ | USART3_BF(USCLKS, USART3_USCLKS_MCK)
+ | USART3_BF(CHRL, USART3_CHRL_8)
+ | USART3_BF(PAR, USART3_PAR_NONE)
+ | USART3_BF(NBSTOP, USART3_NBSTOP_1));
+
+ return 0;
+}
+
+void serial_putc(char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(TXRDY))) ;
+ usart3_writel(gd->console_uart, THR, c);
+}
+
+void serial_puts(const char *s)
+{
+ while (*s)
+ serial_putc(*s++);
+}
+
+int serial_getc(void)
+{
+ while (!(usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY))) ;
+ return usart3_readl(gd->console_uart, RHR);
+}
+
+int serial_tstc(void)
+{
+ return (usart3_readl(gd->console_uart, CSR) & USART3_BIT(RXRDY)) != 0;
+}
+
+#endif /* CONFIG_ATMEL_USART */
--- /dev/null
+/*
+ * Register definitions for the Atmel USART3 module.
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __DRIVERS_ATMEL_USART_H__
+#define __DRIVERS_ATMEL_USART_H__
+
+/* USART3 register offsets */
+#define USART3_CR 0x0000
+#define USART3_MR 0x0004
+#define USART3_IER 0x0008
+#define USART3_IDR 0x000c
+#define USART3_IMR 0x0010
+#define USART3_CSR 0x0014
+#define USART3_RHR 0x0018
+#define USART3_THR 0x001c
+#define USART3_BRGR 0x0020
+#define USART3_RTOR 0x0024
+#define USART3_TTGR 0x0028
+#define USART3_FIDI 0x0040
+#define USART3_NER 0x0044
+#define USART3_XXR 0x0048
+#define USART3_IFR 0x004c
+#define USART3_RPR 0x0100
+#define USART3_RCR 0x0104
+#define USART3_TPR 0x0108
+#define USART3_TCR 0x010c
+#define USART3_RNPR 0x0110
+#define USART3_RNCR 0x0114
+#define USART3_TNPR 0x0118
+#define USART3_TNCR 0x011c
+#define USART3_PTCR 0x0120
+#define USART3_PTSR 0x0124
+
+/* Bitfields in CR */
+#define USART3_RSTRX_OFFSET 2
+#define USART3_RSTRX_SIZE 1
+#define USART3_RSTTX_OFFSET 3
+#define USART3_RSTTX_SIZE 1
+#define USART3_RXEN_OFFSET 4
+#define USART3_RXEN_SIZE 1
+#define USART3_RXDIS_OFFSET 5
+#define USART3_RXDIS_SIZE 1
+#define USART3_TXEN_OFFSET 6
+#define USART3_TXEN_SIZE 1
+#define USART3_TXDIS_OFFSET 7
+#define USART3_TXDIS_SIZE 1
+#define USART3_RSTSTA_OFFSET 8
+#define USART3_RSTSTA_SIZE 1
+#define USART3_STTBRK_OFFSET 9
+#define USART3_STTBRK_SIZE 1
+#define USART3_STPBRK_OFFSET 10
+#define USART3_STPBRK_SIZE 1
+#define USART3_STTTO_OFFSET 11
+#define USART3_STTTO_SIZE 1
+#define USART3_SENDA_OFFSET 12
+#define USART3_SENDA_SIZE 1
+#define USART3_RSTIT_OFFSET 13
+#define USART3_RSTIT_SIZE 1
+#define USART3_RSTNACK_OFFSET 14
+#define USART3_RSTNACK_SIZE 1
+#define USART3_RETTO_OFFSET 15
+#define USART3_RETTO_SIZE 1
+#define USART3_DTREN_OFFSET 16
+#define USART3_DTREN_SIZE 1
+#define USART3_DTRDIS_OFFSET 17
+#define USART3_DTRDIS_SIZE 1
+#define USART3_RTSEN_OFFSET 18
+#define USART3_RTSEN_SIZE 1
+#define USART3_RTSDIS_OFFSET 19
+#define USART3_RTSDIS_SIZE 1
+#define USART3_COMM_TX_OFFSET 30
+#define USART3_COMM_TX_SIZE 1
+#define USART3_COMM_RX_OFFSET 31
+#define USART3_COMM_RX_SIZE 1
+
+/* Bitfields in MR */
+#define USART3_USART_MODE_OFFSET 0
+#define USART3_USART_MODE_SIZE 4
+#define USART3_USCLKS_OFFSET 4
+#define USART3_USCLKS_SIZE 2
+#define USART3_CHRL_OFFSET 6
+#define USART3_CHRL_SIZE 2
+#define USART3_SYNC_OFFSET 8
+#define USART3_SYNC_SIZE 1
+#define USART3_PAR_OFFSET 9
+#define USART3_PAR_SIZE 3
+#define USART3_NBSTOP_OFFSET 12
+#define USART3_NBSTOP_SIZE 2
+#define USART3_CHMODE_OFFSET 14
+#define USART3_CHMODE_SIZE 2
+#define USART3_MSBF_OFFSET 16
+#define USART3_MSBF_SIZE 1
+#define USART3_MODE9_OFFSET 17
+#define USART3_MODE9_SIZE 1
+#define USART3_CLKO_OFFSET 18
+#define USART3_CLKO_SIZE 1
+#define USART3_OVER_OFFSET 19
+#define USART3_OVER_SIZE 1
+#define USART3_INACK_OFFSET 20
+#define USART3_INACK_SIZE 1
+#define USART3_DSNACK_OFFSET 21
+#define USART3_DSNACK_SIZE 1
+#define USART3_MAX_ITERATION_OFFSET 24
+#define USART3_MAX_ITERATION_SIZE 3
+#define USART3_FILTER_OFFSET 28
+#define USART3_FILTER_SIZE 1
+
+/* Bitfields in CSR */
+#define USART3_RXRDY_OFFSET 0
+#define USART3_RXRDY_SIZE 1
+#define USART3_TXRDY_OFFSET 1
+#define USART3_TXRDY_SIZE 1
+#define USART3_RXBRK_OFFSET 2
+#define USART3_RXBRK_SIZE 1
+#define USART3_ENDRX_OFFSET 3
+#define USART3_ENDRX_SIZE 1
+#define USART3_ENDTX_OFFSET 4
+#define USART3_ENDTX_SIZE 1
+#define USART3_OVRE_OFFSET 5
+#define USART3_OVRE_SIZE 1
+#define USART3_FRAME_OFFSET 6
+#define USART3_FRAME_SIZE 1
+#define USART3_PARE_OFFSET 7
+#define USART3_PARE_SIZE 1
+#define USART3_TIMEOUT_OFFSET 8
+#define USART3_TIMEOUT_SIZE 1
+#define USART3_TXEMPTY_OFFSET 9
+#define USART3_TXEMPTY_SIZE 1
+#define USART3_ITERATION_OFFSET 10
+#define USART3_ITERATION_SIZE 1
+#define USART3_TXBUFE_OFFSET 11
+#define USART3_TXBUFE_SIZE 1
+#define USART3_RXBUFF_OFFSET 12
+#define USART3_RXBUFF_SIZE 1
+#define USART3_NACK_OFFSET 13
+#define USART3_NACK_SIZE 1
+#define USART3_RIIC_OFFSET 16
+#define USART3_RIIC_SIZE 1
+#define USART3_DSRIC_OFFSET 17
+#define USART3_DSRIC_SIZE 1
+#define USART3_DCDIC_OFFSET 18
+#define USART3_DCDIC_SIZE 1
+#define USART3_CTSIC_OFFSET 19
+#define USART3_CTSIC_SIZE 1
+#define USART3_RI_OFFSET 20
+#define USART3_RI_SIZE 1
+#define USART3_DSR_OFFSET 21
+#define USART3_DSR_SIZE 1
+#define USART3_DCD_OFFSET 22
+#define USART3_DCD_SIZE 1
+#define USART3_CTS_OFFSET 23
+#define USART3_CTS_SIZE 1
+
+/* Bitfields in RHR */
+#define USART3_RXCHR_OFFSET 0
+#define USART3_RXCHR_SIZE 9
+
+/* Bitfields in THR */
+#define USART3_TXCHR_OFFSET 0
+#define USART3_TXCHR_SIZE 9
+
+/* Bitfields in BRGR */
+#define USART3_CD_OFFSET 0
+#define USART3_CD_SIZE 16
+
+/* Bitfields in RTOR */
+#define USART3_TO_OFFSET 0
+#define USART3_TO_SIZE 16
+
+/* Bitfields in TTGR */
+#define USART3_TG_OFFSET 0
+#define USART3_TG_SIZE 8
+
+/* Bitfields in FIDI */
+#define USART3_FI_DI_RATIO_OFFSET 0
+#define USART3_FI_DI_RATIO_SIZE 11
+
+/* Bitfields in NER */
+#define USART3_NB_ERRORS_OFFSET 0
+#define USART3_NB_ERRORS_SIZE 8
+
+/* Bitfields in XXR */
+#define USART3_XOFF_OFFSET 0
+#define USART3_XOFF_SIZE 8
+#define USART3_XON_OFFSET 8
+#define USART3_XON_SIZE 8
+
+/* Bitfields in IFR */
+#define USART3_IRDA_FILTER_OFFSET 0
+#define USART3_IRDA_FILTER_SIZE 8
+
+/* Bitfields in RCR */
+#define USART3_RXCTR_OFFSET 0
+#define USART3_RXCTR_SIZE 16
+
+/* Bitfields in TCR */
+#define USART3_TXCTR_OFFSET 0
+#define USART3_TXCTR_SIZE 16
+
+/* Bitfields in RNCR */
+#define USART3_RXNCR_OFFSET 0
+#define USART3_RXNCR_SIZE 16
+
+/* Bitfields in TNCR */
+#define USART3_TXNCR_OFFSET 0
+#define USART3_TXNCR_SIZE 16
+
+/* Bitfields in PTCR */
+#define USART3_RXTEN_OFFSET 0
+#define USART3_RXTEN_SIZE 1
+#define USART3_RXTDIS_OFFSET 1
+#define USART3_RXTDIS_SIZE 1
+#define USART3_TXTEN_OFFSET 8
+#define USART3_TXTEN_SIZE 1
+#define USART3_TXTDIS_OFFSET 9
+#define USART3_TXTDIS_SIZE 1
+
+/* Constants for USART_MODE */
+#define USART3_USART_MODE_NORMAL 0
+#define USART3_USART_MODE_RS485 1
+#define USART3_USART_MODE_HARDWARE 2
+#define USART3_USART_MODE_MODEM 3
+#define USART3_USART_MODE_ISO7816_T0 4
+#define USART3_USART_MODE_ISO7816_T1 6
+#define USART3_USART_MODE_IRDA 8
+
+/* Constants for USCLKS */
+#define USART3_USCLKS_MCK 0
+#define USART3_USCLKS_MCK_DIV 1
+#define USART3_USCLKS_SCK 3
+
+/* Constants for CHRL */
+#define USART3_CHRL_5 0
+#define USART3_CHRL_6 1
+#define USART3_CHRL_7 2
+#define USART3_CHRL_8 3
+
+/* Constants for PAR */
+#define USART3_PAR_EVEN 0
+#define USART3_PAR_ODD 1
+#define USART3_PAR_SPACE 2
+#define USART3_PAR_MARK 3
+#define USART3_PAR_NONE 4
+#define USART3_PAR_MULTI 6
+
+/* Constants for NBSTOP */
+#define USART3_NBSTOP_1 0
+#define USART3_NBSTOP_1_5 1
+#define USART3_NBSTOP_2 2
+
+/* Constants for CHMODE */
+#define USART3_CHMODE_NORMAL 0
+#define USART3_CHMODE_ECHO 1
+#define USART3_CHMODE_LOCAL_LOOP 2
+#define USART3_CHMODE_REMOTE_LOOP 3
+
+/* Constants for MSBF */
+#define USART3_MSBF_LSBF 0
+#define USART3_MSBF_MSBF 1
+
+/* Constants for OVER */
+#define USART3_OVER_X16 0
+#define USART3_OVER_X8 1
+
+/* Constants for CD */
+#define USART3_CD_DISABLE 0
+#define USART3_CD_BYPASS 1
+
+/* Constants for TO */
+#define USART3_TO_DISABLE 0
+
+/* Constants for TG */
+#define USART3_TG_DISABLE 0
+
+/* Constants for FI_DI_RATIO */
+#define USART3_FI_DI_RATIO_DISABLE 0
+
+/* Bit manipulation macros */
+#define USART3_BIT(name) \
+ (1 << USART3_##name##_OFFSET)
+#define USART3_BF(name,value) \
+ (((value) & ((1 << USART3_##name##_SIZE) - 1)) \
+ << USART3_##name##_OFFSET)
+#define USART3_BFEXT(name,value) \
+ (((value) >> USART3_##name##_OFFSET) \
+ & ((1 << USART3_##name##_SIZE) - 1))
+#define USART3_BFINS(name,value,old) \
+ (((old) & ~(((1 << USART3_##name##_SIZE) - 1) \
+ << USART3_##name##_OFFSET)) \
+ | USART3_BF(name,value))
+
+/* Register access macros */
+#define usart3_readl(port,reg) \
+ readl((port)->regs + USART3_##reg)
+#define usart3_writel(port,reg,value) \
+ writel((value), (port)->regs + USART3_##reg)
+
+#endif /* __DRIVERS_ATMEL_USART_H__ */
*
* Copyright (C) 2003 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
- * Modified to work with AMD flashes
*
* Copyright (C) 2004
* Ed Okerson
- * Modified to work with little-endian systems.
+ *
+ * Copyright (C) 2006
+ * Tolunay Orkun <listmember@orkun.us>
*
* See file CREDITS for list of people who contributed to this
* project.
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
- * History
- * 01/20/2004 - combined variants of original driver.
- * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
- * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
- * 01/27/2004 - Little endian support Ed Okerson
- *
- * Tested Architectures
- * Port Width Chip Width # of banks Flash Chip Board
- * 32 16 1 28F128J3 seranoa/eagle
- * 64 16 1 28F128J3 seranoa/falcon
- *
*/
/* The DEBUG define must be before common to enable debugging */
* This file implements a Common Flash Interface (CFI) driver for U-Boot.
* The width of the port and the width of the chips are determined at initialization.
* These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
*
* References
* JEDEC Standard JESD68 - Common Flash Interface (CFI)
* JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
* Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
* Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ * AMD CFI Specification, Release 2.0 December 1, 2001
+ * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
+ * Device IDs, Publication Number 25538 Revision A, November 8, 2001
*
- * TODO
- *
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
- * Table (ALT) to determine if protection is available
- *
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
*/
#ifndef CFG_FLASH_BANKS_LIST
#define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555)
#define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA)
+#define FLASH_OFFSET_MANUFACTURER_ID 0x00
+#define FLASH_OFFSET_DEVICE_ID 0x01
+#define FLASH_OFFSET_DEVICE_ID2 0x0E
+#define FLASH_OFFSET_DEVICE_ID3 0x0F
#define FLASH_OFFSET_CFI 0x55
#define FLASH_OFFSET_CFI_RESP 0x10
#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
#define FLASH_OFFSET_USER_PROTECTION 0x85
#define FLASH_OFFSET_INTEL_PROTECTION 0x81
-
-#define FLASH_MAN_CFI 0x01000000
-
-#define CFI_CMDSET_NONE 0
-#define CFI_CMDSET_INTEL_EXTENDED 1
-#define CFI_CMDSET_AMD_STANDARD 2
-#define CFI_CMDSET_INTEL_STANDARD 3
-#define CFI_CMDSET_AMD_EXTENDED 4
-#define CFI_CMDSET_MITSU_STANDARD 256
-#define CFI_CMDSET_MITSU_EXTENDED 257
-#define CFI_CMDSET_SST 258
-
+#define CFI_CMDSET_NONE 0
+#define CFI_CMDSET_INTEL_EXTENDED 1
+#define CFI_CMDSET_AMD_STANDARD 2
+#define CFI_CMDSET_INTEL_STANDARD 3
+#define CFI_CMDSET_AMD_EXTENDED 4
+#define CFI_CMDSET_MITSU_STANDARD 256
+#define CFI_CMDSET_MITSU_EXTENDED 257
+#define CFI_CMDSET_SST 258
#ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
# undef FLASH_CMD_RESET
-# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
+# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
#endif
-
typedef union {
unsigned char c;
unsigned short w;
volatile unsigned long long *llp;
} cfiptr_t;
-#define NUM_ERASE_REGIONS 4
+#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
#ifdef CFG_MAX_FLASH_BANKS_DETECT
static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
+static void flash_read_jedec_ids (flash_info_t * info);
static int flash_detect_cfi (flash_info_t * info);
static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
}
/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
+ * read a long word by picking the least significant byte of each maximum
* port size word. Swap for ppc format.
*/
ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
(info->portwidth << 3), (info->chipwidth << 3));
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
- printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+ printf (" ");
+ switch (info->vendor) {
+ case CFI_CMDSET_INTEL_STANDARD:
+ printf ("Intel Standard");
+ break;
+ case CFI_CMDSET_INTEL_EXTENDED:
+ printf ("Intel Extended");
+ break;
+ case CFI_CMDSET_AMD_STANDARD:
+ printf ("AMD Standard");
+ break;
+ case CFI_CMDSET_AMD_EXTENDED:
+ printf ("AMD Extended");
+ break;
+ default:
+ printf ("Unknown (%d)", info->vendor);
+ break;
+ }
+ printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X",
+ info->manufacturer_id, info->device_id);
+ if (info->device_id == 0x7E) {
+ printf("%04X", info->device_id2);
+ }
+ printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
info->erase_blk_tout,
- info->write_tout,
+ info->write_tout);
+ if (info->buffer_size > 1) {
+ printf (" Buffer write timeout: %ld ms, buffer size: %d bytes\n",
info->buffer_write_tout,
info->buffer_size);
+ }
- puts (" Sector Start Addresses:");
+ puts ("\n Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n");
#ifdef CFG_FLASH_EMPTY_INFO
int k;
int size;
}
}
- if ((i % 5) == 0)
- printf ("\n");
/* print empty and read-only info */
- printf (" %08lX%s%s",
+ printf (" %08lX %c %s ",
info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
+ erased ? 'E' : ' ',
+ info->protect[i] ? "RO" : " ");
#else /* ! CFG_FLASH_EMPTY_INFO */
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
+ printf (" %08lX %s ",
+ info->start[i],
+ info->protect[i] ? "RO" : " ");
#endif
}
putc ('\n');
return retval;
}
+/*-----------------------------------------------------------------------
+ * read jedec ids from device and set corresponding fields in info struct
+ *
+ * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
+ *
+*/
+static void flash_read_jedec_ids (flash_info_t * info)
+{
+ info->manufacturer_id = 0;
+ info->device_id = 0;
+ info->device_id2 = 0;
+
+ switch (info->vendor) {
+ case CFI_CMDSET_INTEL_STANDARD:
+ case CFI_CMDSET_INTEL_EXTENDED:
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
+ udelay(1000); /* some flash are slow to respond */
+ info->manufacturer_id = flash_read_uchar (info,
+ FLASH_OFFSET_MANUFACTURER_ID);
+ info->device_id = flash_read_uchar (info,
+ FLASH_OFFSET_DEVICE_ID);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+ break;
+ case CFI_CMDSET_AMD_STANDARD:
+ case CFI_CMDSET_AMD_EXTENDED:
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+ flash_unlock_seq(info, 0);
+ flash_write_cmd(info, 0, AMD_ADDR_START, FLASH_CMD_READ_ID);
+ udelay(1000); /* some flash are slow to respond */
+ info->manufacturer_id = flash_read_uchar (info,
+ FLASH_OFFSET_MANUFACTURER_ID);
+ info->device_id = flash_read_uchar (info,
+ FLASH_OFFSET_DEVICE_ID);
+ if (info->device_id == 0x7E) {
+ /* AMD 3-byte (expanded) device ids */
+ info->device_id2 = flash_read_uchar (info,
+ FLASH_OFFSET_DEVICE_ID2);
+ info->device_id2 <<= 8;
+ info->device_id2 |= flash_read_uchar (info,
+ FLASH_OFFSET_DEVICE_ID3);
+ }
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+ break;
+ default:
+ break;
+ }
+}
+
/*-----------------------------------------------------------------------
* detect if flash is compatible with the Common Flash Interface (CFI)
* http://www.jedec.org/download/search/jesd68.pdf
uchar num_erase_regions;
int erase_region_size;
int erase_region_count;
+ int geometry_reversed = 0;
+
+ info->ext_addr = 0;
+ info->cfi_version = 0;
#ifdef CFG_FLASH_PROTECTION
- int ext_addr;
info->legacy_unlock = 0;
#endif
info->start[0] = base;
if (flash_detect_cfi (info)) {
- info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR);
+ info->vendor = flash_read_ushort (info, 0,
+ FLASH_OFFSET_PRIMARY_VENDOR);
+ flash_read_jedec_ids (info);
+ flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+ num_erase_regions = flash_read_uchar (info,
+ FLASH_OFFSET_NUM_ERASE_REGIONS);
+ info->ext_addr = flash_read_ushort (info, 0,
+ FLASH_OFFSET_EXT_QUERY_T_P_ADDR);
+ if (info->ext_addr) {
+ info->cfi_version = (ushort) flash_read_uchar (info,
+ info->ext_addr + 3) << 8;
+ info->cfi_version |= (ushort) flash_read_uchar (info,
+ info->ext_addr + 4);
+ }
#ifdef DEBUG
flash_printqry (info, 0);
#endif
info->cmd_reset = FLASH_CMD_RESET;
#ifdef CFG_FLASH_PROTECTION
/* read legacy lock/unlock bit from intel flash */
- ext_addr = flash_read_ushort (info, 0,
- FLASH_OFFSET_EXT_QUERY_T_P_ADDR);
- info->legacy_unlock =
- flash_read_uchar (info, ext_addr + 5) & 0x08;
+ if (info->ext_addr) {
+ info->legacy_unlock = flash_read_uchar (info,
+ info->ext_addr + 5) & 0x08;
+ }
#endif
break;
case CFI_CMDSET_AMD_STANDARD:
case CFI_CMDSET_AMD_EXTENDED:
info->cmd_reset = AMD_CMD_RESET;
+ /* check if flash geometry needs reversal */
+ if (num_erase_regions <= 1)
+ break;
+ /* reverse geometry if top boot part */
+ if (info->cfi_version < 0x3131) {
+ /* CFI < 1.1, try to guess from device id */
+ if ((info->device_id & 0x80) != 0) {
+ geometry_reversed = 1;
+ }
+ break;
+ }
+ /* CFI >= 1.1, deduct from top/bottom flag */
+ /* note: ext_addr is valid since cfi_version > 0 */
+ if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
+ geometry_reversed = 1;
+ }
break;
}
debug ("manufacturer is %d\n", info->vendor);
+ debug ("manufacturer id is 0x%x\n", info->manufacturer_id);
+ debug ("device id is 0x%x\n", info->device_id);
+ debug ("device id2 is 0x%x\n", info->device_id2);
+ debug ("cfi version is 0x%04x\n", info->cfi_version);
+
size_ratio = info->portwidth / info->chipwidth;
/* if the chip is x8/x16 reduce the ratio by half */
if ((info->interface == FLASH_CFI_X8X16)
&& (info->chipwidth == FLASH_CFI_BY8)) {
size_ratio >>= 1;
}
- num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
debug ("size_ratio %d port %d bits chip %d bits\n",
size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
num_erase_regions, NUM_ERASE_REGIONS);
break;
}
- tmp = flash_read_long (info, 0,
+ if (geometry_reversed)
+ tmp = flash_read_long (info, 0,
+ FLASH_OFFSET_ERASE_REGIONS +
+ (num_erase_regions - 1 - i) * 4);
+ else
+ tmp = flash_read_long (info, 0,
FLASH_OFFSET_ERASE_REGIONS +
i * 4);
erase_region_size =
u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
u16 RxStatus, RxLen = 0;
u32 tmplen, i;
+#ifdef CONFIG_DM9000_USE_32BIT
+ u32 tmpdata;
+#endif
/* Check packet ready or not */
DM9000_ior(DM9000_MRCMDX); /* Dummy read */
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_FSL_I2C
+#ifdef CONFIG_HARD_I2C
+
+#include <command.h>
+#include <i2c.h> /* Functional interface */
+
+#include <asm/io.h>
+#include <asm/fsl_i2c.h> /* HW definitions */
+
+#define I2C_TIMEOUT (CFG_HZ / 4)
+#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET))
+
+
+void
+i2c_init(int speed, int slaveadd)
+{
+ /* stop I2C controller */
+ writeb(0x0, &I2C->cr);
+
+ /* set clock */
+ writeb(0x3f, &I2C->fdr);
+
+ /* set default filter */
+ writeb(0x10, &I2C->dfsrr);
+
+ /* write slave address */
+ writeb(slaveadd, &I2C->adr);
+
+ /* clear status register */
+ writeb(0x0, &I2C->sr);
+
+ /* start I2C controller */
+ writeb(I2C_CR_MEN, &I2C->cr);
+}
+
+static __inline__ int
+i2c_wait4bus(void)
+{
+ ulong timeval = get_timer(0);
+
+ while (readb(&I2C->sr) & I2C_SR_MBB) {
+ if (get_timer(timeval) > I2C_TIMEOUT) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+static __inline__ int
+i2c_wait(int write)
+{
+ u32 csr;
+ ulong timeval = get_timer(0);
+
+ do {
+ csr = readb(&I2C->sr);
+ if (!(csr & I2C_SR_MIF))
+ continue;
+
+ writeb(0x0, &I2C->sr);
+
+ if (csr & I2C_SR_MAL) {
+ debug("i2c_wait: MAL\n");
+ return -1;
+ }
+
+ if (!(csr & I2C_SR_MCF)) {
+ debug("i2c_wait: unfinished\n");
+ return -1;
+ }
+
+ if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) {
+ debug("i2c_wait: No RXACK\n");
+ return -1;
+ }
+
+ return 0;
+ } while (get_timer (timeval) < I2C_TIMEOUT);
+
+ debug("i2c_wait: timed out\n");
+ return -1;
+}
+
+static __inline__ int
+i2c_write_addr (u8 dev, u8 dir, int rsta)
+{
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
+ | (rsta ? I2C_CR_RSTA : 0),
+ &I2C->cr);
+
+ writeb((dev << 1) | dir, &I2C->dr);
+
+ if (i2c_wait(I2C_WRITE) < 0)
+ return 0;
+
+ return 1;
+}
+
+static __inline__ int
+__i2c_write(u8 *data, int length)
+{
+ int i;
+
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
+ &I2C->cr);
+
+ for (i = 0; i < length; i++) {
+ writeb(data[i], &I2C->dr);
+
+ if (i2c_wait(I2C_WRITE) < 0)
+ break;
+ }
+
+ return i;
+}
+
+static __inline__ int
+__i2c_read(u8 *data, int length)
+{
+ int i;
+
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
+ &I2C->cr);
+
+ /* dummy read */
+ readb(&I2C->dr);
+
+ for (i = 0; i < length; i++) {
+ if (i2c_wait(I2C_READ) < 0)
+ break;
+
+ /* Generate ack on last next to last byte */
+ if (i == length - 2)
+ writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
+ &I2C->cr);
+
+ /* Generate stop on last byte */
+ if (i == length - 1)
+ writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr);
+
+ data[i] = readb(&I2C->dr);
+ }
+
+ return i;
+}
+
+int
+i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
+{
+ int i = 0;
+ u8 *a = (u8*)&addr;
+
+ if (i2c_wait4bus() >= 0
+ && i2c_write_addr(dev, I2C_WRITE, 0) != 0
+ && __i2c_write(&a[4 - alen], alen) == alen
+ && i2c_write_addr(dev, I2C_READ, 1) != 0) {
+ i = __i2c_read(data, length);
+ }
+
+ writeb(I2C_CR_MEN, &I2C->cr);
+
+ if (i == length)
+ return 0;
+
+ return -1;
+}
+
+int
+i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
+{
+ int i = 0;
+ u8 *a = (u8*)&addr;
+
+ if (i2c_wait4bus() >= 0
+ && i2c_write_addr(dev, I2C_WRITE, 0) != 0
+ && __i2c_write(&a[4 - alen], alen) == alen) {
+ i = __i2c_write(data, length);
+ }
+
+ writeb(I2C_CR_MEN, &I2C->cr);
+
+ if (i == length)
+ return 0;
+
+ return -1;
+}
+
+int
+i2c_probe(uchar chip)
+{
+ int tmp;
+
+ /*
+ * Try to read the first location of the chip. The underlying
+ * driver doesn't appear to support sending just the chip address
+ * and looking for an <ACK> back.
+ */
+ udelay(10000);
+
+ return i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
+}
+
+uchar
+i2c_reg_read(uchar i2c_addr, uchar reg)
+{
+ uchar buf[1];
+
+ i2c_read(i2c_addr, reg, 1, buf, 1);
+
+ return buf[0];
+}
+
+void
+i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
+{
+ i2c_write(i2c_addr, reg, 1, &val, 1);
+}
+
+#endif /* CONFIG_HARD_I2C */
+#endif /* CONFIG_FSL_I2C */
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
include $(TOPDIR)/config.mk
-LIB := libnand.a
+LIB := $(obj)libnand.a
+
+COBJS := nand.o nand_base.o nand_ids.o nand_ecc.o nand_bbt.o nand_util.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
-OBJS := nand.o nand_base.o nand_ids.o nand_ecc.o nand_bbt.o
all: $(LIB)
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
+
+#########################################################################
size += nand_info[i].size;
if (nand_curr_device == -1)
nand_curr_device = i;
-}
+ }
printf("%lu MiB\n", size / (1024 * 1024));
+
+#ifdef CFG_NAND_SELECT_DEVICE
+ /*
+ * Select the chip in the board/cpu specific driver
+ */
+ board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device);
+#endif
}
#endif
--- /dev/null
+/*
+ * drivers/nand/nand_util.c
+ *
+ * Copyright (C) 2006 by Weiss-Electronic GmbH.
+ * All rights reserved.
+ *
+ * @author: Guido Classen <clagix@gmail.com>
+ * @descr: NAND Flash support
+ * @references: borrowed heavily from Linux mtd-utils code:
+ * flash_eraseall.c by Arcom Control System Ltd
+ * nandwrite.c by Steven J. Hill (sjhill@realitydiluted.com)
+ * and Thomas Gleixner (tglx@linutronix.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+
+#include <command.h>
+#include <watchdog.h>
+#include <malloc.h>
+
+#include <nand.h>
+#include <jffs2/jffs2.h>
+
+typedef struct erase_info erase_info_t;
+typedef struct mtd_info mtd_info_t;
+
+/* support only for native endian JFFS2 */
+#define cpu_to_je16(x) (x)
+#define cpu_to_je32(x) (x)
+
+/*****************************************************************************/
+static int nand_block_bad_scrub(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+ return 0;
+}
+
+/**
+ * nand_erase_opts: - erase NAND flash with support for various options
+ * (jffs2 formating)
+ *
+ * @param meminfo NAND device to erase
+ * @param opts options, @see struct nand_erase_options
+ * @return 0 in case of success
+ *
+ * This code is ported from flash_eraseall.c from Linux mtd utils by
+ * Arcom Control System Ltd.
+ */
+int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
+{
+ struct jffs2_unknown_node cleanmarker;
+ int clmpos = 0;
+ int clmlen = 8;
+ erase_info_t erase;
+ ulong erase_length;
+ int isNAND;
+ int bbtest = 1;
+ int result;
+ int percent_complete = -1;
+ int (*nand_block_bad_old)(struct mtd_info *, loff_t, int) = NULL;
+ const char *mtd_device = meminfo->name;
+
+ memset(&erase, 0, sizeof(erase));
+
+ erase.mtd = meminfo;
+ erase.len = meminfo->erasesize;
+ erase.addr = opts->offset;
+ erase_length = opts->length;
+
+ isNAND = meminfo->type == MTD_NANDFLASH ? 1 : 0;
+
+ if (opts->jffs2) {
+ cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK);
+ cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER);
+ if (isNAND) {
+ struct nand_oobinfo *oobinfo = &meminfo->oobinfo;
+
+ /* check for autoplacement */
+ if (oobinfo->useecc == MTD_NANDECC_AUTOPLACE) {
+ /* get the position of the free bytes */
+ if (!oobinfo->oobfree[0][1]) {
+ printf(" Eeep. Autoplacement selected "
+ "and no empty space in oob\n");
+ return -1;
+ }
+ clmpos = oobinfo->oobfree[0][0];
+ clmlen = oobinfo->oobfree[0][1];
+ if (clmlen > 8)
+ clmlen = 8;
+ } else {
+ /* legacy mode */
+ switch (meminfo->oobsize) {
+ case 8:
+ clmpos = 6;
+ clmlen = 2;
+ break;
+ case 16:
+ clmpos = 8;
+ clmlen = 8;
+ break;
+ case 64:
+ clmpos = 16;
+ clmlen = 8;
+ break;
+ }
+ }
+
+ cleanmarker.totlen = cpu_to_je32(8);
+ } else {
+ cleanmarker.totlen =
+ cpu_to_je32(sizeof(struct jffs2_unknown_node));
+ }
+ cleanmarker.hdr_crc = cpu_to_je32(
+ crc32_no_comp(0, (unsigned char *) &cleanmarker,
+ sizeof(struct jffs2_unknown_node) - 4));
+ }
+
+ /* scrub option allows to erase badblock. To prevent internal
+ * check from erase() method, set block check method to dummy
+ * and disable bad block table while erasing.
+ */
+ if (opts->scrub) {
+ struct nand_chip *priv_nand = meminfo->priv;
+
+ nand_block_bad_old = priv_nand->block_bad;
+ priv_nand->block_bad = nand_block_bad_scrub;
+ /* we don't need the bad block table anymore...
+ * after scrub, there are no bad blocks left!
+ */
+ if (priv_nand->bbt) {
+ kfree(priv_nand->bbt);
+ }
+ priv_nand->bbt = NULL;
+ }
+
+ for (;
+ erase.addr < opts->offset + erase_length;
+ erase.addr += meminfo->erasesize) {
+
+ WATCHDOG_RESET ();
+
+ if (!opts->scrub && bbtest) {
+ int ret = meminfo->block_isbad(meminfo, erase.addr);
+ if (ret > 0) {
+ if (!opts->quiet)
+ printf("\rSkipping bad block at "
+ "0x%08x "
+ " \n",
+ erase.addr);
+ continue;
+
+ } else if (ret < 0) {
+ printf("\n%s: MTD get bad block failed: %d\n",
+ mtd_device,
+ ret);
+ return -1;
+ }
+ }
+
+ result = meminfo->erase(meminfo, &erase);
+ if (result != 0) {
+ printf("\n%s: MTD Erase failure: %d\n",
+ mtd_device, result);
+ continue;
+ }
+
+ /* format for JFFS2 ? */
+ if (opts->jffs2) {
+
+ /* write cleanmarker */
+ if (isNAND) {
+ size_t written;
+ result = meminfo->write_oob(meminfo,
+ erase.addr + clmpos,
+ clmlen,
+ &written,
+ (unsigned char *)
+ &cleanmarker);
+ if (result != 0) {
+ printf("\n%s: MTD writeoob failure: %d\n",
+ mtd_device, result);
+ continue;
+ }
+ } else {
+ printf("\n%s: this erase routine only supports"
+ " NAND devices!\n",
+ mtd_device);
+ }
+ }
+
+ if (!opts->quiet) {
+ int percent = (int)
+ ((unsigned long long)
+ (erase.addr+meminfo->erasesize-opts->offset)
+ * 100 / erase_length);
+
+ /* output progress message only at whole percent
+ * steps to reduce the number of messages printed
+ * on (slow) serial consoles
+ */
+ if (percent != percent_complete) {
+ percent_complete = percent;
+
+ printf("\rErasing at 0x%x -- %3d%% complete.",
+ erase.addr, percent);
+
+ if (opts->jffs2 && result == 0)
+ printf(" Cleanmarker written at 0x%x.",
+ erase.addr);
+ }
+ }
+ }
+ if (!opts->quiet)
+ printf("\n");
+
+ if (nand_block_bad_old) {
+ struct nand_chip *priv_nand = meminfo->priv;
+
+ priv_nand->block_bad = nand_block_bad_old;
+ priv_nand->scan_bbt(meminfo);
+ }
+
+ return 0;
+}
+
+#define MAX_PAGE_SIZE 2048
+#define MAX_OOB_SIZE 64
+
+/*
+ * buffer array used for writing data
+ */
+static unsigned char data_buf[MAX_PAGE_SIZE];
+static unsigned char oob_buf[MAX_OOB_SIZE];
+
+/* OOB layouts to pass into the kernel as default */
+static struct nand_oobinfo none_oobinfo = {
+ .useecc = MTD_NANDECC_OFF,
+};
+
+static struct nand_oobinfo jffs2_oobinfo = {
+ .useecc = MTD_NANDECC_PLACE,
+ .eccbytes = 6,
+ .eccpos = { 0, 1, 2, 3, 6, 7 }
+};
+
+static struct nand_oobinfo yaffs_oobinfo = {
+ .useecc = MTD_NANDECC_PLACE,
+ .eccbytes = 6,
+ .eccpos = { 8, 9, 10, 13, 14, 15}
+};
+
+static struct nand_oobinfo autoplace_oobinfo = {
+ .useecc = MTD_NANDECC_AUTOPLACE
+};
+
+/**
+ * nand_write_opts: - write image to NAND flash with support for various options
+ *
+ * @param meminfo NAND device to erase
+ * @param opts write options (@see nand_write_options)
+ * @return 0 in case of success
+ *
+ * This code is ported from nandwrite.c from Linux mtd utils by
+ * Steven J. Hill and Thomas Gleixner.
+ */
+int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts)
+{
+ int imglen = 0;
+ int pagelen;
+ int baderaseblock;
+ int blockstart = -1;
+ loff_t offs;
+ int readlen;
+ int oobinfochanged = 0;
+ int percent_complete = -1;
+ struct nand_oobinfo old_oobinfo;
+ ulong mtdoffset = opts->offset;
+ ulong erasesize_blockalign;
+ u_char *buffer = opts->buffer;
+ size_t written;
+ int result;
+
+ if (opts->pad && opts->writeoob) {
+ printf("Can't pad when oob data is present.\n");
+ return -1;
+ }
+
+ /* set erasesize to specified number of blocks - to match
+ * jffs2 (virtual) block size */
+ if (opts->blockalign == 0) {
+ erasesize_blockalign = meminfo->erasesize;
+ } else {
+ erasesize_blockalign = meminfo->erasesize * opts->blockalign;
+ }
+
+ /* make sure device page sizes are valid */
+ if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512)
+ && !(meminfo->oobsize == 8 && meminfo->oobblock == 256)
+ && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) {
+ printf("Unknown flash (not normal NAND)\n");
+ return -1;
+ }
+
+ /* read the current oob info */
+ memcpy(&old_oobinfo, &meminfo->oobinfo, sizeof(old_oobinfo));
+
+ /* write without ecc? */
+ if (opts->noecc) {
+ memcpy(&meminfo->oobinfo, &none_oobinfo,
+ sizeof(meminfo->oobinfo));
+ oobinfochanged = 1;
+ }
+
+ /* autoplace ECC? */
+ if (opts->autoplace && (old_oobinfo.useecc != MTD_NANDECC_AUTOPLACE)) {
+
+ memcpy(&meminfo->oobinfo, &autoplace_oobinfo,
+ sizeof(meminfo->oobinfo));
+ oobinfochanged = 1;
+ }
+
+ /* force OOB layout for jffs2 or yaffs? */
+ if (opts->forcejffs2 || opts->forceyaffs) {
+ struct nand_oobinfo *oobsel =
+ opts->forcejffs2 ? &jffs2_oobinfo : &yaffs_oobinfo;
+
+ if (meminfo->oobsize == 8) {
+ if (opts->forceyaffs) {
+ printf("YAFSS cannot operate on "
+ "256 Byte page size\n");
+ goto restoreoob;
+ }
+ /* Adjust number of ecc bytes */
+ jffs2_oobinfo.eccbytes = 3;
+ }
+
+ memcpy(&meminfo->oobinfo, oobsel, sizeof(meminfo->oobinfo));
+ }
+
+ /* get image length */
+ imglen = opts->length;
+ pagelen = meminfo->oobblock
+ + ((opts->writeoob != 0) ? meminfo->oobsize : 0);
+
+ /* check, if file is pagealigned */
+ if ((!opts->pad) && ((imglen % pagelen) != 0)) {
+ printf("Input block length is not page aligned\n");
+ goto restoreoob;
+ }
+
+ /* check, if length fits into device */
+ if (((imglen / pagelen) * meminfo->oobblock)
+ > (meminfo->size - opts->offset)) {
+ printf("Image %d bytes, NAND page %d bytes, "
+ "OOB area %u bytes, device size %u bytes\n",
+ imglen, pagelen, meminfo->oobblock, meminfo->size);
+ printf("Input block does not fit into device\n");
+ goto restoreoob;
+ }
+
+ if (!opts->quiet)
+ printf("\n");
+
+ /* get data from input and write to the device */
+ while (imglen && (mtdoffset < meminfo->size)) {
+
+ WATCHDOG_RESET ();
+
+ /*
+ * new eraseblock, check for bad block(s). Stay in the
+ * loop to be sure if the offset changes because of
+ * a bad block, that the next block that will be
+ * written to is also checked. Thus avoiding errors if
+ * the block(s) after the skipped block(s) is also bad
+ * (number of blocks depending on the blockalign
+ */
+ while (blockstart != (mtdoffset & (~erasesize_blockalign+1))) {
+ blockstart = mtdoffset & (~erasesize_blockalign+1);
+ offs = blockstart;
+ baderaseblock = 0;
+
+ /* check all the blocks in an erase block for
+ * bad blocks */
+ do {
+ int ret = meminfo->block_isbad(meminfo, offs);
+
+ if (ret < 0) {
+ printf("Bad block check failed\n");
+ goto restoreoob;
+ }
+ if (ret == 1) {
+ baderaseblock = 1;
+ if (!opts->quiet)
+ printf("\rBad block at 0x%lx "
+ "in erase block from "
+ "0x%x will be skipped\n",
+ (long) offs,
+ blockstart);
+ }
+
+ if (baderaseblock) {
+ mtdoffset = blockstart
+ + erasesize_blockalign;
+ }
+ offs += erasesize_blockalign
+ / opts->blockalign;
+ } while (offs < blockstart + erasesize_blockalign);
+ }
+
+ readlen = meminfo->oobblock;
+ if (opts->pad && (imglen < readlen)) {
+ readlen = imglen;
+ memset(data_buf + readlen, 0xff,
+ meminfo->oobblock - readlen);
+ }
+
+ /* read page data from input memory buffer */
+ memcpy(data_buf, buffer, readlen);
+ buffer += readlen;
+
+ if (opts->writeoob) {
+ /* read OOB data from input memory block, exit
+ * on failure */
+ memcpy(oob_buf, buffer, meminfo->oobsize);
+ buffer += meminfo->oobsize;
+
+ /* write OOB data first, as ecc will be placed
+ * in there*/
+ result = meminfo->write_oob(meminfo,
+ mtdoffset,
+ meminfo->oobsize,
+ &written,
+ (unsigned char *)
+ &oob_buf);
+
+ if (result != 0) {
+ printf("\nMTD writeoob failure: %d\n",
+ result);
+ goto restoreoob;
+ }
+ imglen -= meminfo->oobsize;
+ }
+
+ /* write out the page data */
+ result = meminfo->write(meminfo,
+ mtdoffset,
+ meminfo->oobblock,
+ &written,
+ (unsigned char *) &data_buf);
+
+ if (result != 0) {
+ printf("writing NAND page at offset 0x%lx failed\n",
+ mtdoffset);
+ goto restoreoob;
+ }
+ imglen -= readlen;
+
+ if (!opts->quiet) {
+ int percent = (int)
+ ((unsigned long long)
+ (opts->length-imglen) * 100
+ / opts->length);
+ /* output progress message only at whole percent
+ * steps to reduce the number of messages printed
+ * on (slow) serial consoles
+ */
+ if (percent != percent_complete) {
+ printf("\rWriting data at 0x%x "
+ "-- %3d%% complete.",
+ mtdoffset, percent);
+ percent_complete = percent;
+ }
+ }
+
+ mtdoffset += meminfo->oobblock;
+ }
+
+ if (!opts->quiet)
+ printf("\n");
+
+restoreoob:
+ if (oobinfochanged) {
+ memcpy(&meminfo->oobinfo, &old_oobinfo,
+ sizeof(meminfo->oobinfo));
+ }
+
+ if (imglen > 0) {
+ printf("Data did not fit into device, due to bad blocks\n");
+ return -1;
+ }
+
+ /* return happy */
+ return 0;
+}
+
+/**
+ * nand_read_opts: - read image from NAND flash with support for various options
+ *
+ * @param meminfo NAND device to erase
+ * @param opts read options (@see struct nand_read_options)
+ * @return 0 in case of success
+ *
+ */
+int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts)
+{
+ int imglen = opts->length;
+ int pagelen;
+ int baderaseblock;
+ int blockstart = -1;
+ int percent_complete = -1;
+ loff_t offs;
+ size_t readlen;
+ ulong mtdoffset = opts->offset;
+ u_char *buffer = opts->buffer;
+ int result;
+
+ /* make sure device page sizes are valid */
+ if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512)
+ && !(meminfo->oobsize == 8 && meminfo->oobblock == 256)
+ && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) {
+ printf("Unknown flash (not normal NAND)\n");
+ return -1;
+ }
+
+ pagelen = meminfo->oobblock
+ + ((opts->readoob != 0) ? meminfo->oobsize : 0);
+
+ /* check, if length is not larger than device */
+ if (((imglen / pagelen) * meminfo->oobblock)
+ > (meminfo->size - opts->offset)) {
+ printf("Image %d bytes, NAND page %d bytes, "
+ "OOB area %u bytes, device size %u bytes\n",
+ imglen, pagelen, meminfo->oobblock, meminfo->size);
+ printf("Input block is larger than device\n");
+ return -1;
+ }
+
+ if (!opts->quiet)
+ printf("\n");
+
+ /* get data from input and write to the device */
+ while (imglen && (mtdoffset < meminfo->size)) {
+
+ WATCHDOG_RESET ();
+
+ /*
+ * new eraseblock, check for bad block(s). Stay in the
+ * loop to be sure if the offset changes because of
+ * a bad block, that the next block that will be
+ * written to is also checked. Thus avoiding errors if
+ * the block(s) after the skipped block(s) is also bad
+ * (number of blocks depending on the blockalign
+ */
+ while (blockstart != (mtdoffset & (~meminfo->erasesize+1))) {
+ blockstart = mtdoffset & (~meminfo->erasesize+1);
+ offs = blockstart;
+ baderaseblock = 0;
+
+ /* check all the blocks in an erase block for
+ * bad blocks */
+ do {
+ int ret = meminfo->block_isbad(meminfo, offs);
+
+ if (ret < 0) {
+ printf("Bad block check failed\n");
+ return -1;
+ }
+ if (ret == 1) {
+ baderaseblock = 1;
+ if (!opts->quiet)
+ printf("\rBad block at 0x%lx "
+ "in erase block from "
+ "0x%x will be skipped\n",
+ (long) offs,
+ blockstart);
+ }
+
+ if (baderaseblock) {
+ mtdoffset = blockstart
+ + meminfo->erasesize;
+ }
+ offs += meminfo->erasesize;
+
+ } while (offs < blockstart + meminfo->erasesize);
+ }
+
+
+ /* read page data to memory buffer */
+ result = meminfo->read(meminfo,
+ mtdoffset,
+ meminfo->oobblock,
+ &readlen,
+ (unsigned char *) &data_buf);
+
+ if (result != 0) {
+ printf("reading NAND page at offset 0x%lx failed\n",
+ mtdoffset);
+ return -1;
+ }
+
+ if (imglen < readlen) {
+ readlen = imglen;
+ }
+
+ memcpy(buffer, data_buf, readlen);
+ buffer += readlen;
+ imglen -= readlen;
+
+ if (opts->readoob) {
+ result = meminfo->read_oob(meminfo,
+ mtdoffset,
+ meminfo->oobsize,
+ &readlen,
+ (unsigned char *)
+ &oob_buf);
+
+ if (result != 0) {
+ printf("\nMTD readoob failure: %d\n",
+ result);
+ return -1;
+ }
+
+
+ if (imglen < readlen) {
+ readlen = imglen;
+ }
+
+ memcpy(buffer, oob_buf, readlen);
+
+ buffer += readlen;
+ imglen -= readlen;
+ }
+
+ if (!opts->quiet) {
+ int percent = (int)
+ ((unsigned long long)
+ (opts->length-imglen) * 100
+ / opts->length);
+ /* output progress message only at whole percent
+ * steps to reduce the number of messages printed
+ * on (slow) serial consoles
+ */
+ if (percent != percent_complete) {
+ if (!opts->quiet)
+ printf("\rReading data from 0x%x "
+ "-- %3d%% complete.",
+ mtdoffset, percent);
+ percent_complete = percent;
+ }
+ }
+
+ mtdoffset += meminfo->oobblock;
+ }
+
+ if (!opts->quiet)
+ printf("\n");
+
+ if (imglen > 0) {
+ printf("Could not read entire image due to bad blocks\n");
+ return -1;
+ }
+
+ /* return happy */
+ return 0;
+}
+
+/******************************************************************************
+ * Support for locking / unlocking operations of some NAND devices
+ *****************************************************************************/
+
+#define NAND_CMD_LOCK 0x2a
+#define NAND_CMD_LOCK_TIGHT 0x2c
+#define NAND_CMD_UNLOCK1 0x23
+#define NAND_CMD_UNLOCK2 0x24
+#define NAND_CMD_LOCK_STATUS 0x7a
+
+/**
+ * nand_lock: Set all pages of NAND flash chip to the LOCK or LOCK-TIGHT
+ * state
+ *
+ * @param meminfo nand mtd instance
+ * @param tight bring device in lock tight mode
+ *
+ * @return 0 on success, -1 in case of error
+ *
+ * The lock / lock-tight command only applies to the whole chip. To get some
+ * parts of the chip lock and others unlocked use the following sequence:
+ *
+ * - Lock all pages of the chip using nand_lock(mtd, 0) (or the lockpre pin)
+ * - Call nand_unlock() once for each consecutive area to be unlocked
+ * - If desired: Bring the chip to the lock-tight state using nand_lock(mtd, 1)
+ *
+ * If the device is in lock-tight state software can't change the
+ * current active lock/unlock state of all pages. nand_lock() / nand_unlock()
+ * calls will fail. It is only posible to leave lock-tight state by
+ * an hardware signal (low pulse on _WP pin) or by power down.
+ */
+int nand_lock(nand_info_t *meminfo, int tight)
+{
+ int ret = 0;
+ int status;
+ struct nand_chip *this = meminfo->priv;
+
+ /* select the NAND device */
+ this->select_chip(meminfo, 0);
+
+ this->cmdfunc(meminfo,
+ (tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK),
+ -1, -1);
+
+ /* call wait ready function */
+ status = this->waitfunc(meminfo, this, FL_WRITING);
+
+ /* see if device thinks it succeeded */
+ if (status & 0x01) {
+ ret = -1;
+ }
+
+ /* de-select the NAND device */
+ this->select_chip(meminfo, -1);
+ return ret;
+}
+
+/**
+ * nand_get_lock_status: - query current lock state from one page of NAND
+ * flash
+ *
+ * @param meminfo nand mtd instance
+ * @param offset page address to query (muss be page aligned!)
+ *
+ * @return -1 in case of error
+ * >0 lock status:
+ * bitfield with the following combinations:
+ * NAND_LOCK_STATUS_TIGHT: page in tight state
+ * NAND_LOCK_STATUS_LOCK: page locked
+ * NAND_LOCK_STATUS_UNLOCK: page unlocked
+ *
+ */
+int nand_get_lock_status(nand_info_t *meminfo, ulong offset)
+{
+ int ret = 0;
+ int chipnr;
+ int page;
+ struct nand_chip *this = meminfo->priv;
+
+ /* select the NAND device */
+ chipnr = (int)(offset >> this->chip_shift);
+ this->select_chip(meminfo, chipnr);
+
+
+ if ((offset & (meminfo->oobblock - 1)) != 0) {
+ printf ("nand_get_lock_status: "
+ "Start address must be beginning of "
+ "nand page!\n");
+ ret = -1;
+ goto out;
+ }
+
+ /* check the Lock Status */
+ page = (int)(offset >> this->page_shift);
+ this->cmdfunc(meminfo, NAND_CMD_LOCK_STATUS, -1, page & this->pagemask);
+
+ ret = this->read_byte(meminfo) & (NAND_LOCK_STATUS_TIGHT
+ | NAND_LOCK_STATUS_LOCK
+ | NAND_LOCK_STATUS_UNLOCK);
+
+ out:
+ /* de-select the NAND device */
+ this->select_chip(meminfo, -1);
+ return ret;
+}
+
+/**
+ * nand_unlock: - Unlock area of NAND pages
+ * only one consecutive area can be unlocked at one time!
+ *
+ * @param meminfo nand mtd instance
+ * @param start start byte address
+ * @param length number of bytes to unlock (must be a multiple of
+ * page size nand->oobblock)
+ *
+ * @return 0 on success, -1 in case of error
+ */
+int nand_unlock(nand_info_t *meminfo, ulong start, ulong length)
+{
+ int ret = 0;
+ int chipnr;
+ int status;
+ int page;
+ struct nand_chip *this = meminfo->priv;
+ printf ("nand_unlock: start: %08x, length: %d!\n",
+ (int)start, (int)length);
+
+ /* select the NAND device */
+ chipnr = (int)(start >> this->chip_shift);
+ this->select_chip(meminfo, chipnr);
+
+ /* check the WP bit */
+ this->cmdfunc(meminfo, NAND_CMD_STATUS, -1, -1);
+ if ((this->read_byte(meminfo) & 0x80) == 0) {
+ printf ("nand_unlock: Device is write protected!\n");
+ ret = -1;
+ goto out;
+ }
+
+ if ((start & (meminfo->oobblock - 1)) != 0) {
+ printf ("nand_unlock: Start address must be beginning of "
+ "nand page!\n");
+ ret = -1;
+ goto out;
+ }
+
+ if (length == 0 || (length & (meminfo->oobblock - 1)) != 0) {
+ printf ("nand_unlock: Length must be a multiple of nand page "
+ "size!\n");
+ ret = -1;
+ goto out;
+ }
+
+ /* submit address of first page to unlock */
+ page = (int)(start >> this->page_shift);
+ this->cmdfunc(meminfo, NAND_CMD_UNLOCK1, -1, page & this->pagemask);
+
+ /* submit ADDRESS of LAST page to unlock */
+ page += (int)(length >> this->page_shift) - 1;
+ this->cmdfunc(meminfo, NAND_CMD_UNLOCK2, -1, page & this->pagemask);
+
+ /* call wait ready function */
+ status = this->waitfunc(meminfo, this, FL_WRITING);
+ /* see if device thinks it succeeded */
+ if (status & 0x01) {
+ /* there was an error */
+ ret = -1;
+ goto out;
+ }
+
+ out:
+ /* de-select the NAND device */
+ this->select_chip(meminfo, -1);
+ return ret;
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) */
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
include $(TOPDIR)/config.mk
-LIB := libnand_legacy.a
+LIB := $(obj)libnand_legacy.a
+
+COBJS := nand_legacy.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
-OBJS := nand_legacy.o
all: $(LIB)
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
+
+#########################################################################
DECLARE_GLOBAL_DATA_PTR;
+#if !defined(CONFIG_CONS_INDEX)
+#error "No console index specified."
+#endif
+
#define CONSOLE CONFIG_CONS_INDEX
static unsigned int calcBitrateRegister( void );
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
- bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
+ bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
+ & 0xffff) + 1;
bar_res = io;
DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
} else {
/* We don't support prefetchable memory for now, so disable */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
+ pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
}
if (pci_io) {
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
+ {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
{}
};
#include <ns87308.h>
#endif
+#if defined (CONFIG_SERIAL_MULTI)
+#include <serial.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_CONS_INDEX)
+#if defined (CONFIG_SERIAL_MULTI)
+/* with CONFIG_SERIAL_MULTI we might have no console
+ * on these devices
+ */
+#else
#error "No console index specified."
+#endif /* CONFIG_SERIAL_MULTI */
#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
#error "Invalid console index value."
#endif
};
#define PORT serial_ports[port-1]
+#if defined(CONFIG_CONS_INDEX)
#define CONSOLE (serial_ports[CONFIG_CONS_INDEX-1])
+#endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+/* Multi serial device functions */
+#define DECLARE_ESERIAL_FUNCTIONS(port) \
+ int eserial##port##_init (void) {\
+ int clock_divisor; \
+ clock_divisor = calc_divisor(serial_ports[port-1]); \
+ NS16550_init(serial_ports[port-1], clock_divisor); \
+ return(0);}\
+ void eserial##port##_setbrg (void) {\
+ serial_setbrg_dev(port);}\
+ int eserial##port##_getc (void) {\
+ return serial_getc_dev(port);}\
+ int eserial##port##_tstc (void) {\
+ return serial_tstc_dev(port);}\
+ void eserial##port##_putc (const char c) {\
+ serial_putc_dev(port, c);}\
+ void eserial##port##_puts (const char *s) {\
+ serial_puts_dev(port, s);}
+
+/* Serial device descriptor */
+#define INIT_ESERIAL_STRUCTURE(port,name,bus) {\
+ name,\
+ bus,\
+ eserial##port##_init,\
+ eserial##port##_setbrg,\
+ eserial##port##_getc,\
+ eserial##port##_tstc,\
+ eserial##port##_putc,\
+ eserial##port##_puts, }
+
+#endif /* CONFIG_SERIAL_MULTI */
static int calc_divisor (NS16550_t port)
{
}
+#if !defined(CONFIG_SERIAL_MULTI)
int serial_init (void)
{
int clock_divisor;
return (0);
}
+#endif
void
_serial_putc(const char c,const int port)
NS16550_reinit(PORT, clock_divisor);
}
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_putc_dev(unsigned int dev_index,const char c)
+{
+ _serial_putc(c,dev_index);
+}
+#else
void
serial_putc(const char c)
{
_serial_putc(c,CONFIG_CONS_INDEX);
}
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_putc_raw_dev(unsigned int dev_index,const char c)
+{
+ _serial_putc_raw(c,dev_index);
+}
+#else
void
serial_putc_raw(const char c)
{
_serial_putc_raw(c,CONFIG_CONS_INDEX);
}
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_puts_dev(unsigned int dev_index,const char *s)
+{
+ _serial_puts(s,dev_index);
+}
+#else
void
serial_puts(const char *s)
{
_serial_puts(s,CONFIG_CONS_INDEX);
}
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+static inline int
+serial_getc_dev(unsigned int dev_index)
+{
+ return _serial_getc(dev_index);
+}
+#else
int
serial_getc(void)
{
return _serial_getc(CONFIG_CONS_INDEX);
}
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+static inline int
+serial_tstc_dev(unsigned int dev_index)
+{
+ return _serial_tstc(dev_index);
+}
+#else
int
serial_tstc(void)
{
return _serial_tstc(CONFIG_CONS_INDEX);
}
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+static inline void
+serial_setbrg_dev(unsigned int dev_index)
+{
+ _serial_setbrg(dev_index);
+}
+#else
void
serial_setbrg(void)
{
_serial_setbrg(CONFIG_CONS_INDEX);
}
+#endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+DECLARE_ESERIAL_FUNCTIONS(1);
+struct serial_device eserial1_device =
+ INIT_ESERIAL_STRUCTURE(1,"eserial0","EUART1");
+DECLARE_ESERIAL_FUNCTIONS(2);
+struct serial_device eserial2_device =
+ INIT_ESERIAL_STRUCTURE(2,"eserial1","EUART2");
+DECLARE_ESERIAL_FUNCTIONS(3);
+struct serial_device eserial3_device =
+ INIT_ESERIAL_STRUCTURE(3,"eserial2","EUART3");
+DECLARE_ESERIAL_FUNCTIONS(4);
+struct serial_device eserial4_device =
+ INIT_ESERIAL_STRUCTURE(4,"eserial3","EUART4");
+#endif /* CONFIG_SERIAL_MULTI */
#endif
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# Makefile for the SysKonnect SK-98xx device driver.
#
+
include $(TOPDIR)/config.mk
-LIB := libsk98lin.a
+LIB := $(obj)libsk98lin.a
+
+COBJS := skge.o skaddr.o skgehwt.o skgeinit.o skgepnmi.o skgesirq.o \
+ ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \
+ skxmac2.o skcsum.o #skproc.o
-OBJS := skge.o skaddr.o skgehwt.o skgeinit.o skgepnmi.o skgesirq.o \
- ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \
- skxmac2.o skcsum.o #skproc.o
+COBJS += uboot_skb.o uboot_drv.o
-OBJS += uboot_skb.o uboot_drv.o
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
# DBGDEF = \
# -DDEBUG
EXTRA_CFLAGS += -I. -DSK_USE_CSUM $(DBGDEF)
CFLAGS += $(EXTRA_CFLAGS)
+HOST_CFLAGS += $(EXTRA_CFLAGS)
all: $(LIB)
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
/*
- * tsec.c
* Freescale Three Speed Ethernet Controller driver
*
* This software may be used and distributed according to the
*/
#include <config.h>
-#include <mpc85xx.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#define TX_BUF_CNT 2
-static uint rxIdx; /* index of the current RX buffer */
-static uint txIdx; /* index of the current TX buffer */
+static uint rxIdx; /* index of the current RX buffer */
+static uint txIdx; /* index of the current TX buffer */
typedef volatile struct rtxbd {
txbd8_t txbd[TX_BUF_CNT];
rxbd8_t rxbd[PKTBUFSRX];
-} RTXBD;
+} RTXBD;
struct tsec_info_struct {
unsigned int phyaddr;
unsigned int phyregidx;
};
-
/* The tsec_info structure contains 3 values which the
* driver uses to determine how to operate a given ethernet
- * device. For now, the structure is initialized with the
- * knowledge that all current implementations have 2 TSEC
- * devices, and one FEC. The information needed is:
+ * device. The information needed is:
* phyaddr - The address of the PHY which is attached to
* the given device.
*
*
* phyregidx - This variable specifies which ethernet device
* controls the MII Management registers which are connected
- * to the PHY. For 8540/8560, only TSEC1 (index 0) has
+ * to the PHY. For now, only TSEC1 (index 0) has
* access to the PHYs, so all of the entries have "0".
*
* The values specified in the table are taken from the board's
* config file in include/configs/. When implementing a new
* board with ethernet capability, it is necessary to define:
- * TSEC1_PHY_ADDR
- * TSEC1_PHYIDX
- * TSEC2_PHY_ADDR
- * TSEC2_PHYIDX
+ * TSECn_PHY_ADDR
+ * TSECn_PHYIDX
*
- * and for 8560:
+ * for n = 1,2,3, etc. And for FEC:
* FEC_PHY_ADDR
* FEC_PHYIDX
*/
static struct tsec_info_struct tsec_info[] = {
#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
+#elif defined(CONFIG_MPC86XX_TSEC1)
+ {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else
- { 0, 0, 0},
+ {0, 0, 0},
#endif
#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
+#elif defined(CONFIG_MPC86XX_TSEC2)
+ {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
#else
- { 0, 0, 0},
+ {0, 0, 0},
#endif
#ifdef CONFIG_MPC85XX_FEC
{FEC_PHY_ADDR, 0, FEC_PHYIDX},
#else
-# if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3)
+#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
-# else
- { 0, 0, 0},
-# endif
-# if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
- {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
-# else
- { 0, 0, 0},
-# endif
+#else
+ {0, 0, 0},
+#endif
+#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
+ {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
+#else
+ {0, 0, 0},
+#endif
#endif
};
#error "rtx must be 64-bit aligned"
#endif
-static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
-static int tsec_recv(struct eth_device* dev);
-static int tsec_init(struct eth_device* dev, bd_t * bd);
-static void tsec_halt(struct eth_device* dev);
-static void init_registers(volatile tsec_t *regs);
+static int tsec_send(struct eth_device *dev,
+ volatile void *packet, int length);
+static int tsec_recv(struct eth_device *dev);
+static int tsec_init(struct eth_device *dev, bd_t * bd);
+static void tsec_halt(struct eth_device *dev);
+static void init_registers(volatile tsec_t * regs);
static void startup_tsec(struct eth_device *dev);
static int init_phy(struct eth_device *dev);
void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
uint read_phy_reg(struct tsec_private *priv, uint regnum);
-struct phy_info * get_phy_info(struct eth_device *dev);
+struct phy_info *get_phy_info(struct eth_device *dev);
void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
static void adjust_link(struct eth_device *dev);
static void relocate_cmds(void);
static int tsec_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
+ unsigned char reg, unsigned short value);
static int tsec_miiphy_read(char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
+ unsigned char reg, unsigned short *value);
/* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
*/
-int tsec_initialize(bd_t *bis, int index, char *devname)
+int tsec_initialize(bd_t * bis, int index, char *devname)
{
- struct eth_device* dev;
+ struct eth_device *dev;
int i;
struct tsec_private *priv;
- dev = (struct eth_device*) malloc(sizeof *dev);
+ dev = (struct eth_device *)malloc(sizeof *dev);
- if(NULL == dev)
+ if (NULL == dev)
return 0;
memset(dev, 0, sizeof *dev);
- priv = (struct tsec_private *) malloc(sizeof(*priv));
+ priv = (struct tsec_private *)malloc(sizeof(*priv));
- if(NULL == priv)
+ if (NULL == priv)
return 0;
privlist[index] = priv;
- priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE);
+ priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
- tsec_info[index].phyregidx*TSEC_SIZE);
+ tsec_info[index].phyregidx *
+ TSEC_SIZE);
priv->phyaddr = tsec_info[index].phyaddr;
priv->flags = tsec_info[index].flags;
sprintf(dev->name, devname);
dev->iobase = 0;
- dev->priv = priv;
- dev->init = tsec_init;
- dev->halt = tsec_halt;
- dev->send = tsec_send;
- dev->recv = tsec_recv;
+ dev->priv = priv;
+ dev->init = tsec_init;
+ dev->halt = tsec_halt;
+ dev->send = tsec_send;
+ dev->recv = tsec_recv;
/* Tell u-boot to get the addr from the env */
- for(i=0;i<6;i++)
+ for (i = 0; i < 6; i++)
dev->enetaddr[i] = 0;
eth_register(dev);
-
/* Reset the MAC */
priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
return init_phy(dev);
}
-
/* Initializes data structures and registers for the controller,
* and brings the interface up. Returns the link status, meaning
* that it returns success if the link is up, failure otherwise.
- * This allows u-boot to find the first active controller. */
-int tsec_init(struct eth_device* dev, bd_t * bd)
+ * This allows u-boot to find the first active controller.
+ */
+int tsec_init(struct eth_device *dev, bd_t * bd)
{
uint tempval;
char tmpbuf[MAC_ADDR_LEN];
/* Copy the station address into the address registers.
* Backwards, because little endian MACS are dumb */
- for(i=0;i<MAC_ADDR_LEN;i++) {
+ for (i = 0; i < MAC_ADDR_LEN; i++) {
tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
}
- regs->macstnaddr1 = *((uint *)(tmpbuf));
+ regs->macstnaddr1 = *((uint *) (tmpbuf));
- tempval = *((uint *)(tmpbuf +4));
+ tempval = *((uint *) (tmpbuf + 4));
regs->macstnaddr2 = tempval;
}
-
/* Write value to the device's PHY through the registers
* specified in priv, modifying the register specified in regnum.
* It will wait for the write to be done (or for a timeout to
{
volatile tsec_t *regbase = priv->phyregs;
uint phyid = priv->phyaddr;
- int timeout=1000000;
+ int timeout = 1000000;
regbase->miimadd = (phyid << 8) | regnum;
regbase->miimcon = value;
asm("sync");
- timeout=1000000;
- while((regbase->miimind & MIIMIND_BUSY) && timeout--);
+ timeout = 1000000;
+ while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
}
-
/* Reads register regnum on the device's PHY through the
* registers specified in priv. It lowers and raises the read
* command, and waits for the data to become valid (miimind
asm("sync");
/* Wait for the the indication that the read is done */
- while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
+ while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
/* Grab the value read from the PHY */
value = regbase->miimstat;
return value;
}
-
/* Discover which PHY is attached to the device, and configure it
* properly. If the PHY is not recognized, then return 0
* (failure). Otherwise, return 1
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct phy_info *curphy;
+ volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
/* Assign a Physical address to the TBI */
-
- {
- volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
- regs->tbipa = TBIPA_VALUE;
- regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
- regs->tbipa = TBIPA_VALUE;
- asm("sync");
- }
+ regs->tbipa = TBIPA_VALUE;
+ regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
+ regs->tbipa = TBIPA_VALUE;
+ asm("sync");
/* Reset MII (due to new addresses) */
priv->phyregs->miimcfg = MIIMCFG_RESET;
asm("sync");
priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
asm("sync");
- while(priv->phyregs->miimind & MIIMIND_BUSY);
+ while (priv->phyregs->miimind & MIIMIND_BUSY) ;
- if(0 == relocated)
+ if (0 == relocated)
relocate_cmds();
/* Get the cmd structure corresponding to the attached
* PHY */
curphy = get_phy_info(dev);
- if(NULL == curphy) {
+ if (curphy == NULL) {
+ priv->phyinfo = NULL;
printf("%s: No PHY found\n", dev->name);
return 0;
return 1;
}
-
-/* Returns which value to write to the control register. */
-/* For 10/100, the value is slightly different */
-uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
+/*
+ * Returns which value to write to the control register.
+ * For 10/100, the value is slightly different
+ */
+uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
{
- if(priv->flags & TSEC_GIGABIT)
+ if (priv->flags & TSEC_GIGABIT)
return MIIM_CONTROL_INIT;
else
return MIIM_CR_INIT;
}
-
/* Parse the status register for link, and then do
- * auto-negotiation */
-uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
+ * auto-negotiation
+ */
+uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
{
/*
- * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
+ * Wait if PHY is capable of autonegotiation and autonegotiation
+ * is not complete.
*/
mii_reg = read_phy_reg(priv, MIIM_STATUS);
- if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
+ if ((mii_reg & PHY_BMSR_AUTN_ABLE)
+ && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
int i = 0;
- puts ("Waiting for PHY auto negotiation to complete");
- while (!((mii_reg & PHY_BMSR_AUTN_COMP) && (mii_reg & MIIM_STATUS_LINK))) {
+ puts("Waiting for PHY auto negotiation to complete");
+ while (!((mii_reg & PHY_BMSR_AUTN_COMP)
+ && (mii_reg & MIIM_STATUS_LINK))) {
/*
* Timeout reached ?
*/
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts (" TIMEOUT !\n");
+ puts(" TIMEOUT !\n");
priv->link = 0;
- break;
+ return 0;
}
if ((i++ % 1000) == 0) {
- putc ('.');
+ putc('.');
}
- udelay (1000); /* 1 ms */
+ udelay(1000); /* 1 ms */
mii_reg = read_phy_reg(priv, MIIM_STATUS);
}
- puts (" done\n");
+ puts(" done\n");
priv->link = 1;
- udelay (500000); /* another 500 ms (results in faster booting) */
+ udelay(500000); /* another 500 ms (results in faster booting) */
} else {
priv->link = 1;
}
return 0;
}
-
/* Parse the 88E1011's status register for speed and duplex
- * information */
-uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv)
+ * information
+ */
+uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
{
uint speed;
(mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
int i = 0;
- puts ("Waiting for PHY realtime link");
+ puts("Waiting for PHY realtime link");
while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
(mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
/*
* Timeout reached ?
*/
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts (" TIMEOUT !\n");
+ puts(" TIMEOUT !\n");
priv->link = 0;
break;
}
if ((i++ % 1000) == 0) {
- putc ('.');
+ putc('.');
}
- udelay (1000); /* 1 ms */
+ udelay(1000); /* 1 ms */
mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
}
- puts (" done\n");
- udelay (500000); /* another 500 ms (results in faster booting) */
+ puts(" done\n");
+ udelay(500000); /* another 500 ms (results in faster booting) */
}
- if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
+ if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
priv->duplexity = 1;
else
priv->duplexity = 0;
- speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED);
+ speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
- switch(speed) {
- case MIIM_88E1011_PHYSTAT_GBIT:
- priv->speed = 1000;
- break;
- case MIIM_88E1011_PHYSTAT_100:
- priv->speed = 100;
- break;
- default:
- priv->speed = 10;
+ switch (speed) {
+ case MIIM_88E1011_PHYSTAT_GBIT:
+ priv->speed = 1000;
+ break;
+ case MIIM_88E1011_PHYSTAT_100:
+ priv->speed = 100;
+ break;
+ default:
+ priv->speed = 10;
}
return 0;
}
-
/* Parse the cis8201's status register for speed and duplex
- * information */
-uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv)
+ * information
+ */
+uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
{
uint speed;
- if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
+ if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
priv->duplexity = 1;
else
priv->duplexity = 0;
speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
- switch(speed) {
- case MIIM_CIS8201_AUXCONSTAT_GBIT:
- priv->speed = 1000;
- break;
- case MIIM_CIS8201_AUXCONSTAT_100:
- priv->speed = 100;
- break;
- default:
- priv->speed = 10;
- break;
+ switch (speed) {
+ case MIIM_CIS8201_AUXCONSTAT_GBIT:
+ priv->speed = 1000;
+ break;
+ case MIIM_CIS8201_AUXCONSTAT_100:
+ priv->speed = 100;
+ break;
+ default:
+ priv->speed = 10;
+ break;
}
return 0;
}
+/* Parse the vsc8244's status register for speed and duplex
+ * information
+ */
+uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
+{
+ uint speed;
+
+ if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
+ priv->duplexity = 1;
+ else
+ priv->duplexity = 0;
+
+ speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
+ switch (speed) {
+ case MIIM_VSC8244_AUXCONSTAT_GBIT:
+ priv->speed = 1000;
+ break;
+ case MIIM_VSC8244_AUXCONSTAT_100:
+ priv->speed = 100;
+ break;
+ default:
+ priv->speed = 10;
+ break;
+ }
+
+ return 0;
+}
/* Parse the DM9161's status register for speed and duplex
- * information */
-uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv)
+ * information
+ */
+uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
{
- if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
+ if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
priv->speed = 100;
else
priv->speed = 10;
- if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
+ if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
priv->duplexity = 1;
else
priv->duplexity = 0;
return 0;
}
-
-/* Hack to write all 4 PHYs with the LED values */
-uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
+/*
+ * Hack to write all 4 PHYs with the LED values
+ */
+uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
{
uint phyid;
volatile tsec_t *regbase = priv->phyregs;
- int timeout=1000000;
+ int timeout = 1000000;
- for(phyid=0;phyid<4;phyid++) {
+ for (phyid = 0; phyid < 4; phyid++) {
regbase->miimadd = (phyid << 8) | mii_reg;
regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
asm("sync");
- timeout=1000000;
- while((regbase->miimind & MIIMIND_BUSY) && timeout--);
+ timeout = 1000000;
+ while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
}
return MIIM_CIS8204_SLEDCON_INIT;
}
-uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv)
+uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
{
if (priv->flags & TSEC_REDUCED)
return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
/* Initialized required registers to appropriate values, zeroing
* those we don't care about (unless zero is bad, in which case,
- * choose a more appropriate value) */
-static void init_registers(volatile tsec_t *regs)
+ * choose a more appropriate value)
+ */
+static void init_registers(volatile tsec_t * regs)
{
/* Clear IEVENT */
regs->ievent = IEVENT_INIT_CLEAR;
}
-
/* Configure maccfg2 based on negotiated speed and duplex
- * reported by PHY handling code */
+ * reported by PHY handling code
+ */
static void adjust_link(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
volatile tsec_t *regs = priv->regs;
- if(priv->link) {
- if(priv->duplexity != 0)
+ if (priv->link) {
+ if (priv->duplexity != 0)
regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
else
regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
- switch(priv->speed) {
- case 1000:
- regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
- | MACCFG2_GMII);
- break;
- case 100:
- case 10:
- regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
- | MACCFG2_MII);
-
- /* If We're in reduced mode, we need
- * to say whether we're 10 or 100 MB.
- */
- if ((priv->speed == 100)
- && (priv->flags & TSEC_REDUCED))
- regs->ecntrl |= ECNTRL_R100;
- else
- regs->ecntrl &= ~(ECNTRL_R100);
- break;
- default:
- printf("%s: Speed was bad\n", dev->name);
- break;
+ switch (priv->speed) {
+ case 1000:
+ regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
+ | MACCFG2_GMII);
+ break;
+ case 100:
+ case 10:
+ regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
+ | MACCFG2_MII);
+
+ /* If We're in reduced mode, we need
+ * to say whether we're 10 or 100 MB.
+ */
+ if ((priv->speed == 100)
+ && (priv->flags & TSEC_REDUCED))
+ regs->ecntrl |= ECNTRL_R100;
+ else
+ regs->ecntrl &= ~(ECNTRL_R100);
+ break;
+ default:
+ printf("%s: Speed was bad\n", dev->name);
+ break;
}
printf("Speed: %d, %s duplex\n", priv->speed,
- (priv->duplexity) ? "full" : "half");
+ (priv->duplexity) ? "full" : "half");
} else {
printf("%s: No link.\n", dev->name);
}
}
-
/* Set up the buffers and their descriptors, and bring up the
- * interface */
+ * interface
+ */
static void startup_tsec(struct eth_device *dev)
{
int i;
for (i = 0; i < PKTBUFSRX; i++) {
rtx.rxbd[i].status = RXBD_EMPTY;
rtx.rxbd[i].length = 0;
- rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
+ rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
}
- rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
+ rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
/* Initialize the TX Buffer Descriptors */
- for(i=0; i<TX_BUF_CNT; i++) {
+ for (i = 0; i < TX_BUF_CNT; i++) {
rtx.txbd[i].status = 0;
rtx.txbd[i].length = 0;
rtx.txbd[i].bufPtr = 0;
}
- rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
+ rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
/* Start up the PHY */
- phy_run_commands(priv, priv->phyinfo->startup);
+ if(priv->phyinfo)
+ phy_run_commands(priv, priv->phyinfo->startup);
adjust_link(dev);
/* Enable Transmit and Receive */
/* This returns the status bits of the device. The return value
* is never checked, and this is what the 8260 driver did, so we
* do the same. Presumably, this would be zero if there were no
- * errors */
-static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
+ * errors
+ */
+static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
{
int i;
int result = 0;
volatile tsec_t *regs = priv->regs;
/* Find an empty buffer descriptor */
- for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+ for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
- debug ("%s: tsec: tx buffers full\n", dev->name);
+ debug("%s: tsec: tx buffers full\n", dev->name);
return result;
}
}
- rtx.txbd[txIdx].bufPtr = (uint)packet;
+ rtx.txbd[txIdx].bufPtr = (uint) packet;
rtx.txbd[txIdx].length = length;
- rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
+ rtx.txbd[txIdx].status |=
+ (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
/* Tell the DMA to go */
regs->tstat = TSTAT_CLEAR_THALT;
/* Wait for buffer to be transmitted */
- for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+ for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
- debug ("%s: tsec: tx error\n", dev->name);
+ debug("%s: tsec: tx error\n", dev->name);
return result;
}
}
return result;
}
-static int tsec_recv(struct eth_device* dev)
+static int tsec_recv(struct eth_device *dev)
{
int length;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
volatile tsec_t *regs = priv->regs;
- while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
+ while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
length = rtx.rxbd[rxIdx].length;
NetReceive(NetRxPackets[rxIdx], length - 4);
} else {
printf("Got error %x\n",
- (rtx.rxbd[rxIdx].status & RXBD_STATS));
+ (rtx.rxbd[rxIdx].status & RXBD_STATS));
}
rtx.rxbd[rxIdx].length = 0;
/* Set the wrap bit if this is the last element in the list */
- rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
+ rtx.rxbd[rxIdx].status =
+ RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
rxIdx = (rxIdx + 1) % PKTBUFSRX;
}
- if(regs->ievent&IEVENT_BSY) {
+ if (regs->ievent & IEVENT_BSY) {
regs->ievent = IEVENT_BSY;
regs->rstat = RSTAT_CLEAR_RHALT;
}
}
-
/* Stop the interface */
-static void tsec_halt(struct eth_device* dev)
+static void tsec_halt(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
volatile tsec_t *regs = priv->regs;
regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
- while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
+ while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
/* Shut down the PHY, as needed */
- phy_run_commands(priv, priv->phyinfo->shutdown);
+ if(priv->phyinfo)
+ phy_run_commands(priv, priv->phyinfo->shutdown);
}
-
struct phy_info phy_info_M88E1011S = {
0x01410c6,
"Marvell 88E1011S",
4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {0x1d, 0x1f, NULL},
- {0x1e, 0x200c, NULL},
- {0x1d, 0x5, NULL},
- {0x1e, 0x0, NULL},
- {0x1e, 0x100, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {0x1d, 0x1f, NULL},
+ {0x1e, 0x200c, NULL},
+ {0x1d, 0x5, NULL},
+ {0x1e, 0x0, NULL},
+ {0x1e, 0x100, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_88E1011_PHY_STATUS, miim_read,
+ &mii_parse_88E1011_psr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
struct phy_info phy_info_M88E1111S = {
0x01410cc,
"Marvell 88E1111S",
4,
- (struct phy_cmd[]) { /* config */
- /* Reset and configure the PHY */
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {0x1d, 0x1f, NULL},
- {0x1e, 0x200c, NULL},
- {0x1d, 0x5, NULL},
- {0x1e, 0x0, NULL},
- {0x1e, 0x100, NULL},
- {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
- {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {0x1d, 0x1f, NULL},
+ {0x1e, 0x200c, NULL},
+ {0x1d, 0x5, NULL},
+ {0x1e, 0x0, NULL},
+ {0x1e, 0x100, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_88E1011_PHY_STATUS, miim_read,
+ &mii_parse_88E1011_psr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
+};
+
+static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
+{
+ uint mii_data = read_phy_reg(priv, mii_reg);
+
+ /* Setting MIIM_88E1145_PHY_EXT_CR */
+ if (priv->flags & TSEC_REDUCED)
+ return mii_data |
+ MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
+ else
+ return mii_data;
+}
+
+static struct phy_info phy_info_M88E1145 = {
+ 0x01410cd,
+ "Marvell 88E1145",
+ 4,
+ (struct phy_cmd[]){ /* config */
+ /* Errata E0, E1 */
+ {29, 0x001b, NULL},
+ {30, 0x418f, NULL},
+ {29, 0x0016, NULL},
+ {30, 0xa2da, NULL},
+
+ /* Reset and configure the PHY */
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+ {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
+ NULL},
+ {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ {MIIM_88E1111_PHY_LED_CONTROL,
+ MIIM_88E1111_PHY_LED_DIRECT, NULL},
+ /* Read the Status */
+ {MIIM_88E1011_PHY_STATUS, miim_read,
+ &mii_parse_88E1011_psr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
struct phy_info phy_info_cis8204 = {
0x3f11,
"Cicada Cis8204",
6,
- (struct phy_cmd[]) { /* config */
- /* Override PHY config settings */
- {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
- {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Read the Status (2x to make sure link is right) */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ /* Override PHY config settings */
+ {MIIM_CIS8201_AUX_CONSTAT,
+ MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
+ &mii_cis8204_fixled},
+ {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
+ &mii_cis8204_setmode},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Read the Status (2x to make sure link is right) */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_CIS8201_AUX_CONSTAT, miim_read,
+ &mii_parse_cis8201},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
/* Cicada 8201 */
0xfc41,
"CIS8201",
4,
- (struct phy_cmd[]) { /* config */
- /* Override PHY config settings */
- {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
- /* Set up the interface mode */
- {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Read the Status (2x to make sure link is right) */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ /* Override PHY config settings */
+ {MIIM_CIS8201_AUX_CONSTAT,
+ MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
+ /* Set up the interface mode */
+ {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
+ NULL},
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Read the Status (2x to make sure link is right) */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_CIS8201_AUX_CONSTAT, miim_read,
+ &mii_parse_cis8201},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
+};
+struct phy_info phy_info_VSC8244 = {
+ 0x3f1b,
+ "Vitesse VSC8244",
+ 6,
+ (struct phy_cmd[]){ /* config */
+ /* Override PHY config settings */
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Read the Status (2x to make sure link is right) */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_VSC8244_AUX_CONSTAT, miim_read,
+ &mii_parse_vsc8244},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
-
struct phy_info phy_info_dm9161 = {
0x0181b88,
"Davicom DM9161E",
4,
- (struct phy_cmd[]) { /* config */
- {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
- /* Do not bypass the scrambler/descrambler */
- {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
- /* Clear 10BTCSR to default */
- {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
- /* Configure some basic stuff */
- {MIIM_CONTROL, MIIM_CR_INIT, NULL},
- /* Restart Auto Negotiation */
- {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the status */
- {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
+ /* Do not bypass the scrambler/descrambler */
+ {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
+ /* Clear 10BTCSR to default */
+ {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
+ NULL},
+ /* Configure some basic stuff */
+ {MIIM_CONTROL, MIIM_CR_INIT, NULL},
+ /* Restart Auto Negotiation */
+ {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the status */
+ {MIIM_DM9161_SCSR, miim_read,
+ &mii_parse_dm9161_scsr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
0x0001378e,
"LXT971",
4,
- (struct phy_cmd []) { /* config */
- { MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */
- { miim_end, }
- },
- (struct phy_cmd []) { /* startup - enable interrupts */
- /* { 0x12, 0x00f2, NULL }, */
- { MIIM_STATUS, miim_read, NULL },
- { MIIM_STATUS, miim_read, &mii_parse_sr },
- { MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 },
- { miim_end, }
- },
- (struct phy_cmd []) { /* shutdown - disable interrupts */
- { miim_end, }
- },
+ (struct phy_cmd[]){ /* config */
+ {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup - enable interrupts */
+ /* { 0x12, 0x00f2, NULL }, */
+ {MIIM_STATUS, miim_read, NULL},
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown - disable interrupts */
+ {miim_end,}
+ },
};
/* Parse the DP83865's link and auto-neg status register for speed and duplex
- * information */
+ * information
+ */
uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
{
switch (mii_reg & MIIM_DP83865_SPD_MASK) {
0x20005c7,
"NatSemi DP83865",
4,
- (struct phy_cmd[]) { /* config */
- {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* startup */
- /* Status is read once to clear old link state */
- {MIIM_STATUS, miim_read, NULL},
- /* Auto-negotiate */
- {MIIM_STATUS, miim_read, &mii_parse_sr},
- /* Read the link and auto-neg status */
- {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
- {miim_end,}
- },
- (struct phy_cmd[]) { /* shutdown */
- {miim_end,}
- },
+ (struct phy_cmd[]){ /* config */
+ {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* startup */
+ /* Status is read once to clear old link state */
+ {MIIM_STATUS, miim_read, NULL},
+ /* Auto-negotiate */
+ {MIIM_STATUS, miim_read, &mii_parse_sr},
+ /* Read the link and auto-neg status */
+ {MIIM_DP83865_LANR, miim_read,
+ &mii_parse_dp83865_lanr},
+ {miim_end,}
+ },
+ (struct phy_cmd[]){ /* shutdown */
+ {miim_end,}
+ },
};
struct phy_info *phy_info[] = {
&phy_info_cis8204,
&phy_info_M88E1011S,
&phy_info_M88E1111S,
+ &phy_info_M88E1145,
&phy_info_dm9161,
&phy_info_lxt971,
+ &phy_info_VSC8244,
&phy_info_dp83865,
NULL
};
-
/* Grab the identifier of the device's PHY, and search through
* all of the known PHYs to see if one matches. If so, return
- * it, if not, return NULL */
-struct phy_info * get_phy_info(struct eth_device *dev)
+ * it, if not, return NULL
+ */
+struct phy_info *get_phy_info(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
uint phy_reg, phy_ID;
/* loop through all the known PHY types, and find one that */
/* matches the ID we read from the PHY. */
- for(i=0; phy_info[i]; i++) {
- if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
+ for (i = 0; phy_info[i]; i++) {
+ if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
theInfo = phy_info[i];
}
- if(theInfo == NULL)
- {
+ if (theInfo == NULL) {
printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
return NULL;
} else {
return theInfo;
}
-
/* Execute the given series of commands on the given device's
- * PHY, running functions as necessary*/
+ * PHY, running functions as necessary
+ */
void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
{
int i;
phyregs->miimcfg = MIIMCFG_INIT_VALUE;
- while(phyregs->miimind & MIIMIND_BUSY);
+ while (phyregs->miimind & MIIMIND_BUSY) ;
- for(i=0;cmd->mii_reg != miim_end;i++) {
- if(cmd->mii_data == miim_read) {
+ for (i = 0; cmd->mii_reg != miim_end; i++) {
+ if (cmd->mii_data == miim_read) {
result = read_phy_reg(priv, cmd->mii_reg);
- if(cmd->funct != NULL)
- (*(cmd->funct))(result, priv);
+ if (cmd->funct != NULL)
+ (*(cmd->funct)) (result, priv);
} else {
- if(cmd->funct != NULL)
- result = (*(cmd->funct))(cmd->mii_reg, priv);
+ if (cmd->funct != NULL)
+ result = (*(cmd->funct)) (cmd->mii_reg, priv);
else
result = cmd->mii_data;
}
}
-
/* Relocate the function pointers in the phy cmd lists */
static void relocate_cmds(void)
{
struct phy_cmd **cmdlistptr;
struct phy_cmd *cmd;
- int i,j,k;
+ int i, j, k;
- for(i=0; phy_info[i]; i++) {
+ for (i = 0; phy_info[i]; i++) {
/* First thing's first: relocate the pointers to the
* PHY command structures (the structs were done) */
- phy_info[i] = (struct phy_info *) ((uint)phy_info[i]
- + gd->reloc_off);
+ phy_info[i] = (struct phy_info *)((uint) phy_info[i]
+ + gd->reloc_off);
phy_info[i]->name += gd->reloc_off;
phy_info[i]->config =
- (struct phy_cmd *)((uint)phy_info[i]->config
- + gd->reloc_off);
+ (struct phy_cmd *)((uint) phy_info[i]->config
+ + gd->reloc_off);
phy_info[i]->startup =
- (struct phy_cmd *)((uint)phy_info[i]->startup
- + gd->reloc_off);
+ (struct phy_cmd *)((uint) phy_info[i]->startup
+ + gd->reloc_off);
phy_info[i]->shutdown =
- (struct phy_cmd *)((uint)phy_info[i]->shutdown
- + gd->reloc_off);
+ (struct phy_cmd *)((uint) phy_info[i]->shutdown
+ + gd->reloc_off);
cmdlistptr = &phy_info[i]->config;
- j=0;
- for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) {
- k=0;
- for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) {
+ j = 0;
+ for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
+ k = 0;
+ for (cmd = *cmdlistptr;
+ cmd->mii_reg != miim_end;
+ cmd++) {
/* Only relocate non-NULL pointers */
- if(cmd->funct)
+ if (cmd->funct)
cmd->funct += gd->reloc_off;
k++;
relocated = 1;
}
-
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
&& !defined(BITBANGMII)
-struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
+struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
{
int i;
- for(i=0;i<MAXCONTROLLERS;i++) {
- if(privlist[i]->phyaddr == phyaddr)
+ for (i = 0; i < MAXCONTROLLERS; i++) {
+ if (privlist[i]->phyaddr == phyaddr)
return privlist[i];
}
* 0 on success
*/
static int tsec_miiphy_read(char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value)
+ unsigned char reg, unsigned short *value)
{
unsigned short ret;
struct tsec_private *priv = get_priv_for_phy(addr);
- if(NULL == priv) {
+ if (NULL == priv) {
printf("Can't read PHY at address %d\n", addr);
return -1;
}
* 0 on success
*/
static int tsec_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
+ unsigned char reg, unsigned short value)
{
struct tsec_private *priv = get_priv_for_phy(addr);
- if(NULL == priv) {
+ if (NULL == priv) {
printf("Can't write PHY at address %d\n", addr);
return -1;
}
#define TSEC_SIZE 0x01000
/* FIXME: Should these be pushed back to 83xx and 85xx config files? */
-#if defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
#define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
#elif defined(CONFIG_MPC83XX)
#define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
#define MIIM_GBIT_CON 0x09
#define MIIM_GBIT_CON_ADVERT 0x0e00
+/* Entry for Vitesse VSC8244 regs starts here */
+/* Vitesse VSC8244 Auxiliary Control/Status Register */
+#define MIIM_VSC8244_AUX_CONSTAT 0x1c
+#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000
+#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020
+#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018
+#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010
+#define MIIM_VSC8244_AUXCONSTAT_100 0x0008
+#define MIIM_CONTROL_INIT_LOOPBACK 0x4000
+
+/* Vitesse VSC8244 Extended PHY Control Register 1 */
+#define MIIM_VSC8244_EPHY_CON 0x17
+#define MIIM_VSC8244_EPHYCON_INIT 0x0006
+
+/* Vitesse VSC8244 Serial LED Control Register */
+#define MIIM_VSC8244_LED_CON 0x1b
+#define MIIM_VSC8244_LEDCON_INIT 0xF011
+
/* 88E1011 PHY Status Register */
#define MIIM_88E1011_PHY_STATUS 0x11
#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
#define MIIM_88E1011_PHYSTAT_LINK 0x0400
+#define MIIM_88E1011_PHY_SCR 0x10
+#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
+
+/* 88E1111 PHY LED Control Register */
+#define MIIM_88E1111_PHY_LED_CONTROL 24
+#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
+#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
+
+/* 88E1145 Extended PHY Specific Control Register */
+#define MIIM_88E1145_PHY_EXT_CR 20
+#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
+#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
+
+#define MIIM_88E1145_PHY_PAGE 29
+#define MIIM_88E1145_PHY_CAL_OV 30
+
+
/* DM9161 Control register values */
#define MIIM_DM9161_CR_STOP 0x0400
#define MIIM_DM9161_CR_RSTAN 0x1200
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2001
# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
#
#CFLAGS += -DDEBUG
-LIB = libdtt.a
+LIB = $(obj)libdtt.a
+
+COBJS = lm75.o ds1621.o adm1021.o
-OBJS = lm75.o ds1621.o adm1021.o
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
-$(LIB): $(START) $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
/*
* Setup configuraton register
*/
+#ifdef CONFIG_DTT_AD7414
+ /* config = alert active low and disabled */
+ val = 0x60;
+#else
/* config = 6 sample integration, int mode, active low, and enable */
val = 0x18;
+#endif
if (dtt_write(sensor, DTT_CONFIG, val) != 0)
return 1;
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
LOAD_ADDR = 0x1000
endif
+ifeq ($(ARCH),avr32)
+LOAD_ADDR = 0x00000000
+endif
+
include $(TOPDIR)/config.mk
+ELF = hello_world
SREC = hello_world.srec
-BIN = hello_world.bin hello_world
+BIN = hello_world.bin
ifeq ($(CPU),mpc8xx)
+ELF = test_burst
SREC = test_burst.srec
-BIN = test_burst.bin test_burst
+BIN = test_burst.bin
endif
ifeq ($(ARCH),i386)
-SREC += 82559_eeprom.srec
-BIN += 82559_eeprom.bin 82559_eeprom
+ELF += 82559_eeprom
+SREC += 82559_eeprom.srec
+BIN += 82559_eeprom.bin
endif
ifeq ($(ARCH),ppc)
-SREC += sched.srec
-BIN += sched.bin sched
+ELF += sched
+SREC += sched.srec
+BIN += sched.bin
endif
ifeq ($(ARCH),blackfin)
+ELF += smc91111_eeprom
SREC += smc91111_eeprom.srec
-BIN += smc91111_eeprom.bin smc91111_eeprom
+BIN += smc91111_eeprom.bin
endif
# The following example is pretty 8xx specific...
ifeq ($(CPU),mpc8xx)
-SREC += timer.srec
-BIN += timer.bin timer
+ELF += timer
+SREC += timer.srec
+BIN += timer.bin
endif
# The following example is 8260 specific...
ifeq ($(CPU),mpc8260)
-SREC += mem_to_mem_idma2intr.srec
-BIN += mem_to_mem_idma2intr.bin mem_to_mem_idma2intr
+ELF += mem_to_mem_idma2intr
+SREC += mem_to_mem_idma2intr.srec
+BIN += mem_to_mem_idma2intr.bin
+endif
+
+# Demo for 52xx IRQs
+ifeq ($(CPU),mpc5xxx)
+ELF += interrupt
+SREC += interrupt.srec
+BIN += interrupt.bin
endif
# Utility for resetting i82559 EEPROM
ifeq ($(BOARD),oxc)
-SREC += eepro100_eeprom.srec
-BIN += eepro100_eeprom.bin eepro100_eeprom
+ELF += eepro100_eeprom
+SREC += eepro100_eeprom.srec
+BIN += eepro100_eeprom.bin
endif
ifeq ($(BIG_ENDIAN),y)
EX_LDFLAGS += -EB
endif
-OBJS = $(SREC:.srec=.o)
+COBJS := $(SREC:.srec=.o)
-LIB = libstubs.a
+LIB = $(obj)libstubs.a
LIBAOBJS=
ifeq ($(ARCH),ppc)
LIBAOBJS+= $(ARCH)_longjmp.o $(ARCH)_setjmp.o
LIBAOBJS+= test_burst_lib.o
endif
LIBCOBJS= stubs.o
-LIBOBJS = $(LIBAOBJS) $(LIBCOBJS)
+
+LIBOBJS = $(addprefix $(obj),$(LIBAOBJS) $(LIBCOBJS))
+
+SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(if $(LIBAOBJS),$(LIBAOBJS:.o=.S))
+OBJS := $(addprefix $(obj),$(COBJS))
+ELF := $(addprefix $(obj),$(ELF))
+BIN := $(addprefix $(obj),$(BIN))
+SREC := $(addprefix $(obj),$(SREC))
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`)
CPPFLAGS += -I..
-all: .depend $(OBJS) $(LIB) $(SREC) $(BIN)
+all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF)
#########################################################################
-$(LIB): .depend $(LIBOBJS)
- $(AR) crv $@ $(LIBOBJS)
+$(LIB): $(obj).depend $(LIBOBJS)
+ $(AR) $(ARFLAGS) $@ $(LIBOBJS)
+
+$(ELF):
+$(obj)%: $(obj)%.o $(LIB)
+ $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \
+ -o $@ -e $(notdir $(<:.o=)) $< $(LIB) \
+ -L$(gcclibdir) -lgcc
-%: %.o $(LIB)
- $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \
- -o $@ -e $(<:.o=) $< $(LIB) \
- -L$(gcclibdir) -lgcc
-%.srec: %
- $(OBJCOPY) -O srec $< $@ 2>/dev/null
+$(SREC):
+$(obj)%.srec: $(obj)%
+ $(OBJCOPY) -O srec $< $@ 2>/dev/null
-%.bin: %
- $(OBJCOPY) -O binary $< $@ 2>/dev/null
+$(BIN):
+$(obj)%.bin: $(obj)%
+ $(OBJCOPY) -O binary $< $@ 2>/dev/null
#########################################################################
-.depend: Makefile $(OBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This is a very simple standalone application demonstrating
+ * catching IRQs on the MPC52xx architecture.
+ *
+ * The interrupt to be intercepted can be specified as an argument
+ * to the application. Specifying nothing will intercept IRQ1 on the
+ * MPC5200 platform. On the CR825 carrier board from MicroSys this
+ * maps to the ABORT switch :)
+ *
+ * Note that the specified vector is only a logical number specified
+ * by the respective header file.
+ */
+
+#include <common.h>
+#include <exports.h>
+#include <config.h>
+
+#if defined(CONFIG_MPC5xxx)
+#define DFL_IRQ MPC5XXX_IRQ1
+#else
+#define DFL_IRQ 0
+#endif
+
+static void irq_handler (void *arg);
+
+int interrupt (int argc, char *argv[])
+{
+ int c, irq = -1;
+
+ app_startup (argv);
+
+ if (argc > 1)
+ irq = simple_strtoul (argv[1], NULL, 0);
+ if ((irq < 0) || (irq > NR_IRQS))
+ irq = DFL_IRQ;
+
+ printf ("Installing handler for irq vector %d and doing busy wait\n",
+ irq);
+ printf ("Press 'q' to quit\n");
+
+ /* Install interrupt handler */
+ install_hdlr (irq, irq_handler, NULL);
+ while ((c = getc ()) != 'q') {
+ printf ("Ok, ok, I am still alive!\n");
+ }
+
+ free_hdlr (irq);
+ printf ("\nInterrupt handler has been uninstalled\n");
+
+ return (0);
+}
+
+/*
+ * Handler for interrupt
+ */
+static void irq_handler (void *arg)
+{
+ /* just for demonstration */
+ printf ("+");
+}
" P0 = [P0 + %1]\n" \
" JUMP (P0)\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0");
+#elif defined(CONFIG_AVR32)
+/*
+ * r6 holds the pointer to the global_data. r8 is call clobbered.
+ */
+#define EXPORT_FUNC(x) \
+ asm volatile( \
+ " .globl\t" #x "\n" \
+ #x ":\n" \
+ " ld.w r8, r6[%0]\n" \
+ " ld.w pc, r8[%1]\n" \
+ : \
+ : "i"(offsetof(gd_t, jt)), "i"(XF_ ##x) \
+ : "r8");
#else
#error stubs definition missing for this architecture
#endif
#
-# (C) Copyright 2000, 2001
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
SUBDIRS := jffs2 cramfs fdos fat reiserfs ext2
-.depend all:
+$(obj).depend all:
@for dir in $(SUBDIRS) ; do \
$(MAKE) -C $$dir $@ ; done
#
-# (C) Copyright 2000, 2001
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = libcramfs.a
+LIB = $(obj)libcramfs.a
AOBJS =
COBJS = cramfs.o uncompress.o
-OBJS = $(AOBJS) $(COBJS)
+
+SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
#CPPFLAGS +=
all: $(LIB) $(AOBJS)
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2003
# Pavel Bartusek, Sysgo Real-Time Solutions AG, pba@sysgo.de
#
include $(TOPDIR)/config.mk
-LIB = libext2fs.a
+LIB = $(obj)libext2fs.a
AOBJS =
COBJS = ext2fs.o dev.o
-OBJS = $(AOBJS) $(COBJS)
+
+SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
#CPPFLAGS +=
all: $(LIB) $(AOBJS)
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
-
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
# MA 02111-1307 USA
#
-TOPDIR=../../
-
include $(TOPDIR)/config.mk
-LIB = libfat.a
+LIB = $(obj)libfat.a
AOBJS =
COBJS = fat.o file.o
-OBJS = $(AOBJS) $(COBJS)
+SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
all: $(LIB) $(AOBJS)
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2002
# Stäubli Faverges - <www.staubli.com>
# Pierre AUBERT p.aubert@staubli.com
include $(TOPDIR)/config.mk
-LIB = libfdos.a
+LIB = $(obj)libfdos.a
AOBJS =
COBJS = fat.o vfat.o dev.o fdos.o fs.o subdir.o
-OBJS = $(AOBJS) $(COBJS)
+
+SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
#CPPFLAGS +=
all: $(LIB) $(AOBJS)
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000, 2001
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = libjffs2.a
+LIB = $(obj)libjffs2.a
AOBJS =
COBJS = jffs2_1pass.o compr_rtime.o compr_rubin.o compr_zlib.o mini_inflate.o
COBJS += compr_lzo.o compr_lzari.o
-OBJS = $(AOBJS) $(COBJS)
+
+SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
#CPPFLAGS +=
all: $(LIB) $(AOBJS)
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2003
# Pavel Bartusek, Sysgo Real-Time Solutions AG, pba@sysgo.de
#
include $(TOPDIR)/config.mk
-LIB = libreiserfs.a
+LIB = $(obj)libreiserfs.a
AOBJS =
COBJS = reiserfs.o dev.o mode_string.o
-OBJS = $(AOBJS) $(COBJS)
+
+SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
#CPPFLAGS +=
all: $(LIB) $(AOBJS)
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
-
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#define MAL_ESR_PBEI 0x00000001
/* ^^ ^^ */
/* Mal IER */
-#ifdef CONFIG_440SPE
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define MAL_IER_PT 0x00000080
#define MAL_IER_PRE 0x00000040
#define MAL_IER_PWE 0x00000020
#ifndef _440_i2c_h_
#define _440_i2c_h_
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
#else
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
EXPORT_FUNC(get_timer)
EXPORT_FUNC(vprintf)
EXPORT_FUNC(do_reset)
+EXPORT_FUNC(getenv)
+EXPORT_FUNC(setenv)
+EXPORT_FUNC(simple_strtoul)
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
EXPORT_FUNC(i2c_write)
EXPORT_FUNC(i2c_read)
--- /dev/null
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Author: Jason Jin<Jason.jin@freescale.com>
+ * Zhang Wei<wei.zhang@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef _AHCI_H_
+#define _AHCI_H_
+
+#define AHCI_PCI_BAR 0x24
+#define AHCI_MAX_SG 56 /* hardware max is 64K */
+#define AHCI_CMD_SLOT_SZ 32
+#define AHCI_RX_FIS_SZ 256
+#define AHCI_CMD_TBL_HDR 0x80
+#define AHCI_CMD_TBL_CDB 0x40
+#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
+#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \
+ + AHCI_RX_FIS_SZ
+#define AHCI_CMD_ATAPI (1 << 5)
+#define AHCI_CMD_WRITE (1 << 6)
+#define AHCI_CMD_PREFETCH (1 << 7)
+#define AHCI_CMD_RESET (1 << 8)
+#define AHCI_CMD_CLR_BUSY (1 << 10)
+
+#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
+
+/* Global controller registers */
+#define HOST_CAP 0x00 /* host capabilities */
+#define HOST_CTL 0x04 /* global host control */
+#define HOST_IRQ_STAT 0x08 /* interrupt status */
+#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
+#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
+
+/* HOST_CTL bits */
+#define HOST_RESET (1 << 0) /* reset controller; self-clear */
+#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
+#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
+
+/* Registers for each SATA port */
+#define PORT_LST_ADDR 0x00 /* command list DMA addr */
+#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
+#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
+#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
+#define PORT_IRQ_STAT 0x10 /* interrupt status */
+#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
+#define PORT_CMD 0x18 /* port command */
+#define PORT_TFDATA 0x20 /* taskfile data */
+#define PORT_SIG 0x24 /* device TF signature */
+#define PORT_CMD_ISSUE 0x38 /* command issue */
+#define PORT_SCR 0x28 /* SATA phy register block */
+#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
+#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
+#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
+#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
+
+/* PORT_IRQ_{STAT,MASK} bits */
+#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
+#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
+#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
+#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
+#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
+#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
+#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
+#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
+
+#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
+#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
+#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
+#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
+#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
+#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
+#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
+#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
+#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
+
+#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
+ | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
+
+#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
+ | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
+ | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
+ | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
+ | PORT_IRQ_D2H_REG_FIS
+
+/* PORT_CMD bits */
+#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
+#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
+#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
+#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
+#define PORT_CMD_CLO (1 << 3) /* Command list override */
+#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
+#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
+#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
+
+#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
+#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
+#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
+
+#define AHCI_MAX_PORTS 32
+
+/* SETFEATURES stuff */
+#define SETFEATURES_XFER 0x03
+#define XFER_UDMA_7 0x47
+#define XFER_UDMA_6 0x46
+#define XFER_UDMA_5 0x45
+#define XFER_UDMA_4 0x44
+#define XFER_UDMA_3 0x43
+#define XFER_UDMA_2 0x42
+#define XFER_UDMA_1 0x41
+#define XFER_UDMA_0 0x40
+#define XFER_MW_DMA_2 0x22
+#define XFER_MW_DMA_1 0x21
+#define XFER_MW_DMA_0 0x20
+#define XFER_SW_DMA_2 0x12
+#define XFER_SW_DMA_1 0x11
+#define XFER_SW_DMA_0 0x10
+#define XFER_PIO_4 0x0C
+#define XFER_PIO_3 0x0B
+#define XFER_PIO_2 0x0A
+#define XFER_PIO_1 0x09
+#define XFER_PIO_0 0x08
+#define XFER_PIO_SLOW 0x00
+
+#define ATA_FLAG_SATA (1 << 3)
+#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */
+#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */
+#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */
+#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */
+#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */
+
+struct ahci_cmd_hdr {
+ u32 opts;
+ u32 status;
+ u32 tbl_addr;
+ u32 tbl_addr_hi;
+ u32 reserved[4];
+};
+
+struct ahci_sg {
+ u32 addr;
+ u32 addr_hi;
+ u32 reserved;
+ u32 flags_size;
+};
+
+struct ahci_ioports {
+ u32 cmd_addr;
+ u32 scr_addr;
+ u32 port_mmio;
+ struct ahci_cmd_hdr *cmd_slot;
+ struct ahci_sg *cmd_tbl_sg;
+ u32 cmd_tbl;
+ u32 rx_fis;
+};
+
+struct ahci_probe_ent {
+ pci_dev_t dev;
+ struct ahci_ioports port[AHCI_MAX_PORTS];
+ u32 n_ports;
+ u32 hard_port_no;
+ u32 host_flags;
+ u32 host_set_flags;
+ u32 mmio_base;
+ u32 pio_mask;
+ u32 udma_mask;
+ u32 flags;
+ u32 cap; /* cache of HOST_CAP register */
+ u32 port_map; /* cache of HOST_PORTS_IMPL reg */
+ u32 link_port_map; /*linkup port map*/
+};
+
+#endif
#ifndef __ARM925T_H__
#define __ARM925T_H__
-void gpioreserve(ushort mask);
-void gpiosetdir(ushort mask, ushort in);
-void gpiosetout(ushort mask, ushort out);
-void gpioinit(void);
void archflashwp(void *archdata, int wp);
#endif /*__ARM925T_H__*/
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_ADDRSPACE_H
+#define __ASM_AVR32_ADDRSPACE_H
+
+/* Memory segments when segmentation is enabled */
+#define P0SEG 0x00000000
+#define P1SEG 0x80000000
+#define P2SEG 0xa0000000
+#define P3SEG 0xc0000000
+#define P4SEG 0xe0000000
+
+/* Returns the privileged segment base of a given address */
+#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
+
+/* Returns the physical address of a PnSEG (n=1,2) address */
+#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
+
+/*
+ * Map an address to a certain privileged segment
+ */
+#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
+#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
+#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
+#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
+
+#endif /* __ASM_AVR32_ADDRSPACE_H */
--- /dev/null
+/*
+ * Register definition for the High-speed Bus Matrix
+ */
+#ifndef __ASM_AVR32_HMATRIX2_H__
+#define __ASM_AVR32_HMATRIX2_H__
+
+/* HMATRIX2 register offsets */
+#define HMATRIX2_MCFG0 0x0000
+#define HMATRIX2_MCFG1 0x0004
+#define HMATRIX2_MCFG2 0x0008
+#define HMATRIX2_MCFG3 0x000c
+#define HMATRIX2_MCFG4 0x0010
+#define HMATRIX2_MCFG5 0x0014
+#define HMATRIX2_MCFG6 0x0018
+#define HMATRIX2_MCFG7 0x001c
+#define HMATRIX2_MCFG8 0x0020
+#define HMATRIX2_MCFG9 0x0024
+#define HMATRIX2_MCFG10 0x0028
+#define HMATRIX2_MCFG11 0x002c
+#define HMATRIX2_MCFG12 0x0030
+#define HMATRIX2_MCFG13 0x0034
+#define HMATRIX2_MCFG14 0x0038
+#define HMATRIX2_MCFG15 0x003c
+#define HMATRIX2_SCFG0 0x0040
+#define HMATRIX2_SCFG1 0x0044
+#define HMATRIX2_SCFG2 0x0048
+#define HMATRIX2_SCFG3 0x004c
+#define HMATRIX2_SCFG4 0x0050
+#define HMATRIX2_SCFG5 0x0054
+#define HMATRIX2_SCFG6 0x0058
+#define HMATRIX2_SCFG7 0x005c
+#define HMATRIX2_SCFG8 0x0060
+#define HMATRIX2_SCFG9 0x0064
+#define HMATRIX2_SCFG10 0x0068
+#define HMATRIX2_SCFG11 0x006c
+#define HMATRIX2_SCFG12 0x0070
+#define HMATRIX2_SCFG13 0x0074
+#define HMATRIX2_SCFG14 0x0078
+#define HMATRIX2_SCFG15 0x007c
+#define HMATRIX2_PRAS0 0x0080
+#define HMATRIX2_PRBS0 0x0084
+#define HMATRIX2_PRAS1 0x0088
+#define HMATRIX2_PRBS1 0x008c
+#define HMATRIX2_PRAS2 0x0090
+#define HMATRIX2_PRBS2 0x0094
+#define HMATRIX2_PRAS3 0x0098
+#define HMATRIX2_PRBS3 0x009c
+#define HMATRIX2_PRAS4 0x00a0
+#define HMATRIX2_PRBS4 0x00a4
+#define HMATRIX2_PRAS5 0x00a8
+#define HMATRIX2_PRBS5 0x00ac
+#define HMATRIX2_PRAS6 0x00b0
+#define HMATRIX2_PRBS6 0x00b4
+#define HMATRIX2_PRAS7 0x00b8
+#define HMATRIX2_PRBS7 0x00bc
+#define HMATRIX2_PRAS8 0x00c0
+#define HMATRIX2_PRBS8 0x00c4
+#define HMATRIX2_PRAS9 0x00c8
+#define HMATRIX2_PRBS9 0x00cc
+#define HMATRIX2_PRAS10 0x00d0
+#define HMATRIX2_PRBS10 0x00d4
+#define HMATRIX2_PRAS11 0x00d8
+#define HMATRIX2_PRBS11 0x00dc
+#define HMATRIX2_PRAS12 0x00e0
+#define HMATRIX2_PRBS12 0x00e4
+#define HMATRIX2_PRAS13 0x00e8
+#define HMATRIX2_PRBS13 0x00ec
+#define HMATRIX2_PRAS14 0x00f0
+#define HMATRIX2_PRBS14 0x00f4
+#define HMATRIX2_PRAS15 0x00f8
+#define HMATRIX2_PRBS15 0x00fc
+#define HMATRIX2_MRCR 0x0100
+#define HMATRIX2_SFR0 0x0110
+#define HMATRIX2_SFR1 0x0114
+#define HMATRIX2_SFR2 0x0118
+#define HMATRIX2_SFR3 0x011c
+#define HMATRIX2_SFR4 0x0120
+#define HMATRIX2_SFR5 0x0124
+#define HMATRIX2_SFR6 0x0128
+#define HMATRIX2_SFR7 0x012c
+#define HMATRIX2_SFR8 0x0130
+#define HMATRIX2_SFR9 0x0134
+#define HMATRIX2_SFR10 0x0138
+#define HMATRIX2_SFR11 0x013c
+#define HMATRIX2_SFR12 0x0140
+#define HMATRIX2_SFR13 0x0144
+#define HMATRIX2_SFR14 0x0148
+#define HMATRIX2_SFR15 0x014c
+#define HMATRIX2_VERSION 0x01fc
+
+/* Bitfields in MCFG0 */
+#define HMATRIX2_ULBT_OFFSET 0
+#define HMATRIX2_ULBT_SIZE 3
+
+/* Bitfields in SCFG0 */
+#define HMATRIX2_SLOT_CYCLE_OFFSET 0
+#define HMATRIX2_SLOT_CYCLE_SIZE 8
+#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16
+#define HMATRIX2_DEFMSTR_TYPE_SIZE 2
+#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18
+#define HMATRIX2_FIXED_DEFMSTR_SIZE 4
+#define HMATRIX2_ARBT_OFFSET 24
+#define HMATRIX2_ARBT_SIZE 2
+
+/* Bitfields in PRAS0 */
+#define HMATRIX2_M0PR_OFFSET 0
+#define HMATRIX2_M0PR_SIZE 4
+#define HMATRIX2_M1PR_OFFSET 4
+#define HMATRIX2_M1PR_SIZE 4
+#define HMATRIX2_M2PR_OFFSET 8
+#define HMATRIX2_M2PR_SIZE 4
+#define HMATRIX2_M3PR_OFFSET 12
+#define HMATRIX2_M3PR_SIZE 4
+#define HMATRIX2_M4PR_OFFSET 16
+#define HMATRIX2_M4PR_SIZE 4
+#define HMATRIX2_M5PR_OFFSET 20
+#define HMATRIX2_M5PR_SIZE 4
+#define HMATRIX2_M6PR_OFFSET 24
+#define HMATRIX2_M6PR_SIZE 4
+#define HMATRIX2_M7PR_OFFSET 28
+#define HMATRIX2_M7PR_SIZE 4
+
+/* Bitfields in PRBS0 */
+#define HMATRIX2_M8PR_OFFSET 0
+#define HMATRIX2_M8PR_SIZE 4
+#define HMATRIX2_M9PR_OFFSET 4
+#define HMATRIX2_M9PR_SIZE 4
+#define HMATRIX2_M10PR_OFFSET 8
+#define HMATRIX2_M10PR_SIZE 4
+#define HMATRIX2_M11PR_OFFSET 12
+#define HMATRIX2_M11PR_SIZE 4
+#define HMATRIX2_M12PR_OFFSET 16
+#define HMATRIX2_M12PR_SIZE 4
+#define HMATRIX2_M13PR_OFFSET 20
+#define HMATRIX2_M13PR_SIZE 4
+#define HMATRIX2_M14PR_OFFSET 24
+#define HMATRIX2_M14PR_SIZE 4
+#define HMATRIX2_M15PR_OFFSET 28
+#define HMATRIX2_M15PR_SIZE 4
+
+/* Bitfields in MRCR */
+#define HMATRIX2_RBC0_OFFSET 0
+#define HMATRIX2_RBC0_SIZE 1
+#define HMATRIX2_RBC1_OFFSET 1
+#define HMATRIX2_RBC1_SIZE 1
+#define HMATRIX2_RBC2_OFFSET 2
+#define HMATRIX2_RBC2_SIZE 1
+#define HMATRIX2_RBC3_OFFSET 3
+#define HMATRIX2_RBC3_SIZE 1
+#define HMATRIX2_RBC4_OFFSET 4
+#define HMATRIX2_RBC4_SIZE 1
+#define HMATRIX2_RBC5_OFFSET 5
+#define HMATRIX2_RBC5_SIZE 1
+#define HMATRIX2_RBC6_OFFSET 6
+#define HMATRIX2_RBC6_SIZE 1
+#define HMATRIX2_RBC7_OFFSET 7
+#define HMATRIX2_RBC7_SIZE 1
+#define HMATRIX2_RBC8_OFFSET 8
+#define HMATRIX2_RBC8_SIZE 1
+#define HMATRIX2_RBC9_OFFSET 9
+#define HMATRIX2_RBC9_SIZE 1
+#define HMATRIX2_RBC10_OFFSET 10
+#define HMATRIX2_RBC10_SIZE 1
+#define HMATRIX2_RBC11_OFFSET 11
+#define HMATRIX2_RBC11_SIZE 1
+#define HMATRIX2_RBC12_OFFSET 12
+#define HMATRIX2_RBC12_SIZE 1
+#define HMATRIX2_RBC13_OFFSET 13
+#define HMATRIX2_RBC13_SIZE 1
+#define HMATRIX2_RBC14_OFFSET 14
+#define HMATRIX2_RBC14_SIZE 1
+#define HMATRIX2_RBC15_OFFSET 15
+#define HMATRIX2_RBC15_SIZE 1
+
+/* Bitfields in SFR0 */
+#define HMATRIX2_SFR_OFFSET 0
+#define HMATRIX2_SFR_SIZE 32
+
+/* Bitfields in SFR4 */
+#define HMATRIX2_CS1A_OFFSET 1
+#define HMATRIX2_CS1A_SIZE 1
+#define HMATRIX2_CS3A_OFFSET 3
+#define HMATRIX2_CS3A_SIZE 1
+#define HMATRIX2_CS4A_OFFSET 4
+#define HMATRIX2_CS4A_SIZE 1
+#define HMATRIX2_CS5A_OFFSET 5
+#define HMATRIX2_CS5A_SIZE 1
+#define HMATRIX2_DBPUC_OFFSET 8
+#define HMATRIX2_DBPUC_SIZE 1
+
+/* Bitfields in VERSION */
+#define HMATRIX2_VERSION_OFFSET 0
+#define HMATRIX2_VERSION_SIZE 12
+#define HMATRIX2_MFN_OFFSET 16
+#define HMATRIX2_MFN_SIZE 3
+
+/* Constants for ULBT */
+#define HMATRIX2_ULBT_INFINITE 0
+#define HMATRIX2_ULBT_SINGLE 1
+#define HMATRIX2_ULBT_FOUR_BEAT 2
+#define HMATRIX2_ULBT_SIXTEEN_BEAT 4
+
+/* Constants for DEFMSTR_TYPE */
+#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0
+#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1
+#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2
+
+/* Constants for ARBT */
+#define HMATRIX2_ARBT_ROUND_ROBIN 0
+#define HMATRIX2_ARBT_FIXED_PRIORITY 1
+
+/* Bit manipulation macros */
+#define HMATRIX2_BIT(name) \
+ (1 << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BF(name,value) \
+ (((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \
+ << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BFEXT(name,value) \
+ (((value) >> HMATRIX2_##name##_OFFSET) \
+ & ((1 << HMATRIX2_##name##_SIZE) - 1))
+#define HMATRIX2_BFINS(name,value,old) \
+ (((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \
+ << HMATRIX2_##name##_OFFSET)) \
+ | HMATRIX2_BF(name,value))
+
+/* Register access macros */
+#define hmatrix2_readl(port,reg) \
+ readl((port)->regs + HMATRIX2_##reg)
+#define hmatrix2_writel(port,reg,value) \
+ writel((value), (port)->regs + HMATRIX2_##reg)
+
+#endif /* __ASM_AVR32_HMATRIX2_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__
+#define __ASM_AVR32_PART_MEMORY_MAP_H__
+
+#define AUDIOC_BASE 0xFFF02800
+#define DAC_BASE 0xFFF02000
+#define DMAC_BASE 0xFF200000
+#define ECC_BASE 0xFFF03C00
+#define HISI_BASE 0xFFF02C00
+#define HMATRIX_BASE 0xFFF00800
+#define HSDRAMC_BASE 0xFFF03800
+#define HSMC_BASE 0xFFF03400
+#define LCDC_BASE 0xFF000000
+#define MACB0_BASE 0xFFF01800
+#define MACB1_BASE 0xFFF01C00
+#define MMCI_BASE 0xFFF02400
+#define PIOA_BASE 0xFFE02800
+#define PIOB_BASE 0xFFE02C00
+#define PIOC_BASE 0xFFE03000
+#define PIOD_BASE 0xFFE03400
+#define PIOE_BASE 0xFFE03800
+#define PSIF_BASE 0xFFE03C00
+#define PWM_BASE 0xFFF01400
+#define SM_BASE 0xFFF00000
+#define INTC_BASE 0XFFF00400
+#define SPI0_BASE 0xFFE00000
+#define SPI1_BASE 0xFFE00400
+#define SSC0_BASE 0xFFE01C00
+#define SSC1_BASE 0xFFE02000
+#define SSC2_BASE 0xFFE02400
+#define TIMER0_BASE 0xFFF00C00
+#define TIMER1_BASE 0xFFF01000
+#define TWI_BASE 0xFFE00800
+#define USART0_BASE 0xFFE00C00
+#define USART1_BASE 0xFFE01000
+#define USART2_BASE 0xFFE01400
+#define USART3_BASE 0xFFE01800
+#define USB_FIFO 0xFF300000
+#define USB_BASE 0xFFF03000
+
+#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_AVR32_ARCH_PM_H
+#define _ASM_AVR32_ARCH_PM_H
+
+#include <config.h>
+
+enum clock_domain_id {
+ CLOCK_CPU,
+ CLOCK_HSB,
+ CLOCK_PBA,
+ CLOCK_PBB,
+ NR_CLOCK_DOMAINS,
+};
+
+enum resource_type {
+ RESOURCE_GPIO,
+ RESOURCE_CLOCK,
+};
+
+enum gpio_func {
+ GPIO_FUNC_GPIO,
+ GPIO_FUNC_A,
+ GPIO_FUNC_B,
+};
+
+enum device_id {
+ DEVICE_HEBI,
+ DEVICE_PBA_BRIDGE,
+ DEVICE_PBB_BRIDGE,
+ DEVICE_HRAMC,
+ /* GPIO controllers must be kept together */
+ DEVICE_PIOA,
+ DEVICE_PIOB,
+ DEVICE_PIOC,
+ DEVICE_PIOD,
+ DEVICE_PIOE,
+ DEVICE_SM,
+ DEVICE_INTC,
+ DEVICE_HMATRIX,
+#if defined(CFG_HPDC)
+ DEVICE_HPDC,
+#endif
+#if defined(CFG_MACB0)
+ DEVICE_MACB0,
+#endif
+#if defined(CFG_MACB1)
+ DEVICE_MACB1,
+#endif
+#if defined(CFG_LCDC)
+ DEVICE_LCDC,
+#endif
+#if defined(CFG_USART0)
+ DEVICE_USART0,
+#endif
+#if defined(CFG_USART1)
+ DEVICE_USART1,
+#endif
+#if defined(CFG_USART2)
+ DEVICE_USART2,
+#endif
+#if defined(CFG_USART3)
+ DEVICE_USART3,
+#endif
+#if defined(CFG_MMCI)
+ DEVICE_MMCI,
+#endif
+#if defined(CFG_DMAC)
+ DEVICE_DMAC,
+#endif
+ NR_DEVICES,
+ NO_DEVICE = -1,
+};
+
+struct resource {
+ enum resource_type type;
+ union {
+ struct {
+ unsigned long base;
+ } iomem;
+ struct {
+ unsigned char nr_pins;
+ enum device_id gpio_dev;
+ enum gpio_func func;
+ unsigned short start;
+ } gpio;
+ struct {
+ enum clock_domain_id id;
+ unsigned char index;
+ } clock;
+ } u;
+};
+
+struct device {
+ void *regs;
+ unsigned int nr_resources;
+ const struct resource *resource;
+};
+
+struct clock_domain {
+ unsigned short reg;
+ enum clock_domain_id id;
+ enum device_id bridge;
+};
+
+extern const struct device chip_device[NR_DEVICES];
+extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS];
+
+/**
+ * Set up PIO, clock management and I/O memory for a device.
+ */
+const struct device *get_device(enum device_id devid);
+void put_device(const struct device *dev);
+
+int gpio_set_func(enum device_id gpio_devid, unsigned int start,
+ unsigned int nr_pins, enum gpio_func func);
+void gpio_free(enum device_id gpio_devid, unsigned int start,
+ unsigned int nr_pins);
+
+void pm_init(void);
+int pm_enable_clock(enum clock_domain_id id, unsigned int index);
+void pm_disable_clock(enum clock_domain_id id, unsigned int index);
+unsigned long pm_get_clock_freq(enum clock_domain_id domain);
+
+void cpu_enable_sdram(void);
+
+#endif /* _ASM_AVR32_ARCH_PM_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_BITOPS_H
+#define __ASM_AVR32_BITOPS_H
+
+#endif /* __ASM_AVR32_BITOPS_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_BYTEORDER_H
+#define __ASM_AVR32_BYTEORDER_H
+
+#include <asm/types.h>
+
+#define __arch__swab32(x) __builtin_bswap_32(x)
+#define __arch__swab16(x) __builtin_bswap_16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+# define __BYTEORDER_HAS_U64__
+# define __SWAB_64_THRU_32__
+#endif
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* __ASM_AVR32_BYTEORDER_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_CACHEFLUSH_H
+#define __ASM_AVR32_CACHEFLUSH_H
+
+/*
+ * Invalidate any cacheline containing virtual address vaddr without
+ * writing anything back to memory.
+ *
+ * Note that this function may corrupt unrelated data structures when
+ * applied on buffers that are not cacheline aligned in both ends.
+ */
+static inline void dcache_invalidate_line(volatile void *vaddr)
+{
+ asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Make sure any cacheline containing virtual address vaddr is written
+ * to memory.
+ */
+static inline void dcache_clean_line(volatile void *vaddr)
+{
+ asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Make sure any cacheline containing virtual address vaddr is written
+ * to memory and then invalidate it.
+ */
+static inline void dcache_flush_line(volatile void *vaddr)
+{
+ asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Invalidate any instruction cacheline containing virtual address
+ * vaddr.
+ */
+static inline void icache_invalidate_line(volatile void *vaddr)
+{
+ asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory");
+}
+
+/*
+ * Applies the above functions on all lines that are touched by the
+ * specified virtual address range.
+ */
+void dcache_invalidate_range(volatile void *start, size_t len);
+void dcache_clean_range(volatile void *start, size_t len);
+void dcache_flush_range(volatile void *start, size_t len);
+void icache_invalidate_range(volatile void *start, size_t len);
+
+static inline void dcache_flush_unlocked(void)
+{
+ asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory");
+}
+
+/*
+ * Make sure any pending writes are completed before continuing.
+ */
+#define sync_write_buffer() asm volatile("sync 0" : : : "memory")
+
+#endif /* __ASM_AVR32_CACHEFLUSH_H */
--- /dev/null
+#ifndef _ASM_GENERIC_DIV64_H
+#define _ASM_GENERIC_DIV64_H
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
+ *
+ * The semantics of do_div() are:
+ *
+ * uint32_t do_div(uint64_t *n, uint32_t base)
+ * {
+ * uint32_t remainder = *n % base;
+ * *n = *n / base;
+ * return remainder;
+ * }
+ *
+ * NOTE: macro parameter n is evaluated multiple times,
+ * beware of side effects!
+ */
+
+#include <linux/types.h>
+
+extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
+
+/* The unnecessary pointer compare is there
+ * to check for type safety (n must be 64bit)
+ */
+# define do_div(n,base) ({ \
+ uint32_t __base = (base); \
+ uint32_t __rem; \
+ (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \
+ if (((n) >> 32) == 0) { \
+ __rem = (uint32_t)(n) % __base; \
+ (n) = (uint32_t)(n) / __base; \
+ } else \
+ __rem = __div64_32(&(n), __base); \
+ __rem; \
+ })
+
+#endif /* _ASM_GENERIC_DIV64_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_DMA_MAPPING_H
+#define __ASM_AVR32_DMA_MAPPING_H
+
+#include <asm/io.h>
+#include <asm/cacheflush.h>
+
+enum dma_data_direction {
+ DMA_BIDIRECTIONAL = 0,
+ DMA_TO_DEVICE = 1,
+ DMA_FROM_DEVICE = 2,
+};
+extern void *dma_alloc_coherent(size_t len, unsigned long *handle);
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+ enum dma_data_direction dir)
+{
+ extern void __bad_dma_data_direction(void);
+
+ switch (dir) {
+ case DMA_BIDIRECTIONAL:
+ dcache_flush_range(vaddr, len);
+ break;
+ case DMA_TO_DEVICE:
+ dcache_clean_range(vaddr, len);
+ break;
+ case DMA_FROM_DEVICE:
+ dcache_invalidate_range(vaddr, len);
+ break;
+ default:
+ /* This will cause a linker error */
+ __bad_dma_data_direction();
+ }
+
+ return virt_to_phys(vaddr);
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+ unsigned long paddr)
+{
+
+}
+
+#endif /* __ASM_AVR32_DMA_MAPPING_H */
--- /dev/null
+#ifndef _ASM_AVR32_ERRNO_H
+#define _ASM_AVR32_ERRNO_H
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Argument list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+#define ENOSYS 38 /* Function not implemented */
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+
+#define EDEADLOCK EDEADLK
+
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale NFS file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+
+#endif /* _ASM_AVR32_ERRNO_H */
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_GLOBAL_DATA_H__
+#define __ASM_GLOBAL_DATA_H__
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef struct global_data {
+ bd_t *bd;
+ unsigned long flags;
+ const struct device *console_uart;
+ const struct device *sm;
+ unsigned long baudrate;
+ unsigned long sdram_size;
+ unsigned long have_console; /* serial_init() was called */
+ unsigned long reloc_off; /* Relocation Offset */
+ unsigned long env_addr; /* Address of env struct */
+ unsigned long env_valid; /* Checksum of env valid? */
+ unsigned long cpu_hz; /* cpu core clock frequency */
+ void **jt; /* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
+#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
+#define GD_FLG_SILENT 0x00004 /* Silent mode */
+
+#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
+
+#endif /* __ASM_GLOBAL_DATA_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2005, 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_INITCALLS_H__
+#define __ASM_AVR32_INITCALLS_H__
+
+#include <config.h>
+
+extern int cpu_init(void);
+extern int timer_init(void);
+extern void board_init_memories(void);
+extern void board_init_pio(void);
+extern void board_init_info(void);
+
+#endif /* __ASM_AVR32_INITCALLS_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_IO_H
+#define __ASM_AVR32_IO_H
+
+#ifdef __KERNEL__
+
+/*
+ * Generic IO read/write. These perform native-endian accesses. Note
+ * that some architectures will want to re-define __raw_{read,write}w.
+ */
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
+
+#define __raw_readb(a) (*(volatile unsigned char *)(a))
+#define __raw_readw(a) (*(volatile unsigned short *)(a))
+#define __raw_readl(a) (*(volatile unsigned int *)(a))
+
+/* As long as I/O is only performed in P4 (or possibly P3), we're safe */
+#define writeb(v,a) __raw_writeb(v,a)
+#define writew(v,a) __raw_writew(v,a)
+#define writel(v,a) __raw_writel(v,a)
+
+#define readb(a) __raw_readb(a)
+#define readw(a) __raw_readw(a)
+#define readl(a) __raw_readl(a)
+
+/*
+ * Bad read/write accesses...
+ */
+extern void __readwrite_bug(const char *fn);
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * All I/O is memory mapped, so these macros doesn't make very much sense
+ */
+#define outb(v,p) __raw_writeb(v, p)
+#define outw(v,p) __raw_writew(cpu_to_le16(v),p)
+#define outl(v,p) __raw_writel(cpu_to_le32(v),p)
+
+#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; })
+#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
+#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
+
+#include <asm/addrspace.h>
+
+/* virt_to_phys will only work when address is in P1 or P2 */
+static __inline__ unsigned long virt_to_phys(volatile void *address)
+{
+ return PHYSADDR(address);
+}
+
+static __inline__ void * phys_to_virt(unsigned long address)
+{
+ return (void *)P1SEGADDR(address);
+}
+
+#define cached(addr) ((void *)P1SEGADDR(addr))
+#define uncached(addr) ((void *)P2SEGADDR(addr))
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_AVR32_IO_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_POSIX_TYPES_H
+#define __ASM_AVR32_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long __kernel_dev_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned int __kernel_uid_t;
+typedef unsigned int __kernel_gid_t;
+typedef unsigned long __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_timer_t;
+typedef int __kernel_clockid_t;
+typedef int __kernel_daddr_t;
+typedef char * __kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+typedef unsigned short __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+ int val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+ int __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+ unsigned long *__tmp = __p->fds_bits;
+ int __i;
+
+ if (__builtin_constant_p(__FDSET_LONGS)) {
+ switch (__FDSET_LONGS) {
+ case 16:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ __tmp[ 4] = 0; __tmp[ 5] = 0;
+ __tmp[ 6] = 0; __tmp[ 7] = 0;
+ __tmp[ 8] = 0; __tmp[ 9] = 0;
+ __tmp[10] = 0; __tmp[11] = 0;
+ __tmp[12] = 0; __tmp[13] = 0;
+ __tmp[14] = 0; __tmp[15] = 0;
+ return;
+
+ case 8:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ __tmp[ 4] = 0; __tmp[ 5] = 0;
+ __tmp[ 6] = 0; __tmp[ 7] = 0;
+ return;
+
+ case 4:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ return;
+ }
+ }
+ __i = __FDSET_LONGS;
+ while (__i) {
+ __i--;
+ *__tmp = 0;
+ __tmp++;
+ }
+}
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* __ASM_AVR32_POSIX_TYPES_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PROCESSOR_H
+#define __ASM_AVR32_PROCESSOR_H
+
+#ifndef __ASSEMBLY__
+
+#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; })
+
+struct avr32_cpuinfo {
+ unsigned long loops_per_jiffy;
+};
+
+extern struct avr32_cpuinfo boot_cpu_data;
+
+#ifdef CONFIG_SMP
+extern struct avr32_cpuinfo cpu_data[];
+#define current_cpu_data cpu_data[smp_processor_id()]
+#else
+#define cpu_data (&boot_cpu_data)
+#define current_cpu_data boot_cpu_data
+#endif
+
+/* TODO: Make configurable (2GB will serve as a reasonable default) */
+#define TASK_SIZE 0x80000000
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's
+ */
+#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
+
+#define cpu_relax() barrier()
+#define cpu_sync_pipeline() asm volatile("sub pc, -2" : : : "memory")
+
+/* This struct contains the CPU context as stored by switch_to() */
+struct thread_struct {
+ unsigned long pc;
+ unsigned long ksp; /* Kernel stack pointer */
+ unsigned long r7;
+ unsigned long r6;
+ unsigned long r5;
+ unsigned long r4;
+ unsigned long r3;
+ unsigned long r2;
+ unsigned long r1;
+ unsigned long r0;
+};
+
+#define INIT_THREAD { \
+ .ksp = sizeof(init_stack) + (long)&init_stack, \
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+#define start_thread(regs, new_pc, new_sp) \
+ set_fs(USER_DS); \
+ regs->sr = 0; /* User mode. */ \
+ regs->gr[REG_PC] = new_pc; \
+ regs->gr[REG_SP] = new_sp
+
+struct task_struct;
+
+/* Free all resources held by a thread */
+extern void release_thread(struct task_struct *);
+
+/* Create a kernel thread without removing it from tasklists */
+extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk) do { } while(0)
+
+/* Return saved PC of a blocked thread */
+#define thread_saved_pc(tsk) (tsk->thread.pc)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_PROCESSOR_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PTRACE_H
+#define __ASM_AVR32_PTRACE_H
+
+/*
+ * Status Register bits
+ */
+#define SR_H 0x40000000
+#define SR_R 0x20000000
+#define SR_J 0x10000000
+#define SR_DM 0x08000000
+#define SR_D 0x04000000
+#define MODE_NMI 0x01c00000
+#define MODE_EXCEPTION 0x01800000
+#define MODE_INT3 0x01400000
+#define MODE_INT2 0x01000000
+#define MODE_INT1 0x00c00000
+#define MODE_INT0 0x00800000
+#define MODE_SUPERVISOR 0x00400000
+#define MODE_USER 0x00000000
+#define MODE_MASK 0x01c00000
+#define SR_EM 0x00200000
+#define SR_I3M 0x00100000
+#define SR_I2M 0x00080000
+#define SR_I1M 0x00040000
+#define SR_I0M 0x00020000
+#define SR_GM 0x00010000
+
+#define MODE_SHIFT 22
+#define SR_EM_BIT 21
+#define SR_I3M_BIT 20
+#define SR_I2M_BIT 19
+#define SR_I1M_BIT 18
+#define SR_I0M_BIT 17
+#define SR_GM_BIT 16
+
+/* The user-visible part */
+#define SR_Q 0x00000010
+#define SR_V 0x00000008
+#define SR_N 0x00000004
+#define SR_Z 0x00000002
+#define SR_C 0x00000001
+
+/*
+ * The order is defined by the stdsp instruction. r0 is stored first, so it
+ * gets the highest address.
+ *
+ * Registers 0-12 are general-purpose registers (r12 is normally used for
+ * the function return value).
+ * Register 13 is the stack pointer
+ * Register 14 is the link register
+ * Register 15 is the program counter
+ */
+#define FRAME_SIZE_FULL 72
+#define REG_R12_ORIG 68
+#define REG_R0 64
+#define REG_R1 60
+#define REG_R2 56
+#define REG_R3 52
+#define REG_R4 48
+#define REG_R5 44
+#define REG_R6 40
+#define REG_R7 36
+#define REG_R8 32
+#define REG_R9 28
+#define REG_R10 34
+#define REG_R11 20
+#define REG_R12 16
+#define REG_SP 12
+#define REG_LR 8
+
+#define FRAME_SIZE_MIN 8
+#define REG_PC 4
+#define REG_SR 0
+
+#ifndef __ASSEMBLY__
+struct pt_regs {
+ /* These are always saved */
+ unsigned long sr;
+ unsigned long pc;
+
+ /* These are sometimes saved */
+ unsigned long lr;
+ unsigned long sp;
+ unsigned long r12;
+ unsigned long r11;
+ unsigned long r10;
+ unsigned long r9;
+ unsigned long r8;
+ unsigned long r7;
+ unsigned long r6;
+ unsigned long r5;
+ unsigned long r4;
+ unsigned long r3;
+ unsigned long r2;
+ unsigned long r1;
+ unsigned long r0;
+
+ /* Only saved on system call */
+ unsigned long r12_orig;
+};
+
+#ifdef __KERNEL__
+# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
+# define instruction_pointer(regs) ((regs)->pc)
+extern void show_regs (struct pt_regs *);
+
+static __inline__ int valid_user_regs(struct pt_regs *regs)
+{
+ /*
+ * Some of the Java bits might be acceptable if/when we
+ * implement some support for that stuff...
+ */
+ if ((regs->sr & 0xffff0000) == 0)
+ return 1;
+
+ /*
+ * Force status register flags to be sane and report this
+ * illegal behaviour...
+ */
+ regs->sr &= 0x0000ffff;
+ return 0;
+}
+#endif
+
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_PTRACE_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SDRAM_H
+#define __ASM_AVR32_SDRAM_H
+
+struct sdram_info {
+ unsigned long phys_addr;
+ unsigned int row_bits, col_bits, bank_bits;
+ unsigned int cas, twr, trc, trp, trcd, tras, txsr;
+};
+
+extern unsigned long sdram_init(const struct sdram_info *info);
+
+#endif /* __ASM_AVR32_SDRAM_H */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SECTIONS_H
+#define __ASM_AVR32_SECTIONS_H
+
+/* References to section boundaries */
+
+extern char _text[], _etext[];
+extern char __flashprog_start[], __flashprog_end[];
+extern char _data[], __data_lma[], _edata[], __edata_lma[];
+extern char __got_start[], __got_lma[], __got_end[];
+extern char _end[];
+
+/*
+ * Everything in .flashprog will be locked in the icache so it doesn't
+ * get disturbed when executing flash commands.
+ */
+#define __flashprog __attribute__((section(".flashprog"), __noinline__))
+
+#endif /* __ASM_AVR32_SECTIONS_H */
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * Based on linux/include/asm-arm/setup.h
+ * Copyright (C) 1997-1999 Russel King
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_SETUP_H__
+#define __ASM_AVR32_SETUP_H__
+
+#define COMMAND_LINE_SIZE 256
+
+/* Magic number indicating that a tag table is present */
+#define ATAG_MAGIC 0xa2a25441
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Generic memory range, used by several tags.
+ *
+ * addr is always physical.
+ * size is measured in bytes.
+ * next is for use by the OS, e.g. for grouping regions into
+ * linked lists.
+ */
+struct tag_mem_range {
+ u32 addr;
+ u32 size;
+ struct tag_mem_range * next;
+};
+
+/* The list ends with an ATAG_NONE node. */
+#define ATAG_NONE 0x00000000
+
+struct tag_header {
+ u32 size;
+ u32 tag;
+};
+
+/* The list must start with an ATAG_CORE node */
+#define ATAG_CORE 0x54410001
+
+struct tag_core {
+ u32 flags;
+ u32 pagesize;
+ u32 rootdev;
+};
+
+/* it is allowed to have multiple ATAG_MEM nodes */
+#define ATAG_MEM 0x54410002
+/* ATAG_MEM uses tag_mem_range */
+
+/* command line: \0 terminated string */
+#define ATAG_CMDLINE 0x54410003
+
+struct tag_cmdline {
+ char cmdline[1]; /* this is the minimum size */
+};
+
+/* Ramdisk image (may be compressed) */
+#define ATAG_RDIMG 0x54410004
+/* ATAG_RDIMG uses tag_mem_range */
+
+/* Information about various clocks present in the system */
+#define ATAG_CLOCK 0x54410005
+
+struct tag_clock {
+ u32 clock_id; /* Which clock are we talking about? */
+ u32 clock_flags; /* Special features */
+ u64 clock_hz; /* Clock speed in Hz */
+};
+
+/* The clock types we know about */
+#define ACLOCK_BOOTCPU 0 /* The CPU we're booting from */
+#define ACLOCK_HSB 1 /* Deprecated */
+
+/* Memory reserved for the system (e.g. the bootloader) */
+#define ATAG_RSVD_MEM 0x54410006
+/* ATAG_RSVD_MEM uses tag_mem_range */
+
+/* Ethernet information */
+
+#define ATAG_ETHERNET 0x54410007
+
+struct tag_ethernet {
+ u8 mac_index;
+ u8 mii_phy_addr;
+ u8 hw_address[6];
+};
+
+#define AETH_INVALID_PHY 0xff
+
+struct tag {
+ struct tag_header hdr;
+ union {
+ struct tag_core core;
+ struct tag_mem_range mem_range;
+ struct tag_cmdline cmdline;
+ struct tag_clock clock;
+ struct tag_ethernet ethernet;
+ } u;
+};
+
+struct tagtable {
+ u32 tag;
+ int (*parse)(struct tag *);
+};
+
+#define __tag __attribute_used__ __attribute__((__section__(".taglist")))
+#define __tagtable(tag, fn) \
+ static struct tagtable __tagtable_##fn __tag = { tag, fn }
+
+#define tag_member_present(tag,member) \
+ ((unsigned long)(&((struct tag *)0L)->member + 1) \
+ <= (tag)->hdr.size * 4)
+
+#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
+
+#define for_each_tag(t,base) \
+ for (t = base; t->hdr.size; t = tag_next(t))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_AVR32_SETUP_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_STRING_H
+#define __ASM_AVR32_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *s, int c, size_t n);
+
+#endif /* __ASM_AVR32_STRING_H */
--- /dev/null
+/*
+ * System registers for AVR32
+ */
+#ifndef __ASM_AVR32_SYSREG_H__
+#define __ASM_AVR32_SYSREG_H__
+
+/* system register offsets */
+#define SYSREG_SR 0x0000
+#define SYSREG_EVBA 0x0004
+#define SYSREG_ACBA 0x0008
+#define SYSREG_CPUCR 0x000c
+#define SYSREG_ECR 0x0010
+#define SYSREG_RSR_SUP 0x0014
+#define SYSREG_RSR_INT0 0x0018
+#define SYSREG_RSR_INT1 0x001c
+#define SYSREG_RSR_INT2 0x0020
+#define SYSREG_RSR_INT3 0x0024
+#define SYSREG_RSR_EX 0x0028
+#define SYSREG_RSR_NMI 0x002c
+#define SYSREG_RSR_DBG 0x0030
+#define SYSREG_RAR_SUP 0x0034
+#define SYSREG_RAR_INT0 0x0038
+#define SYSREG_RAR_INT1 0x003c
+#define SYSREG_RAR_INT2 0x0040
+#define SYSREG_RAR_INT3 0x0044
+#define SYSREG_RAR_EX 0x0048
+#define SYSREG_RAR_NMI 0x004c
+#define SYSREG_RAR_DBG 0x0050
+#define SYSREG_JECR 0x0054
+#define SYSREG_JOSP 0x0058
+#define SYSREG_JAVA_LV0 0x005c
+#define SYSREG_JAVA_LV1 0x0060
+#define SYSREG_JAVA_LV2 0x0064
+#define SYSREG_JAVA_LV3 0x0068
+#define SYSREG_JAVA_LV4 0x006c
+#define SYSREG_JAVA_LV5 0x0070
+#define SYSREG_JAVA_LV6 0x0074
+#define SYSREG_JAVA_LV7 0x0078
+#define SYSREG_JTBA 0x007c
+#define SYSREG_JBCR 0x0080
+#define SYSREG_CONFIG0 0x0100
+#define SYSREG_CONFIG1 0x0104
+#define SYSREG_COUNT 0x0108
+#define SYSREG_COMPARE 0x010c
+#define SYSREG_TLBEHI 0x0110
+#define SYSREG_TLBELO 0x0114
+#define SYSREG_PTBR 0x0118
+#define SYSREG_TLBEAR 0x011c
+#define SYSREG_MMUCR 0x0120
+#define SYSREG_TLBARLO 0x0124
+#define SYSREG_TLBARHI 0x0128
+#define SYSREG_PCCNT 0x012c
+#define SYSREG_PCNT0 0x0130
+#define SYSREG_PCNT1 0x0134
+#define SYSREG_PCCR 0x0138
+#define SYSREG_BEAR 0x013c
+#define SYSREG_SABAL 0x0300
+#define SYSREG_SABAH 0x0304
+#define SYSREG_SABD 0x0308
+
+/* Bitfields in SR */
+#define SYSREG_SR_C_OFFSET 0
+#define SYSREG_SR_C_SIZE 1
+#define SYSREG_Z_OFFSET 1
+#define SYSREG_Z_SIZE 1
+#define SYSREG_SR_N_OFFSET 2
+#define SYSREG_SR_N_SIZE 1
+#define SYSREG_SR_V_OFFSET 3
+#define SYSREG_SR_V_SIZE 1
+#define SYSREG_Q_OFFSET 4
+#define SYSREG_Q_SIZE 1
+#define SYSREG_L_OFFSET 5
+#define SYSREG_L_SIZE 1
+#define SYSREG_T_OFFSET 14
+#define SYSREG_T_SIZE 1
+#define SYSREG_SR_R_OFFSET 15
+#define SYSREG_SR_R_SIZE 1
+#define SYSREG_GM_OFFSET 16
+#define SYSREG_GM_SIZE 1
+#define SYSREG_I0M_OFFSET 17
+#define SYSREG_I0M_SIZE 1
+#define SYSREG_I1M_OFFSET 18
+#define SYSREG_I1M_SIZE 1
+#define SYSREG_I2M_OFFSET 19
+#define SYSREG_I2M_SIZE 1
+#define SYSREG_I3M_OFFSET 20
+#define SYSREG_I3M_SIZE 1
+#define SYSREG_EM_OFFSET 21
+#define SYSREG_EM_SIZE 1
+#define SYSREG_M0_OFFSET 22
+#define SYSREG_M0_SIZE 1
+#define SYSREG_M1_OFFSET 23
+#define SYSREG_M1_SIZE 1
+#define SYSREG_M2_OFFSET 24
+#define SYSREG_M2_SIZE 1
+#define SYSREG_SR_D_OFFSET 26
+#define SYSREG_SR_D_SIZE 1
+#define SYSREG_DM_OFFSET 27
+#define SYSREG_DM_SIZE 1
+#define SYSREG_SR_J_OFFSET 28
+#define SYSREG_SR_J_SIZE 1
+#define SYSREG_H_OFFSET 29
+#define SYSREG_H_SIZE 1
+
+/* Bitfields in CPUCR */
+#define SYSREG_BI_OFFSET 0
+#define SYSREG_BI_SIZE 1
+#define SYSREG_BE_OFFSET 1
+#define SYSREG_BE_SIZE 1
+#define SYSREG_FE_OFFSET 2
+#define SYSREG_FE_SIZE 1
+#define SYSREG_RE_OFFSET 3
+#define SYSREG_RE_SIZE 1
+#define SYSREG_IBE_OFFSET 4
+#define SYSREG_IBE_SIZE 1
+#define SYSREG_IEE_OFFSET 5
+#define SYSREG_IEE_SIZE 1
+
+/* Bitfields in ECR */
+#define SYSREG_ECR_OFFSET 0
+#define SYSREG_ECR_SIZE 32
+
+/* Bitfields in CONFIG0 */
+#define SYSREG_CONFIG0_R_OFFSET 0
+#define SYSREG_CONFIG0_R_SIZE 1
+#define SYSREG_CONFIG0_D_OFFSET 1
+#define SYSREG_CONFIG0_D_SIZE 1
+#define SYSREG_CONFIG0_S_OFFSET 2
+#define SYSREG_CONFIG0_S_SIZE 1
+#define SYSREG_O_OFFSET 3
+#define SYSREG_O_SIZE 1
+#define SYSREG_P_OFFSET 4
+#define SYSREG_P_SIZE 1
+#define SYSREG_CONFIG0_J_OFFSET 5
+#define SYSREG_CONFIG0_J_SIZE 1
+#define SYSREG_F_OFFSET 6
+#define SYSREG_F_SIZE 1
+#define SYSREG_MMUT_OFFSET 7
+#define SYSREG_MMUT_SIZE 3
+#define SYSREG_AR_OFFSET 10
+#define SYSREG_AR_SIZE 3
+#define SYSREG_AT_OFFSET 13
+#define SYSREG_AT_SIZE 3
+#define SYSREG_PROCESSORREVISION_OFFSET 16
+#define SYSREG_PROCESSORREVISION_SIZE 8
+#define SYSREG_PROCESSORID_OFFSET 24
+#define SYSREG_PROCESSORID_SIZE 8
+
+/* Bitfields in CONFIG1 */
+#define SYSREG_DASS_OFFSET 0
+#define SYSREG_DASS_SIZE 3
+#define SYSREG_DLSZ_OFFSET 3
+#define SYSREG_DLSZ_SIZE 3
+#define SYSREG_DSET_OFFSET 6
+#define SYSREG_DSET_SIZE 4
+#define SYSREG_IASS_OFFSET 10
+#define SYSREG_IASS_SIZE 3
+#define SYSREG_ILSZ_OFFSET 13
+#define SYSREG_ILSZ_SIZE 3
+#define SYSREG_ISET_OFFSET 16
+#define SYSREG_ISET_SIZE 4
+#define SYSREG_DMMUSZ_OFFSET 20
+#define SYSREG_DMMUSZ_SIZE 6
+#define SYSREG_IMMUSZ_OFFSET 26
+#define SYSREG_IMMUSZ_SIZE 6
+
+/* Bitfields in TLBEHI */
+#define SYSREG_ASID_OFFSET 0
+#define SYSREG_ASID_SIZE 8
+#define SYSREG_TLBEHI_I_OFFSET 8
+#define SYSREG_TLBEHI_I_SIZE 1
+#define SYSREG_TLBEHI_V_OFFSET 9
+#define SYSREG_TLBEHI_V_SIZE 1
+#define SYSREG_VPN_OFFSET 10
+#define SYSREG_VPN_SIZE 22
+
+/* Bitfields in TLBELO */
+#define SYSREG_W_OFFSET 0
+#define SYSREG_W_SIZE 1
+#define SYSREG_TLBELO_D_OFFSET 1
+#define SYSREG_TLBELO_D_SIZE 1
+#define SYSREG_SZ_OFFSET 2
+#define SYSREG_SZ_SIZE 2
+#define SYSREG_AP_OFFSET 4
+#define SYSREG_AP_SIZE 3
+#define SYSREG_B_OFFSET 7
+#define SYSREG_B_SIZE 1
+#define SYSREG_G_OFFSET 8
+#define SYSREG_G_SIZE 1
+#define SYSREG_TLBELO_C_OFFSET 9
+#define SYSREG_TLBELO_C_SIZE 1
+#define SYSREG_PFN_OFFSET 10
+#define SYSREG_PFN_SIZE 22
+
+/* Bitfields in MMUCR */
+#define SYSREG_E_OFFSET 0
+#define SYSREG_E_SIZE 1
+#define SYSREG_M_OFFSET 1
+#define SYSREG_M_SIZE 1
+#define SYSREG_MMUCR_I_OFFSET 2
+#define SYSREG_MMUCR_I_SIZE 1
+#define SYSREG_MMUCR_N_OFFSET 3
+#define SYSREG_MMUCR_N_SIZE 1
+#define SYSREG_MMUCR_S_OFFSET 4
+#define SYSREG_MMUCR_S_SIZE 1
+#define SYSREG_DLA_OFFSET 8
+#define SYSREG_DLA_SIZE 6
+#define SYSREG_DRP_OFFSET 14
+#define SYSREG_DRP_SIZE 6
+#define SYSREG_ILA_OFFSET 20
+#define SYSREG_ILA_SIZE 6
+#define SYSREG_IRP_OFFSET 26
+#define SYSREG_IRP_SIZE 6
+
+/* Bitfields in PCCR */
+#define SYSREG_PCCR_R_OFFSET 1
+#define SYSREG_PCCR_R_SIZE 1
+#define SYSREG_PCCR_C_OFFSET 2
+#define SYSREG_PCCR_C_SIZE 1
+#define SYSREG_PCCR_S_OFFSET 3
+#define SYSREG_PCCR_S_SIZE 1
+#define SYSREG_IEC_OFFSET 4
+#define SYSREG_IEC_SIZE 1
+#define SYSREG_IE0_OFFSET 5
+#define SYSREG_IE0_SIZE 1
+#define SYSREG_IE1_OFFSET 6
+#define SYSREG_IE1_SIZE 1
+#define SYSREG_FC_OFFSET 8
+#define SYSREG_FC_SIZE 1
+#define SYSREG_F0_OFFSET 9
+#define SYSREG_F0_SIZE 1
+#define SYSREG_F1_OFFSET 10
+#define SYSREG_F1_SIZE 1
+#define SYSREG_CONF0_OFFSET 12
+#define SYSREG_CONF0_SIZE 6
+#define SYSREG_CONF1_OFFSET 18
+#define SYSREG_CONF1_SIZE 6
+
+/* Constants for ECR */
+#define ECR_UNRECOVERABLE 0
+#define ECR_TLB_MULTIPLE 1
+#define ECR_BUS_ERROR_WRITE 2
+#define ECR_BUS_ERROR_READ 3
+#define ECR_NMI 4
+#define ECR_ADDR_ALIGN_X 5
+#define ECR_PROTECTION_X 6
+#define ECR_DEBUG 7
+#define ECR_ILLEGAL_OPCODE 8
+#define ECR_UNIMPL_INSTRUCTION 9
+#define ECR_PRIVILEGE_VIOLATION 10
+#define ECR_FPE 11
+#define ECR_COPROC_ABSENT 12
+#define ECR_ADDR_ALIGN_R 13
+#define ECR_ADDR_ALIGN_W 14
+#define ECR_PROTECTION_R 15
+#define ECR_PROTECTION_W 16
+#define ECR_DTLB_MODIFIED 17
+#define ECR_TLB_MISS_X 20
+#define ECR_TLB_MISS_R 24
+#define ECR_TLB_MISS_W 28
+
+/* Bit manipulation macros */
+#define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET)
+#define SYSREG_BF(name,value) \
+ (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) \
+ << SYSREG_##name##_OFFSET)
+#define SYSREG_BFEXT(name,value) \
+ (((value) >> SYSREG_##name##_OFFSET) \
+ & ((1 << SYSREG_##name##_SIZE) - 1))
+#define SYSREG_BFINS(name,value,old) \
+ (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) \
+ << SYSREG_##name##_OFFSET)) \
+ | SYSREG_BF(name,value))
+
+/* Register access macros */
+#define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg)
+#define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value)
+
+#endif /* __ASM_AVR32_SYSREG_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_TYPES_H
+#define __ASM_AVR32_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+typedef __signed__ char s8;
+typedef unsigned char u8;
+
+typedef __signed__ short s16;
+typedef unsigned short u16;
+
+typedef __signed__ int s32;
+typedef unsigned int u32;
+
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+#ifdef CONFIG_LBD
+typedef u64 sector_t;
+#define HAVE_SECTOR_T
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+
+#endif /* __ASM_AVR32_TYPES_H */
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_U_BOOT_H__
+#define __ASM_U_BOOT_H__ 1
+
+typedef struct bd_info {
+ unsigned long bi_baudrate;
+ unsigned long bi_ip_addr;
+ unsigned char bi_enetaddr[6];
+ unsigned char bi_phy_id[4];
+ struct environment_s *bi_env;
+ unsigned long bi_board_number;
+ void *bi_boot_params;
+ struct {
+ unsigned long start;
+ unsigned long size;
+ } bi_dram[CONFIG_NR_DRAM_BANKS];
+ unsigned long bi_flashstart;
+ unsigned long bi_flashsize;
+ unsigned long bi_flashoffset;
+} bd_t;
+
+#define bi_memstart bi_dram[0].start
+#define bi_memsize bi_dram[0].size
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ *
+ * @ptr: the pointer to the member.
+ * @type: the type of the container struct this is embedded in.
+ * @member: the name of the member within the struct.
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
+ (type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif /* __ASM_U_BOOT_H__ */
--- /dev/null
+/*
+ * Freescale I2C Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
+ * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
+ * and Jeff Brown.
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_FSL_I2C_H_
+#define _ASM_FSL_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct fsl_i2c {
+
+ u8 adr; /* I2C slave address */
+ u8 res0[3];
+#define I2C_ADR 0xFE
+#define I2C_ADR_SHIFT 1
+#define I2C_ADR_RES ~(I2C_ADR)
+
+ u8 fdr; /* I2C frequency divider register */
+ u8 res1[3];
+#define IC2_FDR 0x3F
+#define IC2_FDR_SHIFT 0
+#define IC2_FDR_RES ~(IC2_FDR)
+
+ u8 cr; /* I2C control redister */
+ u8 res2[3];
+#define I2C_CR_MEN 0x80
+#define I2C_CR_MIEN 0x40
+#define I2C_CR_MSTA 0x20
+#define I2C_CR_MTX 0x10
+#define I2C_CR_TXAK 0x08
+#define I2C_CR_RSTA 0x04
+#define I2C_CR_BCST 0x01
+
+ u8 sr; /* I2C status register */
+ u8 res3[3];
+#define I2C_SR_MCF 0x80
+#define I2C_SR_MAAS 0x40
+#define I2C_SR_MBB 0x20
+#define I2C_SR_MAL 0x10
+#define I2C_SR_BCSTM 0x08
+#define I2C_SR_SRW 0x04
+#define I2C_SR_MIF 0x02
+#define I2C_SR_RXAK 0x01
+
+ u8 dr; /* I2C data register */
+ u8 res4[3];
+#define I2C_DR 0xFF
+#define I2C_DR_SHIFT 0
+#define I2C_DR_RES ~(I2C_DR)
+
+ u8 dfsrr; /* I2C digital filter sampling rate register */
+ u8 res5[3];
+#define I2C_DFSRR 0x3F
+#define I2C_DFSRR_SHIFT 0
+#define I2C_DFSRR_RES ~(I2C_DR)
+
+ /* Fill out the reserved block */
+ u8 res6[0xE8];
+} fsl_i2c_t;
+
+
+#define I2C_READ 1
+#define I2C_WRITE 0
+
+#endif /* _ASM_I2C_H_ */
#ifndef __IMMAP_85xx__
#define __IMMAP_85xx__
+#include <asm/types.h>
+#include <asm/fsl_i2c.h>
+
/*
* Local-Access Registers and ECM Registers(0x0000-0x2000)
*/
* I2C Registers(0x3000-0x4000)
*/
typedef struct ccsr_i2c {
- u_char i2cadr; /* 0x3000 - I2C Address Register */
-#define MPC85xx_I2CADR_MASK 0xFE
- char res1[3];
- u_char i2cfdr; /* 0x3004 - I2C Frequency Divider Register */
-#define MPC85xx_I2CFDR_MASK 0x3F
- char res2[3];
- u_char i2ccr; /* 0x3008 - I2C Control Register */
-#define MPC85xx_I2CCR_MEN 0x80
-#define MPC85xx_I2CCR_MIEN 0x40
-#define MPC85xx_I2CCR_MSTA 0x20
-#define MPC85xx_I2CCR_MTX 0x10
-#define MPC85xx_I2CCR_TXAK 0x08
-#define MPC85xx_I2CCR_RSTA 0x04
-#define MPC85xx_I2CCR_BCST 0x01
- char res3[3];
- u_char i2csr; /* 0x300c - I2C Status Register */
-#define MPC85xx_I2CSR_MCF 0x80
-#define MPC85xx_I2CSR_MAAS 0x40
-#define MPC85xx_I2CSR_MBB 0x20
-#define MPC85xx_I2CSR_MAL 0x10
-#define MPC85xx_I2CSR_BCSTM 0x08
-#define MPC85xx_I2CSR_SRW 0x04
-#define MPC85xx_I2CSR_MIF 0x02
-#define MPC85xx_I2CSR_RXAK 0x01
- char res4[3];
- u_char i2cdr; /* 0x3010 - I2C Data Register */
-#define MPC85xx_I2CDR_DATA 0xFF
- char res5[3];
- u_char i2cdfsrr; /* 0x3014 - I2C Digital Filtering Sampling Rate Register */
-#define MPC85xx_I2CDFSRR 0x3F
- char res6[4075];
+ struct fsl_i2c i2c[1];
+ u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
} ccsr_i2c_t;
#if defined(CONFIG_MPC8540) \
/*
* PCI Registers(0x8000-0x9000)
- * Omitting Reserved(0x9000-0x2_0000)
*/
typedef struct ccsr_pcix {
uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
- char res11[94688];
+ uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
+ char res11[476];
} ccsr_pcix_t;
+#define PCIX_COMMAND 0x62
+#define POWAR_EN 0x80000000
+#define POWAR_IO_READ 0x00080000
+#define POWAR_MEM_READ 0x00040000
+#define POWAR_IO_WRITE 0x00008000
+#define POWAR_MEM_WRITE 0x00004000
+#define POWAR_MEM_512M 0x0000001c
+#define POWAR_IO_1M 0x00000013
+
+#define PIWAR_EN 0x80000000
+#define PIWAR_PF 0x20000000
+#define PIWAR_LOCAL 0x00f00000
+#define PIWAR_READ_SNOOP 0x00050000
+#define PIWAR_WRITE_SNOOP 0x00005000
+#define PIWAR_MEM_2G 0x0000001e
+
+
/*
* L2 Cache Registers(0x2_0000-0x2_1000)
*/
char res15[61651];
} ccsr_gur_t;
+#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
+
typedef struct immap {
ccsr_local_ecm_t im_local_ecm;
ccsr_ddr_t im_ddr;
ccsr_duart_t im_duart;
ccsr_lbc_t im_lbc;
ccsr_pcix_t im_pcix;
+ ccsr_pcix_t im_pcix2;
+ char reserved[90112];
ccsr_l2cache_t im_l2cache;
ccsr_dma_t im_dma;
ccsr_tsec_t im_tsec1;
--- /dev/null
+/*
+ * MPC86xx Internal Memory Map
+ *
+ * Copyright(c) 2004 Freescale Semiconductor
+ * Jeff Brown (Jeffrey@freescale.com)
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ */
+
+#ifndef __IMMAP_86xx__
+#define __IMMAP_86xx__
+
+#include <asm/types.h>
+#include <asm/fsl_i2c.h>
+
+/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
+typedef struct ccsr_local_mcm {
+ uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
+ char res1[4];
+ uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
+ char res2[4];
+ uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
+ char res3[12];
+ uint bptr; /* 0x20 - Boot Page Translation Register */
+ char res4[3044];
+ uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
+ char res5[4];
+ uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
+ char res6[20];
+ uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
+ char res7[4];
+ uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
+ char res8[20];
+ uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
+ char res9[4];
+ uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
+ char res10[20];
+ uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
+ char res11[4];
+ uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
+ char res12[20];
+ uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
+ char res13[4];
+ uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
+ char res14[20];
+ uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
+ char res15[4];
+ uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
+ char res16[20];
+ uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
+ char res17[4];
+ uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
+ char res18[20];
+ uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
+ char res19[4];
+ uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
+ char res20[20];
+ uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
+ char res21[4];
+ uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
+ char res22[20];
+ uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
+ char res23[4];
+ uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
+ char res24[716];
+ uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */
+ char res25[4];
+ uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */
+ char res26[4];
+ uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */
+ char res27[44];
+ uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */
+ uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */
+ uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */
+ uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */
+ char res28[16];
+ uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */
+ uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */
+ uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */
+ char res29[3476];
+ uint edr; /* 0x1e00 - MCM Error Detect Register */
+ char res30[4];
+ uint eer; /* 0x1e08 - MCM Error Enable Register */
+ uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */
+ uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */
+ uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */
+ char res31[488];
+} ccsr_local_mcm_t;
+
+/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
+
+typedef struct ccsr_ddr {
+ uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
+ char res1[4];
+ uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
+ char res2[4];
+ uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
+ char res3[4];
+ uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
+ char res4[4];
+ uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */
+ char res5[4];
+ uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */
+ char res6[84];
+ uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
+ uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
+ uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
+ uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
+ uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
+ uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
+ char res7[104];
+ uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */
+ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
+ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
+ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
+ uint sdram_cfg_1; /* 0x2110 - DDR SDRAM Control Configuration 1 */
+ uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
+ uint sdram_mode_1; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
+ uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
+ uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
+ uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
+ uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */
+ char res8[4];
+ uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
+ char res9[12];
+ uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */
+ uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */
+ uint init_addr; /* 0x2148 - DDR training initialzation address */
+ uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */
+ char res10[2728];
+ uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
+ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
+ char res11[512];
+ uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
+ uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
+ uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
+ char res12[20];
+ uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
+ uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
+ uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
+ char res13[20];
+ uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
+ uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
+ uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */
+ uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
+ uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
+ uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
+ uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
+ char res14[164];
+ uint debug_1; /* 0x2f00 */
+ uint debug_2;
+ uint debug_3;
+ uint debug_4;
+ uint debug_5;
+ char res15[236];
+} ccsr_ddr_t;
+
+
+/* Daul I2C Registers(0x3000-0x4000) */
+typedef struct ccsr_i2c {
+ struct fsl_i2c i2c[2];
+ u8 res[4096 - 2 * sizeof(struct fsl_i2c)];
+} ccsr_i2c_t;
+
+/* DUART Registers(0x4000-0x5000) */
+typedef struct ccsr_duart {
+ char res1[1280];
+ u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
+ u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
+ u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
+ u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
+ u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
+ u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
+ u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
+ u_char uscr1; /* 0x4507 - UART1 Scratch Register */
+ char res2[8];
+ u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
+ char res3[239];
+ u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
+ u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
+ u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
+ u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
+ u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
+ u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
+ u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
+ u_char uscr2; /* 0x4607 - UART2 Scratch Register */
+ char res4[8];
+ u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
+ char res5[2543];
+} ccsr_duart_t;
+
+
+/* Local Bus Controller Registers(0x5000-0x6000) */
+typedef struct ccsr_lbc {
+ uint br0; /* 0x5000 - LBC Base Register 0 */
+ uint or0; /* 0x5004 - LBC Options Register 0 */
+ uint br1; /* 0x5008 - LBC Base Register 1 */
+ uint or1; /* 0x500c - LBC Options Register 1 */
+ uint br2; /* 0x5010 - LBC Base Register 2 */
+ uint or2; /* 0x5014 - LBC Options Register 2 */
+ uint br3; /* 0x5018 - LBC Base Register 3 */
+ uint or3; /* 0x501c - LBC Options Register 3 */
+ uint br4; /* 0x5020 - LBC Base Register 4 */
+ uint or4; /* 0x5024 - LBC Options Register 4 */
+ uint br5; /* 0x5028 - LBC Base Register 5 */
+ uint or5; /* 0x502c - LBC Options Register 5 */
+ uint br6; /* 0x5030 - LBC Base Register 6 */
+ uint or6; /* 0x5034 - LBC Options Register 6 */
+ uint br7; /* 0x5038 - LBC Base Register 7 */
+ uint or7; /* 0x503c - LBC Options Register 7 */
+ char res1[40];
+ uint mar; /* 0x5068 - LBC UPM Address Register */
+ char res2[4];
+ uint mamr; /* 0x5070 - LBC UPMA Mode Register */
+ uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
+ uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
+ char res3[8];
+ uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
+ uint mdr; /* 0x5088 - LBC UPM Data Register */
+ char res4[8];
+ uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
+ char res5[8];
+ uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
+ uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
+ char res6[8];
+ uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
+ uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
+ uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
+ uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
+ uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
+ char res7[12];
+ uint lbcr; /* 0x50d0 - LBC Configuration Register */
+ uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
+ char res8[3880];
+} ccsr_lbc_t;
+
+/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
+typedef struct ccsr_pex {
+ uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
+ uint cfg_data; /* 0x8004 - PEX Configuration Data Register */
+ char res1[4];
+ uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */
+ char res2[16];
+ uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */
+ uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */
+ uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */
+ uint pm_command; /* 0x802c - PEX PM Command register */
+ char res3[3016];
+ uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */
+ uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */
+ uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
+ uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
+ char res4[8];
+ uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
+ char res5[12];
+ uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
+ uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
+ uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */
+ char res6[4];
+ uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
+ char res7[12];
+ uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
+ uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
+ uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */
+ char res8[4];
+ uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
+ char res9[12];
+ uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
+ uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
+ uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */
+ char res10[4];
+ uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
+ char res11[12];
+ uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
+ uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
+ uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */
+ char res12[4];
+ uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
+ char res13[12];
+ char res14[256];
+ uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */
+ char res15[4];
+ uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */
+ uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
+ uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
+ char res16[12];
+ uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */
+ char res17[4];
+ uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
+ uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
+ uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
+ char res18[12];
+ uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */
+ char res19[4];
+ uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */
+ uint piwbear1;
+ uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
+ char res20[12];
+ uint pedr; /* 0x8e00 - PEX Error Detect Register */
+ char res21[4];
+ uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */
+ char res22[4];
+ uint pecdr; /* 0x8e10 - PEX Error Disable Register */
+ char res23[12];
+ uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */
+ char res24[4];
+ uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */
+ uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */
+ uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */
+ uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */
+ char res25[452];
+ char res26[4];
+} ccsr_pex_t;
+
+/* Hyper Transport Register Block (0xA000-0xB000) */
+typedef struct ccsr_ht {
+ uint hcfg_addr; /* 0xa000 - HT Configuration Address register */
+ uint hcfg_data; /* 0xa004 - HT Configuration Data register */
+ char res1[3064];
+ uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */
+ char res2[12];
+ uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */
+ char res3[12];
+ uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */
+ char res4[4];
+ uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */
+ char res5[4];
+ uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */
+ char res6[12];
+ uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */
+ char res7[4];
+ uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */
+ char res8[4];
+ uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */
+ char res9[12];
+ uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */
+ char res10[4];
+ uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */
+ char res11[4];
+ uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */
+ char res12[12];
+ uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */
+ char res13[4];
+ uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */
+ char res14[4];
+ uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */
+ char res15[236];
+ uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */
+ char res16[4];
+ uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */
+ char res17[4];
+ uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */
+ char res18[12];
+ uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */
+ char res19[4];
+ uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */
+ char res20[4];
+ uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */
+ char res21[12];
+ uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */
+ char res22[4];
+ uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */
+ char res23[4];
+ uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */
+ char res24[12];
+ uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */
+ char res25[4];
+ uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */
+ char res26[4];
+ uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */
+ char res27[12];
+ uint hedr; /* 0xae00 - HT Error Detect register */
+ char res28[4];
+ uint heier; /* 0xae08 - HT Error Interrupt Enable register */
+ char res29[4];
+ uint hecdr; /* 0xae10 - HT Error Capture Disbale register */
+ char res30[12];
+ uint hecsr; /* 0xae20 - HT Error Capture Status register */
+ char res31[4];
+ uint hec0; /* 0xae28 - HT Error Capture 0 register */
+ uint hec1; /* 0xae2c - HT Error Capture 1 register */
+ uint hec2; /* 0xae30 - HT Error Capture 2 register */
+ char res32[460];
+} ccsr_ht_t;
+
+/* DMA Registers(0x2_1000-0x2_2000) */
+typedef struct ccsr_dma {
+ char res1[256];
+ uint mr0; /* 0x21100 - DMA 0 Mode Register */
+ uint sr0; /* 0x21104 - DMA 0 Status Register */
+ char res2[4];
+ uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
+ uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
+ uint sar0; /* 0x21114 - DMA 0 Source Address Register */
+ uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
+ uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
+ uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
+ char res3[4];
+ uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
+ char res4[8];
+ uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
+ char res5[4];
+ uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
+ uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
+ uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
+ char res6[56];
+ uint mr1; /* 0x21180 - DMA 1 Mode Register */
+ uint sr1; /* 0x21184 - DMA 1 Status Register */
+ char res7[4];
+ uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
+ uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
+ uint sar1; /* 0x21194 - DMA 1 Source Address Register */
+ uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
+ uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
+ uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
+ char res8[4];
+ uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
+ char res9[8];
+ uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
+ char res10[4];
+ uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
+ uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
+ uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
+ char res11[56];
+ uint mr2; /* 0x21200 - DMA 2 Mode Register */
+ uint sr2; /* 0x21204 - DMA 2 Status Register */
+ char res12[4];
+ uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
+ uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
+ uint sar2; /* 0x21214 - DMA 2 Source Address Register */
+ uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
+ uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
+ uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
+ char res13[4];
+ uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
+ char res14[8];
+ uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
+ char res15[4];
+ uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
+ uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
+ uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
+ char res16[56];
+ uint mr3; /* 0x21280 - DMA 3 Mode Register */
+ uint sr3; /* 0x21284 - DMA 3 Status Register */
+ char res17[4];
+ uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
+ uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
+ uint sar3; /* 0x21294 - DMA 3 Source Address Register */
+ uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
+ uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
+ uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
+ char res18[4];
+ uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
+ char res19[8];
+ uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
+ char res20[4];
+ uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
+ uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
+ uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
+ char res21[56];
+ uint dgsr; /* 0x21300 - DMA General Status Register */
+ char res22[3324];
+} ccsr_dma_t;
+
+/* tsec1-4: 24000-28000 */
+typedef struct ccsr_tsec {
+ uint id; /* 0x24000 - Controller ID Register */
+ char res1[12];
+ uint ievent; /* 0x24010 - Interrupt Event Register */
+ uint imask; /* 0x24014 - Interrupt Mask Register */
+ uint edis; /* 0x24018 - Error Disabled Register */
+ char res2[4];
+ uint ecntrl; /* 0x24020 - Ethernet Control Register */
+ char res2_1[4];
+ uint ptv; /* 0x24028 - Pause Time Value Register */
+ uint dmactrl; /* 0x2402c - DMA Control Register */
+ uint tbipa; /* 0x24030 - TBI PHY Address Register */
+ char res3[88];
+ uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
+ char res4[8];
+ uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
+ uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
+ char res4_1[4];
+ uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */
+ uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */
+ char res5[84];
+ uint tctrl; /* 0x24100 - Transmit Control Register */
+ uint tstat; /* 0x24104 - Transmit Status Register */
+ uint dfvlan; /* 0x24108 - Default VLAN control word */
+ char res6[4];
+ uint txic; /* 0x24110 - Transmit interrupt coalescing Register */
+ uint tqueue; /* 0x24114 - Transmit Queue Control Register */
+ char res7[40];
+ uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
+ uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
+ char res8[52];
+ uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
+ char res9[4];
+ uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
+ char res10[4];
+ uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
+ char res11[4];
+ uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
+ char res12[4];
+ uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
+ char res13[4];
+ uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
+ char res14[4];
+ uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
+ char res15[4];
+ uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
+ char res16[4];
+ uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
+ char res17[64];
+ uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
+ uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
+ char res18[4];
+ uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
+ char res19[4];
+ uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
+ char res20[4];
+ uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
+ char res21[4];
+ uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
+ char res22[4];
+ uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
+ char res23[4];
+ uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
+ char res24[4];
+ uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
+ char res25[192];
+ uint rctrl; /* 0x24300 - Receive Control Register */
+ uint rstat; /* 0x24304 - Receive Status Register */
+ char res26[8];
+ uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */
+ uint rqueue; /* 0x24314 - Receive queue control register */
+ char res27[24];
+ uint rbifx; /* 0x24330 - Receive bit field extract control Register */
+ uint rqfar; /* 0x24334 - Receive queue filing table address Register */
+ uint rqfcr; /* 0x24338 - Receive queue filing table control Register */
+ uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
+ uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
+ char res28[56];
+ uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
+ char res29[4];
+ uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
+ char res30[4];
+ uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
+ char res31[4];
+ uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
+ char res32[4];
+ uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
+ char res33[4];
+ uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
+ char res34[4];
+ uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
+ char res35[4];
+ uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
+ char res36[4];
+ uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
+ char res37[64];
+ uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
+ uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
+ char res38[4];
+ uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
+ char res39[4];
+ uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
+ char res40[4];
+ uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
+ char res41[4];
+ uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
+ char res42[4];
+ uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
+ char res43[4];
+ uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
+ char res44[4];
+ uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
+ char res45[192];
+ uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
+ uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
+ uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
+ uint hafdup; /* 0x2450c - Half Duplex Register */
+ uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
+ char res46[12];
+ uint miimcfg; /* 0x24520 - MII Management Configuration Register */
+ uint miimcom; /* 0x24524 - MII Management Command Register */
+ uint miimadd; /* 0x24528 - MII Management Address Register */
+ uint miimcon; /* 0x2452c - MII Management Control Register */
+ uint miimstat; /* 0x24530 - MII Management Status Register */
+ uint miimind; /* 0x24534 - MII Management Indicator Register */
+ uint ifctrl; /* 0x24538 - Interface Contrl Register */
+ uint ifstat; /* 0x2453c - Interface Status Register */
+ uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
+ uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
+ uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
+ uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
+ uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
+ uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
+ uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
+ uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
+ uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
+ uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
+ uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
+ uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
+ uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
+ uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
+ uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
+ uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
+ uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
+ uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
+ uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
+ uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
+ uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
+ uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
+ uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
+ uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
+ uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
+ uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
+ uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
+ uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
+ uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
+ uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
+ uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
+ uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */
+ char res48[192];
+ uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
+ uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
+ uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
+ uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
+ uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
+ uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
+ uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
+ uint rbyt; /* 0x2469c - Receive Byte Counter */
+ uint rpkt; /* 0x246a0 - Receive Packet Counter */
+ uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
+ uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
+ uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
+ uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
+ uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
+ uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
+ uint raln; /* 0x246bc - Receive Alignment Error Counter */
+ uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
+ uint rcde; /* 0x246c4 - Receive Code Error Counter */
+ uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
+ uint rund; /* 0x246cc - Receive Undersize Packet Counter */
+ uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
+ uint rfrg; /* 0x246d4 - Receive Fragments Counter */
+ uint rjbr; /* 0x246d8 - Receive Jabber Counter */
+ uint rdrp; /* 0x246dc - Receive Drop Counter */
+ uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
+ uint tpkt; /* 0x246e4 - Transmit Packet Counter */
+ uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
+ uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
+ uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
+ uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
+ uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
+ uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
+ uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
+ uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
+ uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
+ uint tncl; /* 0x2470c - Transmit Total Collision Counter */
+ char res49[4];
+ uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
+ uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
+ uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
+ uint txcf; /* 0x24720 - Transmit Control Frame Counter */
+ uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
+ uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
+ uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
+ uint car1; /* 0x24730 - Carry Register One */
+ uint car2; /* 0x24734 - Carry Register Two */
+ uint cam1; /* 0x24738 - Carry Mask Register One */
+ uint cam2; /* 0x2473c - Carry Mask Register Two */
+ uint rrej; /* 0x24740 - Receive filer rejected packet counter */
+ char res50[188];
+ uint iaddr0; /* 0x24800 - Indivdual address register 0 */
+ uint iaddr1; /* 0x24804 - Indivdual address register 1 */
+ uint iaddr2; /* 0x24808 - Indivdual address register 2 */
+ uint iaddr3; /* 0x2480c - Indivdual address register 3 */
+ uint iaddr4; /* 0x24810 - Indivdual address register 4 */
+ uint iaddr5; /* 0x24814 - Indivdual address register 5 */
+ uint iaddr6; /* 0x24818 - Indivdual address register 6 */
+ uint iaddr7; /* 0x2481c - Indivdual address register 7 */
+ char res51[96];
+ uint gaddr0; /* 0x24880 - Global address register 0 */
+ uint gaddr1; /* 0x24884 - Global address register 1 */
+ uint gaddr2; /* 0x24888 - Global address register 2 */
+ uint gaddr3; /* 0x2488c - Global address register 3 */
+ uint gaddr4; /* 0x24890 - Global address register 4 */
+ uint gaddr5; /* 0x24894 - Global address register 5 */
+ uint gaddr6; /* 0x24898 - Global address register 6 */
+ uint gaddr7; /* 0x2489c - Global address register 7 */
+ char res52[352];
+ uint fifocfg; /* 0x24A00 - FIFO interface configuration register */
+ char res53[500];
+ uint attr; /* 0x24BF8 - DMA Attribute register */
+ uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */
+ char res54[1024];
+} ccsr_tsec_t;
+
+/* PIC Registers(0x4_0000-0x6_1000) */
+
+typedef struct ccsr_pic {
+ char res1[64];
+ uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
+ char res2[12];
+ uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
+ char res3[12];
+ uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
+ char res4[12];
+ uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
+ char res5[12];
+ uint ctpr; /* 0x40080 - Current Task Priority Register */
+ char res6[12];
+ uint whoami; /* 0x40090 - Who Am I Register */
+ char res7[12];
+ uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
+ char res8[12];
+ uint eoi; /* 0x400b0 - End Of Interrupt Register */
+ char res9[3916];
+ uint frr; /* 0x41000 - Feature Reporting Register */
+ char res10[28];
+ uint gcr; /* 0x41020 - Global Configuration Register */
+ char res11[92];
+ uint vir; /* 0x41080 - Vendor Identification Register */
+ char res12[12];
+ uint pir; /* 0x41090 - Processor Initialization Register */
+ char res13[12];
+ uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
+ char res14[12];
+ uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
+ char res15[12];
+ uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
+ char res16[12];
+ uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
+ char res17[12];
+ uint svr; /* 0x410e0 - Spurious Vector Register */
+ char res18[12];
+ uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
+ char res19[12];
+ uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
+ char res20[12];
+ uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
+ char res21[12];
+ uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
+ char res22[12];
+ uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
+ char res23[12];
+ uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
+ char res24[12];
+ uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
+ char res25[12];
+ uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
+ char res26[12];
+ uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
+ char res27[12];
+ uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
+ char res28[12];
+ uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
+ char res29[12];
+ uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
+ char res30[12];
+ uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
+ char res31[12];
+ uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
+ char res32[12];
+ uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
+ char res33[12];
+ uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
+ char res34[12];
+ uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
+ char res35[268];
+ uint tcr; /* 0x41300 - Timer Control Register */
+ char res36[12];
+ uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
+ char res37[12];
+ uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
+ char res38[12];
+ uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
+ char res39[12];
+ uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
+ char res40[12];
+ uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */
+ char res41[12];
+ uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */
+ char res42[12];
+ uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */
+ char res43[12];
+ uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */
+ char res44[12];
+ uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */
+ char res45[12];
+ uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */
+ char res46[12];
+ uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */
+ char res47[12];
+ uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */
+ char res48[60];
+ uint msgr0; /* 0x41400 - Message Register 0 */
+ char res49[12];
+ uint msgr1; /* 0x41410 - Message Register 1 */
+ char res50[12];
+ uint msgr2; /* 0x41420 - Message Register 2 */
+ char res51[12];
+ uint msgr3; /* 0x41430 - Message Register 3 */
+ char res52[204];
+ uint mer; /* 0x41500 - Message Enable Register */
+ char res53[12];
+ uint msr; /* 0x41510 - Message Status Register */
+ char res54[60140];
+ uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
+ char res55[12];
+ uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
+ char res56[12];
+ uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
+ char res57[12];
+ uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
+ char res58[12];
+ uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
+ char res59[12];
+ uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
+ char res60[12];
+ uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
+ char res61[12];
+ uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
+ char res62[12];
+ uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
+ char res63[12];
+ uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
+ char res64[12];
+ uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
+ char res65[12];
+ uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
+ char res66[12];
+ uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
+ char res67[12];
+ uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
+ char res68[12];
+ uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
+ char res69[12];
+ uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
+ char res70[12];
+ uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
+ char res71[12];
+ uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
+ char res72[12];
+ uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
+ char res73[12];
+ uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
+ char res74[12];
+ uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
+ char res75[12];
+ uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
+ char res76[12];
+ uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
+ char res77[12];
+ uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
+ char res78[140];
+ uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
+ char res79[12];
+ uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
+ char res80[12];
+ uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
+ char res81[12];
+ uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
+ char res82[12];
+ uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
+ char res83[12];
+ uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
+ char res84[12];
+ uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
+ char res85[12];
+ uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
+ char res86[12];
+ uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
+ char res87[12];
+ uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
+ char res88[12];
+ uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
+ char res89[12];
+ uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
+ char res90[12];
+ uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
+ char res91[12];
+ uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
+ char res92[12];
+ uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
+ char res93[12];
+ uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
+ char res94[12];
+ uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
+ char res95[12];
+ uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
+ char res96[12];
+ uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
+ char res97[12];
+ uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
+ char res98[12];
+ uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
+ char res99[12];
+ uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
+ char res100[12];
+ uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
+ char res101[12];
+ uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
+ char res102[12];
+ uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
+ char res103[12];
+ uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
+ char res104[12];
+ uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
+ char res105[12];
+ uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
+ char res106[12];
+ uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
+ char res107[12];
+ uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
+ char res108[12];
+ uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
+ char res109[12];
+ uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
+ char res110[12];
+ uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
+ char res111[12];
+ uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
+ char res112[12];
+ uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
+ char res113[12];
+ uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
+ char res114[12];
+ uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
+ char res115[12];
+ uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
+ char res116[12];
+ uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
+ char res117[12];
+ uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
+ char res118[12];
+ uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
+ char res119[12];
+ uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
+ char res120[12];
+ uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
+ char res121[12];
+ uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
+ char res122[12];
+ uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
+ char res123[12];
+ uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
+ char res124[12];
+ uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
+ char res125[12];
+ uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
+ char res126[12];
+ uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
+ char res127[12];
+ uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
+ char res128[12];
+ uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
+ char res129[12];
+ uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
+ char res130[12];
+ uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
+ char res131[12];
+ uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
+ char res132[12];
+ uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
+ char res133[12];
+ uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
+ char res134[12];
+ uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
+ char res135[12];
+ uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
+ char res136[12];
+ uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
+ char res137[12];
+ uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
+ char res138[12];
+ uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
+ char res139[12];
+ uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
+ char res140[12];
+ uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
+ char res141[12];
+ uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
+ char res142[4108];
+ uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
+ char res143[12];
+ uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
+ char res144[12];
+ uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
+ char res145[12];
+ uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
+ char res146[12];
+ uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
+ char res147[12];
+ uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
+ char res148[12];
+ uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
+ char res149[12];
+ uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
+ char res150[59852];
+ uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
+ char res151[12];
+ uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
+ char res152[12];
+ uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
+ char res153[12];
+ uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
+ char res154[12];
+ uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
+ char res155[12];
+ uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
+ char res156[12];
+ uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
+ char res157[12];
+ uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
+ char res158[3916];
+} ccsr_pic_t;
+
+/* RapidIO Registers(0xc_0000-0xe_0000) */
+
+typedef struct ccsr_rio {
+ uint didcar; /* 0xc0000 - Device Identity Capability Register */
+ uint dicar; /* 0xc0004 - Device Information Capability Register */
+ uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
+ uint aicar; /* 0xc000c - Assembly Information Capability Register */
+ uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
+ uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
+ uint socar; /* 0xc0018 - Source Operations Capability Register */
+ uint docar; /* 0xc001c - Destination Operations Capability Register */
+ char res1[32];
+ uint msr; /* 0xc0040 - Mailbox Command And Status Register */
+ uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
+ char res2[4];
+ uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
+ char res3[12];
+ uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
+ uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
+ char res4[4];
+ uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
+ uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
+ char res5[144];
+ uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
+ char res6[28];
+ uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
+ uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
+ char res7[20];
+ uint pgccsr; /* 0xc013c - Port General Command and Status Register */
+ uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
+ uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
+ uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
+ char res8[12];
+ uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
+ uint pccsr; /* 0xc015c - Port Control Command and Status Register */
+ char res9[1184];
+ uint erbh; /* 0xc0600 - Error Reporting Block Header Register */
+ char res10[4];
+ uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */
+ uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */
+ char res11[4];
+ uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */
+ uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */
+ uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */
+ char res12[32];
+ uint edcsr; /* 0xc0640 - Port 0 error detect status register */
+ uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */
+ uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */
+ uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */
+ uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */
+ uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */
+ uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */
+ char res13[12];
+ uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */
+ uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/
+ char res14[63892];
+ uint llcr; /* 0xd0004 - Logical Layer Configuration Register */
+ char res15[12];
+ uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */
+ char res16[12];
+ uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */
+ char res17[92];
+ uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
+ char res18[124];
+ uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
+ char res19[28];
+ uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
+ char res20[12];
+ uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */
+ char res21[12];
+ uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
+ char res22[20];
+ uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */
+ char res23[4];
+ uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */
+ char res24[2716];
+ uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
+ uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
+ char res25[8];
+ uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
+ char res26[12];
+ uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
+ uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
+ uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
+ char res27[4];
+ uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
+ uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
+ uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
+ uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
+ uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
+ uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
+ uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
+ char res28[4];
+ uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
+ uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
+ uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
+ uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
+ uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
+ uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
+ uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
+ char res29[4];
+ uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
+ uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
+ uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
+ uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
+ uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
+ uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
+ uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
+ char res30[4];
+ uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
+ uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
+ uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
+ uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
+ uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
+ uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
+ uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
+ char res31[4];
+ uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
+ uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
+ uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
+ uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
+ uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
+ uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
+ uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
+ char res32[4];
+ uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
+ uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
+ uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
+ uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
+ uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
+ uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
+ uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
+ char res33[4];
+ uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
+ uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
+ uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
+ uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
+ uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
+ uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
+ uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
+ char res34[4];
+ uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
+ uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
+ uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
+ uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
+ char res35[64];
+ uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
+ uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
+ char res36[4];
+ uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
+ char res37[12];
+ uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
+ char res38[4];
+ uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
+ char res39[4];
+ uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
+ char res40[12];
+ uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
+ char res41[4];
+ uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
+ char res42[4];
+ uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
+ char res43[12];
+ uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
+ char res44[4];
+ uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
+ char res45[4];
+ uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
+ char res46[12];
+ uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
+ char res47[12];
+ uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
+ char res48[12];
+ uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
+ uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
+ uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
+ uint pecr; /* 0xd0e0c - Port Error Control Register */
+ uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
+ uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
+ uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
+ char res49[4];
+ uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
+ char res50[4];
+ uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
+ uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
+ char res51[8656];
+ uint omr; /* 0xd3000 - Outbound Mode Register */
+ uint osr; /* 0xd3004 - Outbound Status Register */
+ uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
+ uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
+ uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */
+ uint osar; /* 0xd3014 - Outbound Unit Source Address Register */
+ uint odpr; /* 0xd3018 - Outbound Destination Port Register */
+ uint odatr; /* 0xd301c - Outbound Destination Attributes Register */
+ uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */
+ uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
+ uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
+ uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */
+ uint omgr; /* 0xd3030 - Outbound Multicast Group Register */
+ uint omlr; /* 0xd3034 - Outbound Multicast List Register */
+ char res52[40];
+ uint imr; /* 0xd3060 - Outbound Mode Register */
+ uint isr; /* 0xd3064 - Inbound Status Register */
+ uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
+ uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
+ uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
+ uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
+ uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
+ char res53[900];
+ uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */
+ uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */
+ char res54[16];
+ uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */
+ uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */
+ char res55[12];
+ uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
+ char res56[48];
+ uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */
+ uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */
+ uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
+ uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
+ uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
+ uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
+ uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
+ char res57[100];
+ uint pwmr; /* 0xd34e0 - Port-Write Mode Register */
+ uint pwsr; /* 0xd34e4 - Port-Write Status Register */
+ uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */
+ uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */
+ char res58[51984];
+} ccsr_rio_t;
+
+/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
+typedef struct ccsr_gur {
+ uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
+ uint porbmsr; /* 0xe0004 - POR boot mode status register */
+#define MPC86xx_PORBMSR_HA 0x00060000
+ uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
+ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
+#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
+ uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
+ char res1[12];
+ uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
+ char res2[12];
+ uint gpiocr; /* 0xe0030 - GPIO control register */
+ char res3[12];
+ uint gpoutdr; /* 0xe0040 - General-purpose output data register */
+ char res4[12];
+ uint gpindr; /* 0xe0050 - General-purpose input data register */
+ char res5[12];
+ uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
+ char res6[12];
+ uint devdisr; /* 0xe0070 - Device disable control */
+#define MPC86xx_DEVDISR_PCIEX1 0x80000000
+#define MPC86xx_DEVDISR_PCIEX2 0x40000000
+ char res7[12];
+ uint powmgtcsr; /* 0xe0080 - Power management status and control register */
+ char res8[12];
+ uint mcpsumr; /* 0xe0090 - Machine check summary register */
+ char res9[12];
+ uint pvr; /* 0xe00a0 - Processor version register */
+ uint svr; /* 0xe00a4 - System version register */
+ char res10[3416];
+ uint clkocr; /* 0xe0e00 - Clock out select register */
+ char res11[12];
+ uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
+ char res12[12];
+ uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
+ int res13[57];
+ uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/
+ int res14[6];
+ uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
+ char res15[61656];
+} ccsr_gur_t;
+
+typedef struct immap {
+ ccsr_local_mcm_t im_local_mcm;
+ ccsr_ddr_t im_ddr1;
+ ccsr_i2c_t im_i2c;
+ ccsr_duart_t im_duart;
+ ccsr_lbc_t im_lbc;
+ ccsr_ddr_t im_ddr2;
+ char res1[4096];
+ ccsr_pex_t im_pex1;
+ ccsr_pex_t im_pex2;
+ ccsr_ht_t im_ht;
+ char res2[90112];
+ ccsr_dma_t im_dma;
+ char res3[8192];
+ ccsr_tsec_t im_tsec1;
+ ccsr_tsec_t im_tsec2;
+ ccsr_tsec_t im_tsec3;
+ ccsr_tsec_t im_tsec4;
+ char res4[98304];
+ ccsr_pic_t im_pic;
+ char res5[389120];
+ ccsr_rio_t im_rio;
+ ccsr_gur_t im_gur;
+} immap_t;
+
+extern immap_t *immr;
+
+#endif /*__IMMAP_86xx__*/
*/
typedef struct _pte {
- unsigned long page_num:20;
- unsigned long flags:12; /* Page flags (some unused bits) */
+ unsigned long page_num:20;
+ unsigned long flags:12; /* Page flags (some unused bits) */
} pte;
#define PD_SHIFT (10+12) /* Page directory */
#define BOOKE_PAGESZ_1GB 10
#define BOOKE_PAGESZ_4GB 11
+#if defined(CONFIG_MPC86xx)
+#define LAWBAR_BASE_ADDR 0x00FFFFFF
+#define LAWAR_TRGT_IF 0x01F00000
+#else
#define LAWBAR_BASE_ADDR 0x000FFFFF
-#define LAWAR_EN 0x80000000
#define LAWAR_TRGT_IF 0x00F00000
+#endif
+#define LAWAR_EN 0x80000000
#define LAWAR_SIZE 0x0000003F
#define LAWAR_TRGT_IF_PCI 0x00000000
#define LAWAR_TRGT_IF_PCI2 0x00100000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
+#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
#define LAWAR_TRGT_IF_RIO 0x00c00000
#define LAWAR_TRGT_IF_DDR 0x00f00000
+#define LAWAR_TRGT_IF_DDR1 0x00f00000
+#define LAWAR_TRGT_IF_DDR2 0x01600000
#define LAWAR_SIZE_BASE 0xa
#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
+#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21)
+#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
+#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
+#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
#ifdef CONFIG_440SPE
/*----------------------------------------------------------------------------+
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
+#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
#define SPRN_MBAR 0x137 /* System memory base address */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
#define ESR_ST 0x00800000 /* Store Operation */
+#if defined(CONFIG_MPC86xx)
+#define SPRN_MSSCRO 0x3f6
+#endif
+
+
/* Short-hand versions for a number of the above SPRNs */
#define CTR SPRN_CTR /* Counter Register */
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
+#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
-#if defined(CONFIG_E500)
+#if defined(CONFIG_MPC86xx)
+#define MSSCR0 SPRN_MSSCRO
+#endif
+#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define PIR SPRN_PIR
#endif
#define SVR SPRN_SVR /* System-On-Chip Version Register */
#define CSRR0 SPRN_CSRR0
#define CSRR1 SPRN_CSRR1
#define IVPR SPRN_IVPR
-#define USPRG0 SPRN_USPRG0
+#define USPRG0 SPRN_USPRG
#define SPRG4R SPRN_SPRG4R
#define SPRG5R SPRN_SPRG5R
#define SPRG6R SPRN_SPRG6R
#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
+#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
+#define PVR_440GRX1_RA 0x216218D8 /* 440GRX rev A with Security / Kasumi */
+#define PVR_440GRX2_RA 0x216218DC /* 440GRX rev A without Security / Kasumi */
#define PVR_440GX_RA 0x51B21850
#define PVR_440GX_RB 0x51B21851
#define PVR_440GX_RC 0x51B21892
#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
+#define PVR_86xx 0x80040000
+#define PVR_86xx_REV1 (PVR_86xx | 0x0010)
/*
* For the 8xx processors, all of them report the same PVR family for
#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
+#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
+
#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
#define SVR_8541 0x807A
#define SVR_8548 0x8031
#define SVR_8548_E 0x8039
+#define SVR_8641 0x8090
/* I am just adding a single entry for 8260 boards. I think we may be
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
- || defined(CONFIG_E500)
+ || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5xxx)
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
- defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
unsigned int bi_opbfreq; /* OPB clock in Hz */
int bi_iic_fast[2]; /* Use fast i2c mode */
#endif
#endif
#include <asm/immap_8260.h>
#endif
+#ifdef CONFIG_MPC86xx
+#include <mpc86xx.h>
+#include <asm/immap_86xx.h>
+#endif
#ifdef CONFIG_MPC85xx
#include <mpc85xx.h>
#include <asm/immap_85xx.h>
#define debugX(level,fmt,args...)
#endif /* DEBUG */
+#define BUG() do { \
+ printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
+ panic("BUG!"); \
+} while (0)
+#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
+
typedef void (interrupt_handler_t)(void *);
#include <asm/u-boot.h> /* boot information for Linux kernel */
char * strmhz(char *buf, long hz);
int last_stage_init(void);
extern ulong monitor_flash_len;
+#ifdef CFG_ID_EEPROM
+int mac_read_from_eeprom(void);
+#endif
/* common/flash.c */
void flash_perror (int);
void pci_master_init (struct pci_controller *);
# endif
int is_pci_host (struct pci_controller *);
+#if defined(CONFIG_440SPE)
+ void pcie_setup_hoses(void);
+#endif
#endif
int misc_init_f (void);
void jumptable_init(void);
/* common/memsize.c */
-int get_ram_size (volatile long *, long);
+long get_ram_size (volatile long *, long);
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \
defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \
- defined(CONFIG_METROBOX) || defined(CONFIG_KAREF)
+ defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) || \
+ defined(CONFIG_V38B)
void board_get_enetaddr (uchar *addr);
#endif
defined (CONFIG_74xx) || \
defined (CONFIG_MPC8220) || \
defined (CONFIG_MPC85xx) || \
+ defined (CONFIG_MPC86xx) || \
defined (CONFIG_MPC83XX)
unsigned char in8(unsigned int);
void out8(unsigned int, unsigned char);
typedef MPC85xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * );
#endif
+#if defined(CONFIG_MPC86xx)
+typedef MPC86xx_SYS_INFO sys_info_t;
+void get_sys_info ( sys_info_t * );
+#endif
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
unsigned long determine_pci_clock_per(void);
+ int ppc440spe_revB(void);
# endif
# else
typedef PPC405_SYS_INFO sys_info_t;
#if defined(CONFIG_8xx) || defined(CONFIG_8260)
void cpu_init_f (volatile immap_t *immr);
#endif
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
void cpu_init_f (void);
#endif
#endif
#ifdef CONFIG_INIT_CRITICAL
-#error CONFIG_INIT_CRITICAL is depracted!
+#error CONFIG_INIT_CRITICAL is deprecated!
#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
#endif
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
-#define CONFIG_EBONY 1 /* Board is ebony */
+#define CONFIG_CPCI440 1 /* Board is ebony */
+#define CONFIG_440GP 1 /* Specifc GP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CFG_PROMPT_HUSH_PS2 "> "
-#define CFG_AUTO_COMPLETE 1
+#define CONFIG_AUTO_COMPLETE 1
/* Define which ETH port will be used for connecting the network */
#define CFG_ETH_PORT ETH_0
PSDMR_LDOTOPRE_1C |\
PSDMR_WRC_1C |\
PSDMR_CL_2)
-
+
/*
* Init Memory Controller:
*
/* Include auto complete with tabs */
#define CONFIG_AUTO_COMPLETE 1
-#define CFG_AUTO_COMPLETE 1
#define CFG_ALT_MEMTEST 1 /* use real memory test */
/* Include auto complete with tabs */
#define CONFIG_AUTO_COMPLETE 1
-#define CFG_AUTO_COMPLETE 1
+#define CONFIG_AUTO_COMPLETE 1
#define CFG_ALT_MEMTEST 1 /* use real memory test */
* The board, however, can run at 66MHz. In any event, this value
* must match the settings of some switches. Details can be found
* in the README.mpc85xxads.
+ *
+ * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
+ * 33MHz to accommodate, based on a PCI pin.
+ * Note that PCI-X won't work at 33MHz.
*/
#ifndef CONFIG_SYS_CLK_FREQ
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8540@0"
+#define OF_SOC "soc8540@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF 1
+#define CFG_64BIT_STRTOUL 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/* RapidIO MMU */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+#define CFG_PCI1_IO_BASE 0x0
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
#if defined(CONFIG_PCI)
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/* General PCI */
#define CFG_PCI_MEM_BASE 0x80000000
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8541@0"
+#define OF_SOC "soc8541@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI2_IO_BASE 0xe3000000
-#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe2100000
+#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
#if defined(CONFIG_PCI)
+#define CONFIG_MPC85XX_PCI2
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
-#endif
-
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8548@0"
+#define OF_SOC "soc8548@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI2_IO_BASE 0xe3000000
-#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe2100000
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_85XX_PCI2
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
-#endif
-
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
#define CONFIG_MPC85XX_TSEC3 1
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
-#define CONFIG_MPC85XX_TSEC4 1
+#undef CONFIG_MPC85XX_TSEC4
#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
#define TSEC4_PHY_ADDR 3
-#define FEC_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
-#define FEC_PHYIDX 0
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
+
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8555@0"
+#define OF_SOC "soc8555@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI1_IO_BASE 0xe2000000
-#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI1_IO_BASE 0x00000000
+#define CFG_PCI1_IO_PHYS 0xe2000000
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PCI2_IO_BASE 0xe3000000
-#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
-#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+#define CFG_PCI2_IO_BASE 0x00000000
+#define CFG_PCI2_IO_PHYS 0xe2100000
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_MPC85XX_PCI2
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
- "ramdiskaddr=400000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0"
+ "ramdiskaddr=600000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "fdtaddr=400000\0" \
+ "fdtfile=your.fdt.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "bootm $loadaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8560@0"
+#define OF_SOC "soc8560@e0000000"
+#define OF_TBCLK (bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500"
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/* RapidIO MMU */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MPC8641HPCN board configuration file
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MPC86xx 1 /* MPC86xx */
+#define CONFIG_MPC8641 1 /* MPC8641 specific */
+#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
+#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */
+#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+#undef DEBUG
+
+#ifdef RUN_DIAG
+#define CFG_DIAG_ADDR 0xff800000
+#endif
+
+#define CFG_RESET_ADDRESS 0xfff00100
+
+/*#undef CONFIG_PCI*/
+#define CONFIG_PCI
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
+#undef CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
+#define CONFIG_DDR_ECC /* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+/* #define CONFIG_DDR_INTERLEAVE 1 */
+#define CACHE_LINE_INTERLEAVING 0x20000000
+#define PAGE_INTERLEAVING 0x21000000
+#define BANK_INTERLEAVING 0x22000000
+#define SUPER_BANK_INTERLEAVING 0x23000000
+
+
+#define CONFIG_ALTIVEC 1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CFG_L2
+#define L2_INIT 0
+#define L2_ENABLE (L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define MPC86xx_DDR_SDRAM_CLK_CNTL
+
+#if defined(CONFIG_SPD_EEPROM)
+ /*
+ * Determine DDR configuration from I2C interface.
+ */
+ #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
+ #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
+
+#else
+ /*
+ * Manually set up DDR1 parameters
+ */
+
+ #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
+
+ #define CFG_DDR_CS0_BNDS 0x0000000F
+ #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
+ #define CFG_DDR_EXT_REFRESH 0x00000000
+ #define CFG_DDR_TIMING_0 0x00260802
+ #define CFG_DDR_TIMING_1 0x39357322
+ #define CFG_DDR_TIMING_2 0x14904cc8
+ #define CFG_DDR_MODE_1 0x00480432
+ #define CFG_DDR_MODE_2 0x00000000
+ #define CFG_DDR_INTERVAL 0x06090100
+ #define CFG_DDR_DATA_INIT 0xdeadbeef
+ #define CFG_DDR_CLK_CTRL 0x03800000
+ #define CFG_DDR_OCD_CTRL 0x00000000
+ #define CFG_DDR_OCD_STATUS 0x00000000
+ #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
+ #define CFG_DDR_CONTROL2 0x04400000
+
+ /* Not used in fixed_sdram function */
+
+ #define CFG_DDR_MODE 0x00000022
+ #define CFG_DDR_CS1_BNDS 0x00000000
+ #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */
+ #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */
+ #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */
+ #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
+#endif
+
+#define CFG_ID_EEPROM 1
+#define ID_EEPROM_ADDR 0x57
+
+/*
+ * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000.
+ * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
+ * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
+ * However, when u-boot comes up, the flash_init needs hard start addresses
+ * to build its info table. For user convenience, the flash addresses is
+ * fe800000 and ff800000. That way, u-boot knows where the flash is
+ * and the user can download u-boot code from promjet to fef00000, a
+ * more intuitive location than fe700000.
+ *
+ * Note that, on switching the boot location, fef00000 becomes fff00000.
+ */
+#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */
+#define CFG_FLASH_BASE2 0xff800000
+
+#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
+
+#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */
+#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/
+
+#define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */
+#define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/
+
+#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */
+#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
+
+#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
+#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+
+
+#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
+#define PIXIS_ID 0x0 /* Board ID at offset 0 */
+#define PIXIS_VER 0x1 /* Board version at offset 1 */
+#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
+#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
+#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
+#define PIXIS_VCTL 0x10 /* VELA Control Register */
+#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
+#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
+#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
+#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
+#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
+#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
+
+#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
+#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#if defined(CFG_RAMBOOT)
+#undef CFG_FLASH_CFI_DRIVER
+#undef CONFIG_SPD_EEPROM
+#define CFG_SDRAM_SIZE 256
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#ifndef CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
+#else
+#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
+#endif
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree to kernel
+ */
+#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8641@0"
+#define OF_SOC "soc8641@f8000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500"
+
+#define CFG_64BIT_VSPRINTF 1
+#define CFG_64BIT_STRTOUL 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3100
+
+/*
+ * RapidIO MMU
+ */
+#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
+#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE 0x80000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
+
+/* For RTL8139 */
+#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
+#define _IO_BASE 0x00000000
+
+#define CFG_PCI2_MEM_BASE 0xa0000000
+#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_IO_BASE 0xe3000000
+#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#undef CFG_SCSI_SCAN_BUS_REVERSE
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_RTL8139
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CFG_SCSI_MAX_SCSI_ID 4
+#define CFG_SCSI_MAX_LUN 1
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
+#endif
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 1
+#endif
+
+#define CONFIG_MII 1 /* MII PHY management */
+
+#define CONFIG_MPC86XX_TSEC1 1
+#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1"
+#define CONFIG_MPC86XX_TSEC2 1
+#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2"
+#define CONFIG_MPC86XX_TSEC3 1
+#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3"
+#define CONFIG_MPC86XX_TSEC4 1
+#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4"
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+#define TSEC3_PHY_ADDR 2
+#define TSEC4_PHY_ADDR 3
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC4_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * BAT0 2G Cacheable, non-guarded
+ * 0x0000_0000 2G DDR
+ */
+#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
+#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CFG_IBAT0U CFG_DBAT0U
+
+/*
+ * BAT1 1G Cache-inhibited, guarded
+ * 0x8000_0000 512M PCI-Express 1 Memory
+ * 0xa000_0000 512M PCI-Express 2 Memory
+ * Changed it for operating from 0xd0000000
+ */
+#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U CFG_DBAT1U
+
+/*
+ * BAT2 512M Cache-inhibited, guarded
+ * 0xc000_0000 512M RapidIO Memory
+ */
+#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U CFG_DBAT2U
+
+/*
+ * BAT3 4M Cache-inhibited, guarded
+ * 0xf800_0000 4M CCSR
+ */
+#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U CFG_DBAT3U
+
+/*
+ * BAT4 32M Cache-inhibited, guarded
+ * 0xe200_0000 16M PCI-Express 1 I/O
+ * 0xe300_0000 16M PCI-Express 2 I/0
+ * Note that this is at 0xe0000000
+ */
+#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U CFG_DBAT4U
+
+/*
+ * BAT5 128K Cacheable, non-guarded
+ * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_IBAT5L CFG_DBAT5L
+#define CFG_IBAT5U CFG_DBAT5U
+
+/*
+ * BAT6 32M Cache-inhibited, guarded
+ * 0xfe00_0000 32M FLASH
+ */
+#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U CFG_DBAT6U
+
+#define CFG_DBAT7L 0x00000000
+#define CFG_DBAT7U 0x00000000
+#define CFG_IBAT7L 0x00000000
+#define CFG_IBAT7U 0x00000000
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #define CFG_ENV_SIZE 0x2000
+#else
+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+ #define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_PCI \
+ | CFG_CMD_I2C \
+ | CFG_CMD_SCSI \
+ | CFG_CMD_EXT2) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_IMLS \
+ | CFG_CMD_FLASH \
+ | CFG_CMD_LOADS))
+ #else
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_SCSI \
+ | CGF_CMD_EXT2) \
+ & \
+ ~(CFG_CMD_ENV \
+ | CFG_CMD_IMLS \
+ | CFG_CMD_FLASH \
+ | CFG_CMD_LOADS))
+ #endif
+#else
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PCI \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C \
+ | CFG_CMD_SCSI \
+ | CFG_CMD_EXT2)
+ #else
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_PING \
+ | CFG_CMD_I2C)
+ #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 00:E0:0C:00:00:01
+#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
+#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_HAS_ETH1 1
+#define CONFIG_HAS_ETH2 1
+#define CONFIG_HAS_ETH3 1
+
+#define CONFIG_IPADDR 192.168.1.100
+
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH /opt/nfsroot
+#define CONFIG_BOOTFILE uImage
+
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=your.ramdisk.u-boot\0" \
+ "dtbaddr=400000\0" \
+ "dtbfile=mpc8641_hpcn.dtb\0" \
+ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+ "maxcpus=2"
+
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif /* __CONFIG_H */
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/*
* EEPROM configuration
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/*
* EEPROM configuration
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
#define CFG_PCI_MEM_BASE 0xC0000000
#define CFG_PCI_MEM_PHYS 0xC0000000
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
-#ifndef CONFIG_CAM5200 /* On a Cameron board or ... */
+/* On a Cameron or on a FO300 board or ... */
+#if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300)
#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
#endif
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#ifdef CONFIG_FO300
+#define CFG_DEVICE_NULLDEV 1 /* enable null device */
+#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
+#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */
+#if 0
+#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
+ /* switch is closed */
+#endif
+
+#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
+ /* switch is open */
+#endif /* CONFIG_FO300 */
+
#ifdef CONFIG_STK52XX
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
#define CONFIG_VIDEO_SM501_32BPP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
+
+#ifndef CONFIG_FO300
#define CONFIG_CONSOLE_EXTRA_INFO
+#else
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CFG_CONSOLE_IS_IN_ENV
-#endif
+#endif /* #ifndef CONFIG_TQM5200S */
#ifdef CONFIG_VIDEO
#define ADD_BMP_CMD CFG_CMD_BMP
#define CONFIG_ISO_PARTITION
/* USB */
-#ifdef CONFIG_STK52XX
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
#define CONFIG_USB_OHCI_NEW
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#endif
/* IDE */
-#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
+#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300)
#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
#else
#define ADD_IDE_CMD 0
#undef CONFIG_BOOTARGS
-#ifdef CONFIG_STK52XX
-# if defined(CONFIG_TQM5200_B)
-# if defined(CFG_LOWBOOT)
-# define ENV_UPDT \
- "update=protect off FC000000 FC07FFFF;" \
- "erase FC000000 FC07FFFF;" \
- "cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC07FFFF\0"
-# else /* highboot */
-# define ENV_UPDT \
- "update=protect off FFF00000 FFF7FFFF;" \
- "erase FFF00000 FFF7FFFF;" \
+#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT)
+# define ENV_UPDT \
+ "update=protect off FFF00000 +${filesize};" \
+ "erase FFF00000 +${filesize};" \
"cp.b 200000 FFF00000 ${filesize};" \
- "protect on FFF00000 FFF7FFFF\0"
-# endif /* CFG_LOWBOOT */
-# else /* !CONFIG_TQM5200_B */
-# define ENV_UPDT \
- "update=protect off FC000000 FC05FFFF;" \
- "erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC05FFFF\0"
-# endif /* CONFIG_TQM5200_B */
-#elif defined (CONFIG_CAM5200)
+ "protect on FFF00000 +${filesize}\0"
+#else /* default lowboot configuration */
# define ENV_UPDT \
- "update=protect off FC000000 FC03FFFF;" \
- "erase FC000000 FC03FFFF;" \
+ "update=protect off FC000000 +${filesize};" \
+ "erase FC000000 +${filesize};" \
"cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC03FFFF\0"
-#else
-# error "Unknown Carrier Board"
-#endif /* CONFIG_STK52XX */
+ "protect on FC000000 +${filesize}\0"
+#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
-#if defined(CFG_IPBSPEED_133)
+#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200)
/*
* PCI Bus clocking configuration
*
*/
#define CFG_FLASH_BASE 0xFC000000
+#ifndef CONFIG_CAM5200
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
+ (= chip selects) */
+#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#else /* CONFIG_CAM5200 */
+#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks
+ (= chip selects) */
+#define CFG_FLASH_WORD_SIZE unsigned int /* main flash device with */
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0 0x555
+#define CFG_FLASH_ADDR1 0x2AA
+#define CFG_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
+#define CFG_MAX_FLASH_SECT 128
+#endif /* ifndef CONFIG_CAM5200 */
+
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
-#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#define CFG_FLASH_USE_BUFFER_WRITE 1
#if defined (CONFIG_CAM5200)
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
#endif
-#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
- (= chip selects) */
-
/* Dynamic MTD partition support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM5200-0"
#elif defined (CONFIG_CAM5200)
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
"1792k(kernel)," \
- "3584k(small-fs)," \
+ "5632k(rootfs)," \
+ "24m(home)"
+#elif defined (CONFIG_FO300)
+# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
+ "1408k(kernel)," \
"2m(initrd)," \
+ "4m(small-fs)," \
"8m(misc)," \
"16m(big-fs)"
#else
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
-#if defined(CONFIG_TQM5200_B)
+#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
#define CFG_ENV_SECT_SIZE 0x40000
#else
#define CFG_ENV_SECT_SIZE 0x20000
/*
* GPIO configuration
*
- * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
- * Bit 0 (mask: 0x80000000): 1
+ * use CS1: Bit 0 (mask: 0x80000000):
+ * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
- * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
- * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
- * Use for REV200 STK52XX boards. Do not use with REV100 modules
- * (because, there I2C1 is used as I2C bus)
- * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
- * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
- * 000 -> All PSC2 pins are GIOPs
- * 001 -> CAN1/2 on PSC2 pins
- * Use for REV100 STK52xx boards
- * use PSC6:
- * on STK52xx:
- * use as UART. Pins PSC6_0 to PSC6_3 are used.
- * Bits 9:11 (mask: 0x00700000):
- * 101 -> PSC6 : Extended POST test is not available
- * on MINI-FAP and TQM5200_IB:
- * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
- * 000 -> PSC6 could not be used as UART, CODEC or IrDA
- * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
- * tests.
+ * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ * SPI on PSC3 according to PSC3 setting. Use for CAM5200.
+ * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ * Use for REV200 STK52XX boards and FO300 boards. Do not use
+ * with REV100 modules (because, there I2C1 is used as I2C bus).
+ * use ATA: Bits 6-7 (mask 0x03000000):
+ * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
+ * Use for CAM5200 board.
+ * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
+ * use PSC6: Bits 9-11 (mask 0x00700000):
+ * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
+ * UART, CODEC or IrDA.
+ * GPIO on PSC6_3 is used in post_hotkeys_pressed() to
+ * enable extended POST tests.
+ * Use for MINI-FAP and TQM5200_IB boards.
+ * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
+ * Extended POST test is not available.
+ * Use for STK52xx, FO300 and CAM5200 boards.
+ * use PCI_DIS: Bit 16 (mask 0x00008000):
+ * 1 -> disable PCI controller (on CAM5200 board).
+ * use USB: Bits 18-19 (mask 0x00003000):
+ * 10 -> two UARTs (on FO300 and CAM5200).
+ * use PSC3: Bits 20-23 (mask: 0x00000f00):
+ * 0000 -> All PSC3 pins are GPIOs.
+ * 1100 -> UART/SPI (on FO300 board).
+ * 0100 -> UART (on CAM5200 board).
+ * use PSC2: Bits 25:27 (mask: 0x00000030):
+ * 000 -> All PSC2 pins are GPIOs.
+ * 100 -> UART (on CAM5200 board).
+ * 001 -> CAN1/2 on PSC2 pins.
+ * Use for REV100 STK52xx boards
+ * 01x -> Use AC97 (on FO300 board).
+ * use PSC1: Bits 29-31 (mask: 0x00000007):
+ * 100 -> UART (on all boards).
*/
#if defined (CONFIG_MINIFAP)
# define CFG_GPS_PORT_CONFIG 0x91000004
# define CFG_GPS_PORT_CONFIG 0x91500004
# endif
# endif
+#elif defined (CONFIG_FO300)
+# define CFG_GPS_PORT_CONFIG 0x91502c24
+#elif defined (CONFIG_CAM5200)
+# define CFG_GPS_PORT_CONFIG 0x8050A444
#else /* TMQ5200 Inbetriebnahme-Board */
# define CFG_GPS_PORT_CONFIG 0x81000004
#endif
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
+#if defined(CONFIG_CAM5200)
+#define CFG_CS4_START 0xB0000000
+#define CFG_CS4_SIZE 0x00010000
+#define CFG_CS4_CFG 0x01019C10
+
+#define CFG_CS5_START 0xD0000000
+#define CFG_CS5_SIZE 0x01208000
+#define CFG_CS5_CFG 0x1414BF10
+#endif
+
#define CFG_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_SICRL SICRL_LDP_A
/* i-cache and d-cache disabled */
-#define CFG_HID0_INIT 0x000000000
-#define CFG_HID0_FINAL CFG_HID0_INIT
-#define CFG_HID2 0x000000000
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL CFG_HID0_INIT
+#define CFG_HID2 HID2_HBE
/* DDR 0 - 512M */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
/* PCI */
-#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#ifdef CONFIG_PCI
+#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT3L (0)
+#define CFG_IBAT3U (0)
+#define CFG_IBAT4L (0)
+#define CFG_IBAT4U (0)
+#define CFG_IBAT5L (0)
+#define CFG_IBAT5U (0)
+#endif
/* IMMRBAR */
#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-/* Use the HUSH parser */
-#define CFG_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
/* I2C RTC */
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
"run nfsargs addip addcons;bootm\0" \
"rootpath=/opt/eldk/ppc_85xx\0" \
"kernel_addr=FE000000\0" \
- "ramdisk_addr=FE100000\0" \
+ "ramdisk_addr=FE180000\0" \
"load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if 0
-#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
--- /dev/null
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1002 CPU daughterboard
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AVR32 1
+#define CONFIG_AT32AP 1
+#define CONFIG_AT32AP7000 1
+#define CONFIG_ATSTK1002 1
+#define CONFIG_ATSTK1000 1
+
+#define CONFIG_ATSTK1000_EXT_FLASH 1
+
+/*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+ */
+#define CFG_HZ 1000
+
+/*
+ * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
+ * frequency and the peripherals to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL 1
+#define CFG_POWER_MANAGER 1
+#define CFG_OSC0_HZ 20000000
+#define CFG_PLL0_DIV 1
+#define CFG_PLL0_MUL 7
+#define CFG_PLL0_SUPPRESS_CYCLES 16
+#define CFG_CLKDIV_CPU 0
+#define CFG_CLKDIV_HSB 1
+#define CFG_CLKDIV_PBA 2
+#define CFG_CLKDIV_PBB 1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ * icp = PLLOPT<2>
+ * ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CFG_PLL0_OPT 0x04
+
+#define CFG_USART1 1
+
+#define CFG_CONSOLE_UART_DEV DEVICE_USART1
+
+/* User serviceable stuff */
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_STACKSIZE (2048)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS \
+ "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k"
+
+#define CONFIG_COMMANDS (CFG_CMD_BDI \
+ | CFG_CMD_LOADS \
+ | CFG_CMD_LOADB \
+ /* | CFG_CMD_IMI */ \
+ /* | CFG_CMD_CACHE */ \
+ | CFG_CMD_FLASH \
+ | CFG_CMD_MEMORY \
+ /* | CFG_CMD_NET */ \
+ | CFG_CMD_ENV \
+ /* | CFG_CMD_IRQ */ \
+ | CFG_CMD_BOOTD \
+ | CFG_CMD_CONSOLE \
+ /* | CFG_CMD_EEPROM */ \
+ | CFG_CMD_ASKENV \
+ | CFG_CMD_RUN \
+ | CFG_CMD_ECHO \
+ /* | CFG_CMD_I2C */ \
+ | CFG_CMD_REGINFO \
+ /* | CFG_CMD_DATE */ \
+ /* | CFG_CMD_DHCP */ \
+ /* | CFG_CMD_AUTOSCRIPT */ \
+ /* | CFG_CMD_MII */ \
+ | CFG_CMD_MISC \
+ /* | CFG_CMD_SDRAM */ \
+ /* | CFG_CMD_DIAG */ \
+ /* | CFG_CMD_HWFLOW */ \
+ /* | CFG_CMD_SAVES */ \
+ /* | CFG_CMD_SPI */ \
+ /* | CFG_CMD_PING */ \
+ /* | CFG_CMD_MMC */ \
+ /* | CFG_CMD_FAT */ \
+ /* | CFG_CMD_IMLS */ \
+ /* | CFG_CMD_ITEST */ \
+ /* | CFG_CMD_EXT2 */ \
+ )
+
+#include <cmd_confdefs.h>
+
+#define CONFIG_ATMEL_USART 1
+#define CONFIG_PIO2 1
+#define CFG_NR_PIOS 5
+#define CFG_HSDRAMC 1
+
+#define CFG_DCACHE_LINESZ 32
+#define CFG_ICACHE_LINESZ 32
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+/* External flash on STK1000 */
+#if 0
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#endif
+
+#define CFG_FLASH_BASE 0x00000000
+#define CFG_FLASH_SIZE 0x800000
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 135
+
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+
+#define CFG_INTRAM_BASE 0x24000000
+#define CFG_INTRAM_SIZE 0x8000
+
+#define CFG_SDRAM_BASE 0x10000000
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 65536
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
+
+#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+#define CFG_MALLOC_LEN (256*1024)
+#define CFG_MALLOC_END \
+ ({ \
+ DECLARE_GLOBAL_DATA_PTR; \
+ CFG_SDRAM_BASE + gd->sdram_size; \
+ })
+#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN)
+
+#define CFG_DMA_ALLOC_LEN (16384)
+#define CFG_DMA_ALLOC_END (CFG_MALLOC_START)
+#define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN)
+/* Allow 2MB for the kernel run-time image */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
+#define CFG_BOOTPARAMS_LEN (16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CFG_PROMPT "Uboot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 8
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+
+#define CFG_MEMTEST_START \
+ ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
+#define CFG_MEMTEST_END \
+ ({ \
+ DECLARE_GLOBAL_DATA_PTR; \
+ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
+ })
+#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
- CFG_CMD_EEPROM | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
+ CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CONFIG_CMDLINE_EDITING
-
-#ifdef CONFIG_CMDLINE_EDITING
-#undef CONFIG_AUTO_COMPLETE
-#else
-#define CONFIG_AUTO_COMPLETE
-#endif
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
+ CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
--- /dev/null
+/*
+ * Copyright (C) 2006 Embedded Planet, LLC.
+ *
+ * U-Boot configuration for Embedded Planet EP82xxM boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC8260
+#define CPU_ID_STR "MPC8270"
+
+#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
+ /* 256MB SDRAM / 64MB FLASH */
+
+#undef DEBUG
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define CONFIG_CONS_ON_SMC /* Console is on SMC */
+#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
+#undef CONFIG_CONS_NONE /* It's not on external UART */
+#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
+
+#define CFG_BCSR 0xFA000000
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CFG_CMD_NET must
+ * be removed from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
+#undef CONFIG_ETHER_NONE /* No external Ethernet */
+
+#define CONFIG_NET_MULTI
+
+#define CONFIG_ETHER_ON_FCC2
+#define CONFIG_ETHER_ON_FCC3
+
+#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
+#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+
+#define CFG_CPMFCR_RAMTYPE 0
+#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
+
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT 0 /* Not used - implemented in BCSR */
+#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04)
+#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1)
+
+#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
+ else *(vu_char *)(CFG_BCSR + 8) &= 0xFE
+
+#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
+ else *(vu_char *)(CFG_BCSR + 8) &= 0xFD
+
+#define MIIDELAY udelay(1)
+
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN 66000000 /* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_DHCP \
+ | CFG_CMD_ECHO \
+ | CFG_CMD_I2C \
+ | CFG_CMD_IMMAP \
+ | CFG_CMD_MII \
+ | CFG_CMD_PING \
+ | CFG_CMD_DATE \
+ | CFG_CMD_DTT \
+ | CFG_CMD_EEPROM \
+ | CFG_CMD_PCI \
+ | CFG_CMD_DIAG \
+ )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_ETHADDR 00:10:EC:00:88:65
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:10:EC:80:88:65
+#define CONFIG_IPADDR 10.0.0.245
+#define CONFIG_HOSTNAME EP82xxM
+#define CONFIG_SERVERIP 10.0.0.26
+#define CONFIG_GATEWAYIP 10.0.0.1
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CFG_ENV_IN_OWN_SECT 1
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3 ETHERNET"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
+#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
+#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "ep82xxm=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE 0xFC000000
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+/* EEPROM Configuration */
+#define CFG_EEPROM_SIZE 0x1000
+#define CFG_I2C_EEPROM_ADDR 0x54
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
+#define CFG_ENV_OFFSET 0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+/* RTC Configuration */
+#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */
+#define CFG_I2C_RTC_ADDR 0x68
+#define CONFIG_M41T11_BASE_YEAR 1900
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75 1
+#define CONFIG_DTT_SENSORS {0}
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_LOW_TEMP -30
+#define CFG_DTT_HYSTERESIS 3
+
+/*-----------------------------------------------------------------------
+ * NVRAM Configuration
+ *-----------------------------------------------------------------------
+ */
+#define CFG_NVRAM_BASE_ADDR 0xFA080000
+#define CFG_NVRAM_SIZE (128*1024)-16
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_PCI_BOOTDELAY 0
+
+/* PCI Memory map (if different from default map */
+#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
+#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
+#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
+ PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
+#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
+#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
+#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
+#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
+#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
+#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
+#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
+#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
+#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
+#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
+#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
+#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+
+/* PCIBR0 - for PCI IO*/
+#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */
+#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
+/* PCIBR1 - prefetch and non-prefetch regions joined together */
+#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL
+#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
+
+
+#define CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_FIRST_SECTOR 0
+#define CFG_JFFS2_LAST_SECTOR 62
+#define CFG_JFFS2_SORT_FRAGMENTS
+#define CFG_JFFS_CUSTOM_PART
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C 1 /* To enable I2C support */
+#define CFG_I2C_SPEED 100000 /* I2C speed */
+#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
+#endif /* CFG_CMD_I2C */
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */
+
+#define CFG_DEFAULT_IMMR 0x00010000
+#define CFG_IMMR 0xF0000000
+
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+
+/* Hard reset configuration word */
+#define CFG_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */
+/* No slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
+
+#define CFG_HID2 0
+
+#define CFG_SIUMCR 0x02610000
+#define CFG_SYPCR 0xFFFF0689
+#define CFG_BCR 0x8080E000
+#define CFG_SCCR 0x00000001
+
+#define CFG_RMR 0
+#define CFG_TMCNTSC 0x000000C3
+#define CFG_PISCR 0x00000083
+#define CFG_RCCR 0
+
+#define CFG_MPTPR 0x0A00
+#define CFG_PSDMR 0xC432246E
+#define CFG_PSRT 0x32
+
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041)
+#define CFG_SDRAM_OR 0xF0002900
+
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801)
+#define CFG_OR0_PRELIM 0xFC000882
+#define CFG_BR4_PRELIM (CFG_BCSR | 0x00001001)
+#define CFG_OR4_PRELIM 0xFFF00050
+
+#define CFG_RESET_ADDRESS 0xFFF00100
+
+#endif /* __CONFIG_H */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
+ CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#define CONFIG_MISC_INIT_R
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* To select console on the one of 8 external UARTs,
* define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
* or as 5, 6, 7, or 8 for the second Quad UART.
+ * COM11, COM12, COM13, COM14 are located on the second Quad UART.
*
* CONFIG_PSC_CONSOLE must be undefined in this case.
*/
-/* #define CONFIG_QUART_CONSOLE 1 */ /* console is on UART1 of QUART1 */
+#if !defined(CONFIG_PRS200)
+/* MCC200 configuration: */
+#ifdef CONFIG_CONSOLE_COM12
+#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */
+#else
+#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */
+#endif
+#else
+/* PRS200 configuration: */
+#undef CONFIG_QUART_CONSOLE
+#endif /* CONFIG_PRS200 */
/*
* To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
* and undefine CONFIG_QUART_CONSOLE.
*/
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
+#if !defined(CONFIG_PRS200)
+/* MCC200 configuration: */
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */
+#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */
+#else
+/* PRS200 configuration: */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#endif
+#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
+ !defined(CONFIG_SERIAL_MULTI)
#error "Select only one console device!"
#endif
#define CONFIG_BAUDRATE 115200
/* USB */
#define CONFIG_USB_OHCI
-#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
/*
#undef CONFIG_BOOTARGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
+
+#ifdef CONFIG_PRS200
+# define CFG__BOARDNAME "prs200"
+# define CFG__LINUX_CONSOLE "ttyS0"
+#else
+# define CFG__BOARDNAME "mcc200"
+# define CFG__LINUX_CONSOLE "ttyEU7"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "hostname=mcc200\0" \
+ "hostname=" CFG__BOARDNAME "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
+ "addcons=setenv bootargs ${bootargs} " \
+ "console=${console},${baudrate}\0" \
+ "flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip;" \
+ "flash_self=run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addcons;bootm\0" \
+ "console=" CFG__LINUX_CONSOLE "\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
- "bootfile=/tftpboot/mcc200/uImage\0" \
- "baudrate=115200\0" \
- "load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0" \
- "update=protect off FFF00000 +${filesize};" \
- "era FFF00000 +${filesize};" \
- "cp.b 200000 FFF00000 ${filesize}\0" \
- "serverip=192.168.1.1\0" \
- "ipaddr=192.168.133.144\0" \
- "netmask=255.255.0.0\0" \
+ "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \
+ "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \
+ "text_base=" MK_STR(TEXT_BASE) "\0" \
+ "update=protect off ${text_base} +${filesize};" \
+ "era ${text_base} +${filesize};" \
+ "cp.b 200000 ${text_base} ${filesize}\0" \
"unlock=yes\0" \
- "ethaddr=00:02:44:7D:73:3B\0" \
""
+#undef MK_STR
+#undef XMK_STR
#define CONFIG_BOOTCOMMAND "run flash_self"
/*
* IPB Bus clocking configuration.
*/
-#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+#define CFG_IPBSPEED_133 /* define for 133MHz speed */
/*
* I2C configuration
* TEXT base always at 0xFFF00000
* ENV_ADDR always at 0xFFF40000
* FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
- * 0xFE000000 for 32 MB
- * 0xFF000000 for 16 MB
- * 0xFF800000 for 8 MB
+ * 0xFE000000 for 32 MB
+ * 0xFF000000 for 16 MB
+ * 0xFF800000 for 8 MB
*/
#define CFG_FLASH_BASE 0xfc000000
#define CFG_FLASH_SIZE 0x04000000
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1
#endif
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR 1
+/*
+ * LCD Splash Screen
+ */
+#if !defined(CONFIG_PRS200)
+#define CONFIG_LCD 1
+#endif
+
+#if defined(CONFIG_LCD)
+#define CONFIG_SPLASH_SCREEN 1
+#define CFG_CONSOLE_IS_IN_ENV 1
+#define LCD_BPP LCD_MONOCHROME
+#endif
+
/*
* GPIO configuration
*/
/* 0x10000004 = 32MB SDRAM */
/* 0x90000004 = 64MB SDRAM */
+#if defined(CONFIG_LCD)
+/* set PSC2 in UART mode */
+#define CFG_GPS_PORT_CONFIG 0x00000044
+#else
#define CFG_GPS_PORT_CONFIG 0x00000004
+#endif
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
* One of four SC16C554 UARTs is selected with
* A3-A4 (DA5-DA6) lines.
*/
-#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5)
+#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
#define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
#define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_RESET_DELAY 1000
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
+ CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET 0x3000
#define CFG_PCI_MEM_BASE 0xC0000000
#define CFG_PCI_MEM_PHYS 0xC0000000
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * sequoia.h - configuration for Sequoia board (PowerPC440EPx)
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
+#ifndef CONFIG_RAINIER
+#define CONFIG_SEQUOIA 1 /* Board is Sequoia */
+#define CONFIG_440EPX 1 /* Specific PPC440EPx */
+#else
+#define CONFIG_440GRX 1 /* Specific PPC440GRx */
+#endif
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+
+#define CFG_BOOT_BASE_ADDR 0xf0000000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
+#define CFG_OCM_BASE 0xe0010000 /* ocm */
+#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
+
+#define CFG_USB2D0_BASE 0xe0000100
+#define CFG_USB_DEVICE 0xe0000000
+#define CFG_USB_HOST 0xe0000400
+#define CFG_BCSR_BASE 0xc0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
+#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
+#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
+
+#define CFG_INIT_RAM_END (4 << 10)
+#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SERIAL_MULTI 1
+/* define this if you want console on UART1 */
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
+#else
+#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif
+
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller. sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
+#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
+#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
+#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
+#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
+#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */
+#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
+#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */
+#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */
+#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
+
+#ifdef CFG_ENV_IS_IN_NAND
+/*
+ * For NAND booting the environment is embedded in the U-Boot image. Please take
+ * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
+ */
+#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM (256) /* 256MB */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
+#define CONFIG_DTT_AD7414 1 /* use AD7414 */
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP 70
+#define CFG_DTT_LOW_TEMP -30
+#define CFG_DTT_HYSTERESIS 3
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=sequoia\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xxFP\0" \
+ "bootfile=/tftpboot/sequoia/uImage\0" \
+ "kernel_addr=FC000000\0" \
+ "ramdisk_addr=FC180000\0" \
+ "load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \
+ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
+ "cp.b 100000 FFFA0000 60000\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_M88E1111_PHY 1
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI 1
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_PHY1_ADDR 1
+
+/* USB */
+#ifdef CONFIG_440EPX
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+#define CMD_USB CFG_CMD_USB
+#else
+#define CMD_USB 0 /* no USB on 440GRx */
+#endif /* CONFIG_440EPX */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DTT | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ CFG_CMD_FAT | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NAND | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CMD_USB)
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH CFG_FLASH_BASE
+#define CFG_NAND 0xD0000000
+#define CFG_CPLD 0xC0000000
+
+/*
+ * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
+ */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x03017300
+#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
+
+/* Memory Bank 3 (NAND-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x018003c0
+#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000)
+#else
+#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
+/* Memory Bank 3 (NOR-FLASH) initialization */
+#define CFG_EBC_PB3AP 0x03017300
+#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000)
+
+/* Memory Bank 0 (NAND-FLASH) initialization */
+#define CFG_EBC_PB0AP 0x018003c0
+#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000)
+#endif
+
+/* Memory Bank 2 (CPLD) initialization */
+#define CFG_EBC_PB2AP 0x24814580
+#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000)
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+#endif /* __CONFIG_H */
#define CONFIG_MPC8220_FEC 1
#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
#define CONFIG_PHY_ADDR 0x1F
+#define CONFIG_MII 1
/*
* Miscellaneous configurable options
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-/* I2C */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
#undef CFG_I2C_NOPROBES
#endif
+#define CFG_I2C_OFFSET 0x3000
/* RapdIO Map configuration, mapped 1:1.
*/
--- /dev/null
+/*
+ * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
+ * wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
+#define CONFIG_V38B 1 /* ...on V38B board */
+#define CFG_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
+
+#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
+#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
+
+#undef CONFIG_HW_WATCHDOG /* don't use watchdog */
+
+#define CONFIG_NETCONSOLE 1
+
+#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
+
+#define CFG_XLB_PIPELINING 1 /* gives better performance */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * DDR
+ */
+#define SDRAM_DDR 1 /* is DDR */
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x704f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+/*
+ * PCI - no suport
+ */
+#undef CONFIG_PCI
+
+/*
+ * Partitions
+ */
+#define CONFIG_MAC_PARTITION 1
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00001000
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_FAT | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
+ CFG_CMD_PING | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_MII | \
+ CFG_CMD_SDRAMi | \
+ CFG_CMD_DATE | \
+ CFG_CMD_USB | \
+ CFG_CMD_FAT)
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Boot low with 16 MB Flash
+ */
+#define CFG_LOWBOOT 1
+#define CFG_LOWBOOT16 1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootcmd=run net_nfs\0" \
+ "bootdelay=3\0" \
+ "baudrate=115200\0" \
+ "preboot=echo;echo Type \"run flash_nfs\" to mount root " \
+ "filesystem over NFS; echo\0" \
+ "netdev=eth0\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):" \
+ "$(netmask):$(hostname):$(netdev):off panic=1\0" \
+ "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
+ "flash_self=run ramargs addip;bootm $(kernel_addr) " \
+ "$(ramdisk_addr)\0" \
+ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "hostname=v38b\0" \
+ "ethact=FEC ETHERNET\0" \
+ "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
+ "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
+ "cp.b 200000 ff000000 $(filesize);" \
+ "prot on ff000000 ff03ffff\0" \
+ "load=tftp 200000 $(u-boot)\0" \
+ "netmask=255.255.0.0\0" \
+ "ipaddr=192.168.160.18\0" \
+ "serverip=192.168.1.1\0" \
+ "ethaddr=00:e0:ee:00:05:2e\0" \
+ "bootfile=/tftpboot/v38b/uImage\0" \
+ "u-boot=/tftpboot/v38b/u-boot.bin\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
+
+/*
+ * RTC configuration
+ */
+#define CFG_I2C_RTC_ADDR 0x51
+
+/*
+ * Flash configuration - use CFI driver
+ */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_CFI_AMD_RESET 1
+#define CFG_FLASH_BASE 0xFF000000
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */
+#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
+#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_OVERWRITE 1
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT 1
+#endif
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_MII 1
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG 0x90001404
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG 0x00047801
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x33333333
+
+#define CFG_RESET_ADDRESS 0xff000000
+
+/*
+ * IDE/ATA (supports IDE harddisk)
+ */
+#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+
+#define CFG_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
+
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* normal register accesses offset */
+
+#define CFG_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
+
+#define CFG_ATA_STRIDE 4 /* Interval between registers */
+
+/*
+ * Status LED
+ */
+#define CONFIG_STATUS_LED /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
+
+#define CFG_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
+#ifndef __ASSEMBLY__
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+ do { \
+ *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \
+ } while(0)
+
+#define __led_set(_msk, _st) \
+ do { \
+ if ((_st)) \
+ *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \
+ else \
+ *((volatile long *) (CFG_LED_BASE)) |= (_msk); \
+ } while(0)
+
+#define __led_init(_msk, st) \
+ do { \
+ *((volatile long *) (CFG_LED_BASE)) |= 0x34; \
+ } while(0)
+#endif /* __ASSEMBLY__ */
+
+#endif /* __CONFIG_H */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
+#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* needed for NetConsole */
+
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
+ CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-#define CONFIG_NETCONSOLE /* include NetConsole support */
-#define CONFIG_NET_MULTI /* needed for NetConsole */
-
/*-----------------------------------------------------------------------
* I2C stuff
*-----------------------------------------------------------------------
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
+ CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
+ CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
#ifndef __CONFIG_H
#define __CONFIG_H
-#define DEBUG
-#undef DEBUG
-
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
-#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */
-#define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */
-
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
+
+#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
+#define CFG_PCIE_MEMSIZE 0x01000000
+#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
-/* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */
-/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */
-/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */
+#define CFG_PCIE0_CFGBASE 0xc0000000
+#define CFG_PCIE0_XCFGBASE 0xc0000400
+#define CFG_PCIE1_CFGBASE 0xc0001000
+#define CFG_PCIE1_XCFGBASE 0xc0001400
+#define CFG_PCIE2_CFGBASE 0xc0002000
+#define CFG_PCIE2_XCFGBASE 0xc0002400
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* needed for NetConsole */
+
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
*/
/* Support for Intel 82557/82559/82559ER chips. */
#define CONFIG_EEPRO100
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
#define FPGA_REG1C_PE1_WAKE 0x0040
#define FPGA_REG1C_PE2_WAKE 0x0020
#define FPGA_REG1C_PE0_PERST 0x0010
-#define FPGA_REG1C_PE1_PERST 0x0080
-#define FPGA_REG1C_PE2_PERST 0x0040
+#define FPGA_REG1C_PE1_PERST 0x0008
+#define FPGA_REG1C_PE2_PERST 0x0004
/*----------------------------------------------------------------------------+
| Defines
# ifdef CFG_ENV_OFFSET_REDUND
# define CFG_REDUNDAND_ENVIRONMENT
# endif
+# if defined(CONFIG_NAND_U_BOOT)
+/* Use embedded environment in NAND boot versions */
+# define ENV_IS_EMBEDDED 1
+# endif
#endif /* CFG_ENV_IS_IN_NAND */
unsigned long get_timer(unsigned long);
void vprintf(const char *, va_list);
void do_reset (void);
+unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
+char *getenv (char *name);
+void setenv (char *varname, char *varvalue);
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
XF_MAX
};
-#define XF_VERSION 2
+#define XF_VERSION 3
#if defined(CONFIG_I386)
extern gd_t *global_data;
__u8 name11_12[4]; /* Last 2 characters in name */
} dir_slot;
-/* Private filesystem parameters */
+/* Private filesystem parameters
+ *
+ * Note: FAT buffer has to be 32 bit aligned
+ * (see FAT32 accesses)
+ */
typedef struct {
+ __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
int fatsize; /* Size of FAT in bits */
__u16 fatlength; /* Length of FAT in sectors */
__u16 fat_sect; /* Starting sector of the FAT */
__u16 rootdir_sect; /* Start sector of root directory */
__u16 clust_size; /* Size of clusters in sectors */
short data_begin; /* The sector of the first cluster, can be negative */
- __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
int fatbufnum; /* Used by get_fatent, init to -1 */
} fsdata;
ulong write_tout; /* maximum write timeout */
ulong buffer_write_tout; /* maximum buffer write timeout */
ushort vendor; /* the primary vendor id */
- ushort cmd_reset; /* Vendor specific reset command */
+ ushort cmd_reset; /* vendor specific reset command */
ushort interface; /* used for x8/x16 adjustments */
ushort legacy_unlock; /* support Intel legacy (un)locking */
+ uchar manufacturer_id; /* manufacturer id */
+ ushort device_id; /* device id */
+ ushort device_id2; /* extended device id */
+ ushort ext_addr; /* extended query table address */
+ ushort cfi_version; /* cfi version */
#endif
} flash_info_t;
#define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */
#define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */
#define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */
+#define AMD_ID_GL128N_2 0x22212221 /* 2nd ID word for S29GL128N */
+#define AMD_ID_GL128N_3 0x22012201 /* 3rd ID word for S29GL128N */
+
#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */
#define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */
#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */
#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */
#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */
+#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
#define FLASH_MAN_MT 0x00400000
#define FLASH_MAN_SHARP 0x00500000
#define FLASH_MAN_ATM 0x00600000
+#define FLASH_MAN_CFI 0x01000000
#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
struct ft_cxt {
struct boot_param_header *bph;
- int max_size; /* maximum size of tree */
- int overflow; /* set when this happens */
- u8 *p, *pstr, *pres; /* running pointers */
- u8 *p_begin, *pstr_begin, *pres_begin; /* starting pointers */
- u8 *p_anchor; /* start of constructed area */
- int struct_size, strings_size, res_size;
+ u8 *p_rsvmap;
+ u8 *p_start; /* pointer to beginning of dt_struct */
+ u8 *p_end; /* pointer to end of dt_strings */
+ u8 *p; /* pointer to end of dt_struct and beginning of dt_strings */
};
void ft_begin_node(struct ft_cxt *cxt, const char *name);
+void ft_init_cxt(struct ft_cxt *cxt, void *blob);
void ft_end_node(struct ft_cxt *cxt);
-void ft_begin_tree(struct ft_cxt *cxt);
-int ft_end_tree(struct ft_cxt *cxt);
+void ft_end_tree(struct ft_cxt *cxt);
+void ft_finalize_tree(struct ft_cxt *cxt);
void ft_nop(struct ft_cxt *cxt);
void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz);
void ft_begin(struct ft_cxt *cxt, void *blob, int max_size);
void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
-void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end);
+void ft_setup(void *blob, bd_t * bd, ulong initrd_start, ulong initrd_end);
void ft_dump_blob(const void *bphp);
void ft_merge_blob(struct ft_cxt *cxt, void *blob);
void *ft_get_prop(void *bphp, const char *propname, int *szp);
+#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup(void *blob, bd_t *bd);
+void ft_cpu_setup(void *blob, bd_t *bd);
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
#endif
#define IH_CPU_MICROBLAZE 14 /* MicroBlaze */
#define IH_CPU_NIOS2 15 /* Nios-II */
#define IH_CPU_BLACKFIN 16 /* Blackfin */
+#define IH_CPU_AVR32 17 /* AVR32 */
/*
* Image Types
#define IH_TYPE_FIRMWARE 5 /* Firmware Image */
#define IH_TYPE_SCRIPT 6 /* Script file */
#define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */
+#define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */
/*
* Compression Types
extern vidinfo_t panel_info;
-#endif /* CONFIG_MPC823 or CONFIG_PXA250 */
+#elif defined(CONFIG_MCC200)
+typedef struct vidinfo {
+ ushort vl_col; /* Number of columns (i.e. 160) */
+ ushort vl_row; /* Number of rows (i.e. 100) */
+
+ u_char vl_bpix; /* Bits per pixel, 0 = 1 */
+} vidinfo_t;
+#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 */
/* Video functions */
#define max_t(type,x,y) \
({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
+#ifndef BUG
#define BUG() do { \
printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \
} while (0)
#define BUG_ON(condition) do { if (condition) BUG(); } while(0)
+#endif /* BUG */
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
--- /dev/null
+/*
+ * linux/include/linux/mtd/ndfc.h
+ *
+ * Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Info:
+ * Contains defines, datastructures for ndfc nand controller
+ *
+ */
+#ifndef __LINUX_MTD_NDFC_H
+#define __LINUX_MTD_NDFC_H
+
+/* NDFC Register definitions */
+#define NDFC_CMD 0x00
+#define NDFC_ALE 0x04
+#define NDFC_DATA 0x08
+#define NDFC_ECC 0x10
+#define NDFC_BCFG0 0x30
+#define NDFC_BCFG1 0x34
+#define NDFC_BCFG2 0x38
+#define NDFC_BCFG3 0x3c
+#define NDFC_CCR 0x40
+#define NDFC_STAT 0x44
+#define NDFC_HWCTL 0x48
+#define NDFC_REVID 0x50
+
+#define NDFC_STAT_IS_READY 0x01000000
+
+#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */
+#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */
+#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */
+#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */
+#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */
+#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */
+#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */
+#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */
+#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
+#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
+#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
+#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
+#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */
+#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */
+#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */
+#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */
+
+#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */
+#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */
+#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */
+#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */
+#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */
+
+#define NDFC_MAX_BANKS 4
+
+struct ndfc_controller_settings {
+ uint32_t ccr_settings;
+ uint64_t ndfc_erpn;
+};
+
+struct ndfc_chip_settings {
+ uint32_t bank_settings;
+};
+
+#endif
#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
-#define MPC5XXX_WU_GPIO_DATA (MPC5XXX_WU_GPIO + 0x000c)
+#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c)
+#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020)
+
+/* GPIO pins */
+#define GPIO_WKUP_7 0x80000000UL
+#define GPIO_PSC6_0 0x10000000UL
+#define GPIO_PSC3_9 0x04000000UL
+#define GPIO_PSC1_4 0x01000000UL
/* PCI registers */
#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
+#define NR_IRQS 64
+
+/* IRQ mapping - these are our logical IRQ numbers */
+#define MPC5XXX_CRIT_IRQ_NUM 4
+#define MPC5XXX_MAIN_IRQ_NUM 17
+#define MPC5XXX_SDMA_IRQ_NUM 17
+#define MPC5XXX_PERP_IRQ_NUM 23
+
+#define MPC5XXX_CRIT_IRQ_BASE 1
+#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
+#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
+#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
+
+#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0)
+#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1)
+#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2)
+#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3)
+
+#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1)
+#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2)
+#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3)
+#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5)
+#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6)
+#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7)
+#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8)
+#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9)
+#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10)
+#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11)
+#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12)
+#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13)
+#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14)
+#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15)
+#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16)
+
+#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0)
+#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1)
+#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2)
+#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3)
+#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5)
+#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6)
+#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7)
+#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8)
+#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9)
+#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10)
+#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11)
+#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12)
+#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13)
+#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14)
+#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15)
+#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16)
+#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17)
+#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18)
+#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19)
+#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20)
+#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21)
+#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22)
+
/* General Purpose Timers registers */
#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
+#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C)
#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
+#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C)
#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
+#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C)
#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
+#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C)
#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
+#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C)
#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
+#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C)
#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
+#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C)
#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
+#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C)
+
+#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8)
#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78)
--- /dev/null
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ * Jeffrey Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ */
+
+#ifndef __MPC86xx_H__
+#define __MPC86xx_H__
+
+#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
+
+/*
+ * l2cr values. Look in config_<BOARD>.h for the actual setup
+ */
+#define l2cr 1017
+
+#define L2CR_L2E 0x80000000 /* bit 0 - enable */
+#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
+#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
+#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
+#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */
+#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */
+#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
+#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
+
+/*
+ * BAT settings. Look in config_<BOARD>.h for the actual setup
+ */
+
+#define BATU_BL_128K 0x00000000
+#define BATU_BL_256K 0x00000004
+#define BATU_BL_512K 0x0000000c
+#define BATU_BL_1M 0x0000001c
+#define BATU_BL_2M 0x0000003c
+#define BATU_BL_4M 0x0000007c
+#define BATU_BL_8M 0x000000fc
+#define BATU_BL_16M 0x000001fc
+#define BATU_BL_32M 0x000003fc
+#define BATU_BL_64M 0x000007fc
+#define BATU_BL_128M 0x00000ffc
+#define BATU_BL_256M 0x00001ffc
+#define BATU_BL_512M 0x00003ffc
+#define BATU_BL_1G 0x00007ffc
+#define BATU_BL_2G 0x0000fffc
+#define BATU_BL_4G 0x0001fffc
+
+#define BATU_VS 0x00000002
+#define BATU_VP 0x00000001
+#define BATU_INVALID 0x00000000
+
+#define BATL_WRITETHROUGH 0x00000040
+#define BATL_CACHEINHIBIT 0x00000020
+#define BATL_MEMCOHERENCE 0x00000010
+#define BATL_GUARDEDSTORAGE 0x00000008
+#define BATL_NO_ACCESS 0x00000000
+
+#define BATL_PP_MSK 0x00000003
+#define BATL_PP_00 0x00000000 /* No access */
+#define BATL_PP_01 0x00000001 /* Read-only */
+#define BATL_PP_10 0x00000002 /* Read-write */
+#define BATL_PP_11 0x00000003
+
+#define BATL_PP_NO_ACCESS BATL_PP_00
+#define BATL_PP_RO BATL_PP_01
+#define BATL_PP_RW BATL_PP_10
+
+#define HID0_XBSEN 0x00000100
+#define HID0_HIGH_BAT_EN 0x00800000
+#define HID0_XAEN 0x00020000
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+ unsigned long freqProcessor;
+ unsigned long freqSystemBus;
+} MPC86xx_SYS_INFO;
+
+#define l1icache_enable icache_enable
+
+void l2cache_enable(void);
+void l1dcache_enable(void);
+
+static __inline__ unsigned long get_hid0 (void)
+{
+ unsigned long hid0;
+ asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
+ return hid0;
+}
+
+static __inline__ unsigned long get_hid1 (void)
+{
+ unsigned long hid1;
+ asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
+ return hid1;
+}
+
+static __inline__ void set_hid0 (unsigned long hid0)
+{
+ asm volatile("mtspr 1008, %0" : : "r" (hid0));
+}
+
+static __inline__ void set_hid1 (unsigned long hid1)
+{
+ asm volatile("mtspr 1009, %0" : : "r" (hid1));
+}
+
+
+static __inline__ unsigned long get_l2cr (void)
+{
+ unsigned long l2cr_val;
+ asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
+ return l2cr_val;
+}
+
+#endif /* _ASMLANGUAGE */
+#endif /* __MPC86xx_H__ */
return info->erase(info, &instr);
}
+
+/*****************************************************************************
+ * declarations from nand_util.c
+ ****************************************************************************/
+
+struct nand_write_options {
+ u_char *buffer; /* memory block containing image to write */
+ ulong length; /* number of bytes to write */
+ ulong offset; /* start address in NAND */
+ int quiet; /* don't display progress messages */
+ int autoplace; /* if true use auto oob layout */
+ int forcejffs2; /* force jffs2 oob layout */
+ int forceyaffs; /* force yaffs oob layout */
+ int noecc; /* write without ecc */
+ int writeoob; /* image contains oob data */
+ int pad; /* pad to page size */
+ int blockalign; /* 1|2|4 set multiple of eraseblocks
+ * to align to */
+};
+
+typedef struct nand_write_options nand_write_options_t;
+
+struct nand_read_options {
+ u_char *buffer; /* memory block in which read image is written*/
+ ulong length; /* number of bytes to read */
+ ulong offset; /* start address in NAND */
+ int quiet; /* don't display progress messages */
+ int readoob; /* put oob data in image */
+};
+
+typedef struct nand_read_options nand_read_options_t;
+
+struct nand_erase_options {
+ ulong length; /* number of bytes to erase */
+ ulong offset; /* first address in NAND to erase */
+ int quiet; /* don't display progress messages */
+ int jffs2; /* if true: format for jffs2 usage
+ * (write appropriate cleanmarker blocks) */
+ int scrub; /* if true, really clean NAND by erasing
+ * bad blocks (UNSAFE) */
+};
+
+typedef struct nand_erase_options nand_erase_options_t;
+
+int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts);
+
+int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts);
+int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
+
+#define NAND_LOCK_STATUS_TIGHT 0x01
+#define NAND_LOCK_STATUS_LOCK 0x02
+#define NAND_LOCK_STATUS_UNLOCK 0x04
+
+int nand_lock( nand_info_t *meminfo, int tight );
+int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
+int nand_get_lock_status(nand_info_t *meminfo, ulong offset);
+
+#ifdef CFG_NAND_SELECT_DEVICE
+void board_nand_select_device(struct nand_chip *nand, int chip);
+#endif
+
#endif
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
#define PCI_AGP_SIZEOF 12
+/* PCI-X registers */
+
+#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
+#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
+#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
+#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
+#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
+
+
/* Slot Identification */
#define PCI_SID_ESR 2 /* Expansion Slot Register */
extern void pci_mpc824x_init (struct pci_controller *hose);
#endif
+#ifdef CONFIG_MPC85xx
+extern void pci_mpc85xx_init (struct pci_controller *hose);
+#endif
#endif /* _PCI_H */
#define PCI_DEVICE_ID_REALTEK_8139 0x8139
#define PCI_DEVICE_ID_REALTEK_8169 0x8169
+#define PCI_VENDOR_ID_DLINK 0x1186
+#define PCI_DEVICE_ID_DLINK_8139 0x1300
+
#define PCI_VENDOR_ID_XILINX 0x10ee
#define PCI_DEVICE_ID_TURBOPAM 0x4020
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
#define sdr_ecid1 0x0081
#define sdr_ecid2 0x0082
#define sdr_jtag 0x00c0
+#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
#define sdr_ddrdl 0x00e0
+#else
+#define sdr_cfg 0x00e0
+#define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/
+#define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */
+#define SDR_CFG_32BITS 0x00000000 /* 32 bits */
+#define SDR_CFG_64BITS 0x01000000 /* 64 bits */
+#define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
+#define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */
+#define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */
+#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
#define sdr_ebc 0x0100
#define sdr_uart0 0x0120 /* UART0 Config */
#define sdr_uart1 0x0121 /* UART1 Config */
#define sdr_plbtr 0x4200
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */
+#define DDR0_00 0x00
+#define DDR0_01 0x01
+#define DDR0_02 0x02
+#define DDR0_03 0x03
+#define DDR0_04 0x04
+#define DDR0_05 0x05
+#define DDR0_06 0x06
+#define DDR0_07 0x07
+#define DDR0_08 0x08
+#define DDR0_09 0x09
+#define DDR0_10 0x0A
+#define DDR0_11 0x0B
+#define DDR0_12 0x0C
+#define DDR0_13 0x0D
+#define DDR0_14 0x0E
+#define DDR0_15 0x0F
+#define DDR0_16 0x10
+#define DDR0_17 0x11
+#define DDR0_18 0x12
+#define DDR0_19 0x13
+#define DDR0_20 0x14
+#define DDR0_21 0x15
+#define DDR0_22 0x16
+#define DDR0_23 0x17
+#define DDR0_24 0x18
+#define DDR0_25 0x19
+#define DDR0_26 0x1A
+#define DDR0_27 0x1B
+#define DDR0_28 0x1C
+#define DDR0_29 0x1D
+#define DDR0_30 0x1E
+#define DDR0_31 0x1F
+#define DDR0_32 0x20
+#define DDR0_33 0x21
+#define DDR0_34 0x22
+#define DDR0_35 0x23
+#define DDR0_36 0x24
+#define DDR0_37 0x25
+#define DDR0_38 0x26
+#define DDR0_39 0x27
+#define DDR0_40 0x28
+#define DDR0_41 0x29
+#define DDR0_42 0x2A
+#define DDR0_43 0x2B
+#define DDR0_44 0x2C
+#endif /*CONFIG_440EPX*/
+
/*-----------------------------------------------------------------------------
| SDRAM Controller
+----------------------------------------------------------------------------*/
#define xbcfg 0x23 /* external bus configuration reg */
#define xbcid 0x24 /* external bus core id reg */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* PLB4 to PLB3 Bridge OUT */
#define P4P3_DCR_BASE 0x020
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
/* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR 0x4300
+#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
+#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
+#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
+#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
+#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
+#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
+#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
+#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
+#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
+#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
+#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
+#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
+
+#define SDR0_MFR_ERRATA3_EN0 0x00800000
+#define SDR0_MFR_ERRATA3_EN1 0x00400000
+#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
+#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
+#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
+#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
+
+#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR_USB2D0CR 0x0320
+#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
+#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
+#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
+
+#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
+#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
+#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
+
+#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
+#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
+#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
+
+/* USB2 Host Control Register */
+#define SDR0_USB2H0CR 0x0340
+#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
+#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
+#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
+#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
+
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1 0x4101
+#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
+#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
+#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
+
+#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
+#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
+#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
+#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
+#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
+#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
+#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
+#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
+
+#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
+#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
+#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
+#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
+#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
+#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
+#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
+#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
+#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
+#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
+#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
+#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
+#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
+#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
+#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
+#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
+#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
+#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
+#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
+#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
+#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
+
+#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
+#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
+#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
+
+/* Ethernet PLL Configuration Register */
+#define SDR0_PFC2 0x4102
+#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
+#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
+#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
+#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
+
+#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
+#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
+#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
+
+/* USB2PHY0 Control Register */
+#define SDR0_USB2PHY0CR 0x4103
+#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
+#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
+#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
+
+#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
+#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
+#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
+
+#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
+#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
+#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
+
+#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
+#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
+#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
+
+#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
+#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
+#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
+
+#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
+#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
+#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
+
+#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
+#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
+#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
+
+#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
+#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
+#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
+
+#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
+#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
+#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
+
+#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
+#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
+#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
+#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
+
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR 0x4300
+#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
+#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
+#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
+#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
+#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
+#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
+#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
+#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
+#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
+#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
+
+#define SDR0_MFR_ERRATA3_EN0 0x00800000
+#define SDR0_MFR_ERRATA3_EN1 0x00400000
+#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
+#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
+#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
+#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
+
+#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
+
/* CUST0 Customer Configuration Register0 */
#define SDR0_CUST0 0x4000
#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
-/* Miscealleneaous Function Reg. */
-#define SDR0_MFR 0x4300
-#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
-#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
-#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
-#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
-#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
-#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
-#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
-#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
-#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
-#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
-#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
-
-#define SDR0_MFR_ERRATA3_EN0 0x00800000
-#define SDR0_MFR_ERRATA3_EN1 0x00400000
-#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
-#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
-#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
-#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
-#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
+/*-----------------------------------------------------------------------------
+ | Internal SRAM
+ +----------------------------------------------------------------------------*/
+#define ISRAM0_DCR_BASE 0x380
+#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
+#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
+#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
+#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
+#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
+#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
+#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
+#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
#else
#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UIC2_DCR_BASE 0xe0
#define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */
#define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */
#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
#if defined(CONFIG_440GX)
-#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */
-#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */
+#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
+#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
#endif /* CONFIG_440GX */
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
#define UIC_EIR6 0x00000004 /* External interrupt 6 */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UIC_U0 0x80000000 /* UART 0 */
+#define UIC_U1 0x40000000 /* UART 1 */
+#define UIC_IIC0 0x20000000 /* IIC */
+#define UIC_KRD 0x10000000 /* Kasumi Ready for data */
+#define UIC_KDA 0x08000000 /* Kasumi Data Available */
+#define UIC_PCRW 0x04000000 /* PCI command register write */
+#define UIC_PPM 0x02000000 /* PCI power management */
+#define UIC_IIC1 0x01000000 /* IIC */
+#define UIC_SPI 0x00800000 /* SPI */
+#define UIC_EPCISER 0x00400000 /* External PCI SERR */
+#define UIC_MTE 0x00200000 /* MAL TXEOB */
+#define UIC_MRE 0x00100000 /* MAL RXEOB */
+#define UIC_D0 0x00080000 /* DMA channel 0 */
+#define UIC_D1 0x00040000 /* DMA channel 1 */
+#define UIC_D2 0x00020000 /* DMA channel 2 */
+#define UIC_D3 0x00010000 /* DMA channel 3 */
+#define UIC_UD0 0x00008000 /* UDMA irq 0 */
+#define UIC_UD1 0x00004000 /* UDMA irq 1 */
+#define UIC_UD2 0x00002000 /* UDMA irq 2 */
+#define UIC_UD3 0x00001000 /* UDMA irq 3 */
+#define UIC_HSB2D 0x00000800 /* USB2.0 Device */
+#define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */
+#define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */
+#define UIC_EIP94 0x00000100 /* Security EIP94 */
+#define UIC_ETH0 0x00000080 /* Emac 0 */
+#define UIC_ETH1 0x00000040 /* Emac 1 */
+#define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */
+#define UIC_EIR4 0x00000010 /* External interrupt 4 */
+#define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */
+#define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */
+#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
+#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_TXEOB UIC_MTE
+#define UIC_MAL_RXEOB UIC_MRE
+
#elif !defined(CONFIG_440SPE)
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* Ethernet 1 */
#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UIC_MS 0x80000000 /* MAL SERR */
+#define UIC_MTDE 0x40000000 /* MAL TXDE */
+#define UIC_MRDE 0x20000000 /* MAL RXDE */
+#define UIC_U2 0x10000000 /* UART 2 */
+#define UIC_U3 0x08000000 /* UART 3 */
+#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
+#define UIC_NDFC 0x02000000 /* NDFC */
+#define UIC_KSLE 0x01000000 /* KASUMI slave error */
+#define UIC_CT5 0x00800000 /* GPT compare timer 5 */
+#define UIC_CT6 0x00400000 /* GPT compare timer 6 */
+#define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */
+#define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */
+#define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */
+#define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */
+#define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */
+#define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */
+#define UIC_CT0 0x00008000 /* GPT compare timer 0 */
+#define UIC_CT1 0x00004000 /* GPT compare timer 1 */
+#define UIC_EIR7 0x00002000 /* External interrupt 7 */
+#define UIC_EIR8 0x00001000 /* External interrupt 8 */
+#define UIC_EIR9 0x00000800 /* External interrupt 9 */
+#define UIC_CT2 0x00000400 /* GPT compare timer 2 */
+#define UIC_CT3 0x00000200 /* GPT compare timer 3 */
+#define UIC_CT4 0x00000100 /* GPT compare timer 4 */
+#define UIC_SRE 0x00000080 /* Serial ROM error */
+#define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */
+#define UIC_RSVD0 0x00000020 /* Reserved */
+#define UIC_EPCIPER 0x00000010 /* External PCI PERR */
+#define UIC_EIR0 0x00000008 /* External interrupt 0 */
+#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
+#define UIC_EIR1 0x00000002 /* External interrupt 1 */
+#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_SERR UIC_MS
+#define UIC_MAL_TXDE UIC_MTDE
+#define UIC_MAL_RXDE UIC_MRDE
+#define UIC_ENET UIC_ETH0
+
#elif !defined(CONFIG_440SPE)
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_RSVD29 0x00000004 /* Reserved */
#define UIC_RSVD30 0x00000002 /* Reserved */
#define UIC_RSVD31 0x00000001 /* Reserved */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
+
+#define UIC_EIR5 0x80000000 /* External interrupt 5 */
+#define UIC_EIR6 0x40000000 /* External interrupt 6 */
+#define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */
+#define UIC_EIR2 0x10000000 /* External interrupt 2 */
+#define UIC_EIR3 0x08000000 /* External interrupt 3 */
+#define UIC_DDR2 0x04000000 /* DDR2 sdram */
+#define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */
+#define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */
+#define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */
+#define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */
+
#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UICB0_UIC1CI 0x00000000 /* UIC1 Critical Interrupt */
+#define UICB0_UIC1NCI 0x00000000 /* UIC1 Noncritical Interrupt */
+#define UICB0_UIC2CI 0x00000000 /* UIC2 Critical Interrupt */
+#define UICB0_UIC2NCI 0x00000000 /* UIC2 Noncritical Interrupt */
+
+#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
+ UICB0_UIC1CI | UICB0_UIC2NCI)
+
#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
| Universal interrupt controller interrupts
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
#define SDR0_MFR_ERRATA3_EN0 0x00800000
#define SDR0_MFR_ERRATA3_EN1 0x00400000
+#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
+#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
+#define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29)
+#define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07)
+#endif
+
+#define SDR0_MFR_ECS_MASK 0x10000000
+#define SDR0_MFR_ECS_INTERNAL 0x10000000
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_SRST0 0x200
+#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
+#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
+#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
+#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
+#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
+#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
+#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
+#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
+#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
+#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
+#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
+#define SDR0_SRST0_PCI 0x00100000 /* PCI */
+#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
+#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
+#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
+#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
+#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
+#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
+#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
+#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
+#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
+#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
+#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
+#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
+#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
+#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
+#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
+#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
+#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
+#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
+#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
+
+#define SDR0_SRST1 0x201
+#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
+#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
+#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
+#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
+#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
+#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
+#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
+#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
+#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
+#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
+#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
+#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
+#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
+#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
+#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
+#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
+#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
+#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
+#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
+#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
+
+#else
#define SDR0_SRST_BGO 0x80000000
#define SDR0_SRST_PLB 0x40000000
#define SDR0_SRST_EMAC3 0x00000008
#define SDR0_SRST_RGMII 0x00000001
+#endif
+
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
-#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
+#if !defined (CONFIG_440GX) && \
+ !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
+ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
+ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
#endif /* CONFIG_440GX */
+#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
+/*--------------------------------------*/
+#define CPR0_PLLC 0x40
+#define CPR0_PLLC_RST_MASK 0x80000000
+#define CPR0_PLLC_RST_PLLLOCKED 0x00000000
+#define CPR0_PLLC_RST_PLLRESET 0x80000000
+#define CPR0_PLLC_ENG_MASK 0x40000000
+#define CPR0_PLLC_ENG_DISABLE 0x00000000
+#define CPR0_PLLC_ENG_ENABLE 0x40000000
+#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
+#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
+#define CPR0_PLLC_SRC_MASK 0x20000000
+#define CPR0_PLLC_SRC_PLLOUTA 0x00000000
+#define CPR0_PLLC_SRC_PLLOUTB 0x20000000
+#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
+#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
+#define CPR0_PLLC_SEL_MASK 0x07000000
+#define CPR0_PLLC_SEL_PLL 0x00000000
+#define CPR0_PLLC_SEL_CPU 0x01000000
+#define CPR0_PLLC_SEL_PER 0x05000000
+#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
+#define CPR0_PLLC_TUNE_MASK 0x000003FF
+#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+/*--------------------------------------*/
+#define CPR0_PLLD 0x60
+#define CPR0_PLLD_FBDV_MASK 0x1F000000
+#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
+#define CPR0_PLLD_FWDVA_MASK 0x000F0000
+#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
+#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
+#define CPR0_PLLD_FWDVB_MASK 0x00000700
+#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
+#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
+#define CPR0_PLLD_LFBDV_MASK 0x0000003F
+#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
+#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
+/*--------------------------------------*/
+#define CPR0_PRIMAD 0x80
+#define CPR0_PRIMAD_PRADV0_MASK 0x07000000
+#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#define CPR0_PRIMBD 0xA0
+#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
+#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#if 0
+#define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */
+#define CPR0_CPM0_FR 0xB1 /* CPM Force Register */
+#define CPR0_CPM0_SR 0xB2 /* CPM Status Register */
+#define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */
+#define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */
+#define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */
+#define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */
+#define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */
+#define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */
+#define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */
+#define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */
+#define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */
+#define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */
+#define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */
+#define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
+#define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
+#define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */
+#define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */
+#define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */
+#define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */
+#define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */
+#define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */
+#define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */
+#define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */
+#define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */
+#define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */
+#define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */
+#define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */
+#define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */
+#define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */
+#define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */
+#define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */
+#define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */
+#define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */
+#endif
+/*--------------------------------------*/
+#define CPR0_OPBD 0xC0
+#define CPR0_OPBD_OPBDV0_MASK 0x03000000
+#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_PERD 0xE0
+#define CPR0_PERD_PERDV0_MASK 0x07000000
+#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#define CPR0_MALD 0x100
+#define CPR0_MALD_MALDV0_MASK 0x03000000
+#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_SPCID 0x120
+#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
+#define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+#define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_ICFG 0x140
+#define CPR0_ICFG_RLI_MASK 0x80000000
+#define CPR0_ICFG_RLI_RESETCPR 0x00000000
+#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
+#define CPR0_ICFG_ICS_MASK 0x00000007
+#endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */
+
/*-----------------------------------------------------------------------------
| IIC Register Offsets
'----------------------------------------------------------------------------*/
#define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
#define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* PCI Local Configuration Registers
--------------------------------- */
#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+/* USB2.0 Device */
+#define USB2D0_BASE CFG_USB2D0_BASE
+
+#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
+
+#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
+#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
+#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
+#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
+#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
+#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
+#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
+#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
+#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
+#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
+#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
+#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
+#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
+#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
+#endif
+
/******************************************************************************
* GPIO macro register defines
******************************************************************************/
#define GPIO0_IR (GPIO0_BASE+0x1C)
#endif /* CONFIG_440GP */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
#define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
#define EMAC_STACR_OC_MASK (0x00000000)
#endif
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_PFC1_EM_1000 (0x00200000)
#endif
/*ZMII Bridge Register addresses */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
#else
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
#define ZMII_MDI0 0x80000000
/* ZMII FER Register Bit Definitions */
+#define ZMII_FER_DIS (0x0)
#define ZMII_FER_MDI (0x8)
#define ZMII_FER_SMII (0x4)
#define ZMII_FER_RMII (0x2)
#define ZMII_SMIISR_V(__x) ((3 - __x) * 8)
/* RGMII Register Addresses */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000)
+#else
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790)
+#endif
#define RGMII_FER (RGMII_BASE + 0x00)
#define RGMII_SSR (RGMII_BASE + 0x04)
#define RGMII_SSR_SP_100MBPS (0x02)
#define RGMII_SSR_SP_1000MBPS (0x04)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define RGMII_SSR_V(__x) ((__x) * 8)
+#else
#define RGMII_SSR_V(__x) ((__x -2) * 8)
+#endif
/*---------------------------------------------------------------------------+
/* Ethernet MAC Regsiter Addresses */
#if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
#else
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
#define EMAC_M0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
lwz r3,GOT(transfer_to_handler); \
mtlr r3; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
- li r20,MSR_KERNEL; \
+ li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
rlwimi r20,r23,0,25,25; \
blrl ; \
.L_ ## label : \
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
+#if defined(CFG_NS16550_SERIAL)
+extern struct serial_device eserial1_device;
+extern struct serial_device eserial2_device;
+extern struct serial_device eserial3_device;
+extern struct serial_device eserial4_device;
+#endif /* CFG_NS16550_SERIAL */
+
#endif
#elif defined(CONFIG_NIOS2)
/* XXX empty just to avoid the error */
/************************************************************************/
+#elif defined(CONFIG_V38B)
+
+# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
+# define STATUS_LED_PERIOD (CFG_HZ / 2)
+# define STATUS_LED_STATE STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
+# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
#else
# error Status LED configuration missing
#endif
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).a
-AOBJS = _ashldi3.o _ashrdi3.o _divsi3.o _modsi3.o _udivsi3.o _umodsi3.o
+SOBJS = _ashldi3.o _ashrdi3.o _divsi3.o _modsi3.o _udivsi3.o _umodsi3.o
COBJS = armlinux.o board.o \
cache.o div0.o
-OBJS = $(AOBJS) $(COBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(ARCH).a
+
+SOBJS = memset.o
+
+COBJS = board.o interrupts.o avr32_linux.o div64.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <zlib.h>
+#include <asm/byteorder.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/arch/platform.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* CPU-specific hook to allow flushing of caches, etc. */
+extern void prepare_to_boot(void);
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+extern image_header_t header; /* from cmd_bootm.c */
+
+static struct tag *setup_start_tag(struct tag *params)
+{
+ params->hdr.tag = ATAG_CORE;
+ params->hdr.size = tag_size(tag_core);
+
+ params->u.core.flags = 0;
+ params->u.core.pagesize = 4096;
+ params->u.core.rootdev = 0;
+
+ return tag_next(params);
+}
+
+static struct tag *setup_memory_tags(struct tag *params)
+{
+ bd_t *bd = gd->bd;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ params->hdr.tag = ATAG_MEM;
+ params->hdr.size = tag_size(tag_mem_range);
+
+ params->u.mem_range.addr = bd->bi_dram[i].start;
+ params->u.mem_range.size = bd->bi_dram[i].size;
+
+ params = tag_next(params);
+ }
+
+ return params;
+}
+
+static struct tag *setup_commandline_tag(struct tag *params, char *cmdline)
+{
+ if (!cmdline)
+ return params;
+
+ /* eat leading white space */
+ while (*cmdline == ' ') cmdline++;
+
+ /*
+ * Don't include tags for empty command lines; let the kernel
+ * use its default command line.
+ */
+ if (*cmdline == '\0')
+ return params;
+
+ params->hdr.tag = ATAG_CMDLINE;
+ params->hdr.size =
+ (sizeof (struct tag_header) + strlen(cmdline) + 1 + 3) >> 2;
+ strcpy(params->u.cmdline.cmdline, cmdline);
+
+ return tag_next(params);
+}
+
+static struct tag *setup_ramdisk_tag(struct tag *params,
+ unsigned long rd_start,
+ unsigned long rd_end)
+{
+ if (rd_start == rd_end)
+ return params;
+
+ params->hdr.tag = ATAG_RDIMG;
+ params->hdr.size = tag_size(tag_mem_range);
+
+ params->u.mem_range.addr = rd_start;
+ params->u.mem_range.size = rd_end - rd_start;
+
+ return tag_next(params);
+}
+
+static struct tag *setup_clock_tags(struct tag *params)
+{
+ params->hdr.tag = ATAG_CLOCK;
+ params->hdr.size = tag_size(tag_clock);
+ params->u.clock.clock_id = ACLOCK_BOOTCPU;
+ params->u.clock.clock_flags = 0;
+ params->u.clock.clock_hz = gd->cpu_hz;
+
+#ifdef CONFIG_AT32AP7000
+ /*
+ * New kernels don't need this, but we should be backwards
+ * compatible for a while...
+ */
+ params = tag_next(params);
+
+ params->hdr.tag = ATAG_CLOCK;
+ params->hdr.size = tag_size(tag_clock);
+ params->u.clock.clock_id = ACLOCK_HSB;
+ params->u.clock.clock_flags = 0;
+ params->u.clock.clock_hz = pm_get_clock_freq(CLOCK_HSB);
+#endif
+
+ return tag_next(params);
+}
+
+static struct tag *setup_ethernet_tag(struct tag *params,
+ char *addr, int index)
+{
+ char *s, *e;
+ int i;
+
+ params->hdr.tag = ATAG_ETHERNET;
+ params->hdr.size = tag_size(tag_ethernet);
+
+ params->u.ethernet.mac_index = index;
+ params->u.ethernet.mii_phy_addr = gd->bd->bi_phy_id[index];
+
+ s = addr;
+ for (i = 0; i < 6; i++) {
+ params->u.ethernet.hw_address[i] = simple_strtoul(s, &e, 16);
+ s = e + 1;
+ }
+
+ return tag_next(params);
+}
+
+static struct tag *setup_ethernet_tags(struct tag *params)
+{
+ char name[16] = "ethaddr";
+ char *addr;
+ int i = 0;
+
+ do {
+ addr = getenv(name);
+ if (addr)
+ params = setup_ethernet_tag(params, addr, i);
+ sprintf(name, "eth%daddr", ++i);
+ } while (i < 4);
+
+ return params;
+}
+
+static void setup_end_tag(struct tag *params)
+{
+ params->hdr.tag = ATAG_NONE;
+ params->hdr.size = 0;
+}
+
+void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
+ unsigned long addr, unsigned long *len_ptr, int verify)
+{
+ unsigned long data, len = 0;
+ unsigned long initrd_start, initrd_end;
+ unsigned long image_start, image_end;
+ unsigned long checksum;
+ void (*theKernel)(int magic, void *tagtable);
+ image_header_t *hdr;
+ struct tag *params, *params_start;
+ char *commandline = getenv("bootargs");
+
+ hdr = (image_header_t *)addr;
+ image_start = addr;
+ image_end = addr + hdr->ih_size;
+
+ theKernel = (void *)ntohl(hdr->ih_ep);
+
+ /*
+ * Check if there is an initrd image
+ */
+ if (argc >= 3) {
+ SHOW_BOOT_PROGRESS(9);
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+
+ printf("## Loading RAMDISK image at %08lx ...\n", addr);
+
+ memcpy(&header, (char *)addr, sizeof(header));
+ hdr = &header;
+
+ if (ntohl(hdr->ih_magic) != IH_MAGIC) {
+ puts("Bad Magic Number\n");
+ SHOW_BOOT_PROGRESS(-10);
+ do_reset(cmdtp, flag, argc, argv);
+ }
+
+ data = (unsigned long)hdr;
+ len = sizeof(*hdr);
+ checksum = ntohl(hdr->ih_hcrc);
+ hdr->ih_hcrc = 0;
+
+ if (crc32(0, (unsigned char *)data, len) != checksum) {
+ puts("Bad Header Checksum\n");
+ SHOW_BOOT_PROGRESS(-11);
+ do_reset(cmdtp, flag, argc, argv);
+ }
+
+ SHOW_BOOT_PROGRESS(10);
+
+ print_image_hdr(hdr);
+
+ data = addr + sizeof(header);
+ len = ntohl(hdr->ih_size);
+
+ if (verify) {
+ unsigned long csum = 0;
+
+ puts(" Verifying Checksum ... ");
+ csum = crc32(0, (unsigned char *)data, len);
+ if (csum != ntohl(hdr->ih_dcrc)) {
+ puts("Bad Data CRC\n");
+ SHOW_BOOT_PROGRESS(-12);
+ do_reset(cmdtp, flag, argc, argv);
+ }
+ puts("OK\n");
+ }
+
+ SHOW_BOOT_PROGRESS(11);
+
+ if ((hdr->ih_os != IH_OS_LINUX) ||
+ (hdr->ih_arch != IH_CPU_AVR32) ||
+ (hdr->ih_type != IH_TYPE_RAMDISK)) {
+ puts("Not a Linux/AVR32 RAMDISK image\n");
+ SHOW_BOOT_PROGRESS(-13);
+ do_reset(cmdtp, flag, argc, argv);
+ }
+ } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) {
+ ulong tail = ntohl (len_ptr[0]) % 4;
+ int i;
+
+ SHOW_BOOT_PROGRESS (13);
+
+ /* skip kernel length and terminator */
+ data = (ulong) (&len_ptr[2]);
+ /* skip any additional image length fields */
+ for (i = 1; len_ptr[i]; ++i)
+ data += 4;
+ /* add kernel length, and align */
+ data += ntohl (len_ptr[0]);
+ if (tail) {
+ data += 4 - tail;
+ }
+
+ len = ntohl (len_ptr[1]);
+ } else {
+ /* no initrd image */
+ SHOW_BOOT_PROGRESS(14);
+ len = data = 0;
+ }
+
+ if (data) {
+ initrd_start = data;
+ initrd_end = initrd_start + len;
+ } else {
+ initrd_start = 0;
+ initrd_end = 0;
+ }
+
+ SHOW_BOOT_PROGRESS(15);
+
+ params = params_start = (struct tag *)gd->bd->bi_boot_params;
+ params = setup_start_tag(params);
+ params = setup_memory_tags(params);
+ if (initrd_start) {
+ params = setup_ramdisk_tag(params,
+ PHYSADDR(initrd_start),
+ PHYSADDR(initrd_end));
+ }
+ params = setup_commandline_tag(params, commandline);
+ params = setup_clock_tags(params);
+ params = setup_ethernet_tags(params);
+ setup_end_tag(params);
+
+ printf("\nStarting kernel at %p (params at %p)...\n\n",
+ theKernel, params_start);
+
+ prepare_to_boot();
+
+ theKernel(ATAG_MAGIC, params_start);
+}
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <devices.h>
+#include <version.h>
+#include <net.h>
+
+#include <asm/initcalls.h>
+#include <asm/sections.h>
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const char version_string[] =
+ U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ") " CONFIG_IDENT_STRING;
+
+unsigned long monitor_flash_len;
+
+/*
+ * Begin and end of memory area for malloc(), and current "brk"
+ */
+static unsigned long mem_malloc_start = 0;
+static unsigned long mem_malloc_end = 0;
+static unsigned long mem_malloc_brk = 0;
+
+/* The malloc area is wherever the board wants it to be */
+static void mem_malloc_init(void)
+{
+ mem_malloc_start = CFG_MALLOC_START;
+ mem_malloc_end = CFG_MALLOC_END;
+ mem_malloc_brk = mem_malloc_start;
+
+ printf("malloc: Using memory from 0x%08lx to 0x%08lx\n",
+ mem_malloc_start, mem_malloc_end);
+
+ memset ((void *)mem_malloc_start, 0,
+ mem_malloc_end - mem_malloc_start);
+}
+
+void *sbrk(ptrdiff_t increment)
+{
+ unsigned long old = mem_malloc_brk;
+ unsigned long new = old + increment;
+
+ if ((new < mem_malloc_start) || (new > mem_malloc_end))
+ return NULL;
+
+ mem_malloc_brk = new;
+ return ((void *)old);
+}
+
+static int init_baudrate(void)
+{
+ char tmp[64];
+ int i;
+
+ i = getenv_r("baudrate", tmp, sizeof(tmp));
+ if (i > 0) {
+ gd->baudrate = simple_strtoul(tmp, NULL, 10);
+ } else {
+ gd->baudrate = CONFIG_BAUDRATE;
+ }
+ return 0;
+}
+
+
+static int display_banner (void)
+{
+ printf ("\n\n%s\n\n", version_string);
+ printf ("U-Boot code: %p -> %p data: %p -> %p\n",
+ _text, _etext, _data, _end);
+ return 0;
+}
+
+void hang(void)
+{
+ for (;;) ;
+}
+
+static int display_dram_config (void)
+{
+ int i;
+
+ puts ("DRAM Configuration:\n");
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+ print_size (gd->bd->bi_dram[i].size, "\n");
+ }
+
+ return 0;
+}
+
+static void display_flash_config (void)
+{
+ puts ("Flash: ");
+ print_size(gd->bd->bi_flashsize, " ");
+ printf("at address 0x%08lx\n", gd->bd->bi_flashstart);
+}
+
+void start_u_boot (void)
+{
+ gd_t gd_data;
+
+ /* Initialize the global data pointer */
+ memset(&gd_data, 0, sizeof(gd_data));
+ gd = &gd_data;
+
+ monitor_flash_len = _edata - _text;
+
+ /* Perform initialization sequence */
+ cpu_init();
+ timer_init();
+ env_init();
+ init_baudrate();
+ serial_init();
+ console_init_f();
+ display_banner();
+
+ board_init_memories();
+ mem_malloc_init();
+
+ gd->bd = malloc(sizeof(bd_t));
+ memset(gd->bd, 0, sizeof(bd_t));
+ gd->bd->bi_baudrate = gd->baudrate;
+ gd->bd->bi_dram[0].start = CFG_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->sdram_size;
+
+ board_init_info();
+ flash_init();
+
+ if (gd->bd->bi_flashsize)
+ display_flash_config();
+ if (gd->bd->bi_dram[0].size)
+ display_dram_config();
+
+ gd->bd->bi_boot_params = malloc(CFG_BOOTPARAMS_LEN);
+ if (!gd->bd->bi_boot_params)
+ puts("WARNING: Cannot allocate space for boot parameters\n");
+
+ /* initialize environment */
+ env_relocate();
+
+ devices_init();
+ jumptable_init();
+ console_init_r();
+
+ for (;;) {
+ main_loop();
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ *
+ * Based on former do_div() implementation from asm-parisc/div64.h:
+ * Copyright (C) 1999 Hewlett-Packard Co
+ * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ *
+ * Generic C version of 64bit/32bit division and modulo, with
+ * 64bit result and 32bit remainder.
+ *
+ * The fast case for (n>>32 == 0) is handled inline by do_div().
+ *
+ * Code generated for this function might be very inefficient
+ * for some CPUs. __div64_32() can be overridden by linking arch-specific
+ * assembly versions such as arch/ppc/lib/div64.S and arch/sh/lib/div64.S.
+ */
+
+#include <linux/types.h>
+
+#include <asm/div64.h>
+
+uint32_t __div64_32(uint64_t *n, uint32_t base)
+{
+ uint64_t rem = *n;
+ uint64_t b = base;
+ uint64_t res, d = 1;
+ uint32_t high = rem >> 32;
+
+ /* Reduce the thing a bit first */
+ res = 0;
+ if (high >= base) {
+ high /= base;
+ res = (uint64_t) high << 32;
+ rem -= (uint64_t) (high*base) << 32;
+ }
+
+ while ((int64_t)b > 0 && b < rem) {
+ b = b+b;
+ d = d+d;
+ }
+
+ do {
+ if (rem >= b) {
+ rem -= b;
+ res += d;
+ }
+ b >>= 1;
+ d >>= 1;
+ } while (d);
+
+ *n = res;
+ return rem;
+}
--- /dev/null
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/sysreg.h>
+
+void enable_interrupts(void)
+{
+ asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET));
+}
+
+int disable_interrupts(void)
+{
+ unsigned long sr;
+
+ sr = sysreg_read(SR);
+ asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET));
+
+ return SYSREG_BFEXT(GM, sr);
+}
--- /dev/null
+/*
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ /*
+ * r12: void *b
+ * r11: int c
+ * r10: size_t len
+ *
+ * Returns b in r12
+ */
+ .text
+
+ .global memset
+ .type memset, @function
+ .align 2
+memset:
+ mov r9, r12
+ mov r8, r12
+ or r11, r11, r11 << 8
+ andl r9, 3, COH
+ brne 1f
+
+2: or r11, r11, r11 << 16
+ sub r10, 4
+ brlt 5f
+
+ /* Let's do some real work */
+4: st.w r8++, r11
+ sub r10, 4
+ brge 4b
+
+ /*
+ * When we get here, we've got less than 4 bytes to set. r10
+ * might be negative.
+ */
+5: sub r10, -4
+ reteq r12
+
+ /* Fastpath ends here, exactly 32 bytes from memset */
+
+ /* Handle unaligned count or pointer */
+ bld r10, 1
+ brcc 6f
+ st.b r8++, r11
+ st.b r8++, r11
+ bld r10, 0
+ retcc r12
+6: st.b r8++, r11
+ mov pc, lr
+
+ /* Handle unaligned pointer */
+1: sub r10, 4
+ brlt 5b
+ add r10, r9
+ lsl r9, 1
+ add pc, r9
+ st.b r8++, r11
+ st.b r8++, r11
+ st.b r8++, r11
+ rjmp 2b
+
+ .size memset, . - memset
#
# Copyright (c) 2005 blackfin.uclinux.org
#
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).a
-AOBJS =
+SOBJS =
COBJS = board.o bf533_linux.o bf533_string.o cache.o muldi3.o
-OBJS = $(AOBJS) $(COBJS)
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000-2002
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = libgeneric.a
+LIB = $(obj)libgeneric.a
-OBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \
+COBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \
bzlib_randtable.o bzlib_huffman.o \
crc32.o ctype.o display_options.o ldiv.o \
string.o vsprintf.o zlib.o
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
return crc ^ 0xffffffffL;
}
-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) || \
+ ((CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY))
/* No ones complement version. JFFS2 (and other things ?)
* don't use ones compliment in their CRC calculations.
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).a
-AOBJS = bios.o bios_pci.o realmode_switch.o
+SOBJS = bios.o bios_pci.o realmode_switch.o
COBJS = board.o bios_setup.o i386_linux.o zimage.o realmode.o \
pci_type1.o pci.o video_bios.o video.o
-OBJS = $(AOBJS) $(COBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).a
+
+SOBJS =
-AOBJS =
COBJS = cache.o traps.o time.o board.o m68k_linux.o
-OBJS = $(AOBJS) $(COBJS)
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).a
-AOBJS =
+SOBJS =
COBJS = board.o microblaze_linux.o time.o cache.o
-OBJS = $(AOBJS) $(COBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2003
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).a
-AOBJS =
+SOBJS =
COBJS = board.o time.o mips_linux.o
-OBJS = $(AOBJS) $(COBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).a
-AOBJS =
+SOBJS =
COBJS = board.o cache.o divmod.o nios_linux.o mult.o time.o
-OBJS = $(AOBJS) $(COBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).a
-AOBJS = cache.o
+SOBJS = cache.o
COBJS = board.o divmod.o nios_linux.o mult.o time.o
-OBJS = $(AOBJS) $(COBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = lib$(ARCH).a
+LIB = $(obj)lib$(ARCH).a
-AOBJS = ppcstring.o ticks.o
+SOBJS = ppcstring.o ticks.o
COBJS = board.o \
bat_rw.o cache.o extable.o kgdb.o time.o interrupts.o
-OBJS = $(AOBJS) $(COBJS)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#endif
#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
- defined(CONFIG_E500)
+ defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5xxx)
spi_init_r ();
#endif
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+ WATCHDOG_RESET ();
+ puts ("NAND: ");
+ nand_init(); /* go init the NAND */
+#endif
+
/* relocate environment function pointers etc. */
env_relocate ();
#endif /* CFG_EXTBDINFO */
s = getenv ("ethaddr");
-#if defined (CONFIG_MBX) || defined (CONFIG_RPXCLASSIC) || defined(CONFIG_IAD210)
+#if defined (CONFIG_MBX) || \
+ defined (CONFIG_RPXCLASSIC) || \
+ defined(CONFIG_IAD210) || \
+ defined(CONFIG_V38B)
if (s == NULL)
board_get_enetaddr (bd->bi_enetaddr);
else
}
#endif
+#ifdef CFG_ID_EEPROM
+ mac_read_from_eeprom();
+#endif
+
#if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
load_sernum_ethaddr ();
doc_init ();
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
- WATCHDOG_RESET ();
- puts ("NAND: ");
- nand_init(); /* go init the NAND */
-#endif
-
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
WATCHDOG_RESET ();
#
# Parameters: Target Architecture CPU Board [VENDOR] [SOC]
#
-# (C) 2002 DENX Software Engineering, Wolfgang Denk <wd@denx.de>
+# (C) 2002-2006 DENX Software Engineering, Wolfgang Denk <wd@denx.de>
#
APPEND=no # Default: Create new config file
echo "Configuring for ${BOARD_NAME} board..."
-cd ./include
-
#
# Create link to architecture specific headers
#
-rm -f asm
-ln -s asm-$2 asm
+if [ "$SRCTREE" != "$OBJTREE" ] ; then
+ mkdir -p ${OBJTREE}/include
+ mkdir -p ${OBJTREE}/include2
+ cd ${OBJTREE}/include2
+ rm -f asm
+ ln -s ${SRCTREE}/include/asm-$2 asm
+ LNPREFIX="../../include2/asm/"
+ cd ../include
+ rm -rf asm-$2
+ rm -f asm
+ mkdir asm-$2
+ ln -s asm-$2 asm
+else
+ cd ./include
+ rm -f asm
+ ln -s asm-$2 asm
+fi
+
rm -f asm-$2/arch
if [ -z "$6" -o "$6" = "NULL" ] ; then
- ln -s arch-$3 asm-$2/arch
+ ln -s ${LNPREFIX}arch-$3 asm-$2/arch
else
- ln -s arch-$6 asm-$2/arch
+ ln -s ${LNPREFIX}arch-$6 asm-$2/arch
fi
if [ "$2" = "arm" ] ; then
rm -f asm-$2/proc
- ln -s proc-armv asm-$2/proc
+ ln -s ${LNPREFIX}proc-armv asm-$2/proc
fi
#
--- /dev/null
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
+SOBJS = start.o init.o resetvec.o
+COBJS = nand_boot.o ndfc.o sdram.o
+
+SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj := $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all: $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl: $(OBJS)
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ -Map $(nandobj)u-boot-spl.map \
+ -o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+# from cpu directory
+$(obj)ndfc.c:
+ @rm -f $(obj)ndfc.c
+ ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
+
+$(obj)resetvec.S:
+ @rm -f $(obj)resetvec.S
+ ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+
+$(obj)start.S:
+ @rm -f $(obj)start.S
+ ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
+
+# from board directory
+$(obj)init.S:
+ @rm -f $(obj)init.S
+ ln -s $(SRCTREE)/board/amcc/sequoia/init.S $(obj)init.S
+
+$(obj)sdram.c:
+ @rm -f $(obj)sdram.c
+ ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c
+
+# from nand_spl directory
+$(obj)nand_boot.c:
+ @rm -f $(obj)nand_boot.c
+ ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
+
+#########################################################################
+
+$(obj)%.o: $(obj)%.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o: $(obj)%.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EPx Reference Platform (Sequoia) board
+#
+
+#
+# TEXT_BASE for SPL:
+#
+# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
+# in the last 4kBytes of memory space in cache.
+# We will copy this SPL into internal SRAM in start.S. So we set
+# TEXT_BASE to starting address in internal SRAM here.
+#
+TEXT_BASE = 0xE0013000
+
+# PAD_TO used to generate a 16kByte binary needed for the combined image
+# -> PAD_TO = TEXT_BASE + 0x4000
+PAD_TO = 0xE0017000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc:common)
+SECTIONS
+{
+ .resetvec 0xE0013FFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .text :
+ {
+ start.o (.text)
+ init.o (.text)
+ nand_boot.o (.text)
+ sdram.o (.text)
+ ndfc.o (.text)
+
+ *(.text)
+ *(.fixup)
+ }
+ _etext = .;
+
+ .data :
+ {
+ *(.rodata*)
+ *(.data*)
+ *(.sdata*)
+ __got2_start = .;
+ *(.got2)
+ __got2_end = .;
+ }
+
+ _edata = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss)
+ *(.bss)
+ }
+
+ _end = . ;
+}
--- /dev/null
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+
+#define CFG_NAND_READ_DELAY \
+ { volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
+
+extern void board_nand_init(struct nand_chip *nand);
+extern void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd);
+extern void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte);
+extern u_char ndfc_read_byte(struct mtd_info *mtdinfo);
+extern int ndfc_dev_ready(struct mtd_info *mtdinfo);
+extern int jump_to_ram(ulong delta);
+extern int jump_to_uboot(ulong addr);
+
+static int nand_is_bad_block(struct mtd_info *mtd, int block)
+{
+ struct nand_chip *this = mtd->priv;
+ int page_addr = block * CFG_NAND_PAGE_COUNT;
+
+ /* Begin command latch cycle */
+ this->hwcontrol(mtd, NAND_CTL_SETCLE);
+ this->write_byte(mtd, NAND_CMD_READOOB);
+ /* Set ALE and clear CLE to start address cycle */
+ this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+ this->hwcontrol(mtd, NAND_CTL_SETALE);
+ /* Column address */
+ this->write_byte(mtd, CFG_NAND_BAD_BLOCK_POS); /* A[7:0] */
+ this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */
+ this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */
+#ifdef CFG_NAND_4_ADDR_CYCLE
+ /* One more address cycle for devices > 32MiB */
+ this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */
+#endif
+ /* Latch in address */
+ this->hwcontrol(mtd, NAND_CTL_CLRALE);
+
+ /*
+ * Wait a while for the data to be ready
+ */
+ if (this->dev_ready)
+ this->dev_ready(mtd);
+ else
+ CFG_NAND_READ_DELAY;
+
+ /*
+ * Read on byte
+ */
+ if (this->read_byte(mtd) != 0xff)
+ return 1;
+
+ return 0;
+}
+
+static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
+{
+ struct nand_chip *this = mtd->priv;
+ int page_addr = page + block * CFG_NAND_PAGE_COUNT;
+ int i;
+
+ /* Begin command latch cycle */
+ this->hwcontrol(mtd, NAND_CTL_SETCLE);
+ this->write_byte(mtd, NAND_CMD_READ0);
+ /* Set ALE and clear CLE to start address cycle */
+ this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+ this->hwcontrol(mtd, NAND_CTL_SETALE);
+ /* Column address */
+ this->write_byte(mtd, 0); /* A[7:0] */
+ this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */
+ this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */
+#ifdef CFG_NAND_4_ADDR_CYCLE
+ /* One more address cycle for devices > 32MiB */
+ this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */
+#endif
+ /* Latch in address */
+ this->hwcontrol(mtd, NAND_CTL_CLRALE);
+
+ /*
+ * Wait a while for the data to be ready
+ */
+ if (this->dev_ready)
+ this->dev_ready(mtd);
+ else
+ CFG_NAND_READ_DELAY;
+
+ /*
+ * Read page into buffer
+ */
+ for (i=0; i<CFG_NAND_PAGE_SIZE; i++)
+ *dst++ = this->read_byte(mtd);
+
+ return 0;
+}
+
+static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst)
+{
+ int block;
+ int blockcopy_count;
+ int page;
+
+ /*
+ * offs has to be aligned to a block address!
+ */
+ block = offs / CFG_NAND_BLOCK_SIZE;
+ blockcopy_count = 0;
+
+ while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) {
+ if (!nand_is_bad_block(mtd, block)) {
+ /*
+ * Skip bad blocks
+ */
+ for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) {
+ nand_read_page(mtd, block, page, dst);
+ dst += CFG_NAND_PAGE_SIZE;
+ }
+
+ blockcopy_count++;
+ }
+
+ block++;
+ }
+
+ return 0;
+}
+
+void nand_boot(void)
+{
+ ulong mem_size;
+ struct nand_chip nand_chip;
+ nand_info_t nand_info;
+ int ret;
+ void (*uboot)(void);
+
+ /*
+ * Init sdram, so we have access to memory
+ */
+ mem_size = initdram(0);
+
+ /*
+ * Init board specific nand support
+ */
+ nand_info.priv = &nand_chip;
+ nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CFG_NAND_BASE;
+ nand_chip.dev_ready = NULL; /* preset to NULL */
+ board_nand_init(&nand_chip);
+
+ /*
+ * Load U-Boot image from NAND into RAM
+ */
+ ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
+ (uchar *)CFG_NAND_U_BOOT_DST);
+
+ /*
+ * Jump to U-Boot image
+ */
+ uboot = (void (*)(void))CFG_NAND_U_BOOT_START;
+ (*uboot)();
+}
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# CFLAGS += -DET_DEBUG -DDEBUG
-LIB = libnet.a
+LIB = $(obj)libnet.a
+
+COBJS = net.o tftp.o bootp.o rarp.o eth.o nfs.o sntp.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
-OBJS = net.o tftp.o bootp.o rarp.o eth.o nfs.o sntp.o
all: $(LIB)
-$(LIB): $(START) $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
NetCopyIP(&bp->bp_ciaddr, &bp_offer->bp_ciaddr); /* both in network byte order */
NetCopyIP(&bp->bp_yiaddr, &bp_offer->bp_yiaddr);
NetCopyIP(&bp->bp_siaddr, &bp_offer->bp_siaddr);
- NetCopyIP(&bp->bp_giaddr, &bp_offer->bp_giaddr);
+ /*
+ * RFC3046 requires Relay Agents to discard packets with
+ * nonzero and offered giaddr
+ */
+ NetWriteIP(&bp->bp_giaddr, 0);
+
memcpy (bp->bp_chaddr, NetOurEther, 6);
/*
tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME);
# endif
#endif
+#if defined(CONFIG_MPC86XX_TSEC1)
+ tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC2)
+ tsec_initialize(bis, 1, CONFIG_MPC86XX_TSEC2_NAME);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC3)
+ tsec_initialize(bis, 2, CONFIG_MPC86XX_TSEC3_NAME);
+#endif
+
+#if defined(CONFIG_MPC86XX_TSEC4)
+ tsec_initialize(bis, 3, CONFIG_MPC86XX_TSEC4_NAME);
+#endif
+
#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
fec_initialize(bis);
#endif
if (TftpBlock == 0) {
TftpBlockWrap++;
TftpBlockWrapOffset += TFTP_BLOCK_SIZE * TFTP_SEQUENCE_SIZE;
- printf ("\n\t %lu MB reveived\n\t ", TftpBlockWrapOffset>>20);
+ printf ("\n\t %lu MB received\n\t ", TftpBlockWrapOffset>>20);
} else {
if (((TftpBlock - 1) % 10) == 0) {
putc ('#');
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-OBJS = $(AOBJS) $(COBJS)
+SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS))
+LIB := $(obj)$(LIB)
CPPFLAGS += -I$(TOPDIR)
all: $(LIB)
-$(LIB): .depend $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > .depend
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
-# (C) Copyright 2001-2004
+# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#CFLAGS += -DDEBUG
-LIB = librtc.a
+LIB = $(obj)librtc.a
-OBJS = date.o \
+COBJS = date.o \
bf533_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o \
m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \
mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
all: $(LIB)
-$(LIB): $(START) $(OBJS)
- $(AR) crv $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
--- /dev/null
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#########################################################################
+
+_depend: $(obj).depend
+
+$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(SRCS)
+ @rm -f $@
+ @for f in $(SRCS); do \
+ g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \
+ $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \
+ done
+
+#########################################################################
#
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# MA 02111-1307 USA
#
-BINS = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX)
+BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX)
-OBJS = environment.o img2srec.o mkimage.o crc32.o envcrc.o gen_eth_addr.o bmp_logo.o
+OBJ_LINKS = environment.o crc32.o
+OBJ_FILES = img2srec.o mkimage.o envcrc.o gen_eth_addr.o bmp_logo.o
ifeq ($(ARCH),mips)
-BINS += inca-swap-bytes$(SFX)
-OBJS += inca-swap-bytes.o
+BIN_FILES += inca-swap-bytes$(SFX)
+OBJ_FILES += inca-swap-bytes.o
endif
# Don't build by default
#ifeq ($(ARCH),ppc)
-#BINS += mpc86x_clk$(SFX)
-#OBJS += mpc86x_clk.o
+#BIN_FILES += mpc86x_clk$(SFX)
+#OBJ_FILES += mpc86x_clk.o
#endif
-LOGO_H = $(TOPDIR)/include/bmp_logo.h
+LOGO_H = $(OBJTREE)/include/bmp_logo.h
ifeq ($(LOGO_BMP),)
LOGO_BMP= logos/denx.bmp
#
include $(TOPDIR)/config.mk
+# now $(obj) is defined
+SRCS := $(addprefix $(obj),$(OBJ_LINKS:.o=.c)) $(OBJ_FILES:.o=.c)
+BINS := $(addprefix $(obj),$(BIN_FILES))
+
#
# Use native tools and options
#
-CPPFLAGS = -idirafter ../include -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC
+CPPFLAGS = -idirafter $(SRCTREE)/include \
+ -idirafter $(OBJTREE)/include2 \
+ -idirafter $(OBJTREE)/include \
+ -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC
CFLAGS = $(HOST_CFLAGS) $(CPPFLAGS) -O
AFLAGS = -D__ASSEMBLY__ $(CPPFLAGS)
CC = $(HOSTCC)
STRIP = $(HOSTSTRIP)
MAKEDEPEND = makedepend
-all: .depend $(BINS) $(LOGO_H) subdirs
+all: $(obj).depend $(BINS) $(LOGO_H) subdirs
-envcrc$(SFX): envcrc.o crc32.o environment.o
+$(obj)envcrc$(SFX): $(obj)envcrc.o $(obj)crc32.o $(obj)environment.o
$(CC) $(CFLAGS) -o $@ $^
-img2srec$(SFX): img2srec.o
+$(obj)img2srec$(SFX): $(obj)img2srec.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
-mkimage$(SFX): mkimage.o crc32.o
+$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
-ncb$(SFX): ncb.o
+$(obj)ncb$(SFX): $(obj)ncb.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
-gen_eth_addr$(SFX): gen_eth_addr.o
+$(obj)gen_eth_addr$(SFX): $(obj)gen_eth_addr.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
-bmp_logo$(SFX): bmp_logo.o
+$(obj)bmp_logo$(SFX): $(obj)bmp_logo.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
-inca-swap-bytes$(SFX): inca-swap-bytes.o
+$(obj)inca-swap-bytes$(SFX): $(obj)inca-swap-bytes.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
-mpc86x_clk$(SFX): mpc86x_clk.o
+$(obj)mpc86x_clk$(SFX): $(obj)mpc86x_clk.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
$(STRIP) $@
-envcrc.o: envcrc.c
- $(CC) -g $(CFLAGS) -c $<
+$(obj)envcrc.o: $(src)envcrc.c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
-crc32.o: crc32.c
- $(CC) -g $(CFLAGS) -c $<
+$(obj)crc32.o: $(obj)crc32.c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
-mkimage.o: mkimage.c
- $(CC) -g $(CFLAGS) -c $<
+$(obj)mkimage.o: $(src)mkimage.c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
-ncb.o: ncb.c
- $(CC) -g $(CFLAGS) -c $<
+$(obj)ncb.o: $(src)ncb.c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
-gen_eth_addr.o: gen_eth_addr.c
- $(CC) -g $(CFLAGS) -c $<
+$(obj)gen_eth_addr.o: $(src)gen_eth_addr.c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
-inca-swap-bytes.o: inca-swap-bytes.c
- $(CC) -g $(CFLAGS) -c $<
+$(obj)inca-swap-bytes.o: $(src)inca-swap-bytes.c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
-mpc86x_clk.o: mpc86x_clk.c
- $(CC) -g $(CFLAGS) -c $<
+$(obj)mpc86x_clk.o: $(src)mpc86x_clk.c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
subdirs:
ifeq ($(TOOLSUBDIRS),)
done
endif
-environment.c:
- @rm -f environment.c
- ln -s ../common/environment.c environment.c
+$(obj)environment.c:
+ @rm -f $(obj)environment.c
+ ln -s $(src)../common/environment.c $(obj)environment.c
-environment.o: environment.c
- $(CC) -g $(HOST_ENVIRO_CFLAGS) $(CPPFLAGS) -c $<
+$(obj)environment.o: $(obj)environment.c
+ $(CC) -g $(HOST_ENVIRO_CFLAGS) $(CPPFLAGS) -c -o $@ $<
-crc32.c:
- @rm -f crc32.c
- ln -s ../lib_generic/crc32.c crc32.c
+$(obj)crc32.c:
+ @rm -f $(obj)crc32.c
+ ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c
-$(LOGO_H): bmp_logo $(LOGO_BMP)
- ./bmp_logo $(LOGO_BMP) >$@
+$(LOGO_H): $(obj)bmp_logo $(LOGO_BMP)
+ $(obj)./bmp_logo $(LOGO_BMP) >$@
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
return -1 ;
/* Author information */
- fprintf(file, "/*\n * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi\n/*\n"); */
+ fprintf(file, "/*\n * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi\n *\n");
fprintf(file, " * To use this, include it and call: easylogo_plot(screen,&%s, width,x,y)\n *\n", varname);
fprintf(file, " * Where:\t'screen'\tis the pointer to the frame buffer\n");
fprintf(file, " *\t\t'width'\tis the screen width\n");
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# MA 02111-1307 USA
#
-SOURCES := crc32.c fw_env.c fw_env_main.c
-HEADERS := fw_env.h
+include $(TOPDIR)/config.mk
-all: fw_printenv
+SRCS := $(obj)crc32.c fw_env.c fw_env_main.c
+HEADERS := fw_env.h
-fw_printenv: $(SOURCES) $(HEADERS)
- $(CROSS_COMPILE)gcc -Wall -DUSE_HOSTCC $(SOURCES) -o fw_printenv
+CPPFLAGS := -Wall -DUSE_HOSTCC
+
+all: $(obj)fw_printenv
+
+$(obj)fw_printenv: $(SRCS) $(HEADERS)
+ $(CROSS_COMPILE)gcc $(CPPFLAGS) $(SRCS) -o $(obj)fw_printenv
clean:
- rm -f fw_printenv crc32.c
+ rm -f $(obj)fw_printenv $(obj)crc32.c
-crc32.c:
- ln -s ../../lib_generic/crc32.c crc32.c
+$(obj)crc32.c:
+ ln -s $(src)../../lib_generic/crc32.c $(obj)crc32.c
#########################################################################
-.depend: Makefile $(SOURCES)
- $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) -DUSE_HOSTCC $(SOURCES) > $@
+include $(TOPDIR)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2000
# Murray Jensen <Murray.Jensen@csiro.au>
#
BINS = gdbsend gdbcont
-OBJS = gdbsend.o gdbcont.o error.o remote.o serial.o
+COBJS = gdbsend.o gdbcont.o error.o remote.o serial.o
+
+OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(COBJS:.o=.c)
+BINS := $(addprefix $(obj),$(BINS))
#
# Use native tools and options
else # ! CYGWIN
-all: $(BINS)
+all: $(obj).depend $(BINS)
-gdbsend: gdbsend.o error.o remote.o serial.o
+$(obj)gdbsend: $(obj)gdbsend.o $(obj)error.o $(obj)remote.o $(obj)serial.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
-gdbcont: gdbcont.o error.o remote.o serial.o
+$(obj)gdbcont: $(obj)gdbcont.o $(obj)error.o $(obj)remote.o $(obj)serial.o
$(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
clean:
rm -f $(OBJS)
distclean: clean
- rm -f $(BINS) core *.bak .depend
+ rm -f $(BINS) $(obj)core $(obj)*.bak $(obj).depend
#########################################################################
-.depend: Makefile $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) -I../include $(OBJS:.o=.c) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
--include .depend
+sinclude $(obj).depend
#########################################################################
{ IH_CPU_SPARC, "sparc", "SPARC", },
{ IH_CPU_SPARC64, "sparc64", "SPARC 64 Bit", },
{ IH_CPU_BLACKFIN, "blackfin", "Blackfin", },
+ { IH_CPU_AVR32, "avr32", "AVR32", },
{ -1, "", "", },
};
{ IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", },
{ IH_TYPE_SCRIPT, "script", "Script", },
{ IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
+ { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", },
{ -1, "", "", },
};
if (hdr->ih_type == IH_TYPE_MULTI || hdr->ih_type == IH_TYPE_SCRIPT) {
int i, ptrs;
uint32_t pos;
- unsigned long *len_ptr = (unsigned long *) (
+ uint32_t *len_ptr = (uint32_t *) (
(unsigned long)hdr + sizeof(image_header_t)
);
#
-# (C) Copyright 2000
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-PROG = updater
-IMAGE = updater.image
-SRC = update.c flash.c flash_hw.c utils.c cmd_flash.c string.c ctype.c dummy.c
-ASRC = ppcstring.S
-OBJS = $(SRC:.c=.o) $(ASRC:.S=.o)
+PROG = $(obj)updater
+IMAGE = $(obj)updater.image
-LIB = $(TOPDIR)/examples/libstubs.a
-LIBAOBJS=
-LIBCOBJS= $(TOPDIR)/examples/stubs.o
-LIBOBJS = $(LIBAOBJS) $(LIBCOBJS)
+COBJS = update.o flash.o flash_hw.o utils.o cmd_flash.o string.o ctype.o dummy.o
+COBJS_LINKS = stubs.o
+AOBJS = ppcstring.o
+AOBJS_LINKS = memio.o
+
+OBJS := $(addprefix $(obj),$(COBJS) $(COBJS_LINKS) $(AOBJS) $(AOBJS_LINKS))
+SRCS := $(COBJS:.o=.c) $(AOBJS:.o=.S) $(addprefix $(obj), $(COBJS_LINKS:.o:.c) $(AOBJS_LINKS:.o:.S))
CPPFLAGS += -I$(TOPDIR) -I$(TOPDIR)/board/MAI/AmigaOneG3SE
CFLAGS += -I$(TOPDIR)/board/MAI/AmigaOneG3SE
+AFLAGS += -I$(TOPDIR)/board/MAI/AmigaOneG3SE
+
+DEPS = $(OBJTREE)/u-boot.bin $(OBJTREE)/tools/mkimage
+ifneq ($(DEPS),$(wildcard $(DEPS)))
+$(error "updater: Missing required objects, please run regular build first")
+endif
-all: .depend $(LIB) $(PROG)
+all: $(obj).depend $(PROG) $(IMAGE)
#########################################################################
-$(LIB): .depend $(LIBOBJS)
- $(AR) crv $@ $(LIBOBJS)
-%.srec: %.o $(LIB)
+$(obj)%.srec: %.o $(LIB)
$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $< $(LIB)
$(OBJCOPY) -O srec $(<:.o=) $@
-%.o: %.c
- $(CC) $(CPPFLAGS) -c $<
+$(obj)%.o: %.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+$(obj)%.o: %.S
+ $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)memio.o: $(obj)memio.S
+ $(CC) $(AFLAGS) -c -o $@ $<
-%.o: %.S
- $(CC) $(CPPFLAGS) -c $<
+$(obj)memio.S:
+ rm -f $(obj)memio.c
+ ln -s $(SRCTREE)/board/MAI/AmigaOneG3SE/memio.S $(obj)memio.S
+
+$(obj)stubs.o: $(obj)stubs.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+$(obj)stubs.c:
+ rm -f $(obj)stubs.c
+ ln -s $(SRCTREE)/examples/stubs.c $(obj)stubs.c
#########################################################################
-updater: $(OBJS) $(LIB) $(TOPDIR)/board/MAI/AmigaOneG3SE/memio.o
- $(LD) -g -Ttext $(LOAD_ADDR) -o updater -e _main $(OBJS) $(LIB) \
- $(TOPDIR)/board/MAI/AmigaOneG3SE/memio.o
- $(OBJCOPY) -O binary updater updater.bin
+$(obj)updater: $(OBJS)
+ $(LD) -g -Ttext $(LOAD_ADDR) -o $(obj)updater -e _main $(OBJS)
+ $(OBJCOPY) -O binary $(obj)updater $(obj)updater.bin
-updater.image: updater $(TOPDIR)/u-boot.bin
- cat >/tmp/tempimage updater.bin junk $(TOPDIR)/u-boot.bin
- $(TOPDIR)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \
- -e `ppc-elf32-nm updater | grep _main | cut --bytes=0-8` \
- -n "Firmware Updater" -d /tmp/tempimage updater.image
+$(obj)updater.image: $(obj)updater $(OBJTREE)/u-boot.bin
+ cat >/tmp/tempimage $(obj)updater.bin junk $(OBJTREE)/u-boot.bin
+ $(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \
+ -e `$(NM) $(obj)updater | grep _main | cut --bytes=0-8` \
+ -n "Firmware Updater" -d /tmp/tempimage $(obj)updater.image
rm /tmp/tempimage
- cp updater.image /tftpboot
+ cp $(obj)updater.image /tftpboot
-updater.image2: updater $(TOPDIR)/u-boot.bin
- cat >/tmp/tempimage updater.bin junk ../../create_image/image
- $(TOPDIR)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \
- -e `ppc-elf32-nm updater | grep _main | cut --bytes=0-8` \
- -n "Firmware Updater" -d /tmp/tempimage updater.image
+(obj)updater.image2: $(obj)updater $(OBJTREE)/u-boot.bin
+ cat >/tmp/tempimage $(obj)updater.bin junk ../../create_image/image
+ $(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \
+ -e `$(NM) $(obj)updater | grep _main | cut --bytes=0-8` \
+ -n "Firmware Updater" -d /tmp/tempimage $(obj)updater.image
rm /tmp/tempimage
- cp updater.image /tftpboot
+ cp $(obj)updater.image /tftpboot
+
+#########################################################################
-.depend: Makefile $(SRC) $(ASRC) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S)
- $(CC) -M $(CFLAGS) $(SRC) $(ASRC) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* (only some targets require alignment)
*/
int
-flash_write (uchar *src, ulong addr, ulong cnt)
+flash_write (char *src, ulong addr, ulong cnt)
{
#ifdef CONFIG_SPD823TS
return (ERR_TIMOUT); /* any other error codes are possible as well */
while (1);
}
-int flash_sect_protect (int p, ulong addr_first, ulong addr_last);
-int flash_sect_erase (ulong addr_first, ulong addr_last);
-int flash_write (uchar *src, ulong addr, ulong cnt);
-
void do_updater(void)
{
unsigned long *addr = &__dummy + 65;
projects / oweals / u-boot.git / commitdiff