Note: Without this binary U-Boot will not be able to set up its
SDRAM so will not boot.
+choice
+ prompt "FSP version"
+ depends on HAVE_FSP
+ default FSP_VERSION1
+ help
+ Selects the FSP version to use. Intel has published several versions
+ of the FSP External Architecture Specification and this allows
+ selection of the version number used by a particular SoC.
+
+config FSP_VERSION1
+ bool "FSP version 1.x"
+ help
+ This covers versions 1.0 and 1.1a. See here for details:
+ https://github.com/IntelFsp/fsp/wiki
+
+config FSP_VERSION2
+ bool "FSP version 2.x"
+ help
+ This covers versions 2.0 and 2.1. See here for details:
+ https://github.com/IntelFsp/fsp/wiki
+
+endchoice
+
config FSP_FILE
string "Firmware Support Package binary filename"
depends on HAVE_FSP
For platforms that use Intel FSP for the memory initialization,
please check FSP output HOB via U-Boot command 'fsp hob' to see
- if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
+ if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
If such GUID does not exist, MRC cache is not available on such
platform (eg: Intel Queensbay), which means selecting this option
here does not make any difference.
* and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses
* of these two blocks are programmed by either U-Boot or FSP.
*
- * It has been verified that 1st phase API (see arch/x86/lib/fsp/fsp_car.S)
+ * It has been verified that 1st phase API (see arch/x86/lib/fsp1/fsp_car.S)
* on Intel BayTrail SoC already initializes these two base addresses so
* we are safe to access these registers here.
*/
#include <common.h>
#include <fdtdec.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <fdtdec.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <fdtdec.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
*/
#include <common.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
void update_fsp_configs(struct fsp_config_data *config,
struct fspinit_rtbuf *rt_buf)
#include <asm/post.h>
#include <asm/arch/device.h>
#include <asm/arch/tnc.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
#include <asm/processor.h>
static int __maybe_unused disable_igd(void)
+++ /dev/null
-/* SPDX-License-Identifier: Intel */
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#ifndef __FSP_API_H__
-#define __FSP_API_H__
-
-#include <linux/linkage.h>
-
-/*
- * FSP common configuration structure.
- * This needs to be included in the platform-specific struct fsp_config_data.
- */
-struct fsp_cfg_common {
- struct fsp_header *fsp_hdr;
- u32 stack_top;
- u32 boot_mode;
-};
-
-/*
- * FspInit continuation function prototype.
- * Control will be returned to this callback function after FspInit API call.
- */
-typedef void (*fsp_continuation_f)(u32 status, void *hob_list);
-
-struct fsp_init_params {
- /* Non-volatile storage buffer pointer */
- void *nvs_buf;
- /* Runtime buffer pointer */
- void *rt_buf;
- /* Continuation function address */
- fsp_continuation_f continuation;
-};
-
-struct common_buf {
- /*
- * Stack top pointer used by the bootloader. The new stack frame will be
- * set up at this location after FspInit API call.
- */
- u32 stack_top;
- u32 boot_mode; /* Current system boot mode */
- void *upd_data; /* User platform configuraiton data region */
- u32 tolum_size; /* Top of low usable memory size (FSP 1.1) */
- u32 reserved[6]; /* Reserved */
-};
-
-enum fsp_phase {
- /* Notification code for post PCI enuermation */
- INIT_PHASE_PCI = 0x20,
- /* Notification code before transfering control to the payload */
- INIT_PHASE_BOOT = 0x40
-};
-
-struct fsp_notify_params {
- /* Notification phase used for NotifyPhase API */
- enum fsp_phase phase;
-};
-
-/* FspInit API function prototype */
-typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params);
-
-/* FspNotify API function prototype */
-typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: Intel */
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2015, Google, Inc
- */
-
-#ifndef _FSP_AZALIA_H_
-#define _FSP_AZALIA_H_
-
-struct __packed azalia_verb_table_header {
- u32 vendor_device_id;
- u16 sub_system_id;
- u8 revision_id; /* 0xff applies to all steppings */
- u8 front_panel_support;
- u16 number_of_rear_jacks;
- u16 number_of_front_jacks;
-};
-
-struct __packed azalia_verb_table {
- struct azalia_verb_table_header header;
- const u32 *data;
-};
-
-struct __packed azalia_config {
- u8 pme_enable:1;
- u8 docking_supported:1;
- u8 docking_attached:1;
- u8 hdmi_codec_enable:1;
- u8 azalia_v_ci_enable:1;
- u8 rsvdbits:3;
- /* number of verb tables provided by platform */
- u8 verb_table_num;
- const struct azalia_verb_table *verb_table;
- /* delay timer after azalia reset */
- u16 reset_wait_timer_ms;
-};
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: Intel */
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#ifndef __FSP_BOOT_MODE_H__
-#define __FSP_BOOT_MODE_H__
-
-/* 0x21 - 0xf..f are reserved */
-#define BOOT_FULL_CONFIG 0x00
-#define BOOT_MINIMAL_CONFIG 0x01
-#define BOOT_NO_CONFIG_CHANGES 0x02
-#define BOOT_FULL_CONFIG_PLUS_DIAG 0x03
-#define BOOT_DEFAULT_SETTINGS 0x04
-#define BOOT_ON_S4_RESUME 0x05
-#define BOOT_ON_S5_RESUME 0x06
-#define BOOT_ON_S2_RESUME 0x10
-#define BOOT_ON_S3_RESUME 0x11
-#define BOOT_ON_FLASH_UPDATE 0x12
-#define BOOT_IN_RECOVERY_MODE 0x20
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: Intel */
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#ifndef __FSP_FFS_H__
-#define __FSP_FFS_H__
-
-/* Used to verify the integrity of the file */
-union __packed ffs_integrity {
- struct {
- /*
- * The IntegrityCheck.checksum.header field is an 8-bit
- * checksum of the file header. The State and
- * IntegrityCheck.checksum.file fields are assumed to be zero
- * and the checksum is calculated such that the entire header
- * sums to zero.
- */
- u8 header;
- /*
- * If the FFS_ATTRIB_CHECKSUM (see definition below) bit of
- * the Attributes field is set to one, the
- * IntegrityCheck.checksum.file field is an 8-bit checksum of
- * the file data. If the FFS_ATTRIB_CHECKSUM bit of the
- * Attributes field is cleared to zero, the
- * IntegrityCheck.checksum.file field must be initialized with
- * a value of 0xAA. The IntegrityCheck.checksum.file field is
- * valid any time the EFI_FILE_DATA_VALID bit is set in the
- * State field.
- */
- u8 file;
- } checksum;
-
- /* This is the full 16 bits of the IntegrityCheck field */
- u16 checksum16;
-};
-
-/*
- * Each file begins with the header that describe the
- * contents and state of the files.
- */
-struct __packed ffs_file_header {
- /*
- * This GUID is the file name.
- * It is used to uniquely identify the file.
- */
- efi_guid_t name;
- /* Used to verify the integrity of the file */
- union ffs_integrity integrity;
- /* Identifies the type of file */
- u8 type;
- /* Declares various file attribute bits */
- u8 attr;
- /* The length of the file in bytes, including the FFS header */
- u8 size[3];
- /*
- * Used to track the state of the file throughout the life of
- * the file from creation to deletion.
- */
- u8 state;
-};
-
-struct __packed ffs_file_header2 {
- /*
- * This GUID is the file name. It is used to uniquely identify the file.
- * There may be only one instance of a file with the file name GUID of
- * Name in any given firmware volume, except if the file type is
- * EFI_FV_FILE_TYPE_FFS_PAD.
- */
- efi_guid_t name;
- /* Used to verify the integrity of the file */
- union ffs_integrity integrity;
- /* Identifies the type of file */
- u8 type;
- /* Declares various file attribute bits */
- u8 attr;
- /*
- * The length of the file in bytes, including the FFS header.
- * The length of the file data is either
- * (size - sizeof(struct ffs_file_header)). This calculation means a
- * zero-length file has a size of 24 bytes, which is
- * sizeof(struct ffs_file_header). Size is not required to be a
- * multiple of 8 bytes. Given a file F, the next file header is located
- * at the next 8-byte aligned firmware volume offset following the last
- * byte of the file F.
- */
- u8 size[3];
- /*
- * Used to track the state of the file throughout the life of
- * the file from creation to deletion.
- */
- u8 state;
- /*
- * If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists
- * and size must be set to zero.
- * If FFS_ATTRIB_LARGE_FILE is not set then
- * struct ffs_file_header is used.
- */
- u32 ext_size;
-};
-
-/*
- * Pseudo type. It is used as a wild card when retrieving sections.
- * The section type EFI_SECTION_ALL matches all section types.
- */
-#define EFI_SECTION_ALL 0x00
-
-/* Encapsulation section Type values */
-#define EFI_SECTION_COMPRESSION 0x01
-#define EFI_SECTION_GUID_DEFINED 0x02
-#define EFI_SECTION_DISPOSABLE 0x03
-
-/* Leaf section Type values */
-#define EFI_SECTION_PE32 0x10
-#define EFI_SECTION_PIC 0x11
-#define EFI_SECTION_TE 0x12
-#define EFI_SECTION_DXE_DEPEX 0x13
-#define EFI_SECTION_VERSION 0x14
-#define EFI_SECTION_USER_INTERFACE 0x15
-#define EFI_SECTION_COMPATIBILITY16 0x16
-#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
-#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
-#define EFI_SECTION_RAW 0x19
-#define EFI_SECTION_PEI_DEPEX 0x1B
-#define EFI_SECTION_SMM_DEPEX 0x1C
-
-/* Common section header */
-struct __packed raw_section {
- /*
- * A 24-bit unsigned integer that contains the total size of
- * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
- */
- u8 size[3];
- u8 type;
-};
-
-struct __packed raw_section2 {
- /*
- * A 24-bit unsigned integer that contains the total size of
- * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
- */
- u8 size[3];
- u8 type;
- /*
- * If size is 0xFFFFFF, then ext_size contains the size of
- * the section. If size is not equal to 0xFFFFFF, then this
- * field does not exist.
- */
- u32 ext_size;
-};
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: Intel */
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#ifndef __FSP_FV___
-#define __FSP_FV___
-
-/* Value of EFI_FV_FILE_ATTRIBUTES */
-#define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F
-#define EFI_FV_FILE_ATTR_FIXED 0x00000100
-#define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200
-
-/* Attributes bit definitions */
-#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
-#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
-#define EFI_FVB2_READ_STATUS 0x00000004
-#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
-#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
-#define EFI_FVB2_WRITE_STATUS 0x00000020
-#define EFI_FVB2_LOCK_CAP 0x00000040
-#define EFI_FVB2_LOCK_STATUS 0x00000080
-#define EFI_FVB2_STICKY_WRITE 0x00000200
-#define EFI_FVB2_MEMORY_MAPPED 0x00000400
-#define EFI_FVB2_ERASE_POLARITY 0x00000800
-#define EFI_FVB2_READ_LOCK_CAP 0x00001000
-#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
-#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
-#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
-#define EFI_FVB2_ALIGNMENT 0x001F0000
-#define EFI_FVB2_ALIGNMENT_1 0x00000000
-#define EFI_FVB2_ALIGNMENT_2 0x00010000
-#define EFI_FVB2_ALIGNMENT_4 0x00020000
-#define EFI_FVB2_ALIGNMENT_8 0x00030000
-#define EFI_FVB2_ALIGNMENT_16 0x00040000
-#define EFI_FVB2_ALIGNMENT_32 0x00050000
-#define EFI_FVB2_ALIGNMENT_64 0x00060000
-#define EFI_FVB2_ALIGNMENT_128 0x00070000
-#define EFI_FVB2_ALIGNMENT_256 0x00080000
-#define EFI_FVB2_ALIGNMENT_512 0x00090000
-#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
-#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
-#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
-#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
-#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
-#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
-#define EFI_FVB2_ALIGNMENT_64K 0x00100000
-#define EFI_FVB2_ALIGNMENT_128K 0x00110000
-#define EFI_FVB2_ALIGNMENT_256K 0x00120000
-#define EFI_FVB2_ALIGNMENT_512K 0x00130000
-#define EFI_FVB2_ALIGNMENT_1M 0x00140000
-#define EFI_FVB2_ALIGNMENT_2M 0x00150000
-#define EFI_FVB2_ALIGNMENT_4M 0x00160000
-#define EFI_FVB2_ALIGNMENT_8M 0x00170000
-#define EFI_FVB2_ALIGNMENT_16M 0x00180000
-#define EFI_FVB2_ALIGNMENT_32M 0x00190000
-#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
-#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
-#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
-#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
-#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
-#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
-
-struct fv_blkmap_entry {
- /* The number of sequential blocks which are of the same size */
- u32 num_blocks;
- /* The size of the blocks */
- u32 length;
-};
-
-/* Describes the features and layout of the firmware volume */
-struct fv_header {
- /*
- * The first 16 bytes are reserved to allow for the reset vector of
- * processors whose reset vector is at address 0.
- */
- u8 zero_vec[16];
- /*
- * Declares the file system with which the firmware volume
- * is formatted.
- */
- efi_guid_t fs_guid;
- /*
- * Length in bytes of the complete firmware volume, including
- * the header.
- */
- u64 fv_len;
- /* Set to EFI_FVH_SIGNATURE */
- u32 sign;
- /*
- * Declares capabilities and power-on defaults for the firmware
- * volume.
- */
- u32 attr;
- /* Length in bytes of the complete firmware volume header */
- u16 hdr_len;
- /*
- * A 16-bit checksum of the firmware volume header.
- * A valid header sums to zero.
- */
- u16 checksum;
- /*
- * Offset, relative to the start of the header, of the extended
- * header (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is
- * no extended header.
- */
- u16 ext_hdr_off;
- /* This field must always be set to zero */
- u8 reserved[1];
- /*
- * Set to 2. Future versions of this specification may define new
- * header fields and will increment the Revision field accordingly.
- */
- u8 rev;
- /*
- * An array of run-length encoded FvBlockMapEntry structures.
- * The array is terminated with an entry of {0,0}.
- */
- struct fv_blkmap_entry block_map[1];
-};
-
-#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H')
-
-/* Firmware Volume Header Revision definition */
-#define EFI_FVH_REVISION 0x02
-
-/* Extension header pointed by ExtHeaderOffset of volume header */
-struct fv_ext_header {
- /* firmware volume name */
- efi_guid_t fv_name;
- /* Size of the rest of the extension header including this structure */
- u32 ext_hdr_size;
-};
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: Intel */
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#ifndef __FSP_HOB_H__
-#define __FSP_HOB_H__
-
-#include <asm/hob.h>
-
-enum pixel_format {
- pixel_rgbx_8bpc, /* RGB 8 bit per color */
- pixel_bgrx_8bpc, /* BGR 8 bit per color */
- pixel_bitmask,
-};
-
-struct __packed hob_graphics_info {
- phys_addr_t fb_base; /* framebuffer base address */
- u32 fb_size; /* framebuffer size */
- u32 version;
- u32 width;
- u32 height;
- enum pixel_format pixel_format;
- u32 red_mask;
- u32 green_mask;
- u32 blue_mask;
- u32 reserved_mask;
- u32 pixels_per_scanline;
-};
-
-/* FSP specific GUID HOB definitions */
-#define FSP_GUID_DATA1 0x912740be
-#define FSP_GUID_DATA2 0x2284
-#define FSP_GUID_DATA3 0x4734
-#define FSP_GUID_DATA4_0 0xb9
-#define FSP_GUID_DATA4_1 0x71
-#define FSP_GUID_DATA4_2 0x84
-#define FSP_GUID_DATA4_3 0xb0
-#define FSP_GUID_DATA4_4 0x27
-#define FSP_GUID_DATA4_5 0x35
-#define FSP_GUID_DATA4_6 0x3f
-#define FSP_GUID_DATA4_7 0x0c
-
-#define FSP_GUID_BYTE0 0xbe
-#define FSP_GUID_BYTE1 0x40
-#define FSP_GUID_BYTE2 0x27
-#define FSP_GUID_BYTE3 0x91
-#define FSP_GUID_BYTE4 0x84
-#define FSP_GUID_BYTE5 0x22
-#define FSP_GUID_BYTE6 0x34
-#define FSP_GUID_BYTE7 0x47
-#define FSP_GUID_BYTE8 FSP_GUID_DATA4_0
-#define FSP_GUID_BYTE9 FSP_GUID_DATA4_1
-#define FSP_GUID_BYTE10 FSP_GUID_DATA4_2
-#define FSP_GUID_BYTE11 FSP_GUID_DATA4_3
-#define FSP_GUID_BYTE12 FSP_GUID_DATA4_4
-#define FSP_GUID_BYTE13 FSP_GUID_DATA4_5
-#define FSP_GUID_BYTE14 FSP_GUID_DATA4_6
-#define FSP_GUID_BYTE15 FSP_GUID_DATA4_7
-
-#define FSP_HEADER_GUID \
- EFI_GUID(FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \
- FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \
- FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \
- FSP_GUID_DATA4_6, FSP_GUID_DATA4_7)
-
-#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
- EFI_GUID(0x721acf02, 0x4d77, 0x4c2a, \
- 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0)
-
-#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \
- EFI_GUID(0xbbcff46c, 0xc8d3, 0x4113, \
- 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e)
-
-#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \
- EFI_GUID(0x69a79759, 0x1373, 0x4367, \
- 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e)
-
-#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
- EFI_GUID(0xd038747c, 0xd00c, 0x4980, \
- 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55)
-
-#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \
- EFI_GUID(0x9c7c3aa7, 0x5332, 0x4917, \
- 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07)
-
-/* The following GUIDs are newly introduced in FSP spec 1.1 */
-
-#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \
- EFI_GUID(0x73ff4f56, 0xaa8e, 0x4451, \
- 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44)
-
-#define FSP_GRAPHICS_INFO_HOB_GUID \
- EFI_GUID(0x39f62cce, 0x6825, 0x4669, \
- 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: Intel */
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#ifndef _FSP_HEADER_H_
-#define _FSP_HEADER_H_
-
-#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */
-
-struct __packed fsp_header {
- u32 sign; /* 'FSPH' */
- u32 hdr_len; /* header length */
- u8 reserved1[3];
- u8 hdr_rev; /* header rev */
- u32 img_rev; /* image rev */
- char img_id[8]; /* signature string */
- u32 img_size; /* image size */
- u32 img_base; /* image base */
- u32 img_attr; /* image attribute */
- u32 cfg_region_off; /* configuration region offset */
- u32 cfg_region_size; /* configuration region size */
- u32 api_num; /* number of API entries */
- u32 fsp_tempram_init; /* tempram_init offset */
- u32 fsp_init; /* fsp_init offset */
- u32 fsp_notify; /* fsp_notify offset */
- u32 fsp_mem_init; /* fsp_mem_init offset */
- u32 fsp_tempram_exit; /* fsp_tempram_exit offset */
- u32 fsp_silicon_init; /* fsp_silicon_init offset */
-};
-
-#define FSP_HEADER_REVISION_1 1
-#define FSP_HEADER_REVISION_2 2
-
-#define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0)
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: Intel */
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#ifndef __FSP_SUPPORT_H__
-#define __FSP_SUPPORT_H__
-
-#include "fsp_types.h"
-#include "fsp_hob.h"
-#include "fsp_fv.h"
-#include "fsp_ffs.h"
-#include "fsp_api.h"
-#include "fsp_infoheader.h"
-#include "fsp_bootmode.h"
-#include "fsp_azalia.h"
-#include <asm/arch/fsp/fsp_vpd.h>
-#include <asm/arch/fsp/fsp_configs.h>
-
-#define FSP_LOWMEM_BASE 0x100000UL
-#define FSP_HIGHMEM_BASE 0x100000000ULL
-#define UPD_TERMINATOR 0x55AA
-
-
-/**
- * FSP Continuation assembly helper routine
- *
- * This routine jumps to the C version of FSP continuation function
- */
-void asm_continuation(void);
-
-/**
- * FSP initialization complete
- *
- * This is the function that indicates FSP initialization is complete and jumps
- * back to the bootloader with HOB list pointer as the parameter.
- *
- * @hob_list: HOB list pointer
- */
-void fsp_init_done(void *hob_list);
-
-/**
- * FSP Continuation function
- *
- * @status: Always 0
- * @hob_list: HOB list pointer
- *
- * @retval: Never returns
- */
-void fsp_continue(u32 status, void *hob_list);
-
-/**
- * Find FSP header offset in FSP image
- *
- * @retval: the offset of FSP header. If signature is invalid, returns 0.
- */
-struct fsp_header *find_fsp_header(void);
-
-/**
- * FSP initialization wrapper function.
- *
- * @stack_top: bootloader stack top address
- * @boot_mode: boot mode defined in fsp_bootmode.h
- * @nvs_buf: Non-volatile memory buffer pointer
- */
-void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf);
-
-/**
- * FSP notification wrapper function
- *
- * @fsp_hdr: Pointer to FSP information header
- * @phase: FSP initialization phase defined in enum fsp_phase
- *
- * @retval: compatible status code with EFI_STATUS defined in PI spec
- */
-u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
-
-/**
- * This function retrieves the top of usable low memory.
- *
- * @hob_list: A HOB list pointer.
- *
- * @retval: Usable low memory top.
- */
-u32 fsp_get_usable_lowmem_top(const void *hob_list);
-
-/**
- * This function retrieves the top of usable high memory.
- *
- * @hob_list: A HOB list pointer.
- *
- * @retval: Usable high memory top.
- */
-u64 fsp_get_usable_highmem_top(const void *hob_list);
-
-/**
- * This function retrieves a special reserved memory region.
- *
- * @hob_list: A HOB list pointer.
- * @len: A pointer to the GUID HOB data buffer length.
- * If the GUID HOB is located, the length will be updated.
- * @guid: A pointer to the owner guild.
- *
- * @retval: Reserved region start address.
- * 0 if this region does not exist.
- */
-u64 fsp_get_reserved_mem_from_guid(const void *hob_list,
- u64 *len, const efi_guid_t *guid);
-
-/**
- * This function retrieves the FSP reserved normal memory.
- *
- * @hob_list: A HOB list pointer.
- * @len: A pointer to the FSP reserved memory length buffer.
- * If the GUID HOB is located, the length will be updated.
- * @retval: FSP reserved memory base
- * 0 if this region does not exist.
- */
-u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len);
-
-/**
- * This function retrieves the TSEG reserved normal memory.
- *
- * @hob_list: A HOB list pointer.
- * @len: A pointer to the TSEG reserved memory length buffer.
- * If the GUID HOB is located, the length will be updated.
- *
- * @retval NULL: Failed to find the TSEG reserved memory.
- * @retval others: TSEG reserved memory base.
- */
-u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len);
-
-/**
- * This function retrieves FSP Non-volatile Storage HOB buffer and size.
- *
- * @hob_list: A HOB list pointer.
- * @len: A pointer to the NVS data buffer length.
- * If the HOB is located, the length will be updated.
- *
- * @retval NULL: Failed to find the NVS HOB.
- * @retval others: FSP NVS data buffer pointer.
- */
-void *fsp_get_nvs_data(const void *hob_list, u32 *len);
-
-/**
- * This function retrieves Bootloader temporary stack buffer and size.
- *
- * @hob_list: A HOB list pointer.
- * @len: A pointer to the bootloader temporary stack length.
- * If the HOB is located, the length will be updated.
- *
- * @retval NULL: Failed to find the bootloader temporary stack HOB.
- * @retval others: Bootloader temporary stackbuffer pointer.
- */
-void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
-
-/**
- * This function retrieves graphics information.
- *
- * @hob_list: A HOB list pointer.
- * @len: A pointer to the graphics info HOB length.
- * If the HOB is located, the length will be updated.
- *
- * @retval NULL: Failed to find the graphics info HOB.
- * @retval others: A pointer to struct hob_graphics_info.
- */
-void *fsp_get_graphics_info(const void *hob_list, u32 *len);
-
-/**
- * This function overrides the default configurations of FSP.
- *
- * @config: A pointer to the FSP configuration data structure
- * @rt_buf: A pointer to the FSP runtime buffer data structure
- *
- * @return: None
- */
-void update_fsp_configs(struct fsp_config_data *config,
- struct fspinit_rtbuf *rt_buf);
-
-/**
- * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init
- *
- * @return 0 if OK, -EPERM if the FSP gave an error.
- */
-int fsp_init_phase_pci(void);
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: Intel */
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#ifndef __FSP_TYPES_H__
-#define __FSP_TYPES_H__
-
-/**
- * Returns a 16-bit signature built from 2 ASCII characters.
- *
- * This macro returns a 16-bit value built from the two ASCII characters
- * specified by A and B.
- *
- * @A: The first ASCII character.
- * @B: The second ASCII character.
- *
- * @return: A 16-bit value built from the two ASCII characters specified by
- * A and B.
- */
-#define SIGNATURE_16(A, B) ((A) | (B << 8))
-
-/**
- * Returns a 32-bit signature built from 4 ASCII characters.
- *
- * This macro returns a 32-bit value built from the four ASCII characters
- * specified by A, B, C, and D.
- *
- * @A: The first ASCII character.
- * @B: The second ASCII character.
- * @C: The third ASCII character.
- * @D: The fourth ASCII character.
- *
- * @return: A 32-bit value built from the two ASCII characters specified by
- * A, B, C and D.
- */
-#define SIGNATURE_32(A, B, C, D) \
- (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
-
-/**
- * Returns a 64-bit signature built from 8 ASCII characters.
- *
- * This macro returns a 64-bit value built from the eight ASCII characters
- * specified by A, B, C, D, E, F, G,and H.
- *
- * @A: The first ASCII character.
- * @B: The second ASCII character.
- * @C: The third ASCII character.
- * @D: The fourth ASCII character.
- * @E: The fifth ASCII character.
- * @F: The sixth ASCII character.
- * @G: The seventh ASCII character.
- * @H: The eighth ASCII character.
- *
- * @return: A 64-bit value built from the two ASCII characters specified by
- * A, B, C, D, E, F, G and H.
- */
-#define SIGNATURE_64(A, B, C, D, E, F, G, H) \
- (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
-
-#endif
--- /dev/null
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_API_H__
+#define __FSP_API_H__
+
+#include <linux/linkage.h>
+
+/*
+ * FSP common configuration structure.
+ * This needs to be included in the platform-specific struct fsp_config_data.
+ */
+struct fsp_cfg_common {
+ struct fsp_header *fsp_hdr;
+ u32 stack_top;
+ u32 boot_mode;
+};
+
+/*
+ * FspInit continuation function prototype.
+ * Control will be returned to this callback function after FspInit API call.
+ */
+typedef void (*fsp_continuation_f)(u32 status, void *hob_list);
+
+struct fsp_init_params {
+ /* Non-volatile storage buffer pointer */
+ void *nvs_buf;
+ /* Runtime buffer pointer */
+ void *rt_buf;
+ /* Continuation function address */
+ fsp_continuation_f continuation;
+};
+
+struct common_buf {
+ /*
+ * Stack top pointer used by the bootloader. The new stack frame will be
+ * set up at this location after FspInit API call.
+ */
+ u32 stack_top;
+ u32 boot_mode; /* Current system boot mode */
+ void *upd_data; /* User platform configuraiton data region */
+ u32 tolum_size; /* Top of low usable memory size (FSP 1.1) */
+ u32 reserved[6]; /* Reserved */
+};
+
+enum fsp_phase {
+ /* Notification code for post PCI enuermation */
+ INIT_PHASE_PCI = 0x20,
+ /* Notification code before transfering control to the payload */
+ INIT_PHASE_BOOT = 0x40
+};
+
+struct fsp_notify_params {
+ /* Notification phase used for NotifyPhase API */
+ enum fsp_phase phase;
+};
+
+/* FspInit API function prototype */
+typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params);
+
+/* FspNotify API function prototype */
+typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params);
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Google, Inc
+ */
+
+#ifndef _FSP_AZALIA_H_
+#define _FSP_AZALIA_H_
+
+struct __packed azalia_verb_table_header {
+ u32 vendor_device_id;
+ u16 sub_system_id;
+ u8 revision_id; /* 0xff applies to all steppings */
+ u8 front_panel_support;
+ u16 number_of_rear_jacks;
+ u16 number_of_front_jacks;
+};
+
+struct __packed azalia_verb_table {
+ struct azalia_verb_table_header header;
+ const u32 *data;
+};
+
+struct __packed azalia_config {
+ u8 pme_enable:1;
+ u8 docking_supported:1;
+ u8 docking_attached:1;
+ u8 hdmi_codec_enable:1;
+ u8 azalia_v_ci_enable:1;
+ u8 rsvdbits:3;
+ /* number of verb tables provided by platform */
+ u8 verb_table_num;
+ const struct azalia_verb_table *verb_table;
+ /* delay timer after azalia reset */
+ u16 reset_wait_timer_ms;
+};
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_BOOT_MODE_H__
+#define __FSP_BOOT_MODE_H__
+
+/* 0x21 - 0xf..f are reserved */
+#define BOOT_FULL_CONFIG 0x00
+#define BOOT_MINIMAL_CONFIG 0x01
+#define BOOT_NO_CONFIG_CHANGES 0x02
+#define BOOT_FULL_CONFIG_PLUS_DIAG 0x03
+#define BOOT_DEFAULT_SETTINGS 0x04
+#define BOOT_ON_S4_RESUME 0x05
+#define BOOT_ON_S5_RESUME 0x06
+#define BOOT_ON_S2_RESUME 0x10
+#define BOOT_ON_S3_RESUME 0x11
+#define BOOT_ON_FLASH_UPDATE 0x12
+#define BOOT_IN_RECOVERY_MODE 0x20
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_FFS_H__
+#define __FSP_FFS_H__
+
+/* Used to verify the integrity of the file */
+union __packed ffs_integrity {
+ struct {
+ /*
+ * The IntegrityCheck.checksum.header field is an 8-bit
+ * checksum of the file header. The State and
+ * IntegrityCheck.checksum.file fields are assumed to be zero
+ * and the checksum is calculated such that the entire header
+ * sums to zero.
+ */
+ u8 header;
+ /*
+ * If the FFS_ATTRIB_CHECKSUM (see definition below) bit of
+ * the Attributes field is set to one, the
+ * IntegrityCheck.checksum.file field is an 8-bit checksum of
+ * the file data. If the FFS_ATTRIB_CHECKSUM bit of the
+ * Attributes field is cleared to zero, the
+ * IntegrityCheck.checksum.file field must be initialized with
+ * a value of 0xAA. The IntegrityCheck.checksum.file field is
+ * valid any time the EFI_FILE_DATA_VALID bit is set in the
+ * State field.
+ */
+ u8 file;
+ } checksum;
+
+ /* This is the full 16 bits of the IntegrityCheck field */
+ u16 checksum16;
+};
+
+/*
+ * Each file begins with the header that describe the
+ * contents and state of the files.
+ */
+struct __packed ffs_file_header {
+ /*
+ * This GUID is the file name.
+ * It is used to uniquely identify the file.
+ */
+ efi_guid_t name;
+ /* Used to verify the integrity of the file */
+ union ffs_integrity integrity;
+ /* Identifies the type of file */
+ u8 type;
+ /* Declares various file attribute bits */
+ u8 attr;
+ /* The length of the file in bytes, including the FFS header */
+ u8 size[3];
+ /*
+ * Used to track the state of the file throughout the life of
+ * the file from creation to deletion.
+ */
+ u8 state;
+};
+
+struct __packed ffs_file_header2 {
+ /*
+ * This GUID is the file name. It is used to uniquely identify the file.
+ * There may be only one instance of a file with the file name GUID of
+ * Name in any given firmware volume, except if the file type is
+ * EFI_FV_FILE_TYPE_FFS_PAD.
+ */
+ efi_guid_t name;
+ /* Used to verify the integrity of the file */
+ union ffs_integrity integrity;
+ /* Identifies the type of file */
+ u8 type;
+ /* Declares various file attribute bits */
+ u8 attr;
+ /*
+ * The length of the file in bytes, including the FFS header.
+ * The length of the file data is either
+ * (size - sizeof(struct ffs_file_header)). This calculation means a
+ * zero-length file has a size of 24 bytes, which is
+ * sizeof(struct ffs_file_header). Size is not required to be a
+ * multiple of 8 bytes. Given a file F, the next file header is located
+ * at the next 8-byte aligned firmware volume offset following the last
+ * byte of the file F.
+ */
+ u8 size[3];
+ /*
+ * Used to track the state of the file throughout the life of
+ * the file from creation to deletion.
+ */
+ u8 state;
+ /*
+ * If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists
+ * and size must be set to zero.
+ * If FFS_ATTRIB_LARGE_FILE is not set then
+ * struct ffs_file_header is used.
+ */
+ u32 ext_size;
+};
+
+/*
+ * Pseudo type. It is used as a wild card when retrieving sections.
+ * The section type EFI_SECTION_ALL matches all section types.
+ */
+#define EFI_SECTION_ALL 0x00
+
+/* Encapsulation section Type values */
+#define EFI_SECTION_COMPRESSION 0x01
+#define EFI_SECTION_GUID_DEFINED 0x02
+#define EFI_SECTION_DISPOSABLE 0x03
+
+/* Leaf section Type values */
+#define EFI_SECTION_PE32 0x10
+#define EFI_SECTION_PIC 0x11
+#define EFI_SECTION_TE 0x12
+#define EFI_SECTION_DXE_DEPEX 0x13
+#define EFI_SECTION_VERSION 0x14
+#define EFI_SECTION_USER_INTERFACE 0x15
+#define EFI_SECTION_COMPATIBILITY16 0x16
+#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
+#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
+#define EFI_SECTION_RAW 0x19
+#define EFI_SECTION_PEI_DEPEX 0x1B
+#define EFI_SECTION_SMM_DEPEX 0x1C
+
+/* Common section header */
+struct __packed raw_section {
+ /*
+ * A 24-bit unsigned integer that contains the total size of
+ * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
+ */
+ u8 size[3];
+ u8 type;
+};
+
+struct __packed raw_section2 {
+ /*
+ * A 24-bit unsigned integer that contains the total size of
+ * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
+ */
+ u8 size[3];
+ u8 type;
+ /*
+ * If size is 0xFFFFFF, then ext_size contains the size of
+ * the section. If size is not equal to 0xFFFFFF, then this
+ * field does not exist.
+ */
+ u32 ext_size;
+};
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_FV___
+#define __FSP_FV___
+
+/* Value of EFI_FV_FILE_ATTRIBUTES */
+#define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F
+#define EFI_FV_FILE_ATTR_FIXED 0x00000100
+#define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200
+
+/* Attributes bit definitions */
+#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
+#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
+#define EFI_FVB2_READ_STATUS 0x00000004
+#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
+#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
+#define EFI_FVB2_WRITE_STATUS 0x00000020
+#define EFI_FVB2_LOCK_CAP 0x00000040
+#define EFI_FVB2_LOCK_STATUS 0x00000080
+#define EFI_FVB2_STICKY_WRITE 0x00000200
+#define EFI_FVB2_MEMORY_MAPPED 0x00000400
+#define EFI_FVB2_ERASE_POLARITY 0x00000800
+#define EFI_FVB2_READ_LOCK_CAP 0x00001000
+#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
+#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
+#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
+#define EFI_FVB2_ALIGNMENT 0x001F0000
+#define EFI_FVB2_ALIGNMENT_1 0x00000000
+#define EFI_FVB2_ALIGNMENT_2 0x00010000
+#define EFI_FVB2_ALIGNMENT_4 0x00020000
+#define EFI_FVB2_ALIGNMENT_8 0x00030000
+#define EFI_FVB2_ALIGNMENT_16 0x00040000
+#define EFI_FVB2_ALIGNMENT_32 0x00050000
+#define EFI_FVB2_ALIGNMENT_64 0x00060000
+#define EFI_FVB2_ALIGNMENT_128 0x00070000
+#define EFI_FVB2_ALIGNMENT_256 0x00080000
+#define EFI_FVB2_ALIGNMENT_512 0x00090000
+#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
+#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
+#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
+#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
+#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
+#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
+#define EFI_FVB2_ALIGNMENT_64K 0x00100000
+#define EFI_FVB2_ALIGNMENT_128K 0x00110000
+#define EFI_FVB2_ALIGNMENT_256K 0x00120000
+#define EFI_FVB2_ALIGNMENT_512K 0x00130000
+#define EFI_FVB2_ALIGNMENT_1M 0x00140000
+#define EFI_FVB2_ALIGNMENT_2M 0x00150000
+#define EFI_FVB2_ALIGNMENT_4M 0x00160000
+#define EFI_FVB2_ALIGNMENT_8M 0x00170000
+#define EFI_FVB2_ALIGNMENT_16M 0x00180000
+#define EFI_FVB2_ALIGNMENT_32M 0x00190000
+#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
+#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
+#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
+#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
+#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
+#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
+
+struct fv_blkmap_entry {
+ /* The number of sequential blocks which are of the same size */
+ u32 num_blocks;
+ /* The size of the blocks */
+ u32 length;
+};
+
+/* Describes the features and layout of the firmware volume */
+struct fv_header {
+ /*
+ * The first 16 bytes are reserved to allow for the reset vector of
+ * processors whose reset vector is at address 0.
+ */
+ u8 zero_vec[16];
+ /*
+ * Declares the file system with which the firmware volume
+ * is formatted.
+ */
+ efi_guid_t fs_guid;
+ /*
+ * Length in bytes of the complete firmware volume, including
+ * the header.
+ */
+ u64 fv_len;
+ /* Set to EFI_FVH_SIGNATURE */
+ u32 sign;
+ /*
+ * Declares capabilities and power-on defaults for the firmware
+ * volume.
+ */
+ u32 attr;
+ /* Length in bytes of the complete firmware volume header */
+ u16 hdr_len;
+ /*
+ * A 16-bit checksum of the firmware volume header.
+ * A valid header sums to zero.
+ */
+ u16 checksum;
+ /*
+ * Offset, relative to the start of the header, of the extended
+ * header (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is
+ * no extended header.
+ */
+ u16 ext_hdr_off;
+ /* This field must always be set to zero */
+ u8 reserved[1];
+ /*
+ * Set to 2. Future versions of this specification may define new
+ * header fields and will increment the Revision field accordingly.
+ */
+ u8 rev;
+ /*
+ * An array of run-length encoded FvBlockMapEntry structures.
+ * The array is terminated with an entry of {0,0}.
+ */
+ struct fv_blkmap_entry block_map[1];
+};
+
+#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H')
+
+/* Firmware Volume Header Revision definition */
+#define EFI_FVH_REVISION 0x02
+
+/* Extension header pointed by ExtHeaderOffset of volume header */
+struct fv_ext_header {
+ /* firmware volume name */
+ efi_guid_t fv_name;
+ /* Size of the rest of the extension header including this structure */
+ u32 ext_hdr_size;
+};
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_HOB_H__
+#define __FSP_HOB_H__
+
+#include <asm/hob.h>
+
+enum pixel_format {
+ pixel_rgbx_8bpc, /* RGB 8 bit per color */
+ pixel_bgrx_8bpc, /* BGR 8 bit per color */
+ pixel_bitmask,
+};
+
+struct __packed hob_graphics_info {
+ phys_addr_t fb_base; /* framebuffer base address */
+ u32 fb_size; /* framebuffer size */
+ u32 version;
+ u32 width;
+ u32 height;
+ enum pixel_format pixel_format;
+ u32 red_mask;
+ u32 green_mask;
+ u32 blue_mask;
+ u32 reserved_mask;
+ u32 pixels_per_scanline;
+};
+
+/* FSP specific GUID HOB definitions */
+#define FSP_GUID_DATA1 0x912740be
+#define FSP_GUID_DATA2 0x2284
+#define FSP_GUID_DATA3 0x4734
+#define FSP_GUID_DATA4_0 0xb9
+#define FSP_GUID_DATA4_1 0x71
+#define FSP_GUID_DATA4_2 0x84
+#define FSP_GUID_DATA4_3 0xb0
+#define FSP_GUID_DATA4_4 0x27
+#define FSP_GUID_DATA4_5 0x35
+#define FSP_GUID_DATA4_6 0x3f
+#define FSP_GUID_DATA4_7 0x0c
+
+#define FSP_GUID_BYTE0 0xbe
+#define FSP_GUID_BYTE1 0x40
+#define FSP_GUID_BYTE2 0x27
+#define FSP_GUID_BYTE3 0x91
+#define FSP_GUID_BYTE4 0x84
+#define FSP_GUID_BYTE5 0x22
+#define FSP_GUID_BYTE6 0x34
+#define FSP_GUID_BYTE7 0x47
+#define FSP_GUID_BYTE8 FSP_GUID_DATA4_0
+#define FSP_GUID_BYTE9 FSP_GUID_DATA4_1
+#define FSP_GUID_BYTE10 FSP_GUID_DATA4_2
+#define FSP_GUID_BYTE11 FSP_GUID_DATA4_3
+#define FSP_GUID_BYTE12 FSP_GUID_DATA4_4
+#define FSP_GUID_BYTE13 FSP_GUID_DATA4_5
+#define FSP_GUID_BYTE14 FSP_GUID_DATA4_6
+#define FSP_GUID_BYTE15 FSP_GUID_DATA4_7
+
+#define FSP_HEADER_GUID \
+ EFI_GUID(FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \
+ FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \
+ FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \
+ FSP_GUID_DATA4_6, FSP_GUID_DATA4_7)
+
+#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
+ EFI_GUID(0x721acf02, 0x4d77, 0x4c2a, \
+ 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0)
+
+#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \
+ EFI_GUID(0xbbcff46c, 0xc8d3, 0x4113, \
+ 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e)
+
+#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \
+ EFI_GUID(0x69a79759, 0x1373, 0x4367, \
+ 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e)
+
+#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
+ EFI_GUID(0xd038747c, 0xd00c, 0x4980, \
+ 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55)
+
+#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \
+ EFI_GUID(0x9c7c3aa7, 0x5332, 0x4917, \
+ 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07)
+
+/* The following GUIDs are newly introduced in FSP spec 1.1 */
+
+#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \
+ EFI_GUID(0x73ff4f56, 0xaa8e, 0x4451, \
+ 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44)
+
+#define FSP_GRAPHICS_INFO_HOB_GUID \
+ EFI_GUID(0x39f62cce, 0x6825, 0x4669, \
+ 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07)
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _FSP_HEADER_H_
+#define _FSP_HEADER_H_
+
+#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */
+
+struct __packed fsp_header {
+ u32 sign; /* 'FSPH' */
+ u32 hdr_len; /* header length */
+ u8 reserved1[3];
+ u8 hdr_rev; /* header rev */
+ u32 img_rev; /* image rev */
+ char img_id[8]; /* signature string */
+ u32 img_size; /* image size */
+ u32 img_base; /* image base */
+ u32 img_attr; /* image attribute */
+ u32 cfg_region_off; /* configuration region offset */
+ u32 cfg_region_size; /* configuration region size */
+ u32 api_num; /* number of API entries */
+ u32 fsp_tempram_init; /* tempram_init offset */
+ u32 fsp_init; /* fsp_init offset */
+ u32 fsp_notify; /* fsp_notify offset */
+ u32 fsp_mem_init; /* fsp_mem_init offset */
+ u32 fsp_tempram_exit; /* fsp_tempram_exit offset */
+ u32 fsp_silicon_init; /* fsp_silicon_init offset */
+};
+
+#define FSP_HEADER_REVISION_1 1
+#define FSP_HEADER_REVISION_2 2
+
+#define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0)
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_SUPPORT_H__
+#define __FSP_SUPPORT_H__
+
+#include "fsp_types.h"
+#include "fsp_hob.h"
+#include "fsp_fv.h"
+#include "fsp_ffs.h"
+#include "fsp_api.h"
+#include "fsp_infoheader.h"
+#include "fsp_bootmode.h"
+#include "fsp_azalia.h"
+#include <asm/arch/fsp/fsp_vpd.h>
+#include <asm/arch/fsp/fsp_configs.h>
+
+#define FSP_LOWMEM_BASE 0x100000UL
+#define FSP_HIGHMEM_BASE 0x100000000ULL
+#define UPD_TERMINATOR 0x55AA
+
+
+/**
+ * FSP Continuation assembly helper routine
+ *
+ * This routine jumps to the C version of FSP continuation function
+ */
+void asm_continuation(void);
+
+/**
+ * FSP initialization complete
+ *
+ * This is the function that indicates FSP initialization is complete and jumps
+ * back to the bootloader with HOB list pointer as the parameter.
+ *
+ * @hob_list: HOB list pointer
+ */
+void fsp_init_done(void *hob_list);
+
+/**
+ * FSP Continuation function
+ *
+ * @status: Always 0
+ * @hob_list: HOB list pointer
+ *
+ * @retval: Never returns
+ */
+void fsp_continue(u32 status, void *hob_list);
+
+/**
+ * Find FSP header offset in FSP image
+ *
+ * @retval: the offset of FSP header. If signature is invalid, returns 0.
+ */
+struct fsp_header *find_fsp_header(void);
+
+/**
+ * FSP initialization wrapper function.
+ *
+ * @stack_top: bootloader stack top address
+ * @boot_mode: boot mode defined in fsp_bootmode.h
+ * @nvs_buf: Non-volatile memory buffer pointer
+ */
+void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf);
+
+/**
+ * FSP notification wrapper function
+ *
+ * @fsp_hdr: Pointer to FSP information header
+ * @phase: FSP initialization phase defined in enum fsp_phase
+ *
+ * @retval: compatible status code with EFI_STATUS defined in PI spec
+ */
+u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
+
+/**
+ * This function retrieves the top of usable low memory.
+ *
+ * @hob_list: A HOB list pointer.
+ *
+ * @retval: Usable low memory top.
+ */
+u32 fsp_get_usable_lowmem_top(const void *hob_list);
+
+/**
+ * This function retrieves the top of usable high memory.
+ *
+ * @hob_list: A HOB list pointer.
+ *
+ * @retval: Usable high memory top.
+ */
+u64 fsp_get_usable_highmem_top(const void *hob_list);
+
+/**
+ * This function retrieves a special reserved memory region.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the GUID HOB data buffer length.
+ * If the GUID HOB is located, the length will be updated.
+ * @guid: A pointer to the owner guild.
+ *
+ * @retval: Reserved region start address.
+ * 0 if this region does not exist.
+ */
+u64 fsp_get_reserved_mem_from_guid(const void *hob_list,
+ u64 *len, const efi_guid_t *guid);
+
+/**
+ * This function retrieves the FSP reserved normal memory.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the FSP reserved memory length buffer.
+ * If the GUID HOB is located, the length will be updated.
+ * @retval: FSP reserved memory base
+ * 0 if this region does not exist.
+ */
+u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len);
+
+/**
+ * This function retrieves the TSEG reserved normal memory.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the TSEG reserved memory length buffer.
+ * If the GUID HOB is located, the length will be updated.
+ *
+ * @retval NULL: Failed to find the TSEG reserved memory.
+ * @retval others: TSEG reserved memory base.
+ */
+u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len);
+
+/**
+ * This function retrieves FSP Non-volatile Storage HOB buffer and size.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the NVS data buffer length.
+ * If the HOB is located, the length will be updated.
+ *
+ * @retval NULL: Failed to find the NVS HOB.
+ * @retval others: FSP NVS data buffer pointer.
+ */
+void *fsp_get_nvs_data(const void *hob_list, u32 *len);
+
+/**
+ * This function retrieves Bootloader temporary stack buffer and size.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the bootloader temporary stack length.
+ * If the HOB is located, the length will be updated.
+ *
+ * @retval NULL: Failed to find the bootloader temporary stack HOB.
+ * @retval others: Bootloader temporary stackbuffer pointer.
+ */
+void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
+
+/**
+ * This function retrieves graphics information.
+ *
+ * @hob_list: A HOB list pointer.
+ * @len: A pointer to the graphics info HOB length.
+ * If the HOB is located, the length will be updated.
+ *
+ * @retval NULL: Failed to find the graphics info HOB.
+ * @retval others: A pointer to struct hob_graphics_info.
+ */
+void *fsp_get_graphics_info(const void *hob_list, u32 *len);
+
+/**
+ * This function overrides the default configurations of FSP.
+ *
+ * @config: A pointer to the FSP configuration data structure
+ * @rt_buf: A pointer to the FSP runtime buffer data structure
+ *
+ * @return: None
+ */
+void update_fsp_configs(struct fsp_config_data *config,
+ struct fspinit_rtbuf *rt_buf);
+
+/**
+ * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init
+ *
+ * @return 0 if OK, -EPERM if the FSP gave an error.
+ */
+int fsp_init_phase_pci(void);
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_TYPES_H__
+#define __FSP_TYPES_H__
+
+/**
+ * Returns a 16-bit signature built from 2 ASCII characters.
+ *
+ * This macro returns a 16-bit value built from the two ASCII characters
+ * specified by A and B.
+ *
+ * @A: The first ASCII character.
+ * @B: The second ASCII character.
+ *
+ * @return: A 16-bit value built from the two ASCII characters specified by
+ * A and B.
+ */
+#define SIGNATURE_16(A, B) ((A) | (B << 8))
+
+/**
+ * Returns a 32-bit signature built from 4 ASCII characters.
+ *
+ * This macro returns a 32-bit value built from the four ASCII characters
+ * specified by A, B, C, and D.
+ *
+ * @A: The first ASCII character.
+ * @B: The second ASCII character.
+ * @C: The third ASCII character.
+ * @D: The fourth ASCII character.
+ *
+ * @return: A 32-bit value built from the two ASCII characters specified by
+ * A, B, C and D.
+ */
+#define SIGNATURE_32(A, B, C, D) \
+ (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
+
+/**
+ * Returns a 64-bit signature built from 8 ASCII characters.
+ *
+ * This macro returns a 64-bit value built from the eight ASCII characters
+ * specified by A, B, C, D, E, F, G,and H.
+ *
+ * @A: The first ASCII character.
+ * @B: The second ASCII character.
+ * @C: The third ASCII character.
+ * @D: The fourth ASCII character.
+ * @E: The fifth ASCII character.
+ * @F: The sixth ASCII character.
+ * @G: The seventh ASCII character.
+ * @H: The eighth ASCII character.
+ *
+ * @return: A 64-bit value built from the two ASCII characters specified by
+ * A, B, C, D, E, F, G and H.
+ */
+#define SIGNATURE_64(A, B, C, D, E, F, G, H) \
+ (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
+
+#endif
/* arch/x86/lib/... */
int video_bios_init(void);
-/* arch/x86/lib/fsp/... */
+/* arch/x86/lib/fsp1,2/... */
/**
* fsp_save_s3_stack() - save stack address to CMOS for next S3 boot
obj-$(CONFIG_CMD_ZBOOT) += zimage.o
endif
obj-$(CONFIG_USE_HOB) += hob.o
-obj-$(CONFIG_HAVE_FSP) += fsp/
+obj-$(CONFIG_FSP_VERSION1) += fsp1/
+obj-$(CONFIG_FSP_VERSION2) += fsp2/
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TPL_BUILD
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015 Google, Inc
-
-obj-y += fsp_car.o
-obj-y += fsp_common.o
-obj-y += fsp_dram.o
-obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o
-obj-y += fsp_support.o
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <config.h>
-#include <asm/post.h>
-
-.globl car_init
-car_init:
- /*
- * Note: ebp holds the BIST value (built-in self test) so far, but ebp
- * will be destroyed through the FSP call, thus we have to test the
- * BIST value here before we call into FSP.
- */
- test %ebp, %ebp
- jz car_init_start
- post_code(POST_BIST_FAILURE)
- jmp die
-
-car_init_start:
- post_code(POST_CAR_START)
- lea find_fsp_header_romstack, %esp
- jmp find_fsp_header
-
-find_fsp_header_ret:
- /* EAX points to FSP_INFO_HEADER */
- mov %eax, %ebp
-
- /* sanity test */
- cmp $CONFIG_FSP_ADDR, %eax
- jb die
-
- /* calculate TempRamInitEntry address */
- mov 0x30(%ebp), %eax
- add 0x1c(%ebp), %eax
-
- /* call FSP TempRamInitEntry to setup temporary stack */
- lea temp_ram_init_romstack, %esp
- jmp *%eax
-
-temp_ram_init_ret:
- addl $4, %esp
- cmp $0, %eax
- jnz car_init_fail
-
- post_code(POST_CAR_CPU_CACHE)
-
- /*
- * The FSP TempRamInit initializes the ecx and edx registers to
- * point to a temporary but writable memory range (Cache-As-RAM).
- * ecx: the start of this temporary memory range,
- * edx: the end of this range.
- */
-
- /* stack grows down from top of CAR */
- movl %edx, %esp
- subl $4, %esp
-
- xor %esi, %esi
- jmp car_init_done
-
-.global fsp_init_done
-fsp_init_done:
- /*
- * We come here from fsp_continue() with eax pointing to the HOB list.
- * Save eax to esi temporarily.
- */
- movl %eax, %esi
-
-car_init_done:
- /*
- * Re-initialize the ebp (BIST) to zero, as we already reach here
- * which means we passed BIST testing before.
- */
- xorl %ebp, %ebp
- jmp car_init_ret
-
-car_init_fail:
- post_code(POST_CAR_FAILURE)
-
-die:
- hlt
- jmp die
- hlt
-
- /*
- * The function call before CAR initialization is tricky. It cannot
- * be called using the 'call' instruction but only the 'jmp' with
- * the help of a handcrafted stack in the ROM. The stack needs to
- * contain the function return address as well as the parameters.
- */
- .balign 4
-find_fsp_header_romstack:
- .long find_fsp_header_ret
-
- .balign 4
-temp_ram_init_romstack:
- .long temp_ram_init_ret
- .long temp_ram_init_params
-temp_ram_init_params:
-_dt_ucode_base_size:
- /* These next two fields are filled in by binman */
-.globl ucode_base
-ucode_base: /* Declared in microcode.h */
- .long 0 /* microcode base */
-.globl ucode_size
-ucode_size: /* Declared in microcode.h */
- .long 0 /* microcode size */
- .long CONFIG_SYS_MONITOR_BASE /* code region base */
- .long CONFIG_SYS_MONITOR_LEN /* code region size */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <rtc.h>
-#include <asm/acpi_s3.h>
-#include <asm/cmos_layout.h>
-#include <asm/early_cmos.h>
-#include <asm/io.h>
-#include <asm/mrccache.h>
-#include <asm/post.h>
-#include <asm/processor.h>
-#include <asm/fsp/fsp_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkcpu(void)
-{
- return 0;
-}
-
-int print_cpuinfo(void)
-{
- post_code(POST_CPU_INFO);
- return default_print_cpuinfo();
-}
-
-int fsp_init_phase_pci(void)
-{
- u32 status;
-
- /* call into FspNotify */
- debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
- status = fsp_notify(NULL, INIT_PHASE_PCI);
- if (status)
- debug("fail, error code %x\n", status);
- else
- debug("OK\n");
-
- return status ? -EPERM : 0;
-}
-
-void board_final_cleanup(void)
-{
- u32 status;
-
- /* call into FspNotify */
- debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
- status = fsp_notify(NULL, INIT_PHASE_BOOT);
- if (status)
- debug("fail, error code %x\n", status);
- else
- debug("OK\n");
-
- return;
-}
-
-static __maybe_unused void *fsp_prepare_mrc_cache(void)
-{
- struct mrc_data_container *cache;
- struct mrc_region entry;
- int ret;
-
- ret = mrccache_get_region(NULL, &entry);
- if (ret)
- return NULL;
-
- cache = mrccache_find_current(&entry);
- if (!cache)
- return NULL;
-
- debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
- cache->data, cache->data_size, cache->checksum);
-
- return cache->data;
-}
-
-#ifdef CONFIG_HAVE_ACPI_RESUME
-int fsp_save_s3_stack(void)
-{
- struct udevice *dev;
- int ret;
-
- if (gd->arch.prev_sleep_state == ACPI_S3)
- return 0;
-
- ret = uclass_get_device(UCLASS_RTC, 0, &dev);
- if (ret) {
- debug("Cannot find RTC: err=%d\n", ret);
- return -ENODEV;
- }
-
- /* Save the stack address to CMOS */
- ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
- if (ret) {
- debug("Save stack address to CMOS: err=%d\n", ret);
- return -EIO;
- }
-
- return 0;
-}
-#endif
-
-int arch_fsp_init(void)
-{
- void *nvs;
- int stack = CONFIG_FSP_TEMP_RAM_ADDR;
- int boot_mode = BOOT_FULL_CONFIG;
-#ifdef CONFIG_HAVE_ACPI_RESUME
- int prev_sleep_state = chipset_prev_sleep_state();
- gd->arch.prev_sleep_state = prev_sleep_state;
-#endif
-
- if (!gd->arch.hob_list) {
-#ifdef CONFIG_ENABLE_MRC_CACHE
- nvs = fsp_prepare_mrc_cache();
-#else
- nvs = NULL;
-#endif
-
-#ifdef CONFIG_HAVE_ACPI_RESUME
- if (prev_sleep_state == ACPI_S3) {
- if (nvs == NULL) {
- /* If waking from S3 and no cache then */
- debug("No MRC cache found in S3 resume path\n");
- post_code(POST_RESUME_FAILURE);
- /* Clear Sleep Type */
- chipset_clear_sleep_state();
- /* Reboot */
- debug("Rebooting..\n");
- outb(SYS_RST | RST_CPU, IO_PORT_RESET);
- /* Should not reach here.. */
- panic("Reboot System");
- }
-
- /*
- * DM is not available yet at this point, hence call
- * CMOS access library which does not depend on DM.
- */
- stack = cmos_read32(CMOS_FSP_STACK_ADDR);
- boot_mode = BOOT_ON_S3_RESUME;
- }
-#endif
- /*
- * The first time we enter here, call fsp_init().
- * Note the execution does not return to this function,
- * instead it jumps to fsp_continue().
- */
- fsp_init(stack, boot_mode, nvs);
- } else {
- /*
- * The second time we enter here, adjust the size of malloc()
- * pool before relocation. Given gd->malloc_base was adjusted
- * after the call to board_init_f_init_reserve() in arch/x86/
- * cpu/start.S, we should fix up gd->malloc_limit here.
- */
- gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
- }
-
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <common.h>
-#include <asm/fsp/fsp_support.h>
-#include <asm/e820.h>
-#include <asm/mrccache.h>
-#include <asm/post.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- phys_size_t ram_size = 0;
- const struct hob_header *hdr;
- struct hob_res_desc *res_desc;
-
- hdr = gd->arch.hob_list;
- while (!end_of_hob(hdr)) {
- if (hdr->type == HOB_TYPE_RES_DESC) {
- res_desc = (struct hob_res_desc *)hdr;
- if (res_desc->type == RES_SYS_MEM ||
- res_desc->type == RES_MEM_RESERVED) {
- ram_size += res_desc->len;
- }
- }
- hdr = get_next_hob(hdr);
- }
-
- gd->ram_size = ram_size;
- post_code(POST_DRAM);
-
-#ifdef CONFIG_ENABLE_MRC_CACHE
- gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list,
- &gd->arch.mrc_output_len);
-#endif
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = 0;
- gd->bd->bi_dram[0].size = gd->ram_size;
-
- return 0;
-}
-
-/*
- * This function looks for the highest region of memory lower than 4GB which
- * has enough space for U-Boot where U-Boot is aligned on a page boundary.
- * It overrides the default implementation found elsewhere which simply
- * picks the end of ram, wherever that may be. The location of the stack,
- * the relocation address, and how far U-Boot is moved by relocation are
- * set in the global data structure.
- */
-ulong board_get_usable_ram_top(ulong total_size)
-{
- return fsp_get_usable_lowmem_top(gd->arch.hob_list);
-}
-
-unsigned int install_e820_map(unsigned int max_entries,
- struct e820_entry *entries)
-{
- unsigned int num_entries = 0;
- const struct hob_header *hdr;
- struct hob_res_desc *res_desc;
-
- hdr = gd->arch.hob_list;
-
- while (!end_of_hob(hdr)) {
- if (hdr->type == HOB_TYPE_RES_DESC) {
- res_desc = (struct hob_res_desc *)hdr;
- entries[num_entries].addr = res_desc->phys_start;
- entries[num_entries].size = res_desc->len;
-
- if (res_desc->type == RES_SYS_MEM)
- entries[num_entries].type = E820_RAM;
- else if (res_desc->type == RES_MEM_RESERVED)
- entries[num_entries].type = E820_RESERVED;
-
- num_entries++;
- }
- hdr = get_next_hob(hdr);
- }
-
- /* Mark PCIe ECAM address range as reserved */
- entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
- entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
- entries[num_entries].type = E820_RESERVED;
- num_entries++;
-
-#ifdef CONFIG_HAVE_ACPI_RESUME
- /*
- * Everything between U-Boot's stack and ram top needs to be
- * reserved in order for ACPI S3 resume to work.
- */
- entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
- entries[num_entries].size = gd->ram_top - gd->start_addr_sp + \
- CONFIG_STACK_SIZE;
- entries[num_entries].type = E820_RESERVED;
- num_entries++;
-#endif
-
- return num_entries;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <vbe.h>
-#include <video.h>
-#include <asm/fsp/fsp_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct pixel {
- u8 pos;
- u8 size;
-};
-
-static const struct fsp_framebuffer {
- struct pixel red;
- struct pixel green;
- struct pixel blue;
- struct pixel rsvd;
-} fsp_framebuffer_format_map[] = {
- [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
- [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
-};
-
-static int save_vesa_mode(struct vesa_mode_info *vesa)
-{
- const struct hob_graphics_info *ginfo;
- const struct fsp_framebuffer *fbinfo;
-
- ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
-
- /*
- * If there is no graphics info structure, bail out and keep
- * running on the serial console.
- *
- * Note: on some platforms (eg: Braswell), the FSP will not produce
- * the graphics info HOB unless you plug some cables to the display
- * interface (eg: HDMI) on the board.
- */
- if (!ginfo) {
- debug("FSP graphics hand-off block not found\n");
- return -ENXIO;
- }
-
- vesa->x_resolution = ginfo->width;
- vesa->y_resolution = ginfo->height;
- vesa->bits_per_pixel = 32;
- vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
- vesa->phys_base_ptr = ginfo->fb_base;
-
- if (ginfo->pixel_format >= pixel_bitmask) {
- debug("FSP set unknown framebuffer format: %d\n",
- ginfo->pixel_format);
- return -EINVAL;
- }
- fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format];
- vesa->red_mask_size = fbinfo->red.size;
- vesa->red_mask_pos = fbinfo->red.pos;
- vesa->green_mask_size = fbinfo->green.size;
- vesa->green_mask_pos = fbinfo->green.pos;
- vesa->blue_mask_size = fbinfo->blue.size;
- vesa->blue_mask_pos = fbinfo->blue.pos;
- vesa->reserved_mask_size = fbinfo->rsvd.size;
- vesa->reserved_mask_pos = fbinfo->rsvd.pos;
-
- return 0;
-}
-
-static int fsp_video_probe(struct udevice *dev)
-{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
- struct video_priv *uc_priv = dev_get_uclass_priv(dev);
- struct vesa_mode_info *vesa = &mode_info.vesa;
- int ret;
-
- printf("Video: ");
-
- /* Initialize vesa_mode_info structure */
- ret = save_vesa_mode(vesa);
- if (ret)
- goto err;
-
- /*
- * The framebuffer base address in the FSP graphics info HOB reflects
- * the value assigned by the FSP. After PCI enumeration the framebuffer
- * base address may be relocated. Let's get the updated one from device.
- *
- * For IGD, it seems to be always on BAR2.
- */
- vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
-
- ret = vbe_setup_video_priv(vesa, uc_priv, plat);
- if (ret)
- goto err;
-
- printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
- vesa->bits_per_pixel);
-
- return 0;
-
-err:
- printf("No video mode configured in FSP!\n");
- return ret;
-}
-
-static const struct udevice_id fsp_video_ids[] = {
- { .compatible = "fsp-fb" },
- { }
-};
-
-U_BOOT_DRIVER(fsp_video) = {
- .name = "fsp_video",
- .id = UCLASS_VIDEO,
- .of_match = fsp_video_ids,
- .probe = fsp_video_probe,
-};
-
-static struct pci_device_id fsp_video_supported[] = {
- { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) },
- { },
-};
-
-U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported);
+++ /dev/null
-// SPDX-License-Identifier: Intel
-/*
- * Copyright (C) 2013, Intel Corporation
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <common.h>
-#include <asm/fsp/fsp_support.h>
-#include <asm/post.h>
-
-struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void)
-{
- /*
- * This function may be called before the a stack is established,
- * so special care must be taken. First, it cannot declare any local
- * variable using stack. Only register variable can be used here.
- * Secondly, some compiler version will add prolog or epilog code
- * for the C function. If so the function call may not work before
- * stack is ready.
- *
- * GCC 4.8.1 has been verified to be working for the following codes.
- */
- volatile register u8 *fsp asm("eax");
-
- /* Initalize the FSP base */
- fsp = (u8 *)CONFIG_FSP_ADDR;
-
- /* Check the FV signature, _FVH */
- if (((struct fv_header *)fsp)->sign == EFI_FVH_SIGNATURE) {
- /* Go to the end of the FV header and align the address */
- fsp += ((struct fv_header *)fsp)->ext_hdr_off;
- fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size;
- fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8);
- } else {
- fsp = 0;
- }
-
- /* Check the FFS GUID */
- if (fsp &&
- ((struct ffs_file_header *)fsp)->name.b[0] == FSP_GUID_BYTE0 &&
- ((struct ffs_file_header *)fsp)->name.b[1] == FSP_GUID_BYTE1 &&
- ((struct ffs_file_header *)fsp)->name.b[2] == FSP_GUID_BYTE2 &&
- ((struct ffs_file_header *)fsp)->name.b[3] == FSP_GUID_BYTE3 &&
- ((struct ffs_file_header *)fsp)->name.b[4] == FSP_GUID_BYTE4 &&
- ((struct ffs_file_header *)fsp)->name.b[5] == FSP_GUID_BYTE5 &&
- ((struct ffs_file_header *)fsp)->name.b[6] == FSP_GUID_BYTE6 &&
- ((struct ffs_file_header *)fsp)->name.b[7] == FSP_GUID_BYTE7 &&
- ((struct ffs_file_header *)fsp)->name.b[8] == FSP_GUID_BYTE8 &&
- ((struct ffs_file_header *)fsp)->name.b[9] == FSP_GUID_BYTE9 &&
- ((struct ffs_file_header *)fsp)->name.b[10] == FSP_GUID_BYTE10 &&
- ((struct ffs_file_header *)fsp)->name.b[11] == FSP_GUID_BYTE11 &&
- ((struct ffs_file_header *)fsp)->name.b[12] == FSP_GUID_BYTE12 &&
- ((struct ffs_file_header *)fsp)->name.b[13] == FSP_GUID_BYTE13 &&
- ((struct ffs_file_header *)fsp)->name.b[14] == FSP_GUID_BYTE14 &&
- ((struct ffs_file_header *)fsp)->name.b[15] == FSP_GUID_BYTE15) {
- /* Add the FFS header size to find the raw section header */
- fsp += sizeof(struct ffs_file_header);
- } else {
- fsp = 0;
- }
-
- if (fsp &&
- ((struct raw_section *)fsp)->type == EFI_SECTION_RAW) {
- /* Add the raw section header size to find the FSP header */
- fsp += sizeof(struct raw_section);
- } else {
- fsp = 0;
- }
-
- return (struct fsp_header *)fsp;
-}
-
-void fsp_continue(u32 status, void *hob_list)
-{
- post_code(POST_MRC);
-
- assert(status == 0);
-
- /* The boot loader main function entry */
- fsp_init_done(hob_list);
-}
-
-void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
-{
- struct fsp_config_data config_data;
- fsp_init_f init;
- struct fsp_init_params params;
- struct fspinit_rtbuf rt_buf;
- struct fsp_header *fsp_hdr;
- struct fsp_init_params *params_ptr;
-#ifdef CONFIG_FSP_USE_UPD
- struct vpd_region *fsp_vpd;
- struct upd_region *fsp_upd;
-#endif
-
- fsp_hdr = find_fsp_header();
- if (fsp_hdr == NULL) {
- /* No valid FSP info header was found */
- panic("Invalid FSP header");
- }
-
- config_data.common.fsp_hdr = fsp_hdr;
- config_data.common.stack_top = stack_top;
- config_data.common.boot_mode = boot_mode;
-
-#ifdef CONFIG_FSP_USE_UPD
- /* Get VPD region start */
- fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
- fsp_hdr->cfg_region_off);
-
- /* Verify the VPD data region is valid */
- assert(fsp_vpd->sign == VPD_IMAGE_ID);
-
- fsp_upd = &config_data.fsp_upd;
-
- /* Copy default data from Flash */
- memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
- sizeof(struct upd_region));
-
- /* Verify the UPD data region is valid */
- assert(fsp_upd->terminator == UPD_TERMINATOR);
-#endif
-
- memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
-
- /* Override any configuration if required */
- update_fsp_configs(&config_data, &rt_buf);
-
- memset(¶ms, 0, sizeof(struct fsp_init_params));
- params.nvs_buf = nvs_buf;
- params.rt_buf = (struct fspinit_rtbuf *)&rt_buf;
- params.continuation = (fsp_continuation_f)asm_continuation;
-
- init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init);
- params_ptr = ¶ms;
-
- post_code(POST_PRE_MRC);
-
- /* Load GDT for FSP */
- setup_fsp_gdt();
-
- /*
- * Use ASM code to ensure the register value in EAX & EDX
- * will be passed into fsp_continue
- */
- asm volatile (
- "pushl %0;"
- "call *%%eax;"
- ".global asm_continuation;"
- "asm_continuation:;"
- "movl 4(%%esp), %%eax;" /* status */
- "movl 8(%%esp), %%edx;" /* hob_list */
- "jmp fsp_continue;"
- : : "m"(params_ptr), "a"(init)
- );
-
- /*
- * Should never get here.
- * Control will continue from fsp_continue.
- * This line below is to prevent the compiler from optimizing
- * structure intialization.
- *
- * DO NOT REMOVE!
- */
- init(¶ms);
-}
-
-u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase)
-{
- fsp_notify_f notify;
- struct fsp_notify_params params;
- struct fsp_notify_params *params_ptr;
- u32 status;
-
- if (!fsp_hdr)
- fsp_hdr = (struct fsp_header *)find_fsp_header();
-
- if (fsp_hdr == NULL) {
- /* No valid FSP info header */
- panic("Invalid FSP header");
- }
-
- notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify);
- params.phase = phase;
- params_ptr = ¶ms;
-
- /*
- * Use ASM code to ensure correct parameter is on the stack for
- * FspNotify as U-Boot is using different ABI from FSP
- */
- asm volatile (
- "pushl %1;" /* push notify phase */
- "call *%%eax;" /* call FspNotify */
- "addl $4, %%esp;" /* clean up the stack */
- : "=a"(status) : "m"(params_ptr), "a"(notify), "m"(*params_ptr)
- );
-
- return status;
-}
-
-u32 fsp_get_usable_lowmem_top(const void *hob_list)
-{
- const struct hob_header *hdr;
- struct hob_res_desc *res_desc;
- phys_addr_t phys_start;
- u32 top;
-#ifdef CONFIG_FSP_BROKEN_HOB
- struct hob_mem_alloc *res_mem;
- phys_addr_t mem_base = 0;
-#endif
-
- /* Get the HOB list for processing */
- hdr = hob_list;
-
- /* * Collect memory ranges */
- top = FSP_LOWMEM_BASE;
- while (!end_of_hob(hdr)) {
- if (hdr->type == HOB_TYPE_RES_DESC) {
- res_desc = (struct hob_res_desc *)hdr;
- if (res_desc->type == RES_SYS_MEM) {
- phys_start = res_desc->phys_start;
- /* Need memory above 1MB to be collected here */
- if (phys_start >= FSP_LOWMEM_BASE &&
- phys_start < (phys_addr_t)FSP_HIGHMEM_BASE)
- top += (u32)(res_desc->len);
- }
- }
-
-#ifdef CONFIG_FSP_BROKEN_HOB
- /*
- * Find out the lowest memory base address allocated by FSP
- * for the boot service data
- */
- if (hdr->type == HOB_TYPE_MEM_ALLOC) {
- res_mem = (struct hob_mem_alloc *)hdr;
- if (!mem_base)
- mem_base = res_mem->mem_base;
- if (res_mem->mem_base < mem_base)
- mem_base = res_mem->mem_base;
- }
-#endif
-
- hdr = get_next_hob(hdr);
- }
-
-#ifdef CONFIG_FSP_BROKEN_HOB
- /*
- * Check whether the memory top address is below the FSP HOB list.
- * If not, use the lowest memory base address allocated by FSP as
- * the memory top address. This is to prevent U-Boot relocation
- * overwrites the important boot service data which is used by FSP,
- * otherwise the subsequent call to fsp_notify() will fail.
- */
- if (top > (u32)hob_list) {
- debug("Adjust memory top address due to a buggy FSP\n");
- top = (u32)mem_base;
- }
-#endif
-
- return top;
-}
-
-u64 fsp_get_usable_highmem_top(const void *hob_list)
-{
- const struct hob_header *hdr;
- struct hob_res_desc *res_desc;
- phys_addr_t phys_start;
- u64 top;
-
- /* Get the HOB list for processing */
- hdr = hob_list;
-
- /* Collect memory ranges */
- top = FSP_HIGHMEM_BASE;
- while (!end_of_hob(hdr)) {
- if (hdr->type == HOB_TYPE_RES_DESC) {
- res_desc = (struct hob_res_desc *)hdr;
- if (res_desc->type == RES_SYS_MEM) {
- phys_start = res_desc->phys_start;
- /* Need memory above 4GB to be collected here */
- if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE)
- top += (u32)(res_desc->len);
- }
- }
- hdr = get_next_hob(hdr);
- }
-
- return top;
-}
-
-u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
- const efi_guid_t *guid)
-{
- const struct hob_header *hdr;
- struct hob_res_desc *res_desc;
-
- /* Get the HOB list for processing */
- hdr = hob_list;
-
- /* Collect memory ranges */
- while (!end_of_hob(hdr)) {
- if (hdr->type == HOB_TYPE_RES_DESC) {
- res_desc = (struct hob_res_desc *)hdr;
- if (res_desc->type == RES_MEM_RESERVED) {
- if (!guidcmp(&res_desc->owner, guid)) {
- if (len)
- *len = (u32)(res_desc->len);
-
- return (u64)(res_desc->phys_start);
- }
- }
- }
- hdr = get_next_hob(hdr);
- }
-
- return 0;
-}
-
-u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len)
-{
- const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
- u64 length;
- u32 base;
-
- base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
- &length, &guid);
- if ((len != 0) && (base != 0))
- *len = (u32)length;
-
- return base;
-}
-
-u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len)
-{
- const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
- u64 length;
- u32 base;
-
- base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
- &length, &guid);
- if ((len != 0) && (base != 0))
- *len = (u32)length;
-
- return base;
-}
-
-void *fsp_get_nvs_data(const void *hob_list, u32 *len)
-{
- const efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
-
- return hob_get_guid_hob_data(hob_list, len, &guid);
-}
-
-void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len)
-{
- const efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
-
- return hob_get_guid_hob_data(hob_list, len, &guid);
-}
-
-void *fsp_get_graphics_info(const void *hob_list, u32 *len)
-{
- const efi_guid_t guid = FSP_GRAPHICS_INFO_HOB_GUID;
-
- return hob_get_guid_hob_data(hob_list, len, &guid);
-}
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Google, Inc
+
+obj-y += fsp_car.o
+obj-y += fsp_common.o
+obj-y += fsp_dram.o
+obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o
+obj-y += fsp_support.o
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <config.h>
+#include <asm/post.h>
+
+.globl car_init
+car_init:
+ /*
+ * Note: ebp holds the BIST value (built-in self test) so far, but ebp
+ * will be destroyed through the FSP call, thus we have to test the
+ * BIST value here before we call into FSP.
+ */
+ test %ebp, %ebp
+ jz car_init_start
+ post_code(POST_BIST_FAILURE)
+ jmp die
+
+car_init_start:
+ post_code(POST_CAR_START)
+ lea find_fsp_header_romstack, %esp
+ jmp find_fsp_header
+
+find_fsp_header_ret:
+ /* EAX points to FSP_INFO_HEADER */
+ mov %eax, %ebp
+
+ /* sanity test */
+ cmp $CONFIG_FSP_ADDR, %eax
+ jb die
+
+ /* calculate TempRamInitEntry address */
+ mov 0x30(%ebp), %eax
+ add 0x1c(%ebp), %eax
+
+ /* call FSP TempRamInitEntry to setup temporary stack */
+ lea temp_ram_init_romstack, %esp
+ jmp *%eax
+
+temp_ram_init_ret:
+ addl $4, %esp
+ cmp $0, %eax
+ jnz car_init_fail
+
+ post_code(POST_CAR_CPU_CACHE)
+
+ /*
+ * The FSP TempRamInit initializes the ecx and edx registers to
+ * point to a temporary but writable memory range (Cache-As-RAM).
+ * ecx: the start of this temporary memory range,
+ * edx: the end of this range.
+ */
+
+ /* stack grows down from top of CAR */
+ movl %edx, %esp
+ subl $4, %esp
+
+ xor %esi, %esi
+ jmp car_init_done
+
+.global fsp_init_done
+fsp_init_done:
+ /*
+ * We come here from fsp_continue() with eax pointing to the HOB list.
+ * Save eax to esi temporarily.
+ */
+ movl %eax, %esi
+
+car_init_done:
+ /*
+ * Re-initialize the ebp (BIST) to zero, as we already reach here
+ * which means we passed BIST testing before.
+ */
+ xorl %ebp, %ebp
+ jmp car_init_ret
+
+car_init_fail:
+ post_code(POST_CAR_FAILURE)
+
+die:
+ hlt
+ jmp die
+ hlt
+
+ /*
+ * The function call before CAR initialization is tricky. It cannot
+ * be called using the 'call' instruction but only the 'jmp' with
+ * the help of a handcrafted stack in the ROM. The stack needs to
+ * contain the function return address as well as the parameters.
+ */
+ .balign 4
+find_fsp_header_romstack:
+ .long find_fsp_header_ret
+
+ .balign 4
+temp_ram_init_romstack:
+ .long temp_ram_init_ret
+ .long temp_ram_init_params
+temp_ram_init_params:
+_dt_ucode_base_size:
+ /* These next two fields are filled in by binman */
+.globl ucode_base
+ucode_base: /* Declared in microcode.h */
+ .long 0 /* microcode base */
+.globl ucode_size
+ucode_size: /* Declared in microcode.h */
+ .long 0 /* microcode size */
+ .long CONFIG_SYS_MONITOR_BASE /* code region base */
+ .long CONFIG_SYS_MONITOR_LEN /* code region size */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <rtc.h>
+#include <asm/acpi_s3.h>
+#include <asm/cmos_layout.h>
+#include <asm/early_cmos.h>
+#include <asm/io.h>
+#include <asm/mrccache.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+#include <asm/fsp1/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkcpu(void)
+{
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ post_code(POST_CPU_INFO);
+ return default_print_cpuinfo();
+}
+
+int fsp_init_phase_pci(void)
+{
+ u32 status;
+
+ /* call into FspNotify */
+ debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
+ status = fsp_notify(NULL, INIT_PHASE_PCI);
+ if (status)
+ debug("fail, error code %x\n", status);
+ else
+ debug("OK\n");
+
+ return status ? -EPERM : 0;
+}
+
+void board_final_cleanup(void)
+{
+ u32 status;
+
+ /* call into FspNotify */
+ debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
+ status = fsp_notify(NULL, INIT_PHASE_BOOT);
+ if (status)
+ debug("fail, error code %x\n", status);
+ else
+ debug("OK\n");
+
+ return;
+}
+
+static __maybe_unused void *fsp_prepare_mrc_cache(void)
+{
+ struct mrc_data_container *cache;
+ struct mrc_region entry;
+ int ret;
+
+ ret = mrccache_get_region(NULL, &entry);
+ if (ret)
+ return NULL;
+
+ cache = mrccache_find_current(&entry);
+ if (!cache)
+ return NULL;
+
+ debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
+ cache->data, cache->data_size, cache->checksum);
+
+ return cache->data;
+}
+
+#ifdef CONFIG_HAVE_ACPI_RESUME
+int fsp_save_s3_stack(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (gd->arch.prev_sleep_state == ACPI_S3)
+ return 0;
+
+ ret = uclass_get_device(UCLASS_RTC, 0, &dev);
+ if (ret) {
+ debug("Cannot find RTC: err=%d\n", ret);
+ return -ENODEV;
+ }
+
+ /* Save the stack address to CMOS */
+ ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
+ if (ret) {
+ debug("Save stack address to CMOS: err=%d\n", ret);
+ return -EIO;
+ }
+
+ return 0;
+}
+#endif
+
+int arch_fsp_init(void)
+{
+ void *nvs;
+ int stack = CONFIG_FSP_TEMP_RAM_ADDR;
+ int boot_mode = BOOT_FULL_CONFIG;
+#ifdef CONFIG_HAVE_ACPI_RESUME
+ int prev_sleep_state = chipset_prev_sleep_state();
+ gd->arch.prev_sleep_state = prev_sleep_state;
+#endif
+
+ if (!gd->arch.hob_list) {
+#ifdef CONFIG_ENABLE_MRC_CACHE
+ nvs = fsp_prepare_mrc_cache();
+#else
+ nvs = NULL;
+#endif
+
+#ifdef CONFIG_HAVE_ACPI_RESUME
+ if (prev_sleep_state == ACPI_S3) {
+ if (nvs == NULL) {
+ /* If waking from S3 and no cache then */
+ debug("No MRC cache found in S3 resume path\n");
+ post_code(POST_RESUME_FAILURE);
+ /* Clear Sleep Type */
+ chipset_clear_sleep_state();
+ /* Reboot */
+ debug("Rebooting..\n");
+ outb(SYS_RST | RST_CPU, IO_PORT_RESET);
+ /* Should not reach here.. */
+ panic("Reboot System");
+ }
+
+ /*
+ * DM is not available yet at this point, hence call
+ * CMOS access library which does not depend on DM.
+ */
+ stack = cmos_read32(CMOS_FSP_STACK_ADDR);
+ boot_mode = BOOT_ON_S3_RESUME;
+ }
+#endif
+ /*
+ * The first time we enter here, call fsp_init().
+ * Note the execution does not return to this function,
+ * instead it jumps to fsp_continue().
+ */
+ fsp_init(stack, boot_mode, nvs);
+ } else {
+ /*
+ * The second time we enter here, adjust the size of malloc()
+ * pool before relocation. Given gd->malloc_base was adjusted
+ * after the call to board_init_f_init_reserve() in arch/x86/
+ * cpu/start.S, we should fix up gd->malloc_limit here.
+ */
+ gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN;
+ }
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/fsp1/fsp_support.h>
+#include <asm/e820.h>
+#include <asm/mrccache.h>
+#include <asm/post.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ phys_size_t ram_size = 0;
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
+
+ hdr = gd->arch.hob_list;
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ if (res_desc->type == RES_SYS_MEM ||
+ res_desc->type == RES_MEM_RESERVED) {
+ ram_size += res_desc->len;
+ }
+ }
+ hdr = get_next_hob(hdr);
+ }
+
+ gd->ram_size = ram_size;
+ post_code(POST_DRAM);
+
+#ifdef CONFIG_ENABLE_MRC_CACHE
+ gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list,
+ &gd->arch.mrc_output_len);
+#endif
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+/*
+ * This function looks for the highest region of memory lower than 4GB which
+ * has enough space for U-Boot where U-Boot is aligned on a page boundary.
+ * It overrides the default implementation found elsewhere which simply
+ * picks the end of ram, wherever that may be. The location of the stack,
+ * the relocation address, and how far U-Boot is moved by relocation are
+ * set in the global data structure.
+ */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return fsp_get_usable_lowmem_top(gd->arch.hob_list);
+}
+
+unsigned int install_e820_map(unsigned int max_entries,
+ struct e820_entry *entries)
+{
+ unsigned int num_entries = 0;
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
+
+ hdr = gd->arch.hob_list;
+
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ entries[num_entries].addr = res_desc->phys_start;
+ entries[num_entries].size = res_desc->len;
+
+ if (res_desc->type == RES_SYS_MEM)
+ entries[num_entries].type = E820_RAM;
+ else if (res_desc->type == RES_MEM_RESERVED)
+ entries[num_entries].type = E820_RESERVED;
+
+ num_entries++;
+ }
+ hdr = get_next_hob(hdr);
+ }
+
+ /* Mark PCIe ECAM address range as reserved */
+ entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
+ entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
+ entries[num_entries].type = E820_RESERVED;
+ num_entries++;
+
+#ifdef CONFIG_HAVE_ACPI_RESUME
+ /*
+ * Everything between U-Boot's stack and ram top needs to be
+ * reserved in order for ACPI S3 resume to work.
+ */
+ entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
+ entries[num_entries].size = gd->ram_top - gd->start_addr_sp + \
+ CONFIG_STACK_SIZE;
+ entries[num_entries].type = E820_RESERVED;
+ num_entries++;
+#endif
+
+ return num_entries;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <vbe.h>
+#include <video.h>
+#include <asm/fsp1/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pixel {
+ u8 pos;
+ u8 size;
+};
+
+static const struct fsp_framebuffer {
+ struct pixel red;
+ struct pixel green;
+ struct pixel blue;
+ struct pixel rsvd;
+} fsp_framebuffer_format_map[] = {
+ [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
+ [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
+};
+
+static int save_vesa_mode(struct vesa_mode_info *vesa)
+{
+ const struct hob_graphics_info *ginfo;
+ const struct fsp_framebuffer *fbinfo;
+
+ ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
+
+ /*
+ * If there is no graphics info structure, bail out and keep
+ * running on the serial console.
+ *
+ * Note: on some platforms (eg: Braswell), the FSP will not produce
+ * the graphics info HOB unless you plug some cables to the display
+ * interface (eg: HDMI) on the board.
+ */
+ if (!ginfo) {
+ debug("FSP graphics hand-off block not found\n");
+ return -ENXIO;
+ }
+
+ vesa->x_resolution = ginfo->width;
+ vesa->y_resolution = ginfo->height;
+ vesa->bits_per_pixel = 32;
+ vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
+ vesa->phys_base_ptr = ginfo->fb_base;
+
+ if (ginfo->pixel_format >= pixel_bitmask) {
+ debug("FSP set unknown framebuffer format: %d\n",
+ ginfo->pixel_format);
+ return -EINVAL;
+ }
+ fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format];
+ vesa->red_mask_size = fbinfo->red.size;
+ vesa->red_mask_pos = fbinfo->red.pos;
+ vesa->green_mask_size = fbinfo->green.size;
+ vesa->green_mask_pos = fbinfo->green.pos;
+ vesa->blue_mask_size = fbinfo->blue.size;
+ vesa->blue_mask_pos = fbinfo->blue.pos;
+ vesa->reserved_mask_size = fbinfo->rsvd.size;
+ vesa->reserved_mask_pos = fbinfo->rsvd.pos;
+
+ return 0;
+}
+
+static int fsp_video_probe(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct vesa_mode_info *vesa = &mode_info.vesa;
+ int ret;
+
+ printf("Video: ");
+
+ /* Initialize vesa_mode_info structure */
+ ret = save_vesa_mode(vesa);
+ if (ret)
+ goto err;
+
+ /*
+ * The framebuffer base address in the FSP graphics info HOB reflects
+ * the value assigned by the FSP. After PCI enumeration the framebuffer
+ * base address may be relocated. Let's get the updated one from device.
+ *
+ * For IGD, it seems to be always on BAR2.
+ */
+ vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
+
+ ret = vbe_setup_video_priv(vesa, uc_priv, plat);
+ if (ret)
+ goto err;
+
+ printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
+ vesa->bits_per_pixel);
+
+ return 0;
+
+err:
+ printf("No video mode configured in FSP!\n");
+ return ret;
+}
+
+static const struct udevice_id fsp_video_ids[] = {
+ { .compatible = "fsp-fb" },
+ { }
+};
+
+U_BOOT_DRIVER(fsp_video) = {
+ .name = "fsp_video",
+ .id = UCLASS_VIDEO,
+ .of_match = fsp_video_ids,
+ .probe = fsp_video_probe,
+};
+
+static struct pci_device_id fsp_video_supported[] = {
+ { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) },
+ { },
+};
+
+U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported);
--- /dev/null
+// SPDX-License-Identifier: Intel
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/fsp1/fsp_support.h>
+#include <asm/post.h>
+
+struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void)
+{
+ /*
+ * This function may be called before the a stack is established,
+ * so special care must be taken. First, it cannot declare any local
+ * variable using stack. Only register variable can be used here.
+ * Secondly, some compiler version will add prolog or epilog code
+ * for the C function. If so the function call may not work before
+ * stack is ready.
+ *
+ * GCC 4.8.1 has been verified to be working for the following codes.
+ */
+ volatile register u8 *fsp asm("eax");
+
+ /* Initalize the FSP base */
+ fsp = (u8 *)CONFIG_FSP_ADDR;
+
+ /* Check the FV signature, _FVH */
+ if (((struct fv_header *)fsp)->sign == EFI_FVH_SIGNATURE) {
+ /* Go to the end of the FV header and align the address */
+ fsp += ((struct fv_header *)fsp)->ext_hdr_off;
+ fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size;
+ fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8);
+ } else {
+ fsp = 0;
+ }
+
+ /* Check the FFS GUID */
+ if (fsp &&
+ ((struct ffs_file_header *)fsp)->name.b[0] == FSP_GUID_BYTE0 &&
+ ((struct ffs_file_header *)fsp)->name.b[1] == FSP_GUID_BYTE1 &&
+ ((struct ffs_file_header *)fsp)->name.b[2] == FSP_GUID_BYTE2 &&
+ ((struct ffs_file_header *)fsp)->name.b[3] == FSP_GUID_BYTE3 &&
+ ((struct ffs_file_header *)fsp)->name.b[4] == FSP_GUID_BYTE4 &&
+ ((struct ffs_file_header *)fsp)->name.b[5] == FSP_GUID_BYTE5 &&
+ ((struct ffs_file_header *)fsp)->name.b[6] == FSP_GUID_BYTE6 &&
+ ((struct ffs_file_header *)fsp)->name.b[7] == FSP_GUID_BYTE7 &&
+ ((struct ffs_file_header *)fsp)->name.b[8] == FSP_GUID_BYTE8 &&
+ ((struct ffs_file_header *)fsp)->name.b[9] == FSP_GUID_BYTE9 &&
+ ((struct ffs_file_header *)fsp)->name.b[10] == FSP_GUID_BYTE10 &&
+ ((struct ffs_file_header *)fsp)->name.b[11] == FSP_GUID_BYTE11 &&
+ ((struct ffs_file_header *)fsp)->name.b[12] == FSP_GUID_BYTE12 &&
+ ((struct ffs_file_header *)fsp)->name.b[13] == FSP_GUID_BYTE13 &&
+ ((struct ffs_file_header *)fsp)->name.b[14] == FSP_GUID_BYTE14 &&
+ ((struct ffs_file_header *)fsp)->name.b[15] == FSP_GUID_BYTE15) {
+ /* Add the FFS header size to find the raw section header */
+ fsp += sizeof(struct ffs_file_header);
+ } else {
+ fsp = 0;
+ }
+
+ if (fsp &&
+ ((struct raw_section *)fsp)->type == EFI_SECTION_RAW) {
+ /* Add the raw section header size to find the FSP header */
+ fsp += sizeof(struct raw_section);
+ } else {
+ fsp = 0;
+ }
+
+ return (struct fsp_header *)fsp;
+}
+
+void fsp_continue(u32 status, void *hob_list)
+{
+ post_code(POST_MRC);
+
+ assert(status == 0);
+
+ /* The boot loader main function entry */
+ fsp_init_done(hob_list);
+}
+
+void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
+{
+ struct fsp_config_data config_data;
+ fsp_init_f init;
+ struct fsp_init_params params;
+ struct fspinit_rtbuf rt_buf;
+ struct fsp_header *fsp_hdr;
+ struct fsp_init_params *params_ptr;
+#ifdef CONFIG_FSP_USE_UPD
+ struct vpd_region *fsp_vpd;
+ struct upd_region *fsp_upd;
+#endif
+
+ fsp_hdr = find_fsp_header();
+ if (fsp_hdr == NULL) {
+ /* No valid FSP info header was found */
+ panic("Invalid FSP header");
+ }
+
+ config_data.common.fsp_hdr = fsp_hdr;
+ config_data.common.stack_top = stack_top;
+ config_data.common.boot_mode = boot_mode;
+
+#ifdef CONFIG_FSP_USE_UPD
+ /* Get VPD region start */
+ fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
+ fsp_hdr->cfg_region_off);
+
+ /* Verify the VPD data region is valid */
+ assert(fsp_vpd->sign == VPD_IMAGE_ID);
+
+ fsp_upd = &config_data.fsp_upd;
+
+ /* Copy default data from Flash */
+ memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
+ sizeof(struct upd_region));
+
+ /* Verify the UPD data region is valid */
+ assert(fsp_upd->terminator == UPD_TERMINATOR);
+#endif
+
+ memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
+
+ /* Override any configuration if required */
+ update_fsp_configs(&config_data, &rt_buf);
+
+ memset(¶ms, 0, sizeof(struct fsp_init_params));
+ params.nvs_buf = nvs_buf;
+ params.rt_buf = (struct fspinit_rtbuf *)&rt_buf;
+ params.continuation = (fsp_continuation_f)asm_continuation;
+
+ init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init);
+ params_ptr = ¶ms;
+
+ post_code(POST_PRE_MRC);
+
+ /* Load GDT for FSP */
+ setup_fsp_gdt();
+
+ /*
+ * Use ASM code to ensure the register value in EAX & EDX
+ * will be passed into fsp_continue
+ */
+ asm volatile (
+ "pushl %0;"
+ "call *%%eax;"
+ ".global asm_continuation;"
+ "asm_continuation:;"
+ "movl 4(%%esp), %%eax;" /* status */
+ "movl 8(%%esp), %%edx;" /* hob_list */
+ "jmp fsp_continue;"
+ : : "m"(params_ptr), "a"(init)
+ );
+
+ /*
+ * Should never get here.
+ * Control will continue from fsp_continue.
+ * This line below is to prevent the compiler from optimizing
+ * structure intialization.
+ *
+ * DO NOT REMOVE!
+ */
+ init(¶ms);
+}
+
+u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase)
+{
+ fsp_notify_f notify;
+ struct fsp_notify_params params;
+ struct fsp_notify_params *params_ptr;
+ u32 status;
+
+ if (!fsp_hdr)
+ fsp_hdr = (struct fsp_header *)find_fsp_header();
+
+ if (fsp_hdr == NULL) {
+ /* No valid FSP info header */
+ panic("Invalid FSP header");
+ }
+
+ notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify);
+ params.phase = phase;
+ params_ptr = ¶ms;
+
+ /*
+ * Use ASM code to ensure correct parameter is on the stack for
+ * FspNotify as U-Boot is using different ABI from FSP
+ */
+ asm volatile (
+ "pushl %1;" /* push notify phase */
+ "call *%%eax;" /* call FspNotify */
+ "addl $4, %%esp;" /* clean up the stack */
+ : "=a"(status) : "m"(params_ptr), "a"(notify), "m"(*params_ptr)
+ );
+
+ return status;
+}
+
+u32 fsp_get_usable_lowmem_top(const void *hob_list)
+{
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
+ phys_addr_t phys_start;
+ u32 top;
+#ifdef CONFIG_FSP_BROKEN_HOB
+ struct hob_mem_alloc *res_mem;
+ phys_addr_t mem_base = 0;
+#endif
+
+ /* Get the HOB list for processing */
+ hdr = hob_list;
+
+ /* * Collect memory ranges */
+ top = FSP_LOWMEM_BASE;
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ if (res_desc->type == RES_SYS_MEM) {
+ phys_start = res_desc->phys_start;
+ /* Need memory above 1MB to be collected here */
+ if (phys_start >= FSP_LOWMEM_BASE &&
+ phys_start < (phys_addr_t)FSP_HIGHMEM_BASE)
+ top += (u32)(res_desc->len);
+ }
+ }
+
+#ifdef CONFIG_FSP_BROKEN_HOB
+ /*
+ * Find out the lowest memory base address allocated by FSP
+ * for the boot service data
+ */
+ if (hdr->type == HOB_TYPE_MEM_ALLOC) {
+ res_mem = (struct hob_mem_alloc *)hdr;
+ if (!mem_base)
+ mem_base = res_mem->mem_base;
+ if (res_mem->mem_base < mem_base)
+ mem_base = res_mem->mem_base;
+ }
+#endif
+
+ hdr = get_next_hob(hdr);
+ }
+
+#ifdef CONFIG_FSP_BROKEN_HOB
+ /*
+ * Check whether the memory top address is below the FSP HOB list.
+ * If not, use the lowest memory base address allocated by FSP as
+ * the memory top address. This is to prevent U-Boot relocation
+ * overwrites the important boot service data which is used by FSP,
+ * otherwise the subsequent call to fsp_notify() will fail.
+ */
+ if (top > (u32)hob_list) {
+ debug("Adjust memory top address due to a buggy FSP\n");
+ top = (u32)mem_base;
+ }
+#endif
+
+ return top;
+}
+
+u64 fsp_get_usable_highmem_top(const void *hob_list)
+{
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
+ phys_addr_t phys_start;
+ u64 top;
+
+ /* Get the HOB list for processing */
+ hdr = hob_list;
+
+ /* Collect memory ranges */
+ top = FSP_HIGHMEM_BASE;
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ if (res_desc->type == RES_SYS_MEM) {
+ phys_start = res_desc->phys_start;
+ /* Need memory above 4GB to be collected here */
+ if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE)
+ top += (u32)(res_desc->len);
+ }
+ }
+ hdr = get_next_hob(hdr);
+ }
+
+ return top;
+}
+
+u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
+ const efi_guid_t *guid)
+{
+ const struct hob_header *hdr;
+ struct hob_res_desc *res_desc;
+
+ /* Get the HOB list for processing */
+ hdr = hob_list;
+
+ /* Collect memory ranges */
+ while (!end_of_hob(hdr)) {
+ if (hdr->type == HOB_TYPE_RES_DESC) {
+ res_desc = (struct hob_res_desc *)hdr;
+ if (res_desc->type == RES_MEM_RESERVED) {
+ if (!guidcmp(&res_desc->owner, guid)) {
+ if (len)
+ *len = (u32)(res_desc->len);
+
+ return (u64)(res_desc->phys_start);
+ }
+ }
+ }
+ hdr = get_next_hob(hdr);
+ }
+
+ return 0;
+}
+
+u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len)
+{
+ const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
+ u64 length;
+ u32 base;
+
+ base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
+ &length, &guid);
+ if ((len != 0) && (base != 0))
+ *len = (u32)length;
+
+ return base;
+}
+
+u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len)
+{
+ const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
+ u64 length;
+ u32 base;
+
+ base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
+ &length, &guid);
+ if ((len != 0) && (base != 0))
+ *len = (u32)length;
+
+ return base;
+}
+
+void *fsp_get_nvs_data(const void *hob_list, u32 *len)
+{
+ const efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
+
+ return hob_get_guid_hob_data(hob_list, len, &guid);
+}
+
+void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len)
+{
+ const efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
+
+ return hob_get_guid_hob_data(hob_list, len, &guid);
+}
+
+void *fsp_get_graphics_info(const void *hob_list, u32 *len)
+{
+ const efi_guid_t guid = FSP_GRAPHICS_INFO_HOB_GUID;
+
+ return hob_get_guid_hob_data(hob_list, len, &guid);
+}
*/
#include <common.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
/* ALC262 Verb Table - 10EC0262 */
static const u32 verb_table_data13[] = {
#include <common.h>
#include <asm/arch/gpio.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
static const struct gpio_family gpio_family[] = {
GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0,
#include <common.h>
#include <command.h>
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
#include <dm/device-internal.h>
#include <dm/lists.h>
#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
-#include <asm/fsp/fsp_support.h>
+#include <asm/fsp1/fsp_support.h>
#endif
#include "pci_internal.h"
projects / oweals / u-boot.git / commitdiff